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38b2d076 | 1 | /* Target Definitions for R8C/M16C/M32C |
2f83c7d6 | 2 | Copyright (C) 2005, 2007 |
38b2d076 DD |
3 | Free Software Foundation, Inc. |
4 | Contributed by Red Hat. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 10 | by the Free Software Foundation; either version 3, or (at your |
38b2d076 DD |
11 | option) any later version. |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
38b2d076 DD |
21 | |
22 | #ifndef GCC_M32C_H | |
23 | #define GCC_M32C_H | |
24 | ||
25 | /* Controlling the Compilation Driver, `gcc'. */ | |
26 | ||
27 | #undef STARTFILE_SPEC | |
28 | #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s" | |
29 | ||
30 | /* There are four CPU series we support, but they basically break down | |
85f65093 KH |
31 | into two families - the R8C/M16C families, with 16-bit address |
32 | registers and one set of opcodes, and the M32CM/M32C group, with | |
33 | 24-bit address registers and a different set of opcodes. The | |
38b2d076 DD |
34 | assembler doesn't care except for which opcode set is needed; the |
35 | big difference is in the memory maps, which we cover in | |
36 | LIB_SPEC. */ | |
37 | ||
38 | #undef ASM_SPEC | |
39 | #define ASM_SPEC "\ | |
40 | %{mcpu=r8c:--m16c} \ | |
41 | %{mcpu=m16c:--m16c} \ | |
42 | %{mcpu=m32cm:--m32c} \ | |
43 | %{mcpu=m32c:--m32c} " | |
44 | ||
45 | /* The default is R8C hardware. We support a simulator, which has its | |
46 | own libgloss and link map, plus one default link map for each chip | |
47 | family. Most of the logic here is making sure we do the right | |
48 | thing when no CPU is specified, which defaults to R8C. */ | |
49 | #undef LIB_SPEC | |
50 | #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \ | |
51 | %{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \ | |
52 | %{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \ | |
53 | %{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \ | |
54 | %{mcpu=m32cm:-Tm32cm.ld} \ | |
55 | %{mcpu=m32c:-Tm32c.ld} \ | |
56 | %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \ | |
57 | " | |
58 | ||
59 | /* Run-time Target Specification */ | |
60 | ||
61 | /* Nothing unusual here. */ | |
62 | #define TARGET_CPU_CPP_BUILTINS() \ | |
63 | { \ | |
64 | builtin_assert ("cpu=m32c"); \ | |
65 | builtin_assert ("machine=m32c"); \ | |
66 | builtin_define ("__m32c__=1"); \ | |
67 | if (TARGET_R8C) \ | |
68 | builtin_define ("__r8c_cpu__=1"); \ | |
69 | if (TARGET_M16C) \ | |
70 | builtin_define ("__m16c_cpu__=1"); \ | |
71 | if (TARGET_M32CM) \ | |
72 | builtin_define ("__m32cm_cpu__=1"); \ | |
73 | if (TARGET_M32C) \ | |
74 | builtin_define ("__m32c_cpu__=1"); \ | |
75 | } | |
76 | ||
77 | /* The pragma handlers need to know if we've started processing | |
78 | functions yet, as the memregs pragma should only be given at the | |
79 | beginning of the file. This variable starts off TRUE and later | |
80 | becomes FALSE. */ | |
81 | extern int ok_to_change_target_memregs; | |
82 | extern int target_memregs; | |
83 | ||
84 | /* TARGET_CPU is a multi-way option set in m32c.opt. While we could | |
85 | use enums or defines for this, this and m32c.opt are the only | |
86 | places that know (or care) what values are being used. */ | |
87 | #define TARGET_R8C (target_cpu == 'r') | |
88 | #define TARGET_M16C (target_cpu == '6') | |
89 | #define TARGET_M32CM (target_cpu == 'm') | |
90 | #define TARGET_M32C (target_cpu == '3') | |
91 | ||
92 | /* Address register sizes. Warning: these are used all over the place | |
93 | to select between the two CPU families in general. */ | |
94 | #define TARGET_A16 (TARGET_R8C || TARGET_M16C) | |
95 | #define TARGET_A24 (TARGET_M32CM || TARGET_M32C) | |
96 | ||
97 | #define TARGET_VERSION fprintf (stderr, " (m32c)"); | |
98 | ||
58ef0ffa | 99 | #define OVERRIDE_OPTIONS m32c_override_options () |
38b2d076 DD |
100 | |
101 | /* Defining data structures for per-function information */ | |
102 | ||
103 | typedef struct machine_function GTY (()) | |
104 | { | |
105 | /* How much we adjust the stack when returning from an exception | |
106 | handler. */ | |
107 | rtx eh_stack_adjust; | |
108 | ||
109 | /* TRUE if the current function is an interrupt handler. */ | |
110 | int is_interrupt; | |
111 | ||
112 | /* TRUE if the current function is a leaf function. Currently, this | |
113 | only affects saving $a0 in interrupt functions. */ | |
114 | int is_leaf; | |
115 | ||
116 | /* Bitmask that keeps track of which registers are used in an | |
117 | interrupt function, so we know which ones need to be saved and | |
118 | restored. */ | |
119 | int intr_pushm; | |
120 | /* Likewise, one element for each memreg that needs to be saved. */ | |
121 | char intr_pushmem[16]; | |
122 | ||
123 | /* TRUE if the current function can use a simple RTS to return, instead | |
124 | of the longer ENTER/EXIT pair. */ | |
125 | int use_rts; | |
126 | } | |
127 | machine_function; | |
128 | ||
129 | #define INIT_EXPANDERS m32c_init_expanders () | |
130 | ||
131 | /* Storage Layout */ | |
132 | ||
133 | #define BITS_BIG_ENDIAN 0 | |
134 | #define BYTES_BIG_ENDIAN 0 | |
135 | #define WORDS_BIG_ENDIAN 0 | |
136 | ||
137 | /* We can do QI, HI, and SI operations pretty much equally well, but | |
138 | GCC expects us to have a "native" format, so we pick the one that | |
139 | matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16 | |
140 | is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but | |
85f65093 | 141 | 24-bit pointers are stored in 32-bit words. */ |
38b2d076 DD |
142 | #define BITS_PER_UNIT 8 |
143 | #define UNITS_PER_WORD 2 | |
144 | #define POINTER_SIZE (TARGET_A16 ? 16 : 32) | |
145 | #define POINTERS_EXTEND_UNSIGNED 1 | |
146 | ||
147 | /* These match the alignment enforced by the two types of stack operations. */ | |
148 | #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16) | |
149 | #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16) | |
150 | ||
151 | /* We do this because we care more about space than about speed. For | |
85f65093 | 152 | the chips with 16-bit busses, we could set these to 16 if |
38b2d076 DD |
153 | desired. */ |
154 | #define FUNCTION_BOUNDARY 8 | |
155 | #define BIGGEST_ALIGNMENT 8 | |
156 | ||
157 | #define STRICT_ALIGNMENT 0 | |
158 | #define SLOW_BYTE_ACCESS 1 | |
159 | ||
160 | /* Layout of Source Language Data Types */ | |
161 | ||
162 | #define INT_TYPE_SIZE 16 | |
163 | #define SHORT_TYPE_SIZE 16 | |
164 | #define LONG_TYPE_SIZE 32 | |
165 | #define LONG_LONG_TYPE_SIZE 64 | |
166 | ||
167 | #define FLOAT_TYPE_SIZE 32 | |
168 | #define DOUBLE_TYPE_SIZE 64 | |
169 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
170 | ||
171 | #define DEFAULT_SIGNED_CHAR 1 | |
172 | ||
7e96ee36 DD |
173 | #undef PTRDIFF_TYPE |
174 | #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int") | |
175 | ||
38b2d076 DD |
176 | /* REGISTER USAGE */ |
177 | ||
178 | /* Register Basics */ | |
179 | ||
180 | /* Register layout: | |
181 | ||
85f65093 | 182 | [r0h][r0l] $r0 (16 bits, or two 8-bit halves) |
38b2d076 | 183 | [--------] $r2 (16 bits) |
85f65093 | 184 | [r1h][r1l] $r1 (16 bits, or two 8-bit halves) |
38b2d076 DD |
185 | [--------] $r3 (16 bits) |
186 | [---][--------] $a0 (might be 24 bits) | |
187 | [---][--------] $a1 (might be 24 bits) | |
188 | [---][--------] $sb (might be 24 bits) | |
189 | [---][--------] $fb (might be 24 bits) | |
190 | [---][--------] $sp (might be 24 bits) | |
191 | [-------------] $pc (20 or 24 bits) | |
192 | [---] $flg (CPU flags) | |
193 | [---][--------] $argp (virtual) | |
194 | [--------] $mem0 (all 16 bits) | |
195 | . . . | |
196 | [--------] $mem14 | |
197 | */ | |
198 | ||
199 | #define FIRST_PSEUDO_REGISTER 20 | |
200 | ||
201 | /* Note that these two tables are modified based on which CPU family | |
202 | you select; see m32c_conditional_register_usage for details. */ | |
203 | ||
204 | /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */ | |
205 | #define FIXED_REGISTERS { 0, 0, 0, 0, \ | |
206 | 0, 0, 1, 0, \ | |
207 | 1, 1, 0, 1, \ | |
208 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
209 | #define CALL_USED_REGISTERS { 1, 1, 1, 1, \ | |
210 | 1, 1, 1, 0, \ | |
211 | 1, 1, 1, 1, \ | |
212 | 1, 1, 1, 1, 1, 1, 1, 1 } | |
213 | ||
214 | #define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage (); | |
215 | ||
216 | /* The *_REGNO theme matches m32c.md and most register number | |
217 | arguments; the PC_REGNUM is the odd one out. */ | |
218 | #ifndef PC_REGNO | |
219 | #define PC_REGNO 9 | |
220 | #endif | |
221 | #define PC_REGNUM PC_REGNO | |
222 | ||
e9a8eb89 DD |
223 | /* Order of Allocation of Registers */ |
224 | ||
225 | #define REG_ALLOC_ORDER { \ | |
226 | 0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \ | |
227 | 12, 13, 14, 15, 16, 17, 18, /* mem0..mem7 */ \ | |
228 | 6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ } | |
229 | ||
38b2d076 DD |
230 | /* How Values Fit in Registers */ |
231 | ||
232 | #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M) | |
233 | #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M) | |
234 | #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2) | |
235 | #define AVOID_CCMODE_COPIES | |
236 | ||
237 | /* Register Classes */ | |
238 | ||
239 | /* Most registers are special purpose in some form or another, so this | |
240 | table is pretty big. Class names are used for constraints also; | |
241 | for example the HL_REGS class (HL below) is "Rhl" in the md files. | |
242 | See m32c_reg_class_from_constraint for the mapping. There's some | |
243 | duplication so that we can better isolate the reason for using | |
244 | constraints in the md files from the actual registers used; for | |
245 | example we may want to exclude a1a0 from SI_REGS in the future, | |
246 | without precluding their use as HImode registers. */ | |
247 | ||
248 | /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */ | |
249 | /* mmPAR */ | |
250 | #define REG_CLASS_CONTENTS \ | |
251 | { { 0x00000000 }, /* NO */\ | |
252 | { 0x00000100 }, /* SP - sp */\ | |
253 | { 0x00000080 }, /* FB - fb */\ | |
254 | { 0x00000040 }, /* SB - sb */\ | |
255 | { 0x000001c0 }, /* CR - sb fb sp */\ | |
256 | { 0x00000001 }, /* R0 - r0 */\ | |
257 | { 0x00000004 }, /* R1 - r1 */\ | |
258 | { 0x00000002 }, /* R2 - r2 */\ | |
259 | { 0x00000008 }, /* R3 - r3 */\ | |
260 | { 0x00000003 }, /* R02 - r0r2 */\ | |
261 | { 0x00000005 }, /* HL - r0 r1 */\ | |
262 | { 0x00000005 }, /* QI - r0 r1 */\ | |
263 | { 0x0000000a }, /* R23 - r2 r3 */\ | |
264 | { 0x0000000f }, /* R03 - r0r2 r1r3 */\ | |
265 | { 0x0000000f }, /* DI - r0r2r1r3 + mems */\ | |
07127a0a DD |
266 | { 0x00000010 }, /* A0 - a0 */\ |
267 | { 0x00000020 }, /* A1 - a1 */\ | |
38b2d076 DD |
268 | { 0x00000030 }, /* A - a0 a1 */\ |
269 | { 0x000000f0 }, /* AD - a0 a1 sb fp */\ | |
270 | { 0x000001f0 }, /* PS - a0 a1 sb fp sp */\ | |
07127a0a | 271 | { 0x0000000f }, /* SI - r0r2 r1r3 a0a1 */\ |
38b2d076 DD |
272 | { 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\ |
273 | { 0x0000003f }, /* RA - r0..r3 a0 a1 */\ | |
274 | { 0x0000007f }, /* GENERAL */\ | |
275 | { 0x00000400 }, /* FLG */\ | |
276 | { 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\ | |
277 | { 0x000ff000 }, /* MEM */\ | |
278 | { 0x000ff003 }, /* R02_A_MEM */\ | |
279 | { 0x000ff005 }, /* A_HL_MEM */\ | |
280 | { 0x000ff00c }, /* R1_R3_A_MEM */\ | |
281 | { 0x000ff00f }, /* R03_MEM */\ | |
282 | { 0x000ff03f }, /* A_HI_MEM */\ | |
283 | { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\ | |
284 | { 0x000ff1ff }, /* ALL */\ | |
285 | } | |
286 | ||
287 | enum reg_class | |
288 | { | |
289 | NO_REGS, | |
290 | SP_REGS, | |
291 | FB_REGS, | |
292 | SB_REGS, | |
293 | CR_REGS, | |
294 | R0_REGS, | |
295 | R1_REGS, | |
296 | R2_REGS, | |
297 | R3_REGS, | |
298 | R02_REGS, | |
299 | HL_REGS, | |
300 | QI_REGS, | |
301 | R23_REGS, | |
302 | R03_REGS, | |
303 | DI_REGS, | |
07127a0a DD |
304 | A0_REGS, |
305 | A1_REGS, | |
38b2d076 DD |
306 | A_REGS, |
307 | AD_REGS, | |
308 | PS_REGS, | |
309 | SI_REGS, | |
310 | HI_REGS, | |
311 | RA_REGS, | |
312 | GENERAL_REGS, | |
313 | FLG_REGS, | |
314 | HC_REGS, | |
315 | MEM_REGS, | |
316 | R02_A_MEM_REGS, | |
317 | A_HL_MEM_REGS, | |
318 | R1_R3_A_MEM_REGS, | |
319 | R03_MEM_REGS, | |
320 | A_HI_MEM_REGS, | |
321 | A_AD_CR_MEM_SI_REGS, | |
322 | ALL_REGS, | |
323 | LIM_REG_CLASSES | |
324 | }; | |
325 | ||
326 | #define N_REG_CLASSES LIM_REG_CLASSES | |
327 | ||
328 | #define REG_CLASS_NAMES {\ | |
329 | "NO_REGS", \ | |
330 | "SP_REGS", \ | |
331 | "FB_REGS", \ | |
332 | "SB_REGS", \ | |
333 | "CR_REGS", \ | |
334 | "R0_REGS", \ | |
335 | "R1_REGS", \ | |
336 | "R2_REGS", \ | |
337 | "R3_REGS", \ | |
338 | "R02_REGS", \ | |
339 | "HL_REGS", \ | |
340 | "QI_REGS", \ | |
341 | "R23_REGS", \ | |
342 | "R03_REGS", \ | |
343 | "DI_REGS", \ | |
07127a0a DD |
344 | "A0_REGS", \ |
345 | "A1_REGS", \ | |
38b2d076 DD |
346 | "A_REGS", \ |
347 | "AD_REGS", \ | |
348 | "PS_REGS", \ | |
349 | "SI_REGS", \ | |
350 | "HI_REGS", \ | |
351 | "RA_REGS", \ | |
352 | "GENERAL_REGS", \ | |
353 | "FLG_REGS", \ | |
354 | "HC_REGS", \ | |
355 | "MEM_REGS", \ | |
356 | "R02_A_MEM_REGS", \ | |
357 | "A_HL_MEM_REGS", \ | |
358 | "R1_R3_A_MEM_REGS", \ | |
359 | "R03_MEM_REGS", \ | |
360 | "A_HI_MEM_REGS", \ | |
361 | "A_AD_CR_MEM_SI_REGS", \ | |
362 | "ALL_REGS", \ | |
363 | } | |
364 | ||
365 | #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R) | |
366 | ||
367 | /* We support simple displacements off address registers, nothing else. */ | |
368 | #define BASE_REG_CLASS A_REGS | |
369 | #define INDEX_REG_CLASS NO_REGS | |
370 | ||
a4174ebf | 371 | /* We primarily use the new "long" constraint names, with the initial |
38b2d076 DD |
372 | letter classifying the constraint type and following letters |
373 | specifying which. The types are: | |
374 | ||
375 | I - integer values | |
376 | R - register classes | |
377 | S - memory references (M was used) | |
378 | A - addresses (currently unused) | |
379 | */ | |
380 | ||
381 | #define CONSTRAINT_LEN(CHAR,STR) \ | |
382 | ((CHAR) == 'I' ? 3 \ | |
383 | : (CHAR) == 'R' ? 3 \ | |
384 | : (CHAR) == 'S' ? 2 \ | |
385 | : (CHAR) == 'A' ? 2 \ | |
386 | : DEFAULT_CONSTRAINT_LEN(CHAR,STR)) | |
387 | #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \ | |
388 | m32c_reg_class_from_constraint (CHAR, STR) | |
389 | ||
390 | #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM) | |
391 | #define REGNO_OK_FOR_INDEX_P(NUM) 0 | |
392 | ||
393 | #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS) | |
394 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS) | |
395 | #define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS) | |
396 | ||
397 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X) | |
398 | ||
399 | #define SMALL_REGISTER_CLASSES 1 | |
400 | ||
401 | #define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C) | |
402 | ||
403 | #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M) | |
404 | ||
405 | #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C) | |
406 | ||
407 | #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \ | |
408 | m32c_const_ok_for_constraint_p (VALUE, C, STR) | |
409 | #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0 | |
410 | #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \ | |
411 | m32c_extra_constraint_p (VALUE, C, STR) | |
412 | #define EXTRA_MEMORY_CONSTRAINT(C,STR) \ | |
413 | m32c_extra_memory_constraint (C, STR) | |
414 | #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \ | |
415 | m32c_extra_address_constraint (C, STR) | |
416 | ||
417 | /* STACK AND CALLING */ | |
418 | ||
419 | /* Frame Layout */ | |
420 | ||
421 | /* Standard push/pop stack, no surprises here. */ | |
422 | ||
423 | #define STACK_GROWS_DOWNWARD 1 | |
424 | #define STACK_PUSH_CODE PRE_DEC | |
425 | #define FRAME_GROWS_DOWNWARD 1 | |
426 | ||
427 | #define STARTING_FRAME_OFFSET 0 | |
428 | #define FIRST_PARM_OFFSET(F) 0 | |
429 | ||
430 | #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT) | |
431 | ||
432 | #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx() | |
0f681872 | 433 | #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3) |
38b2d076 DD |
434 | |
435 | /* Exception Handling Support */ | |
436 | ||
437 | #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N) | |
438 | #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx () | |
439 | ||
440 | /* Registers That Address the Stack Frame */ | |
441 | ||
442 | #ifndef FP_REGNO | |
443 | #define FP_REGNO 7 | |
444 | #endif | |
445 | #ifndef SP_REGNO | |
446 | #define SP_REGNO 8 | |
447 | #endif | |
448 | #define AP_REGNO 11 | |
449 | ||
450 | #define STACK_POINTER_REGNUM SP_REGNO | |
451 | #define FRAME_POINTER_REGNUM FP_REGNO | |
452 | #define ARG_POINTER_REGNUM AP_REGNO | |
453 | ||
454 | /* The static chain must be pointer-capable. */ | |
455 | #define STATIC_CHAIN_REGNUM A0_REGNO | |
456 | ||
457 | #define DWARF_FRAME_REGISTERS 20 | |
458 | #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N) | |
459 | #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N) | |
460 | ||
461 | /* Eliminating Frame Pointer and Arg Pointer */ | |
462 | ||
463 | /* If the frame pointer isn't used, we detect it manually. But the | |
464 | stack pointer doesn't have as flexible addressing as the frame | |
465 | pointer, so we always assume we have it. */ | |
466 | #define FRAME_POINTER_REQUIRED 1 | |
467 | ||
468 | #define ELIMINABLE_REGS \ | |
469 | {{AP_REGNO, SP_REGNO}, \ | |
470 | {AP_REGNO, FB_REGNO}, \ | |
471 | {FB_REGNO, SP_REGNO}} | |
472 | ||
473 | #define CAN_ELIMINATE(FROM,TO) 1 | |
474 | #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \ | |
475 | (VAR) = m32c_initial_elimination_offset(FROM,TO) | |
476 | ||
477 | /* Passing Function Arguments on the Stack */ | |
478 | ||
479 | #define PUSH_ARGS 1 | |
480 | #define PUSH_ROUNDING(N) m32c_push_rounding (N) | |
481 | #define RETURN_POPS_ARGS(D,T,S) 0 | |
482 | #define CALL_POPS_ARGS(C) 0 | |
483 | ||
484 | /* Passing Arguments in Registers */ | |
485 | ||
486 | #define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \ | |
487 | m32c_function_arg (&(CA),MODE,TYPE,NAMED) | |
488 | ||
489 | typedef struct m32c_cumulative_args | |
490 | { | |
491 | /* For address of return value buffer (structures are returned by | |
492 | passing the address of a buffer as an invisible first argument. | |
493 | This identifies it). If set, the current parameter will be put | |
494 | on the stack, regardless of type. */ | |
495 | int force_mem; | |
496 | /* First parm is 1, parm 0 is hidden pointer for returning | |
497 | aggregates. */ | |
498 | int parm_num; | |
499 | } m32c_cumulative_args; | |
500 | ||
501 | #define CUMULATIVE_ARGS m32c_cumulative_args | |
502 | #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ | |
503 | m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) | |
504 | #define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \ | |
505 | m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED) | |
506 | #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16) | |
507 | #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r) | |
508 | ||
509 | /* How Scalar Function Values Are Returned */ | |
510 | ||
511 | #define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F) | |
512 | #define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE) | |
513 | ||
514 | #define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO) | |
515 | ||
516 | /* How Large Values Are Returned */ | |
517 | ||
518 | #define DEFAULT_PCC_STRUCT_RETURN 1 | |
519 | ||
520 | /* Function Entry and Exit */ | |
521 | ||
522 | #define EXIT_IGNORE_STACK 0 | |
523 | #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO) | |
524 | #define EH_USES(REGNO) 0 /* FIXME */ | |
525 | ||
526 | /* Generating Code for Profiling */ | |
527 | ||
528 | #define FUNCTION_PROFILER(FILE,LABELNO) | |
529 | ||
530 | /* Implementing the Varargs Macros */ | |
531 | ||
532 | /* Trampolines for Nested Functions */ | |
533 | ||
534 | #define TRAMPOLINE_SIZE m32c_trampoline_size () | |
dc019eb8 | 535 | #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment () |
38b2d076 DD |
536 | #define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc) |
537 | ||
538 | /* Addressing Modes */ | |
539 | ||
540 | #define HAVE_PRE_DECREMENT 1 | |
541 | #define HAVE_POST_INCREMENT 1 | |
542 | #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X) | |
543 | #define MAX_REGS_PER_ADDRESS 1 | |
544 | ||
545 | /* This is passed to the macros below, so that they can be implemented | |
546 | in m32c.c. */ | |
547 | #ifdef REG_OK_STRICT | |
548 | #define REG_OK_STRICT_V 1 | |
549 | #else | |
550 | #define REG_OK_STRICT_V 0 | |
551 | #endif | |
552 | ||
553 | #define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \ | |
554 | if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \ | |
555 | goto LABEL; | |
556 | ||
557 | #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V) | |
558 | #define REG_OK_FOR_INDEX_P(X) 0 | |
559 | ||
560 | /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */ | |
561 | ||
562 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
563 | if (m32c_legitimize_address(&(X),OLDX,MODE)) \ | |
564 | goto win; | |
565 | ||
566 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
567 | if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \ | |
568 | goto win; | |
569 | ||
b9a76028 | 570 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) |
38b2d076 DD |
571 | |
572 | #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X) | |
573 | ||
574 | /* Condition Code Status */ | |
575 | ||
576 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
577 | ||
578 | /* Describing Relative Costs of Operations */ | |
579 | ||
580 | #define REGISTER_MOVE_COST(MODE,FROM,TO) \ | |
581 | m32c_register_move_cost (MODE, FROM, TO) | |
582 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
583 | m32c_memory_move_cost (MODE, CLASS, IN) | |
584 | ||
585 | /* Dividing the Output into Sections (Texts, Data, ...) */ | |
586 | ||
587 | #define TEXT_SECTION_ASM_OP ".text" | |
588 | #define DATA_SECTION_ASM_OP ".data" | |
589 | #define BSS_SECTION_ASM_OP ".bss" | |
590 | ||
04aff2c0 DD |
591 | #define CTOR_LIST_BEGIN |
592 | #define CTOR_LIST_END | |
593 | #define DTOR_LIST_BEGIN | |
594 | #define DTOR_LIST_END | |
595 | #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array" | |
596 | #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array" | |
597 | #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array" | |
598 | #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array" | |
599 | ||
38b2d076 DD |
600 | /* The Overall Framework of an Assembler File */ |
601 | ||
602 | #define ASM_COMMENT_START ";" | |
603 | #define ASM_APP_ON "" | |
604 | #define ASM_APP_OFF "" | |
605 | ||
606 | /* Output and Generation of Labels */ | |
607 | ||
608 | #define GLOBAL_ASM_OP "\t.global\t" | |
609 | ||
610 | /* Output of Assembler Instructions */ | |
611 | ||
612 | #define REGISTER_NAMES { \ | |
613 | "r0", "r2", "r1", "r3", \ | |
614 | "a0", "a1", "sb", "fb", "sp", \ | |
615 | "pc", "flg", "argp", \ | |
616 | "mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \ | |
617 | } | |
618 | ||
619 | #define ADDITIONAL_REGISTER_NAMES { \ | |
620 | {"r0l", 0}, \ | |
621 | {"r1l", 2}, \ | |
622 | {"r0r2", 0}, \ | |
623 | {"r1r3", 2}, \ | |
624 | {"a0a1", 4}, \ | |
625 | {"r0r2r1r3", 0} } | |
626 | ||
627 | #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C) | |
628 | #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C) | |
629 | #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X) | |
630 | ||
631 | #undef USER_LABEL_PREFIX | |
632 | #define USER_LABEL_PREFIX "_" | |
633 | ||
634 | #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R) | |
635 | #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R) | |
636 | ||
637 | /* Output of Dispatch Tables */ | |
638 | ||
639 | #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \ | |
640 | fprintf (S, "\t.word L%d\n", V) | |
641 | ||
642 | /* Assembler Commands for Exception Regions */ | |
643 | ||
644 | #define DWARF_CIE_DATA_ALIGNMENT -1 | |
645 | ||
646 | /* Assembler Commands for Alignment */ | |
647 | ||
648 | #define ASM_OUTPUT_ALIGN(STREAM,POWER) \ | |
649 | fprintf (STREAM, "\t.p2align\t%d\n", POWER); | |
650 | ||
651 | /* Controlling Debugging Information Format */ | |
652 | ||
653 | #define DWARF2_ADDR_SIZE 4 | |
654 | ||
655 | /* Miscellaneous Parameters */ | |
656 | ||
657 | #define HAS_LONG_COND_BRANCH false | |
658 | #define HAS_LONG_UNCOND_BRANCH true | |
659 | #define CASE_VECTOR_MODE SImode | |
660 | #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND | |
661 | ||
662 | #define MOVE_MAX 4 | |
663 | #define TRULY_NOOP_TRUNCATION(op,ip) 1 | |
664 | ||
07127a0a DD |
665 | #define STORE_FLAG_VALUE 1 |
666 | ||
85f65093 | 667 | /* 16- or 24-bit pointers */ |
38b2d076 DD |
668 | #define Pmode (TARGET_A16 ? HImode : PSImode) |
669 | #define FUNCTION_MODE QImode | |
670 | ||
671 | #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas() | |
672 | ||
673 | #endif |