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1 | ;; Machine Descriptions for R8C/M16C/M32C |
2 | ;; Copyright (C) 2005 | |
3 | ;; Free Software Foundation, Inc. | |
4 | ;; Contributed by Red Hat. | |
5 | ;; | |
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify it | |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING. If not, write to the Free | |
20 | ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA | |
21 | ;; 02110-1301, USA. | |
22 | ||
23 | ;; Predicates | |
24 | ||
07127a0a DD |
25 | ; TRUE for any valid operand. We do this because general_operand |
26 | ; refuses to match volatile memory refs. | |
27 | ||
28 | (define_predicate "m32c_any_operand" | |
29 | (ior (match_operand 0 "general_operand") | |
f9b89438 DD |
30 | (match_operand 1 "memory_operand")) |
31 | { | |
32 | return ! m32c_illegal_subreg_p (op); | |
33 | } | |
34 | ) | |
07127a0a DD |
35 | |
36 | ; Likewise for nonimmediate_operand. | |
37 | ||
38 | (define_predicate "m32c_nonimmediate_operand" | |
39 | (ior (match_operand 0 "nonimmediate_operand") | |
40 | (match_operand 1 "memory_operand"))) | |
41 | ||
38b2d076 DD |
42 | ; TRUE if the operand is a pseudo-register. |
43 | (define_predicate "m32c_pseudo" | |
44 | (ior (and (match_code "reg") | |
45 | (match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER")) | |
46 | (and (match_code "subreg") | |
47 | (and (match_test "GET_CODE (XEXP (op, 0)) == REG") | |
48 | (match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER"))))) | |
49 | ||
50 | ||
51 | ; Returning true causes many predicates to NOT match. We allow | |
52 | ; subregs for type changing, but not for size changing. | |
53 | (define_predicate "m32c_wide_subreg" | |
54 | (and (match_code "subreg") | |
55 | (not (match_operand 0 "m32c_pseudo"))) | |
56 | { | |
57 | unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op)); | |
58 | unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0))); | |
59 | sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
60 | sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
61 | return sizeo != sizei; | |
62 | }) | |
63 | ||
64 | ; TRUE for r0 through r3, or a pseudo that reload could put in r0 | |
65 | ; through r3 (likewise for the next couple too) | |
66 | (define_predicate "r0123_operand" | |
67 | (ior (match_operand 0 "m32c_pseudo" "") | |
68 | (and (match_code "reg") | |
69 | (match_test "REGNO(op) <= R3_REGNO")))) | |
70 | ||
71 | ; TRUE for r0 | |
72 | (define_predicate "m32c_r0_operand" | |
73 | (ior (match_operand 0 "m32c_pseudo" "") | |
74 | (and (match_code "reg") | |
75 | (match_test "REGNO(op) == R0_REGNO")))) | |
76 | ||
77 | ; TRUE for r1 | |
78 | (define_predicate "m32c_r1_operand" | |
79 | (ior (match_operand 0 "m32c_pseudo" "") | |
80 | (and (match_code "reg") | |
81 | (match_test "REGNO(op) == R1_REGNO")))) | |
82 | ||
07127a0a DD |
83 | ; TRUE for HL_CLASS (r0 or r1) |
84 | (define_predicate "m32c_hl_operand" | |
85 | (ior (match_operand 0 "m32c_pseudo" "") | |
86 | (and (match_code "reg") | |
87 | (match_test "REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO")))) | |
88 | ||
89 | ||
38b2d076 DD |
90 | ; TRUE for r2 |
91 | (define_predicate "m32c_r2_operand" | |
92 | (ior (match_operand 0 "m32c_pseudo" "") | |
93 | (and (match_code "reg") | |
94 | (match_test "REGNO(op) == R2_REGNO")))) | |
95 | ||
07127a0a DD |
96 | ; TRUE for r3 |
97 | (define_predicate "m32c_r3_operand" | |
98 | (ior (match_operand 0 "m32c_pseudo" "") | |
99 | (and (match_code "reg") | |
100 | (match_test "REGNO(op) == R3_REGNO")))) | |
101 | ||
38b2d076 DD |
102 | ; TRUE for any general operand except r2. |
103 | (define_predicate "m32c_notr2_operand" | |
104 | (and (match_operand 0 "general_operand") | |
105 | (ior (not (match_code "reg")) | |
106 | (match_test "REGNO(op) != R2_REGNO")))) | |
107 | ||
108 | ; TRUE for the stack pointer. | |
109 | (define_predicate "m32c_sp_operand" | |
110 | (ior (match_operand 0 "m32c_pseudo" "") | |
111 | (and (match_code "reg") | |
112 | (match_test "REGNO(op) == SP_REGNO")))) | |
113 | ||
114 | ; TRUE for control registers. | |
115 | (define_predicate "cr_operand" | |
116 | (match_code "reg") | |
117 | "return (REGNO (op) >= SB_REGNO | |
118 | && REGNO (op) <= FLG_REGNO);") | |
119 | ||
120 | ; TRUE for $a0 or $a1. | |
121 | (define_predicate "a_operand" | |
07127a0a DD |
122 | (and (match_code "reg") |
123 | (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO"))) | |
124 | ||
125 | ; TRUE for $a0 or $a1 or a pseudo | |
126 | (define_predicate "ap_operand" | |
127 | (ior (match_operand 0 "m32c_pseudo" "") | |
128 | (and (match_code "reg") | |
129 | (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO")))) | |
38b2d076 DD |
130 | |
131 | ; TRUE for r0 through r3, or a0 or a1. | |
132 | (define_predicate "ra_operand" | |
133 | (and (and (match_operand 0 "register_operand" "") | |
134 | (not (match_operand 1 "cr_operand" ""))) | |
135 | (not (match_operand 2 "m32c_wide_subreg" "")))) | |
136 | ||
137 | ; Likewise, plus TRUE for memory references. | |
138 | (define_predicate "mra_operand" | |
139 | (and (and (match_operand 0 "nonimmediate_operand" "") | |
140 | (not (match_operand 1 "cr_operand" ""))) | |
141 | (not (match_operand 2 "m32c_wide_subreg" "")))) | |
142 | ||
143 | ; Likewise, plus TRUE for subregs. | |
144 | (define_predicate "mras_operand" | |
145 | (and (match_operand 0 "nonimmediate_operand" "") | |
146 | (not (match_operand 1 "cr_operand" "")))) | |
147 | ||
0166ff05 DD |
148 | ; As above, but no push/pop operations |
149 | (define_predicate "mra_nopp_operand" | |
150 | (match_operand 0 "mra_operand" "") | |
151 | { | |
152 | if (GET_CODE (op) == MEM | |
153 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
154 | || (GET_CODE (XEXP (op, 0)) == POST_INC))) | |
155 | return 0; | |
156 | return 1; | |
157 | }) | |
158 | ||
38b2d076 DD |
159 | ; TRUE for memory, r0..r3, a0..a1, or immediates. |
160 | (define_predicate "mrai_operand" | |
07127a0a | 161 | (and (and (match_operand 0 "m32c_any_operand" "") |
38b2d076 DD |
162 | (not (match_operand 1 "cr_operand" ""))) |
163 | (not (match_operand 2 "m32c_wide_subreg" "")))) | |
164 | ||
165 | ; Likewise, plus true for subregs. | |
166 | (define_predicate "mrasi_operand" | |
167 | (and (match_operand 0 "general_operand" "") | |
168 | (not (match_operand 1 "cr_operand" "")))) | |
169 | ||
170 | ; TRUE for r0..r3 or memory. | |
171 | (define_predicate "mr_operand" | |
172 | (and (match_operand 0 "mra_operand" "") | |
173 | (not (match_operand 1 "a_operand" "")))) | |
174 | ||
07127a0a DD |
175 | ; TRUE for a0..a1 or memory. |
176 | (define_predicate "ma_operand" | |
177 | (ior (match_operand 0 "a_operand" "") | |
178 | (match_operand 1 "memory_operand" ""))) | |
179 | ||
180 | ; TRUE for memory operands that are not indexed | |
181 | (define_predicate "memsym_operand" | |
182 | (and (match_operand 0 "memory_operand" "") | |
183 | (match_test "m32c_extra_constraint_p (op, 'S', \"Si\")"))) | |
184 | ||
185 | ; TRUE for memory operands with small integer addresses | |
186 | (define_predicate "memimmed_operand" | |
187 | (and (match_operand 0 "memory_operand" "") | |
188 | (match_test "m32c_extra_constraint_p (op, 'S', \"Sp\")"))) | |
189 | ||
190 | ; TRUE for r1h. This is complicated since r1h isn't a register GCC | |
38b2d076 DD |
191 | ; normally knows about. |
192 | (define_predicate "r1h_operand" | |
193 | (match_code "zero_extract") | |
194 | { | |
195 | rtx reg = XEXP (op, 0); | |
196 | rtx size = XEXP (op, 1); | |
197 | rtx pos = XEXP (op, 2); | |
198 | return (GET_CODE (reg) == REG | |
199 | && REGNO (reg) == R1_REGNO | |
200 | && GET_CODE (size) == CONST_INT | |
201 | && INTVAL (size) == 8 | |
202 | && GET_CODE (pos) == CONST_INT | |
203 | && INTVAL (pos) == 8); | |
204 | }) | |
205 | ||
206 | ; TRUE if we can shift by this amount. Constant shift counts have a | |
207 | ; limited range. | |
208 | (define_predicate "shiftcount_operand" | |
23fed240 | 209 | (ior (match_operand 0 "mra_operand" "") |
38b2d076 DD |
210 | (and (match_operand 2 "const_int_operand" "") |
211 | (match_test "-8 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 8")))) | |
23fed240 DD |
212 | (define_predicate "longshiftcount_operand" |
213 | (ior (match_operand 0 "mra_operand" "") | |
214 | (and (match_operand 2 "const_int_operand" "") | |
215 | (match_test "-32 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 32")))) | |
38b2d076 DD |
216 | |
217 | ; TRUE for r0..r3, a0..a1, or sp. | |
218 | (define_predicate "mra_or_sp_operand" | |
219 | (and (ior (match_operand 0 "mra_operand") | |
220 | (match_operand 1 "m32c_sp_operand")) | |
221 | (not (match_operand 2 "m32c_wide_subreg" "")))) | |
222 | ||
223 | ||
224 | ; TRUE for r2 or r3. | |
225 | (define_predicate "m32c_r2r3_operand" | |
226 | (ior (and (match_code "reg") | |
227 | (ior (match_test "REGNO(op) == R2_REGNO") | |
228 | (match_test "REGNO(op) == R3_REGNO"))) | |
229 | (and (match_code "subreg") | |
230 | (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)")))) | |
231 | ||
232 | ; Likewise, plus TRUE for a0..a1. | |
233 | (define_predicate "m32c_r2r3a_operand" | |
234 | (ior (match_operand 0 "m32c_r2r3_operand" "") | |
235 | (match_operand 0 "a_operand" ""))) | |
236 | ||
237 | ; These two are only for movqi - no subreg limit | |
238 | (define_predicate "mra_qi_operand" | |
07127a0a | 239 | (and (and (match_operand 0 "m32c_nonimmediate_operand" "") |
38b2d076 DD |
240 | (not (match_operand 1 "cr_operand" ""))) |
241 | (not (match_operand 1 "m32c_r2r3a_operand" "")))) | |
242 | ||
243 | (define_predicate "mrai_qi_operand" | |
07127a0a | 244 | (and (and (match_operand 0 "m32c_any_operand" "") |
38b2d076 DD |
245 | (not (match_operand 1 "cr_operand" ""))) |
246 | (not (match_operand 1 "m32c_r2r3a_operand" "")))) | |
247 | ||
07127a0a DD |
248 | (define_predicate "a_qi_operand" |
249 | (ior (match_operand 0 "m32c_pseudo" "") | |
250 | (match_operand 1 "a_operand" ""))) | |
251 | ||
38b2d076 DD |
252 | ; TRUE for comparisons we support. |
253 | (define_predicate "m32c_cmp_operator" | |
254 | (match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu")) | |
255 | ||
07127a0a DD |
256 | (define_predicate "m32c_eqne_operator" |
257 | (match_code "eq,ne")) | |
258 | ||
38b2d076 DD |
259 | ; TRUE for mem0 |
260 | (define_predicate "m32c_mem0_operand" | |
261 | (ior (match_operand 0 "m32c_pseudo" "") | |
262 | (and (match_code "reg") | |
263 | (match_test "REGNO(op) == MEM0_REGNO")))) | |
264 | ||
265 | ; TRUE for things the call patterns can return. | |
266 | (define_predicate "m32c_return_operand" | |
267 | (ior (match_operand 0 "m32c_r0_operand") | |
268 | (ior (match_operand 0 "m32c_mem0_operand") | |
269 | (match_code "parallel")))) | |
12ea2512 DD |
270 | |
271 | ; TRUE for constants we can multiply pointers by | |
272 | (define_predicate "m32c_psi_scale" | |
273 | (and (match_operand 0 "const_int_operand") | |
274 | (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")"))) | |
07127a0a DD |
275 | |
276 | ; TRUE for one bit set (bit) or clear (mask) out of N bits. | |
277 | ||
278 | (define_predicate "m32c_1bit8_operand" | |
279 | (and (match_operand 0 "const_int_operand") | |
280 | (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")"))) | |
281 | ||
282 | (define_predicate "m32c_1bit16_operand" | |
283 | (and (match_operand 0 "const_int_operand") | |
284 | (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilw\")"))) | |
285 | ||
286 | (define_predicate "m32c_1mask8_operand" | |
287 | (and (match_operand 0 "const_int_operand") | |
288 | (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imb\")"))) | |
289 | ||
290 | (define_predicate "m32c_1mask16_operand" | |
291 | (and (match_operand 0 "const_int_operand") | |
292 | (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imw\")"))) |