[thirdparty/gcc.git] / gcc / config / m32c / shift.md

;; Machine Descriptions for R8C/M16C/M32C
;; Copyright (C) 2005, 2007
;; Free Software Foundation, Inc.
;; Contributed by Red Hat.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; bit shifting

; Shifts are unusual for m32c.  We only support shifting in one
; "direction" but the shift count is signed.  Also, immediate shift
; counts have a limited range, and variable shift counts have to be in
; $r1h which GCC normally doesn't even know about.

; Other than compensating for the above, the patterns below are pretty
; straightforward.

(define_insn "ashlqi3_i"
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
	(ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
		   (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.b\t%2,%0
   mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrqi3_i"
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.b\t%2,%0
   mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrqi3_i"
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   shl.b\t%2,%0
   mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_expand "ashlqi3"
  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
	(ashift:QI (match_operand:QI 1 "mra_operand" "")
		   (match_operand:QI 2 "general_operand" "")))
   (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrqi3"
  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
		     (neg:QI (match_operand:QI 2 "general_operand" ""))))
   (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrqi3"
  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
		   (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
				(neg:QI (match_operand:QI 2 "general_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

(define_insn "ashlhi3_i"
  [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
	(ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
		   (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.w\t%2,%0
   mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrhi3_i"
  [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.w\t%2,%0
   mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrhi3_i"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   shl.w\t%2,%0
   mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_expand "ashlhi3"
  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
		   (ashift:HI (match_operand:HI 1 "mra_operand" "")
			      (match_operand:QI 2 "general_operand" "")))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrhi3"
  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
		   (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
				(neg:QI (match_operand:QI 2 "general_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrhi3"
  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
		   (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
				(neg:QI (match_operand:QI 2 "general_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )


; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


(define_insn "ashlpsi3_i"
  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
	(ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
		    (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrpsi3_i"
  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
		      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrpsi3_i"
  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
		      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   shl.l\t%2,%0
   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_expand "ashlpsi3"
  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
		   (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
			       (match_operand:QI 2 "shiftcount_operand" "")))
	      (clobber (match_scratch:HI 3 ""))])]
  "TARGET_A24"
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrpsi3"
  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
		   (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
				 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  "TARGET_A24"
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrpsi3"
  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
		   (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
				 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  "TARGET_A24"
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

; The m16c has a maximum shift count of -16..16, even when in a
; register.  It's optimal to use multiple shifts of -8..8 rather than
; loading larger constants into R1H multiple time.  The m32c can shift
; -32..32 either via immediates or in registers.  Hence, separate
; patterns.


(define_insn "ashlsi3_16"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
		   (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A16"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrsi3_16"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A16"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrsi3_16"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A16"
  "@
   shl.l\t%2,%0
   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_insn "ashlsi3_24"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
		   (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  )

(define_insn "ashrsi3_24"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  )

(define_insn "lshrsi3_24"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   shl.l\t%2,%0
   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
  )


(define_expand "ashlsi3"
  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
		   (ashift:SI (match_operand:SI 1 "r0123_operand" "")
			      (match_operand:QI 2 "mrai_operand" "")))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrsi3"
  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
		   (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
				(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrsi3"
  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
		   (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
				(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )
Commit	Line	Data
38b2d076	1	;; Machine Descriptions for R8C/M16C/M32C
2f83c7d6	2	;; Copyright (C) 2005, 2007
38b2d076 DD	3	;; Free Software Foundation, Inc.
	4	;; Contributed by Red Hat.
	5	;;
	6	;; This file is part of GCC.
	7	;;
	8	;; GCC is free software; you can redistribute it and/or modify it
	9	;; under the terms of the GNU General Public License as published
2f83c7d6	10	;; by the Free Software Foundation; either version 3, or (at your
38b2d076 DD	11	;; option) any later version.
	12	;;
	13	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	14	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	;; License for more details.
	17	;;
	18	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	19	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	20	;; <http://www.gnu.org/licenses/>.
38b2d076 DD	21
	22	;; bit shifting
	23
	24	; Shifts are unusual for m32c. We only support shifting in one
	25	; "direction" but the shift count is signed. Also, immediate shift
	26	; counts have a limited range, and variable shift counts have to be in
	27	; $r1h which GCC normally doesn't even know about.
	28
	29	; Other than compensating for the above, the patterns below are pretty
	30	; straightforward.
	31
	32	(define_insn "ashlqi3_i"
	33	[(set (match_operand:QI 0 "mra_operand" "=RqiSdRmm,RqiSdRmm")
	34	(ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
23fed240	35	(match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
38b2d076 DD	36	(clobber (match_scratch:HI 3 "=X,R1w"))]
	37	""
	38	"@
	39	sha.b\t%2,%0
23fed240	40	mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
16659fcf	41	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	42	)
	43
	44	(define_insn "ashrqi3_i"
	45	[(set (match_operand:QI 0 "mra_operand" "=RqiSdRmm,RqiSdRmm")
	46	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
23fed240	47	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	48	(clobber (match_scratch:HI 3 "=X,R1w"))]
	49	""
	50	"@
	51	sha.b\t%2,%0
23fed240	52	mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
16659fcf	53	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	54	)
38b2d076 DD	55
23fed240	56	(define_insn "lshrqi3_i"
38b2d076 DD	57	[(set (match_operand:QI 0 "mra_operand" "=RqiSdRmm,RqiSdRmm")
38b2d076 DD	58	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
23fed240	59	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	60	(clobber (match_scratch:HI 3 "=X,R1w"))]
	61	""
	62	"@
	63	shl.b\t%2,%0
23fed240	64	mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
16659fcf	65	[(set_attr "flags" "szc,szc")]
38b2d076 DD	66	)
	67
	68
	69	(define_expand "ashlqi3"
	70	[(parallel [(set (match_operand:QI 0 "mra_operand" "")
	71	(ashift:QI (match_operand:QI 1 "mra_operand" "")
	72	(match_operand:QI 2 "general_operand" "")))
	73	(clobber (match_scratch:HI 3 ""))])]
	74	""
23fed240	75	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	76	DONE;"
	77	)
	78
	79	(define_expand "ashrqi3"
	80	[(parallel [(set (match_operand:QI 0 "mra_operand" "")
	81	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
	82	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	83	(clobber (match_scratch:HI 3 ""))])]
	84	""
23fed240	85	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	86	DONE;"
	87	)
	88
	89	(define_expand "lshrqi3"
	90	[(parallel [(set (match_operand:QI 0 "mra_operand" "")
	91	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
	92	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	93	(clobber (match_scratch:HI 3 ""))])]
	94	""
23fed240	95	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	96	DONE;"
	97	)
	98
	99	; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	100
	101	(define_insn "ashlhi3_i"
	102	[(set (match_operand:HI 0 "mra_operand" "=SdRhiRmm,SdRhiRmm")
	103	(ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
23fed240	104	(match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
38b2d076 DD	105	(clobber (match_scratch:HI 3 "=X,R1w"))]
	106	""
	107	"@
	108	sha.w\t%2,%0
23fed240	109	mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
16659fcf	110	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	111	)
	112
	113	(define_insn "ashrhi3_i"
	114	[(set (match_operand:HI 0 "mra_operand" "=SdRhiRmm,SdRhiRmm")
	115	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
23fed240	116	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	117	(clobber (match_scratch:HI 3 "=X,R1w"))]
	118	""
	119	"@
	120	sha.w\t%2,%0
23fed240	121	mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
16659fcf	122	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	123	)
38b2d076 DD	124
23fed240	125	(define_insn "lshrhi3_i"
38b2d076 DD	126	[(set (match_operand:HI 0 "mra_operand" "=RhiSdRmm,RhiSdRmm")
38b2d076 DD	127	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
23fed240	128	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	129	(clobber (match_scratch:HI 3 "=X,R1w"))]
	130	""
	131	"@
	132	shl.w\t%2,%0
23fed240	133	mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
16659fcf	134	[(set_attr "flags" "szc,szc")]
38b2d076 DD	135	)
	136
	137
	138	(define_expand "ashlhi3"
	139	[(parallel [(set (match_operand:HI 0 "mra_operand" "")
	140	(ashift:HI (match_operand:HI 1 "mra_operand" "")
	141	(match_operand:QI 2 "general_operand" "")))
	142	(clobber (match_scratch:HI 3 ""))])]
	143	""
23fed240	144	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	145	DONE;"
	146	)
	147
	148	(define_expand "ashrhi3"
	149	[(parallel [(set (match_operand:HI 0 "mra_operand" "")
	150	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
	151	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	152	(clobber (match_scratch:HI 3 ""))])]
	153	""
23fed240	154	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	155	DONE;"
	156	)
	157
	158	(define_expand "lshrhi3"
	159	[(parallel [(set (match_operand:HI 0 "mra_operand" "")
	160	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
	161	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	162	(clobber (match_scratch:HI 3 ""))])]
	163	""
23fed240	164	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	165	DONE;"
	166	)
	167
	168
	169
	170
	171	; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	172
	173
	174	(define_insn "ashlpsi3_i"
	175	[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSdRmm,R02RaaSdRmm")
	176	(ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
3eb5f26f	177	(match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
38b2d076 DD	178	(clobber (match_scratch:HI 3 "=X,R1w"))]
	179	"TARGET_A24"
	180	"@
	181	sha.l\t%2,%0
23fed240	182	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	183	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	184	)
	185
	186	(define_insn "ashrpsi3_i"
	187	[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSdRmm,R02RaaSdRmm")
	188	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
3eb5f26f	189	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076 DD	190	(clobber (match_scratch:HI 3 "=X,R1w"))]
	191	"TARGET_A24"
	192	"@
	193	sha.l\t%2,%0
23fed240	194	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	195	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	196	)
38b2d076 DD	197
23fed240	198	(define_insn "lshrpsi3_i"
38b2d076 DD	199	[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
38b2d076 DD	200	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
23fed240	201	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076 DD	202	(clobber (match_scratch:HI 3 "=X,R1w"))]
	203	"TARGET_A24"
	204	"@
	205	shl.l\t%2,%0
23fed240	206	mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
16659fcf	207	[(set_attr "flags" "szc,szc")]
38b2d076 DD	208	)
	209
	210
	211	(define_expand "ashlpsi3"
	212	[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
	213	(ashift:PSI (match_operand:PSI 1 "mra_operand" "")
3eb5f26f	214	(match_operand:QI 2 "shiftcount_operand" "")))
38b2d076 DD	215	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	216	"TARGET_A24"
23fed240	217	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	218	DONE;"
	219	)
	220
	221	(define_expand "ashrpsi3"
	222	[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
	223	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
3eb5f26f	224	(neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
38b2d076 DD	225	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	226	"TARGET_A24"
23fed240	227	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	228	DONE;"
	229	)
	230
	231	(define_expand "lshrpsi3"
	232	[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
	233	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
3eb5f26f	234	(neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
38b2d076 DD	235	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	236	"TARGET_A24"
23fed240	237	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	238	DONE;"
	239	)
	240
	241	; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	242
23fed240 DD	243	; The m16c has a maximum shift count of -16..16, even when in a
	244	; register. It's optimal to use multiple shifts of -8..8 rather than
	245	; loading larger constants into R1H multiple time. The m32c can shift
	246	; -32..32 either via immediates or in registers. Hence, separate
	247	; patterns.
38b2d076 DD	248
38b2d076 DD	249
23fed240	250	(define_insn "ashlsi3_16"
38b2d076 DD	251	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
38b2d076 DD	252	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
23fed240	253	(match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
38b2d076	254	(clobber (match_scratch:HI 3 "=X,R1w"))]
23fed240	255	"TARGET_A16"
38b2d076 DD	256	"@
38b2d076 DD	257	sha.l\t%2,%0
23fed240	258	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	259	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	260	)
38b2d076 DD	261
23fed240	262	(define_insn "ashrsi3_16"
38b2d076 DD	263	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
38b2d076 DD	264	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
23fed240	265	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076	266	(clobber (match_scratch:HI 3 "=X,R1w"))]
23fed240	267	"TARGET_A16"
38b2d076 DD	268	"@
38b2d076 DD	269	sha.l\t%2,%0
23fed240	270	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	271	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	272	)
38b2d076 DD	273
23fed240	274	(define_insn "lshrsi3_16"
38b2d076 DD	275	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
38b2d076 DD	276	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
23fed240	277	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076	278	(clobber (match_scratch:HI 3 "=X,R1w"))]
23fed240	279	"TARGET_A16"
38b2d076 DD	280	"@
38b2d076 DD	281	shl.l\t%2,%0
23fed240	282	mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
16659fcf	283	[(set_attr "flags" "szc,szc")]
23fed240 DD	284	)
	285
	286
	287
	288	(define_insn "ashlsi3_24"
	289	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	290	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
	291	(match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
	292	(clobber (match_scratch:HI 3 "=X,R1w"))]
	293	"TARGET_A24"
	294	"@
	295	sha.l\t%2,%0
	296	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
38b2d076 DD	297	)
38b2d076 DD	298
23fed240 DD	299	(define_insn "ashrsi3_24"
	300	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	301	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
	302	(neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
	303	(clobber (match_scratch:HI 3 "=X,R1w"))]
	304	"TARGET_A24"
	305	"@
	306	sha.l\t%2,%0
	307	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
	308	)
	309
	310	(define_insn "lshrsi3_24"
	311	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	312	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
	313	(neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
	314	(clobber (match_scratch:HI 3 "=X,R1w"))]
	315	"TARGET_A24"
	316	"@
	317	shl.l\t%2,%0
	318	mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
	319	)
	320
	321
	322
38b2d076 DD	323
	324	(define_expand "ashlsi3"
	325	[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
23fed240 DD	326	(ashift:SI (match_operand:SI 1 "r0123_operand" "")
23fed240 DD	327	(match_operand:QI 2 "mrai_operand" "")))
38b2d076 DD	328	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	329	""
23fed240	330	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	331	DONE;"
	332	)
	333
	334	(define_expand "ashrsi3"
	335	[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
	336	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
	337	(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	338	(clobber (match_scratch:HI 3 ""))])]
	339	""
23fed240	340	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	341	DONE;"
	342	)
	343
	344	(define_expand "lshrsi3"
	345	[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
	346	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
	347	(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	348	(clobber (match_scratch:HI 3 ""))])]
	349	""
23fed240	350	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	351	DONE;"
38b2d076 DD	352	)