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1f92da87 | 1 | /* Subroutines used for code generation on the Renesas M32R cpu. |
22a14e0d | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
e2265be0 | 3 | 2005, 2007 Free Software Foundation, Inc. |
8c5ca3b9 | 4 | |
1f92da87 | 5 | This file is part of GCC. |
8c5ca3b9 | 6 | |
1f92da87 NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
1f92da87 | 10 | option) any later version. |
8c5ca3b9 | 11 | |
1f92da87 NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
8c5ca3b9 | 16 | |
1f92da87 | 17 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
8c5ca3b9 | 20 | |
8c5ca3b9 | 21 | #include "config.h" |
5b8ae21f | 22 | #include "system.h" |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
8c5ca3b9 DE |
25 | #include "tree.h" |
26 | #include "rtl.h" | |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "real.h" | |
30 | #include "insn-config.h" | |
31 | #include "conditions.h" | |
8c5ca3b9 DE |
32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "expr.h" | |
bf6bb899 | 36 | #include "function.h" |
8c5ca3b9 | 37 | #include "recog.h" |
61f3b78f | 38 | #include "toplev.h" |
16f104b3 | 39 | #include "ggc.h" |
18d7916e | 40 | #include "integrate.h" |
245ff137 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
fbaeb717 | 44 | #include "tm-constrs.h" |
8c5ca3b9 DE |
45 | |
46 | /* Save the operands last given to a compare for use when we | |
47 | generate a scc or bcc insn. */ | |
48 | rtx m32r_compare_op0, m32r_compare_op1; | |
49 | ||
50 | /* Array of valid operand punctuation characters. */ | |
51 | char m32r_punct_chars[256]; | |
52 | ||
8c5ca3b9 | 53 | /* Selected code model. */ |
97b73103 | 54 | enum m32r_model m32r_model = M32R_MODEL_DEFAULT; |
8c5ca3b9 DE |
55 | |
56 | /* Selected SDA support. */ | |
97b73103 | 57 | enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT; |
8c5ca3b9 | 58 | |
89e6b702 RH |
59 | /* Machine-specific symbol_ref flags. */ |
60 | #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT | |
61 | #define SYMBOL_REF_MODEL(X) \ | |
62 | ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3)) | |
63 | ||
64 | /* For string literals, etc. */ | |
65 | #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.') | |
66 | ||
2b7972b0 | 67 | /* Forward declaration. */ |
97b73103 | 68 | static bool m32r_handle_option (size_t, const char *, int); |
7f682641 SB |
69 | static void init_reg_tables (void); |
70 | static void block_move_call (rtx, rtx, rtx); | |
71 | static int m32r_is_insn (rtx); | |
91d231cb | 72 | const struct attribute_spec m32r_attribute_table[]; |
7f682641 SB |
73 | static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *); |
74 | static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT); | |
75 | static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
76 | ||
77 | static void m32r_file_start (void); | |
78 | ||
7f682641 | 79 | static int m32r_adjust_priority (rtx, int); |
7f682641 SB |
80 | static int m32r_issue_rate (void); |
81 | ||
82 | static void m32r_encode_section_info (tree, rtx, int); | |
83 | static bool m32r_in_small_data_p (tree); | |
a7ed00da KH |
84 | static bool m32r_return_in_memory (tree, tree); |
85 | static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, | |
86 | tree, int *, int); | |
7f682641 SB |
87 | static void init_idents (void); |
88 | static bool m32r_rtx_costs (rtx, int, int, int *); | |
8cd5a4e0 RH |
89 | static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
90 | tree, bool); | |
78a52f11 RH |
91 | static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
92 | tree, bool); | |
672a6f42 NB |
93 | \f |
94 | /* Initialize the GCC target structure. */ | |
1f92da87 | 95 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 96 | #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table |
2b7972b0 | 97 | |
1f92da87 | 98 | #undef TARGET_ASM_ALIGNED_HI_OP |
301d03af | 99 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" |
1f92da87 | 100 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af RS |
101 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" |
102 | ||
1f92da87 | 103 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 | 104 | #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue |
1f92da87 | 105 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
106 | #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue |
107 | ||
1f92da87 | 108 | #undef TARGET_ASM_FILE_START |
1bc7c5b6 ZW |
109 | #define TARGET_ASM_FILE_START m32r_file_start |
110 | ||
1f92da87 | 111 | #undef TARGET_SCHED_ADJUST_PRIORITY |
c237e94a | 112 | #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority |
1f92da87 | 113 | #undef TARGET_SCHED_ISSUE_RATE |
c237e94a | 114 | #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate |
c237e94a | 115 | |
97b73103 RS |
116 | #undef TARGET_DEFAULT_TARGET_FLAGS |
117 | #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT | |
118 | #undef TARGET_HANDLE_OPTION | |
119 | #define TARGET_HANDLE_OPTION m32r_handle_option | |
120 | ||
1f92da87 | 121 | #undef TARGET_ENCODE_SECTION_INFO |
fb49053f | 122 | #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info |
1f92da87 | 123 | #undef TARGET_IN_SMALL_DATA_P |
89e6b702 | 124 | #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p |
fb49053f | 125 | |
1f92da87 | 126 | #undef TARGET_RTX_COSTS |
3c50106f | 127 | #define TARGET_RTX_COSTS m32r_rtx_costs |
1f92da87 | 128 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 129 | #define TARGET_ADDRESS_COST hook_int_rtx_0 |
3c50106f | 130 | |
a7ed00da KH |
131 | #undef TARGET_PROMOTE_PROTOTYPES |
132 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
a7ed00da KH |
133 | #undef TARGET_RETURN_IN_MEMORY |
134 | #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory | |
a7ed00da KH |
135 | #undef TARGET_SETUP_INCOMING_VARARGS |
136 | #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs | |
fe984136 RH |
137 | #undef TARGET_MUST_PASS_IN_STACK |
138 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
139 | #undef TARGET_PASS_BY_REFERENCE |
140 | #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference | |
78a52f11 RH |
141 | #undef TARGET_ARG_PARTIAL_BYTES |
142 | #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes | |
fe984136 | 143 | |
f6897b10 | 144 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 145 | \f |
97b73103 RS |
146 | /* Implement TARGET_HANDLE_OPTION. */ |
147 | ||
148 | static bool | |
149 | m32r_handle_option (size_t code, const char *arg, int value) | |
150 | { | |
151 | switch (code) | |
152 | { | |
153 | case OPT_m32r: | |
154 | target_flags &= ~(MASK_M32R2 | MASK_M32RX); | |
155 | return true; | |
156 | ||
157 | case OPT_mmodel_: | |
158 | if (strcmp (arg, "small") == 0) | |
159 | m32r_model = M32R_MODEL_SMALL; | |
160 | else if (strcmp (arg, "medium") == 0) | |
161 | m32r_model = M32R_MODEL_MEDIUM; | |
162 | else if (strcmp (arg, "large") == 0) | |
163 | m32r_model = M32R_MODEL_LARGE; | |
164 | else | |
165 | return false; | |
166 | return true; | |
167 | ||
168 | case OPT_msdata_: | |
169 | if (strcmp (arg, "none") == 0) | |
170 | m32r_sdata = M32R_SDATA_NONE; | |
171 | else if (strcmp (arg, "sdata") == 0) | |
172 | m32r_sdata = M32R_SDATA_SDATA; | |
173 | else if (strcmp (arg, "use") == 0) | |
174 | m32r_sdata = M32R_SDATA_USE; | |
175 | else | |
176 | return false; | |
177 | return true; | |
178 | ||
97b73103 RS |
179 | case OPT_mno_flush_func: |
180 | m32r_cache_flush_func = NULL; | |
181 | return true; | |
182 | ||
183 | case OPT_mflush_trap_: | |
55bea00a | 184 | return value <= 15; |
97b73103 RS |
185 | |
186 | case OPT_mno_flush_trap: | |
187 | m32r_cache_flush_trap = -1; | |
188 | return true; | |
189 | ||
190 | default: | |
191 | return true; | |
192 | } | |
193 | } | |
194 | ||
8c5ca3b9 DE |
195 | /* Called by OVERRIDE_OPTIONS to initialize various things. */ |
196 | ||
197 | void | |
1f92da87 | 198 | m32r_init (void) |
8c5ca3b9 DE |
199 | { |
200 | init_reg_tables (); | |
201 | ||
202 | /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */ | |
203 | memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars)); | |
204 | m32r_punct_chars['#'] = 1; | |
205 | m32r_punct_chars['@'] = 1; /* ??? no longer used */ | |
206 | ||
207 | /* Provide default value if not specified. */ | |
208 | if (!g_switch_set) | |
209 | g_switch_value = SDATA_DEFAULT_SIZE; | |
8c5ca3b9 DE |
210 | } |
211 | ||
212 | /* Vectors to keep interesting information about registers where it can easily | |
213 | be got. We use to use the actual mode value as the bit number, but there | |
214 | is (or may be) more than 32 modes now. Instead we use two tables: one | |
215 | indexed by hard register number, and one indexed by mode. */ | |
216 | ||
217 | /* The purpose of m32r_mode_class is to shrink the range of modes so that | |
85f65093 | 218 | they all fit (as bit numbers) in a 32-bit word (again). Each real mode is |
8c5ca3b9 DE |
219 | mapped into one m32r_mode_class mode. */ |
220 | ||
2b7972b0 MM |
221 | enum m32r_mode_class |
222 | { | |
8c5ca3b9 DE |
223 | C_MODE, |
224 | S_MODE, D_MODE, T_MODE, O_MODE, | |
56e2e762 | 225 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE |
8c5ca3b9 DE |
226 | }; |
227 | ||
228 | /* Modes for condition codes. */ | |
229 | #define C_MODES (1 << (int) C_MODE) | |
230 | ||
231 | /* Modes for single-word and smaller quantities. */ | |
232 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
233 | ||
234 | /* Modes for double-word and smaller quantities. */ | |
235 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
236 | ||
237 | /* Modes for quad-word and smaller quantities. */ | |
238 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
239 | ||
56e2e762 NC |
240 | /* Modes for accumulators. */ |
241 | #define A_MODES (1 << (int) A_MODE) | |
2b7972b0 | 242 | |
8c5ca3b9 DE |
243 | /* Value is 1 if register/mode pair is acceptable on arc. */ |
244 | ||
0139adca | 245 | const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = |
2b7972b0 | 246 | { |
8c5ca3b9 DE |
247 | T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, |
248 | T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES, | |
de41e41c | 249 | S_MODES, C_MODES, A_MODES, A_MODES |
8c5ca3b9 DE |
250 | }; |
251 | ||
252 | unsigned int m32r_mode_class [NUM_MACHINE_MODES]; | |
253 | ||
254 | enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
255 | ||
256 | static void | |
1f92da87 | 257 | init_reg_tables (void) |
8c5ca3b9 DE |
258 | { |
259 | int i; | |
260 | ||
261 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
262 | { | |
263 | switch (GET_MODE_CLASS (i)) | |
264 | { | |
265 | case MODE_INT: | |
266 | case MODE_PARTIAL_INT: | |
267 | case MODE_COMPLEX_INT: | |
268 | if (GET_MODE_SIZE (i) <= 4) | |
269 | m32r_mode_class[i] = 1 << (int) S_MODE; | |
270 | else if (GET_MODE_SIZE (i) == 8) | |
271 | m32r_mode_class[i] = 1 << (int) D_MODE; | |
272 | else if (GET_MODE_SIZE (i) == 16) | |
273 | m32r_mode_class[i] = 1 << (int) T_MODE; | |
274 | else if (GET_MODE_SIZE (i) == 32) | |
275 | m32r_mode_class[i] = 1 << (int) O_MODE; | |
e2265be0 | 276 | else |
8c5ca3b9 DE |
277 | m32r_mode_class[i] = 0; |
278 | break; | |
279 | case MODE_FLOAT: | |
280 | case MODE_COMPLEX_FLOAT: | |
281 | if (GET_MODE_SIZE (i) <= 4) | |
282 | m32r_mode_class[i] = 1 << (int) SF_MODE; | |
283 | else if (GET_MODE_SIZE (i) == 8) | |
284 | m32r_mode_class[i] = 1 << (int) DF_MODE; | |
285 | else if (GET_MODE_SIZE (i) == 16) | |
286 | m32r_mode_class[i] = 1 << (int) TF_MODE; | |
287 | else if (GET_MODE_SIZE (i) == 32) | |
288 | m32r_mode_class[i] = 1 << (int) OF_MODE; | |
e2265be0 | 289 | else |
8c5ca3b9 DE |
290 | m32r_mode_class[i] = 0; |
291 | break; | |
292 | case MODE_CC: | |
94134f42 ZW |
293 | m32r_mode_class[i] = 1 << (int) C_MODE; |
294 | break; | |
8c5ca3b9 | 295 | default: |
94134f42 | 296 | m32r_mode_class[i] = 0; |
8c5ca3b9 DE |
297 | break; |
298 | } | |
299 | } | |
300 | ||
301 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
302 | { | |
303 | if (GPR_P (i)) | |
304 | m32r_regno_reg_class[i] = GENERAL_REGS; | |
305 | else if (i == ARG_POINTER_REGNUM) | |
306 | m32r_regno_reg_class[i] = GENERAL_REGS; | |
307 | else | |
308 | m32r_regno_reg_class[i] = NO_REGS; | |
309 | } | |
310 | } | |
311 | \f | |
312 | /* M32R specific attribute support. | |
313 | ||
314 | interrupt - for interrupt functions | |
315 | ||
316 | model - select code model used to access object | |
317 | ||
318 | small: addresses use 24 bits, use bl to make calls | |
319 | medium: addresses use 32 bits, use bl to make calls | |
320 | large: addresses use 32 bits, use seth/add3/jl to make calls | |
321 | ||
1f92da87 | 322 | Grep for MODEL in m32r.h for more info. */ |
8c5ca3b9 | 323 | |
6aa489b4 NC |
324 | static tree small_ident1; |
325 | static tree small_ident2; | |
326 | static tree medium_ident1; | |
327 | static tree medium_ident2; | |
328 | static tree large_ident1; | |
329 | static tree large_ident2; | |
330 | ||
331 | static void | |
1f92da87 | 332 | init_idents (void) |
6aa489b4 | 333 | { |
91d231cb | 334 | if (small_ident1 == 0) |
6aa489b4 | 335 | { |
6aa489b4 NC |
336 | small_ident1 = get_identifier ("small"); |
337 | small_ident2 = get_identifier ("__small__"); | |
338 | medium_ident1 = get_identifier ("medium"); | |
339 | medium_ident2 = get_identifier ("__medium__"); | |
340 | large_ident1 = get_identifier ("large"); | |
341 | large_ident2 = get_identifier ("__large__"); | |
342 | } | |
343 | } | |
344 | ||
91d231cb JM |
345 | const struct attribute_spec m32r_attribute_table[] = |
346 | { | |
347 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
348 | { "interrupt", 0, 0, true, false, false, NULL }, | |
349 | { "model", 1, 1, true, false, false, m32r_handle_model_attribute }, | |
350 | { NULL, 0, 0, false, false, false, NULL } | |
351 | }; | |
8c5ca3b9 | 352 | |
91d231cb JM |
353 | |
354 | /* Handle an "model" attribute; arguments as in | |
355 | struct attribute_spec.handler. */ | |
356 | static tree | |
1f92da87 NC |
357 | m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name, |
358 | tree args, int flags ATTRIBUTE_UNUSED, | |
359 | bool *no_add_attrs) | |
8c5ca3b9 | 360 | { |
91d231cb | 361 | tree arg; |
8c5ca3b9 | 362 | |
91d231cb JM |
363 | init_idents (); |
364 | arg = TREE_VALUE (args); | |
365 | ||
366 | if (arg != small_ident1 | |
367 | && arg != small_ident2 | |
368 | && arg != medium_ident1 | |
369 | && arg != medium_ident2 | |
370 | && arg != large_ident1 | |
371 | && arg != large_ident2) | |
372 | { | |
5c498b10 | 373 | warning (OPT_Wattributes, "invalid argument of %qs attribute", |
91d231cb JM |
374 | IDENTIFIER_POINTER (name)); |
375 | *no_add_attrs = true; | |
376 | } | |
8c5ca3b9 | 377 | |
91d231cb | 378 | return NULL_TREE; |
8c5ca3b9 | 379 | } |
8c5ca3b9 | 380 | \f |
8c5ca3b9 DE |
381 | /* Encode section information of DECL, which is either a VAR_DECL, |
382 | FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???. | |
383 | ||
384 | For the M32R we want to record: | |
385 | ||
386 | - whether the object lives in .sdata/.sbss. | |
8c5ca3b9 | 387 | - what code model should be used to access the object |
8c5ca3b9 DE |
388 | */ |
389 | ||
fb49053f | 390 | static void |
1f92da87 | 391 | m32r_encode_section_info (tree decl, rtx rtl, int first) |
8c5ca3b9 | 392 | { |
89e6b702 RH |
393 | int extra_flags = 0; |
394 | tree model_attr; | |
395 | enum m32r_model model; | |
8c5ca3b9 | 396 | |
c6a2438a | 397 | default_encode_section_info (decl, rtl, first); |
89e6b702 RH |
398 | |
399 | if (!DECL_P (decl)) | |
b2003250 RH |
400 | return; |
401 | ||
89e6b702 RH |
402 | model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); |
403 | if (model_attr) | |
8c5ca3b9 | 404 | { |
89e6b702 | 405 | tree id; |
8c5ca3b9 | 406 | |
89e6b702 | 407 | init_idents (); |
8c5ca3b9 | 408 | |
89e6b702 | 409 | id = TREE_VALUE (TREE_VALUE (model_attr)); |
8c5ca3b9 | 410 | |
89e6b702 RH |
411 | if (id == small_ident1 || id == small_ident2) |
412 | model = M32R_MODEL_SMALL; | |
413 | else if (id == medium_ident1 || id == medium_ident2) | |
414 | model = M32R_MODEL_MEDIUM; | |
415 | else if (id == large_ident1 || id == large_ident2) | |
416 | model = M32R_MODEL_LARGE; | |
417 | else | |
75c3cfba | 418 | gcc_unreachable (); /* shouldn't happen */ |
89e6b702 RH |
419 | } |
420 | else | |
8c5ca3b9 | 421 | { |
89e6b702 RH |
422 | if (TARGET_MODEL_SMALL) |
423 | model = M32R_MODEL_SMALL; | |
424 | else if (TARGET_MODEL_MEDIUM) | |
425 | model = M32R_MODEL_MEDIUM; | |
426 | else if (TARGET_MODEL_LARGE) | |
427 | model = M32R_MODEL_LARGE; | |
8c5ca3b9 | 428 | else |
75c3cfba | 429 | gcc_unreachable (); /* shouldn't happen */ |
8c5ca3b9 | 430 | } |
89e6b702 | 431 | extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT; |
8c5ca3b9 | 432 | |
89e6b702 | 433 | if (extra_flags) |
c6a2438a | 434 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; |
89e6b702 | 435 | } |
6aa489b4 | 436 | |
89e6b702 RH |
437 | /* Only mark the object as being small data area addressable if |
438 | it hasn't been explicitly marked with a code model. | |
6aa489b4 | 439 | |
89e6b702 RH |
440 | The user can explicitly put an object in the small data area with the |
441 | section attribute. If the object is in sdata/sbss and marked with a | |
442 | code model do both [put the object in .sdata and mark it as being | |
443 | addressed with a specific code model - don't mark it as being addressed | |
444 | with an SDA reloc though]. This is ok and might be useful at times. If | |
445 | the object doesn't fit the linker will give an error. */ | |
8c5ca3b9 | 446 | |
89e6b702 | 447 | static bool |
1f92da87 | 448 | m32r_in_small_data_p (tree decl) |
89e6b702 RH |
449 | { |
450 | tree section; | |
451 | ||
452 | if (TREE_CODE (decl) != VAR_DECL) | |
453 | return false; | |
454 | ||
455 | if (lookup_attribute ("model", DECL_ATTRIBUTES (decl))) | |
456 | return false; | |
457 | ||
458 | section = DECL_SECTION_NAME (decl); | |
459 | if (section) | |
8c5ca3b9 | 460 | { |
89e6b702 RH |
461 | char *name = (char *) TREE_STRING_POINTER (section); |
462 | if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0) | |
463 | return true; | |
8c5ca3b9 | 464 | } |
89e6b702 RH |
465 | else |
466 | { | |
467 | if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE) | |
468 | { | |
469 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8c5ca3b9 | 470 | |
307b599c | 471 | if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) |
89e6b702 RH |
472 | return true; |
473 | } | |
474 | } | |
772c5265 | 475 | |
89e6b702 | 476 | return false; |
772c5265 RH |
477 | } |
478 | ||
8c5ca3b9 DE |
479 | /* Do anything needed before RTL is emitted for each function. */ |
480 | ||
481 | void | |
1f92da87 | 482 | m32r_init_expanders (void) |
8c5ca3b9 DE |
483 | { |
484 | /* ??? At one point there was code here. The function is left in | |
485 | to make it easy to experiment. */ | |
486 | } | |
487 | \f | |
8c5ca3b9 | 488 | int |
1f92da87 | 489 | call_operand (rtx op, enum machine_mode mode) |
8c5ca3b9 DE |
490 | { |
491 | if (GET_CODE (op) != MEM) | |
492 | return 0; | |
493 | op = XEXP (op, 0); | |
494 | return call_address_operand (op, mode); | |
495 | } | |
496 | ||
8c5ca3b9 DE |
497 | /* Return 1 if OP is a reference to an object in .sdata/.sbss. */ |
498 | ||
499 | int | |
1f92da87 | 500 | small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8c5ca3b9 DE |
501 | { |
502 | if (! TARGET_SDATA_USE) | |
503 | return 0; | |
504 | ||
505 | if (GET_CODE (op) == SYMBOL_REF) | |
89e6b702 | 506 | return SYMBOL_REF_SMALL_P (op); |
8c5ca3b9 DE |
507 | |
508 | if (GET_CODE (op) == CONST | |
509 | && GET_CODE (XEXP (op, 0)) == PLUS | |
510 | && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
fbaeb717 | 511 | && satisfies_constraint_J (XEXP (XEXP (op, 0), 1))) |
89e6b702 | 512 | return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0)); |
8c5ca3b9 DE |
513 | |
514 | return 0; | |
515 | } | |
516 | ||
85f65093 | 517 | /* Return 1 if OP is a symbol that can use 24-bit addressing. */ |
8c5ca3b9 DE |
518 | |
519 | int | |
1f92da87 | 520 | addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8c5ca3b9 | 521 | { |
89e6b702 RH |
522 | rtx sym; |
523 | ||
ad126521 KI |
524 | if (flag_pic) |
525 | return 0; | |
526 | ||
8c5ca3b9 DE |
527 | if (GET_CODE (op) == LABEL_REF) |
528 | return TARGET_ADDR24; | |
529 | ||
530 | if (GET_CODE (op) == SYMBOL_REF) | |
89e6b702 RH |
531 | sym = op; |
532 | else if (GET_CODE (op) == CONST | |
533 | && GET_CODE (XEXP (op, 0)) == PLUS | |
534 | && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
fbaeb717 | 535 | && satisfies_constraint_M (XEXP (XEXP (op, 0), 1))) |
89e6b702 RH |
536 | sym = XEXP (XEXP (op, 0), 0); |
537 | else | |
538 | return 0; | |
8c5ca3b9 | 539 | |
89e6b702 RH |
540 | if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL) |
541 | return 1; | |
542 | ||
543 | if (TARGET_ADDR24 | |
544 | && (CONSTANT_POOL_ADDRESS_P (sym) | |
545 | || LIT_NAME_P (XSTR (sym, 0)))) | |
546 | return 1; | |
8c5ca3b9 DE |
547 | |
548 | return 0; | |
549 | } | |
550 | ||
85f65093 | 551 | /* Return 1 if OP is a symbol that needs 32-bit addressing. */ |
8c5ca3b9 DE |
552 | |
553 | int | |
1f92da87 | 554 | addr32_operand (rtx op, enum machine_mode mode) |
8c5ca3b9 | 555 | { |
89e6b702 RH |
556 | rtx sym; |
557 | ||
8c5ca3b9 DE |
558 | if (GET_CODE (op) == LABEL_REF) |
559 | return TARGET_ADDR32; | |
560 | ||
561 | if (GET_CODE (op) == SYMBOL_REF) | |
89e6b702 RH |
562 | sym = op; |
563 | else if (GET_CODE (op) == CONST | |
564 | && GET_CODE (XEXP (op, 0)) == PLUS | |
565 | && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
ad126521 KI |
566 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT |
567 | && ! flag_pic) | |
89e6b702 RH |
568 | sym = XEXP (XEXP (op, 0), 0); |
569 | else | |
570 | return 0; | |
8c5ca3b9 | 571 | |
89e6b702 RH |
572 | return (! addr24_operand (sym, mode) |
573 | && ! small_data_operand (sym, mode)); | |
8c5ca3b9 DE |
574 | } |
575 | ||
576 | /* Return 1 if OP is a function that can be called with the `bl' insn. */ | |
577 | ||
578 | int | |
1f92da87 | 579 | call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8c5ca3b9 | 580 | { |
ad126521 | 581 | if (flag_pic) |
900a35c8 | 582 | return 1; |
ad126521 | 583 | |
8c5ca3b9 | 584 | if (GET_CODE (op) == SYMBOL_REF) |
89e6b702 | 585 | return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE; |
8c5ca3b9 DE |
586 | |
587 | return TARGET_CALL26; | |
588 | } | |
589 | ||
8c5ca3b9 DE |
590 | /* Return 1 if OP is a DImode const we want to handle inline. |
591 | This must match the code in the movdi pattern. | |
592 | It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */ | |
593 | ||
594 | int | |
1f92da87 | 595 | easy_di_const (rtx op) |
8c5ca3b9 DE |
596 | { |
597 | rtx high_rtx, low_rtx; | |
598 | HOST_WIDE_INT high, low; | |
599 | ||
600 | split_double (op, &high_rtx, &low_rtx); | |
601 | high = INTVAL (high_rtx); | |
602 | low = INTVAL (low_rtx); | |
85f65093 | 603 | /* Pick constants loadable with 2 16-bit `ldi' insns. */ |
8c5ca3b9 DE |
604 | if (high >= -128 && high <= 127 |
605 | && low >= -128 && low <= 127) | |
606 | return 1; | |
607 | return 0; | |
608 | } | |
609 | ||
610 | /* Return 1 if OP is a DFmode const we want to handle inline. | |
611 | This must match the code in the movdf pattern. | |
612 | It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */ | |
613 | ||
614 | int | |
1f92da87 | 615 | easy_df_const (rtx op) |
8c5ca3b9 DE |
616 | { |
617 | REAL_VALUE_TYPE r; | |
618 | long l[2]; | |
619 | ||
620 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
621 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
622 | if (l[0] == 0 && l[1] == 0) | |
623 | return 1; | |
624 | if ((l[0] & 0xffff) == 0 && l[1] == 0) | |
625 | return 1; | |
626 | return 0; | |
627 | } | |
628 | ||
8c5ca3b9 DE |
629 | /* Return 1 if OP is (mem (reg ...)). |
630 | This is used in insn length calcs. */ | |
631 | ||
632 | int | |
1f92da87 | 633 | memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8c5ca3b9 DE |
634 | { |
635 | return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG; | |
636 | } | |
2b7972b0 | 637 | |
8cd5a4e0 | 638 | /* Return nonzero if TYPE must be passed by indirect reference. */ |
d88e80e6 | 639 | |
8cd5a4e0 RH |
640 | static bool |
641 | m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
642 | enum machine_mode mode, tree type, | |
643 | bool named ATTRIBUTE_UNUSED) | |
d88e80e6 | 644 | { |
8cd5a4e0 | 645 | int size; |
d88e80e6 | 646 | |
8cd5a4e0 RH |
647 | if (type) |
648 | size = int_size_in_bytes (type); | |
649 | else | |
650 | size = GET_MODE_SIZE (mode); | |
d88e80e6 | 651 | |
8cd5a4e0 | 652 | return (size < 0 || size > 8); |
d88e80e6 | 653 | } |
8c5ca3b9 DE |
654 | \f |
655 | /* Comparisons. */ | |
656 | ||
8c5ca3b9 | 657 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2b7972b0 MM |
658 | return the rtx for compare [arg0 of the if_then_else]. |
659 | If need_compare is true then the comparison insn must be generated, rather | |
dab66575 | 660 | than being subsumed into the following branch instruction. */ |
8c5ca3b9 DE |
661 | |
662 | rtx | |
1f92da87 | 663 | gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) |
8c5ca3b9 | 664 | { |
1f92da87 NC |
665 | enum rtx_code compare_code; |
666 | enum rtx_code branch_code; | |
ac17cd8f | 667 | rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM); |
61f3b78f | 668 | int must_swap = 0; |
8c5ca3b9 DE |
669 | |
670 | switch (code) | |
671 | { | |
2e076ddf NC |
672 | case EQ: compare_code = EQ; branch_code = NE; break; |
673 | case NE: compare_code = EQ; branch_code = EQ; break; | |
674 | case LT: compare_code = LT; branch_code = NE; break; | |
675 | case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break; | |
676 | case GT: compare_code = LT; branch_code = NE; must_swap = 1; break; | |
677 | case GE: compare_code = LT; branch_code = EQ; break; | |
8c5ca3b9 | 678 | case LTU: compare_code = LTU; branch_code = NE; break; |
2e076ddf NC |
679 | case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break; |
680 | case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break; | |
8c5ca3b9 | 681 | case GEU: compare_code = LTU; branch_code = EQ; break; |
61f3b78f RH |
682 | |
683 | default: | |
75c3cfba | 684 | gcc_unreachable (); |
8c5ca3b9 DE |
685 | } |
686 | ||
2b7972b0 MM |
687 | if (need_compare) |
688 | { | |
689 | switch (compare_code) | |
690 | { | |
691 | case EQ: | |
fbaeb717 | 692 | if (satisfies_constraint_P (y) /* Reg equal to small const. */ |
2b7972b0 MM |
693 | && y != const0_rtx) |
694 | { | |
e2265be0 KK |
695 | rtx tmp = gen_reg_rtx (SImode); |
696 | ||
085bd3ff | 697 | emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y)))); |
2b7972b0 MM |
698 | x = tmp; |
699 | y = const0_rtx; | |
700 | } | |
1f92da87 | 701 | else if (CONSTANT_P (y)) /* Reg equal to const. */ |
2b7972b0 MM |
702 | { |
703 | rtx tmp = force_reg (GET_MODE (x), y); | |
704 | y = tmp; | |
705 | } | |
706 | ||
1f92da87 NC |
707 | if (register_operand (y, SImode) /* Reg equal to reg. */ |
708 | || y == const0_rtx) /* Reg equal to zero. */ | |
2b7972b0 | 709 | { |
56e2e762 | 710 | emit_insn (gen_cmp_eqsi_insn (x, y)); |
e2265be0 | 711 | |
1c563bed | 712 | return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); |
2b7972b0 MM |
713 | } |
714 | break; | |
e2265be0 | 715 | |
2b7972b0 MM |
716 | case LT: |
717 | if (register_operand (y, SImode) | |
fbaeb717 | 718 | || satisfies_constraint_P (y)) |
2b7972b0 | 719 | { |
1f92da87 | 720 | rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */ |
e2265be0 | 721 | |
2b7972b0 MM |
722 | switch (code) |
723 | { | |
724 | case LT: | |
725 | emit_insn (gen_cmp_ltsi_insn (x, y)); | |
726 | code = EQ; | |
727 | break; | |
728 | case LE: | |
729 | if (y == const0_rtx) | |
730 | tmp = const1_rtx; | |
731 | else | |
085bd3ff | 732 | emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); |
2b7972b0 MM |
733 | emit_insn (gen_cmp_ltsi_insn (x, tmp)); |
734 | code = EQ; | |
735 | break; | |
736 | case GT: | |
737 | if (GET_CODE (y) == CONST_INT) | |
f1c25d3b | 738 | tmp = gen_rtx_PLUS (SImode, y, const1_rtx); |
2b7972b0 | 739 | else |
085bd3ff | 740 | emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); |
2b7972b0 MM |
741 | emit_insn (gen_cmp_ltsi_insn (x, tmp)); |
742 | code = NE; | |
743 | break; | |
744 | case GE: | |
745 | emit_insn (gen_cmp_ltsi_insn (x, y)); | |
746 | code = NE; | |
747 | break; | |
748 | default: | |
75c3cfba | 749 | gcc_unreachable (); |
2b7972b0 | 750 | } |
e2265be0 | 751 | |
1c563bed | 752 | return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); |
2b7972b0 MM |
753 | } |
754 | break; | |
e2265be0 | 755 | |
2b7972b0 MM |
756 | case LTU: |
757 | if (register_operand (y, SImode) | |
fbaeb717 | 758 | || satisfies_constraint_P (y)) |
2b7972b0 | 759 | { |
1f92da87 | 760 | rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */ |
e2265be0 | 761 | |
2b7972b0 MM |
762 | switch (code) |
763 | { | |
764 | case LTU: | |
765 | emit_insn (gen_cmp_ltusi_insn (x, y)); | |
766 | code = EQ; | |
767 | break; | |
768 | case LEU: | |
769 | if (y == const0_rtx) | |
770 | tmp = const1_rtx; | |
771 | else | |
085bd3ff | 772 | emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); |
2b7972b0 MM |
773 | emit_insn (gen_cmp_ltusi_insn (x, tmp)); |
774 | code = EQ; | |
775 | break; | |
776 | case GTU: | |
777 | if (GET_CODE (y) == CONST_INT) | |
f1c25d3b | 778 | tmp = gen_rtx_PLUS (SImode, y, const1_rtx); |
2b7972b0 | 779 | else |
085bd3ff | 780 | emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); |
2b7972b0 MM |
781 | emit_insn (gen_cmp_ltusi_insn (x, tmp)); |
782 | code = NE; | |
783 | break; | |
784 | case GEU: | |
785 | emit_insn (gen_cmp_ltusi_insn (x, y)); | |
786 | code = NE; | |
787 | break; | |
788 | default: | |
75c3cfba | 789 | gcc_unreachable (); |
2b7972b0 | 790 | } |
e2265be0 | 791 | |
1c563bed | 792 | return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); |
2b7972b0 MM |
793 | } |
794 | break; | |
795 | ||
796 | default: | |
75c3cfba | 797 | gcc_unreachable (); |
2b7972b0 MM |
798 | } |
799 | } | |
800 | else | |
8c5ca3b9 | 801 | { |
1f92da87 | 802 | /* Reg/reg equal comparison. */ |
8c5ca3b9 DE |
803 | if (compare_code == EQ |
804 | && register_operand (y, SImode)) | |
1c563bed | 805 | return gen_rtx_fmt_ee (code, CCmode, x, y); |
e2265be0 | 806 | |
1f92da87 | 807 | /* Reg/zero signed comparison. */ |
8c5ca3b9 DE |
808 | if ((compare_code == EQ || compare_code == LT) |
809 | && y == const0_rtx) | |
1c563bed | 810 | return gen_rtx_fmt_ee (code, CCmode, x, y); |
e2265be0 | 811 | |
1f92da87 | 812 | /* Reg/smallconst equal comparison. */ |
8c5ca3b9 | 813 | if (compare_code == EQ |
fbaeb717 | 814 | && satisfies_constraint_P (y)) |
8c5ca3b9 DE |
815 | { |
816 | rtx tmp = gen_reg_rtx (SImode); | |
1f92da87 | 817 | |
085bd3ff | 818 | emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y)))); |
1c563bed | 819 | return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx); |
8c5ca3b9 | 820 | } |
e2265be0 | 821 | |
1f92da87 | 822 | /* Reg/const equal comparison. */ |
8c5ca3b9 DE |
823 | if (compare_code == EQ |
824 | && CONSTANT_P (y)) | |
825 | { | |
826 | rtx tmp = force_reg (GET_MODE (x), y); | |
1f92da87 | 827 | |
1c563bed | 828 | return gen_rtx_fmt_ee (code, CCmode, x, tmp); |
8c5ca3b9 DE |
829 | } |
830 | } | |
831 | ||
2e076ddf | 832 | if (CONSTANT_P (y)) |
8c5ca3b9 | 833 | { |
2e076ddf | 834 | if (must_swap) |
8c5ca3b9 | 835 | y = force_reg (GET_MODE (x), y); |
2e076ddf NC |
836 | else |
837 | { | |
b72e46f0 NC |
838 | int ok_const = reg_or_int16_operand (y, GET_MODE (y)); |
839 | ||
2e076ddf NC |
840 | if (! ok_const) |
841 | y = force_reg (GET_MODE (x), y); | |
842 | } | |
8c5ca3b9 DE |
843 | } |
844 | ||
845 | switch (compare_code) | |
846 | { | |
847 | case EQ : | |
2e076ddf | 848 | emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y)); |
8c5ca3b9 DE |
849 | break; |
850 | case LT : | |
2e076ddf | 851 | emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y)); |
8c5ca3b9 DE |
852 | break; |
853 | case LTU : | |
2e076ddf | 854 | emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y)); |
8c5ca3b9 | 855 | break; |
61f3b78f RH |
856 | |
857 | default: | |
75c3cfba | 858 | gcc_unreachable (); |
8c5ca3b9 DE |
859 | } |
860 | ||
1c563bed | 861 | return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode)); |
8c5ca3b9 | 862 | } |
5b8ae21f MM |
863 | \f |
864 | /* Split a 2 word move (DI or DF) into component parts. */ | |
865 | ||
866 | rtx | |
1f92da87 | 867 | gen_split_move_double (rtx operands[]) |
5b8ae21f MM |
868 | { |
869 | enum machine_mode mode = GET_MODE (operands[0]); | |
870 | rtx dest = operands[0]; | |
871 | rtx src = operands[1]; | |
872 | rtx val; | |
873 | ||
ca3bf2b5 JW |
874 | /* We might have (SUBREG (MEM)) here, so just get rid of the |
875 | subregs to make this code simpler. It is safe to call | |
876 | alter_subreg any time after reload. */ | |
877 | if (GET_CODE (dest) == SUBREG) | |
68882f0f | 878 | alter_subreg (&dest); |
ca3bf2b5 | 879 | if (GET_CODE (src) == SUBREG) |
68882f0f | 880 | alter_subreg (&src); |
ca3bf2b5 | 881 | |
5b8ae21f | 882 | start_sequence (); |
ca3bf2b5 | 883 | if (GET_CODE (dest) == REG) |
5b8ae21f | 884 | { |
ca3bf2b5 JW |
885 | int dregno = REGNO (dest); |
886 | ||
1f92da87 | 887 | /* Reg = reg. */ |
ca3bf2b5 | 888 | if (GET_CODE (src) == REG) |
5b8ae21f | 889 | { |
ca3bf2b5 JW |
890 | int sregno = REGNO (src); |
891 | ||
892 | int reverse = (dregno == sregno + 1); | |
893 | ||
5b8ae21f MM |
894 | /* We normally copy the low-numbered register first. However, if |
895 | the first register operand 0 is the same as the second register of | |
896 | operand 1, we must copy in the opposite order. */ | |
5b8ae21f MM |
897 | emit_insn (gen_rtx_SET (VOIDmode, |
898 | operand_subword (dest, reverse, TRUE, mode), | |
899 | operand_subword (src, reverse, TRUE, mode))); | |
900 | ||
901 | emit_insn (gen_rtx_SET (VOIDmode, | |
902 | operand_subword (dest, !reverse, TRUE, mode), | |
903 | operand_subword (src, !reverse, TRUE, mode))); | |
904 | } | |
905 | ||
1f92da87 | 906 | /* Reg = constant. */ |
5b8ae21f MM |
907 | else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE) |
908 | { | |
909 | rtx words[2]; | |
910 | split_double (src, &words[0], &words[1]); | |
911 | emit_insn (gen_rtx_SET (VOIDmode, | |
912 | operand_subword (dest, 0, TRUE, mode), | |
913 | words[0])); | |
914 | ||
915 | emit_insn (gen_rtx_SET (VOIDmode, | |
916 | operand_subword (dest, 1, TRUE, mode), | |
917 | words[1])); | |
918 | } | |
919 | ||
1f92da87 | 920 | /* Reg = mem. */ |
5b8ae21f MM |
921 | else if (GET_CODE (src) == MEM) |
922 | { | |
923 | /* If the high-address word is used in the address, we must load it | |
924 | last. Otherwise, load it first. */ | |
f4ef873c RK |
925 | int reverse |
926 | = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0); | |
5b8ae21f MM |
927 | |
928 | /* We used to optimize loads from single registers as | |
929 | ||
930 | ld r1,r3+; ld r2,r3 | |
931 | ||
932 | if r3 were not used subsequently. However, the REG_NOTES aren't | |
dab66575 | 933 | propagated correctly by the reload phase, and it can cause bad |
5b8ae21f MM |
934 | code to be generated. We could still try: |
935 | ||
936 | ld r1,r3+; ld r2,r3; addi r3,-4 | |
937 | ||
938 | which saves 2 bytes and doesn't force longword alignment. */ | |
939 | emit_insn (gen_rtx_SET (VOIDmode, | |
940 | operand_subword (dest, reverse, TRUE, mode), | |
f4ef873c RK |
941 | adjust_address (src, SImode, |
942 | reverse * UNITS_PER_WORD))); | |
5b8ae21f MM |
943 | |
944 | emit_insn (gen_rtx_SET (VOIDmode, | |
945 | operand_subword (dest, !reverse, TRUE, mode), | |
f4ef873c RK |
946 | adjust_address (src, SImode, |
947 | !reverse * UNITS_PER_WORD))); | |
5b8ae21f | 948 | } |
5b8ae21f | 949 | else |
75c3cfba | 950 | gcc_unreachable (); |
5b8ae21f MM |
951 | } |
952 | ||
1f92da87 | 953 | /* Mem = reg. */ |
5b8ae21f MM |
954 | /* We used to optimize loads from single registers as |
955 | ||
956 | st r1,r3; st r2,+r3 | |
957 | ||
958 | if r3 were not used subsequently. However, the REG_NOTES aren't | |
dab66575 | 959 | propagated correctly by the reload phase, and it can cause bad |
5b8ae21f MM |
960 | code to be generated. We could still try: |
961 | ||
962 | st r1,r3; st r2,+r3; addi r3,-4 | |
963 | ||
964 | which saves 2 bytes and doesn't force longword alignment. */ | |
ca3bf2b5 | 965 | else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG) |
5b8ae21f | 966 | { |
5b8ae21f | 967 | emit_insn (gen_rtx_SET (VOIDmode, |
f4ef873c | 968 | adjust_address (dest, SImode, 0), |
5b8ae21f MM |
969 | operand_subword (src, 0, TRUE, mode))); |
970 | ||
971 | emit_insn (gen_rtx_SET (VOIDmode, | |
f4ef873c | 972 | adjust_address (dest, SImode, UNITS_PER_WORD), |
5b8ae21f MM |
973 | operand_subword (src, 1, TRUE, mode))); |
974 | } | |
975 | ||
976 | else | |
75c3cfba | 977 | gcc_unreachable (); |
5b8ae21f | 978 | |
2f937369 | 979 | val = get_insns (); |
5b8ae21f MM |
980 | end_sequence (); |
981 | return val; | |
982 | } | |
983 | ||
8c5ca3b9 | 984 | \f |
78a52f11 RH |
985 | static int |
986 | m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
987 | tree type, bool named ATTRIBUTE_UNUSED) | |
8c5ca3b9 | 988 | { |
78a52f11 | 989 | int words; |
16f104b3 NC |
990 | unsigned int size = |
991 | (((mode == BLKmode && type) | |
992 | ? (unsigned int) int_size_in_bytes (type) | |
993 | : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) | |
994 | / UNITS_PER_WORD; | |
8c5ca3b9 DE |
995 | |
996 | if (*cum >= M32R_MAX_PARM_REGS) | |
78a52f11 | 997 | words = 0; |
8c5ca3b9 | 998 | else if (*cum + size > M32R_MAX_PARM_REGS) |
78a52f11 | 999 | words = (*cum + size) - M32R_MAX_PARM_REGS; |
8c5ca3b9 | 1000 | else |
78a52f11 | 1001 | words = 0; |
8c5ca3b9 | 1002 | |
78a52f11 | 1003 | return words * UNITS_PER_WORD; |
8c5ca3b9 DE |
1004 | } |
1005 | ||
a7ed00da KH |
1006 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1007 | ||
1008 | static bool | |
1009 | m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
1010 | { | |
8cd5a4e0 | 1011 | return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false); |
a7ed00da KH |
1012 | } |
1013 | ||
8c5ca3b9 DE |
1014 | /* Do any needed setup for a variadic function. For the M32R, we must |
1015 | create a register parameter block, and then copy any anonymous arguments | |
1016 | in registers to memory. | |
1017 | ||
1018 | CUM has not been updated for the last named argument which has type TYPE | |
1019 | and mode MODE, and we rely on this fact. */ | |
1020 | ||
a7ed00da | 1021 | static void |
1f92da87 NC |
1022 | m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1023 | tree type, int *pretend_size, int no_rtl) | |
8c5ca3b9 DE |
1024 | { |
1025 | int first_anon_arg; | |
1026 | ||
1027 | if (no_rtl) | |
1028 | return; | |
1029 | ||
1030 | /* All BLKmode values are passed by reference. */ | |
75c3cfba | 1031 | gcc_assert (mode != BLKmode); |
8c5ca3b9 | 1032 | |
6c535c69 ZW |
1033 | first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type) |
1034 | + ROUND_ADVANCE_ARG (mode, type)); | |
8c5ca3b9 DE |
1035 | |
1036 | if (first_anon_arg < M32R_MAX_PARM_REGS) | |
1037 | { | |
1038 | /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */ | |
1039 | int first_reg_offset = first_anon_arg; | |
1040 | /* Size in words to "pretend" allocate. */ | |
1041 | int size = M32R_MAX_PARM_REGS - first_reg_offset; | |
1042 | rtx regblock; | |
1043 | ||
e2265be0 KK |
1044 | regblock = gen_frame_mem (BLKmode, |
1045 | plus_constant (arg_pointer_rtx, | |
1046 | FIRST_PARM_OFFSET (0))); | |
ba4828e0 | 1047 | set_mem_alias_set (regblock, get_varargs_alias_set ()); |
c6b97fac | 1048 | move_block_from_reg (first_reg_offset, regblock, size); |
8c5ca3b9 DE |
1049 | |
1050 | *pretend_size = (size * UNITS_PER_WORD); | |
1051 | } | |
1052 | } | |
40cae311 | 1053 | |
56e2e762 | 1054 | \f |
23568fa0 | 1055 | /* Return true if INSN is real instruction bearing insn. */ |
56e2e762 | 1056 | |
23568fa0 | 1057 | static int |
1f92da87 | 1058 | m32r_is_insn (rtx insn) |
23568fa0 NC |
1059 | { |
1060 | return (INSN_P (insn) | |
1061 | && GET_CODE (PATTERN (insn)) != USE | |
1062 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
1063 | && GET_CODE (PATTERN (insn)) != ADDR_VEC); | |
1064 | } | |
1065 | ||
1066 | /* Increase the priority of long instructions so that the | |
1067 | short instructions are scheduled ahead of the long ones. */ | |
56e2e762 | 1068 | |
c237e94a | 1069 | static int |
1f92da87 | 1070 | m32r_adjust_priority (rtx insn, int priority) |
56e2e762 | 1071 | { |
23568fa0 NC |
1072 | if (m32r_is_insn (insn) |
1073 | && get_attr_insn_size (insn) != INSN_SIZE_SHORT) | |
1074 | priority <<= 3; | |
56e2e762 NC |
1075 | |
1076 | return priority; | |
1077 | } | |
1078 | ||
1079 | \f | |
c237e94a ZW |
1080 | /* Indicate how many instructions can be issued at the same time. |
1081 | This is sort of a lie. The m32r can issue only 1 long insn at | |
1082 | once, but it can issue 2 short insns. The default therefore is | |
1083 | set at 2, but this can be overridden by the command line option | |
1f92da87 NC |
1084 | -missue-rate=1. */ |
1085 | ||
c237e94a | 1086 | static int |
1f92da87 | 1087 | m32r_issue_rate (void) |
c237e94a ZW |
1088 | { |
1089 | return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2); | |
56e2e762 | 1090 | } |
56e2e762 | 1091 | \f |
8c5ca3b9 DE |
1092 | /* Cost functions. */ |
1093 | ||
3c50106f | 1094 | static bool |
1f92da87 | 1095 | m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total) |
3c50106f RH |
1096 | { |
1097 | switch (code) | |
1098 | { | |
1099 | /* Small integers are as cheap as registers. 4 byte values can be | |
1100 | fetched as immediate constants - let's give that the cost of an | |
1101 | extra insn. */ | |
1102 | case CONST_INT: | |
1103 | if (INT16_P (INTVAL (x))) | |
1104 | { | |
1105 | *total = 0; | |
1106 | return true; | |
1107 | } | |
5efb1046 | 1108 | /* FALLTHRU */ |
3c50106f RH |
1109 | |
1110 | case CONST: | |
1111 | case LABEL_REF: | |
1112 | case SYMBOL_REF: | |
1113 | *total = COSTS_N_INSNS (1); | |
1114 | return true; | |
1115 | ||
1116 | case CONST_DOUBLE: | |
1117 | { | |
1118 | rtx high, low; | |
1f92da87 | 1119 | |
3c50106f RH |
1120 | split_double (x, &high, &low); |
1121 | *total = COSTS_N_INSNS (!INT16_P (INTVAL (high)) | |
1122 | + !INT16_P (INTVAL (low))); | |
1123 | return true; | |
1124 | } | |
1125 | ||
1126 | case MULT: | |
1127 | *total = COSTS_N_INSNS (3); | |
1128 | return true; | |
1129 | ||
1130 | case DIV: | |
1131 | case UDIV: | |
1132 | case MOD: | |
1133 | case UMOD: | |
1134 | *total = COSTS_N_INSNS (10); | |
1135 | return true; | |
1136 | ||
1137 | default: | |
1138 | return false; | |
1139 | } | |
1140 | } | |
8c5ca3b9 DE |
1141 | \f |
1142 | /* Type of function DECL. | |
1143 | ||
1144 | The result is cached. To reset the cache at the end of a function, | |
1145 | call with DECL = NULL_TREE. */ | |
1146 | ||
1147 | enum m32r_function_type | |
1f92da87 | 1148 | m32r_compute_function_type (tree decl) |
8c5ca3b9 DE |
1149 | { |
1150 | /* Cached value. */ | |
1151 | static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN; | |
1152 | /* Last function we were called for. */ | |
1153 | static tree last_fn = NULL_TREE; | |
1154 | ||
1155 | /* Resetting the cached value? */ | |
1156 | if (decl == NULL_TREE) | |
1157 | { | |
1158 | fn_type = M32R_FUNCTION_UNKNOWN; | |
1159 | last_fn = NULL_TREE; | |
1160 | return fn_type; | |
1161 | } | |
1162 | ||
1163 | if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN) | |
1164 | return fn_type; | |
1165 | ||
1166 | /* Compute function type. */ | |
91d231cb | 1167 | fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE |
8c5ca3b9 DE |
1168 | ? M32R_FUNCTION_INTERRUPT |
1169 | : M32R_FUNCTION_NORMAL); | |
1170 | ||
1171 | last_fn = decl; | |
1172 | return fn_type; | |
1173 | } | |
1174 | \f/* Function prologue/epilogue handlers. */ | |
1175 | ||
1176 | /* M32R stack frames look like: | |
1177 | ||
1178 | Before call After call | |
1179 | +-----------------------+ +-----------------------+ | |
1180 | | | | | | |
1181 | high | local variables, | | local variables, | | |
1182 | mem | reg save area, etc. | | reg save area, etc. | | |
1183 | | | | | | |
1184 | +-----------------------+ +-----------------------+ | |
1185 | | | | | | |
1186 | | arguments on stack. | | arguments on stack. | | |
1187 | | | | | | |
1188 | SP+0->+-----------------------+ +-----------------------+ | |
1189 | | reg parm save area, | | |
e2265be0 KK |
1190 | | only created for | |
1191 | | variable argument | | |
1192 | | functions | | |
8c5ca3b9 DE |
1193 | +-----------------------+ |
1194 | | previous frame ptr | | |
e2265be0 KK |
1195 | +-----------------------+ |
1196 | | | | |
1197 | | register save area | | |
1198 | | | | |
8c5ca3b9 | 1199 | +-----------------------+ |
e2265be0 KK |
1200 | | return address | |
1201 | +-----------------------+ | |
1202 | | | | |
1203 | | local variables | | |
1204 | | | | |
1205 | +-----------------------+ | |
1206 | | | | |
1207 | | alloca allocations | | |
1208 | | | | |
1209 | +-----------------------+ | |
1210 | | | | |
1211 | low | arguments on stack | | |
1212 | memory | | | |
1213 | SP+0->+-----------------------+ | |
8c5ca3b9 DE |
1214 | |
1215 | Notes: | |
1216 | 1) The "reg parm save area" does not exist for non variable argument fns. | |
1217 | 2) The "reg parm save area" can be eliminated completely if we saved regs | |
1218 | containing anonymous args separately but that complicates things too | |
1219 | much (so it's not done). | |
1220 | 3) The return address is saved after the register save area so as to have as | |
1f92da87 | 1221 | many insns as possible between the restoration of `lr' and the `jmp lr'. */ |
8c5ca3b9 DE |
1222 | |
1223 | /* Structure to be filled in by m32r_compute_frame_size with register | |
1224 | save masks, and offsets for the current function. */ | |
1225 | struct m32r_frame_info | |
1226 | { | |
1f92da87 NC |
1227 | unsigned int total_size; /* # bytes that the entire frame takes up. */ |
1228 | unsigned int extra_size; /* # bytes of extra stuff. */ | |
1229 | unsigned int pretend_size; /* # bytes we push and pretend caller did. */ | |
1230 | unsigned int args_size; /* # bytes that outgoing arguments take up. */ | |
1231 | unsigned int reg_size; /* # bytes needed to store regs. */ | |
1232 | unsigned int var_size; /* # bytes that variables take up. */ | |
1233 | unsigned int gmask; /* Mask of saved gp registers. */ | |
1234 | unsigned int save_fp; /* Nonzero if fp must be saved. */ | |
1235 | unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */ | |
1236 | int initialized; /* Nonzero if frame size already calculated. */ | |
8c5ca3b9 DE |
1237 | }; |
1238 | ||
1239 | /* Current frame information calculated by m32r_compute_frame_size. */ | |
1240 | static struct m32r_frame_info current_frame_info; | |
1241 | ||
1242 | /* Zero structure to initialize current_frame_info. */ | |
1243 | static struct m32r_frame_info zero_frame_info; | |
1244 | ||
1245 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
1f92da87 | 1246 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) |
8c5ca3b9 DE |
1247 | |
1248 | /* Tell prologue and epilogue if register REGNO should be saved / restored. | |
1249 | The return address and frame pointer are treated separately. | |
1250 | Don't consider them here. */ | |
1251 | #define MUST_SAVE_REGISTER(regno, interrupt_p) \ | |
69a53ee8 | 1252 | ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \ |
6fb5fa3c | 1253 | && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p))) |
8c5ca3b9 | 1254 | |
6fb5fa3c DB |
1255 | #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM)) |
1256 | #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || current_function_profile) | |
8c5ca3b9 | 1257 | |
1f92da87 NC |
1258 | #define SHORT_INSN_SIZE 2 /* Size of small instructions. */ |
1259 | #define LONG_INSN_SIZE 4 /* Size of long instructions. */ | |
2b7972b0 | 1260 | |
8c5ca3b9 DE |
1261 | /* Return the bytes needed to compute the frame pointer from the current |
1262 | stack pointer. | |
1263 | ||
1264 | SIZE is the size needed for local variables. */ | |
1265 | ||
1266 | unsigned int | |
1f92da87 | 1267 | m32r_compute_frame_size (int size) /* # of var. bytes allocated. */ |
8c5ca3b9 | 1268 | { |
e2265be0 | 1269 | unsigned int regno; |
8c5ca3b9 | 1270 | unsigned int total_size, var_size, args_size, pretend_size, extra_size; |
5b8ae21f | 1271 | unsigned int reg_size, frame_size; |
8c5ca3b9 DE |
1272 | unsigned int gmask; |
1273 | enum m32r_function_type fn_type; | |
1274 | int interrupt_p; | |
cdc9bfe6 KI |
1275 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table |
1276 | | current_function_profile); | |
8c5ca3b9 DE |
1277 | |
1278 | var_size = M32R_STACK_ALIGN (size); | |
1279 | args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size); | |
1280 | pretend_size = current_function_pretend_args_size; | |
1281 | extra_size = FIRST_PARM_OFFSET (0); | |
1282 | total_size = extra_size + pretend_size + args_size + var_size; | |
1283 | reg_size = 0; | |
1284 | gmask = 0; | |
1285 | ||
1286 | /* See if this is an interrupt handler. Call used registers must be saved | |
1287 | for them too. */ | |
1288 | fn_type = m32r_compute_function_type (current_function_decl); | |
1289 | interrupt_p = M32R_INTERRUPT_P (fn_type); | |
1290 | ||
1291 | /* Calculate space needed for registers. */ | |
8c5ca3b9 DE |
1292 | for (regno = 0; regno < M32R_MAX_INT_REGS; regno++) |
1293 | { | |
ad126521 KI |
1294 | if (MUST_SAVE_REGISTER (regno, interrupt_p) |
1295 | || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) | |
8c5ca3b9 DE |
1296 | { |
1297 | reg_size += UNITS_PER_WORD; | |
1298 | gmask |= 1 << regno; | |
1299 | } | |
1300 | } | |
1301 | ||
1302 | current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER; | |
ad126521 | 1303 | current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used; |
8c5ca3b9 DE |
1304 | |
1305 | reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr) | |
1306 | * UNITS_PER_WORD); | |
1307 | total_size += reg_size; | |
1308 | ||
efbbf34f | 1309 | /* ??? Not sure this is necessary, and I don't think the epilogue |
8c5ca3b9 DE |
1310 | handler will do the right thing if this changes total_size. */ |
1311 | total_size = M32R_STACK_ALIGN (total_size); | |
1312 | ||
2b7972b0 MM |
1313 | frame_size = total_size - (pretend_size + reg_size); |
1314 | ||
8c5ca3b9 DE |
1315 | /* Save computed information. */ |
1316 | current_frame_info.total_size = total_size; | |
1317 | current_frame_info.extra_size = extra_size; | |
1318 | current_frame_info.pretend_size = pretend_size; | |
1319 | current_frame_info.var_size = var_size; | |
1320 | current_frame_info.args_size = args_size; | |
1321 | current_frame_info.reg_size = reg_size; | |
1322 | current_frame_info.gmask = gmask; | |
1323 | current_frame_info.initialized = reload_completed; | |
1324 | ||
1325 | /* Ok, we're done. */ | |
1326 | return total_size; | |
1327 | } | |
1328 | \f | |
ad126521 KI |
1329 | /* The table we use to reference PIC data. */ |
1330 | static rtx global_offset_table; | |
e2265be0 | 1331 | |
7b14411a KI |
1332 | static void |
1333 | m32r_reload_lr (rtx sp, int size) | |
1334 | { | |
1335 | rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); | |
1336 | ||
1337 | if (size == 0) | |
e2265be0 | 1338 | emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp))); |
2a6a63c1 | 1339 | else if (size < 32768) |
e2265be0 KK |
1340 | emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, |
1341 | gen_rtx_PLUS (Pmode, sp, | |
1342 | GEN_INT (size))))); | |
7b14411a | 1343 | else |
e2265be0 | 1344 | { |
7b14411a KI |
1345 | rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); |
1346 | ||
1347 | emit_insn (gen_movsi (tmp, GEN_INT (size))); | |
1348 | emit_insn (gen_addsi3 (tmp, tmp, sp)); | |
e2265be0 | 1349 | emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp))); |
7b14411a KI |
1350 | } |
1351 | ||
1352 | emit_insn (gen_rtx_USE (VOIDmode, lr)); | |
1353 | } | |
1354 | ||
ad126521 KI |
1355 | void |
1356 | m32r_load_pic_register (void) | |
1357 | { | |
1358 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
1359 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, | |
aeba8f80 | 1360 | GEN_INT (TARGET_MODEL_SMALL))); |
e2265be0 | 1361 | |
ad126521 KI |
1362 | /* Need to emit this whether or not we obey regdecls, |
1363 | since setjmp/longjmp can cause life info to screw up. */ | |
1364 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
1365 | } | |
1366 | ||
5b8ae21f | 1367 | /* Expand the m32r prologue as a series of insns. */ |
8c5ca3b9 DE |
1368 | |
1369 | void | |
1f92da87 | 1370 | m32r_expand_prologue (void) |
8c5ca3b9 DE |
1371 | { |
1372 | int regno; | |
5b8ae21f | 1373 | int frame_size; |
56e2e762 | 1374 | unsigned int gmask; |
cdc9bfe6 KI |
1375 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table |
1376 | | current_function_profile); | |
8c5ca3b9 | 1377 | |
5b8ae21f MM |
1378 | if (! current_frame_info.initialized) |
1379 | m32r_compute_frame_size (get_frame_size ()); | |
2b7972b0 | 1380 | |
5b8ae21f | 1381 | gmask = current_frame_info.gmask; |
8c5ca3b9 DE |
1382 | |
1383 | /* These cases shouldn't happen. Catch them now. */ | |
75c3cfba | 1384 | gcc_assert (current_frame_info.total_size || !gmask); |
8c5ca3b9 | 1385 | |
8c5ca3b9 DE |
1386 | /* Allocate space for register arguments if this is a variadic function. */ |
1387 | if (current_frame_info.pretend_size != 0) | |
737e7965 JW |
1388 | { |
1389 | /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives | |
1390 | the wrong result on a 64-bit host. */ | |
1391 | HOST_WIDE_INT pretend_size = current_frame_info.pretend_size; | |
1392 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1393 | stack_pointer_rtx, | |
1394 | GEN_INT (-pretend_size))); | |
1395 | } | |
8c5ca3b9 DE |
1396 | |
1397 | /* Save any registers we need to and set up fp. */ | |
8c5ca3b9 | 1398 | if (current_frame_info.save_fp) |
5b8ae21f | 1399 | emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx)); |
8c5ca3b9 DE |
1400 | |
1401 | gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK); | |
1402 | ||
1403 | /* Save any needed call-saved regs (and call-used if this is an | |
1404 | interrupt handler). */ | |
1405 | for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno) | |
1406 | { | |
1407 | if ((gmask & (1 << regno)) != 0) | |
5b8ae21f MM |
1408 | emit_insn (gen_movsi_push (stack_pointer_rtx, |
1409 | gen_rtx_REG (Pmode, regno))); | |
8c5ca3b9 DE |
1410 | } |
1411 | ||
1412 | if (current_frame_info.save_lr) | |
5b8ae21f MM |
1413 | emit_insn (gen_movsi_push (stack_pointer_rtx, |
1414 | gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); | |
8c5ca3b9 DE |
1415 | |
1416 | /* Allocate the stack frame. */ | |
5b8ae21f MM |
1417 | frame_size = (current_frame_info.total_size |
1418 | - (current_frame_info.pretend_size | |
1419 | + current_frame_info.reg_size)); | |
1420 | ||
8c5ca3b9 | 1421 | if (frame_size == 0) |
1f92da87 | 1422 | ; /* Nothing to do. */ |
8c5ca3b9 | 1423 | else if (frame_size <= 32768) |
5b8ae21f MM |
1424 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
1425 | GEN_INT (-frame_size))); | |
8c5ca3b9 | 1426 | else |
5b8ae21f MM |
1427 | { |
1428 | rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1f92da87 | 1429 | |
5b8ae21f MM |
1430 | emit_insn (gen_movsi (tmp, GEN_INT (frame_size))); |
1431 | emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp)); | |
1432 | } | |
8c5ca3b9 DE |
1433 | |
1434 | if (frame_pointer_needed) | |
5b8ae21f MM |
1435 | emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); |
1436 | ||
70f4f91c | 1437 | if (current_function_profile) |
ad126521 KI |
1438 | /* Push lr for mcount (form_pc, x). */ |
1439 | emit_insn (gen_movsi_push (stack_pointer_rtx, | |
1440 | gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); | |
e2265be0 | 1441 | |
ad126521 | 1442 | if (pic_reg_used) |
7b14411a KI |
1443 | { |
1444 | m32r_load_pic_register (); | |
1445 | m32r_reload_lr (stack_pointer_rtx, | |
1446 | (current_function_profile ? 0 : frame_size)); | |
1447 | } | |
ad126521 KI |
1448 | |
1449 | if (current_function_profile && !pic_reg_used) | |
5b8ae21f MM |
1450 | emit_insn (gen_blockage ()); |
1451 | } | |
1452 | ||
1453 | \f | |
1454 | /* Set up the stack and frame pointer (if desired) for the function. | |
1455 | Note, if this is changed, you need to mirror the changes in | |
1456 | m32r_compute_frame_size which calculates the prolog size. */ | |
1457 | ||
08c148a8 | 1458 | static void |
1f92da87 | 1459 | m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size) |
5b8ae21f MM |
1460 | { |
1461 | enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl); | |
1462 | ||
1463 | /* If this is an interrupt handler, mark it as such. */ | |
1464 | if (M32R_INTERRUPT_P (fn_type)) | |
1f92da87 | 1465 | fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START); |
5b8ae21f MM |
1466 | |
1467 | if (! current_frame_info.initialized) | |
1468 | m32r_compute_frame_size (size); | |
8c5ca3b9 | 1469 | |
5b8ae21f MM |
1470 | /* This is only for the human reader. */ |
1471 | fprintf (file, | |
1472 | "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n", | |
1473 | ASM_COMMENT_START, | |
1474 | current_frame_info.var_size, | |
1475 | current_frame_info.reg_size / 4, | |
1476 | current_frame_info.args_size, | |
1477 | current_frame_info.extra_size); | |
8c5ca3b9 DE |
1478 | } |
1479 | \f | |
e2265be0 | 1480 | /* Output RTL to pop register REGNO from the stack. */ |
8c5ca3b9 | 1481 | |
08c148a8 | 1482 | static void |
e2265be0 KK |
1483 | pop (int regno) |
1484 | { | |
1485 | rtx x; | |
1486 | ||
1487 | x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno), | |
1488 | stack_pointer_rtx)); | |
1489 | REG_NOTES (x) | |
1490 | = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0); | |
1491 | } | |
1492 | ||
1493 | /* Expand the m32r epilogue as a series of insns. */ | |
1494 | ||
1495 | void | |
1496 | m32r_expand_epilogue (void) | |
8c5ca3b9 DE |
1497 | { |
1498 | int regno; | |
1499 | int noepilogue = FALSE; | |
1500 | int total_size; | |
8c5ca3b9 | 1501 | |
75c3cfba | 1502 | gcc_assert (current_frame_info.initialized); |
8c5ca3b9 DE |
1503 | total_size = current_frame_info.total_size; |
1504 | ||
1505 | if (total_size == 0) | |
1506 | { | |
1507 | rtx insn = get_last_insn (); | |
1508 | ||
1509 | /* If the last insn was a BARRIER, we don't have to write any code | |
1510 | because a jump (aka return) was put there. */ | |
e2265be0 | 1511 | if (insn && GET_CODE (insn) == NOTE) |
8c5ca3b9 DE |
1512 | insn = prev_nonnote_insn (insn); |
1513 | if (insn && GET_CODE (insn) == BARRIER) | |
1514 | noepilogue = TRUE; | |
1515 | } | |
1516 | ||
1517 | if (!noepilogue) | |
1518 | { | |
8c5ca3b9 DE |
1519 | unsigned int var_size = current_frame_info.var_size; |
1520 | unsigned int args_size = current_frame_info.args_size; | |
1521 | unsigned int gmask = current_frame_info.gmask; | |
1522 | int can_trust_sp_p = !current_function_calls_alloca; | |
e2265be0 KK |
1523 | |
1524 | if (flag_exceptions) | |
1525 | emit_insn (gen_blockage ()); | |
8c5ca3b9 DE |
1526 | |
1527 | /* The first thing to do is point the sp at the bottom of the register | |
1528 | save area. */ | |
1529 | if (can_trust_sp_p) | |
1530 | { | |
1531 | unsigned int reg_offset = var_size + args_size; | |
e2265be0 | 1532 | |
8c5ca3b9 | 1533 | if (reg_offset == 0) |
1f92da87 | 1534 | ; /* Nothing to do. */ |
8c5ca3b9 | 1535 | else if (reg_offset < 32768) |
e2265be0 KK |
1536 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
1537 | GEN_INT (reg_offset))); | |
6a7b00ad | 1538 | else |
e2265be0 KK |
1539 | { |
1540 | rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1541 | ||
1542 | emit_insn (gen_movsi (tmp, GEN_INT (reg_offset))); | |
1543 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1544 | tmp)); | |
1545 | } | |
8c5ca3b9 DE |
1546 | } |
1547 | else if (frame_pointer_needed) | |
1548 | { | |
1549 | unsigned int reg_offset = var_size + args_size; | |
1f92da87 | 1550 | |
8c5ca3b9 | 1551 | if (reg_offset == 0) |
e2265be0 | 1552 | emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); |
8c5ca3b9 | 1553 | else if (reg_offset < 32768) |
e2265be0 KK |
1554 | emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, |
1555 | GEN_INT (reg_offset))); | |
6a7b00ad | 1556 | else |
e2265be0 KK |
1557 | { |
1558 | rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1559 | ||
1560 | emit_insn (gen_movsi (tmp, GEN_INT (reg_offset))); | |
1561 | emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); | |
1562 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1563 | tmp)); | |
1564 | } | |
8c5ca3b9 DE |
1565 | } |
1566 | else | |
75c3cfba | 1567 | gcc_unreachable (); |
8c5ca3b9 DE |
1568 | |
1569 | if (current_frame_info.save_lr) | |
e2265be0 | 1570 | pop (RETURN_ADDR_REGNUM); |
8c5ca3b9 DE |
1571 | |
1572 | /* Restore any saved registers, in reverse order of course. */ | |
1573 | gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK); | |
1574 | for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno) | |
1575 | { | |
1576 | if ((gmask & (1L << regno)) != 0) | |
e2265be0 | 1577 | pop (regno); |
8c5ca3b9 DE |
1578 | } |
1579 | ||
1580 | if (current_frame_info.save_fp) | |
e2265be0 | 1581 | pop (FRAME_POINTER_REGNUM); |
8c5ca3b9 DE |
1582 | |
1583 | /* Remove varargs area if present. */ | |
8c5ca3b9 | 1584 | if (current_frame_info.pretend_size != 0) |
e2265be0 KK |
1585 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
1586 | GEN_INT (current_frame_info.pretend_size))); | |
1587 | ||
1588 | emit_insn (gen_blockage ()); | |
8c5ca3b9 | 1589 | } |
e2265be0 KK |
1590 | } |
1591 | ||
1592 | /* Do any necessary cleanup after a function to restore stack, frame, | |
1593 | and regs. */ | |
8c5ca3b9 | 1594 | |
e2265be0 KK |
1595 | static void |
1596 | m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED, | |
1597 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
1598 | { | |
8c5ca3b9 DE |
1599 | /* Reset state info for each function. */ |
1600 | current_frame_info = zero_frame_info; | |
1601 | m32r_compute_function_type (NULL_TREE); | |
1602 | } | |
56e2e762 | 1603 | \f |
a0ab749a | 1604 | /* Return nonzero if this function is known to have a null or 1 instruction |
56e2e762 NC |
1605 | epilogue. */ |
1606 | ||
1607 | int | |
1f92da87 | 1608 | direct_return (void) |
56e2e762 NC |
1609 | { |
1610 | if (!reload_completed) | |
1611 | return FALSE; | |
1612 | ||
e2265be0 KK |
1613 | if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl))) |
1614 | return FALSE; | |
1615 | ||
56e2e762 NC |
1616 | if (! current_frame_info.initialized) |
1617 | m32r_compute_frame_size (get_frame_size ()); | |
1618 | ||
e2265be0 | 1619 | return current_frame_info.total_size == 0; |
56e2e762 NC |
1620 | } |
1621 | ||
8c5ca3b9 | 1622 | \f |
1f92da87 | 1623 | /* PIC. */ |
8c5ca3b9 | 1624 | |
ad126521 KI |
1625 | int |
1626 | m32r_legitimate_pic_operand_p (rtx x) | |
1627 | { | |
1628 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1629 | return 0; | |
e2265be0 | 1630 | |
ad126521 KI |
1631 | if (GET_CODE (x) == CONST |
1632 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1633 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1634 | || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF) | |
1635 | && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) | |
1636 | return 0; | |
e2265be0 | 1637 | |
ad126521 KI |
1638 | return 1; |
1639 | } | |
1640 | ||
1641 | rtx | |
1642 | m32r_legitimize_pic_address (rtx orig, rtx reg) | |
1643 | { | |
1644 | #ifdef DEBUG_PIC | |
1645 | printf("m32r_legitimize_pic_address()\n"); | |
1646 | #endif | |
1647 | ||
1648 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1649 | { | |
1650 | rtx pic_ref, address; | |
1651 | rtx insn; | |
1652 | int subregs = 0; | |
1653 | ||
1654 | if (reg == 0) | |
1655 | { | |
75c3cfba NS |
1656 | gcc_assert (!reload_in_progress && !reload_completed); |
1657 | reg = gen_reg_rtx (Pmode); | |
ad126521 KI |
1658 | |
1659 | subregs = 1; | |
1660 | } | |
1661 | ||
1662 | if (subregs) | |
1663 | address = gen_reg_rtx (Pmode); | |
1664 | else | |
1665 | address = reg; | |
1666 | ||
c331bf08 KI |
1667 | current_function_uses_pic_offset_table = 1; |
1668 | ||
1669 | if (GET_CODE (orig) == LABEL_REF | |
1670 | || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) | |
1671 | { | |
1672 | emit_insn (gen_gotoff_load_addr (reg, orig)); | |
1673 | emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx)); | |
1674 | return reg; | |
1675 | } | |
1676 | ||
ad126521 KI |
1677 | emit_insn (gen_pic_load_addr (address, orig)); |
1678 | ||
1679 | emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx)); | |
542a8afa | 1680 | pic_ref = gen_const_mem (Pmode, address); |
ad126521 | 1681 | insn = emit_move_insn (reg, pic_ref); |
ad126521 KI |
1682 | #if 0 |
1683 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
1684 | by loop. */ | |
bd94cb6e | 1685 | set_unique_reg_note (insn, REG_EQUAL, orig); |
ad126521 KI |
1686 | #endif |
1687 | return reg; | |
1688 | } | |
1689 | else if (GET_CODE (orig) == CONST) | |
1690 | { | |
1691 | rtx base, offset; | |
1692 | ||
1693 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
1694 | && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx) | |
1695 | return orig; | |
1696 | ||
1697 | if (reg == 0) | |
1698 | { | |
75c3cfba NS |
1699 | gcc_assert (!reload_in_progress && !reload_completed); |
1700 | reg = gen_reg_rtx (Pmode); | |
ad126521 KI |
1701 | } |
1702 | ||
1703 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
1704 | { | |
1705 | base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg); | |
1706 | if (base == reg) | |
1707 | offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX); | |
1708 | else | |
1709 | offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg); | |
1710 | } | |
1711 | else | |
1712 | return orig; | |
1713 | ||
1714 | if (GET_CODE (offset) == CONST_INT) | |
1715 | { | |
1716 | if (INT16_P (INTVAL (offset))) | |
1717 | return plus_constant (base, INTVAL (offset)); | |
ad126521 | 1718 | else |
75c3cfba NS |
1719 | { |
1720 | gcc_assert (! reload_in_progress && ! reload_completed); | |
1721 | offset = force_reg (Pmode, offset); | |
1722 | } | |
ad126521 KI |
1723 | } |
1724 | ||
f1c25d3b | 1725 | return gen_rtx_PLUS (Pmode, base, offset); |
ad126521 KI |
1726 | } |
1727 | ||
1728 | return orig; | |
1729 | } | |
8c5ca3b9 DE |
1730 | \f |
1731 | /* Nested function support. */ | |
1732 | ||
1733 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1734 | FNADDR is an RTX for the address of the function's pure code. | |
1735 | CXT is an RTX for the static chain value for the function. */ | |
1736 | ||
1737 | void | |
1f92da87 NC |
1738 | m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED, |
1739 | rtx fnaddr ATTRIBUTE_UNUSED, | |
1740 | rtx cxt ATTRIBUTE_UNUSED) | |
8c5ca3b9 DE |
1741 | { |
1742 | } | |
1743 | \f | |
1bc7c5b6 | 1744 | static void |
1f92da87 | 1745 | m32r_file_start (void) |
8c5ca3b9 | 1746 | { |
1bc7c5b6 ZW |
1747 | default_file_start (); |
1748 | ||
8c5ca3b9 | 1749 | if (flag_verbose_asm) |
1bc7c5b6 | 1750 | fprintf (asm_out_file, |
307b599c | 1751 | "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
8c5ca3b9 | 1752 | ASM_COMMENT_START, g_switch_value); |
ad126521 KI |
1753 | |
1754 | if (TARGET_LITTLE_ENDIAN) | |
1755 | fprintf (asm_out_file, "\t.little\n"); | |
8c5ca3b9 DE |
1756 | } |
1757 | \f | |
1758 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1759 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1760 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1761 | ||
1762 | void | |
1f92da87 | 1763 | m32r_print_operand (FILE * file, rtx x, int code) |
8c5ca3b9 | 1764 | { |
5b8ae21f MM |
1765 | rtx addr; |
1766 | ||
8c5ca3b9 DE |
1767 | switch (code) |
1768 | { | |
d2a73f8e NC |
1769 | /* The 's' and 'p' codes are used by output_block_move() to |
1770 | indicate post-increment 's'tores and 'p're-increment loads. */ | |
1771 | case 's': | |
1772 | if (GET_CODE (x) == REG) | |
1773 | fprintf (file, "@+%s", reg_names [REGNO (x)]); | |
1774 | else | |
a52453cc | 1775 | output_operand_lossage ("invalid operand to %%s code"); |
d2a73f8e | 1776 | return; |
e2265be0 | 1777 | |
d2a73f8e NC |
1778 | case 'p': |
1779 | if (GET_CODE (x) == REG) | |
1780 | fprintf (file, "@%s+", reg_names [REGNO (x)]); | |
1781 | else | |
a52453cc | 1782 | output_operand_lossage ("invalid operand to %%p code"); |
d2a73f8e NC |
1783 | return; |
1784 | ||
8c5ca3b9 DE |
1785 | case 'R' : |
1786 | /* Write second word of DImode or DFmode reference, | |
1787 | register or memory. */ | |
1788 | if (GET_CODE (x) == REG) | |
1789 | fputs (reg_names[REGNO (x)+1], file); | |
1790 | else if (GET_CODE (x) == MEM) | |
1791 | { | |
1792 | fprintf (file, "@("); | |
1793 | /* Handle possible auto-increment. Since it is pre-increment and | |
1794 | we have already done it, we can just use an offset of four. */ | |
1795 | /* ??? This is taken from rs6000.c I think. I don't think it is | |
1796 | currently necessary, but keep it around. */ | |
1797 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1798 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1799 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); | |
1800 | else | |
1801 | output_address (plus_constant (XEXP (x, 0), 4)); | |
1802 | fputc (')', file); | |
1803 | } | |
1804 | else | |
a52453cc | 1805 | output_operand_lossage ("invalid operand to %%R code"); |
8c5ca3b9 DE |
1806 | return; |
1807 | ||
1f92da87 NC |
1808 | case 'H' : /* High word. */ |
1809 | case 'L' : /* Low word. */ | |
8c5ca3b9 DE |
1810 | if (GET_CODE (x) == REG) |
1811 | { | |
1f92da87 | 1812 | /* L = least significant word, H = most significant word. */ |
8c5ca3b9 DE |
1813 | if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L')) |
1814 | fputs (reg_names[REGNO (x)], file); | |
1815 | else | |
1816 | fputs (reg_names[REGNO (x)+1], file); | |
1817 | } | |
1818 | else if (GET_CODE (x) == CONST_INT | |
1819 | || GET_CODE (x) == CONST_DOUBLE) | |
1820 | { | |
1821 | rtx first, second; | |
1822 | ||
1823 | split_double (x, &first, &second); | |
61f3b78f | 1824 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
8c5ca3b9 DE |
1825 | code == 'L' ? INTVAL (first) : INTVAL (second)); |
1826 | } | |
1827 | else | |
a52453cc | 1828 | output_operand_lossage ("invalid operand to %%H/%%L code"); |
8c5ca3b9 DE |
1829 | return; |
1830 | ||
1831 | case 'A' : | |
1832 | { | |
8c5ca3b9 DE |
1833 | char str[30]; |
1834 | ||
1835 | if (GET_CODE (x) != CONST_DOUBLE | |
1836 | || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT) | |
c725bd79 | 1837 | fatal_insn ("bad insn for 'A'", x); |
da6eec72 RH |
1838 | |
1839 | real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1); | |
8c5ca3b9 DE |
1840 | fprintf (file, "%s", str); |
1841 | return; | |
1842 | } | |
1843 | ||
1f92da87 NC |
1844 | case 'B' : /* Bottom half. */ |
1845 | case 'T' : /* Top half. */ | |
8c5ca3b9 DE |
1846 | /* Output the argument to a `seth' insn (sets the Top half-word). |
1847 | For constants output arguments to a seth/or3 pair to set Top and | |
1848 | Bottom halves. For symbols output arguments to a seth/add3 pair to | |
1849 | set Top and Bottom halves. The difference exists because for | |
1850 | constants seth/or3 is more readable but for symbols we need to use | |
85f65093 | 1851 | the same scheme as `ld' and `st' insns (16-bit addend is signed). */ |
8c5ca3b9 DE |
1852 | switch (GET_CODE (x)) |
1853 | { | |
1854 | case CONST_INT : | |
1855 | case CONST_DOUBLE : | |
1856 | { | |
1857 | rtx first, second; | |
1858 | ||
1859 | split_double (x, &first, &second); | |
1860 | x = WORDS_BIG_ENDIAN ? second : first; | |
89e6b702 | 1861 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
8c5ca3b9 DE |
1862 | (code == 'B' |
1863 | ? INTVAL (x) & 0xffff | |
1864 | : (INTVAL (x) >> 16) & 0xffff)); | |
1865 | } | |
1866 | return; | |
1867 | case CONST : | |
1868 | case SYMBOL_REF : | |
1869 | if (code == 'B' | |
1870 | && small_data_operand (x, VOIDmode)) | |
1871 | { | |
1872 | fputs ("sda(", file); | |
1873 | output_addr_const (file, x); | |
1874 | fputc (')', file); | |
1875 | return; | |
1876 | } | |
1877 | /* fall through */ | |
1878 | case LABEL_REF : | |
1879 | fputs (code == 'T' ? "shigh(" : "low(", file); | |
1880 | output_addr_const (file, x); | |
1881 | fputc (')', file); | |
1882 | return; | |
1883 | default : | |
a52453cc | 1884 | output_operand_lossage ("invalid operand to %%T/%%B code"); |
8c5ca3b9 DE |
1885 | return; |
1886 | } | |
1887 | break; | |
1888 | ||
1889 | case 'U' : | |
2e076ddf | 1890 | /* ??? wip */ |
8c5ca3b9 DE |
1891 | /* Output a load/store with update indicator if appropriate. */ |
1892 | if (GET_CODE (x) == MEM) | |
1893 | { | |
1894 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1895 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1896 | fputs (".a", file); | |
1897 | } | |
1898 | else | |
a52453cc | 1899 | output_operand_lossage ("invalid operand to %%U code"); |
8c5ca3b9 DE |
1900 | return; |
1901 | ||
1902 | case 'N' : | |
1903 | /* Print a constant value negated. */ | |
1904 | if (GET_CODE (x) == CONST_INT) | |
1905 | output_addr_const (file, GEN_INT (- INTVAL (x))); | |
1906 | else | |
a52453cc | 1907 | output_operand_lossage ("invalid operand to %%N code"); |
8c5ca3b9 DE |
1908 | return; |
1909 | ||
4d6c607f DE |
1910 | case 'X' : |
1911 | /* Print a const_int in hex. Used in comments. */ | |
1912 | if (GET_CODE (x) == CONST_INT) | |
89e6b702 | 1913 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
4d6c607f DE |
1914 | return; |
1915 | ||
8c5ca3b9 DE |
1916 | case '#' : |
1917 | fputs (IMMEDIATE_PREFIX, file); | |
1918 | return; | |
1919 | ||
8c5ca3b9 DE |
1920 | case 0 : |
1921 | /* Do nothing special. */ | |
1922 | break; | |
1923 | ||
1924 | default : | |
1925 | /* Unknown flag. */ | |
1926 | output_operand_lossage ("invalid operand output code"); | |
1927 | } | |
1928 | ||
1929 | switch (GET_CODE (x)) | |
1930 | { | |
1931 | case REG : | |
1932 | fputs (reg_names[REGNO (x)], file); | |
1933 | break; | |
1934 | ||
1935 | case MEM : | |
5b8ae21f MM |
1936 | addr = XEXP (x, 0); |
1937 | if (GET_CODE (addr) == PRE_INC) | |
1938 | { | |
1939 | if (GET_CODE (XEXP (addr, 0)) != REG) | |
c725bd79 | 1940 | fatal_insn ("pre-increment address is not a register", x); |
5b8ae21f MM |
1941 | |
1942 | fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]); | |
1943 | } | |
1944 | else if (GET_CODE (addr) == PRE_DEC) | |
1945 | { | |
1946 | if (GET_CODE (XEXP (addr, 0)) != REG) | |
c725bd79 | 1947 | fatal_insn ("pre-decrement address is not a register", x); |
5b8ae21f MM |
1948 | |
1949 | fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]); | |
1950 | } | |
1951 | else if (GET_CODE (addr) == POST_INC) | |
1952 | { | |
1953 | if (GET_CODE (XEXP (addr, 0)) != REG) | |
c725bd79 | 1954 | fatal_insn ("post-increment address is not a register", x); |
5b8ae21f MM |
1955 | |
1956 | fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]); | |
1957 | } | |
8c5ca3b9 | 1958 | else |
5b8ae21f MM |
1959 | { |
1960 | fputs ("@(", file); | |
1961 | output_address (XEXP (x, 0)); | |
1962 | fputc (')', file); | |
1963 | } | |
8c5ca3b9 DE |
1964 | break; |
1965 | ||
1966 | case CONST_DOUBLE : | |
1967 | /* We handle SFmode constants here as output_addr_const doesn't. */ | |
1968 | if (GET_MODE (x) == SFmode) | |
1969 | { | |
1970 | REAL_VALUE_TYPE d; | |
1971 | long l; | |
1972 | ||
1973 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
1974 | REAL_VALUE_TO_TARGET_SINGLE (d, l); | |
1975 | fprintf (file, "0x%08lx", l); | |
1976 | break; | |
1977 | } | |
1978 | ||
1979 | /* Fall through. Let output_addr_const deal with it. */ | |
1980 | ||
1981 | default : | |
1982 | output_addr_const (file, x); | |
1983 | break; | |
1984 | } | |
1985 | } | |
1986 | ||
1987 | /* Print a memory address as an operand to reference that memory location. */ | |
1988 | ||
1989 | void | |
1f92da87 | 1990 | m32r_print_operand_address (FILE * file, rtx addr) |
8c5ca3b9 | 1991 | { |
1f92da87 NC |
1992 | rtx base; |
1993 | rtx index = 0; | |
1994 | int offset = 0; | |
8c5ca3b9 DE |
1995 | |
1996 | switch (GET_CODE (addr)) | |
1997 | { | |
1998 | case REG : | |
1999 | fputs (reg_names[REGNO (addr)], file); | |
2000 | break; | |
2001 | ||
2002 | case PLUS : | |
2003 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) | |
2004 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); | |
2005 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2006 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); | |
2007 | else | |
2008 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
2009 | if (GET_CODE (base) == REG) | |
2010 | { | |
2011 | /* Print the offset first (if present) to conform to the manual. */ | |
2012 | if (index == 0) | |
2013 | { | |
2014 | if (offset != 0) | |
2015 | fprintf (file, "%d,", offset); | |
2016 | fputs (reg_names[REGNO (base)], file); | |
2017 | } | |
2018 | /* The chip doesn't support this, but left in for generality. */ | |
2019 | else if (GET_CODE (index) == REG) | |
2020 | fprintf (file, "%s,%s", | |
2021 | reg_names[REGNO (base)], reg_names[REGNO (index)]); | |
2022 | /* Not sure this can happen, but leave in for now. */ | |
2023 | else if (GET_CODE (index) == SYMBOL_REF) | |
2024 | { | |
2025 | output_addr_const (file, index); | |
2026 | fputc (',', file); | |
2027 | fputs (reg_names[REGNO (base)], file); | |
2028 | } | |
2029 | else | |
c725bd79 | 2030 | fatal_insn ("bad address", addr); |
8c5ca3b9 DE |
2031 | } |
2032 | else if (GET_CODE (base) == LO_SUM) | |
2033 | { | |
75c3cfba | 2034 | gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG); |
8c5ca3b9 DE |
2035 | if (small_data_operand (XEXP (base, 1), VOIDmode)) |
2036 | fputs ("sda(", file); | |
2037 | else | |
2038 | fputs ("low(", file); | |
2039 | output_addr_const (file, plus_constant (XEXP (base, 1), offset)); | |
2040 | fputs ("),", file); | |
2041 | fputs (reg_names[REGNO (XEXP (base, 0))], file); | |
2042 | } | |
2043 | else | |
c725bd79 | 2044 | fatal_insn ("bad address", addr); |
8c5ca3b9 DE |
2045 | break; |
2046 | ||
2047 | case LO_SUM : | |
2048 | if (GET_CODE (XEXP (addr, 0)) != REG) | |
c725bd79 | 2049 | fatal_insn ("lo_sum not of register", addr); |
8c5ca3b9 DE |
2050 | if (small_data_operand (XEXP (addr, 1), VOIDmode)) |
2051 | fputs ("sda(", file); | |
2052 | else | |
2053 | fputs ("low(", file); | |
2054 | output_addr_const (file, XEXP (addr, 1)); | |
2055 | fputs ("),", file); | |
2056 | fputs (reg_names[REGNO (XEXP (addr, 0))], file); | |
2057 | break; | |
2058 | ||
1f92da87 | 2059 | case PRE_INC : /* Assume SImode. */ |
5b8ae21f MM |
2060 | fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]); |
2061 | break; | |
2062 | ||
1f92da87 | 2063 | case PRE_DEC : /* Assume SImode. */ |
5b8ae21f MM |
2064 | fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]); |
2065 | break; | |
2066 | ||
1f92da87 | 2067 | case POST_INC : /* Assume SImode. */ |
5b8ae21f | 2068 | fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]); |
8c5ca3b9 DE |
2069 | break; |
2070 | ||
2071 | default : | |
2072 | output_addr_const (file, addr); | |
2073 | break; | |
2074 | } | |
2075 | } | |
2b7972b0 MM |
2076 | |
2077 | /* Return true if the operands are the constants 0 and 1. */ | |
1f92da87 | 2078 | |
2b7972b0 | 2079 | int |
1f92da87 | 2080 | zero_and_one (rtx operand1, rtx operand2) |
2b7972b0 MM |
2081 | { |
2082 | return | |
2083 | GET_CODE (operand1) == CONST_INT | |
2084 | && GET_CODE (operand2) == CONST_INT | |
2085 | && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1)) | |
2086 | ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0))); | |
2087 | } | |
2088 | ||
2b7972b0 MM |
2089 | /* Generate the correct assembler code to handle the conditional loading of a |
2090 | value into a register. It is known that the operands satisfy the | |
2091 | conditional_move_operand() function above. The destination is operand[0]. | |
2092 | The condition is operand [1]. The 'true' value is operand [2] and the | |
2093 | 'false' value is operand [3]. */ | |
1f92da87 | 2094 | |
2b7972b0 | 2095 | char * |
1f92da87 | 2096 | emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED) |
2b7972b0 MM |
2097 | { |
2098 | static char buffer [100]; | |
99f44eba | 2099 | const char * dest = reg_names [REGNO (operands [0])]; |
e2265be0 | 2100 | |
2b7972b0 | 2101 | buffer [0] = 0; |
e2265be0 | 2102 | |
2b7972b0 | 2103 | /* Destination must be a register. */ |
75c3cfba NS |
2104 | gcc_assert (GET_CODE (operands [0]) == REG); |
2105 | gcc_assert (conditional_move_operand (operands [2], SImode)); | |
2106 | gcc_assert (conditional_move_operand (operands [3], SImode)); | |
e2265be0 | 2107 | |
2b7972b0 MM |
2108 | /* Check to see if the test is reversed. */ |
2109 | if (GET_CODE (operands [1]) == NE) | |
2110 | { | |
2111 | rtx tmp = operands [2]; | |
2112 | operands [2] = operands [3]; | |
2113 | operands [3] = tmp; | |
2114 | } | |
2115 | ||
51c10c4e | 2116 | sprintf (buffer, "mvfc %s, cbr", dest); |
16f104b3 | 2117 | |
51c10c4e NC |
2118 | /* If the true value was '0' then we need to invert the results of the move. */ |
2119 | if (INTVAL (operands [2]) == 0) | |
2120 | sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1", | |
2121 | dest, dest); | |
16f104b3 | 2122 | |
2b7972b0 MM |
2123 | return buffer; |
2124 | } | |
2125 | ||
56e2e762 | 2126 | /* Returns true if the registers contained in the two |
ff482c8d | 2127 | rtl expressions are different. */ |
1f92da87 | 2128 | |
56e2e762 | 2129 | int |
1f92da87 | 2130 | m32r_not_same_reg (rtx a, rtx b) |
56e2e762 NC |
2131 | { |
2132 | int reg_a = -1; | |
2133 | int reg_b = -2; | |
e2265be0 | 2134 | |
56e2e762 NC |
2135 | while (GET_CODE (a) == SUBREG) |
2136 | a = SUBREG_REG (a); | |
e2265be0 | 2137 | |
56e2e762 NC |
2138 | if (GET_CODE (a) == REG) |
2139 | reg_a = REGNO (a); | |
e2265be0 | 2140 | |
56e2e762 NC |
2141 | while (GET_CODE (b) == SUBREG) |
2142 | b = SUBREG_REG (b); | |
e2265be0 | 2143 | |
56e2e762 NC |
2144 | if (GET_CODE (b) == REG) |
2145 | reg_b = REGNO (b); | |
e2265be0 | 2146 | |
56e2e762 NC |
2147 | return reg_a != reg_b; |
2148 | } | |
d2a73f8e NC |
2149 | |
2150 | \f | |
767dec6b KI |
2151 | rtx |
2152 | m32r_function_symbol (const char *name) | |
2153 | { | |
2154 | int extra_flags = 0; | |
2155 | enum m32r_model model; | |
2156 | rtx sym = gen_rtx_SYMBOL_REF (Pmode, name); | |
2157 | ||
2158 | if (TARGET_MODEL_SMALL) | |
2159 | model = M32R_MODEL_SMALL; | |
2160 | else if (TARGET_MODEL_MEDIUM) | |
2161 | model = M32R_MODEL_MEDIUM; | |
2162 | else if (TARGET_MODEL_LARGE) | |
2163 | model = M32R_MODEL_LARGE; | |
2164 | else | |
75c3cfba | 2165 | gcc_unreachable (); /* Shouldn't happen. */ |
767dec6b | 2166 | extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT; |
e2265be0 | 2167 | |
767dec6b KI |
2168 | if (extra_flags) |
2169 | SYMBOL_REF_FLAGS (sym) |= extra_flags; | |
2170 | ||
2171 | return sym; | |
2172 | } | |
2173 | ||
d2a73f8e | 2174 | /* Use a library function to move some bytes. */ |
1f92da87 | 2175 | |
d2a73f8e | 2176 | static void |
f8e405a3 | 2177 | block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx) |
d2a73f8e NC |
2178 | { |
2179 | /* We want to pass the size as Pmode, which will normally be SImode | |
85f65093 | 2180 | but will be DImode if we are using 64-bit longs and pointers. */ |
d2a73f8e NC |
2181 | if (GET_MODE (bytes_rtx) != VOIDmode |
2182 | && GET_MODE (bytes_rtx) != Pmode) | |
2183 | bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1); | |
2184 | ||
767dec6b | 2185 | emit_library_call (m32r_function_symbol ("memcpy"), 0, |
d2a73f8e NC |
2186 | VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode, |
2187 | convert_to_mode (TYPE_MODE (sizetype), bytes_rtx, | |
8df83eae | 2188 | TYPE_UNSIGNED (sizetype)), |
d2a73f8e | 2189 | TYPE_MODE (sizetype)); |
d2a73f8e NC |
2190 | } |
2191 | ||
d2a73f8e NC |
2192 | /* Expand string/block move operations. |
2193 | ||
2194 | operands[0] is the pointer to the destination. | |
2195 | operands[1] is the pointer to the source. | |
2196 | operands[2] is the number of bytes to move. | |
0be4693a | 2197 | operands[3] is the alignment. |
d2a73f8e | 2198 | |
0be4693a KI |
2199 | Returns 1 upon success, 0 otherwise. */ |
2200 | ||
2201 | int | |
1f92da87 | 2202 | m32r_expand_block_move (rtx operands[]) |
d2a73f8e NC |
2203 | { |
2204 | rtx orig_dst = operands[0]; | |
2205 | rtx orig_src = operands[1]; | |
2206 | rtx bytes_rtx = operands[2]; | |
2207 | rtx align_rtx = operands[3]; | |
2208 | int constp = GET_CODE (bytes_rtx) == CONST_INT; | |
2209 | HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0; | |
2210 | int align = INTVAL (align_rtx); | |
2211 | int leftover; | |
2212 | rtx src_reg; | |
2213 | rtx dst_reg; | |
2214 | ||
2215 | if (constp && bytes <= 0) | |
0be4693a | 2216 | return 1; |
d2a73f8e NC |
2217 | |
2218 | /* Move the address into scratch registers. */ | |
2219 | dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0)); | |
2220 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2221 | ||
2222 | if (align > UNITS_PER_WORD) | |
2223 | align = UNITS_PER_WORD; | |
2224 | ||
2225 | /* If we prefer size over speed, always use a function call. | |
2226 | If we do not know the size, use a function call. | |
2227 | If the blocks are not word aligned, use a function call. */ | |
2228 | if (optimize_size || ! constp || align != UNITS_PER_WORD) | |
2229 | { | |
2230 | block_move_call (dst_reg, src_reg, bytes_rtx); | |
0be4693a | 2231 | return 0; |
d2a73f8e NC |
2232 | } |
2233 | ||
2234 | leftover = bytes % MAX_MOVE_BYTES; | |
2235 | bytes -= leftover; | |
e2265be0 | 2236 | |
d2a73f8e NC |
2237 | /* If necessary, generate a loop to handle the bulk of the copy. */ |
2238 | if (bytes) | |
2239 | { | |
950a3816 KG |
2240 | rtx label = NULL_RTX; |
2241 | rtx final_src = NULL_RTX; | |
0ae9f65b DE |
2242 | rtx at_a_time = GEN_INT (MAX_MOVE_BYTES); |
2243 | rtx rounded_total = GEN_INT (bytes); | |
81ad38a6 KH |
2244 | rtx new_dst_reg = gen_reg_rtx (SImode); |
2245 | rtx new_src_reg = gen_reg_rtx (SImode); | |
d2a73f8e NC |
2246 | |
2247 | /* If we are going to have to perform this loop more than | |
2248 | once, then generate a label and compute the address the | |
2249 | source register will contain upon completion of the final | |
dab66575 | 2250 | iteration. */ |
d2a73f8e NC |
2251 | if (bytes > MAX_MOVE_BYTES) |
2252 | { | |
2253 | final_src = gen_reg_rtx (Pmode); | |
2254 | ||
2255 | if (INT16_P(bytes)) | |
0ae9f65b | 2256 | emit_insn (gen_addsi3 (final_src, src_reg, rounded_total)); |
d2a73f8e NC |
2257 | else |
2258 | { | |
0ae9f65b | 2259 | emit_insn (gen_movsi (final_src, rounded_total)); |
d2a73f8e NC |
2260 | emit_insn (gen_addsi3 (final_src, final_src, src_reg)); |
2261 | } | |
2262 | ||
2263 | label = gen_label_rtx (); | |
2264 | emit_label (label); | |
2265 | } | |
2266 | ||
2267 | /* It is known that output_block_move() will update src_reg to point | |
2268 | to the word after the end of the source block, and dst_reg to point | |
2269 | to the last word of the destination block, provided that the block | |
2270 | is MAX_MOVE_BYTES long. */ | |
70128ad9 | 2271 | emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time, |
81ad38a6 KH |
2272 | new_dst_reg, new_src_reg)); |
2273 | emit_move_insn (dst_reg, new_dst_reg); | |
2274 | emit_move_insn (src_reg, new_src_reg); | |
d2a73f8e | 2275 | emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4))); |
e2265be0 | 2276 | |
d2a73f8e NC |
2277 | if (bytes > MAX_MOVE_BYTES) |
2278 | { | |
2279 | emit_insn (gen_cmpsi (src_reg, final_src)); | |
2280 | emit_jump_insn (gen_bne (label)); | |
2281 | } | |
2282 | } | |
2283 | ||
2284 | if (leftover) | |
70128ad9 | 2285 | emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover), |
81ad38a6 KH |
2286 | gen_reg_rtx (SImode), |
2287 | gen_reg_rtx (SImode))); | |
0be4693a | 2288 | return 1; |
d2a73f8e NC |
2289 | } |
2290 | ||
2291 | \f | |
e2265be0 | 2292 | /* Emit load/stores for a small constant word aligned block_move. |
d2a73f8e NC |
2293 | |
2294 | operands[0] is the memory address of the destination. | |
2295 | operands[1] is the memory address of the source. | |
2296 | operands[2] is the number of bytes to move. | |
2297 | operands[3] is a temp register. | |
2298 | operands[4] is a temp register. */ | |
2299 | ||
16f104b3 | 2300 | void |
1f92da87 | 2301 | m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[]) |
d2a73f8e NC |
2302 | { |
2303 | HOST_WIDE_INT bytes = INTVAL (operands[2]); | |
2304 | int first_time; | |
2305 | int got_extra = 0; | |
e2265be0 | 2306 | |
75c3cfba | 2307 | gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES); |
e2265be0 | 2308 | |
d2a73f8e NC |
2309 | /* We do not have a post-increment store available, so the first set of |
2310 | stores are done without any increment, then the remaining ones can use | |
2311 | the pre-increment addressing mode. | |
e2265be0 | 2312 | |
a0ab749a | 2313 | Note: expand_block_move() also relies upon this behavior when building |
d2a73f8e NC |
2314 | loops to copy large blocks. */ |
2315 | first_time = 1; | |
e2265be0 | 2316 | |
d2a73f8e NC |
2317 | while (bytes > 0) |
2318 | { | |
2319 | if (bytes >= 8) | |
2320 | { | |
2321 | if (first_time) | |
2322 | { | |
81ad38a6 KH |
2323 | output_asm_insn ("ld\t%5, %p1", operands); |
2324 | output_asm_insn ("ld\t%6, %p1", operands); | |
2325 | output_asm_insn ("st\t%5, @%0", operands); | |
2326 | output_asm_insn ("st\t%6, %s0", operands); | |
d2a73f8e NC |
2327 | } |
2328 | else | |
2329 | { | |
81ad38a6 KH |
2330 | output_asm_insn ("ld\t%5, %p1", operands); |
2331 | output_asm_insn ("ld\t%6, %p1", operands); | |
2332 | output_asm_insn ("st\t%5, %s0", operands); | |
2333 | output_asm_insn ("st\t%6, %s0", operands); | |
d2a73f8e NC |
2334 | } |
2335 | ||
2336 | bytes -= 8; | |
2337 | } | |
2338 | else if (bytes >= 4) | |
2339 | { | |
2340 | if (bytes > 4) | |
2341 | got_extra = 1; | |
e2265be0 | 2342 | |
81ad38a6 | 2343 | output_asm_insn ("ld\t%5, %p1", operands); |
e2265be0 | 2344 | |
d2a73f8e | 2345 | if (got_extra) |
81ad38a6 | 2346 | output_asm_insn ("ld\t%6, %p1", operands); |
e2265be0 | 2347 | |
d2a73f8e | 2348 | if (first_time) |
81ad38a6 | 2349 | output_asm_insn ("st\t%5, @%0", operands); |
d2a73f8e | 2350 | else |
81ad38a6 | 2351 | output_asm_insn ("st\t%5, %s0", operands); |
d2a73f8e NC |
2352 | |
2353 | bytes -= 4; | |
2354 | } | |
e2265be0 | 2355 | else |
d2a73f8e NC |
2356 | { |
2357 | /* Get the entire next word, even though we do not want all of it. | |
2358 | The saves us from doing several smaller loads, and we assume that | |
2359 | we cannot cause a page fault when at least part of the word is in | |
0ae9f65b DE |
2360 | valid memory [since we don't get called if things aren't properly |
2361 | aligned]. */ | |
2362 | int dst_offset = first_time ? 0 : 4; | |
81ad38a6 KH |
2363 | /* The amount of increment we have to make to the |
2364 | destination pointer. */ | |
2365 | int dst_inc_amount = dst_offset + bytes - 4; | |
2366 | /* The same for the source pointer. */ | |
2367 | int src_inc_amount = bytes; | |
0ae9f65b DE |
2368 | int last_shift; |
2369 | rtx my_operands[3]; | |
2370 | ||
2371 | /* If got_extra is true then we have already loaded | |
d2a73f8e NC |
2372 | the next word as part of loading and storing the previous word. */ |
2373 | if (! got_extra) | |
81ad38a6 | 2374 | output_asm_insn ("ld\t%6, @%1", operands); |
d2a73f8e NC |
2375 | |
2376 | if (bytes >= 2) | |
2377 | { | |
2378 | bytes -= 2; | |
2379 | ||
81ad38a6 KH |
2380 | output_asm_insn ("sra3\t%5, %6, #16", operands); |
2381 | my_operands[0] = operands[5]; | |
0ae9f65b DE |
2382 | my_operands[1] = GEN_INT (dst_offset); |
2383 | my_operands[2] = operands[0]; | |
2384 | output_asm_insn ("sth\t%0, @(%1,%2)", my_operands); | |
e2265be0 | 2385 | |
d2a73f8e NC |
2386 | /* If there is a byte left to store then increment the |
2387 | destination address and shift the contents of the source | |
0ae9f65b | 2388 | register down by 8 bits. We could not do the address |
d2a73f8e NC |
2389 | increment in the store half word instruction, because it does |
2390 | not have an auto increment mode. */ | |
2391 | if (bytes > 0) /* assert (bytes == 1) */ | |
2392 | { | |
0ae9f65b DE |
2393 | dst_offset += 2; |
2394 | last_shift = 8; | |
d2a73f8e NC |
2395 | } |
2396 | } | |
0ae9f65b DE |
2397 | else |
2398 | last_shift = 24; | |
2399 | ||
2400 | if (bytes > 0) | |
2401 | { | |
81ad38a6 | 2402 | my_operands[0] = operands[6]; |
0ae9f65b DE |
2403 | my_operands[1] = GEN_INT (last_shift); |
2404 | output_asm_insn ("srai\t%0, #%1", my_operands); | |
81ad38a6 | 2405 | my_operands[0] = operands[6]; |
0ae9f65b DE |
2406 | my_operands[1] = GEN_INT (dst_offset); |
2407 | my_operands[2] = operands[0]; | |
2408 | output_asm_insn ("stb\t%0, @(%1,%2)", my_operands); | |
2409 | } | |
81ad38a6 KH |
2410 | |
2411 | /* Update the destination pointer if needed. We have to do | |
2412 | this so that the patterns matches what we output in this | |
2413 | function. */ | |
2414 | if (dst_inc_amount | |
2415 | && !find_reg_note (insn, REG_UNUSED, operands[0])) | |
2416 | { | |
2417 | my_operands[0] = operands[0]; | |
2418 | my_operands[1] = GEN_INT (dst_inc_amount); | |
2419 | output_asm_insn ("addi\t%0, #%1", my_operands); | |
2420 | } | |
e2265be0 | 2421 | |
81ad38a6 KH |
2422 | /* Update the source pointer if needed. We have to do this |
2423 | so that the patterns matches what we output in this | |
2424 | function. */ | |
2425 | if (src_inc_amount | |
2426 | && !find_reg_note (insn, REG_UNUSED, operands[1])) | |
2427 | { | |
2428 | my_operands[0] = operands[1]; | |
2429 | my_operands[1] = GEN_INT (src_inc_amount); | |
2430 | output_asm_insn ("addi\t%0, #%1", my_operands); | |
2431 | } | |
e2265be0 | 2432 | |
d2a73f8e NC |
2433 | bytes = 0; |
2434 | } | |
2435 | ||
2436 | first_time = 0; | |
2437 | } | |
d2a73f8e NC |
2438 | } |
2439 | ||
a398a822 KI |
2440 | /* Return true if using NEW_REG in place of OLD_REG is ok. */ |
2441 | ||
2442 | int | |
1f92da87 NC |
2443 | m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, |
2444 | unsigned int new_reg) | |
a398a822 KI |
2445 | { |
2446 | /* Interrupt routines can't clobber any register that isn't already used. */ | |
2447 | if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) | |
6fb5fa3c | 2448 | && !df_regs_ever_live_p (new_reg)) |
a398a822 KI |
2449 | return 0; |
2450 | ||
a398a822 KI |
2451 | return 1; |
2452 | } | |
7b14411a KI |
2453 | |
2454 | rtx | |
2455 | m32r_return_addr (int count) | |
2456 | { | |
2457 | if (count != 0) | |
2458 | return const0_rtx; | |
e2265be0 | 2459 | |
7b14411a KI |
2460 | return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); |
2461 | } |