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aea2fd96 1/* Subroutines used for code generation on the Renesas M32R cpu.
deceffc1 2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
71e45bc2 3 2005, 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
d868a170 4
aea2fd96 5 This file is part of GCC.
d868a170 6
aea2fd96 7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
038d1e19 9 by the Free Software Foundation; either version 3, or (at your
aea2fd96 10 option) any later version.
d868a170 11
aea2fd96 12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
d868a170 16
aea2fd96 17 You should have received a copy of the GNU General Public License
038d1e19 18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
d868a170 20
d868a170 21#include "config.h"
7dbe3569 22#include "system.h"
805e22b2 23#include "coretypes.h"
24#include "tm.h"
d868a170 25#include "tree.h"
26#include "rtl.h"
27#include "regs.h"
28#include "hard-reg-set.h"
d868a170 29#include "insn-config.h"
30#include "conditions.h"
d868a170 31#include "output.h"
b5369b7d 32#include "dbxout.h"
d868a170 33#include "insn-attr.h"
34#include "flags.h"
35#include "expr.h"
4faf81b8 36#include "function.h"
d868a170 37#include "recog.h"
0b205f4c 38#include "diagnostic-core.h"
03033f8f 39#include "ggc.h"
ef51d1e3 40#include "df.h"
79e2a0ca 41#include "tm_p.h"
a767736d 42#include "target.h"
43#include "target-def.h"
bd9c4764 44#include "tm-constrs.h"
fba5dd52 45#include "opts.h"
d868a170 46
d868a170 47/* Array of valid operand punctuation characters. */
8e8a63d1 48static char m32r_punct_chars[256];
d868a170 49
5c5d0ae9 50/* Machine-specific symbol_ref flags. */
51#define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
52#define SYMBOL_REF_MODEL(X) \
53 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
54
55/* For string literals, etc. */
56#define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
57
868d8e32 58/* Forward declaration. */
4c834714 59static void m32r_option_override (void);
0792f2cf 60static void init_reg_tables (void);
61static void block_move_call (rtx, rtx, rtx);
62static int m32r_is_insn (rtx);
bb10104e 63static bool m32r_legitimate_address_p (enum machine_mode, rtx, bool);
41e3a0c7 64static rtx m32r_legitimize_address (rtx, rtx, enum machine_mode);
4e27ffd0 65static bool m32r_mode_dependent_address_p (const_rtx, addr_space_t);
0792f2cf 66static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
8e8a63d1 67static void m32r_print_operand (FILE *, rtx, int);
68static void m32r_print_operand_address (FILE *, rtx);
69static bool m32r_print_operand_punct_valid_p (unsigned char code);
0792f2cf 70static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
71static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
72
73static void m32r_file_start (void);
74
0792f2cf 75static int m32r_adjust_priority (rtx, int);
0792f2cf 76static int m32r_issue_rate (void);
77
78static void m32r_encode_section_info (tree, rtx, int);
a9f1838b 79static bool m32r_in_small_data_p (const_tree);
fb80456a 80static bool m32r_return_in_memory (const_tree, const_tree);
fb97ed3e 81static rtx m32r_function_value (const_tree, const_tree, bool);
82static rtx m32r_libcall_value (enum machine_mode, const_rtx);
83static bool m32r_function_value_regno_p (const unsigned int);
39cba157 84static void m32r_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
efc813ec 85 tree, int *, int);
0792f2cf 86static void init_idents (void);
20d892d1 87static bool m32r_rtx_costs (rtx, int, int, int, int *, bool speed);
5e5dc6b5 88static int m32r_memory_move_cost (enum machine_mode, reg_class_t, bool);
39cba157 89static bool m32r_pass_by_reference (cumulative_args_t, enum machine_mode,
fb80456a 90 const_tree, bool);
39cba157 91static int m32r_arg_partial_bytes (cumulative_args_t, enum machine_mode,
f054eb3c 92 tree, bool);
39cba157 93static rtx m32r_function_arg (cumulative_args_t, enum machine_mode,
1bd483c2 94 const_tree, bool);
39cba157 95static void m32r_function_arg_advance (cumulative_args_t, enum machine_mode,
1bd483c2 96 const_tree, bool);
cd90919d 97static bool m32r_can_eliminate (const int, const int);
b2d7ede1 98static void m32r_conditional_register_usage (void);
06b77609 99static void m32r_trampoline_init (rtx, tree, rtx);
ca316360 100static bool m32r_legitimate_constant_p (enum machine_mode, rtx);
a767736d 101\f
ef51d1e3 102/* M32R specific attributes. */
103
104static const struct attribute_spec m32r_attribute_table[] =
105{
ac86af5d 106 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
107 affects_type_identity } */
108 { "interrupt", 0, 0, true, false, false, NULL, false },
109 { "model", 1, 1, true, false, false, m32r_handle_model_attribute,
110 false },
111 { NULL, 0, 0, false, false, false, NULL, false }
ef51d1e3 112};
113\f
a767736d 114/* Initialize the GCC target structure. */
aea2fd96 115#undef TARGET_ATTRIBUTE_TABLE
e3c541f0 116#define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
868d8e32 117
bb10104e 118#undef TARGET_LEGITIMATE_ADDRESS_P
119#define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
41e3a0c7 120#undef TARGET_LEGITIMIZE_ADDRESS
121#define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
8c9a773b 122#undef TARGET_MODE_DEPENDENT_ADDRESS_P
123#define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
41e3a0c7 124
aea2fd96 125#undef TARGET_ASM_ALIGNED_HI_OP
58356836 126#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
aea2fd96 127#undef TARGET_ASM_ALIGNED_SI_OP
58356836 128#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
129
8e8a63d1 130#undef TARGET_PRINT_OPERAND
131#define TARGET_PRINT_OPERAND m32r_print_operand
132#undef TARGET_PRINT_OPERAND_ADDRESS
133#define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
134#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
135#define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
136
aea2fd96 137#undef TARGET_ASM_FUNCTION_PROLOGUE
17d9b0c3 138#define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
aea2fd96 139#undef TARGET_ASM_FUNCTION_EPILOGUE
17d9b0c3 140#define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
141
aea2fd96 142#undef TARGET_ASM_FILE_START
92c473b8 143#define TARGET_ASM_FILE_START m32r_file_start
144
aea2fd96 145#undef TARGET_SCHED_ADJUST_PRIORITY
747af5e7 146#define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
aea2fd96 147#undef TARGET_SCHED_ISSUE_RATE
747af5e7 148#define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
747af5e7 149
4c834714 150#undef TARGET_OPTION_OVERRIDE
151#define TARGET_OPTION_OVERRIDE m32r_option_override
d21dcfd4 152
aea2fd96 153#undef TARGET_ENCODE_SECTION_INFO
7811991d 154#define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
aea2fd96 155#undef TARGET_IN_SMALL_DATA_P
5c5d0ae9 156#define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
7811991d 157
5e5dc6b5 158
09c20b62 159#undef TARGET_MEMORY_MOVE_COST
160#define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
aea2fd96 161#undef TARGET_RTX_COSTS
fab7adbf 162#define TARGET_RTX_COSTS m32r_rtx_costs
aea2fd96 163#undef TARGET_ADDRESS_COST
d9c5e5f4 164#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
fab7adbf 165
efc813ec 166#undef TARGET_PROMOTE_PROTOTYPES
fb80456a 167#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
efc813ec 168#undef TARGET_RETURN_IN_MEMORY
169#define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
fb97ed3e 170
171#undef TARGET_FUNCTION_VALUE
172#define TARGET_FUNCTION_VALUE m32r_function_value
173#undef TARGET_LIBCALL_VALUE
174#define TARGET_LIBCALL_VALUE m32r_libcall_value
175#undef TARGET_FUNCTION_VALUE_REGNO_P
176#define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
177
efc813ec 178#undef TARGET_SETUP_INCOMING_VARARGS
179#define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
0336f0f0 180#undef TARGET_MUST_PASS_IN_STACK
181#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
b981d932 182#undef TARGET_PASS_BY_REFERENCE
183#define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
f054eb3c 184#undef TARGET_ARG_PARTIAL_BYTES
185#define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
1bd483c2 186#undef TARGET_FUNCTION_ARG
187#define TARGET_FUNCTION_ARG m32r_function_arg
188#undef TARGET_FUNCTION_ARG_ADVANCE
189#define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
0336f0f0 190
cd90919d 191#undef TARGET_CAN_ELIMINATE
192#define TARGET_CAN_ELIMINATE m32r_can_eliminate
193
b2d7ede1 194#undef TARGET_CONDITIONAL_REGISTER_USAGE
195#define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
196
06b77609 197#undef TARGET_TRAMPOLINE_INIT
198#define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
199
ca316360 200#undef TARGET_LEGITIMATE_CONSTANT_P
201#define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
202
57e4bbfb 203struct gcc_target targetm = TARGET_INITIALIZER;
a767736d 204\f
4c834714 205/* Called by m32r_option_override to initialize various things. */
d868a170 206
207void
aea2fd96 208m32r_init (void)
d868a170 209{
210 init_reg_tables ();
211
8e8a63d1 212 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
d868a170 213 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
214 m32r_punct_chars['#'] = 1;
215 m32r_punct_chars['@'] = 1; /* ??? no longer used */
216
217 /* Provide default value if not specified. */
13a54dd9 218 if (!global_options_set.x_g_switch_value)
d868a170 219 g_switch_value = SDATA_DEFAULT_SIZE;
d868a170 220}
221
4c834714 222static void
223m32r_option_override (void)
224{
225 /* These need to be done at start up.
226 It's convenient to do them here. */
227 m32r_init ();
228 SUBTARGET_OVERRIDE_OPTIONS;
229}
230
d868a170 231/* Vectors to keep interesting information about registers where it can easily
232 be got. We use to use the actual mode value as the bit number, but there
233 is (or may be) more than 32 modes now. Instead we use two tables: one
234 indexed by hard register number, and one indexed by mode. */
235
236/* The purpose of m32r_mode_class is to shrink the range of modes so that
c910419d 237 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
d868a170 238 mapped into one m32r_mode_class mode. */
239
868d8e32 240enum m32r_mode_class
241{
d868a170 242 C_MODE,
243 S_MODE, D_MODE, T_MODE, O_MODE,
947391dc 244 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
d868a170 245};
246
247/* Modes for condition codes. */
248#define C_MODES (1 << (int) C_MODE)
249
250/* Modes for single-word and smaller quantities. */
251#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
252
253/* Modes for double-word and smaller quantities. */
254#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
255
256/* Modes for quad-word and smaller quantities. */
257#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
258
947391dc 259/* Modes for accumulators. */
260#define A_MODES (1 << (int) A_MODE)
868d8e32 261
d868a170 262/* Value is 1 if register/mode pair is acceptable on arc. */
263
c8834c5f 264const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
868d8e32 265{
d868a170 266 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
267 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
6f9235e4 268 S_MODES, C_MODES, A_MODES, A_MODES
d868a170 269};
270
271unsigned int m32r_mode_class [NUM_MACHINE_MODES];
272
273enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
274
275static void
aea2fd96 276init_reg_tables (void)
d868a170 277{
278 int i;
279
280 for (i = 0; i < NUM_MACHINE_MODES; i++)
281 {
282 switch (GET_MODE_CLASS (i))
283 {
284 case MODE_INT:
285 case MODE_PARTIAL_INT:
286 case MODE_COMPLEX_INT:
287 if (GET_MODE_SIZE (i) <= 4)
288 m32r_mode_class[i] = 1 << (int) S_MODE;
289 else if (GET_MODE_SIZE (i) == 8)
290 m32r_mode_class[i] = 1 << (int) D_MODE;
291 else if (GET_MODE_SIZE (i) == 16)
292 m32r_mode_class[i] = 1 << (int) T_MODE;
293 else if (GET_MODE_SIZE (i) == 32)
294 m32r_mode_class[i] = 1 << (int) O_MODE;
58f4ce52 295 else
d868a170 296 m32r_mode_class[i] = 0;
297 break;
298 case MODE_FLOAT:
299 case MODE_COMPLEX_FLOAT:
300 if (GET_MODE_SIZE (i) <= 4)
301 m32r_mode_class[i] = 1 << (int) SF_MODE;
302 else if (GET_MODE_SIZE (i) == 8)
303 m32r_mode_class[i] = 1 << (int) DF_MODE;
304 else if (GET_MODE_SIZE (i) == 16)
305 m32r_mode_class[i] = 1 << (int) TF_MODE;
306 else if (GET_MODE_SIZE (i) == 32)
307 m32r_mode_class[i] = 1 << (int) OF_MODE;
58f4ce52 308 else
d868a170 309 m32r_mode_class[i] = 0;
310 break;
311 case MODE_CC:
15460c97 312 m32r_mode_class[i] = 1 << (int) C_MODE;
313 break;
d868a170 314 default:
15460c97 315 m32r_mode_class[i] = 0;
d868a170 316 break;
317 }
318 }
319
320 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
321 {
322 if (GPR_P (i))
323 m32r_regno_reg_class[i] = GENERAL_REGS;
324 else if (i == ARG_POINTER_REGNUM)
325 m32r_regno_reg_class[i] = GENERAL_REGS;
326 else
327 m32r_regno_reg_class[i] = NO_REGS;
328 }
329}
330\f
331/* M32R specific attribute support.
332
333 interrupt - for interrupt functions
334
335 model - select code model used to access object
336
337 small: addresses use 24 bits, use bl to make calls
338 medium: addresses use 32 bits, use bl to make calls
339 large: addresses use 32 bits, use seth/add3/jl to make calls
340
aea2fd96 341 Grep for MODEL in m32r.h for more info. */
d868a170 342
d7f038f8 343static tree small_ident1;
344static tree small_ident2;
345static tree medium_ident1;
346static tree medium_ident2;
347static tree large_ident1;
348static tree large_ident2;
349
350static void
aea2fd96 351init_idents (void)
d7f038f8 352{
e3c541f0 353 if (small_ident1 == 0)
d7f038f8 354 {
d7f038f8 355 small_ident1 = get_identifier ("small");
356 small_ident2 = get_identifier ("__small__");
357 medium_ident1 = get_identifier ("medium");
358 medium_ident2 = get_identifier ("__medium__");
359 large_ident1 = get_identifier ("large");
360 large_ident2 = get_identifier ("__large__");
361 }
362}
363
e3c541f0 364/* Handle an "model" attribute; arguments as in
365 struct attribute_spec.handler. */
366static tree
aea2fd96 367m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
368 tree args, int flags ATTRIBUTE_UNUSED,
369 bool *no_add_attrs)
d868a170 370{
e3c541f0 371 tree arg;
d868a170 372
e3c541f0 373 init_idents ();
374 arg = TREE_VALUE (args);
375
376 if (arg != small_ident1
377 && arg != small_ident2
378 && arg != medium_ident1
379 && arg != medium_ident2
380 && arg != large_ident1
381 && arg != large_ident2)
382 {
9b2d6d13 383 warning (OPT_Wattributes, "invalid argument of %qs attribute",
e3c541f0 384 IDENTIFIER_POINTER (name));
385 *no_add_attrs = true;
386 }
d868a170 387
e3c541f0 388 return NULL_TREE;
d868a170 389}
d868a170 390\f
d868a170 391/* Encode section information of DECL, which is either a VAR_DECL,
392 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
393
394 For the M32R we want to record:
395
396 - whether the object lives in .sdata/.sbss.
d868a170 397 - what code model should be used to access the object
d868a170 398*/
399
7811991d 400static void
aea2fd96 401m32r_encode_section_info (tree decl, rtx rtl, int first)
d868a170 402{
5c5d0ae9 403 int extra_flags = 0;
404 tree model_attr;
405 enum m32r_model model;
d868a170 406
2c129d70 407 default_encode_section_info (decl, rtl, first);
5c5d0ae9 408
409 if (!DECL_P (decl))
41eb471c 410 return;
411
5c5d0ae9 412 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
413 if (model_attr)
d868a170 414 {
5c5d0ae9 415 tree id;
d868a170 416
5c5d0ae9 417 init_idents ();
d868a170 418
5c5d0ae9 419 id = TREE_VALUE (TREE_VALUE (model_attr));
d868a170 420
5c5d0ae9 421 if (id == small_ident1 || id == small_ident2)
422 model = M32R_MODEL_SMALL;
423 else if (id == medium_ident1 || id == medium_ident2)
424 model = M32R_MODEL_MEDIUM;
425 else if (id == large_ident1 || id == large_ident2)
426 model = M32R_MODEL_LARGE;
427 else
7afac3c3 428 gcc_unreachable (); /* shouldn't happen */
5c5d0ae9 429 }
430 else
d868a170 431 {
5c5d0ae9 432 if (TARGET_MODEL_SMALL)
433 model = M32R_MODEL_SMALL;
434 else if (TARGET_MODEL_MEDIUM)
435 model = M32R_MODEL_MEDIUM;
436 else if (TARGET_MODEL_LARGE)
437 model = M32R_MODEL_LARGE;
d868a170 438 else
7afac3c3 439 gcc_unreachable (); /* shouldn't happen */
d868a170 440 }
5c5d0ae9 441 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
d868a170 442
5c5d0ae9 443 if (extra_flags)
2c129d70 444 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5c5d0ae9 445}
d7f038f8 446
5c5d0ae9 447/* Only mark the object as being small data area addressable if
448 it hasn't been explicitly marked with a code model.
d7f038f8 449
5c5d0ae9 450 The user can explicitly put an object in the small data area with the
451 section attribute. If the object is in sdata/sbss and marked with a
452 code model do both [put the object in .sdata and mark it as being
453 addressed with a specific code model - don't mark it as being addressed
454 with an SDA reloc though]. This is ok and might be useful at times. If
455 the object doesn't fit the linker will give an error. */
d868a170 456
5c5d0ae9 457static bool
a9f1838b 458m32r_in_small_data_p (const_tree decl)
5c5d0ae9 459{
a9f1838b 460 const_tree section;
5c5d0ae9 461
462 if (TREE_CODE (decl) != VAR_DECL)
463 return false;
464
465 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
466 return false;
467
468 section = DECL_SECTION_NAME (decl);
469 if (section)
d868a170 470 {
fb80456a 471 const char *const name = TREE_STRING_POINTER (section);
5c5d0ae9 472 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
473 return true;
d868a170 474 }
5c5d0ae9 475 else
476 {
477 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
478 {
479 int size = int_size_in_bytes (TREE_TYPE (decl));
d868a170 480
13a54dd9 481 if (size > 0 && size <= g_switch_value)
5c5d0ae9 482 return true;
483 }
484 }
7b4a38a6 485
5c5d0ae9 486 return false;
7b4a38a6 487}
488
d868a170 489/* Do anything needed before RTL is emitted for each function. */
490
491void
aea2fd96 492m32r_init_expanders (void)
d868a170 493{
494 /* ??? At one point there was code here. The function is left in
495 to make it easy to experiment. */
496}
497\f
d868a170 498int
aea2fd96 499call_operand (rtx op, enum machine_mode mode)
d868a170 500{
452bfb8b 501 if (!MEM_P (op))
d868a170 502 return 0;
503 op = XEXP (op, 0);
504 return call_address_operand (op, mode);
505}
506
d868a170 507/* Return 1 if OP is a reference to an object in .sdata/.sbss. */
508
509int
aea2fd96 510small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 511{
512 if (! TARGET_SDATA_USE)
513 return 0;
514
515 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 516 return SYMBOL_REF_SMALL_P (op);
d868a170 517
518 if (GET_CODE (op) == CONST
519 && GET_CODE (XEXP (op, 0)) == PLUS
520 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
bd9c4764 521 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
5c5d0ae9 522 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
d868a170 523
524 return 0;
525}
526
c910419d 527/* Return 1 if OP is a symbol that can use 24-bit addressing. */
d868a170 528
529int
aea2fd96 530addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 531{
5c5d0ae9 532 rtx sym;
533
467dc9aa 534 if (flag_pic)
535 return 0;
536
d868a170 537 if (GET_CODE (op) == LABEL_REF)
538 return TARGET_ADDR24;
539
540 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 541 sym = op;
542 else if (GET_CODE (op) == CONST
543 && GET_CODE (XEXP (op, 0)) == PLUS
544 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
bd9c4764 545 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
5c5d0ae9 546 sym = XEXP (XEXP (op, 0), 0);
547 else
548 return 0;
d868a170 549
5c5d0ae9 550 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
551 return 1;
552
553 if (TARGET_ADDR24
554 && (CONSTANT_POOL_ADDRESS_P (sym)
555 || LIT_NAME_P (XSTR (sym, 0))))
556 return 1;
d868a170 557
558 return 0;
559}
560
c910419d 561/* Return 1 if OP is a symbol that needs 32-bit addressing. */
d868a170 562
563int
aea2fd96 564addr32_operand (rtx op, enum machine_mode mode)
d868a170 565{
5c5d0ae9 566 rtx sym;
567
d868a170 568 if (GET_CODE (op) == LABEL_REF)
569 return TARGET_ADDR32;
570
571 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 572 sym = op;
573 else if (GET_CODE (op) == CONST
574 && GET_CODE (XEXP (op, 0)) == PLUS
575 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
452bfb8b 576 && CONST_INT_P (XEXP (XEXP (op, 0), 1))
467dc9aa 577 && ! flag_pic)
5c5d0ae9 578 sym = XEXP (XEXP (op, 0), 0);
579 else
580 return 0;
d868a170 581
5c5d0ae9 582 return (! addr24_operand (sym, mode)
583 && ! small_data_operand (sym, mode));
d868a170 584}
585
586/* Return 1 if OP is a function that can be called with the `bl' insn. */
587
588int
aea2fd96 589call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 590{
467dc9aa 591 if (flag_pic)
843505b2 592 return 1;
467dc9aa 593
d868a170 594 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 595 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
d868a170 596
597 return TARGET_CALL26;
598}
599
d868a170 600/* Return 1 if OP is a DImode const we want to handle inline.
601 This must match the code in the movdi pattern.
602 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
603
604int
aea2fd96 605easy_di_const (rtx op)
d868a170 606{
607 rtx high_rtx, low_rtx;
608 HOST_WIDE_INT high, low;
609
610 split_double (op, &high_rtx, &low_rtx);
611 high = INTVAL (high_rtx);
612 low = INTVAL (low_rtx);
c910419d 613 /* Pick constants loadable with 2 16-bit `ldi' insns. */
d868a170 614 if (high >= -128 && high <= 127
615 && low >= -128 && low <= 127)
616 return 1;
617 return 0;
618}
619
620/* Return 1 if OP is a DFmode const we want to handle inline.
621 This must match the code in the movdf pattern.
622 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
623
624int
aea2fd96 625easy_df_const (rtx op)
d868a170 626{
627 REAL_VALUE_TYPE r;
628 long l[2];
629
630 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
631 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
632 if (l[0] == 0 && l[1] == 0)
633 return 1;
634 if ((l[0] & 0xffff) == 0 && l[1] == 0)
635 return 1;
636 return 0;
637}
638
d868a170 639/* Return 1 if OP is (mem (reg ...)).
640 This is used in insn length calcs. */
641
642int
aea2fd96 643memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 644{
be96c8c6 645 return MEM_P (op) && REG_P (XEXP (op, 0));
d868a170 646}
868d8e32 647
b981d932 648/* Return nonzero if TYPE must be passed by indirect reference. */
daece349 649
b981d932 650static bool
39cba157 651m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
fb80456a 652 enum machine_mode mode, const_tree type,
b981d932 653 bool named ATTRIBUTE_UNUSED)
daece349 654{
b981d932 655 int size;
daece349 656
b981d932 657 if (type)
658 size = int_size_in_bytes (type);
659 else
660 size = GET_MODE_SIZE (mode);
daece349 661
b981d932 662 return (size < 0 || size > 8);
daece349 663}
d868a170 664\f
665/* Comparisons. */
666
d868a170 667/* X and Y are two things to compare using CODE. Emit the compare insn and
868d8e32 668 return the rtx for compare [arg0 of the if_then_else].
669 If need_compare is true then the comparison insn must be generated, rather
dfd1079d 670 than being subsumed into the following branch instruction. */
d868a170 671
672rtx
aea2fd96 673gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
d868a170 674{
aea2fd96 675 enum rtx_code compare_code;
676 enum rtx_code branch_code;
60a061f2 677 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
6441a98f 678 int must_swap = 0;
d868a170 679
680 switch (code)
681 {
8ec9afef 682 case EQ: compare_code = EQ; branch_code = NE; break;
683 case NE: compare_code = EQ; branch_code = EQ; break;
684 case LT: compare_code = LT; branch_code = NE; break;
685 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
686 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
687 case GE: compare_code = LT; branch_code = EQ; break;
d868a170 688 case LTU: compare_code = LTU; branch_code = NE; break;
8ec9afef 689 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
690 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
d868a170 691 case GEU: compare_code = LTU; branch_code = EQ; break;
6441a98f 692
693 default:
7afac3c3 694 gcc_unreachable ();
d868a170 695 }
696
868d8e32 697 if (need_compare)
698 {
699 switch (compare_code)
700 {
701 case EQ:
bd9c4764 702 if (satisfies_constraint_P (y) /* Reg equal to small const. */
868d8e32 703 && y != const0_rtx)
704 {
58f4ce52 705 rtx tmp = gen_reg_rtx (SImode);
706
467cdcb9 707 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
868d8e32 708 x = tmp;
709 y = const0_rtx;
710 }
aea2fd96 711 else if (CONSTANT_P (y)) /* Reg equal to const. */
868d8e32 712 {
713 rtx tmp = force_reg (GET_MODE (x), y);
714 y = tmp;
715 }
716
aea2fd96 717 if (register_operand (y, SImode) /* Reg equal to reg. */
718 || y == const0_rtx) /* Reg equal to zero. */
868d8e32 719 {
947391dc 720 emit_insn (gen_cmp_eqsi_insn (x, y));
58f4ce52 721
29bb088d 722 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
868d8e32 723 }
724 break;
58f4ce52 725
868d8e32 726 case LT:
727 if (register_operand (y, SImode)
bd9c4764 728 || satisfies_constraint_P (y))
868d8e32 729 {
aea2fd96 730 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
58f4ce52 731
868d8e32 732 switch (code)
733 {
734 case LT:
735 emit_insn (gen_cmp_ltsi_insn (x, y));
736 code = EQ;
737 break;
738 case LE:
739 if (y == const0_rtx)
740 tmp = const1_rtx;
741 else
467cdcb9 742 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 743 emit_insn (gen_cmp_ltsi_insn (x, tmp));
744 code = EQ;
745 break;
746 case GT:
452bfb8b 747 if (CONST_INT_P (y))
1a83b3ff 748 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
868d8e32 749 else
467cdcb9 750 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 751 emit_insn (gen_cmp_ltsi_insn (x, tmp));
752 code = NE;
753 break;
754 case GE:
755 emit_insn (gen_cmp_ltsi_insn (x, y));
756 code = NE;
757 break;
758 default:
7afac3c3 759 gcc_unreachable ();
868d8e32 760 }
58f4ce52 761
29bb088d 762 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
868d8e32 763 }
764 break;
58f4ce52 765
868d8e32 766 case LTU:
767 if (register_operand (y, SImode)
bd9c4764 768 || satisfies_constraint_P (y))
868d8e32 769 {
aea2fd96 770 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
58f4ce52 771
868d8e32 772 switch (code)
773 {
774 case LTU:
775 emit_insn (gen_cmp_ltusi_insn (x, y));
776 code = EQ;
777 break;
778 case LEU:
779 if (y == const0_rtx)
780 tmp = const1_rtx;
781 else
467cdcb9 782 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 783 emit_insn (gen_cmp_ltusi_insn (x, tmp));
784 code = EQ;
785 break;
786 case GTU:
452bfb8b 787 if (CONST_INT_P (y))
1a83b3ff 788 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
868d8e32 789 else
467cdcb9 790 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 791 emit_insn (gen_cmp_ltusi_insn (x, tmp));
792 code = NE;
793 break;
794 case GEU:
795 emit_insn (gen_cmp_ltusi_insn (x, y));
796 code = NE;
797 break;
798 default:
7afac3c3 799 gcc_unreachable ();
868d8e32 800 }
58f4ce52 801
29bb088d 802 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
868d8e32 803 }
804 break;
805
806 default:
7afac3c3 807 gcc_unreachable ();
868d8e32 808 }
809 }
810 else
d868a170 811 {
aea2fd96 812 /* Reg/reg equal comparison. */
d868a170 813 if (compare_code == EQ
814 && register_operand (y, SImode))
29bb088d 815 return gen_rtx_fmt_ee (code, CCmode, x, y);
58f4ce52 816
aea2fd96 817 /* Reg/zero signed comparison. */
d868a170 818 if ((compare_code == EQ || compare_code == LT)
819 && y == const0_rtx)
29bb088d 820 return gen_rtx_fmt_ee (code, CCmode, x, y);
58f4ce52 821
aea2fd96 822 /* Reg/smallconst equal comparison. */
d868a170 823 if (compare_code == EQ
bd9c4764 824 && satisfies_constraint_P (y))
d868a170 825 {
826 rtx tmp = gen_reg_rtx (SImode);
aea2fd96 827
467cdcb9 828 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
29bb088d 829 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
d868a170 830 }
58f4ce52 831
aea2fd96 832 /* Reg/const equal comparison. */
d868a170 833 if (compare_code == EQ
834 && CONSTANT_P (y))
835 {
836 rtx tmp = force_reg (GET_MODE (x), y);
aea2fd96 837
29bb088d 838 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
d868a170 839 }
840 }
841
8ec9afef 842 if (CONSTANT_P (y))
d868a170 843 {
8ec9afef 844 if (must_swap)
d868a170 845 y = force_reg (GET_MODE (x), y);
8ec9afef 846 else
847 {
4c6c8621 848 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
849
8ec9afef 850 if (! ok_const)
851 y = force_reg (GET_MODE (x), y);
852 }
d868a170 853 }
854
855 switch (compare_code)
856 {
857 case EQ :
8ec9afef 858 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
d868a170 859 break;
860 case LT :
8ec9afef 861 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
d868a170 862 break;
863 case LTU :
8ec9afef 864 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
d868a170 865 break;
6441a98f 866
867 default:
7afac3c3 868 gcc_unreachable ();
d868a170 869 }
870
29bb088d 871 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
d868a170 872}
74f4459c 873
874bool
875gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
876{
877 enum machine_mode mode = GET_MODE (op0);
878
879 gcc_assert (mode == SImode);
880 switch (code)
881 {
882 case EQ:
883 if (!register_operand (op1, mode))
884 op1 = force_reg (mode, op1);
885
886 if (TARGET_M32RX || TARGET_M32R2)
887 {
888 if (!reg_or_zero_operand (op2, mode))
889 op2 = force_reg (mode, op2);
890
891 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
892 return true;
893 }
452bfb8b 894 if (CONST_INT_P (op2) && INTVAL (op2) == 0)
74f4459c 895 {
896 emit_insn (gen_seq_zero_insn (op0, op1));
897 return true;
898 }
899
900 if (!reg_or_eq_int16_operand (op2, mode))
901 op2 = force_reg (mode, op2);
902
903 emit_insn (gen_seq_insn (op0, op1, op2));
904 return true;
905
906 case NE:
452bfb8b 907 if (!CONST_INT_P (op2)
74f4459c 908 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
909 {
910 rtx reg;
911
912 if (reload_completed || reload_in_progress)
913 return false;
914
915 reg = gen_reg_rtx (SImode);
916 emit_insn (gen_xorsi3 (reg, op1, op2));
917 op1 = reg;
918
919 if (!register_operand (op1, mode))
920 op1 = force_reg (mode, op1);
921
922 emit_insn (gen_sne_zero_insn (op0, op1));
923 return true;
924 }
925 return false;
926
927 case LT:
928 case GT:
929 if (code == GT)
930 {
931 rtx tmp = op2;
932 op2 = op1;
933 op1 = tmp;
934 code = LT;
935 }
936
937 if (!register_operand (op1, mode))
938 op1 = force_reg (mode, op1);
939
940 if (!reg_or_int16_operand (op2, mode))
941 op2 = force_reg (mode, op2);
942
943 emit_insn (gen_slt_insn (op0, op1, op2));
944 return true;
945
946 case LTU:
947 case GTU:
948 if (code == GTU)
949 {
950 rtx tmp = op2;
951 op2 = op1;
952 op1 = tmp;
953 code = LTU;
954 }
955
956 if (!register_operand (op1, mode))
957 op1 = force_reg (mode, op1);
958
959 if (!reg_or_int16_operand (op2, mode))
960 op2 = force_reg (mode, op2);
961
962 emit_insn (gen_sltu_insn (op0, op1, op2));
963 return true;
964
965 case GE:
966 case GEU:
967 if (!register_operand (op1, mode))
968 op1 = force_reg (mode, op1);
969
970 if (!reg_or_int16_operand (op2, mode))
971 op2 = force_reg (mode, op2);
972
973 if (code == GE)
974 emit_insn (gen_sge_insn (op0, op1, op2));
975 else
976 emit_insn (gen_sgeu_insn (op0, op1, op2));
977 return true;
978
979 case LE:
980 case LEU:
981 if (!register_operand (op1, mode))
982 op1 = force_reg (mode, op1);
983
452bfb8b 984 if (CONST_INT_P (op2))
74f4459c 985 {
986 HOST_WIDE_INT value = INTVAL (op2);
987 if (value >= 2147483647)
988 {
989 emit_move_insn (op0, const1_rtx);
990 return true;
991 }
992
993 op2 = GEN_INT (value + 1);
994 if (value < -32768 || value >= 32767)
995 op2 = force_reg (mode, op2);
996
997 if (code == LEU)
998 emit_insn (gen_sltu_insn (op0, op1, op2));
999 else
1000 emit_insn (gen_slt_insn (op0, op1, op2));
1001 return true;
1002 }
1003
1004 if (!register_operand (op2, mode))
1005 op2 = force_reg (mode, op2);
1006
1007 if (code == LEU)
1008 emit_insn (gen_sleu_insn (op0, op1, op2));
1009 else
1010 emit_insn (gen_sle_insn (op0, op1, op2));
1011 return true;
1012
1013 default:
1014 gcc_unreachable ();
1015 }
1016}
1017
7dbe3569 1018\f
1019/* Split a 2 word move (DI or DF) into component parts. */
1020
1021rtx
aea2fd96 1022gen_split_move_double (rtx operands[])
7dbe3569 1023{
1024 enum machine_mode mode = GET_MODE (operands[0]);
1025 rtx dest = operands[0];
1026 rtx src = operands[1];
1027 rtx val;
1028
df5991ff 1029 /* We might have (SUBREG (MEM)) here, so just get rid of the
1030 subregs to make this code simpler. It is safe to call
1031 alter_subreg any time after reload. */
1032 if (GET_CODE (dest) == SUBREG)
c6a6cdaa 1033 alter_subreg (&dest, true);
df5991ff 1034 if (GET_CODE (src) == SUBREG)
c6a6cdaa 1035 alter_subreg (&src, true);
df5991ff 1036
7dbe3569 1037 start_sequence ();
452bfb8b 1038 if (REG_P (dest))
7dbe3569 1039 {
df5991ff 1040 int dregno = REGNO (dest);
1041
aea2fd96 1042 /* Reg = reg. */
452bfb8b 1043 if (REG_P (src))
7dbe3569 1044 {
df5991ff 1045 int sregno = REGNO (src);
1046
1047 int reverse = (dregno == sregno + 1);
1048
7dbe3569 1049 /* We normally copy the low-numbered register first. However, if
1050 the first register operand 0 is the same as the second register of
1051 operand 1, we must copy in the opposite order. */
7dbe3569 1052 emit_insn (gen_rtx_SET (VOIDmode,
1053 operand_subword (dest, reverse, TRUE, mode),
1054 operand_subword (src, reverse, TRUE, mode)));
1055
1056 emit_insn (gen_rtx_SET (VOIDmode,
1057 operand_subword (dest, !reverse, TRUE, mode),
1058 operand_subword (src, !reverse, TRUE, mode)));
1059 }
1060
aea2fd96 1061 /* Reg = constant. */
452bfb8b 1062 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
7dbe3569 1063 {
1064 rtx words[2];
1065 split_double (src, &words[0], &words[1]);
1066 emit_insn (gen_rtx_SET (VOIDmode,
1067 operand_subword (dest, 0, TRUE, mode),
1068 words[0]));
1069
1070 emit_insn (gen_rtx_SET (VOIDmode,
1071 operand_subword (dest, 1, TRUE, mode),
1072 words[1]));
1073 }
1074
aea2fd96 1075 /* Reg = mem. */
452bfb8b 1076 else if (MEM_P (src))
7dbe3569 1077 {
1078 /* If the high-address word is used in the address, we must load it
1079 last. Otherwise, load it first. */
e513d163 1080 int reverse
1081 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
7dbe3569 1082
1083 /* We used to optimize loads from single registers as
1084
1085 ld r1,r3+; ld r2,r3
1086
1087 if r3 were not used subsequently. However, the REG_NOTES aren't
dfd1079d 1088 propagated correctly by the reload phase, and it can cause bad
7dbe3569 1089 code to be generated. We could still try:
1090
1091 ld r1,r3+; ld r2,r3; addi r3,-4
1092
1093 which saves 2 bytes and doesn't force longword alignment. */
1094 emit_insn (gen_rtx_SET (VOIDmode,
1095 operand_subword (dest, reverse, TRUE, mode),
e513d163 1096 adjust_address (src, SImode,
1097 reverse * UNITS_PER_WORD)));
7dbe3569 1098
1099 emit_insn (gen_rtx_SET (VOIDmode,
1100 operand_subword (dest, !reverse, TRUE, mode),
e513d163 1101 adjust_address (src, SImode,
1102 !reverse * UNITS_PER_WORD)));
7dbe3569 1103 }
7dbe3569 1104 else
7afac3c3 1105 gcc_unreachable ();
7dbe3569 1106 }
1107
aea2fd96 1108 /* Mem = reg. */
7dbe3569 1109 /* We used to optimize loads from single registers as
1110
1111 st r1,r3; st r2,+r3
1112
1113 if r3 were not used subsequently. However, the REG_NOTES aren't
dfd1079d 1114 propagated correctly by the reload phase, and it can cause bad
7dbe3569 1115 code to be generated. We could still try:
1116
1117 st r1,r3; st r2,+r3; addi r3,-4
1118
1119 which saves 2 bytes and doesn't force longword alignment. */
be96c8c6 1120 else if (MEM_P (dest) && REG_P (src))
7dbe3569 1121 {
7dbe3569 1122 emit_insn (gen_rtx_SET (VOIDmode,
e513d163 1123 adjust_address (dest, SImode, 0),
7dbe3569 1124 operand_subword (src, 0, TRUE, mode)));
1125
1126 emit_insn (gen_rtx_SET (VOIDmode,
e513d163 1127 adjust_address (dest, SImode, UNITS_PER_WORD),
7dbe3569 1128 operand_subword (src, 1, TRUE, mode)));
1129 }
1130
1131 else
7afac3c3 1132 gcc_unreachable ();
7dbe3569 1133
31d3e01c 1134 val = get_insns ();
7dbe3569 1135 end_sequence ();
1136 return val;
1137}
1138
d868a170 1139\f
f054eb3c 1140static int
39cba157 1141m32r_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
f054eb3c 1142 tree type, bool named ATTRIBUTE_UNUSED)
d868a170 1143{
39cba157 1144 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1145
f054eb3c 1146 int words;
03033f8f 1147 unsigned int size =
1148 (((mode == BLKmode && type)
1149 ? (unsigned int) int_size_in_bytes (type)
1150 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1151 / UNITS_PER_WORD;
d868a170 1152
1153 if (*cum >= M32R_MAX_PARM_REGS)
f054eb3c 1154 words = 0;
d868a170 1155 else if (*cum + size > M32R_MAX_PARM_REGS)
f054eb3c 1156 words = (*cum + size) - M32R_MAX_PARM_REGS;
d868a170 1157 else
f054eb3c 1158 words = 0;
d868a170 1159
f054eb3c 1160 return words * UNITS_PER_WORD;
d868a170 1161}
1162
1bd483c2 1163/* The ROUND_ADVANCE* macros are local to this file. */
1164/* Round SIZE up to a word boundary. */
1165#define ROUND_ADVANCE(SIZE) \
1166 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1167
1168/* Round arg MODE/TYPE up to the next word boundary. */
1169#define ROUND_ADVANCE_ARG(MODE, TYPE) \
1170 ((MODE) == BLKmode \
1171 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1172 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1173
1174/* Round CUM up to the necessary point for argument MODE/TYPE. */
1175#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1176
1177/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1178 a reg. This includes arguments that have to be passed by reference as the
1179 pointer to them is passed in a reg if one is available (and that is what
1180 we're given).
1181 This macro is only used in this file. */
1182#define PASS_IN_REG_P(CUM, MODE, TYPE) \
1183 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1184
1185/* Determine where to put an argument to a function.
1186 Value is zero to push the argument on the stack,
1187 or a hard register in which to store the argument.
1188
1189 MODE is the argument's machine mode.
1190 TYPE is the data type of the argument (as a tree).
1191 This is null for libcalls where that information may
1192 not be available.
1193 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1194 the preceding args and about the function being called.
1195 NAMED is nonzero if this argument is a named parameter
1196 (otherwise it is an extra parameter matching an ellipsis). */
1197/* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1198 and the rest are pushed. */
1199
1200static rtx
39cba157 1201m32r_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
09c20b62 1202 const_tree type ATTRIBUTE_UNUSED,
1203 bool named ATTRIBUTE_UNUSED)
1bd483c2 1204{
39cba157 1205 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1206
1bd483c2 1207 return (PASS_IN_REG_P (*cum, mode, type)
1208 ? gen_rtx_REG (mode, ROUND_ADVANCE_CUM (*cum, mode, type))
1209 : NULL_RTX);
1210}
1211
1212/* Update the data in CUM to advance over an argument
1213 of mode MODE and data type TYPE.
1214 (TYPE is null for libcalls where that information may not be available.) */
1215
1216static void
39cba157 1217m32r_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1bd483c2 1218 const_tree type, bool named ATTRIBUTE_UNUSED)
1219{
39cba157 1220 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1221
1bd483c2 1222 *cum = (ROUND_ADVANCE_CUM (*cum, mode, type)
1223 + ROUND_ADVANCE_ARG (mode, type));
1224}
1225
efc813ec 1226/* Worker function for TARGET_RETURN_IN_MEMORY. */
1227
1228static bool
fb80456a 1229m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
efc813ec 1230{
39cba157 1231 cumulative_args_t dummy = pack_cumulative_args (NULL);
1232
1233 return m32r_pass_by_reference (dummy, TYPE_MODE (type), type, false);
efc813ec 1234}
1235
fb97ed3e 1236/* Worker function for TARGET_FUNCTION_VALUE. */
1237
1238static rtx
1239m32r_function_value (const_tree valtype,
1240 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1241 bool outgoing ATTRIBUTE_UNUSED)
1242{
1243 return gen_rtx_REG (TYPE_MODE (valtype), 0);
1244}
1245
1246/* Worker function for TARGET_LIBCALL_VALUE. */
1247
1248static rtx
1249m32r_libcall_value (enum machine_mode mode,
1250 const_rtx fun ATTRIBUTE_UNUSED)
1251{
1252 return gen_rtx_REG (mode, 0);
1253}
1254
1255/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1256
1257 ??? What about r1 in DI/DF values. */
1258
1259static bool
1260m32r_function_value_regno_p (const unsigned int regno)
1261{
1262 return (regno == 0);
1263}
1264
d868a170 1265/* Do any needed setup for a variadic function. For the M32R, we must
1266 create a register parameter block, and then copy any anonymous arguments
1267 in registers to memory.
1268
1269 CUM has not been updated for the last named argument which has type TYPE
1270 and mode MODE, and we rely on this fact. */
1271
efc813ec 1272static void
39cba157 1273m32r_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
aea2fd96 1274 tree type, int *pretend_size, int no_rtl)
d868a170 1275{
1276 int first_anon_arg;
1277
1278 if (no_rtl)
1279 return;
1280
1281 /* All BLKmode values are passed by reference. */
7afac3c3 1282 gcc_assert (mode != BLKmode);
d868a170 1283
39cba157 1284 first_anon_arg = (ROUND_ADVANCE_CUM (*get_cumulative_args (cum), mode, type)
7ccc713a 1285 + ROUND_ADVANCE_ARG (mode, type));
d868a170 1286
1287 if (first_anon_arg < M32R_MAX_PARM_REGS)
1288 {
1289 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1290 int first_reg_offset = first_anon_arg;
1291 /* Size in words to "pretend" allocate. */
1292 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1293 rtx regblock;
1294
58f4ce52 1295 regblock = gen_frame_mem (BLKmode,
29c05e22 1296 plus_constant (Pmode, arg_pointer_rtx,
58f4ce52 1297 FIRST_PARM_OFFSET (0)));
ab6ab77e 1298 set_mem_alias_set (regblock, get_varargs_alias_set ());
530178a9 1299 move_block_from_reg (first_reg_offset, regblock, size);
d868a170 1300
1301 *pretend_size = (size * UNITS_PER_WORD);
1302 }
1303}
acfbd054 1304
947391dc 1305\f
4a655456 1306/* Return true if INSN is real instruction bearing insn. */
947391dc 1307
4a655456 1308static int
aea2fd96 1309m32r_is_insn (rtx insn)
4a655456 1310{
f5417e32 1311 return (NONDEBUG_INSN_P (insn)
4a655456 1312 && GET_CODE (PATTERN (insn)) != USE
1313 && GET_CODE (PATTERN (insn)) != CLOBBER
1314 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1315}
1316
1317/* Increase the priority of long instructions so that the
1318 short instructions are scheduled ahead of the long ones. */
947391dc 1319
747af5e7 1320static int
aea2fd96 1321m32r_adjust_priority (rtx insn, int priority)
947391dc 1322{
4a655456 1323 if (m32r_is_insn (insn)
1324 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1325 priority <<= 3;
947391dc 1326
1327 return priority;
1328}
1329
1330\f
747af5e7 1331/* Indicate how many instructions can be issued at the same time.
1332 This is sort of a lie. The m32r can issue only 1 long insn at
1333 once, but it can issue 2 short insns. The default therefore is
1334 set at 2, but this can be overridden by the command line option
aea2fd96 1335 -missue-rate=1. */
1336
747af5e7 1337static int
aea2fd96 1338m32r_issue_rate (void)
747af5e7 1339{
1340 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
947391dc 1341}
947391dc 1342\f
d868a170 1343/* Cost functions. */
218e3e4e 1344/* Memory is 3 times as expensive as registers.
5e5dc6b5 1345 ??? Is that the right way to look at it? */
1346
1347static int
1348m32r_memory_move_cost (enum machine_mode mode,
1349 reg_class_t rclass ATTRIBUTE_UNUSED,
1350 bool in ATTRIBUTE_UNUSED)
1351{
1352 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
1353 return 6;
1354 else
1355 return 12;
1356}
1357
fab7adbf 1358static bool
20d892d1 1359m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
1360 int opno ATTRIBUTE_UNUSED, int *total,
f529eb25 1361 bool speed ATTRIBUTE_UNUSED)
fab7adbf 1362{
1363 switch (code)
1364 {
1365 /* Small integers are as cheap as registers. 4 byte values can be
1366 fetched as immediate constants - let's give that the cost of an
1367 extra insn. */
1368 case CONST_INT:
1369 if (INT16_P (INTVAL (x)))
1370 {
1371 *total = 0;
1372 return true;
1373 }
8e262b5e 1374 /* FALLTHRU */
fab7adbf 1375
1376 case CONST:
1377 case LABEL_REF:
1378 case SYMBOL_REF:
1379 *total = COSTS_N_INSNS (1);
1380 return true;
1381
1382 case CONST_DOUBLE:
1383 {
1384 rtx high, low;
aea2fd96 1385
fab7adbf 1386 split_double (x, &high, &low);
1387 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1388 + !INT16_P (INTVAL (low)));
1389 return true;
1390 }
1391
1392 case MULT:
1393 *total = COSTS_N_INSNS (3);
1394 return true;
1395
1396 case DIV:
1397 case UDIV:
1398 case MOD:
1399 case UMOD:
1400 *total = COSTS_N_INSNS (10);
1401 return true;
1402
1403 default:
1404 return false;
1405 }
1406}
d868a170 1407\f
1408/* Type of function DECL.
1409
1410 The result is cached. To reset the cache at the end of a function,
1411 call with DECL = NULL_TREE. */
1412
1413enum m32r_function_type
aea2fd96 1414m32r_compute_function_type (tree decl)
d868a170 1415{
1416 /* Cached value. */
1417 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1418 /* Last function we were called for. */
1419 static tree last_fn = NULL_TREE;
1420
1421 /* Resetting the cached value? */
1422 if (decl == NULL_TREE)
1423 {
1424 fn_type = M32R_FUNCTION_UNKNOWN;
1425 last_fn = NULL_TREE;
1426 return fn_type;
1427 }
1428
1429 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1430 return fn_type;
1431
1432 /* Compute function type. */
e3c541f0 1433 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
d868a170 1434 ? M32R_FUNCTION_INTERRUPT
1435 : M32R_FUNCTION_NORMAL);
1436
1437 last_fn = decl;
1438 return fn_type;
1439}
1440\f/* Function prologue/epilogue handlers. */
1441
1442/* M32R stack frames look like:
1443
1444 Before call After call
1445 +-----------------------+ +-----------------------+
1446 | | | |
1447 high | local variables, | | local variables, |
1448 mem | reg save area, etc. | | reg save area, etc. |
1449 | | | |
1450 +-----------------------+ +-----------------------+
1451 | | | |
1452 | arguments on stack. | | arguments on stack. |
1453 | | | |
1454 SP+0->+-----------------------+ +-----------------------+
1455 | reg parm save area, |
58f4ce52 1456 | only created for |
1457 | variable argument |
1458 | functions |
d868a170 1459 +-----------------------+
1460 | previous frame ptr |
58f4ce52 1461 +-----------------------+
1462 | |
1463 | register save area |
1464 | |
d868a170 1465 +-----------------------+
58f4ce52 1466 | return address |
1467 +-----------------------+
1468 | |
1469 | local variables |
1470 | |
1471 +-----------------------+
1472 | |
1473 | alloca allocations |
1474 | |
1475 +-----------------------+
1476 | |
1477 low | arguments on stack |
1478 memory | |
1479 SP+0->+-----------------------+
d868a170 1480
1481Notes:
14821) The "reg parm save area" does not exist for non variable argument fns.
14832) The "reg parm save area" can be eliminated completely if we saved regs
1484 containing anonymous args separately but that complicates things too
1485 much (so it's not done).
14863) The return address is saved after the register save area so as to have as
aea2fd96 1487 many insns as possible between the restoration of `lr' and the `jmp lr'. */
d868a170 1488
1489/* Structure to be filled in by m32r_compute_frame_size with register
1490 save masks, and offsets for the current function. */
1491struct m32r_frame_info
1492{
aea2fd96 1493 unsigned int total_size; /* # bytes that the entire frame takes up. */
1494 unsigned int extra_size; /* # bytes of extra stuff. */
1495 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1496 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1497 unsigned int reg_size; /* # bytes needed to store regs. */
1498 unsigned int var_size; /* # bytes that variables take up. */
1499 unsigned int gmask; /* Mask of saved gp registers. */
1500 unsigned int save_fp; /* Nonzero if fp must be saved. */
1501 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1502 int initialized; /* Nonzero if frame size already calculated. */
d868a170 1503};
1504
1505/* Current frame information calculated by m32r_compute_frame_size. */
1506static struct m32r_frame_info current_frame_info;
1507
1508/* Zero structure to initialize current_frame_info. */
1509static struct m32r_frame_info zero_frame_info;
1510
1511#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
aea2fd96 1512#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
d868a170 1513
1514/* Tell prologue and epilogue if register REGNO should be saved / restored.
1515 The return address and frame pointer are treated separately.
1516 Don't consider them here. */
1517#define MUST_SAVE_REGISTER(regno, interrupt_p) \
bca30b06 1518 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
3072d30e 1519 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
d868a170 1520
3072d30e 1521#define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
18d50ae6 1522#define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
d868a170 1523
aea2fd96 1524#define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1525#define LONG_INSN_SIZE 4 /* Size of long instructions. */
868d8e32 1526
d868a170 1527/* Return the bytes needed to compute the frame pointer from the current
1528 stack pointer.
1529
1530 SIZE is the size needed for local variables. */
1531
1532unsigned int
aea2fd96 1533m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
d868a170 1534{
58f4ce52 1535 unsigned int regno;
d868a170 1536 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
72061572 1537 unsigned int reg_size;
d868a170 1538 unsigned int gmask;
1539 enum m32r_function_type fn_type;
1540 int interrupt_p;
18d50ae6 1541 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1542 | crtl->profile);
d868a170 1543
1544 var_size = M32R_STACK_ALIGN (size);
abe32cce 1545 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size);
1546 pretend_size = crtl->args.pretend_args_size;
d868a170 1547 extra_size = FIRST_PARM_OFFSET (0);
1548 total_size = extra_size + pretend_size + args_size + var_size;
1549 reg_size = 0;
1550 gmask = 0;
1551
1552 /* See if this is an interrupt handler. Call used registers must be saved
1553 for them too. */
1554 fn_type = m32r_compute_function_type (current_function_decl);
1555 interrupt_p = M32R_INTERRUPT_P (fn_type);
1556
1557 /* Calculate space needed for registers. */
d868a170 1558 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1559 {
467dc9aa 1560 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1561 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
d868a170 1562 {
1563 reg_size += UNITS_PER_WORD;
1564 gmask |= 1 << regno;
1565 }
1566 }
1567
1568 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
467dc9aa 1569 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
d868a170 1570
1571 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1572 * UNITS_PER_WORD);
1573 total_size += reg_size;
1574
b4d5d8b8 1575 /* ??? Not sure this is necessary, and I don't think the epilogue
d868a170 1576 handler will do the right thing if this changes total_size. */
1577 total_size = M32R_STACK_ALIGN (total_size);
1578
72061572 1579 /* frame_size = total_size - (pretend_size + reg_size); */
868d8e32 1580
d868a170 1581 /* Save computed information. */
1582 current_frame_info.total_size = total_size;
1583 current_frame_info.extra_size = extra_size;
1584 current_frame_info.pretend_size = pretend_size;
1585 current_frame_info.var_size = var_size;
1586 current_frame_info.args_size = args_size;
1587 current_frame_info.reg_size = reg_size;
1588 current_frame_info.gmask = gmask;
1589 current_frame_info.initialized = reload_completed;
1590
1591 /* Ok, we're done. */
1592 return total_size;
1593}
cd90919d 1594
1595/* Worker function for TARGET_CAN_ELIMINATE. */
1596
1597bool
1598m32r_can_eliminate (const int from, const int to)
1599{
1600 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
1601 ? ! frame_pointer_needed
1602 : true);
1603}
1604
d868a170 1605\f
467dc9aa 1606/* The table we use to reference PIC data. */
1607static rtx global_offset_table;
58f4ce52 1608
6440ef45 1609static void
1610m32r_reload_lr (rtx sp, int size)
1611{
1612 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1613
1614 if (size == 0)
58f4ce52 1615 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp)));
84e0b98d 1616 else if (size < 32768)
58f4ce52 1617 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode,
1618 gen_rtx_PLUS (Pmode, sp,
1619 GEN_INT (size)))));
6440ef45 1620 else
58f4ce52 1621 {
6440ef45 1622 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1623
1624 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1625 emit_insn (gen_addsi3 (tmp, tmp, sp));
58f4ce52 1626 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp)));
6440ef45 1627 }
1628
18b42941 1629 emit_use (lr);
6440ef45 1630}
1631
467dc9aa 1632void
1633m32r_load_pic_register (void)
1634{
1635 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1636 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
73a1a86f 1637 GEN_INT (TARGET_MODEL_SMALL)));
58f4ce52 1638
467dc9aa 1639 /* Need to emit this whether or not we obey regdecls,
1640 since setjmp/longjmp can cause life info to screw up. */
18b42941 1641 emit_use (pic_offset_table_rtx);
467dc9aa 1642}
1643
7dbe3569 1644/* Expand the m32r prologue as a series of insns. */
d868a170 1645
1646void
aea2fd96 1647m32r_expand_prologue (void)
d868a170 1648{
1649 int regno;
7dbe3569 1650 int frame_size;
947391dc 1651 unsigned int gmask;
18d50ae6 1652 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1653 | crtl->profile);
d868a170 1654
7dbe3569 1655 if (! current_frame_info.initialized)
1656 m32r_compute_frame_size (get_frame_size ());
868d8e32 1657
7dbe3569 1658 gmask = current_frame_info.gmask;
d868a170 1659
1660 /* These cases shouldn't happen. Catch them now. */
7afac3c3 1661 gcc_assert (current_frame_info.total_size || !gmask);
d868a170 1662
d868a170 1663 /* Allocate space for register arguments if this is a variadic function. */
1664 if (current_frame_info.pretend_size != 0)
31a162bd 1665 {
1666 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1667 the wrong result on a 64-bit host. */
1668 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1669 emit_insn (gen_addsi3 (stack_pointer_rtx,
1670 stack_pointer_rtx,
1671 GEN_INT (-pretend_size)));
1672 }
d868a170 1673
1674 /* Save any registers we need to and set up fp. */
d868a170 1675 if (current_frame_info.save_fp)
7dbe3569 1676 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
d868a170 1677
1678 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1679
1680 /* Save any needed call-saved regs (and call-used if this is an
1681 interrupt handler). */
1682 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1683 {
1684 if ((gmask & (1 << regno)) != 0)
7dbe3569 1685 emit_insn (gen_movsi_push (stack_pointer_rtx,
1686 gen_rtx_REG (Pmode, regno)));
d868a170 1687 }
1688
1689 if (current_frame_info.save_lr)
7dbe3569 1690 emit_insn (gen_movsi_push (stack_pointer_rtx,
1691 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
d868a170 1692
1693 /* Allocate the stack frame. */
7dbe3569 1694 frame_size = (current_frame_info.total_size
1695 - (current_frame_info.pretend_size
1696 + current_frame_info.reg_size));
1697
d868a170 1698 if (frame_size == 0)
aea2fd96 1699 ; /* Nothing to do. */
d868a170 1700 else if (frame_size <= 32768)
7dbe3569 1701 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1702 GEN_INT (-frame_size)));
d868a170 1703 else
7dbe3569 1704 {
1705 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
aea2fd96 1706
7dbe3569 1707 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1708 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1709 }
d868a170 1710
1711 if (frame_pointer_needed)
7dbe3569 1712 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1713
18d50ae6 1714 if (crtl->profile)
467dc9aa 1715 /* Push lr for mcount (form_pc, x). */
1716 emit_insn (gen_movsi_push (stack_pointer_rtx,
1717 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
58f4ce52 1718
467dc9aa 1719 if (pic_reg_used)
6440ef45 1720 {
1721 m32r_load_pic_register ();
1722 m32r_reload_lr (stack_pointer_rtx,
18d50ae6 1723 (crtl->profile ? 0 : frame_size));
6440ef45 1724 }
467dc9aa 1725
18d50ae6 1726 if (crtl->profile && !pic_reg_used)
7dbe3569 1727 emit_insn (gen_blockage ());
1728}
1729
1730\f
1731/* Set up the stack and frame pointer (if desired) for the function.
1732 Note, if this is changed, you need to mirror the changes in
1733 m32r_compute_frame_size which calculates the prolog size. */
1734
17d9b0c3 1735static void
aea2fd96 1736m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
7dbe3569 1737{
1738 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1739
1740 /* If this is an interrupt handler, mark it as such. */
1741 if (M32R_INTERRUPT_P (fn_type))
aea2fd96 1742 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
7dbe3569 1743
1744 if (! current_frame_info.initialized)
1745 m32r_compute_frame_size (size);
d868a170 1746
7dbe3569 1747 /* This is only for the human reader. */
1748 fprintf (file,
1749 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1750 ASM_COMMENT_START,
1751 current_frame_info.var_size,
1752 current_frame_info.reg_size / 4,
1753 current_frame_info.args_size,
1754 current_frame_info.extra_size);
d868a170 1755}
1756\f
58f4ce52 1757/* Output RTL to pop register REGNO from the stack. */
d868a170 1758
17d9b0c3 1759static void
58f4ce52 1760pop (int regno)
1761{
1762 rtx x;
1763
1764 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno),
1765 stack_pointer_rtx));
ef51d1e3 1766 add_reg_note (x, REG_INC, stack_pointer_rtx);
58f4ce52 1767}
1768
1769/* Expand the m32r epilogue as a series of insns. */
1770
1771void
1772m32r_expand_epilogue (void)
d868a170 1773{
1774 int regno;
1775 int noepilogue = FALSE;
1776 int total_size;
d868a170 1777
7afac3c3 1778 gcc_assert (current_frame_info.initialized);
d868a170 1779 total_size = current_frame_info.total_size;
1780
1781 if (total_size == 0)
1782 {
1783 rtx insn = get_last_insn ();
1784
1785 /* If the last insn was a BARRIER, we don't have to write any code
1786 because a jump (aka return) was put there. */
452bfb8b 1787 if (insn && NOTE_P (insn))
d868a170 1788 insn = prev_nonnote_insn (insn);
452bfb8b 1789 if (insn && BARRIER_P (insn))
d868a170 1790 noepilogue = TRUE;
1791 }
1792
1793 if (!noepilogue)
1794 {
d868a170 1795 unsigned int var_size = current_frame_info.var_size;
1796 unsigned int args_size = current_frame_info.args_size;
1797 unsigned int gmask = current_frame_info.gmask;
18d50ae6 1798 int can_trust_sp_p = !cfun->calls_alloca;
58f4ce52 1799
1800 if (flag_exceptions)
1801 emit_insn (gen_blockage ());
d868a170 1802
1803 /* The first thing to do is point the sp at the bottom of the register
1804 save area. */
1805 if (can_trust_sp_p)
1806 {
1807 unsigned int reg_offset = var_size + args_size;
58f4ce52 1808
d868a170 1809 if (reg_offset == 0)
aea2fd96 1810 ; /* Nothing to do. */
d868a170 1811 else if (reg_offset < 32768)
58f4ce52 1812 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1813 GEN_INT (reg_offset)));
69e870b0 1814 else
58f4ce52 1815 {
1816 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1817
1818 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1819 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1820 tmp));
1821 }
d868a170 1822 }
1823 else if (frame_pointer_needed)
1824 {
1825 unsigned int reg_offset = var_size + args_size;
aea2fd96 1826
d868a170 1827 if (reg_offset == 0)
58f4ce52 1828 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
d868a170 1829 else if (reg_offset < 32768)
58f4ce52 1830 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
1831 GEN_INT (reg_offset)));
69e870b0 1832 else
58f4ce52 1833 {
1834 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1835
1836 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1837 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1838 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1839 tmp));
1840 }
d868a170 1841 }
1842 else
7afac3c3 1843 gcc_unreachable ();
d868a170 1844
1845 if (current_frame_info.save_lr)
58f4ce52 1846 pop (RETURN_ADDR_REGNUM);
d868a170 1847
1848 /* Restore any saved registers, in reverse order of course. */
1849 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1850 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1851 {
1852 if ((gmask & (1L << regno)) != 0)
58f4ce52 1853 pop (regno);
d868a170 1854 }
1855
1856 if (current_frame_info.save_fp)
58f4ce52 1857 pop (FRAME_POINTER_REGNUM);
d868a170 1858
1859 /* Remove varargs area if present. */
d868a170 1860 if (current_frame_info.pretend_size != 0)
58f4ce52 1861 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1862 GEN_INT (current_frame_info.pretend_size)));
1863
1864 emit_insn (gen_blockage ());
d868a170 1865 }
58f4ce52 1866}
1867
1868/* Do any necessary cleanup after a function to restore stack, frame,
1869 and regs. */
d868a170 1870
58f4ce52 1871static void
1872m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED,
1873 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1874{
d868a170 1875 /* Reset state info for each function. */
1876 current_frame_info = zero_frame_info;
1877 m32r_compute_function_type (NULL_TREE);
1878}
947391dc 1879\f
e911aedf 1880/* Return nonzero if this function is known to have a null or 1 instruction
947391dc 1881 epilogue. */
1882
1883int
aea2fd96 1884direct_return (void)
947391dc 1885{
1886 if (!reload_completed)
1887 return FALSE;
1888
58f4ce52 1889 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl)))
1890 return FALSE;
1891
947391dc 1892 if (! current_frame_info.initialized)
1893 m32r_compute_frame_size (get_frame_size ());
1894
58f4ce52 1895 return current_frame_info.total_size == 0;
947391dc 1896}
1897
d868a170 1898\f
aea2fd96 1899/* PIC. */
d868a170 1900
467dc9aa 1901int
1902m32r_legitimate_pic_operand_p (rtx x)
1903{
1904 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1905 return 0;
58f4ce52 1906
467dc9aa 1907 if (GET_CODE (x) == CONST
1908 && GET_CODE (XEXP (x, 0)) == PLUS
1909 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1910 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
452bfb8b 1911 && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
467dc9aa 1912 return 0;
58f4ce52 1913
467dc9aa 1914 return 1;
1915}
1916
1917rtx
1918m32r_legitimize_pic_address (rtx orig, rtx reg)
1919{
1920#ifdef DEBUG_PIC
1921 printf("m32r_legitimize_pic_address()\n");
1922#endif
1923
1924 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1925 {
1926 rtx pic_ref, address;
467dc9aa 1927 int subregs = 0;
1928
1929 if (reg == 0)
1930 {
7afac3c3 1931 gcc_assert (!reload_in_progress && !reload_completed);
1932 reg = gen_reg_rtx (Pmode);
467dc9aa 1933
1934 subregs = 1;
1935 }
1936
1937 if (subregs)
1938 address = gen_reg_rtx (Pmode);
1939 else
1940 address = reg;
1941
18d50ae6 1942 crtl->uses_pic_offset_table = 1;
72afe58b 1943
1944 if (GET_CODE (orig) == LABEL_REF
1945 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1946 {
1947 emit_insn (gen_gotoff_load_addr (reg, orig));
1948 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1949 return reg;
1950 }
1951
467dc9aa 1952 emit_insn (gen_pic_load_addr (address, orig));
1953
1954 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
e265a6da 1955 pic_ref = gen_const_mem (Pmode, address);
72061572 1956 emit_move_insn (reg, pic_ref);
467dc9aa 1957 return reg;
1958 }
1959 else if (GET_CODE (orig) == CONST)
1960 {
1961 rtx base, offset;
1962
1963 if (GET_CODE (XEXP (orig, 0)) == PLUS
1964 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1965 return orig;
1966
1967 if (reg == 0)
1968 {
7afac3c3 1969 gcc_assert (!reload_in_progress && !reload_completed);
1970 reg = gen_reg_rtx (Pmode);
467dc9aa 1971 }
1972
1973 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1974 {
1975 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1976 if (base == reg)
1977 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1978 else
1979 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1980 }
1981 else
1982 return orig;
1983
452bfb8b 1984 if (CONST_INT_P (offset))
467dc9aa 1985 {
1986 if (INT16_P (INTVAL (offset)))
29c05e22 1987 return plus_constant (Pmode, base, INTVAL (offset));
467dc9aa 1988 else
7afac3c3 1989 {
1990 gcc_assert (! reload_in_progress && ! reload_completed);
1991 offset = force_reg (Pmode, offset);
1992 }
467dc9aa 1993 }
1994
1a83b3ff 1995 return gen_rtx_PLUS (Pmode, base, offset);
467dc9aa 1996 }
1997
1998 return orig;
1999}
41e3a0c7 2000
2001static rtx
2002m32r_legitimize_address (rtx x, rtx orig_x ATTRIBUTE_UNUSED,
2003 enum machine_mode mode ATTRIBUTE_UNUSED)
2004{
2005 if (flag_pic)
2006 return m32r_legitimize_pic_address (x, NULL_RTX);
2007 else
2008 return x;
2009}
8c9a773b 2010
2011/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2012
2013static bool
4e27ffd0 2014m32r_mode_dependent_address_p (const_rtx addr, addr_space_t as ATTRIBUTE_UNUSED)
8c9a773b 2015{
2016 if (GET_CODE (addr) == LO_SUM)
2017 return true;
2018
2019 return false;
2020}
d868a170 2021\f
2022/* Nested function support. */
2023
2024/* Emit RTL insns to initialize the variable parts of a trampoline.
2025 FNADDR is an RTX for the address of the function's pure code.
2026 CXT is an RTX for the static chain value for the function. */
2027
2028void
aea2fd96 2029m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
2030 rtx fnaddr ATTRIBUTE_UNUSED,
2031 rtx cxt ATTRIBUTE_UNUSED)
d868a170 2032{
2033}
2034\f
92c473b8 2035static void
aea2fd96 2036m32r_file_start (void)
d868a170 2037{
92c473b8 2038 default_file_start ();
2039
d868a170 2040 if (flag_verbose_asm)
92c473b8 2041 fprintf (asm_out_file,
13a54dd9 2042 "%s M32R/D special options: -G %d\n",
d868a170 2043 ASM_COMMENT_START, g_switch_value);
467dc9aa 2044
2045 if (TARGET_LITTLE_ENDIAN)
2046 fprintf (asm_out_file, "\t.little\n");
d868a170 2047}
2048\f
2049/* Print operand X (an rtx) in assembler syntax to file FILE.
2050 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2051 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2052
8e8a63d1 2053static void
aea2fd96 2054m32r_print_operand (FILE * file, rtx x, int code)
d868a170 2055{
7dbe3569 2056 rtx addr;
2057
d868a170 2058 switch (code)
2059 {
173e37ab 2060 /* The 's' and 'p' codes are used by output_block_move() to
2061 indicate post-increment 's'tores and 'p're-increment loads. */
2062 case 's':
452bfb8b 2063 if (REG_P (x))
173e37ab 2064 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2065 else
a1657b95 2066 output_operand_lossage ("invalid operand to %%s code");
173e37ab 2067 return;
58f4ce52 2068
173e37ab 2069 case 'p':
452bfb8b 2070 if (REG_P (x))
173e37ab 2071 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2072 else
a1657b95 2073 output_operand_lossage ("invalid operand to %%p code");
173e37ab 2074 return;
2075
d868a170 2076 case 'R' :
2077 /* Write second word of DImode or DFmode reference,
2078 register or memory. */
452bfb8b 2079 if (REG_P (x))
d868a170 2080 fputs (reg_names[REGNO (x)+1], file);
452bfb8b 2081 else if (MEM_P (x))
d868a170 2082 {
2083 fprintf (file, "@(");
2084 /* Handle possible auto-increment. Since it is pre-increment and
2085 we have already done it, we can just use an offset of four. */
2086 /* ??? This is taken from rs6000.c I think. I don't think it is
2087 currently necessary, but keep it around. */
2088 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2089 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
29c05e22 2090 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 4));
d868a170 2091 else
29c05e22 2092 output_address (plus_constant (Pmode, XEXP (x, 0), 4));
d868a170 2093 fputc (')', file);
2094 }
2095 else
a1657b95 2096 output_operand_lossage ("invalid operand to %%R code");
d868a170 2097 return;
2098
aea2fd96 2099 case 'H' : /* High word. */
2100 case 'L' : /* Low word. */
452bfb8b 2101 if (REG_P (x))
d868a170 2102 {
aea2fd96 2103 /* L = least significant word, H = most significant word. */
d868a170 2104 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2105 fputs (reg_names[REGNO (x)], file);
2106 else
2107 fputs (reg_names[REGNO (x)+1], file);
2108 }
452bfb8b 2109 else if (CONST_INT_P (x)
d868a170 2110 || GET_CODE (x) == CONST_DOUBLE)
2111 {
2112 rtx first, second;
2113
2114 split_double (x, &first, &second);
6441a98f 2115 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
d868a170 2116 code == 'L' ? INTVAL (first) : INTVAL (second));
2117 }
2118 else
a1657b95 2119 output_operand_lossage ("invalid operand to %%H/%%L code");
d868a170 2120 return;
2121
2122 case 'A' :
2123 {
d868a170 2124 char str[30];
2125
2126 if (GET_CODE (x) != CONST_DOUBLE
2127 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
68435912 2128 fatal_insn ("bad insn for 'A'", x);
c7fbc741 2129
2130 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
d868a170 2131 fprintf (file, "%s", str);
2132 return;
2133 }
2134
aea2fd96 2135 case 'B' : /* Bottom half. */
2136 case 'T' : /* Top half. */
d868a170 2137 /* Output the argument to a `seth' insn (sets the Top half-word).
2138 For constants output arguments to a seth/or3 pair to set Top and
2139 Bottom halves. For symbols output arguments to a seth/add3 pair to
2140 set Top and Bottom halves. The difference exists because for
2141 constants seth/or3 is more readable but for symbols we need to use
c910419d 2142 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
d868a170 2143 switch (GET_CODE (x))
2144 {
2145 case CONST_INT :
2146 case CONST_DOUBLE :
2147 {
2148 rtx first, second;
2149
2150 split_double (x, &first, &second);
2151 x = WORDS_BIG_ENDIAN ? second : first;
5c5d0ae9 2152 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
d868a170 2153 (code == 'B'
2154 ? INTVAL (x) & 0xffff
2155 : (INTVAL (x) >> 16) & 0xffff));
2156 }
2157 return;
2158 case CONST :
2159 case SYMBOL_REF :
2160 if (code == 'B'
2161 && small_data_operand (x, VOIDmode))
2162 {
2163 fputs ("sda(", file);
2164 output_addr_const (file, x);
2165 fputc (')', file);
2166 return;
2167 }
2168 /* fall through */
2169 case LABEL_REF :
2170 fputs (code == 'T' ? "shigh(" : "low(", file);
2171 output_addr_const (file, x);
2172 fputc (')', file);
2173 return;
2174 default :
a1657b95 2175 output_operand_lossage ("invalid operand to %%T/%%B code");
d868a170 2176 return;
2177 }
2178 break;
2179
2180 case 'U' :
8ec9afef 2181 /* ??? wip */
d868a170 2182 /* Output a load/store with update indicator if appropriate. */
452bfb8b 2183 if (MEM_P (x))
d868a170 2184 {
2185 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2186 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2187 fputs (".a", file);
2188 }
2189 else
a1657b95 2190 output_operand_lossage ("invalid operand to %%U code");
d868a170 2191 return;
2192
2193 case 'N' :
2194 /* Print a constant value negated. */
452bfb8b 2195 if (CONST_INT_P (x))
d868a170 2196 output_addr_const (file, GEN_INT (- INTVAL (x)));
2197 else
a1657b95 2198 output_operand_lossage ("invalid operand to %%N code");
d868a170 2199 return;
2200
205bb293 2201 case 'X' :
2202 /* Print a const_int in hex. Used in comments. */
452bfb8b 2203 if (CONST_INT_P (x))
5c5d0ae9 2204 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
205bb293 2205 return;
2206
d868a170 2207 case '#' :
2208 fputs (IMMEDIATE_PREFIX, file);
2209 return;
2210
d868a170 2211 case 0 :
2212 /* Do nothing special. */
2213 break;
2214
2215 default :
2216 /* Unknown flag. */
2217 output_operand_lossage ("invalid operand output code");
2218 }
2219
2220 switch (GET_CODE (x))
2221 {
2222 case REG :
2223 fputs (reg_names[REGNO (x)], file);
2224 break;
2225
2226 case MEM :
7dbe3569 2227 addr = XEXP (x, 0);
2228 if (GET_CODE (addr) == PRE_INC)
2229 {
452bfb8b 2230 if (!REG_P (XEXP (addr, 0)))
68435912 2231 fatal_insn ("pre-increment address is not a register", x);
7dbe3569 2232
2233 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2234 }
2235 else if (GET_CODE (addr) == PRE_DEC)
2236 {
452bfb8b 2237 if (!REG_P (XEXP (addr, 0)))
68435912 2238 fatal_insn ("pre-decrement address is not a register", x);
7dbe3569 2239
2240 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2241 }
2242 else if (GET_CODE (addr) == POST_INC)
2243 {
452bfb8b 2244 if (!REG_P (XEXP (addr, 0)))
68435912 2245 fatal_insn ("post-increment address is not a register", x);
7dbe3569 2246
2247 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2248 }
d868a170 2249 else
7dbe3569 2250 {
2251 fputs ("@(", file);
2252 output_address (XEXP (x, 0));
2253 fputc (')', file);
2254 }
d868a170 2255 break;
2256
2257 case CONST_DOUBLE :
2258 /* We handle SFmode constants here as output_addr_const doesn't. */
2259 if (GET_MODE (x) == SFmode)
2260 {
2261 REAL_VALUE_TYPE d;
2262 long l;
2263
2264 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2265 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2266 fprintf (file, "0x%08lx", l);
2267 break;
2268 }
2269
2270 /* Fall through. Let output_addr_const deal with it. */
2271
2272 default :
2273 output_addr_const (file, x);
2274 break;
2275 }
2276}
2277
2278/* Print a memory address as an operand to reference that memory location. */
2279
8e8a63d1 2280static void
aea2fd96 2281m32r_print_operand_address (FILE * file, rtx addr)
d868a170 2282{
aea2fd96 2283 rtx base;
2284 rtx index = 0;
2285 int offset = 0;
d868a170 2286
2287 switch (GET_CODE (addr))
2288 {
2289 case REG :
2290 fputs (reg_names[REGNO (addr)], file);
2291 break;
2292
2293 case PLUS :
452bfb8b 2294 if (CONST_INT_P (XEXP (addr, 0)))
d868a170 2295 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
452bfb8b 2296 else if (CONST_INT_P (XEXP (addr, 1)))
d868a170 2297 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2298 else
2299 base = XEXP (addr, 0), index = XEXP (addr, 1);
452bfb8b 2300 if (REG_P (base))
d868a170 2301 {
2302 /* Print the offset first (if present) to conform to the manual. */
2303 if (index == 0)
2304 {
2305 if (offset != 0)
2306 fprintf (file, "%d,", offset);
2307 fputs (reg_names[REGNO (base)], file);
2308 }
2309 /* The chip doesn't support this, but left in for generality. */
452bfb8b 2310 else if (REG_P (index))
d868a170 2311 fprintf (file, "%s,%s",
2312 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2313 /* Not sure this can happen, but leave in for now. */
2314 else if (GET_CODE (index) == SYMBOL_REF)
2315 {
2316 output_addr_const (file, index);
2317 fputc (',', file);
2318 fputs (reg_names[REGNO (base)], file);
2319 }
2320 else
68435912 2321 fatal_insn ("bad address", addr);
d868a170 2322 }
2323 else if (GET_CODE (base) == LO_SUM)
2324 {
452bfb8b 2325 gcc_assert (!index && REG_P (XEXP (base, 0)));
d868a170 2326 if (small_data_operand (XEXP (base, 1), VOIDmode))
2327 fputs ("sda(", file);
2328 else
2329 fputs ("low(", file);
29c05e22 2330 output_addr_const (file, plus_constant (Pmode, XEXP (base, 1),
2331 offset));
d868a170 2332 fputs ("),", file);
2333 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2334 }
2335 else
68435912 2336 fatal_insn ("bad address", addr);
d868a170 2337 break;
2338
2339 case LO_SUM :
452bfb8b 2340 if (!REG_P (XEXP (addr, 0)))
68435912 2341 fatal_insn ("lo_sum not of register", addr);
d868a170 2342 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2343 fputs ("sda(", file);
2344 else
2345 fputs ("low(", file);
2346 output_addr_const (file, XEXP (addr, 1));
2347 fputs ("),", file);
2348 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2349 break;
2350
aea2fd96 2351 case PRE_INC : /* Assume SImode. */
7dbe3569 2352 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2353 break;
2354
aea2fd96 2355 case PRE_DEC : /* Assume SImode. */
7dbe3569 2356 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2357 break;
2358
aea2fd96 2359 case POST_INC : /* Assume SImode. */
7dbe3569 2360 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
d868a170 2361 break;
2362
2363 default :
2364 output_addr_const (file, addr);
2365 break;
2366 }
2367}
868d8e32 2368
8e8a63d1 2369static bool
2370m32r_print_operand_punct_valid_p (unsigned char code)
2371{
2372 return m32r_punct_chars[code];
2373}
2374
868d8e32 2375/* Return true if the operands are the constants 0 and 1. */
aea2fd96 2376
868d8e32 2377int
aea2fd96 2378zero_and_one (rtx operand1, rtx operand2)
868d8e32 2379{
2380 return
452bfb8b 2381 CONST_INT_P (operand1)
2382 && CONST_INT_P (operand2)
868d8e32 2383 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2384 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2385}
2386
868d8e32 2387/* Generate the correct assembler code to handle the conditional loading of a
2388 value into a register. It is known that the operands satisfy the
2389 conditional_move_operand() function above. The destination is operand[0].
2390 The condition is operand [1]. The 'true' value is operand [2] and the
2391 'false' value is operand [3]. */
aea2fd96 2392
868d8e32 2393char *
aea2fd96 2394emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
868d8e32 2395{
2396 static char buffer [100];
08c762a3 2397 const char * dest = reg_names [REGNO (operands [0])];
58f4ce52 2398
868d8e32 2399 buffer [0] = 0;
58f4ce52 2400
868d8e32 2401 /* Destination must be a register. */
452bfb8b 2402 gcc_assert (REG_P (operands [0]));
7afac3c3 2403 gcc_assert (conditional_move_operand (operands [2], SImode));
2404 gcc_assert (conditional_move_operand (operands [3], SImode));
58f4ce52 2405
868d8e32 2406 /* Check to see if the test is reversed. */
2407 if (GET_CODE (operands [1]) == NE)
2408 {
2409 rtx tmp = operands [2];
2410 operands [2] = operands [3];
2411 operands [3] = tmp;
2412 }
2413
60bbc120 2414 sprintf (buffer, "mvfc %s, cbr", dest);
03033f8f 2415
60bbc120 2416 /* If the true value was '0' then we need to invert the results of the move. */
2417 if (INTVAL (operands [2]) == 0)
2418 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2419 dest, dest);
03033f8f 2420
868d8e32 2421 return buffer;
2422}
2423
947391dc 2424/* Returns true if the registers contained in the two
1d60d981 2425 rtl expressions are different. */
aea2fd96 2426
947391dc 2427int
aea2fd96 2428m32r_not_same_reg (rtx a, rtx b)
947391dc 2429{
2430 int reg_a = -1;
2431 int reg_b = -2;
58f4ce52 2432
947391dc 2433 while (GET_CODE (a) == SUBREG)
2434 a = SUBREG_REG (a);
58f4ce52 2435
452bfb8b 2436 if (REG_P (a))
947391dc 2437 reg_a = REGNO (a);
58f4ce52 2438
947391dc 2439 while (GET_CODE (b) == SUBREG)
2440 b = SUBREG_REG (b);
58f4ce52 2441
452bfb8b 2442 if (REG_P (b))
947391dc 2443 reg_b = REGNO (b);
58f4ce52 2444
947391dc 2445 return reg_a != reg_b;
2446}
173e37ab 2447
2448\f
fe34fa5a 2449rtx
2450m32r_function_symbol (const char *name)
2451{
2452 int extra_flags = 0;
2453 enum m32r_model model;
2454 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2455
2456 if (TARGET_MODEL_SMALL)
2457 model = M32R_MODEL_SMALL;
2458 else if (TARGET_MODEL_MEDIUM)
2459 model = M32R_MODEL_MEDIUM;
2460 else if (TARGET_MODEL_LARGE)
2461 model = M32R_MODEL_LARGE;
2462 else
7afac3c3 2463 gcc_unreachable (); /* Shouldn't happen. */
fe34fa5a 2464 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
58f4ce52 2465
fe34fa5a 2466 if (extra_flags)
2467 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2468
2469 return sym;
2470}
2471
173e37ab 2472/* Use a library function to move some bytes. */
aea2fd96 2473
173e37ab 2474static void
a11b18dd 2475block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
173e37ab 2476{
2477 /* We want to pass the size as Pmode, which will normally be SImode
c910419d 2478 but will be DImode if we are using 64-bit longs and pointers. */
173e37ab 2479 if (GET_MODE (bytes_rtx) != VOIDmode
2480 && GET_MODE (bytes_rtx) != Pmode)
2481 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2482
ef51d1e3 2483 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL,
173e37ab 2484 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2485 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
78a8ed03 2486 TYPE_UNSIGNED (sizetype)),
173e37ab 2487 TYPE_MODE (sizetype));
173e37ab 2488}
2489
173e37ab 2490/* Expand string/block move operations.
2491
2492 operands[0] is the pointer to the destination.
2493 operands[1] is the pointer to the source.
2494 operands[2] is the number of bytes to move.
9ca439fa 2495 operands[3] is the alignment.
173e37ab 2496
9ca439fa 2497 Returns 1 upon success, 0 otherwise. */
2498
2499int
aea2fd96 2500m32r_expand_block_move (rtx operands[])
173e37ab 2501{
2502 rtx orig_dst = operands[0];
2503 rtx orig_src = operands[1];
2504 rtx bytes_rtx = operands[2];
2505 rtx align_rtx = operands[3];
452bfb8b 2506 int constp = CONST_INT_P (bytes_rtx);
173e37ab 2507 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2508 int align = INTVAL (align_rtx);
2509 int leftover;
2510 rtx src_reg;
2511 rtx dst_reg;
2512
2513 if (constp && bytes <= 0)
9ca439fa 2514 return 1;
173e37ab 2515
2516 /* Move the address into scratch registers. */
2517 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2518 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2519
2520 if (align > UNITS_PER_WORD)
2521 align = UNITS_PER_WORD;
2522
2523 /* If we prefer size over speed, always use a function call.
2524 If we do not know the size, use a function call.
2525 If the blocks are not word aligned, use a function call. */
2526 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2527 {
2528 block_move_call (dst_reg, src_reg, bytes_rtx);
9ca439fa 2529 return 0;
173e37ab 2530 }
2531
2532 leftover = bytes % MAX_MOVE_BYTES;
2533 bytes -= leftover;
58f4ce52 2534
173e37ab 2535 /* If necessary, generate a loop to handle the bulk of the copy. */
2536 if (bytes)
2537 {
e51fa923 2538 rtx label = NULL_RTX;
2539 rtx final_src = NULL_RTX;
f4a9eadc 2540 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2541 rtx rounded_total = GEN_INT (bytes);
76dad66d 2542 rtx new_dst_reg = gen_reg_rtx (SImode);
2543 rtx new_src_reg = gen_reg_rtx (SImode);
173e37ab 2544
2545 /* If we are going to have to perform this loop more than
2546 once, then generate a label and compute the address the
2547 source register will contain upon completion of the final
dfd1079d 2548 iteration. */
173e37ab 2549 if (bytes > MAX_MOVE_BYTES)
2550 {
2551 final_src = gen_reg_rtx (Pmode);
2552
2553 if (INT16_P(bytes))
f4a9eadc 2554 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
173e37ab 2555 else
2556 {
f4a9eadc 2557 emit_insn (gen_movsi (final_src, rounded_total));
173e37ab 2558 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2559 }
2560
2561 label = gen_label_rtx ();
2562 emit_label (label);
2563 }
2564
2565 /* It is known that output_block_move() will update src_reg to point
2566 to the word after the end of the source block, and dst_reg to point
2567 to the last word of the destination block, provided that the block
2568 is MAX_MOVE_BYTES long. */
008c057d 2569 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
76dad66d 2570 new_dst_reg, new_src_reg));
2571 emit_move_insn (dst_reg, new_dst_reg);
2572 emit_move_insn (src_reg, new_src_reg);
173e37ab 2573 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
58f4ce52 2574
173e37ab 2575 if (bytes > MAX_MOVE_BYTES)
2576 {
74f4459c 2577 rtx test = gen_rtx_NE (VOIDmode, src_reg, final_src);
2578 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
173e37ab 2579 }
2580 }
2581
2582 if (leftover)
008c057d 2583 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
76dad66d 2584 gen_reg_rtx (SImode),
2585 gen_reg_rtx (SImode)));
9ca439fa 2586 return 1;
173e37ab 2587}
2588
2589\f
58f4ce52 2590/* Emit load/stores for a small constant word aligned block_move.
173e37ab 2591
2592 operands[0] is the memory address of the destination.
2593 operands[1] is the memory address of the source.
2594 operands[2] is the number of bytes to move.
2595 operands[3] is a temp register.
2596 operands[4] is a temp register. */
2597
03033f8f 2598void
aea2fd96 2599m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
173e37ab 2600{
2601 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2602 int first_time;
2603 int got_extra = 0;
58f4ce52 2604
7afac3c3 2605 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
58f4ce52 2606
173e37ab 2607 /* We do not have a post-increment store available, so the first set of
2608 stores are done without any increment, then the remaining ones can use
2609 the pre-increment addressing mode.
58f4ce52 2610
e911aedf 2611 Note: expand_block_move() also relies upon this behavior when building
173e37ab 2612 loops to copy large blocks. */
2613 first_time = 1;
58f4ce52 2614
173e37ab 2615 while (bytes > 0)
2616 {
2617 if (bytes >= 8)
2618 {
2619 if (first_time)
2620 {
76dad66d 2621 output_asm_insn ("ld\t%5, %p1", operands);
2622 output_asm_insn ("ld\t%6, %p1", operands);
2623 output_asm_insn ("st\t%5, @%0", operands);
2624 output_asm_insn ("st\t%6, %s0", operands);
173e37ab 2625 }
2626 else
2627 {
76dad66d 2628 output_asm_insn ("ld\t%5, %p1", operands);
2629 output_asm_insn ("ld\t%6, %p1", operands);
2630 output_asm_insn ("st\t%5, %s0", operands);
2631 output_asm_insn ("st\t%6, %s0", operands);
173e37ab 2632 }
2633
2634 bytes -= 8;
2635 }
2636 else if (bytes >= 4)
2637 {
2638 if (bytes > 4)
2639 got_extra = 1;
58f4ce52 2640
76dad66d 2641 output_asm_insn ("ld\t%5, %p1", operands);
58f4ce52 2642
173e37ab 2643 if (got_extra)
76dad66d 2644 output_asm_insn ("ld\t%6, %p1", operands);
58f4ce52 2645
173e37ab 2646 if (first_time)
76dad66d 2647 output_asm_insn ("st\t%5, @%0", operands);
173e37ab 2648 else
76dad66d 2649 output_asm_insn ("st\t%5, %s0", operands);
173e37ab 2650
2651 bytes -= 4;
2652 }
58f4ce52 2653 else
173e37ab 2654 {
2655 /* Get the entire next word, even though we do not want all of it.
2656 The saves us from doing several smaller loads, and we assume that
2657 we cannot cause a page fault when at least part of the word is in
f4a9eadc 2658 valid memory [since we don't get called if things aren't properly
2659 aligned]. */
2660 int dst_offset = first_time ? 0 : 4;
76dad66d 2661 /* The amount of increment we have to make to the
2662 destination pointer. */
2663 int dst_inc_amount = dst_offset + bytes - 4;
2664 /* The same for the source pointer. */
2665 int src_inc_amount = bytes;
f4a9eadc 2666 int last_shift;
2667 rtx my_operands[3];
2668
2669 /* If got_extra is true then we have already loaded
173e37ab 2670 the next word as part of loading and storing the previous word. */
2671 if (! got_extra)
76dad66d 2672 output_asm_insn ("ld\t%6, @%1", operands);
173e37ab 2673
2674 if (bytes >= 2)
2675 {
2676 bytes -= 2;
2677
76dad66d 2678 output_asm_insn ("sra3\t%5, %6, #16", operands);
2679 my_operands[0] = operands[5];
f4a9eadc 2680 my_operands[1] = GEN_INT (dst_offset);
2681 my_operands[2] = operands[0];
2682 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
58f4ce52 2683
173e37ab 2684 /* If there is a byte left to store then increment the
2685 destination address and shift the contents of the source
f4a9eadc 2686 register down by 8 bits. We could not do the address
173e37ab 2687 increment in the store half word instruction, because it does
2688 not have an auto increment mode. */
2689 if (bytes > 0) /* assert (bytes == 1) */
2690 {
f4a9eadc 2691 dst_offset += 2;
2692 last_shift = 8;
173e37ab 2693 }
2694 }
f4a9eadc 2695 else
2696 last_shift = 24;
2697
2698 if (bytes > 0)
2699 {
76dad66d 2700 my_operands[0] = operands[6];
f4a9eadc 2701 my_operands[1] = GEN_INT (last_shift);
2702 output_asm_insn ("srai\t%0, #%1", my_operands);
76dad66d 2703 my_operands[0] = operands[6];
f4a9eadc 2704 my_operands[1] = GEN_INT (dst_offset);
2705 my_operands[2] = operands[0];
2706 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2707 }
76dad66d 2708
2709 /* Update the destination pointer if needed. We have to do
2710 this so that the patterns matches what we output in this
2711 function. */
2712 if (dst_inc_amount
2713 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2714 {
2715 my_operands[0] = operands[0];
2716 my_operands[1] = GEN_INT (dst_inc_amount);
2717 output_asm_insn ("addi\t%0, #%1", my_operands);
2718 }
58f4ce52 2719
76dad66d 2720 /* Update the source pointer if needed. We have to do this
2721 so that the patterns matches what we output in this
2722 function. */
2723 if (src_inc_amount
2724 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2725 {
2726 my_operands[0] = operands[1];
2727 my_operands[1] = GEN_INT (src_inc_amount);
2728 output_asm_insn ("addi\t%0, #%1", my_operands);
2729 }
58f4ce52 2730
173e37ab 2731 bytes = 0;
2732 }
2733
2734 first_time = 0;
2735 }
173e37ab 2736}
2737
d741027b 2738/* Return true if using NEW_REG in place of OLD_REG is ok. */
2739
2740int
aea2fd96 2741m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2742 unsigned int new_reg)
d741027b 2743{
2744 /* Interrupt routines can't clobber any register that isn't already used. */
2745 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
3072d30e 2746 && !df_regs_ever_live_p (new_reg))
d741027b 2747 return 0;
2748
d741027b 2749 return 1;
2750}
6440ef45 2751
2752rtx
2753m32r_return_addr (int count)
2754{
2755 if (count != 0)
2756 return const0_rtx;
58f4ce52 2757
6440ef45 2758 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2759}
06b77609 2760
2761static void
2762m32r_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2763{
2764 emit_move_insn (adjust_address (m_tramp, SImode, 0),
2765 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2766 0x017e8e17 : 0x178e7e01, SImode));
2767 emit_move_insn (adjust_address (m_tramp, SImode, 4),
2768 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2769 0x0c00ae86 : 0x86ae000c, SImode));
2770 emit_move_insn (adjust_address (m_tramp, SImode, 8),
2771 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2772 0xe627871e : 0x1e8727e6, SImode));
2773 emit_move_insn (adjust_address (m_tramp, SImode, 12),
2774 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2775 0xc616c626 : 0x26c61fc6, SImode));
2776 emit_move_insn (adjust_address (m_tramp, SImode, 16),
2777 chain_value);
2778 emit_move_insn (adjust_address (m_tramp, SImode, 20),
2779 XEXP (DECL_RTL (fndecl), 0));
2780
2781 if (m32r_cache_flush_trap >= 0)
2782 emit_insn (gen_flush_icache
2783 (validize_mem (adjust_address (m_tramp, SImode, 0)),
2784 gen_int_mode (m32r_cache_flush_trap, SImode)));
2785 else if (m32r_cache_flush_func && m32r_cache_flush_func[0])
2786 emit_library_call (m32r_function_symbol (m32r_cache_flush_func),
2787 LCT_NORMAL, VOIDmode, 3, XEXP (m_tramp, 0), Pmode,
2788 gen_int_mode (TRAMPOLINE_SIZE, SImode), SImode,
2789 GEN_INT (3), SImode);
2790}
b2d7ede1 2791
bb10104e 2792/* True if X is a reg that can be used as a base reg. */
2793
2794static bool
2795m32r_rtx_ok_for_base_p (const_rtx x, bool strict)
2796{
2797 if (! REG_P (x))
2798 return false;
2799
2800 if (strict)
2801 {
2802 if (GPR_P (REGNO (x)))
2803 return true;
2804 }
2805 else
2806 {
2807 if (GPR_P (REGNO (x))
2808 || REGNO (x) == ARG_POINTER_REGNUM
2809 || ! HARD_REGISTER_P (x))
2810 return true;
2811 }
2812
2813 return false;
2814}
2815
2816static inline bool
2817m32r_rtx_ok_for_offset_p (const_rtx x)
2818{
2819 return (CONST_INT_P (x) && INT16_P (INTVAL (x)));
2820}
2821
2822static inline bool
2823m32r_legitimate_offset_addres_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2824 const_rtx x, bool strict)
2825{
2826 if (GET_CODE (x) == PLUS
2827 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
2828 && m32r_rtx_ok_for_offset_p (XEXP (x, 1)))
2829 return true;
2830
2831 return false;
2832}
2833
2834/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2835 since more than one instruction will be required. */
2836
2837static inline bool
2838m32r_legitimate_lo_sum_addres_p (enum machine_mode mode, const_rtx x,
2839 bool strict)
2840{
2841 if (GET_CODE (x) == LO_SUM
2842 && (mode != BLKmode && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
2843 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
2844 && CONSTANT_P (XEXP (x, 1)))
2845 return true;
2846
2847 return false;
2848}
2849
2850/* Is this a load and increment operation. */
2851
2852static inline bool
2853m32r_load_postinc_p (enum machine_mode mode, const_rtx x, bool strict)
2854{
2855 if ((mode == SImode || mode == SFmode)
2856 && GET_CODE (x) == POST_INC
2857 && REG_P (XEXP (x, 0))
2858 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
2859 return true;
2860
2861 return false;
2862}
2863
2864/* Is this an increment/decrement and store operation. */
2865
2866static inline bool
2867m32r_store_preinc_predec_p (enum machine_mode mode, const_rtx x, bool strict)
2868{
2869 if ((mode == SImode || mode == SFmode)
2870 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
2871 && REG_P (XEXP (x, 0)) \
2872 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
2873 return true;
2874
2875 return false;
2876}
2877
2878/* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2879
2880static bool
2881m32r_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
2882{
2883 if (m32r_rtx_ok_for_base_p (x, strict)
2884 || m32r_legitimate_offset_addres_p (mode, x, strict)
2885 || m32r_legitimate_lo_sum_addres_p (mode, x, strict)
2886 || m32r_load_postinc_p (mode, x, strict)
2887 || m32r_store_preinc_predec_p (mode, x, strict))
2888 return true;
2889
2890 return false;
2891}
2892
b2d7ede1 2893static void
2894m32r_conditional_register_usage (void)
2895{
2896 if (flag_pic)
2897 {
2898 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2899 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2900 }
2901}
ca316360 2902
2903/* Implement TARGET_LEGITIMATE_CONSTANT_P
2904
2905 We don't allow (plus symbol large-constant) as the relocations can't
2906 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2907 We allow all CONST_DOUBLE's as the md file patterns will force the
2908 constant to memory if they can't handle them. */
2909
2910static bool
2911m32r_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2912{
2913 return !(GET_CODE (x) == CONST
2914 && GET_CODE (XEXP (x, 0)) == PLUS
2915 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2916 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
2917 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
2918 && UINTVAL (XEXP (XEXP (x, 0), 1)) > 32767);
2919}
Mirror of https://gcc.gnu.org/git/gcc.git