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2e076ddf 1/* Subroutines used for code generation on the Mitsubishi M32R cpu.
c6b97fac 2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
f4ef873c 3 Free Software Foundation, Inc.
8c5ca3b9 4
7ec022b2 5This file is part of GCC.
8c5ca3b9 6
7ec022b2 7GCC is free software; you can redistribute it and/or modify
8c5ca3b9
DE		 8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
7ec022b2 12GCC is distributed in the hope that it will be useful,
8c5ca3b9
DE		 13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
7ec022b2 18along with GCC; see the file COPYING. If not, write to
8c5ca3b9
DE		 19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
8c5ca3b9 22#include "config.h"
5b8ae21f 23#include "system.h"
4977bab6
ZW		 24#include "coretypes.h"
25#include "tm.h"
8c5ca3b9
DE		 26#include "tree.h"
27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
8c5ca3b9
DE		 33#include "output.h"
34#include "insn-attr.h"
35#include "flags.h"
36#include "expr.h"
bf6bb899 37#include "function.h"
8c5ca3b9 38#include "recog.h"
61f3b78f 39#include "toplev.h"
16f104b3 40#include "ggc.h"
245ff137 41#include "tm_p.h"
672a6f42
NB		 42#include "target.h"
43#include "target-def.h"
8c5ca3b9
DE		 44
45/* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
47rtx m32r_compare_op0, m32r_compare_op1;
48
49/* Array of valid operand punctuation characters. */
50char m32r_punct_chars[256];
51
8c5ca3b9 52/* Selected code model. */
56e2e762 53const char * m32r_model_string = M32R_MODEL_DEFAULT;
8c5ca3b9
DE		 54enum m32r_model m32r_model;
55
56/* Selected SDA support. */
56e2e762 57const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
8c5ca3b9
DE		 58enum m32r_sdata m32r_sdata;
59
56e2e762 60/* Scheduler support */
c237e94a 61static int m32r_sched_odd_word_p;
2b7972b0 62
89e6b702
RH		 63/* Machine-specific symbol_ref flags. */
64#define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
65#define SYMBOL_REF_MODEL(X) \
66 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
67
68/* For string literals, etc. */
69#define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
70
2b7972b0 71/* Forward declaration. */
16f104b3
NC		 72static void init_reg_tables PARAMS ((void));
73static void block_move_call PARAMS ((rtx, rtx, rtx));
74static int m32r_is_insn PARAMS ((rtx));
91d231cb
JM		 75const struct attribute_spec m32r_attribute_table[];
76static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
08c148a8
NB		 77static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
78static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
c237e94a 79
1bc7c5b6
ZW		 80static void m32r_file_start PARAMS ((void));
81
c237e94a
ZW		 82static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
83static int m32r_adjust_priority PARAMS ((rtx, int));
950a3816 84static void m32r_sched_init PARAMS ((FILE *, int, int));
c237e94a
ZW		 85static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
86static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
87static int m32r_issue_rate PARAMS ((void));
88
c6a2438a 89static void m32r_encode_section_info PARAMS ((tree, rtx, int));
89e6b702 90static bool m32r_in_small_data_p PARAMS ((tree));
ab2877a3 91static void init_idents PARAMS ((void));
3c50106f 92static bool m32r_rtx_costs PARAMS ((rtx, int, int, int *));
672a6f42
NB		 93\f
94/* Initialize the GCC target structure. */
91d231cb
JM		 95#undef TARGET_ATTRIBUTE_TABLE
96#define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
2b7972b0 97
301d03af
RS		 98#undef TARGET_ASM_ALIGNED_HI_OP
99#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100#undef TARGET_ASM_ALIGNED_SI_OP
101#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
102
08c148a8
NB		 103#undef TARGET_ASM_FUNCTION_PROLOGUE
104#define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
105#undef TARGET_ASM_FUNCTION_EPILOGUE
106#define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
107
1bc7c5b6
ZW		 108#undef TARGET_ASM_FILE_START
109#define TARGET_ASM_FILE_START m32r_file_start
110
c237e94a
ZW		 111#undef TARGET_SCHED_ADJUST_COST
112#define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
113#undef TARGET_SCHED_ADJUST_PRIORITY
114#define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
115#undef TARGET_SCHED_ISSUE_RATE
116#define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
117#undef TARGET_SCHED_VARIABLE_ISSUE
118#define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
119#undef TARGET_SCHED_INIT
120#define TARGET_SCHED_INIT m32r_sched_init
121#undef TARGET_SCHED_REORDER
122#define TARGET_SCHED_REORDER m32r_sched_reorder
123
fb49053f
RH		 124#undef TARGET_ENCODE_SECTION_INFO
125#define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
89e6b702
RH		 126#undef TARGET_IN_SMALL_DATA_P
127#define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
fb49053f 128
3c50106f
RH		 129#undef TARGET_RTX_COSTS
130#define TARGET_RTX_COSTS m32r_rtx_costs
dcefdf67
RH		 131#undef TARGET_ADDRESS_COST
132#define TARGET_ADDRESS_COST hook_int_rtx_0
3c50106f 133
f6897b10 134struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 135\f
8c5ca3b9
DE		 136/* Called by OVERRIDE_OPTIONS to initialize various things. */
137
138void
139m32r_init ()
140{
141 init_reg_tables ();
142
143 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
144 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
145 m32r_punct_chars['#'] = 1;
146 m32r_punct_chars['@'] = 1; /* ??? no longer used */
147
148 /* Provide default value if not specified. */
149 if (!g_switch_set)
150 g_switch_value = SDATA_DEFAULT_SIZE;
151
152 if (strcmp (m32r_model_string, "small") == 0)
153 m32r_model = M32R_MODEL_SMALL;
154 else if (strcmp (m32r_model_string, "medium") == 0)
155 m32r_model = M32R_MODEL_MEDIUM;
156 else if (strcmp (m32r_model_string, "large") == 0)
157 m32r_model = M32R_MODEL_LARGE;
158 else
159 error ("bad value (%s) for -mmodel switch", m32r_model_string);
160
161 if (strcmp (m32r_sdata_string, "none") == 0)
162 m32r_sdata = M32R_SDATA_NONE;
163 else if (strcmp (m32r_sdata_string, "sdata") == 0)
164 m32r_sdata = M32R_SDATA_SDATA;
165 else if (strcmp (m32r_sdata_string, "use") == 0)
166 m32r_sdata = M32R_SDATA_USE;
167 else
168 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
169}
170
171/* Vectors to keep interesting information about registers where it can easily
172 be got. We use to use the actual mode value as the bit number, but there
173 is (or may be) more than 32 modes now. Instead we use two tables: one
174 indexed by hard register number, and one indexed by mode. */
175
176/* The purpose of m32r_mode_class is to shrink the range of modes so that
177 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
178 mapped into one m32r_mode_class mode. */
179
2b7972b0
MM		 180enum m32r_mode_class
181{
8c5ca3b9
DE		 182 C_MODE,
183 S_MODE, D_MODE, T_MODE, O_MODE,
56e2e762 184 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
8c5ca3b9
DE		 185};
186
187/* Modes for condition codes. */
188#define C_MODES (1 << (int) C_MODE)
189
190/* Modes for single-word and smaller quantities. */
191#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
192
193/* Modes for double-word and smaller quantities. */
194#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
195
196/* Modes for quad-word and smaller quantities. */
197#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
198
56e2e762
NC		 199/* Modes for accumulators. */
200#define A_MODES (1 << (int) A_MODE)
2b7972b0 201
8c5ca3b9
DE		 202/* Value is 1 if register/mode pair is acceptable on arc. */
203
0139adca 204const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
2b7972b0 205{
8c5ca3b9
DE		 206 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
207 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
de41e41c 208 S_MODES, C_MODES, A_MODES, A_MODES
8c5ca3b9
DE		 209};
210
211unsigned int m32r_mode_class [NUM_MACHINE_MODES];
212
213enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
214
215static void
216init_reg_tables ()
217{
218 int i;
219
220 for (i = 0; i < NUM_MACHINE_MODES; i++)
221 {
222 switch (GET_MODE_CLASS (i))
223 {
224 case MODE_INT:
225 case MODE_PARTIAL_INT:
226 case MODE_COMPLEX_INT:
227 if (GET_MODE_SIZE (i) <= 4)
228 m32r_mode_class[i] = 1 << (int) S_MODE;
229 else if (GET_MODE_SIZE (i) == 8)
230 m32r_mode_class[i] = 1 << (int) D_MODE;
231 else if (GET_MODE_SIZE (i) == 16)
232 m32r_mode_class[i] = 1 << (int) T_MODE;
233 else if (GET_MODE_SIZE (i) == 32)
234 m32r_mode_class[i] = 1 << (int) O_MODE;
235 else
236 m32r_mode_class[i] = 0;
237 break;
238 case MODE_FLOAT:
239 case MODE_COMPLEX_FLOAT:
240 if (GET_MODE_SIZE (i) <= 4)
241 m32r_mode_class[i] = 1 << (int) SF_MODE;
242 else if (GET_MODE_SIZE (i) == 8)
243 m32r_mode_class[i] = 1 << (int) DF_MODE;
244 else if (GET_MODE_SIZE (i) == 16)
245 m32r_mode_class[i] = 1 << (int) TF_MODE;
246 else if (GET_MODE_SIZE (i) == 32)
247 m32r_mode_class[i] = 1 << (int) OF_MODE;
248 else
249 m32r_mode_class[i] = 0;
250 break;
251 case MODE_CC:
252 default:
253 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
254 we must explicitly check for them here. */
255 if (i == (int) CCmode)
256 m32r_mode_class[i] = 1 << (int) C_MODE;
257 else
258 m32r_mode_class[i] = 0;
259 break;
260 }
261 }
262
263 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
264 {
265 if (GPR_P (i))
266 m32r_regno_reg_class[i] = GENERAL_REGS;
267 else if (i == ARG_POINTER_REGNUM)
268 m32r_regno_reg_class[i] = GENERAL_REGS;
269 else
270 m32r_regno_reg_class[i] = NO_REGS;
271 }
272}
273\f
274/* M32R specific attribute support.
275
276 interrupt - for interrupt functions
277
278 model - select code model used to access object
279
280 small: addresses use 24 bits, use bl to make calls
281 medium: addresses use 32 bits, use bl to make calls
282 large: addresses use 32 bits, use seth/add3/jl to make calls
283
284 Grep for MODEL in m32r.h for more info.
285*/
286
6aa489b4
NC		 287static tree small_ident1;
288static tree small_ident2;
289static tree medium_ident1;
290static tree medium_ident2;
291static tree large_ident1;
292static tree large_ident2;
293
294static void
ab2877a3 295init_idents ()
6aa489b4 296{
91d231cb 297 if (small_ident1 == 0)
6aa489b4 298 {
6aa489b4
NC		 299 small_ident1 = get_identifier ("small");
300 small_ident2 = get_identifier ("__small__");
301 medium_ident1 = get_identifier ("medium");
302 medium_ident2 = get_identifier ("__medium__");
303 large_ident1 = get_identifier ("large");
304 large_ident2 = get_identifier ("__large__");
305 }
306}
307
91d231cb
JM		 308const struct attribute_spec m32r_attribute_table[] =
309{
310 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
311 { "interrupt", 0, 0, true, false, false, NULL },
312 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
313 { NULL, 0, 0, false, false, false, NULL }
314};
8c5ca3b9 315
91d231cb
JM		 316
317/* Handle an "model" attribute; arguments as in
318 struct attribute_spec.handler. */
319static tree
320m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
321 tree *node ATTRIBUTE_UNUSED;
322 tree name;
8c5ca3b9 323 tree args;
91d231cb
JM		 324 int flags ATTRIBUTE_UNUSED;
325 bool *no_add_attrs;
8c5ca3b9 326{
91d231cb 327 tree arg;
8c5ca3b9 328
91d231cb
JM		 329 init_idents ();
330 arg = TREE_VALUE (args);
331
332 if (arg != small_ident1
333 && arg != small_ident2
334 && arg != medium_ident1
335 && arg != medium_ident2
336 && arg != large_ident1
337 && arg != large_ident2)
338 {
339 warning ("invalid argument of `%s' attribute",
340 IDENTIFIER_POINTER (name));
341 *no_add_attrs = true;
342 }
8c5ca3b9 343
91d231cb 344 return NULL_TREE;
8c5ca3b9 345}
8c5ca3b9 346\f
8c5ca3b9
DE		 347/* Encode section information of DECL, which is either a VAR_DECL,
348 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
349
350 For the M32R we want to record:
351
352 - whether the object lives in .sdata/.sbss.
8c5ca3b9 353 - what code model should be used to access the object
8c5ca3b9
DE		 354*/
355
fb49053f 356static void
c6a2438a 357m32r_encode_section_info (decl, rtl, first)
8c5ca3b9 358 tree decl;
c6a2438a 359 rtx rtl;
b2003250 360 int first;
8c5ca3b9 361{
89e6b702
RH		 362 int extra_flags = 0;
363 tree model_attr;
364 enum m32r_model model;
8c5ca3b9 365
c6a2438a 366 default_encode_section_info (decl, rtl, first);
89e6b702
RH		 367
368 if (!DECL_P (decl))
b2003250
RH		 369 return;
370
89e6b702
RH		 371 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
372 if (model_attr)
8c5ca3b9 373 {
89e6b702 374 tree id;
8c5ca3b9 375
89e6b702 376 init_idents ();
8c5ca3b9 377
89e6b702 378 id = TREE_VALUE (TREE_VALUE (model_attr));
8c5ca3b9 379
89e6b702
RH		 380 if (id == small_ident1 || id == small_ident2)
381 model = M32R_MODEL_SMALL;
382 else if (id == medium_ident1 || id == medium_ident2)
383 model = M32R_MODEL_MEDIUM;
384 else if (id == large_ident1 || id == large_ident2)
385 model = M32R_MODEL_LARGE;
386 else
387 abort (); /* shouldn't happen */
388 }
389 else
8c5ca3b9 390 {
89e6b702
RH		 391 if (TARGET_MODEL_SMALL)
392 model = M32R_MODEL_SMALL;
393 else if (TARGET_MODEL_MEDIUM)
394 model = M32R_MODEL_MEDIUM;
395 else if (TARGET_MODEL_LARGE)
396 model = M32R_MODEL_LARGE;
8c5ca3b9 397 else
89e6b702 398 abort (); /* shouldn't happen */
8c5ca3b9 399 }
89e6b702 400 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
8c5ca3b9 401
89e6b702 402 if (extra_flags)
c6a2438a 403 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
89e6b702 404}
6aa489b4 405
89e6b702
RH		 406/* Only mark the object as being small data area addressable if
407 it hasn't been explicitly marked with a code model.
6aa489b4 408
89e6b702
RH		 409 The user can explicitly put an object in the small data area with the
410 section attribute. If the object is in sdata/sbss and marked with a
411 code model do both [put the object in .sdata and mark it as being
412 addressed with a specific code model - don't mark it as being addressed
413 with an SDA reloc though]. This is ok and might be useful at times. If
414 the object doesn't fit the linker will give an error. */
8c5ca3b9 415
89e6b702
RH		 416static bool
417m32r_in_small_data_p (decl)
418 tree decl;
419{
420 tree section;
421
422 if (TREE_CODE (decl) != VAR_DECL)
423 return false;
424
425 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
426 return false;
427
428 section = DECL_SECTION_NAME (decl);
429 if (section)
8c5ca3b9 430 {
89e6b702
RH		 431 char *name = (char *) TREE_STRING_POINTER (section);
432 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
433 return true;
8c5ca3b9 434 }
89e6b702
RH		 435 else
436 {
437 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
438 {
439 int size = int_size_in_bytes (TREE_TYPE (decl));
8c5ca3b9 440
307b599c 441 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
89e6b702
RH		 442 return true;
443 }
444 }
772c5265 445
89e6b702 446 return false;
772c5265
RH		 447}
448
8c5ca3b9
DE		 449/* Do anything needed before RTL is emitted for each function. */
450
451void
452m32r_init_expanders ()
453{
454 /* ??? At one point there was code here. The function is left in
455 to make it easy to experiment. */
456}
457\f
458/* Acceptable arguments to the call insn. */
459
460int
56e2e762 461call_address_operand (op, mode)
8c5ca3b9 462 rtx op;
56e2e762 463 enum machine_mode mode;
8c5ca3b9 464{
56e2e762 465 return symbolic_operand (op, mode);
2e076ddf 466
2b7972b0
MM		 467/* Constants and values in registers are not OK, because
468 the m32r BL instruction can only support PC relative branching. */
8c5ca3b9
DE		 469}
470
471int
56e2e762 472call_operand (op, mode)
8c5ca3b9 473 rtx op;
56e2e762 474 enum machine_mode mode;
8c5ca3b9
DE		 475{
476 if (GET_CODE (op) != MEM)
477 return 0;
478 op = XEXP (op, 0);
479 return call_address_operand (op, mode);
480}
481
482/* Returns 1 if OP is a symbol reference. */
483
484int
56e2e762 485symbolic_operand (op, mode)
8c5ca3b9 486 rtx op;
56e2e762 487 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 488{
489 switch (GET_CODE (op))
490 {
491 case SYMBOL_REF:
492 case LABEL_REF:
493 case CONST :
494 return 1;
2b7972b0 495
8c5ca3b9
DE		 496 default:
497 return 0;
498 }
499}
500
8c5ca3b9
DE		 501/* Return 1 if OP is a reference to an object in .sdata/.sbss. */
502
503int
56e2e762 504small_data_operand (op, mode)
8c5ca3b9 505 rtx op;
56e2e762 506 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 507{
508 if (! TARGET_SDATA_USE)
509 return 0;
510
511 if (GET_CODE (op) == SYMBOL_REF)
89e6b702 512 return SYMBOL_REF_SMALL_P (op);
8c5ca3b9
DE		 513
514 if (GET_CODE (op) == CONST
515 && GET_CODE (XEXP (op, 0)) == PLUS
516 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
517 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
518 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
89e6b702 519 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
8c5ca3b9
DE		 520
521 return 0;
522}
523
524/* Return 1 if OP is a symbol that can use 24 bit addressing. */
525
526int
56e2e762 527addr24_operand (op, mode)
8c5ca3b9 528 rtx op;
56e2e762 529 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9 530{
89e6b702
RH		 531 rtx sym;
532
8c5ca3b9
DE		 533 if (GET_CODE (op) == LABEL_REF)
534 return TARGET_ADDR24;
535
536 if (GET_CODE (op) == SYMBOL_REF)
89e6b702
RH		 537 sym = op;
538 else if (GET_CODE (op) == CONST
539 && GET_CODE (XEXP (op, 0)) == PLUS
540 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
541 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
542 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
543 sym = XEXP (XEXP (op, 0), 0);
544 else
545 return 0;
8c5ca3b9 546
89e6b702
RH		 547 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
548 return 1;
549
550 if (TARGET_ADDR24
551 && (CONSTANT_POOL_ADDRESS_P (sym)
552 || LIT_NAME_P (XSTR (sym, 0))))
553 return 1;
8c5ca3b9
DE		 554
555 return 0;
556}
557
558/* Return 1 if OP is a symbol that needs 32 bit addressing. */
559
560int
56e2e762 561addr32_operand (op, mode)
8c5ca3b9 562 rtx op;
56e2e762 563 enum machine_mode mode;
8c5ca3b9 564{
89e6b702
RH		 565 rtx sym;
566
8c5ca3b9
DE		 567 if (GET_CODE (op) == LABEL_REF)
568 return TARGET_ADDR32;
569
570 if (GET_CODE (op) == SYMBOL_REF)
89e6b702
RH		 571 sym = op;
572 else if (GET_CODE (op) == CONST
573 && GET_CODE (XEXP (op, 0)) == PLUS
574 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
575 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
576 sym = XEXP (XEXP (op, 0), 0);
577 else
578 return 0;
8c5ca3b9 579
89e6b702
RH		 580 return (! addr24_operand (sym, mode)
581 && ! small_data_operand (sym, mode));
8c5ca3b9
DE		 582}
583
584/* Return 1 if OP is a function that can be called with the `bl' insn. */
585
586int
56e2e762 587call26_operand (op, mode)
8c5ca3b9 588 rtx op;
56e2e762 589 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 590{
591 if (GET_CODE (op) == SYMBOL_REF)
89e6b702 592 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
8c5ca3b9
DE		 593
594 return TARGET_CALL26;
595}
596
8c5ca3b9
DE		 597/* Returns 1 if OP is an acceptable operand for seth/add3. */
598
599int
56e2e762 600seth_add3_operand (op, mode)
8c5ca3b9 601 rtx op;
56e2e762 602 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 603{
604 if (GET_CODE (op) == SYMBOL_REF
605 || GET_CODE (op) == LABEL_REF)
606 return 1;
607
608 if (GET_CODE (op) == CONST
609 && GET_CODE (XEXP (op, 0)) == PLUS
610 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
611 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
612 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
613 return 1;
614
615 return 0;
616}
617
56e2e762
NC		 618/* Return true if OP is a signed 8 bit immediate value. */
619
620int
621int8_operand (op, mode)
622 rtx op;
623 enum machine_mode mode ATTRIBUTE_UNUSED;
624{
625 if (GET_CODE (op) != CONST_INT)
626 return 0;
627 return INT8_P (INTVAL (op));
628}
629
8c5ca3b9
DE		 630/* Return true if OP is a signed 16 bit immediate value
631 useful in comparisons. */
632
633int
56e2e762 634cmp_int16_operand (op, mode)
8c5ca3b9 635 rtx op;
56e2e762 636 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 637{
638 if (GET_CODE (op) != CONST_INT)
639 return 0;
640 return CMP_INT16_P (INTVAL (op));
641}
642
643/* Return true if OP is an unsigned 16 bit immediate value. */
644
2b7972b0 645int
56e2e762 646uint16_operand (op, mode)
8c5ca3b9 647 rtx op;
56e2e762 648 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 649{
650 if (GET_CODE (op) != CONST_INT)
651 return 0;
652 return UINT16_P (INTVAL (op));
653}
654
56e2e762 655/* Return true if OP is a register or signed 16 bit value. */
8c5ca3b9
DE		 656
657int
56e2e762 658reg_or_int16_operand (op, mode)
8c5ca3b9 659 rtx op;
56e2e762 660 enum machine_mode mode;
8c5ca3b9
DE		 661{
662 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
663 return register_operand (op, mode);
664 if (GET_CODE (op) != CONST_INT)
665 return 0;
666 return INT16_P (INTVAL (op));
667}
668
2e076ddf 669/* Return true if OP is a register or an unsigned 16 bit value. */
8c5ca3b9
DE		 670
671int
56e2e762 672reg_or_uint16_operand (op, mode)
8c5ca3b9 673 rtx op;
56e2e762 674 enum machine_mode mode;
8c5ca3b9
DE		 675{
676 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
677 return register_operand (op, mode);
678 if (GET_CODE (op) != CONST_INT)
679 return 0;
680 return UINT16_P (INTVAL (op));
681}
682
56e2e762
NC		 683/* Return true if OP is a register or an integer value that can be
684 used is SEQ/SNE. We can use either XOR of the value or ADD of
685 the negative of the value for the constant. Don't allow 0,
686 because that is special cased. */
8c5ca3b9
DE		 687
688int
56e2e762 689reg_or_eq_int16_operand (op, mode)
8c5ca3b9 690 rtx op;
56e2e762 691 enum machine_mode mode;
8c5ca3b9 692{
56e2e762 693 HOST_WIDE_INT value;
2b7972b0 694
56e2e762
NC		 695 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
696 return register_operand (op, mode);
697
698 if (GET_CODE (op) != CONST_INT)
699 return 0;
700
701 value = INTVAL (op);
702 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
703}
704
705/* Return true if OP is a register or signed 16 bit value for compares. */
706
707int
708reg_or_cmp_int16_operand (op, mode)
709 rtx op;
710 enum machine_mode mode;
711{
8c5ca3b9
DE		 712 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
713 return register_operand (op, mode);
714 if (GET_CODE (op) != CONST_INT)
715 return 0;
716 return CMP_INT16_P (INTVAL (op));
717}
718
de41e41c
BE		 719/* Return true if OP is a register or the constant 0. */
720
721int
722reg_or_zero_operand (op, mode)
723 rtx op;
724 enum machine_mode mode;
725{
726 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
727 return register_operand (op, mode);
728
729 if (GET_CODE (op) != CONST_INT)
730 return 0;
731
732 return INTVAL (op) == 0;
733}
734
4d6c607f
DE		 735/* Return true if OP is a const_int requiring two instructions to load. */
736
737int
56e2e762 738two_insn_const_operand (op, mode)
4d6c607f 739 rtx op;
56e2e762 740 enum machine_mode mode ATTRIBUTE_UNUSED;
4d6c607f
DE		 741{
742 if (GET_CODE (op) != CONST_INT)
743 return 0;
744 if (INT16_P (INTVAL (op))
745 || UINT24_P (INTVAL (op))
746 || UPPER16_P (INTVAL (op)))
747 return 0;
748 return 1;
749}
750
8c5ca3b9
DE		 751/* Return true if OP is an acceptable argument for a single word
752 move source. */
753
754int
56e2e762 755move_src_operand (op, mode)
8c5ca3b9 756 rtx op;
56e2e762 757 enum machine_mode mode;
8c5ca3b9
DE		 758{
759 switch (GET_CODE (op))
760 {
761 case SYMBOL_REF :
762 case CONST :
56e2e762 763 return addr24_operand (op, mode);
8c5ca3b9 764 case CONST_INT :
efbbf34f
DE		 765 /* ??? We allow more cse opportunities if we only allow constants
766 loadable with one insn, and split the rest into two. The instances
767 where this would help should be rare and the current way is
768 simpler. */
c73a5e94
RH		 769 if (HOST_BITS_PER_WIDE_INT > 32)
770 {
771 HOST_WIDE_INT rest = INTVAL (op) >> 31;
772 return (rest == 0 || rest == -1);
773 }
774 else
775 return 1;
8c5ca3b9
DE		 776 case LABEL_REF :
777 return TARGET_ADDR24;
778 case CONST_DOUBLE :
779 if (mode == SFmode)
780 return 1;
781 else if (mode == SImode)
782 {
783 /* Large unsigned constants are represented as const_double's. */
784 unsigned HOST_WIDE_INT low, high;
785
786 low = CONST_DOUBLE_LOW (op);
787 high = CONST_DOUBLE_HIGH (op);
9d303046 788 return high == 0 && low <= (unsigned) 0xffffffff;
8c5ca3b9
DE		 789 }
790 else
791 return 0;
792 case REG :
793 return register_operand (op, mode);
794 case SUBREG :
795 /* (subreg (mem ...) ...) can occur here if the inner part was once a
796 pseudo-reg and is now a stack slot. */
797 if (GET_CODE (SUBREG_REG (op)) == MEM)
798 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
799 else
800 return register_operand (op, mode);
801 case MEM :
56e2e762
NC		 802 if (GET_CODE (XEXP (op, 0)) == PRE_INC
803 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
804 return 0; /* loads can't do pre-{inc,dec} */
8c5ca3b9
DE		 805 return address_operand (XEXP (op, 0), mode);
806 default :
807 return 0;
808 }
809}
810
811/* Return true if OP is an acceptable argument for a double word
812 move source. */
813
814int
56e2e762 815move_double_src_operand (op, mode)
8c5ca3b9 816 rtx op;
56e2e762 817 enum machine_mode mode;
8c5ca3b9
DE		 818{
819 switch (GET_CODE (op))
820 {
821 case CONST_INT :
822 case CONST_DOUBLE :
5b8ae21f 823 return 1;
8c5ca3b9
DE		 824 case REG :
825 return register_operand (op, mode);
826 case SUBREG :
827 /* (subreg (mem ...) ...) can occur here if the inner part was once a
828 pseudo-reg and is now a stack slot. */
829 if (GET_CODE (SUBREG_REG (op)) == MEM)
56e2e762 830 return move_double_src_operand (SUBREG_REG (op), mode);
8c5ca3b9
DE		 831 else
832 return register_operand (op, mode);
833 case MEM :
834 /* Disallow auto inc/dec for now. */
835 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
836 || GET_CODE (XEXP (op, 0)) == PRE_INC)
837 return 0;
838 return address_operand (XEXP (op, 0), mode);
839 default :
840 return 0;
841 }
842}
843
844/* Return true if OP is an acceptable argument for a move destination. */
845
846int
56e2e762 847move_dest_operand (op, mode)
8c5ca3b9 848 rtx op;
56e2e762 849 enum machine_mode mode;
8c5ca3b9
DE		 850{
851 switch (GET_CODE (op))
852 {
853 case REG :
854 return register_operand (op, mode);
855 case SUBREG :
856 /* (subreg (mem ...) ...) can occur here if the inner part was once a
857 pseudo-reg and is now a stack slot. */
858 if (GET_CODE (SUBREG_REG (op)) == MEM)
859 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
860 else
861 return register_operand (op, mode);
862 case MEM :
56e2e762
NC		 863 if (GET_CODE (XEXP (op, 0)) == POST_INC)
864 return 0; /* stores can't do post inc */
8c5ca3b9
DE		 865 return address_operand (XEXP (op, 0), mode);
866 default :
867 return 0;
868 }
869}
870
871/* Return 1 if OP is a DImode const we want to handle inline.
872 This must match the code in the movdi pattern.
873 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
874
875int
876easy_di_const (op)
877 rtx op;
878{
879 rtx high_rtx, low_rtx;
880 HOST_WIDE_INT high, low;
881
882 split_double (op, &high_rtx, &low_rtx);
883 high = INTVAL (high_rtx);
884 low = INTVAL (low_rtx);
885 /* Pick constants loadable with 2 16 bit `ldi' insns. */
886 if (high >= -128 && high <= 127
887 && low >= -128 && low <= 127)
888 return 1;
889 return 0;
890}
891
892/* Return 1 if OP is a DFmode const we want to handle inline.
893 This must match the code in the movdf pattern.
894 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
895
896int
897easy_df_const (op)
898 rtx op;
899{
900 REAL_VALUE_TYPE r;
901 long l[2];
902
903 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
904 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
905 if (l[0] == 0 && l[1] == 0)
906 return 1;
907 if ((l[0] & 0xffff) == 0 && l[1] == 0)
908 return 1;
909 return 0;
910}
911
912/* Return 1 if OP is an EQ or NE comparison operator. */
913
914int
56e2e762 915eqne_comparison_operator (op, mode)
8c5ca3b9 916 rtx op;
56e2e762 917 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 918{
919 enum rtx_code code = GET_CODE (op);
920
921 if (GET_RTX_CLASS (code) != '<')
922 return 0;
923 return (code == EQ || code == NE);
924}
925
926/* Return 1 if OP is a signed comparison operator. */
927
928int
56e2e762 929signed_comparison_operator (op, mode)
8c5ca3b9 930 rtx op;
56e2e762 931 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 932{
933 enum rtx_code code = GET_CODE (op);
934
935 if (GET_RTX_CLASS (code) != '<')
936 return 0;
937 return (code == EQ || code == NE
938 || code == LT || code == LE || code == GT || code == GE);
939}
940
941/* Return 1 if OP is (mem (reg ...)).
942 This is used in insn length calcs. */
943
944int
56e2e762 945memreg_operand (op, mode)
8c5ca3b9 946 rtx op;
56e2e762 947 enum machine_mode mode ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 948{
949 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
950}
2b7972b0 951
56e2e762
NC		 952/* Return true if OP is an acceptable input argument for a zero/sign extend
953 operation. */
954
955int
956extend_operand (op, mode)
957 rtx op;
958 enum machine_mode mode;
959{
960 rtx addr;
961
962 switch (GET_CODE (op))
963 {
964 case REG :
965 case SUBREG :
966 return register_operand (op, mode);
967
968 case MEM :
969 addr = XEXP (op, 0);
970 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
971 return 0; /* loads can't do pre inc/pre dec */
972
973 return address_operand (addr, mode);
974
975 default :
976 return 0;
977 }
978}
979
a0ab749a 980/* Return nonzero if the operand is an insn that is a small insn.
2b7972b0
MM		 981 Allow const_int 0 as well, which is a placeholder for NOP slots. */
982
983int
56e2e762 984small_insn_p (op, mode)
2b7972b0 985 rtx op;
56e2e762 986 enum machine_mode mode ATTRIBUTE_UNUSED;
2b7972b0
MM		 987{
988 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
989 return 1;
990
23568fa0 991 if (! INSN_P (op))
2b7972b0
MM		 992 return 0;
993
994 return get_attr_length (op) == 2;
995}
996
a0ab749a 997/* Return nonzero if the operand is an insn that is a large insn. */
2b7972b0
MM		 998
999int
56e2e762 1000large_insn_p (op, mode)
2b7972b0 1001 rtx op;
56e2e762 1002 enum machine_mode mode ATTRIBUTE_UNUSED;
2b7972b0 1003{
23568fa0 1004 if (! INSN_P (op))
2b7972b0
MM		 1005 return 0;
1006
1007 return get_attr_length (op) != 2;
1008}
1009
72ac76be 1010/* Return nonzero if TYPE must be passed or returned in memory.
d88e80e6
DE		 1011 The m32r treats both directions the same so we handle both directions
1012 in this function. */
1013
1014int
1015m32r_pass_by_reference (type)
1016 tree type;
1017{
1018 int size = int_size_in_bytes (type);
1019
1020 if (size < 0 || size > 8)
1021 return 1;
1022
1023 return 0;
1024}
8c5ca3b9
DE		 1025\f
1026/* Comparisons. */
1027
8c5ca3b9 1028/* X and Y are two things to compare using CODE. Emit the compare insn and
2b7972b0
MM		 1029 return the rtx for compare [arg0 of the if_then_else].
1030 If need_compare is true then the comparison insn must be generated, rather
dab66575 1031 than being subsumed into the following branch instruction. */
8c5ca3b9
DE		 1032
1033rtx
c5c76735
JL		 1034gen_compare (code, x, y, need_compare)
1035 enum rtx_code code;
1036 rtx x, y;
1037 int need_compare;
8c5ca3b9 1038{
c5c76735 1039 enum rtx_code compare_code, branch_code;
ac17cd8f 1040 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
61f3b78f 1041 int must_swap = 0;
8c5ca3b9
DE		 1042
1043 switch (code)
1044 {
2e076ddf
NC		 1045 case EQ: compare_code = EQ; branch_code = NE; break;
1046 case NE: compare_code = EQ; branch_code = EQ; break;
1047 case LT: compare_code = LT; branch_code = NE; break;
1048 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1049 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1050 case GE: compare_code = LT; branch_code = EQ; break;
8c5ca3b9 1051 case LTU: compare_code = LTU; branch_code = NE; break;
2e076ddf
NC		 1052 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1053 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
8c5ca3b9 1054 case GEU: compare_code = LTU; branch_code = EQ; break;
61f3b78f
RH		 1055
1056 default:
56e2e762 1057 abort ();
8c5ca3b9
DE		 1058 }
1059
2b7972b0
MM		 1060 if (need_compare)
1061 {
1062 switch (compare_code)
1063 {
1064 case EQ:
1065 if (GET_CODE (y) == CONST_INT
1066 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1067 && y != const0_rtx)
1068 {
1069 rtx tmp = gen_reg_rtx (SImode);
1070
1071 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1072 x = tmp;
1073 y = const0_rtx;
1074 }
1075 else if (CONSTANT_P (y)) /* reg equal to const. */
1076 {
1077 rtx tmp = force_reg (GET_MODE (x), y);
1078 y = tmp;
1079 }
1080
1081 if (register_operand (y, SImode) /* reg equal to reg. */
1082 || y == const0_rtx) /* req equal to zero. */
1083 {
56e2e762 1084 emit_insn (gen_cmp_eqsi_insn (x, y));
2b7972b0 1085
ac17cd8f 1086 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
2b7972b0
MM		 1087 }
1088 break;
1089
1090 case LT:
1091 if (register_operand (y, SImode)
1092 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1093 {
1094 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1095
1096 switch (code)
1097 {
1098 case LT:
1099 emit_insn (gen_cmp_ltsi_insn (x, y));
1100 code = EQ;
1101 break;
1102 case LE:
1103 if (y == const0_rtx)
1104 tmp = const1_rtx;
1105 else
1106 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1107 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1108 code = EQ;
1109 break;
1110 case GT:
1111 if (GET_CODE (y) == CONST_INT)
1112 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1113 else
1114 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1115 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1116 code = NE;
1117 break;
1118 case GE:
1119 emit_insn (gen_cmp_ltsi_insn (x, y));
1120 code = NE;
1121 break;
1122 default:
56e2e762 1123 abort ();
2b7972b0
MM		 1124 }
1125
ac17cd8f 1126 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
2b7972b0
MM		 1127 }
1128 break;
1129
1130 case LTU:
1131 if (register_operand (y, SImode)
1132 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1133 {
1134 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1135
1136 switch (code)
1137 {
1138 case LTU:
1139 emit_insn (gen_cmp_ltusi_insn (x, y));
1140 code = EQ;
1141 break;
1142 case LEU:
1143 if (y == const0_rtx)
1144 tmp = const1_rtx;
1145 else
1146 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1147 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1148 code = EQ;
1149 break;
1150 case GTU:
1151 if (GET_CODE (y) == CONST_INT)
1152 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1153 else
1154 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1155 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1156 code = NE;
1157 break;
1158 case GEU:
1159 emit_insn (gen_cmp_ltusi_insn (x, y));
1160 code = NE;
1161 break;
1162 default:
1163 abort();
1164 }
1165
ac17cd8f 1166 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
2b7972b0
MM		 1167 }
1168 break;
1169
1170 default:
1171 abort();
1172 }
1173 }
1174 else
8c5ca3b9
DE		 1175 {
1176 /* reg/reg equal comparison */
1177 if (compare_code == EQ
1178 && register_operand (y, SImode))
ac17cd8f 1179 return gen_rtx (code, CCmode, x, y);
2e076ddf 1180
8c5ca3b9
DE		 1181 /* reg/zero signed comparison */
1182 if ((compare_code == EQ || compare_code == LT)
1183 && y == const0_rtx)
ac17cd8f 1184 return gen_rtx (code, CCmode, x, y);
2e076ddf 1185
8c5ca3b9
DE		 1186 /* reg/smallconst equal comparison */
1187 if (compare_code == EQ
1188 && GET_CODE (y) == CONST_INT
1189 && CMP_INT16_P (INTVAL (y)))
1190 {
1191 rtx tmp = gen_reg_rtx (SImode);
1192 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
ac17cd8f 1193 return gen_rtx (code, CCmode, tmp, const0_rtx);
8c5ca3b9 1194 }
2e076ddf 1195
8c5ca3b9
DE		 1196 /* reg/const equal comparison */
1197 if (compare_code == EQ
1198 && CONSTANT_P (y))
1199 {
1200 rtx tmp = force_reg (GET_MODE (x), y);
ac17cd8f 1201 return gen_rtx (code, CCmode, x, tmp);
8c5ca3b9
DE		 1202 }
1203 }
1204
2e076ddf 1205 if (CONSTANT_P (y))
8c5ca3b9 1206 {
2e076ddf 1207 if (must_swap)
8c5ca3b9 1208 y = force_reg (GET_MODE (x), y);
2e076ddf
NC		 1209 else
1210 {
1211 int ok_const =
1212 (code == LTU || code == LEU || code == GTU || code == GEU)
1213 ? uint16_operand (y, GET_MODE (y))
1214 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1215
1216 if (! ok_const)
1217 y = force_reg (GET_MODE (x), y);
1218 }
8c5ca3b9
DE		 1219 }
1220
1221 switch (compare_code)
1222 {
1223 case EQ :
2e076ddf 1224 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
8c5ca3b9
DE		 1225 break;
1226 case LT :
2e076ddf 1227 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
8c5ca3b9
DE		 1228 break;
1229 case LTU :
2e076ddf 1230 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
8c5ca3b9 1231 break;
61f3b78f
RH		 1232
1233 default:
1234 abort ();
8c5ca3b9
DE		 1235 }
1236
ac17cd8f 1237 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
8c5ca3b9 1238}
5b8ae21f
MM		 1239\f
1240/* Split a 2 word move (DI or DF) into component parts. */
1241
1242rtx
1243gen_split_move_double (operands)
1244 rtx operands[];
1245{
1246 enum machine_mode mode = GET_MODE (operands[0]);
1247 rtx dest = operands[0];
1248 rtx src = operands[1];
1249 rtx val;
1250
ca3bf2b5
JW		 1251 /* We might have (SUBREG (MEM)) here, so just get rid of the
1252 subregs to make this code simpler. It is safe to call
1253 alter_subreg any time after reload. */
1254 if (GET_CODE (dest) == SUBREG)
68882f0f 1255 alter_subreg (&dest);
ca3bf2b5 1256 if (GET_CODE (src) == SUBREG)
68882f0f 1257 alter_subreg (&src);
ca3bf2b5 1258
5b8ae21f 1259 start_sequence ();
ca3bf2b5 1260 if (GET_CODE (dest) == REG)
5b8ae21f 1261 {
ca3bf2b5
JW		 1262 int dregno = REGNO (dest);
1263
5b8ae21f 1264 /* reg = reg */
ca3bf2b5 1265 if (GET_CODE (src) == REG)
5b8ae21f 1266 {
ca3bf2b5
JW		 1267 int sregno = REGNO (src);
1268
1269 int reverse = (dregno == sregno + 1);
1270
5b8ae21f
MM		 1271 /* We normally copy the low-numbered register first. However, if
1272 the first register operand 0 is the same as the second register of
1273 operand 1, we must copy in the opposite order. */
5b8ae21f
MM		 1274 emit_insn (gen_rtx_SET (VOIDmode,
1275 operand_subword (dest, reverse, TRUE, mode),
1276 operand_subword (src, reverse, TRUE, mode)));
1277
1278 emit_insn (gen_rtx_SET (VOIDmode,
1279 operand_subword (dest, !reverse, TRUE, mode),
1280 operand_subword (src, !reverse, TRUE, mode)));
1281 }
1282
1283 /* reg = constant */
1284 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1285 {
1286 rtx words[2];
1287 split_double (src, &words[0], &words[1]);
1288 emit_insn (gen_rtx_SET (VOIDmode,
1289 operand_subword (dest, 0, TRUE, mode),
1290 words[0]));
1291
1292 emit_insn (gen_rtx_SET (VOIDmode,
1293 operand_subword (dest, 1, TRUE, mode),
1294 words[1]));
1295 }
1296
1297 /* reg = mem */
1298 else if (GET_CODE (src) == MEM)
1299 {
1300 /* If the high-address word is used in the address, we must load it
1301 last. Otherwise, load it first. */
f4ef873c
RK		 1302 int reverse
1303 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
5b8ae21f
MM		 1304
1305 /* We used to optimize loads from single registers as
1306
1307 ld r1,r3+; ld r2,r3
1308
1309 if r3 were not used subsequently. However, the REG_NOTES aren't
dab66575 1310 propagated correctly by the reload phase, and it can cause bad
5b8ae21f
MM		 1311 code to be generated. We could still try:
1312
1313 ld r1,r3+; ld r2,r3; addi r3,-4
1314
1315 which saves 2 bytes and doesn't force longword alignment. */
1316 emit_insn (gen_rtx_SET (VOIDmode,
1317 operand_subword (dest, reverse, TRUE, mode),
f4ef873c
RK		 1318 adjust_address (src, SImode,
1319 reverse * UNITS_PER_WORD)));
5b8ae21f
MM		 1320
1321 emit_insn (gen_rtx_SET (VOIDmode,
1322 operand_subword (dest, !reverse, TRUE, mode),
f4ef873c
RK		 1323 adjust_address (src, SImode,
1324 !reverse * UNITS_PER_WORD)));
5b8ae21f
MM		 1325 }
1326
1327 else
1328 abort ();
1329 }
1330
1331 /* mem = reg */
1332 /* We used to optimize loads from single registers as
1333
1334 st r1,r3; st r2,+r3
1335
1336 if r3 were not used subsequently. However, the REG_NOTES aren't
dab66575 1337 propagated correctly by the reload phase, and it can cause bad
5b8ae21f
MM		 1338 code to be generated. We could still try:
1339
1340 st r1,r3; st r2,+r3; addi r3,-4
1341
1342 which saves 2 bytes and doesn't force longword alignment. */
ca3bf2b5 1343 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
5b8ae21f 1344 {
5b8ae21f 1345 emit_insn (gen_rtx_SET (VOIDmode,
f4ef873c 1346 adjust_address (dest, SImode, 0),
5b8ae21f
MM		 1347 operand_subword (src, 0, TRUE, mode)));
1348
1349 emit_insn (gen_rtx_SET (VOIDmode,
f4ef873c 1350 adjust_address (dest, SImode, UNITS_PER_WORD),
5b8ae21f
MM		 1351 operand_subword (src, 1, TRUE, mode)));
1352 }
1353
1354 else
1355 abort ();
1356
2f937369 1357 val = get_insns ();
5b8ae21f
MM		 1358 end_sequence ();
1359 return val;
1360}
1361
8c5ca3b9
DE		 1362\f
1363/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1364
1365int
56e2e762 1366function_arg_partial_nregs (cum, mode, type, named)
8c5ca3b9 1367 CUMULATIVE_ARGS *cum;
56e2e762 1368 enum machine_mode mode;
8c5ca3b9 1369 tree type;
61f3b78f 1370 int named ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 1371{
1372 int ret;
16f104b3
NC		 1373 unsigned int size =
1374 (((mode == BLKmode && type)
1375 ? (unsigned int) int_size_in_bytes (type)
1376 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1377 / UNITS_PER_WORD;
8c5ca3b9
DE		 1378
1379 if (*cum >= M32R_MAX_PARM_REGS)
1380 ret = 0;
1381 else if (*cum + size > M32R_MAX_PARM_REGS)
1382 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1383 else
1384 ret = 0;
1385
1386 return ret;
1387}
1388
1389/* Do any needed setup for a variadic function. For the M32R, we must
1390 create a register parameter block, and then copy any anonymous arguments
1391 in registers to memory.
1392
1393 CUM has not been updated for the last named argument which has type TYPE
1394 and mode MODE, and we rely on this fact. */
1395
1396void
56e2e762 1397m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
8c5ca3b9 1398 CUMULATIVE_ARGS *cum;
56e2e762 1399 enum machine_mode mode;
8c5ca3b9
DE		 1400 tree type;
1401 int *pretend_size;
1402 int no_rtl;
1403{
1404 int first_anon_arg;
1405
1406 if (no_rtl)
1407 return;
1408
1409 /* All BLKmode values are passed by reference. */
1410 if (mode == BLKmode)
1411 abort ();
1412
6c535c69
ZW		 1413 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1414 + ROUND_ADVANCE_ARG (mode, type));
8c5ca3b9
DE		 1415
1416 if (first_anon_arg < M32R_MAX_PARM_REGS)
1417 {
1418 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1419 int first_reg_offset = first_anon_arg;
1420 /* Size in words to "pretend" allocate. */
1421 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1422 rtx regblock;
1423
c5c76735
JL		 1424 regblock = gen_rtx_MEM (BLKmode,
1425 plus_constant (arg_pointer_rtx,
1426 FIRST_PARM_OFFSET (0)));
ba4828e0 1427 set_mem_alias_set (regblock, get_varargs_alias_set ());
c6b97fac 1428 move_block_from_reg (first_reg_offset, regblock, size);
8c5ca3b9
DE		 1429
1430 *pretend_size = (size * UNITS_PER_WORD);
1431 }
1432}
40cae311 1433
56e2e762 1434\f
40cae311
RH		 1435/* Implement `va_arg'. */
1436
1437rtx
1438m32r_va_arg (valist, type)
1439 tree valist, type;
1440{
1441 HOST_WIDE_INT size, rsize;
1442 tree t;
1443 rtx addr_rtx;
1444
1445 size = int_size_in_bytes (type);
1446 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1447
d88e80e6 1448 if (m32r_pass_by_reference (type))
40cae311
RH		 1449 {
1450 tree type_ptr, type_ptr_ptr;
1451
1452 /* Pass by reference. */
1453
1454 type_ptr = build_pointer_type (type);
1455 type_ptr_ptr = build_pointer_type (type_ptr);
1456
1457 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1458 build_int_2 (UNITS_PER_WORD, 0));
1459 TREE_SIDE_EFFECTS (t) = 1;
1460 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1461 TREE_SIDE_EFFECTS (t) = 1;
1462 t = build1 (INDIRECT_REF, type_ptr, t);
1463
1464 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1465 }
1466 else
1467 {
1468 /* Pass by value. */
1469
1470 if (size < UNITS_PER_WORD)
1471 {
1472 /* Care for bigendian correction on the aligned address. */
1473 t = build (PLUS_EXPR, ptr_type_node, valist,
1474 build_int_2 (rsize - size, 0));
1475 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1476 addr_rtx = copy_to_reg (addr_rtx);
1477
1478 /* Increment AP. */
1479 t = build (PLUS_EXPR, va_list_type_node, valist,
1480 build_int_2 (rsize, 0));
1481 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1482 TREE_SIDE_EFFECTS (t) = 1;
1483 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1484 }
1485 else
1486 {
1487 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1488 build_int_2 (rsize, 0));
1489 TREE_SIDE_EFFECTS (t) = 1;
1490 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1491 }
1492 }
1493
1494 return addr_rtx;
1495}
8c5ca3b9 1496\f
c237e94a 1497static int
56e2e762
NC		 1498m32r_adjust_cost (insn, link, dep_insn, cost)
1499 rtx insn ATTRIBUTE_UNUSED;
1500 rtx link ATTRIBUTE_UNUSED;
1501 rtx dep_insn ATTRIBUTE_UNUSED;
1502 int cost;
1503{
1504 return cost;
1505}
1506
1507\f
23568fa0 1508/* Return true if INSN is real instruction bearing insn. */
56e2e762 1509
23568fa0
NC		 1510static int
1511m32r_is_insn (insn)
1512 rtx insn;
1513{
1514 return (INSN_P (insn)
1515 && GET_CODE (PATTERN (insn)) != USE
1516 && GET_CODE (PATTERN (insn)) != CLOBBER
1517 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1518}
1519
1520/* Increase the priority of long instructions so that the
1521 short instructions are scheduled ahead of the long ones. */
56e2e762 1522
c237e94a 1523static int
56e2e762
NC		 1524m32r_adjust_priority (insn, priority)
1525 rtx insn;
1526 int priority;
1527{
23568fa0
NC		 1528 if (m32r_is_insn (insn)
1529 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1530 priority <<= 3;
56e2e762
NC		 1531
1532 return priority;
1533}
1534
1535\f
1536/* Initialize for scheduling a group of instructions. */
1537
c237e94a 1538static void
950a3816 1539m32r_sched_init (stream, verbose, max_ready)
56e2e762
NC		 1540 FILE * stream ATTRIBUTE_UNUSED;
1541 int verbose ATTRIBUTE_UNUSED;
950a3816 1542 int max_ready ATTRIBUTE_UNUSED;
56e2e762
NC		 1543{
1544 m32r_sched_odd_word_p = FALSE;
1545}
1546
1547\f
1548/* Reorder the schedulers priority list if needed */
1549
c237e94a
ZW		 1550static int
1551m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
56e2e762
NC		 1552 FILE * stream;
1553 int verbose;
1554 rtx * ready;
c237e94a
ZW		 1555 int *n_readyp;
1556 int clock ATTRIBUTE_UNUSED;
56e2e762 1557{
c237e94a
ZW		 1558 int n_ready = *n_readyp;
1559
56e2e762 1560 if (TARGET_DEBUG)
c237e94a 1561 return m32r_issue_rate ();
56e2e762
NC		 1562
1563 if (verbose <= 7)
1564 stream = (FILE *)0;
1565
1566 if (stream)
1567 fprintf (stream,
1568 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1569 n_ready,
1570 (m32r_sched_odd_word_p) ? "odd" : "even");
1571
1572 if (n_ready > 1)
1573 {
1574 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1575 rtx * long_tail = long_head;
1576 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1577 rtx * short_tail = short_head;
1578 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1579 rtx * new_tail = new_head + (n_ready - 1);
1580 int i;
1581
dab66575 1582 /* Loop through the instructions, classifying them as short/long. Try
56e2e762
NC		 1583 to keep 2 short together and/or 1 long. Note, the ready list is
1584 actually ordered backwards, so keep it in that manner. */
1585 for (i = n_ready-1; i >= 0; i--)
1586 {
1587 rtx insn = ready[i];
56e2e762 1588
23568fa0 1589 if (! m32r_is_insn (insn))
56e2e762 1590 {
23568fa0 1591 /* Dump all current short/long insns just in case. */
56e2e762
NC		 1592 while (long_head != long_tail)
1593 *new_tail-- = *long_head++;
1594
1595 while (short_head != short_tail)
1596 *new_tail-- = *short_head++;
1597
1598 *new_tail-- = insn;
1599 if (stream)
1600 fprintf (stream,
1601 ";;\t\t::: Skipping non instruction %d\n",
1602 INSN_UID (insn));
1603
1604 }
1605
1606 else
1607 {
1608 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1609 *long_tail++ = insn;
1610
1611 else
1612 *short_tail++ = insn;
1613 }
1614 }
1615
1616 /* If we are on an odd word, emit a single short instruction if
1617 we can */
1618 if (m32r_sched_odd_word_p && short_head != short_tail)
1619 *new_tail-- = *short_head++;
1620
1621 /* Now dump out all of the long instructions */
1622 while (long_head != long_tail)
1623 *new_tail-- = *long_head++;
1624
1625 /* Now dump out all of the short instructions */
1626 while (short_head != short_tail)
1627 *new_tail-- = *short_head++;
1628
1629 if (new_tail+1 != new_head)
1630 abort ();
1631
6439a1f2 1632 memcpy (ready, new_head, sizeof (rtx) * n_ready);
56e2e762
NC		 1633 if (stream)
1634 {
56e2e762 1635 int i;
c237e94a 1636 fprintf (stream, ";;\t\t::: New ready list: ");
56e2e762
NC		 1637 for (i = 0; i < n_ready; i++)
1638 {
1639 rtx insn = ready[i];
56e2e762
NC		 1640
1641 fprintf (stream, " %d", INSN_UID (ready[i]));
23568fa0
NC		 1642
1643 if (! m32r_is_insn (insn))
56e2e762
NC		 1644 fputs ("(?)", stream);
1645
1646 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1647 fputs ("(l)", stream);
1648
1649 else
1650 fputs ("(s)", stream);
1651 }
1652
1653 fprintf (stream, "\n");
56e2e762
NC		 1654 }
1655 }
c237e94a
ZW		 1656 return m32r_issue_rate ();
1657}
1658
1659/* Indicate how many instructions can be issued at the same time.
1660 This is sort of a lie. The m32r can issue only 1 long insn at
1661 once, but it can issue 2 short insns. The default therefore is
1662 set at 2, but this can be overridden by the command line option
1663 -missue-rate=1 */
1664static int
1665m32r_issue_rate ()
1666{
1667 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
56e2e762
NC		 1668}
1669
56e2e762
NC		 1670/* If we have a machine that can issue a variable # of instructions
1671 per cycle, indicate how many more instructions can be issued
1672 after the current one. */
c237e94a
ZW		 1673static int
1674m32r_variable_issue (stream, verbose, insn, how_many)
56e2e762
NC		 1675 FILE * stream;
1676 int verbose;
1677 rtx insn;
1678 int how_many;
1679{
1680 int orig_odd_word_p = m32r_sched_odd_word_p;
1681 int short_p = FALSE;
1682
1683 how_many--;
1684 if (how_many > 0 && !TARGET_DEBUG)
1685 {
23568fa0 1686 if (! m32r_is_insn (insn))
56e2e762
NC		 1687 how_many++;
1688
1689 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1690 {
1691 how_many = 0;
1692 m32r_sched_odd_word_p = 0;
1693 }
1694 else
1695 {
1696 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1697 short_p = TRUE;
1698 }
1699 }
1700
1701 if (verbose > 7 && stream)
1702 fprintf (stream,
1703 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1704 short_p ? "short" : "long",
1705 INSN_UID (insn),
1706 orig_odd_word_p ? "odd" : "even",
1707 how_many);
1708
1709 return how_many;
1710}
1711\f
8c5ca3b9
DE		 1712/* Cost functions. */
1713
3c50106f
RH		 1714static bool
1715m32r_rtx_costs (x, code, outer_code, total)
1716 rtx x;
1717 int code, outer_code ATTRIBUTE_UNUSED;
1718 int *total;
1719{
1720 switch (code)
1721 {
1722 /* Small integers are as cheap as registers. 4 byte values can be
1723 fetched as immediate constants - let's give that the cost of an
1724 extra insn. */
1725 case CONST_INT:
1726 if (INT16_P (INTVAL (x)))
1727 {
1728 *total = 0;
1729 return true;
1730 }
1731 /* FALLTHRU */
1732
1733 case CONST:
1734 case LABEL_REF:
1735 case SYMBOL_REF:
1736 *total = COSTS_N_INSNS (1);
1737 return true;
1738
1739 case CONST_DOUBLE:
1740 {
1741 rtx high, low;
1742 split_double (x, &high, &low);
1743 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1744 + !INT16_P (INTVAL (low)));
1745 return true;
1746 }
1747
1748 case MULT:
1749 *total = COSTS_N_INSNS (3);
1750 return true;
1751
1752 case DIV:
1753 case UDIV:
1754 case MOD:
1755 case UMOD:
1756 *total = COSTS_N_INSNS (10);
1757 return true;
1758
1759 default:
1760 return false;
1761 }
1762}
8c5ca3b9
DE		 1763\f
1764/* Type of function DECL.
1765
1766 The result is cached. To reset the cache at the end of a function,
1767 call with DECL = NULL_TREE. */
1768
1769enum m32r_function_type
1770m32r_compute_function_type (decl)
1771 tree decl;
1772{
1773 /* Cached value. */
1774 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1775 /* Last function we were called for. */
1776 static tree last_fn = NULL_TREE;
1777
1778 /* Resetting the cached value? */
1779 if (decl == NULL_TREE)
1780 {
1781 fn_type = M32R_FUNCTION_UNKNOWN;
1782 last_fn = NULL_TREE;
1783 return fn_type;
1784 }
1785
1786 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1787 return fn_type;
1788
1789 /* Compute function type. */
91d231cb 1790 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
8c5ca3b9
DE		 1791 ? M32R_FUNCTION_INTERRUPT
1792 : M32R_FUNCTION_NORMAL);
1793
1794 last_fn = decl;
1795 return fn_type;
1796}
1797\f/* Function prologue/epilogue handlers. */
1798
1799/* M32R stack frames look like:
1800
1801 Before call After call
1802 +-----------------------+ +-----------------------+
1803 | | | |
1804 high | local variables, | | local variables, |
1805 mem | reg save area, etc. | | reg save area, etc. |
1806 | | | |
1807 +-----------------------+ +-----------------------+
1808 | | | |
1809 | arguments on stack. | | arguments on stack. |
1810 | | | |
1811 SP+0->+-----------------------+ +-----------------------+
1812 | reg parm save area, |
1813 | only created for |
1814 | variable argument |
1815 | functions |
1816 +-----------------------+
1817 | previous frame ptr |
1818 +-----------------------+
1819 | |
1820 | register save area |
1821 | |
1822 +-----------------------+
1823 | return address |
1824 +-----------------------+
1825 | |
1826 | local variables |
1827 | |
1828 +-----------------------+
1829 | |
1830 | alloca allocations |
1831 | |
1832 +-----------------------+
1833 | |
1834 low | arguments on stack |
1835 memory | |
1836 SP+0->+-----------------------+
1837
1838Notes:
18391) The "reg parm save area" does not exist for non variable argument fns.
18402) The "reg parm save area" can be eliminated completely if we saved regs
1841 containing anonymous args separately but that complicates things too
1842 much (so it's not done).
18433) The return address is saved after the register save area so as to have as
1844 many insns as possible between the restoration of `lr' and the `jmp lr'.
1845*/
1846
1847/* Structure to be filled in by m32r_compute_frame_size with register
1848 save masks, and offsets for the current function. */
1849struct m32r_frame_info
1850{
1851 unsigned int total_size; /* # bytes that the entire frame takes up */
1852 unsigned int extra_size; /* # bytes of extra stuff */
1853 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1854 unsigned int args_size; /* # bytes that outgoing arguments take up */
1855 unsigned int reg_size; /* # bytes needed to store regs */
1856 unsigned int var_size; /* # bytes that variables take up */
1857 unsigned int gmask; /* mask of saved gp registers */
1858 unsigned int save_fp; /* nonzero if fp must be saved */
1859 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1860 int initialized; /* nonzero if frame size already calculated */
1861};
1862
1863/* Current frame information calculated by m32r_compute_frame_size. */
1864static struct m32r_frame_info current_frame_info;
1865
1866/* Zero structure to initialize current_frame_info. */
1867static struct m32r_frame_info zero_frame_info;
1868
1869#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1870#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1871
1872/* Tell prologue and epilogue if register REGNO should be saved / restored.
1873 The return address and frame pointer are treated separately.
1874 Don't consider them here. */
1875#define MUST_SAVE_REGISTER(regno, interrupt_p) \
1876((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1877 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1878
1879#define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
70f4f91c 1880#define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
8c5ca3b9 1881
2b7972b0
MM		 1882#define SHORT_INSN_SIZE 2 /* size of small instructions */
1883#define LONG_INSN_SIZE 4 /* size of long instructions */
1884
8c5ca3b9
DE		 1885/* Return the bytes needed to compute the frame pointer from the current
1886 stack pointer.
1887
1888 SIZE is the size needed for local variables. */
1889
1890unsigned int
1891m32r_compute_frame_size (size)
1892 int size; /* # of var. bytes allocated. */
1893{
1894 int regno;
1895 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
5b8ae21f 1896 unsigned int reg_size, frame_size;
8c5ca3b9
DE		 1897 unsigned int gmask;
1898 enum m32r_function_type fn_type;
1899 int interrupt_p;
1900
1901 var_size = M32R_STACK_ALIGN (size);
1902 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1903 pretend_size = current_function_pretend_args_size;
1904 extra_size = FIRST_PARM_OFFSET (0);
1905 total_size = extra_size + pretend_size + args_size + var_size;
1906 reg_size = 0;
1907 gmask = 0;
1908
1909 /* See if this is an interrupt handler. Call used registers must be saved
1910 for them too. */
1911 fn_type = m32r_compute_function_type (current_function_decl);
1912 interrupt_p = M32R_INTERRUPT_P (fn_type);
1913
1914 /* Calculate space needed for registers. */
1915
1916 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1917 {
1918 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1919 {
1920 reg_size += UNITS_PER_WORD;
1921 gmask |= 1 << regno;
1922 }
1923 }
1924
1925 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1926 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1927
1928 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1929 * UNITS_PER_WORD);
1930 total_size += reg_size;
1931
efbbf34f 1932 /* ??? Not sure this is necessary, and I don't think the epilogue
8c5ca3b9
DE		 1933 handler will do the right thing if this changes total_size. */
1934 total_size = M32R_STACK_ALIGN (total_size);
1935
2b7972b0
MM		 1936 frame_size = total_size - (pretend_size + reg_size);
1937
8c5ca3b9
DE		 1938 /* Save computed information. */
1939 current_frame_info.total_size = total_size;
1940 current_frame_info.extra_size = extra_size;
1941 current_frame_info.pretend_size = pretend_size;
1942 current_frame_info.var_size = var_size;
1943 current_frame_info.args_size = args_size;
1944 current_frame_info.reg_size = reg_size;
1945 current_frame_info.gmask = gmask;
1946 current_frame_info.initialized = reload_completed;
1947
1948 /* Ok, we're done. */
1949 return total_size;
1950}
1951\f
2b7972b0
MM		 1952/* When the `length' insn attribute is used, this macro specifies the
1953 value to be assigned to the address of the first insn in a
1954 function. If not specified, 0 is used. */
1955
1956int
1957m32r_first_insn_address ()
1958{
1959 if (! current_frame_info.initialized)
1960 m32r_compute_frame_size (get_frame_size ());
1961
5b8ae21f 1962 return 0;
2b7972b0
MM		 1963}
1964\f
5b8ae21f 1965/* Expand the m32r prologue as a series of insns. */
8c5ca3b9
DE		 1966
1967void
5b8ae21f 1968m32r_expand_prologue ()
8c5ca3b9
DE		 1969{
1970 int regno;
5b8ae21f 1971 int frame_size;
56e2e762 1972 unsigned int gmask;
8c5ca3b9 1973
5b8ae21f
MM		 1974 if (! current_frame_info.initialized)
1975 m32r_compute_frame_size (get_frame_size ());
2b7972b0 1976
5b8ae21f 1977 gmask = current_frame_info.gmask;
8c5ca3b9
DE		 1978
1979 /* These cases shouldn't happen. Catch them now. */
5b8ae21f 1980 if (current_frame_info.total_size == 0 && gmask)
8c5ca3b9
DE		 1981 abort ();
1982
8c5ca3b9
DE		 1983 /* Allocate space for register arguments if this is a variadic function. */
1984 if (current_frame_info.pretend_size != 0)
737e7965
JW		 1985 {
1986 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1987 the wrong result on a 64-bit host. */
1988 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1989 emit_insn (gen_addsi3 (stack_pointer_rtx,
1990 stack_pointer_rtx,
1991 GEN_INT (-pretend_size)));
1992 }
8c5ca3b9
DE		 1993
1994 /* Save any registers we need to and set up fp. */
1995
1996 if (current_frame_info.save_fp)
5b8ae21f 1997 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
8c5ca3b9
DE		 1998
1999 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2000
2001 /* Save any needed call-saved regs (and call-used if this is an
2002 interrupt handler). */
2003 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
2004 {
2005 if ((gmask & (1 << regno)) != 0)
5b8ae21f
MM		 2006 emit_insn (gen_movsi_push (stack_pointer_rtx,
2007 gen_rtx_REG (Pmode, regno)));
8c5ca3b9
DE		 2008 }
2009
2010 if (current_frame_info.save_lr)
5b8ae21f
MM		 2011 emit_insn (gen_movsi_push (stack_pointer_rtx,
2012 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
8c5ca3b9
DE		 2013
2014 /* Allocate the stack frame. */
5b8ae21f
MM		 2015 frame_size = (current_frame_info.total_size
2016 - (current_frame_info.pretend_size
2017 + current_frame_info.reg_size));
2018
8c5ca3b9
DE		 2019 if (frame_size == 0)
2020 ; /* nothing to do */
8c5ca3b9 2021 else if (frame_size <= 32768)
5b8ae21f
MM		 2022 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2023 GEN_INT (-frame_size)));
8c5ca3b9 2024 else
5b8ae21f
MM		 2025 {
2026 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2027 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2028 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2029 }
8c5ca3b9
DE		 2030
2031 if (frame_pointer_needed)
5b8ae21f
MM		 2032 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2033
70f4f91c 2034 if (current_function_profile)
5b8ae21f
MM		 2035 emit_insn (gen_blockage ());
2036}
2037
2038\f
2039/* Set up the stack and frame pointer (if desired) for the function.
2040 Note, if this is changed, you need to mirror the changes in
2041 m32r_compute_frame_size which calculates the prolog size. */
2042
08c148a8 2043static void
5b8ae21f
MM		 2044m32r_output_function_prologue (file, size)
2045 FILE * file;
08c148a8 2046 HOST_WIDE_INT size;
5b8ae21f
MM		 2047{
2048 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2049
2050 /* If this is an interrupt handler, mark it as such. */
2051 if (M32R_INTERRUPT_P (fn_type))
2052 {
2053 fprintf (file, "\t%s interrupt handler\n",
2054 ASM_COMMENT_START);
2055 }
2056
2057 if (! current_frame_info.initialized)
2058 m32r_compute_frame_size (size);
8c5ca3b9 2059
5b8ae21f
MM		 2060 /* This is only for the human reader. */
2061 fprintf (file,
2062 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2063 ASM_COMMENT_START,
2064 current_frame_info.var_size,
2065 current_frame_info.reg_size / 4,
2066 current_frame_info.args_size,
2067 current_frame_info.extra_size);
8c5ca3b9
DE		 2068}
2069\f
2070/* Do any necessary cleanup after a function to restore stack, frame,
2071 and regs. */
2072
08c148a8 2073static void
8c5ca3b9 2074m32r_output_function_epilogue (file, size)
2e076ddf 2075 FILE * file;
08c148a8 2076 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 2077{
2078 int regno;
2079 int noepilogue = FALSE;
2080 int total_size;
2081 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2082
2083 /* This is only for the human reader. */
2084 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2085
2086 if (!current_frame_info.initialized)
2087 abort ();
2088 total_size = current_frame_info.total_size;
2089
2090 if (total_size == 0)
2091 {
2092 rtx insn = get_last_insn ();
2093
2094 /* If the last insn was a BARRIER, we don't have to write any code
2095 because a jump (aka return) was put there. */
2096 if (GET_CODE (insn) == NOTE)
2097 insn = prev_nonnote_insn (insn);
2098 if (insn && GET_CODE (insn) == BARRIER)
2099 noepilogue = TRUE;
2100 }
2101
2102 if (!noepilogue)
2103 {
8c5ca3b9
DE		 2104 unsigned int var_size = current_frame_info.var_size;
2105 unsigned int args_size = current_frame_info.args_size;
2106 unsigned int gmask = current_frame_info.gmask;
2107 int can_trust_sp_p = !current_function_calls_alloca;
99f44eba
KG		 2108 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2109 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
8c5ca3b9
DE		 2110
2111 /* The first thing to do is point the sp at the bottom of the register
2112 save area. */
2113 if (can_trust_sp_p)
2114 {
2115 unsigned int reg_offset = var_size + args_size;
2116 if (reg_offset == 0)
2117 ; /* nothing to do */
630f5ae6
DE		 2118 else if (reg_offset < 128)
2119 fprintf (file, "\taddi %s,%s%d\n",
2120 sp_str, IMMEDIATE_PREFIX, reg_offset);
8c5ca3b9 2121 else if (reg_offset < 32768)
630f5ae6
DE		 2122 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2123 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
8c5ca3b9 2124 else
630f5ae6
DE		 2125 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2126 reg_names[PROLOGUE_TMP_REGNUM],
2127 IMMEDIATE_PREFIX, reg_offset,
8c5ca3b9
DE		 2128 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2129 }
2130 else if (frame_pointer_needed)
2131 {
2132 unsigned int reg_offset = var_size + args_size;
2133 if (reg_offset == 0)
2134 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2135 else if (reg_offset < 32768)
630f5ae6
DE		 2136 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2137 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
8c5ca3b9 2138 else
630f5ae6
DE		 2139 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2140 reg_names[PROLOGUE_TMP_REGNUM],
2141 IMMEDIATE_PREFIX, reg_offset,
8c5ca3b9
DE		 2142 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2143 }
2144 else
2145 abort ();
2146
2147 if (current_frame_info.save_lr)
2148 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2149
2150 /* Restore any saved registers, in reverse order of course. */
2151 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2152 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2153 {
2154 if ((gmask & (1L << regno)) != 0)
2155 fprintf (file, "\tpop %s\n", reg_names[regno]);
2156 }
2157
2158 if (current_frame_info.save_fp)
2159 fprintf (file, "\tpop %s\n", fp_str);
2160
2161 /* Remove varargs area if present. */
8c5ca3b9 2162 if (current_frame_info.pretend_size != 0)
630f5ae6
DE		 2163 fprintf (file, "\taddi %s,%s%d\n",
2164 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
8c5ca3b9
DE		 2165
2166 /* Emit the return instruction. */
2167 if (M32R_INTERRUPT_P (fn_type))
2168 fprintf (file, "\trte\n");
2169 else
2170 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2171 }
2172
2173#if 0 /* no longer needed */
2174 /* Ensure the function cleanly ends on a 32 bit boundary. */
2175 fprintf (file, "\t.fillinsn\n");
2176#endif
2177
2178 /* Reset state info for each function. */
2179 current_frame_info = zero_frame_info;
2180 m32r_compute_function_type (NULL_TREE);
2181}
56e2e762 2182\f
a0ab749a 2183/* Return nonzero if this function is known to have a null or 1 instruction
56e2e762
NC		 2184 epilogue. */
2185
2186int
2187direct_return ()
2188{
2189 if (!reload_completed)
2190 return FALSE;
2191
2192 if (! current_frame_info.initialized)
2193 m32r_compute_frame_size (get_frame_size ());
2194
2195 return current_frame_info.total_size == 0;
2196}
2197
8c5ca3b9
DE		 2198\f
2199/* PIC */
2200
2201/* Emit special PIC prologues and epilogues. */
2202
2203void
2204m32r_finalize_pic ()
2205{
2206 /* nothing to do */
2207}
2208\f
2209/* Nested function support. */
2210
2211/* Emit RTL insns to initialize the variable parts of a trampoline.
2212 FNADDR is an RTX for the address of the function's pure code.
2213 CXT is an RTX for the static chain value for the function. */
2214
2215void
2216m32r_initialize_trampoline (tramp, fnaddr, cxt)
61f3b78f
RH		 2217 rtx tramp ATTRIBUTE_UNUSED;
2218 rtx fnaddr ATTRIBUTE_UNUSED;
2219 rtx cxt ATTRIBUTE_UNUSED;
8c5ca3b9
DE		 2220{
2221}
2222\f
1bc7c5b6
ZW		 2223static void
2224m32r_file_start ()
8c5ca3b9 2225{
1bc7c5b6
ZW		 2226 default_file_start ();
2227
8c5ca3b9 2228 if (flag_verbose_asm)
1bc7c5b6 2229 fprintf (asm_out_file,
307b599c 2230 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8c5ca3b9
DE		 2231 ASM_COMMENT_START, g_switch_value);
2232}
2233\f
2234/* Print operand X (an rtx) in assembler syntax to file FILE.
2235 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2236 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2237
2238void
2239m32r_print_operand (file, x, code)
2e076ddf
NC		 2240 FILE * file;
2241 rtx x;
2242 int code;
8c5ca3b9 2243{
5b8ae21f
MM		 2244 rtx addr;
2245
8c5ca3b9
DE		 2246 switch (code)
2247 {
d2a73f8e
NC		 2248 /* The 's' and 'p' codes are used by output_block_move() to
2249 indicate post-increment 's'tores and 'p're-increment loads. */
2250 case 's':
2251 if (GET_CODE (x) == REG)
2252 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2253 else
a52453cc 2254 output_operand_lossage ("invalid operand to %%s code");
d2a73f8e
NC		 2255 return;
2256
2257 case 'p':
2258 if (GET_CODE (x) == REG)
2259 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2260 else
a52453cc 2261 output_operand_lossage ("invalid operand to %%p code");
d2a73f8e
NC		 2262 return;
2263
8c5ca3b9
DE		 2264 case 'R' :
2265 /* Write second word of DImode or DFmode reference,
2266 register or memory. */
2267 if (GET_CODE (x) == REG)
2268 fputs (reg_names[REGNO (x)+1], file);
2269 else if (GET_CODE (x) == MEM)
2270 {
2271 fprintf (file, "@(");
2272 /* Handle possible auto-increment. Since it is pre-increment and
2273 we have already done it, we can just use an offset of four. */
2274 /* ??? This is taken from rs6000.c I think. I don't think it is
2275 currently necessary, but keep it around. */
2276 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2277 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2278 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2279 else
2280 output_address (plus_constant (XEXP (x, 0), 4));
2281 fputc (')', file);
2282 }
2283 else
a52453cc 2284 output_operand_lossage ("invalid operand to %%R code");
8c5ca3b9
DE		 2285 return;
2286
2287 case 'H' : /* High word */
2288 case 'L' : /* Low word */
2289 if (GET_CODE (x) == REG)
2290 {
2291 /* L = least significant word, H = most significant word */
2292 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2293 fputs (reg_names[REGNO (x)], file);
2294 else
2295 fputs (reg_names[REGNO (x)+1], file);
2296 }
2297 else if (GET_CODE (x) == CONST_INT
2298 || GET_CODE (x) == CONST_DOUBLE)
2299 {
2300 rtx first, second;
2301
2302 split_double (x, &first, &second);
61f3b78f 2303 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8c5ca3b9
DE		 2304 code == 'L' ? INTVAL (first) : INTVAL (second));
2305 }
2306 else
a52453cc 2307 output_operand_lossage ("invalid operand to %%H/%%L code");
8c5ca3b9
DE		 2308 return;
2309
2310 case 'A' :
2311 {
8c5ca3b9
DE		 2312 char str[30];
2313
2314 if (GET_CODE (x) != CONST_DOUBLE
2315 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
c725bd79 2316 fatal_insn ("bad insn for 'A'", x);
da6eec72
RH		 2317
2318 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
8c5ca3b9
DE		 2319 fprintf (file, "%s", str);
2320 return;
2321 }
2322
2323 case 'B' : /* Bottom half */
2324 case 'T' : /* Top half */
2325 /* Output the argument to a `seth' insn (sets the Top half-word).
2326 For constants output arguments to a seth/or3 pair to set Top and
2327 Bottom halves. For symbols output arguments to a seth/add3 pair to
2328 set Top and Bottom halves. The difference exists because for
2329 constants seth/or3 is more readable but for symbols we need to use
2330 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2331 switch (GET_CODE (x))
2332 {
2333 case CONST_INT :
2334 case CONST_DOUBLE :
2335 {
2336 rtx first, second;
2337
2338 split_double (x, &first, &second);
2339 x = WORDS_BIG_ENDIAN ? second : first;
89e6b702 2340 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8c5ca3b9
DE		 2341 (code == 'B'
2342 ? INTVAL (x) & 0xffff
2343 : (INTVAL (x) >> 16) & 0xffff));
2344 }
2345 return;
2346 case CONST :
2347 case SYMBOL_REF :
2348 if (code == 'B'
2349 && small_data_operand (x, VOIDmode))
2350 {
2351 fputs ("sda(", file);
2352 output_addr_const (file, x);
2353 fputc (')', file);
2354 return;
2355 }
2356 /* fall through */
2357 case LABEL_REF :
2358 fputs (code == 'T' ? "shigh(" : "low(", file);
2359 output_addr_const (file, x);
2360 fputc (')', file);
2361 return;
2362 default :
a52453cc 2363 output_operand_lossage ("invalid operand to %%T/%%B code");
8c5ca3b9
DE		 2364 return;
2365 }
2366 break;
2367
2368 case 'U' :
2e076ddf 2369 /* ??? wip */
8c5ca3b9
DE		 2370 /* Output a load/store with update indicator if appropriate. */
2371 if (GET_CODE (x) == MEM)
2372 {
2373 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2374 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2375 fputs (".a", file);
2376 }
2377 else
a52453cc 2378 output_operand_lossage ("invalid operand to %%U code");
8c5ca3b9
DE		 2379 return;
2380
2381 case 'N' :
2382 /* Print a constant value negated. */
2383 if (GET_CODE (x) == CONST_INT)
2384 output_addr_const (file, GEN_INT (- INTVAL (x)));
2385 else
a52453cc 2386 output_operand_lossage ("invalid operand to %%N code");
8c5ca3b9
DE		 2387 return;
2388
4d6c607f
DE		 2389 case 'X' :
2390 /* Print a const_int in hex. Used in comments. */
2391 if (GET_CODE (x) == CONST_INT)
89e6b702 2392 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
4d6c607f
DE		 2393 return;
2394
8c5ca3b9
DE		 2395 case '#' :
2396 fputs (IMMEDIATE_PREFIX, file);
2397 return;
2398
2399#if 0 /* ??? no longer used */
2400 case '@' :
2401 fputs (reg_names[SDA_REGNUM], file);
2402 return;
2403#endif
2404
2405 case 0 :
2406 /* Do nothing special. */
2407 break;
2408
2409 default :
2410 /* Unknown flag. */
2411 output_operand_lossage ("invalid operand output code");
2412 }
2413
2414 switch (GET_CODE (x))
2415 {
2416 case REG :
2417 fputs (reg_names[REGNO (x)], file);
2418 break;
2419
2420 case MEM :
5b8ae21f
MM		 2421 addr = XEXP (x, 0);
2422 if (GET_CODE (addr) == PRE_INC)
2423 {
2424 if (GET_CODE (XEXP (addr, 0)) != REG)
c725bd79 2425 fatal_insn ("pre-increment address is not a register", x);
5b8ae21f
MM		 2426
2427 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2428 }
2429 else if (GET_CODE (addr) == PRE_DEC)
2430 {
2431 if (GET_CODE (XEXP (addr, 0)) != REG)
c725bd79 2432 fatal_insn ("pre-decrement address is not a register", x);
5b8ae21f
MM		 2433
2434 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2435 }
2436 else if (GET_CODE (addr) == POST_INC)
2437 {
2438 if (GET_CODE (XEXP (addr, 0)) != REG)
c725bd79 2439 fatal_insn ("post-increment address is not a register", x);
5b8ae21f
MM		 2440
2441 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2442 }
8c5ca3b9 2443 else
5b8ae21f
MM		 2444 {
2445 fputs ("@(", file);
2446 output_address (XEXP (x, 0));
2447 fputc (')', file);
2448 }
8c5ca3b9
DE		 2449 break;
2450
2451 case CONST_DOUBLE :
2452 /* We handle SFmode constants here as output_addr_const doesn't. */
2453 if (GET_MODE (x) == SFmode)
2454 {
2455 REAL_VALUE_TYPE d;
2456 long l;
2457
2458 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2459 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2460 fprintf (file, "0x%08lx", l);
2461 break;
2462 }
2463
2464 /* Fall through. Let output_addr_const deal with it. */
2465
2466 default :
2467 output_addr_const (file, x);
2468 break;
2469 }
2470}
2471
2472/* Print a memory address as an operand to reference that memory location. */
2473
2474void
2475m32r_print_operand_address (file, addr)
2e076ddf
NC		 2476 FILE * file;
2477 rtx addr;
8c5ca3b9 2478{
2e076ddf
NC		 2479 register rtx base;
2480 register rtx index = 0;
2481 int offset = 0;
8c5ca3b9
DE		 2482
2483 switch (GET_CODE (addr))
2484 {
2485 case REG :
2486 fputs (reg_names[REGNO (addr)], file);
2487 break;
2488
2489 case PLUS :
2490 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2491 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2492 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2493 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2494 else
2495 base = XEXP (addr, 0), index = XEXP (addr, 1);
2496 if (GET_CODE (base) == REG)
2497 {
2498 /* Print the offset first (if present) to conform to the manual. */
2499 if (index == 0)
2500 {
2501 if (offset != 0)
2502 fprintf (file, "%d,", offset);
2503 fputs (reg_names[REGNO (base)], file);
2504 }
2505 /* The chip doesn't support this, but left in for generality. */
2506 else if (GET_CODE (index) == REG)
2507 fprintf (file, "%s,%s",
2508 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2509 /* Not sure this can happen, but leave in for now. */
2510 else if (GET_CODE (index) == SYMBOL_REF)
2511 {
2512 output_addr_const (file, index);
2513 fputc (',', file);
2514 fputs (reg_names[REGNO (base)], file);
2515 }
2516 else
c725bd79 2517 fatal_insn ("bad address", addr);
8c5ca3b9
DE		 2518 }
2519 else if (GET_CODE (base) == LO_SUM)
2520 {
2521 if (index != 0
2522 || GET_CODE (XEXP (base, 0)) != REG)
2523 abort ();
2524 if (small_data_operand (XEXP (base, 1), VOIDmode))
2525 fputs ("sda(", file);
2526 else
2527 fputs ("low(", file);
2528 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2529 fputs ("),", file);
2530 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2531 }
2532 else
c725bd79 2533 fatal_insn ("bad address", addr);
8c5ca3b9
DE		 2534 break;
2535
2536 case LO_SUM :
2537 if (GET_CODE (XEXP (addr, 0)) != REG)
c725bd79 2538 fatal_insn ("lo_sum not of register", addr);
8c5ca3b9
DE		 2539 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2540 fputs ("sda(", file);
2541 else
2542 fputs ("low(", file);
2543 output_addr_const (file, XEXP (addr, 1));
2544 fputs ("),", file);
2545 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2546 break;
2547
5b8ae21f
MM		 2548 case PRE_INC : /* Assume SImode */
2549 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2550 break;
2551
2552 case PRE_DEC : /* Assume SImode */
2553 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2554 break;
2555
2556 case POST_INC : /* Assume SImode */
2557 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
8c5ca3b9
DE		 2558 break;
2559
2560 default :
2561 output_addr_const (file, addr);
2562 break;
2563 }
2564}
2b7972b0
MM		 2565
2566/* Return true if the operands are the constants 0 and 1. */
2567int
2568zero_and_one (operand1, operand2)
2569 rtx operand1;
2570 rtx operand2;
2571{
2572 return
2573 GET_CODE (operand1) == CONST_INT
2574 && GET_CODE (operand2) == CONST_INT
2575 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2576 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2577}
2578
a0ab749a 2579/* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2b7972b0 2580int
56e2e762 2581conditional_move_operand (operand, mode)
2b7972b0 2582 rtx operand;
56e2e762 2583 enum machine_mode mode;
2b7972b0 2584{
2b7972b0
MM		 2585 /* Only defined for simple integers so far... */
2586 if (mode != SImode && mode != HImode && mode != QImode)
2587 return FALSE;
2588
dab66575 2589 /* At the moment we can handle moving registers and loading constants. */
2b7972b0
MM		 2590 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2591
2592 switch (GET_CODE (operand))
2593 {
2594 case REG:
2595 return 1;
2596
2597 case CONST_INT:
2598 return INT8_P (INTVAL (operand));
2599
2600 default:
2601#if 0
2602 fprintf (stderr, "Test for cond move op of type: %s\n",
2603 GET_RTX_NAME (GET_CODE (operand)));
2604#endif
2605 return 0;
2606 }
2607}
2608
2609/* Return true if the code is a test of the carry bit */
2610int
56e2e762 2611carry_compare_operand (op, mode)
2b7972b0 2612 rtx op;
56e2e762 2613 enum machine_mode mode ATTRIBUTE_UNUSED;
2b7972b0
MM		 2614{
2615 rtx x;
2616
56e2e762 2617 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2b7972b0
MM		 2618 return FALSE;
2619
2620 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2621 return FALSE;
2622
2623 x = XEXP (op, 0);
2624 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2625 return FALSE;
2626
2627 x = XEXP (op, 1);
2628 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2629 return FALSE;
2630
2631 return TRUE;
2632}
2633
2b7972b0
MM		 2634/* Generate the correct assembler code to handle the conditional loading of a
2635 value into a register. It is known that the operands satisfy the
2636 conditional_move_operand() function above. The destination is operand[0].
2637 The condition is operand [1]. The 'true' value is operand [2] and the
2638 'false' value is operand [3]. */
2639char *
2640emit_cond_move (operands, insn)
2641 rtx * operands;
61f3b78f 2642 rtx insn ATTRIBUTE_UNUSED;
2b7972b0
MM		 2643{
2644 static char buffer [100];
99f44eba 2645 const char * dest = reg_names [REGNO (operands [0])];
51c10c4e 2646
2b7972b0
MM		 2647 buffer [0] = 0;
2648
2649 /* Destination must be a register. */
2650 if (GET_CODE (operands [0]) != REG)
2651 abort();
2652 if (! conditional_move_operand (operands [2], SImode))
2653 abort();
2654 if (! conditional_move_operand (operands [3], SImode))
2655 abort();
2656
2b7972b0
MM		 2657 /* Check to see if the test is reversed. */
2658 if (GET_CODE (operands [1]) == NE)
2659 {
2660 rtx tmp = operands [2];
2661 operands [2] = operands [3];
2662 operands [3] = tmp;
2663 }
2664
51c10c4e 2665 sprintf (buffer, "mvfc %s, cbr", dest);
16f104b3 2666
51c10c4e
NC		 2667 /* If the true value was '0' then we need to invert the results of the move. */
2668 if (INTVAL (operands [2]) == 0)
2669 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2670 dest, dest);
16f104b3 2671
2b7972b0
MM		 2672 return buffer;
2673}
2674
56e2e762
NC		 2675/* Returns true if the registers contained in the two
2676 rtl expressions are different. */
2677int
2678m32r_not_same_reg (a, b)
2679 rtx a;
2680 rtx b;
2681{
2682 int reg_a = -1;
2683 int reg_b = -2;
2684
2685 while (GET_CODE (a) == SUBREG)
2686 a = SUBREG_REG (a);
2687
2688 if (GET_CODE (a) == REG)
2689 reg_a = REGNO (a);
2690
2691 while (GET_CODE (b) == SUBREG)
2692 b = SUBREG_REG (b);
2693
2694 if (GET_CODE (b) == REG)
2695 reg_b = REGNO (b);
2696
2697 return reg_a != reg_b;
2698}
d2a73f8e
NC		 2699
2700\f
2701/* Use a library function to move some bytes. */
2702static void
2703block_move_call (dest_reg, src_reg, bytes_rtx)
2704 rtx dest_reg;
2705 rtx src_reg;
2706 rtx bytes_rtx;
2707{
2708 /* We want to pass the size as Pmode, which will normally be SImode
2709 but will be DImode if we are using 64 bit longs and pointers. */
2710 if (GET_MODE (bytes_rtx) != VOIDmode
2711 && GET_MODE (bytes_rtx) != Pmode)
2712 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2713
2714#ifdef TARGET_MEM_FUNCTIONS
2715 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2716 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2717 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2718 TREE_UNSIGNED (sizetype)),
2719 TYPE_MODE (sizetype));
2720#else
2721 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2722 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2723 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2724 TREE_UNSIGNED (integer_type_node)),
2725 TYPE_MODE (integer_type_node));
2726#endif
2727}
2728
2729/* The maximum number of bytes to copy using pairs of load/store instructions.
2730 If a block is larger than this then a loop will be generated to copy
dab66575 2731 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
d2a73f8e
NC		 2732 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2733 string copy in it. */
2734#define MAX_MOVE_BYTES 32
2735
2736/* Expand string/block move operations.
2737
2738 operands[0] is the pointer to the destination.
2739 operands[1] is the pointer to the source.
2740 operands[2] is the number of bytes to move.
2741 operands[3] is the alignment. */
2742
2743void
2744m32r_expand_block_move (operands)
2745 rtx operands[];
2746{
2747 rtx orig_dst = operands[0];
2748 rtx orig_src = operands[1];
2749 rtx bytes_rtx = operands[2];
2750 rtx align_rtx = operands[3];
2751 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2752 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2753 int align = INTVAL (align_rtx);
2754 int leftover;
2755 rtx src_reg;
2756 rtx dst_reg;
2757
2758 if (constp && bytes <= 0)
2759 return;
2760
2761 /* Move the address into scratch registers. */
2762 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2763 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2764
2765 if (align > UNITS_PER_WORD)
2766 align = UNITS_PER_WORD;
2767
2768 /* If we prefer size over speed, always use a function call.
2769 If we do not know the size, use a function call.
2770 If the blocks are not word aligned, use a function call. */
2771 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2772 {
2773 block_move_call (dst_reg, src_reg, bytes_rtx);
2774 return;
2775 }
2776
2777 leftover = bytes % MAX_MOVE_BYTES;
2778 bytes -= leftover;
2779
2780 /* If necessary, generate a loop to handle the bulk of the copy. */
2781 if (bytes)
2782 {
950a3816
KG		 2783 rtx label = NULL_RTX;
2784 rtx final_src = NULL_RTX;
0ae9f65b
DE		 2785 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2786 rtx rounded_total = GEN_INT (bytes);
d2a73f8e
NC		 2787
2788 /* If we are going to have to perform this loop more than
2789 once, then generate a label and compute the address the
2790 source register will contain upon completion of the final
dab66575 2791 iteration. */
d2a73f8e
NC		 2792 if (bytes > MAX_MOVE_BYTES)
2793 {
2794 final_src = gen_reg_rtx (Pmode);
2795
2796 if (INT16_P(bytes))
0ae9f65b 2797 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
d2a73f8e
NC		 2798 else
2799 {
0ae9f65b 2800 emit_insn (gen_movsi (final_src, rounded_total));
d2a73f8e
NC		 2801 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2802 }
2803
2804 label = gen_label_rtx ();
2805 emit_label (label);
2806 }
2807
2808 /* It is known that output_block_move() will update src_reg to point
2809 to the word after the end of the source block, and dst_reg to point
2810 to the last word of the destination block, provided that the block
2811 is MAX_MOVE_BYTES long. */
0ae9f65b 2812 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
d2a73f8e
NC		 2813 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2814
2815 if (bytes > MAX_MOVE_BYTES)
2816 {
2817 emit_insn (gen_cmpsi (src_reg, final_src));
2818 emit_jump_insn (gen_bne (label));
2819 }
2820 }
2821
2822 if (leftover)
2823 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2824}
2825
2826\f
2827/* Emit load/stores for a small constant word aligned block_move.
2828
2829 operands[0] is the memory address of the destination.
2830 operands[1] is the memory address of the source.
2831 operands[2] is the number of bytes to move.
2832 operands[3] is a temp register.
2833 operands[4] is a temp register. */
2834
16f104b3 2835void
d2a73f8e 2836m32r_output_block_move (insn, operands)
61f3b78f 2837 rtx insn ATTRIBUTE_UNUSED;
d2a73f8e
NC		 2838 rtx operands[];
2839{
2840 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2841 int first_time;
2842 int got_extra = 0;
2843
2844 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2845 abort ();
2846
2847 /* We do not have a post-increment store available, so the first set of
2848 stores are done without any increment, then the remaining ones can use
2849 the pre-increment addressing mode.
2850
a0ab749a 2851 Note: expand_block_move() also relies upon this behavior when building
d2a73f8e
NC		 2852 loops to copy large blocks. */
2853 first_time = 1;
2854
2855 while (bytes > 0)
2856 {
2857 if (bytes >= 8)
2858 {
2859 if (first_time)
2860 {
2861 output_asm_insn ("ld\t%3, %p1", operands);
2862 output_asm_insn ("ld\t%4, %p1", operands);
2863 output_asm_insn ("st\t%3, @%0", operands);
2864 output_asm_insn ("st\t%4, %s0", operands);
2865 }
2866 else
2867 {
2868 output_asm_insn ("ld\t%3, %p1", operands);
2869 output_asm_insn ("ld\t%4, %p1", operands);
2870 output_asm_insn ("st\t%3, %s0", operands);
2871 output_asm_insn ("st\t%4, %s0", operands);
2872 }
2873
2874 bytes -= 8;
2875 }
2876 else if (bytes >= 4)
2877 {
2878 if (bytes > 4)
2879 got_extra = 1;
2880
2881 output_asm_insn ("ld\t%3, %p1", operands);
2882
2883 if (got_extra)
2884 output_asm_insn ("ld\t%4, %p1", operands);
2885
2886 if (first_time)
2887 output_asm_insn ("st\t%3, @%0", operands);
2888 else
2889 output_asm_insn ("st\t%3, %s0", operands);
2890
2891 bytes -= 4;
2892 }
2893 else
2894 {
2895 /* Get the entire next word, even though we do not want all of it.
2896 The saves us from doing several smaller loads, and we assume that
2897 we cannot cause a page fault when at least part of the word is in
0ae9f65b
DE		 2898 valid memory [since we don't get called if things aren't properly
2899 aligned]. */
2900 int dst_offset = first_time ? 0 : 4;
2901 int last_shift;
2902 rtx my_operands[3];
2903
2904 /* If got_extra is true then we have already loaded
d2a73f8e
NC		 2905 the next word as part of loading and storing the previous word. */
2906 if (! got_extra)
2907 output_asm_insn ("ld\t%4, @%1", operands);
2908
2909 if (bytes >= 2)
2910 {
2911 bytes -= 2;
2912
0ae9f65b
DE		 2913 output_asm_insn ("sra3\t%3, %4, #16", operands);
2914 my_operands[0] = operands[3];
2915 my_operands[1] = GEN_INT (dst_offset);
2916 my_operands[2] = operands[0];
2917 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
d2a73f8e
NC		 2918
2919 /* If there is a byte left to store then increment the
2920 destination address and shift the contents of the source
0ae9f65b 2921 register down by 8 bits. We could not do the address
d2a73f8e
NC		 2922 increment in the store half word instruction, because it does
2923 not have an auto increment mode. */
2924 if (bytes > 0) /* assert (bytes == 1) */
2925 {
0ae9f65b
DE		 2926 dst_offset += 2;
2927 last_shift = 8;
d2a73f8e
NC		 2928 }
2929 }
0ae9f65b
DE		 2930 else
2931 last_shift = 24;
2932
2933 if (bytes > 0)
2934 {
2935 my_operands[0] = operands[4];
2936 my_operands[1] = GEN_INT (last_shift);
2937 output_asm_insn ("srai\t%0, #%1", my_operands);
2938 my_operands[0] = operands[4];
2939 my_operands[1] = GEN_INT (dst_offset);
2940 my_operands[2] = operands[0];
2941 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2942 }
d2a73f8e
NC		 2943
2944 bytes = 0;
2945 }
2946
2947 first_time = 0;
2948 }
d2a73f8e
NC		 2949}
2950
2951/* Return true if op is an integer constant, less than or equal to
2952 MAX_MOVE_BYTES. */
2953int
2954m32r_block_immediate_operand (op, mode)
2955 rtx op;
56e2e762 2956 enum machine_mode mode ATTRIBUTE_UNUSED;
d2a73f8e
NC		 2957{
2958 if (GET_CODE (op) != CONST_INT
2959 || INTVAL (op) > MAX_MOVE_BYTES
2960 || INTVAL (op) <= 0)
2961 return 0;
2962
2963 return 1;
2964}
a398a822
KI		 2965
2966/* Return true if using NEW_REG in place of OLD_REG is ok. */
2967
2968int
2969m32r_hard_regno_rename_ok (old_reg, new_reg)
2970 unsigned int old_reg ATTRIBUTE_UNUSED;
2971 unsigned int new_reg;
2972{
2973 /* Interrupt routines can't clobber any register that isn't already used. */
2974 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2975 && !regs_ever_live[new_reg])
2976 return 0;
2977
2978 /* We currently emit epilogues as text, not rtl, so the liveness
2979 of the return address register isn't visible. */
2980 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2981 return 0;
2982
2983 return 1;
2984}
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