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Factor unrelated declarations out of tree.h.
[thirdparty/gcc.git] / gcc / config / m32r / m32r.c
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aea2fd96 1/* Subroutines used for code generation on the Renesas M32R cpu.
711789cc 2 Copyright (C) 1996-2013 Free Software Foundation, Inc.
d868a170 3
aea2fd96 4 This file is part of GCC.
d868a170 5
aea2fd96 6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
038d1e19 8 by the Free Software Foundation; either version 3, or (at your
aea2fd96 9 option) any later version.
d868a170 10
aea2fd96 11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
d868a170 15
aea2fd96 16 You should have received a copy of the GNU General Public License
038d1e19 17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
d868a170 19
d868a170 20#include "config.h"
7dbe3569 21#include "system.h"
805e22b2 22#include "coretypes.h"
23#include "tm.h"
d868a170 24#include "tree.h"
9ed99284 25#include "stor-layout.h"
26#include "varasm.h"
27#include "stringpool.h"
28#include "calls.h"
d868a170 29#include "rtl.h"
30#include "regs.h"
31#include "hard-reg-set.h"
d868a170 32#include "insn-config.h"
33#include "conditions.h"
d868a170 34#include "output.h"
b5369b7d 35#include "dbxout.h"
d868a170 36#include "insn-attr.h"
37#include "flags.h"
38#include "expr.h"
4faf81b8 39#include "function.h"
d868a170 40#include "recog.h"
0b205f4c 41#include "diagnostic-core.h"
03033f8f 42#include "ggc.h"
ef51d1e3 43#include "df.h"
79e2a0ca 44#include "tm_p.h"
a767736d 45#include "target.h"
46#include "target-def.h"
bd9c4764 47#include "tm-constrs.h"
fba5dd52 48#include "opts.h"
d868a170 49
d868a170 50/* Array of valid operand punctuation characters. */
8e8a63d1 51static char m32r_punct_chars[256];
d868a170 52
5c5d0ae9 53/* Machine-specific symbol_ref flags. */
54#define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
55#define SYMBOL_REF_MODEL(X) \
56 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
57
58/* For string literals, etc. */
59#define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
60
868d8e32 61/* Forward declaration. */
4c834714 62static void m32r_option_override (void);
0792f2cf 63static void init_reg_tables (void);
64static void block_move_call (rtx, rtx, rtx);
65static int m32r_is_insn (rtx);
bb10104e 66static bool m32r_legitimate_address_p (enum machine_mode, rtx, bool);
41e3a0c7 67static rtx m32r_legitimize_address (rtx, rtx, enum machine_mode);
4e27ffd0 68static bool m32r_mode_dependent_address_p (const_rtx, addr_space_t);
0792f2cf 69static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
8e8a63d1 70static void m32r_print_operand (FILE *, rtx, int);
71static void m32r_print_operand_address (FILE *, rtx);
72static bool m32r_print_operand_punct_valid_p (unsigned char code);
0792f2cf 73static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
74static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
75
76static void m32r_file_start (void);
77
0792f2cf 78static int m32r_adjust_priority (rtx, int);
0792f2cf 79static int m32r_issue_rate (void);
80
81static void m32r_encode_section_info (tree, rtx, int);
a9f1838b 82static bool m32r_in_small_data_p (const_tree);
fb80456a 83static bool m32r_return_in_memory (const_tree, const_tree);
fb97ed3e 84static rtx m32r_function_value (const_tree, const_tree, bool);
85static rtx m32r_libcall_value (enum machine_mode, const_rtx);
86static bool m32r_function_value_regno_p (const unsigned int);
39cba157 87static void m32r_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
efc813ec 88 tree, int *, int);
0792f2cf 89static void init_idents (void);
20d892d1 90static bool m32r_rtx_costs (rtx, int, int, int, int *, bool speed);
5e5dc6b5 91static int m32r_memory_move_cost (enum machine_mode, reg_class_t, bool);
39cba157 92static bool m32r_pass_by_reference (cumulative_args_t, enum machine_mode,
fb80456a 93 const_tree, bool);
39cba157 94static int m32r_arg_partial_bytes (cumulative_args_t, enum machine_mode,
f054eb3c 95 tree, bool);
39cba157 96static rtx m32r_function_arg (cumulative_args_t, enum machine_mode,
1bd483c2 97 const_tree, bool);
39cba157 98static void m32r_function_arg_advance (cumulative_args_t, enum machine_mode,
1bd483c2 99 const_tree, bool);
cd90919d 100static bool m32r_can_eliminate (const int, const int);
b2d7ede1 101static void m32r_conditional_register_usage (void);
06b77609 102static void m32r_trampoline_init (rtx, tree, rtx);
ca316360 103static bool m32r_legitimate_constant_p (enum machine_mode, rtx);
a767736d 104\f
ef51d1e3 105/* M32R specific attributes. */
106
107static const struct attribute_spec m32r_attribute_table[] =
108{
ac86af5d 109 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
110 affects_type_identity } */
111 { "interrupt", 0, 0, true, false, false, NULL, false },
112 { "model", 1, 1, true, false, false, m32r_handle_model_attribute,
113 false },
114 { NULL, 0, 0, false, false, false, NULL, false }
ef51d1e3 115};
116\f
a767736d 117/* Initialize the GCC target structure. */
aea2fd96 118#undef TARGET_ATTRIBUTE_TABLE
e3c541f0 119#define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
868d8e32 120
bb10104e 121#undef TARGET_LEGITIMATE_ADDRESS_P
122#define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
41e3a0c7 123#undef TARGET_LEGITIMIZE_ADDRESS
124#define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
8c9a773b 125#undef TARGET_MODE_DEPENDENT_ADDRESS_P
126#define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
41e3a0c7 127
aea2fd96 128#undef TARGET_ASM_ALIGNED_HI_OP
58356836 129#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
aea2fd96 130#undef TARGET_ASM_ALIGNED_SI_OP
58356836 131#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
132
8e8a63d1 133#undef TARGET_PRINT_OPERAND
134#define TARGET_PRINT_OPERAND m32r_print_operand
135#undef TARGET_PRINT_OPERAND_ADDRESS
136#define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
137#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
138#define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
139
aea2fd96 140#undef TARGET_ASM_FUNCTION_PROLOGUE
17d9b0c3 141#define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
aea2fd96 142#undef TARGET_ASM_FUNCTION_EPILOGUE
17d9b0c3 143#define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
144
aea2fd96 145#undef TARGET_ASM_FILE_START
92c473b8 146#define TARGET_ASM_FILE_START m32r_file_start
147
aea2fd96 148#undef TARGET_SCHED_ADJUST_PRIORITY
747af5e7 149#define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
aea2fd96 150#undef TARGET_SCHED_ISSUE_RATE
747af5e7 151#define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
747af5e7 152
4c834714 153#undef TARGET_OPTION_OVERRIDE
154#define TARGET_OPTION_OVERRIDE m32r_option_override
d21dcfd4 155
aea2fd96 156#undef TARGET_ENCODE_SECTION_INFO
7811991d 157#define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
aea2fd96 158#undef TARGET_IN_SMALL_DATA_P
5c5d0ae9 159#define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
7811991d 160
5e5dc6b5 161
09c20b62 162#undef TARGET_MEMORY_MOVE_COST
163#define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
aea2fd96 164#undef TARGET_RTX_COSTS
fab7adbf 165#define TARGET_RTX_COSTS m32r_rtx_costs
aea2fd96 166#undef TARGET_ADDRESS_COST
d9c5e5f4 167#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
fab7adbf 168
efc813ec 169#undef TARGET_PROMOTE_PROTOTYPES
fb80456a 170#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
efc813ec 171#undef TARGET_RETURN_IN_MEMORY
172#define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
fb97ed3e 173
174#undef TARGET_FUNCTION_VALUE
175#define TARGET_FUNCTION_VALUE m32r_function_value
176#undef TARGET_LIBCALL_VALUE
177#define TARGET_LIBCALL_VALUE m32r_libcall_value
178#undef TARGET_FUNCTION_VALUE_REGNO_P
179#define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
180
efc813ec 181#undef TARGET_SETUP_INCOMING_VARARGS
182#define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
0336f0f0 183#undef TARGET_MUST_PASS_IN_STACK
184#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
b981d932 185#undef TARGET_PASS_BY_REFERENCE
186#define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
f054eb3c 187#undef TARGET_ARG_PARTIAL_BYTES
188#define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
1bd483c2 189#undef TARGET_FUNCTION_ARG
190#define TARGET_FUNCTION_ARG m32r_function_arg
191#undef TARGET_FUNCTION_ARG_ADVANCE
192#define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
0336f0f0 193
cd90919d 194#undef TARGET_CAN_ELIMINATE
195#define TARGET_CAN_ELIMINATE m32r_can_eliminate
196
b2d7ede1 197#undef TARGET_CONDITIONAL_REGISTER_USAGE
198#define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
199
06b77609 200#undef TARGET_TRAMPOLINE_INIT
201#define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
202
ca316360 203#undef TARGET_LEGITIMATE_CONSTANT_P
204#define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
205
57e4bbfb 206struct gcc_target targetm = TARGET_INITIALIZER;
a767736d 207\f
4c834714 208/* Called by m32r_option_override to initialize various things. */
d868a170 209
210void
aea2fd96 211m32r_init (void)
d868a170 212{
213 init_reg_tables ();
214
8e8a63d1 215 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
d868a170 216 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
217 m32r_punct_chars['#'] = 1;
218 m32r_punct_chars['@'] = 1; /* ??? no longer used */
219
220 /* Provide default value if not specified. */
13a54dd9 221 if (!global_options_set.x_g_switch_value)
d868a170 222 g_switch_value = SDATA_DEFAULT_SIZE;
d868a170 223}
224
4c834714 225static void
226m32r_option_override (void)
227{
228 /* These need to be done at start up.
229 It's convenient to do them here. */
230 m32r_init ();
231 SUBTARGET_OVERRIDE_OPTIONS;
232}
233
d868a170 234/* Vectors to keep interesting information about registers where it can easily
235 be got. We use to use the actual mode value as the bit number, but there
236 is (or may be) more than 32 modes now. Instead we use two tables: one
237 indexed by hard register number, and one indexed by mode. */
238
239/* The purpose of m32r_mode_class is to shrink the range of modes so that
c910419d 240 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
d868a170 241 mapped into one m32r_mode_class mode. */
242
868d8e32 243enum m32r_mode_class
244{
d868a170 245 C_MODE,
246 S_MODE, D_MODE, T_MODE, O_MODE,
947391dc 247 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
d868a170 248};
249
250/* Modes for condition codes. */
251#define C_MODES (1 << (int) C_MODE)
252
253/* Modes for single-word and smaller quantities. */
254#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
255
256/* Modes for double-word and smaller quantities. */
257#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
258
259/* Modes for quad-word and smaller quantities. */
260#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
261
947391dc 262/* Modes for accumulators. */
263#define A_MODES (1 << (int) A_MODE)
868d8e32 264
d868a170 265/* Value is 1 if register/mode pair is acceptable on arc. */
266
c8834c5f 267const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
868d8e32 268{
d868a170 269 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
270 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
6f9235e4 271 S_MODES, C_MODES, A_MODES, A_MODES
d868a170 272};
273
274unsigned int m32r_mode_class [NUM_MACHINE_MODES];
275
276enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
277
278static void
aea2fd96 279init_reg_tables (void)
d868a170 280{
281 int i;
282
283 for (i = 0; i < NUM_MACHINE_MODES; i++)
284 {
285 switch (GET_MODE_CLASS (i))
286 {
287 case MODE_INT:
288 case MODE_PARTIAL_INT:
289 case MODE_COMPLEX_INT:
290 if (GET_MODE_SIZE (i) <= 4)
291 m32r_mode_class[i] = 1 << (int) S_MODE;
292 else if (GET_MODE_SIZE (i) == 8)
293 m32r_mode_class[i] = 1 << (int) D_MODE;
294 else if (GET_MODE_SIZE (i) == 16)
295 m32r_mode_class[i] = 1 << (int) T_MODE;
296 else if (GET_MODE_SIZE (i) == 32)
297 m32r_mode_class[i] = 1 << (int) O_MODE;
58f4ce52 298 else
d868a170 299 m32r_mode_class[i] = 0;
300 break;
301 case MODE_FLOAT:
302 case MODE_COMPLEX_FLOAT:
303 if (GET_MODE_SIZE (i) <= 4)
304 m32r_mode_class[i] = 1 << (int) SF_MODE;
305 else if (GET_MODE_SIZE (i) == 8)
306 m32r_mode_class[i] = 1 << (int) DF_MODE;
307 else if (GET_MODE_SIZE (i) == 16)
308 m32r_mode_class[i] = 1 << (int) TF_MODE;
309 else if (GET_MODE_SIZE (i) == 32)
310 m32r_mode_class[i] = 1 << (int) OF_MODE;
58f4ce52 311 else
d868a170 312 m32r_mode_class[i] = 0;
313 break;
314 case MODE_CC:
15460c97 315 m32r_mode_class[i] = 1 << (int) C_MODE;
316 break;
d868a170 317 default:
15460c97 318 m32r_mode_class[i] = 0;
d868a170 319 break;
320 }
321 }
322
323 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
324 {
325 if (GPR_P (i))
326 m32r_regno_reg_class[i] = GENERAL_REGS;
327 else if (i == ARG_POINTER_REGNUM)
328 m32r_regno_reg_class[i] = GENERAL_REGS;
329 else
330 m32r_regno_reg_class[i] = NO_REGS;
331 }
332}
333\f
334/* M32R specific attribute support.
335
336 interrupt - for interrupt functions
337
338 model - select code model used to access object
339
340 small: addresses use 24 bits, use bl to make calls
341 medium: addresses use 32 bits, use bl to make calls
342 large: addresses use 32 bits, use seth/add3/jl to make calls
343
aea2fd96 344 Grep for MODEL in m32r.h for more info. */
d868a170 345
d7f038f8 346static tree small_ident1;
347static tree small_ident2;
348static tree medium_ident1;
349static tree medium_ident2;
350static tree large_ident1;
351static tree large_ident2;
352
353static void
aea2fd96 354init_idents (void)
d7f038f8 355{
e3c541f0 356 if (small_ident1 == 0)
d7f038f8 357 {
d7f038f8 358 small_ident1 = get_identifier ("small");
359 small_ident2 = get_identifier ("__small__");
360 medium_ident1 = get_identifier ("medium");
361 medium_ident2 = get_identifier ("__medium__");
362 large_ident1 = get_identifier ("large");
363 large_ident2 = get_identifier ("__large__");
364 }
365}
366
e3c541f0 367/* Handle an "model" attribute; arguments as in
368 struct attribute_spec.handler. */
369static tree
aea2fd96 370m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
371 tree args, int flags ATTRIBUTE_UNUSED,
372 bool *no_add_attrs)
d868a170 373{
e3c541f0 374 tree arg;
d868a170 375
e3c541f0 376 init_idents ();
377 arg = TREE_VALUE (args);
378
379 if (arg != small_ident1
380 && arg != small_ident2
381 && arg != medium_ident1
382 && arg != medium_ident2
383 && arg != large_ident1
384 && arg != large_ident2)
385 {
9b2d6d13 386 warning (OPT_Wattributes, "invalid argument of %qs attribute",
e3c541f0 387 IDENTIFIER_POINTER (name));
388 *no_add_attrs = true;
389 }
d868a170 390
e3c541f0 391 return NULL_TREE;
d868a170 392}
d868a170 393\f
d868a170 394/* Encode section information of DECL, which is either a VAR_DECL,
395 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
396
397 For the M32R we want to record:
398
399 - whether the object lives in .sdata/.sbss.
d868a170 400 - what code model should be used to access the object
d868a170 401*/
402
7811991d 403static void
aea2fd96 404m32r_encode_section_info (tree decl, rtx rtl, int first)
d868a170 405{
5c5d0ae9 406 int extra_flags = 0;
407 tree model_attr;
408 enum m32r_model model;
d868a170 409
2c129d70 410 default_encode_section_info (decl, rtl, first);
5c5d0ae9 411
412 if (!DECL_P (decl))
41eb471c 413 return;
414
5c5d0ae9 415 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
416 if (model_attr)
d868a170 417 {
5c5d0ae9 418 tree id;
d868a170 419
5c5d0ae9 420 init_idents ();
d868a170 421
5c5d0ae9 422 id = TREE_VALUE (TREE_VALUE (model_attr));
d868a170 423
5c5d0ae9 424 if (id == small_ident1 || id == small_ident2)
425 model = M32R_MODEL_SMALL;
426 else if (id == medium_ident1 || id == medium_ident2)
427 model = M32R_MODEL_MEDIUM;
428 else if (id == large_ident1 || id == large_ident2)
429 model = M32R_MODEL_LARGE;
430 else
7afac3c3 431 gcc_unreachable (); /* shouldn't happen */
5c5d0ae9 432 }
433 else
d868a170 434 {
5c5d0ae9 435 if (TARGET_MODEL_SMALL)
436 model = M32R_MODEL_SMALL;
437 else if (TARGET_MODEL_MEDIUM)
438 model = M32R_MODEL_MEDIUM;
439 else if (TARGET_MODEL_LARGE)
440 model = M32R_MODEL_LARGE;
d868a170 441 else
7afac3c3 442 gcc_unreachable (); /* shouldn't happen */
d868a170 443 }
5c5d0ae9 444 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
d868a170 445
5c5d0ae9 446 if (extra_flags)
2c129d70 447 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5c5d0ae9 448}
d7f038f8 449
5c5d0ae9 450/* Only mark the object as being small data area addressable if
451 it hasn't been explicitly marked with a code model.
d7f038f8 452
5c5d0ae9 453 The user can explicitly put an object in the small data area with the
454 section attribute. If the object is in sdata/sbss and marked with a
455 code model do both [put the object in .sdata and mark it as being
456 addressed with a specific code model - don't mark it as being addressed
457 with an SDA reloc though]. This is ok and might be useful at times. If
458 the object doesn't fit the linker will give an error. */
d868a170 459
5c5d0ae9 460static bool
a9f1838b 461m32r_in_small_data_p (const_tree decl)
5c5d0ae9 462{
a9f1838b 463 const_tree section;
5c5d0ae9 464
465 if (TREE_CODE (decl) != VAR_DECL)
466 return false;
467
468 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
469 return false;
470
471 section = DECL_SECTION_NAME (decl);
472 if (section)
d868a170 473 {
fb80456a 474 const char *const name = TREE_STRING_POINTER (section);
5c5d0ae9 475 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
476 return true;
d868a170 477 }
5c5d0ae9 478 else
479 {
480 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
481 {
482 int size = int_size_in_bytes (TREE_TYPE (decl));
d868a170 483
13a54dd9 484 if (size > 0 && size <= g_switch_value)
5c5d0ae9 485 return true;
486 }
487 }
7b4a38a6 488
5c5d0ae9 489 return false;
7b4a38a6 490}
491
d868a170 492/* Do anything needed before RTL is emitted for each function. */
493
494void
aea2fd96 495m32r_init_expanders (void)
d868a170 496{
497 /* ??? At one point there was code here. The function is left in
498 to make it easy to experiment. */
499}
500\f
d868a170 501int
aea2fd96 502call_operand (rtx op, enum machine_mode mode)
d868a170 503{
452bfb8b 504 if (!MEM_P (op))
d868a170 505 return 0;
506 op = XEXP (op, 0);
507 return call_address_operand (op, mode);
508}
509
d868a170 510/* Return 1 if OP is a reference to an object in .sdata/.sbss. */
511
512int
aea2fd96 513small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 514{
515 if (! TARGET_SDATA_USE)
516 return 0;
517
518 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 519 return SYMBOL_REF_SMALL_P (op);
d868a170 520
521 if (GET_CODE (op) == CONST
522 && GET_CODE (XEXP (op, 0)) == PLUS
523 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
bd9c4764 524 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
5c5d0ae9 525 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
d868a170 526
527 return 0;
528}
529
c910419d 530/* Return 1 if OP is a symbol that can use 24-bit addressing. */
d868a170 531
532int
aea2fd96 533addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 534{
5c5d0ae9 535 rtx sym;
536
467dc9aa 537 if (flag_pic)
538 return 0;
539
d868a170 540 if (GET_CODE (op) == LABEL_REF)
541 return TARGET_ADDR24;
542
543 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 544 sym = op;
545 else if (GET_CODE (op) == CONST
546 && GET_CODE (XEXP (op, 0)) == PLUS
547 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
bd9c4764 548 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
5c5d0ae9 549 sym = XEXP (XEXP (op, 0), 0);
550 else
551 return 0;
d868a170 552
5c5d0ae9 553 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
554 return 1;
555
556 if (TARGET_ADDR24
557 && (CONSTANT_POOL_ADDRESS_P (sym)
558 || LIT_NAME_P (XSTR (sym, 0))))
559 return 1;
d868a170 560
561 return 0;
562}
563
c910419d 564/* Return 1 if OP is a symbol that needs 32-bit addressing. */
d868a170 565
566int
aea2fd96 567addr32_operand (rtx op, enum machine_mode mode)
d868a170 568{
5c5d0ae9 569 rtx sym;
570
d868a170 571 if (GET_CODE (op) == LABEL_REF)
572 return TARGET_ADDR32;
573
574 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 575 sym = op;
576 else if (GET_CODE (op) == CONST
577 && GET_CODE (XEXP (op, 0)) == PLUS
578 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
452bfb8b 579 && CONST_INT_P (XEXP (XEXP (op, 0), 1))
467dc9aa 580 && ! flag_pic)
5c5d0ae9 581 sym = XEXP (XEXP (op, 0), 0);
582 else
583 return 0;
d868a170 584
5c5d0ae9 585 return (! addr24_operand (sym, mode)
586 && ! small_data_operand (sym, mode));
d868a170 587}
588
589/* Return 1 if OP is a function that can be called with the `bl' insn. */
590
591int
aea2fd96 592call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 593{
467dc9aa 594 if (flag_pic)
843505b2 595 return 1;
467dc9aa 596
d868a170 597 if (GET_CODE (op) == SYMBOL_REF)
5c5d0ae9 598 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
d868a170 599
600 return TARGET_CALL26;
601}
602
d868a170 603/* Return 1 if OP is a DImode const we want to handle inline.
604 This must match the code in the movdi pattern.
605 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
606
607int
aea2fd96 608easy_di_const (rtx op)
d868a170 609{
610 rtx high_rtx, low_rtx;
611 HOST_WIDE_INT high, low;
612
613 split_double (op, &high_rtx, &low_rtx);
614 high = INTVAL (high_rtx);
615 low = INTVAL (low_rtx);
c910419d 616 /* Pick constants loadable with 2 16-bit `ldi' insns. */
d868a170 617 if (high >= -128 && high <= 127
618 && low >= -128 && low <= 127)
619 return 1;
620 return 0;
621}
622
623/* Return 1 if OP is a DFmode const we want to handle inline.
624 This must match the code in the movdf pattern.
625 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
626
627int
aea2fd96 628easy_df_const (rtx op)
d868a170 629{
630 REAL_VALUE_TYPE r;
631 long l[2];
632
633 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
634 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
635 if (l[0] == 0 && l[1] == 0)
636 return 1;
637 if ((l[0] & 0xffff) == 0 && l[1] == 0)
638 return 1;
639 return 0;
640}
641
d868a170 642/* Return 1 if OP is (mem (reg ...)).
643 This is used in insn length calcs. */
644
645int
aea2fd96 646memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d868a170 647{
be96c8c6 648 return MEM_P (op) && REG_P (XEXP (op, 0));
d868a170 649}
868d8e32 650
b981d932 651/* Return nonzero if TYPE must be passed by indirect reference. */
daece349 652
b981d932 653static bool
39cba157 654m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
fb80456a 655 enum machine_mode mode, const_tree type,
b981d932 656 bool named ATTRIBUTE_UNUSED)
daece349 657{
b981d932 658 int size;
daece349 659
b981d932 660 if (type)
661 size = int_size_in_bytes (type);
662 else
663 size = GET_MODE_SIZE (mode);
daece349 664
b981d932 665 return (size < 0 || size > 8);
daece349 666}
d868a170 667\f
668/* Comparisons. */
669
d868a170 670/* X and Y are two things to compare using CODE. Emit the compare insn and
868d8e32 671 return the rtx for compare [arg0 of the if_then_else].
672 If need_compare is true then the comparison insn must be generated, rather
dfd1079d 673 than being subsumed into the following branch instruction. */
d868a170 674
675rtx
aea2fd96 676gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
d868a170 677{
aea2fd96 678 enum rtx_code compare_code;
679 enum rtx_code branch_code;
60a061f2 680 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
6441a98f 681 int must_swap = 0;
d868a170 682
683 switch (code)
684 {
8ec9afef 685 case EQ: compare_code = EQ; branch_code = NE; break;
686 case NE: compare_code = EQ; branch_code = EQ; break;
687 case LT: compare_code = LT; branch_code = NE; break;
688 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
689 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
690 case GE: compare_code = LT; branch_code = EQ; break;
d868a170 691 case LTU: compare_code = LTU; branch_code = NE; break;
8ec9afef 692 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
693 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
d868a170 694 case GEU: compare_code = LTU; branch_code = EQ; break;
6441a98f 695
696 default:
7afac3c3 697 gcc_unreachable ();
d868a170 698 }
699
868d8e32 700 if (need_compare)
701 {
702 switch (compare_code)
703 {
704 case EQ:
bd9c4764 705 if (satisfies_constraint_P (y) /* Reg equal to small const. */
868d8e32 706 && y != const0_rtx)
707 {
58f4ce52 708 rtx tmp = gen_reg_rtx (SImode);
709
467cdcb9 710 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
868d8e32 711 x = tmp;
712 y = const0_rtx;
713 }
aea2fd96 714 else if (CONSTANT_P (y)) /* Reg equal to const. */
868d8e32 715 {
716 rtx tmp = force_reg (GET_MODE (x), y);
717 y = tmp;
718 }
719
aea2fd96 720 if (register_operand (y, SImode) /* Reg equal to reg. */
721 || y == const0_rtx) /* Reg equal to zero. */
868d8e32 722 {
947391dc 723 emit_insn (gen_cmp_eqsi_insn (x, y));
58f4ce52 724
29bb088d 725 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
868d8e32 726 }
727 break;
58f4ce52 728
868d8e32 729 case LT:
730 if (register_operand (y, SImode)
bd9c4764 731 || satisfies_constraint_P (y))
868d8e32 732 {
aea2fd96 733 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
58f4ce52 734
868d8e32 735 switch (code)
736 {
737 case LT:
738 emit_insn (gen_cmp_ltsi_insn (x, y));
739 code = EQ;
740 break;
741 case LE:
742 if (y == const0_rtx)
743 tmp = const1_rtx;
744 else
467cdcb9 745 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 746 emit_insn (gen_cmp_ltsi_insn (x, tmp));
747 code = EQ;
748 break;
749 case GT:
452bfb8b 750 if (CONST_INT_P (y))
1a83b3ff 751 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
868d8e32 752 else
467cdcb9 753 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 754 emit_insn (gen_cmp_ltsi_insn (x, tmp));
755 code = NE;
756 break;
757 case GE:
758 emit_insn (gen_cmp_ltsi_insn (x, y));
759 code = NE;
760 break;
761 default:
7afac3c3 762 gcc_unreachable ();
868d8e32 763 }
58f4ce52 764
29bb088d 765 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
868d8e32 766 }
767 break;
58f4ce52 768
868d8e32 769 case LTU:
770 if (register_operand (y, SImode)
bd9c4764 771 || satisfies_constraint_P (y))
868d8e32 772 {
aea2fd96 773 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
58f4ce52 774
868d8e32 775 switch (code)
776 {
777 case LTU:
778 emit_insn (gen_cmp_ltusi_insn (x, y));
779 code = EQ;
780 break;
781 case LEU:
782 if (y == const0_rtx)
783 tmp = const1_rtx;
784 else
467cdcb9 785 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 786 emit_insn (gen_cmp_ltusi_insn (x, tmp));
787 code = EQ;
788 break;
789 case GTU:
452bfb8b 790 if (CONST_INT_P (y))
1a83b3ff 791 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
868d8e32 792 else
467cdcb9 793 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
868d8e32 794 emit_insn (gen_cmp_ltusi_insn (x, tmp));
795 code = NE;
796 break;
797 case GEU:
798 emit_insn (gen_cmp_ltusi_insn (x, y));
799 code = NE;
800 break;
801 default:
7afac3c3 802 gcc_unreachable ();
868d8e32 803 }
58f4ce52 804
29bb088d 805 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
868d8e32 806 }
807 break;
808
809 default:
7afac3c3 810 gcc_unreachable ();
868d8e32 811 }
812 }
813 else
d868a170 814 {
aea2fd96 815 /* Reg/reg equal comparison. */
d868a170 816 if (compare_code == EQ
817 && register_operand (y, SImode))
29bb088d 818 return gen_rtx_fmt_ee (code, CCmode, x, y);
58f4ce52 819
aea2fd96 820 /* Reg/zero signed comparison. */
d868a170 821 if ((compare_code == EQ || compare_code == LT)
822 && y == const0_rtx)
29bb088d 823 return gen_rtx_fmt_ee (code, CCmode, x, y);
58f4ce52 824
aea2fd96 825 /* Reg/smallconst equal comparison. */
d868a170 826 if (compare_code == EQ
bd9c4764 827 && satisfies_constraint_P (y))
d868a170 828 {
829 rtx tmp = gen_reg_rtx (SImode);
aea2fd96 830
467cdcb9 831 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
29bb088d 832 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
d868a170 833 }
58f4ce52 834
aea2fd96 835 /* Reg/const equal comparison. */
d868a170 836 if (compare_code == EQ
837 && CONSTANT_P (y))
838 {
839 rtx tmp = force_reg (GET_MODE (x), y);
aea2fd96 840
29bb088d 841 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
d868a170 842 }
843 }
844
8ec9afef 845 if (CONSTANT_P (y))
d868a170 846 {
8ec9afef 847 if (must_swap)
d868a170 848 y = force_reg (GET_MODE (x), y);
8ec9afef 849 else
850 {
4c6c8621 851 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
852
8ec9afef 853 if (! ok_const)
854 y = force_reg (GET_MODE (x), y);
855 }
d868a170 856 }
857
858 switch (compare_code)
859 {
860 case EQ :
8ec9afef 861 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
d868a170 862 break;
863 case LT :
8ec9afef 864 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
d868a170 865 break;
866 case LTU :
8ec9afef 867 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
d868a170 868 break;
6441a98f 869
870 default:
7afac3c3 871 gcc_unreachable ();
d868a170 872 }
873
29bb088d 874 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
d868a170 875}
74f4459c 876
877bool
878gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
879{
880 enum machine_mode mode = GET_MODE (op0);
881
882 gcc_assert (mode == SImode);
883 switch (code)
884 {
885 case EQ:
886 if (!register_operand (op1, mode))
887 op1 = force_reg (mode, op1);
888
889 if (TARGET_M32RX || TARGET_M32R2)
890 {
891 if (!reg_or_zero_operand (op2, mode))
892 op2 = force_reg (mode, op2);
893
894 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
895 return true;
896 }
452bfb8b 897 if (CONST_INT_P (op2) && INTVAL (op2) == 0)
74f4459c 898 {
899 emit_insn (gen_seq_zero_insn (op0, op1));
900 return true;
901 }
902
903 if (!reg_or_eq_int16_operand (op2, mode))
904 op2 = force_reg (mode, op2);
905
906 emit_insn (gen_seq_insn (op0, op1, op2));
907 return true;
908
909 case NE:
452bfb8b 910 if (!CONST_INT_P (op2)
74f4459c 911 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
912 {
913 rtx reg;
914
915 if (reload_completed || reload_in_progress)
916 return false;
917
918 reg = gen_reg_rtx (SImode);
919 emit_insn (gen_xorsi3 (reg, op1, op2));
920 op1 = reg;
921
922 if (!register_operand (op1, mode))
923 op1 = force_reg (mode, op1);
924
925 emit_insn (gen_sne_zero_insn (op0, op1));
926 return true;
927 }
928 return false;
929
930 case LT:
931 case GT:
932 if (code == GT)
933 {
934 rtx tmp = op2;
935 op2 = op1;
936 op1 = tmp;
937 code = LT;
938 }
939
940 if (!register_operand (op1, mode))
941 op1 = force_reg (mode, op1);
942
943 if (!reg_or_int16_operand (op2, mode))
944 op2 = force_reg (mode, op2);
945
946 emit_insn (gen_slt_insn (op0, op1, op2));
947 return true;
948
949 case LTU:
950 case GTU:
951 if (code == GTU)
952 {
953 rtx tmp = op2;
954 op2 = op1;
955 op1 = tmp;
956 code = LTU;
957 }
958
959 if (!register_operand (op1, mode))
960 op1 = force_reg (mode, op1);
961
962 if (!reg_or_int16_operand (op2, mode))
963 op2 = force_reg (mode, op2);
964
965 emit_insn (gen_sltu_insn (op0, op1, op2));
966 return true;
967
968 case GE:
969 case GEU:
970 if (!register_operand (op1, mode))
971 op1 = force_reg (mode, op1);
972
973 if (!reg_or_int16_operand (op2, mode))
974 op2 = force_reg (mode, op2);
975
976 if (code == GE)
977 emit_insn (gen_sge_insn (op0, op1, op2));
978 else
979 emit_insn (gen_sgeu_insn (op0, op1, op2));
980 return true;
981
982 case LE:
983 case LEU:
984 if (!register_operand (op1, mode))
985 op1 = force_reg (mode, op1);
986
452bfb8b 987 if (CONST_INT_P (op2))
74f4459c 988 {
989 HOST_WIDE_INT value = INTVAL (op2);
990 if (value >= 2147483647)
991 {
992 emit_move_insn (op0, const1_rtx);
993 return true;
994 }
995
996 op2 = GEN_INT (value + 1);
997 if (value < -32768 || value >= 32767)
998 op2 = force_reg (mode, op2);
999
1000 if (code == LEU)
1001 emit_insn (gen_sltu_insn (op0, op1, op2));
1002 else
1003 emit_insn (gen_slt_insn (op0, op1, op2));
1004 return true;
1005 }
1006
1007 if (!register_operand (op2, mode))
1008 op2 = force_reg (mode, op2);
1009
1010 if (code == LEU)
1011 emit_insn (gen_sleu_insn (op0, op1, op2));
1012 else
1013 emit_insn (gen_sle_insn (op0, op1, op2));
1014 return true;
1015
1016 default:
1017 gcc_unreachable ();
1018 }
1019}
1020
7dbe3569 1021\f
1022/* Split a 2 word move (DI or DF) into component parts. */
1023
1024rtx
aea2fd96 1025gen_split_move_double (rtx operands[])
7dbe3569 1026{
1027 enum machine_mode mode = GET_MODE (operands[0]);
1028 rtx dest = operands[0];
1029 rtx src = operands[1];
1030 rtx val;
1031
df5991ff 1032 /* We might have (SUBREG (MEM)) here, so just get rid of the
1033 subregs to make this code simpler. It is safe to call
1034 alter_subreg any time after reload. */
1035 if (GET_CODE (dest) == SUBREG)
c6a6cdaa 1036 alter_subreg (&dest, true);
df5991ff 1037 if (GET_CODE (src) == SUBREG)
c6a6cdaa 1038 alter_subreg (&src, true);
df5991ff 1039
7dbe3569 1040 start_sequence ();
452bfb8b 1041 if (REG_P (dest))
7dbe3569 1042 {
df5991ff 1043 int dregno = REGNO (dest);
1044
aea2fd96 1045 /* Reg = reg. */
452bfb8b 1046 if (REG_P (src))
7dbe3569 1047 {
df5991ff 1048 int sregno = REGNO (src);
1049
1050 int reverse = (dregno == sregno + 1);
1051
7dbe3569 1052 /* We normally copy the low-numbered register first. However, if
1053 the first register operand 0 is the same as the second register of
1054 operand 1, we must copy in the opposite order. */
7dbe3569 1055 emit_insn (gen_rtx_SET (VOIDmode,
1056 operand_subword (dest, reverse, TRUE, mode),
1057 operand_subword (src, reverse, TRUE, mode)));
1058
1059 emit_insn (gen_rtx_SET (VOIDmode,
1060 operand_subword (dest, !reverse, TRUE, mode),
1061 operand_subword (src, !reverse, TRUE, mode)));
1062 }
1063
aea2fd96 1064 /* Reg = constant. */
452bfb8b 1065 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
7dbe3569 1066 {
1067 rtx words[2];
1068 split_double (src, &words[0], &words[1]);
1069 emit_insn (gen_rtx_SET (VOIDmode,
1070 operand_subword (dest, 0, TRUE, mode),
1071 words[0]));
1072
1073 emit_insn (gen_rtx_SET (VOIDmode,
1074 operand_subword (dest, 1, TRUE, mode),
1075 words[1]));
1076 }
1077
aea2fd96 1078 /* Reg = mem. */
452bfb8b 1079 else if (MEM_P (src))
7dbe3569 1080 {
1081 /* If the high-address word is used in the address, we must load it
1082 last. Otherwise, load it first. */
e513d163 1083 int reverse
1084 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
7dbe3569 1085
1086 /* We used to optimize loads from single registers as
1087
1088 ld r1,r3+; ld r2,r3
1089
1090 if r3 were not used subsequently. However, the REG_NOTES aren't
dfd1079d 1091 propagated correctly by the reload phase, and it can cause bad
7dbe3569 1092 code to be generated. We could still try:
1093
1094 ld r1,r3+; ld r2,r3; addi r3,-4
1095
1096 which saves 2 bytes and doesn't force longword alignment. */
1097 emit_insn (gen_rtx_SET (VOIDmode,
1098 operand_subword (dest, reverse, TRUE, mode),
e513d163 1099 adjust_address (src, SImode,
1100 reverse * UNITS_PER_WORD)));
7dbe3569 1101
1102 emit_insn (gen_rtx_SET (VOIDmode,
1103 operand_subword (dest, !reverse, TRUE, mode),
e513d163 1104 adjust_address (src, SImode,
1105 !reverse * UNITS_PER_WORD)));
7dbe3569 1106 }
7dbe3569 1107 else
7afac3c3 1108 gcc_unreachable ();
7dbe3569 1109 }
1110
aea2fd96 1111 /* Mem = reg. */
7dbe3569 1112 /* We used to optimize loads from single registers as
1113
1114 st r1,r3; st r2,+r3
1115
1116 if r3 were not used subsequently. However, the REG_NOTES aren't
dfd1079d 1117 propagated correctly by the reload phase, and it can cause bad
7dbe3569 1118 code to be generated. We could still try:
1119
1120 st r1,r3; st r2,+r3; addi r3,-4
1121
1122 which saves 2 bytes and doesn't force longword alignment. */
be96c8c6 1123 else if (MEM_P (dest) && REG_P (src))
7dbe3569 1124 {
7dbe3569 1125 emit_insn (gen_rtx_SET (VOIDmode,
e513d163 1126 adjust_address (dest, SImode, 0),
7dbe3569 1127 operand_subword (src, 0, TRUE, mode)));
1128
1129 emit_insn (gen_rtx_SET (VOIDmode,
e513d163 1130 adjust_address (dest, SImode, UNITS_PER_WORD),
7dbe3569 1131 operand_subword (src, 1, TRUE, mode)));
1132 }
1133
1134 else
7afac3c3 1135 gcc_unreachable ();
7dbe3569 1136
31d3e01c 1137 val = get_insns ();
7dbe3569 1138 end_sequence ();
1139 return val;
1140}
1141
d868a170 1142\f
f054eb3c 1143static int
39cba157 1144m32r_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
f054eb3c 1145 tree type, bool named ATTRIBUTE_UNUSED)
d868a170 1146{
39cba157 1147 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1148
f054eb3c 1149 int words;
03033f8f 1150 unsigned int size =
1151 (((mode == BLKmode && type)
1152 ? (unsigned int) int_size_in_bytes (type)
1153 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1154 / UNITS_PER_WORD;
d868a170 1155
1156 if (*cum >= M32R_MAX_PARM_REGS)
f054eb3c 1157 words = 0;
d868a170 1158 else if (*cum + size > M32R_MAX_PARM_REGS)
f054eb3c 1159 words = (*cum + size) - M32R_MAX_PARM_REGS;
d868a170 1160 else
f054eb3c 1161 words = 0;
d868a170 1162
f054eb3c 1163 return words * UNITS_PER_WORD;
d868a170 1164}
1165
1bd483c2 1166/* The ROUND_ADVANCE* macros are local to this file. */
1167/* Round SIZE up to a word boundary. */
1168#define ROUND_ADVANCE(SIZE) \
1169 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1170
1171/* Round arg MODE/TYPE up to the next word boundary. */
1172#define ROUND_ADVANCE_ARG(MODE, TYPE) \
1173 ((MODE) == BLKmode \
1174 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1175 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1176
1177/* Round CUM up to the necessary point for argument MODE/TYPE. */
1178#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1179
1180/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1181 a reg. This includes arguments that have to be passed by reference as the
1182 pointer to them is passed in a reg if one is available (and that is what
1183 we're given).
1184 This macro is only used in this file. */
1185#define PASS_IN_REG_P(CUM, MODE, TYPE) \
1186 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1187
1188/* Determine where to put an argument to a function.
1189 Value is zero to push the argument on the stack,
1190 or a hard register in which to store the argument.
1191
1192 MODE is the argument's machine mode.
1193 TYPE is the data type of the argument (as a tree).
1194 This is null for libcalls where that information may
1195 not be available.
1196 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1197 the preceding args and about the function being called.
1198 NAMED is nonzero if this argument is a named parameter
1199 (otherwise it is an extra parameter matching an ellipsis). */
1200/* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1201 and the rest are pushed. */
1202
1203static rtx
39cba157 1204m32r_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
09c20b62 1205 const_tree type ATTRIBUTE_UNUSED,
1206 bool named ATTRIBUTE_UNUSED)
1bd483c2 1207{
39cba157 1208 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1209
1bd483c2 1210 return (PASS_IN_REG_P (*cum, mode, type)
1211 ? gen_rtx_REG (mode, ROUND_ADVANCE_CUM (*cum, mode, type))
1212 : NULL_RTX);
1213}
1214
1215/* Update the data in CUM to advance over an argument
1216 of mode MODE and data type TYPE.
1217 (TYPE is null for libcalls where that information may not be available.) */
1218
1219static void
39cba157 1220m32r_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1bd483c2 1221 const_tree type, bool named ATTRIBUTE_UNUSED)
1222{
39cba157 1223 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1224
1bd483c2 1225 *cum = (ROUND_ADVANCE_CUM (*cum, mode, type)
1226 + ROUND_ADVANCE_ARG (mode, type));
1227}
1228
efc813ec 1229/* Worker function for TARGET_RETURN_IN_MEMORY. */
1230
1231static bool
fb80456a 1232m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
efc813ec 1233{
39cba157 1234 cumulative_args_t dummy = pack_cumulative_args (NULL);
1235
1236 return m32r_pass_by_reference (dummy, TYPE_MODE (type), type, false);
efc813ec 1237}
1238
fb97ed3e 1239/* Worker function for TARGET_FUNCTION_VALUE. */
1240
1241static rtx
1242m32r_function_value (const_tree valtype,
1243 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1244 bool outgoing ATTRIBUTE_UNUSED)
1245{
1246 return gen_rtx_REG (TYPE_MODE (valtype), 0);
1247}
1248
1249/* Worker function for TARGET_LIBCALL_VALUE. */
1250
1251static rtx
1252m32r_libcall_value (enum machine_mode mode,
1253 const_rtx fun ATTRIBUTE_UNUSED)
1254{
1255 return gen_rtx_REG (mode, 0);
1256}
1257
1258/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1259
1260 ??? What about r1 in DI/DF values. */
1261
1262static bool
1263m32r_function_value_regno_p (const unsigned int regno)
1264{
1265 return (regno == 0);
1266}
1267
d868a170 1268/* Do any needed setup for a variadic function. For the M32R, we must
1269 create a register parameter block, and then copy any anonymous arguments
1270 in registers to memory.
1271
1272 CUM has not been updated for the last named argument which has type TYPE
1273 and mode MODE, and we rely on this fact. */
1274
efc813ec 1275static void
39cba157 1276m32r_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
aea2fd96 1277 tree type, int *pretend_size, int no_rtl)
d868a170 1278{
1279 int first_anon_arg;
1280
1281 if (no_rtl)
1282 return;
1283
1284 /* All BLKmode values are passed by reference. */
7afac3c3 1285 gcc_assert (mode != BLKmode);
d868a170 1286
39cba157 1287 first_anon_arg = (ROUND_ADVANCE_CUM (*get_cumulative_args (cum), mode, type)
7ccc713a 1288 + ROUND_ADVANCE_ARG (mode, type));
d868a170 1289
1290 if (first_anon_arg < M32R_MAX_PARM_REGS)
1291 {
1292 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1293 int first_reg_offset = first_anon_arg;
1294 /* Size in words to "pretend" allocate. */
1295 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1296 rtx regblock;
1297
58f4ce52 1298 regblock = gen_frame_mem (BLKmode,
29c05e22 1299 plus_constant (Pmode, arg_pointer_rtx,
58f4ce52 1300 FIRST_PARM_OFFSET (0)));
ab6ab77e 1301 set_mem_alias_set (regblock, get_varargs_alias_set ());
530178a9 1302 move_block_from_reg (first_reg_offset, regblock, size);
d868a170 1303
1304 *pretend_size = (size * UNITS_PER_WORD);
1305 }
1306}
acfbd054 1307
947391dc 1308\f
4a655456 1309/* Return true if INSN is real instruction bearing insn. */
947391dc 1310
4a655456 1311static int
aea2fd96 1312m32r_is_insn (rtx insn)
4a655456 1313{
f5417e32 1314 return (NONDEBUG_INSN_P (insn)
4a655456 1315 && GET_CODE (PATTERN (insn)) != USE
77985f1a 1316 && GET_CODE (PATTERN (insn)) != CLOBBER);
4a655456 1317}
1318
1319/* Increase the priority of long instructions so that the
1320 short instructions are scheduled ahead of the long ones. */
947391dc 1321
747af5e7 1322static int
aea2fd96 1323m32r_adjust_priority (rtx insn, int priority)
947391dc 1324{
4a655456 1325 if (m32r_is_insn (insn)
1326 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1327 priority <<= 3;
947391dc 1328
1329 return priority;
1330}
1331
1332\f
747af5e7 1333/* Indicate how many instructions can be issued at the same time.
1334 This is sort of a lie. The m32r can issue only 1 long insn at
1335 once, but it can issue 2 short insns. The default therefore is
1336 set at 2, but this can be overridden by the command line option
aea2fd96 1337 -missue-rate=1. */
1338
747af5e7 1339static int
aea2fd96 1340m32r_issue_rate (void)
747af5e7 1341{
1342 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
947391dc 1343}
947391dc 1344\f
d868a170 1345/* Cost functions. */
218e3e4e 1346/* Memory is 3 times as expensive as registers.
5e5dc6b5 1347 ??? Is that the right way to look at it? */
1348
1349static int
1350m32r_memory_move_cost (enum machine_mode mode,
1351 reg_class_t rclass ATTRIBUTE_UNUSED,
1352 bool in ATTRIBUTE_UNUSED)
1353{
1354 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
1355 return 6;
1356 else
1357 return 12;
1358}
1359
fab7adbf 1360static bool
20d892d1 1361m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
1362 int opno ATTRIBUTE_UNUSED, int *total,
f529eb25 1363 bool speed ATTRIBUTE_UNUSED)
fab7adbf 1364{
1365 switch (code)
1366 {
1367 /* Small integers are as cheap as registers. 4 byte values can be
1368 fetched as immediate constants - let's give that the cost of an
1369 extra insn. */
1370 case CONST_INT:
1371 if (INT16_P (INTVAL (x)))
1372 {
1373 *total = 0;
1374 return true;
1375 }
8e262b5e 1376 /* FALLTHRU */
fab7adbf 1377
1378 case CONST:
1379 case LABEL_REF:
1380 case SYMBOL_REF:
1381 *total = COSTS_N_INSNS (1);
1382 return true;
1383
1384 case CONST_DOUBLE:
1385 {
1386 rtx high, low;
aea2fd96 1387
fab7adbf 1388 split_double (x, &high, &low);
1389 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1390 + !INT16_P (INTVAL (low)));
1391 return true;
1392 }
1393
1394 case MULT:
1395 *total = COSTS_N_INSNS (3);
1396 return true;
1397
1398 case DIV:
1399 case UDIV:
1400 case MOD:
1401 case UMOD:
1402 *total = COSTS_N_INSNS (10);
1403 return true;
1404
1405 default:
1406 return false;
1407 }
1408}
d868a170 1409\f
1410/* Type of function DECL.
1411
1412 The result is cached. To reset the cache at the end of a function,
1413 call with DECL = NULL_TREE. */
1414
1415enum m32r_function_type
aea2fd96 1416m32r_compute_function_type (tree decl)
d868a170 1417{
1418 /* Cached value. */
1419 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1420 /* Last function we were called for. */
1421 static tree last_fn = NULL_TREE;
1422
1423 /* Resetting the cached value? */
1424 if (decl == NULL_TREE)
1425 {
1426 fn_type = M32R_FUNCTION_UNKNOWN;
1427 last_fn = NULL_TREE;
1428 return fn_type;
1429 }
1430
1431 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1432 return fn_type;
1433
1434 /* Compute function type. */
e3c541f0 1435 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
d868a170 1436 ? M32R_FUNCTION_INTERRUPT
1437 : M32R_FUNCTION_NORMAL);
1438
1439 last_fn = decl;
1440 return fn_type;
1441}
1442\f/* Function prologue/epilogue handlers. */
1443
1444/* M32R stack frames look like:
1445
1446 Before call After call
1447 +-----------------------+ +-----------------------+
1448 | | | |
1449 high | local variables, | | local variables, |
1450 mem | reg save area, etc. | | reg save area, etc. |
1451 | | | |
1452 +-----------------------+ +-----------------------+
1453 | | | |
1454 | arguments on stack. | | arguments on stack. |
1455 | | | |
1456 SP+0->+-----------------------+ +-----------------------+
1457 | reg parm save area, |
58f4ce52 1458 | only created for |
1459 | variable argument |
1460 | functions |
d868a170 1461 +-----------------------+
1462 | previous frame ptr |
58f4ce52 1463 +-----------------------+
1464 | |
1465 | register save area |
1466 | |
d868a170 1467 +-----------------------+
58f4ce52 1468 | return address |
1469 +-----------------------+
1470 | |
1471 | local variables |
1472 | |
1473 +-----------------------+
1474 | |
1475 | alloca allocations |
1476 | |
1477 +-----------------------+
1478 | |
1479 low | arguments on stack |
1480 memory | |
1481 SP+0->+-----------------------+
d868a170 1482
1483Notes:
14841) The "reg parm save area" does not exist for non variable argument fns.
14852) The "reg parm save area" can be eliminated completely if we saved regs
1486 containing anonymous args separately but that complicates things too
1487 much (so it's not done).
14883) The return address is saved after the register save area so as to have as
aea2fd96 1489 many insns as possible between the restoration of `lr' and the `jmp lr'. */
d868a170 1490
1491/* Structure to be filled in by m32r_compute_frame_size with register
1492 save masks, and offsets for the current function. */
1493struct m32r_frame_info
1494{
aea2fd96 1495 unsigned int total_size; /* # bytes that the entire frame takes up. */
1496 unsigned int extra_size; /* # bytes of extra stuff. */
1497 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1498 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1499 unsigned int reg_size; /* # bytes needed to store regs. */
1500 unsigned int var_size; /* # bytes that variables take up. */
1501 unsigned int gmask; /* Mask of saved gp registers. */
1502 unsigned int save_fp; /* Nonzero if fp must be saved. */
1503 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1504 int initialized; /* Nonzero if frame size already calculated. */
d868a170 1505};
1506
1507/* Current frame information calculated by m32r_compute_frame_size. */
1508static struct m32r_frame_info current_frame_info;
1509
1510/* Zero structure to initialize current_frame_info. */
1511static struct m32r_frame_info zero_frame_info;
1512
1513#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
aea2fd96 1514#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
d868a170 1515
1516/* Tell prologue and epilogue if register REGNO should be saved / restored.
1517 The return address and frame pointer are treated separately.
1518 Don't consider them here. */
1519#define MUST_SAVE_REGISTER(regno, interrupt_p) \
bca30b06 1520 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
3072d30e 1521 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
d868a170 1522
3072d30e 1523#define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
18d50ae6 1524#define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
d868a170 1525
aea2fd96 1526#define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1527#define LONG_INSN_SIZE 4 /* Size of long instructions. */
868d8e32 1528
d868a170 1529/* Return the bytes needed to compute the frame pointer from the current
1530 stack pointer.
1531
1532 SIZE is the size needed for local variables. */
1533
1534unsigned int
aea2fd96 1535m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
d868a170 1536{
58f4ce52 1537 unsigned int regno;
d868a170 1538 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
72061572 1539 unsigned int reg_size;
d868a170 1540 unsigned int gmask;
1541 enum m32r_function_type fn_type;
1542 int interrupt_p;
18d50ae6 1543 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1544 | crtl->profile);
d868a170 1545
1546 var_size = M32R_STACK_ALIGN (size);
abe32cce 1547 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size);
1548 pretend_size = crtl->args.pretend_args_size;
d868a170 1549 extra_size = FIRST_PARM_OFFSET (0);
1550 total_size = extra_size + pretend_size + args_size + var_size;
1551 reg_size = 0;
1552 gmask = 0;
1553
1554 /* See if this is an interrupt handler. Call used registers must be saved
1555 for them too. */
1556 fn_type = m32r_compute_function_type (current_function_decl);
1557 interrupt_p = M32R_INTERRUPT_P (fn_type);
1558
1559 /* Calculate space needed for registers. */
d868a170 1560 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1561 {
467dc9aa 1562 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1563 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
d868a170 1564 {
1565 reg_size += UNITS_PER_WORD;
1566 gmask |= 1 << regno;
1567 }
1568 }
1569
1570 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
467dc9aa 1571 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
d868a170 1572
1573 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1574 * UNITS_PER_WORD);
1575 total_size += reg_size;
1576
b4d5d8b8 1577 /* ??? Not sure this is necessary, and I don't think the epilogue
d868a170 1578 handler will do the right thing if this changes total_size. */
1579 total_size = M32R_STACK_ALIGN (total_size);
1580
72061572 1581 /* frame_size = total_size - (pretend_size + reg_size); */
868d8e32 1582
d868a170 1583 /* Save computed information. */
1584 current_frame_info.total_size = total_size;
1585 current_frame_info.extra_size = extra_size;
1586 current_frame_info.pretend_size = pretend_size;
1587 current_frame_info.var_size = var_size;
1588 current_frame_info.args_size = args_size;
1589 current_frame_info.reg_size = reg_size;
1590 current_frame_info.gmask = gmask;
1591 current_frame_info.initialized = reload_completed;
1592
1593 /* Ok, we're done. */
1594 return total_size;
1595}
cd90919d 1596
1597/* Worker function for TARGET_CAN_ELIMINATE. */
1598
1599bool
1600m32r_can_eliminate (const int from, const int to)
1601{
1602 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
1603 ? ! frame_pointer_needed
1604 : true);
1605}
1606
d868a170 1607\f
467dc9aa 1608/* The table we use to reference PIC data. */
1609static rtx global_offset_table;
58f4ce52 1610
6440ef45 1611static void
1612m32r_reload_lr (rtx sp, int size)
1613{
1614 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1615
1616 if (size == 0)
58f4ce52 1617 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp)));
84e0b98d 1618 else if (size < 32768)
58f4ce52 1619 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode,
1620 gen_rtx_PLUS (Pmode, sp,
1621 GEN_INT (size)))));
6440ef45 1622 else
58f4ce52 1623 {
6440ef45 1624 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1625
1626 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1627 emit_insn (gen_addsi3 (tmp, tmp, sp));
58f4ce52 1628 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp)));
6440ef45 1629 }
1630
18b42941 1631 emit_use (lr);
6440ef45 1632}
1633
467dc9aa 1634void
1635m32r_load_pic_register (void)
1636{
1637 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1638 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
73a1a86f 1639 GEN_INT (TARGET_MODEL_SMALL)));
58f4ce52 1640
467dc9aa 1641 /* Need to emit this whether or not we obey regdecls,
1642 since setjmp/longjmp can cause life info to screw up. */
18b42941 1643 emit_use (pic_offset_table_rtx);
467dc9aa 1644}
1645
7dbe3569 1646/* Expand the m32r prologue as a series of insns. */
d868a170 1647
1648void
aea2fd96 1649m32r_expand_prologue (void)
d868a170 1650{
1651 int regno;
7dbe3569 1652 int frame_size;
947391dc 1653 unsigned int gmask;
18d50ae6 1654 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1655 | crtl->profile);
d868a170 1656
7dbe3569 1657 if (! current_frame_info.initialized)
1658 m32r_compute_frame_size (get_frame_size ());
868d8e32 1659
7dbe3569 1660 gmask = current_frame_info.gmask;
d868a170 1661
1662 /* These cases shouldn't happen. Catch them now. */
7afac3c3 1663 gcc_assert (current_frame_info.total_size || !gmask);
d868a170 1664
d868a170 1665 /* Allocate space for register arguments if this is a variadic function. */
1666 if (current_frame_info.pretend_size != 0)
31a162bd 1667 {
1668 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1669 the wrong result on a 64-bit host. */
1670 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1671 emit_insn (gen_addsi3 (stack_pointer_rtx,
1672 stack_pointer_rtx,
1673 GEN_INT (-pretend_size)));
1674 }
d868a170 1675
1676 /* Save any registers we need to and set up fp. */
d868a170 1677 if (current_frame_info.save_fp)
7dbe3569 1678 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
d868a170 1679
1680 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1681
1682 /* Save any needed call-saved regs (and call-used if this is an
1683 interrupt handler). */
1684 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1685 {
1686 if ((gmask & (1 << regno)) != 0)
7dbe3569 1687 emit_insn (gen_movsi_push (stack_pointer_rtx,
1688 gen_rtx_REG (Pmode, regno)));
d868a170 1689 }
1690
1691 if (current_frame_info.save_lr)
7dbe3569 1692 emit_insn (gen_movsi_push (stack_pointer_rtx,
1693 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
d868a170 1694
1695 /* Allocate the stack frame. */
7dbe3569 1696 frame_size = (current_frame_info.total_size
1697 - (current_frame_info.pretend_size
1698 + current_frame_info.reg_size));
1699
d868a170 1700 if (frame_size == 0)
aea2fd96 1701 ; /* Nothing to do. */
d868a170 1702 else if (frame_size <= 32768)
7dbe3569 1703 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1704 GEN_INT (-frame_size)));
d868a170 1705 else
7dbe3569 1706 {
1707 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
aea2fd96 1708
7dbe3569 1709 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1710 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1711 }
d868a170 1712
1713 if (frame_pointer_needed)
7dbe3569 1714 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1715
18d50ae6 1716 if (crtl->profile)
467dc9aa 1717 /* Push lr for mcount (form_pc, x). */
1718 emit_insn (gen_movsi_push (stack_pointer_rtx,
1719 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
58f4ce52 1720
467dc9aa 1721 if (pic_reg_used)
6440ef45 1722 {
1723 m32r_load_pic_register ();
1724 m32r_reload_lr (stack_pointer_rtx,
18d50ae6 1725 (crtl->profile ? 0 : frame_size));
6440ef45 1726 }
467dc9aa 1727
18d50ae6 1728 if (crtl->profile && !pic_reg_used)
7dbe3569 1729 emit_insn (gen_blockage ());
1730}
1731
1732\f
1733/* Set up the stack and frame pointer (if desired) for the function.
1734 Note, if this is changed, you need to mirror the changes in
1735 m32r_compute_frame_size which calculates the prolog size. */
1736
17d9b0c3 1737static void
aea2fd96 1738m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
7dbe3569 1739{
1740 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1741
1742 /* If this is an interrupt handler, mark it as such. */
1743 if (M32R_INTERRUPT_P (fn_type))
aea2fd96 1744 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
7dbe3569 1745
1746 if (! current_frame_info.initialized)
1747 m32r_compute_frame_size (size);
d868a170 1748
7dbe3569 1749 /* This is only for the human reader. */
1750 fprintf (file,
1751 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1752 ASM_COMMENT_START,
1753 current_frame_info.var_size,
1754 current_frame_info.reg_size / 4,
1755 current_frame_info.args_size,
1756 current_frame_info.extra_size);
d868a170 1757}
1758\f
58f4ce52 1759/* Output RTL to pop register REGNO from the stack. */
d868a170 1760
17d9b0c3 1761static void
58f4ce52 1762pop (int regno)
1763{
1764 rtx x;
1765
1766 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno),
1767 stack_pointer_rtx));
ef51d1e3 1768 add_reg_note (x, REG_INC, stack_pointer_rtx);
58f4ce52 1769}
1770
1771/* Expand the m32r epilogue as a series of insns. */
1772
1773void
1774m32r_expand_epilogue (void)
d868a170 1775{
1776 int regno;
1777 int noepilogue = FALSE;
1778 int total_size;
d868a170 1779
7afac3c3 1780 gcc_assert (current_frame_info.initialized);
d868a170 1781 total_size = current_frame_info.total_size;
1782
1783 if (total_size == 0)
1784 {
1785 rtx insn = get_last_insn ();
1786
1787 /* If the last insn was a BARRIER, we don't have to write any code
1788 because a jump (aka return) was put there. */
452bfb8b 1789 if (insn && NOTE_P (insn))
d868a170 1790 insn = prev_nonnote_insn (insn);
452bfb8b 1791 if (insn && BARRIER_P (insn))
d868a170 1792 noepilogue = TRUE;
1793 }
1794
1795 if (!noepilogue)
1796 {
d868a170 1797 unsigned int var_size = current_frame_info.var_size;
1798 unsigned int args_size = current_frame_info.args_size;
1799 unsigned int gmask = current_frame_info.gmask;
18d50ae6 1800 int can_trust_sp_p = !cfun->calls_alloca;
58f4ce52 1801
1802 if (flag_exceptions)
1803 emit_insn (gen_blockage ());
d868a170 1804
1805 /* The first thing to do is point the sp at the bottom of the register
1806 save area. */
1807 if (can_trust_sp_p)
1808 {
1809 unsigned int reg_offset = var_size + args_size;
58f4ce52 1810
d868a170 1811 if (reg_offset == 0)
aea2fd96 1812 ; /* Nothing to do. */
d868a170 1813 else if (reg_offset < 32768)
58f4ce52 1814 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1815 GEN_INT (reg_offset)));
69e870b0 1816 else
58f4ce52 1817 {
1818 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1819
1820 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1821 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1822 tmp));
1823 }
d868a170 1824 }
1825 else if (frame_pointer_needed)
1826 {
1827 unsigned int reg_offset = var_size + args_size;
aea2fd96 1828
d868a170 1829 if (reg_offset == 0)
58f4ce52 1830 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
d868a170 1831 else if (reg_offset < 32768)
58f4ce52 1832 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
1833 GEN_INT (reg_offset)));
69e870b0 1834 else
58f4ce52 1835 {
1836 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1837
1838 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1839 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1840 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1841 tmp));
1842 }
d868a170 1843 }
1844 else
7afac3c3 1845 gcc_unreachable ();
d868a170 1846
1847 if (current_frame_info.save_lr)
58f4ce52 1848 pop (RETURN_ADDR_REGNUM);
d868a170 1849
1850 /* Restore any saved registers, in reverse order of course. */
1851 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1852 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1853 {
1854 if ((gmask & (1L << regno)) != 0)
58f4ce52 1855 pop (regno);
d868a170 1856 }
1857
1858 if (current_frame_info.save_fp)
58f4ce52 1859 pop (FRAME_POINTER_REGNUM);
d868a170 1860
1861 /* Remove varargs area if present. */
d868a170 1862 if (current_frame_info.pretend_size != 0)
58f4ce52 1863 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1864 GEN_INT (current_frame_info.pretend_size)));
1865
1866 emit_insn (gen_blockage ());
d868a170 1867 }
58f4ce52 1868}
1869
1870/* Do any necessary cleanup after a function to restore stack, frame,
1871 and regs. */
d868a170 1872
58f4ce52 1873static void
1874m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED,
1875 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1876{
d868a170 1877 /* Reset state info for each function. */
1878 current_frame_info = zero_frame_info;
1879 m32r_compute_function_type (NULL_TREE);
1880}
947391dc 1881\f
e911aedf 1882/* Return nonzero if this function is known to have a null or 1 instruction
947391dc 1883 epilogue. */
1884
1885int
aea2fd96 1886direct_return (void)
947391dc 1887{
1888 if (!reload_completed)
1889 return FALSE;
1890
58f4ce52 1891 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl)))
1892 return FALSE;
1893
947391dc 1894 if (! current_frame_info.initialized)
1895 m32r_compute_frame_size (get_frame_size ());
1896
58f4ce52 1897 return current_frame_info.total_size == 0;
947391dc 1898}
1899
d868a170 1900\f
aea2fd96 1901/* PIC. */
d868a170 1902
467dc9aa 1903int
1904m32r_legitimate_pic_operand_p (rtx x)
1905{
1906 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1907 return 0;
58f4ce52 1908
467dc9aa 1909 if (GET_CODE (x) == CONST
1910 && GET_CODE (XEXP (x, 0)) == PLUS
1911 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1912 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
452bfb8b 1913 && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
467dc9aa 1914 return 0;
58f4ce52 1915
467dc9aa 1916 return 1;
1917}
1918
1919rtx
1920m32r_legitimize_pic_address (rtx orig, rtx reg)
1921{
1922#ifdef DEBUG_PIC
1923 printf("m32r_legitimize_pic_address()\n");
1924#endif
1925
1926 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1927 {
1928 rtx pic_ref, address;
467dc9aa 1929 int subregs = 0;
1930
1931 if (reg == 0)
1932 {
7afac3c3 1933 gcc_assert (!reload_in_progress && !reload_completed);
1934 reg = gen_reg_rtx (Pmode);
467dc9aa 1935
1936 subregs = 1;
1937 }
1938
1939 if (subregs)
1940 address = gen_reg_rtx (Pmode);
1941 else
1942 address = reg;
1943
18d50ae6 1944 crtl->uses_pic_offset_table = 1;
72afe58b 1945
1946 if (GET_CODE (orig) == LABEL_REF
1947 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1948 {
1949 emit_insn (gen_gotoff_load_addr (reg, orig));
1950 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1951 return reg;
1952 }
1953
467dc9aa 1954 emit_insn (gen_pic_load_addr (address, orig));
1955
1956 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
e265a6da 1957 pic_ref = gen_const_mem (Pmode, address);
72061572 1958 emit_move_insn (reg, pic_ref);
467dc9aa 1959 return reg;
1960 }
1961 else if (GET_CODE (orig) == CONST)
1962 {
1963 rtx base, offset;
1964
1965 if (GET_CODE (XEXP (orig, 0)) == PLUS
1966 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1967 return orig;
1968
1969 if (reg == 0)
1970 {
7afac3c3 1971 gcc_assert (!reload_in_progress && !reload_completed);
1972 reg = gen_reg_rtx (Pmode);
467dc9aa 1973 }
1974
1975 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1976 {
1977 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1978 if (base == reg)
1979 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1980 else
1981 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1982 }
1983 else
1984 return orig;
1985
452bfb8b 1986 if (CONST_INT_P (offset))
467dc9aa 1987 {
1988 if (INT16_P (INTVAL (offset)))
29c05e22 1989 return plus_constant (Pmode, base, INTVAL (offset));
467dc9aa 1990 else
7afac3c3 1991 {
1992 gcc_assert (! reload_in_progress && ! reload_completed);
1993 offset = force_reg (Pmode, offset);
1994 }
467dc9aa 1995 }
1996
1a83b3ff 1997 return gen_rtx_PLUS (Pmode, base, offset);
467dc9aa 1998 }
1999
2000 return orig;
2001}
41e3a0c7 2002
2003static rtx
2004m32r_legitimize_address (rtx x, rtx orig_x ATTRIBUTE_UNUSED,
2005 enum machine_mode mode ATTRIBUTE_UNUSED)
2006{
2007 if (flag_pic)
2008 return m32r_legitimize_pic_address (x, NULL_RTX);
2009 else
2010 return x;
2011}
8c9a773b 2012
2013/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2014
2015static bool
4e27ffd0 2016m32r_mode_dependent_address_p (const_rtx addr, addr_space_t as ATTRIBUTE_UNUSED)
8c9a773b 2017{
2018 if (GET_CODE (addr) == LO_SUM)
2019 return true;
2020
2021 return false;
2022}
d868a170 2023\f
2024/* Nested function support. */
2025
2026/* Emit RTL insns to initialize the variable parts of a trampoline.
2027 FNADDR is an RTX for the address of the function's pure code.
2028 CXT is an RTX for the static chain value for the function. */
2029
2030void
aea2fd96 2031m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
2032 rtx fnaddr ATTRIBUTE_UNUSED,
2033 rtx cxt ATTRIBUTE_UNUSED)
d868a170 2034{
2035}
2036\f
92c473b8 2037static void
aea2fd96 2038m32r_file_start (void)
d868a170 2039{
92c473b8 2040 default_file_start ();
2041
d868a170 2042 if (flag_verbose_asm)
92c473b8 2043 fprintf (asm_out_file,
13a54dd9 2044 "%s M32R/D special options: -G %d\n",
d868a170 2045 ASM_COMMENT_START, g_switch_value);
467dc9aa 2046
2047 if (TARGET_LITTLE_ENDIAN)
2048 fprintf (asm_out_file, "\t.little\n");
d868a170 2049}
2050\f
2051/* Print operand X (an rtx) in assembler syntax to file FILE.
2052 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2053 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2054
8e8a63d1 2055static void
aea2fd96 2056m32r_print_operand (FILE * file, rtx x, int code)
d868a170 2057{
7dbe3569 2058 rtx addr;
2059
d868a170 2060 switch (code)
2061 {
173e37ab 2062 /* The 's' and 'p' codes are used by output_block_move() to
2063 indicate post-increment 's'tores and 'p're-increment loads. */
2064 case 's':
452bfb8b 2065 if (REG_P (x))
173e37ab 2066 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2067 else
a1657b95 2068 output_operand_lossage ("invalid operand to %%s code");
173e37ab 2069 return;
58f4ce52 2070
173e37ab 2071 case 'p':
452bfb8b 2072 if (REG_P (x))
173e37ab 2073 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2074 else
a1657b95 2075 output_operand_lossage ("invalid operand to %%p code");
173e37ab 2076 return;
2077
d868a170 2078 case 'R' :
2079 /* Write second word of DImode or DFmode reference,
2080 register or memory. */
452bfb8b 2081 if (REG_P (x))
d868a170 2082 fputs (reg_names[REGNO (x)+1], file);
452bfb8b 2083 else if (MEM_P (x))
d868a170 2084 {
2085 fprintf (file, "@(");
2086 /* Handle possible auto-increment. Since it is pre-increment and
2087 we have already done it, we can just use an offset of four. */
2088 /* ??? This is taken from rs6000.c I think. I don't think it is
2089 currently necessary, but keep it around. */
2090 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2091 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
29c05e22 2092 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 4));
d868a170 2093 else
29c05e22 2094 output_address (plus_constant (Pmode, XEXP (x, 0), 4));
d868a170 2095 fputc (')', file);
2096 }
2097 else
a1657b95 2098 output_operand_lossage ("invalid operand to %%R code");
d868a170 2099 return;
2100
aea2fd96 2101 case 'H' : /* High word. */
2102 case 'L' : /* Low word. */
452bfb8b 2103 if (REG_P (x))
d868a170 2104 {
aea2fd96 2105 /* L = least significant word, H = most significant word. */
d868a170 2106 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2107 fputs (reg_names[REGNO (x)], file);
2108 else
2109 fputs (reg_names[REGNO (x)+1], file);
2110 }
452bfb8b 2111 else if (CONST_INT_P (x)
d868a170 2112 || GET_CODE (x) == CONST_DOUBLE)
2113 {
2114 rtx first, second;
2115
2116 split_double (x, &first, &second);
6441a98f 2117 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
d868a170 2118 code == 'L' ? INTVAL (first) : INTVAL (second));
2119 }
2120 else
a1657b95 2121 output_operand_lossage ("invalid operand to %%H/%%L code");
d868a170 2122 return;
2123
2124 case 'A' :
2125 {
d868a170 2126 char str[30];
2127
2128 if (GET_CODE (x) != CONST_DOUBLE
2129 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
68435912 2130 fatal_insn ("bad insn for 'A'", x);
c7fbc741 2131
2132 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
d868a170 2133 fprintf (file, "%s", str);
2134 return;
2135 }
2136
aea2fd96 2137 case 'B' : /* Bottom half. */
2138 case 'T' : /* Top half. */
d868a170 2139 /* Output the argument to a `seth' insn (sets the Top half-word).
2140 For constants output arguments to a seth/or3 pair to set Top and
2141 Bottom halves. For symbols output arguments to a seth/add3 pair to
2142 set Top and Bottom halves. The difference exists because for
2143 constants seth/or3 is more readable but for symbols we need to use
c910419d 2144 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
d868a170 2145 switch (GET_CODE (x))
2146 {
2147 case CONST_INT :
2148 case CONST_DOUBLE :
2149 {
2150 rtx first, second;
2151
2152 split_double (x, &first, &second);
2153 x = WORDS_BIG_ENDIAN ? second : first;
5c5d0ae9 2154 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
d868a170 2155 (code == 'B'
2156 ? INTVAL (x) & 0xffff
2157 : (INTVAL (x) >> 16) & 0xffff));
2158 }
2159 return;
2160 case CONST :
2161 case SYMBOL_REF :
2162 if (code == 'B'
2163 && small_data_operand (x, VOIDmode))
2164 {
2165 fputs ("sda(", file);
2166 output_addr_const (file, x);
2167 fputc (')', file);
2168 return;
2169 }
2170 /* fall through */
2171 case LABEL_REF :
2172 fputs (code == 'T' ? "shigh(" : "low(", file);
2173 output_addr_const (file, x);
2174 fputc (')', file);
2175 return;
2176 default :
a1657b95 2177 output_operand_lossage ("invalid operand to %%T/%%B code");
d868a170 2178 return;
2179 }
2180 break;
2181
2182 case 'U' :
8ec9afef 2183 /* ??? wip */
d868a170 2184 /* Output a load/store with update indicator if appropriate. */
452bfb8b 2185 if (MEM_P (x))
d868a170 2186 {
2187 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2188 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2189 fputs (".a", file);
2190 }
2191 else
a1657b95 2192 output_operand_lossage ("invalid operand to %%U code");
d868a170 2193 return;
2194
2195 case 'N' :
2196 /* Print a constant value negated. */
452bfb8b 2197 if (CONST_INT_P (x))
d868a170 2198 output_addr_const (file, GEN_INT (- INTVAL (x)));
2199 else
a1657b95 2200 output_operand_lossage ("invalid operand to %%N code");
d868a170 2201 return;
2202
205bb293 2203 case 'X' :
2204 /* Print a const_int in hex. Used in comments. */
452bfb8b 2205 if (CONST_INT_P (x))
5c5d0ae9 2206 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
205bb293 2207 return;
2208
d868a170 2209 case '#' :
2210 fputs (IMMEDIATE_PREFIX, file);
2211 return;
2212
d868a170 2213 case 0 :
2214 /* Do nothing special. */
2215 break;
2216
2217 default :
2218 /* Unknown flag. */
2219 output_operand_lossage ("invalid operand output code");
2220 }
2221
2222 switch (GET_CODE (x))
2223 {
2224 case REG :
2225 fputs (reg_names[REGNO (x)], file);
2226 break;
2227
2228 case MEM :
7dbe3569 2229 addr = XEXP (x, 0);
2230 if (GET_CODE (addr) == PRE_INC)
2231 {
452bfb8b 2232 if (!REG_P (XEXP (addr, 0)))
68435912 2233 fatal_insn ("pre-increment address is not a register", x);
7dbe3569 2234
2235 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2236 }
2237 else if (GET_CODE (addr) == PRE_DEC)
2238 {
452bfb8b 2239 if (!REG_P (XEXP (addr, 0)))
68435912 2240 fatal_insn ("pre-decrement address is not a register", x);
7dbe3569 2241
2242 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2243 }
2244 else if (GET_CODE (addr) == POST_INC)
2245 {
452bfb8b 2246 if (!REG_P (XEXP (addr, 0)))
68435912 2247 fatal_insn ("post-increment address is not a register", x);
7dbe3569 2248
2249 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2250 }
d868a170 2251 else
7dbe3569 2252 {
2253 fputs ("@(", file);
2254 output_address (XEXP (x, 0));
2255 fputc (')', file);
2256 }
d868a170 2257 break;
2258
2259 case CONST_DOUBLE :
2260 /* We handle SFmode constants here as output_addr_const doesn't. */
2261 if (GET_MODE (x) == SFmode)
2262 {
2263 REAL_VALUE_TYPE d;
2264 long l;
2265
2266 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2267 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2268 fprintf (file, "0x%08lx", l);
2269 break;
2270 }
2271
2272 /* Fall through. Let output_addr_const deal with it. */
2273
2274 default :
2275 output_addr_const (file, x);
2276 break;
2277 }
2278}
2279
2280/* Print a memory address as an operand to reference that memory location. */
2281
8e8a63d1 2282static void
aea2fd96 2283m32r_print_operand_address (FILE * file, rtx addr)
d868a170 2284{
aea2fd96 2285 rtx base;
2286 rtx index = 0;
2287 int offset = 0;
d868a170 2288
2289 switch (GET_CODE (addr))
2290 {
2291 case REG :
2292 fputs (reg_names[REGNO (addr)], file);
2293 break;
2294
2295 case PLUS :
452bfb8b 2296 if (CONST_INT_P (XEXP (addr, 0)))
d868a170 2297 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
452bfb8b 2298 else if (CONST_INT_P (XEXP (addr, 1)))
d868a170 2299 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2300 else
2301 base = XEXP (addr, 0), index = XEXP (addr, 1);
452bfb8b 2302 if (REG_P (base))
d868a170 2303 {
2304 /* Print the offset first (if present) to conform to the manual. */
2305 if (index == 0)
2306 {
2307 if (offset != 0)
2308 fprintf (file, "%d,", offset);
2309 fputs (reg_names[REGNO (base)], file);
2310 }
2311 /* The chip doesn't support this, but left in for generality. */
452bfb8b 2312 else if (REG_P (index))
d868a170 2313 fprintf (file, "%s,%s",
2314 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2315 /* Not sure this can happen, but leave in for now. */
2316 else if (GET_CODE (index) == SYMBOL_REF)
2317 {
2318 output_addr_const (file, index);
2319 fputc (',', file);
2320 fputs (reg_names[REGNO (base)], file);
2321 }
2322 else
68435912 2323 fatal_insn ("bad address", addr);
d868a170 2324 }
2325 else if (GET_CODE (base) == LO_SUM)
2326 {
452bfb8b 2327 gcc_assert (!index && REG_P (XEXP (base, 0)));
d868a170 2328 if (small_data_operand (XEXP (base, 1), VOIDmode))
2329 fputs ("sda(", file);
2330 else
2331 fputs ("low(", file);
29c05e22 2332 output_addr_const (file, plus_constant (Pmode, XEXP (base, 1),
2333 offset));
d868a170 2334 fputs ("),", file);
2335 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2336 }
2337 else
68435912 2338 fatal_insn ("bad address", addr);
d868a170 2339 break;
2340
2341 case LO_SUM :
452bfb8b 2342 if (!REG_P (XEXP (addr, 0)))
68435912 2343 fatal_insn ("lo_sum not of register", addr);
d868a170 2344 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2345 fputs ("sda(", file);
2346 else
2347 fputs ("low(", file);
2348 output_addr_const (file, XEXP (addr, 1));
2349 fputs ("),", file);
2350 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2351 break;
2352
aea2fd96 2353 case PRE_INC : /* Assume SImode. */
7dbe3569 2354 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2355 break;
2356
aea2fd96 2357 case PRE_DEC : /* Assume SImode. */
7dbe3569 2358 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2359 break;
2360
aea2fd96 2361 case POST_INC : /* Assume SImode. */
7dbe3569 2362 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
d868a170 2363 break;
2364
2365 default :
2366 output_addr_const (file, addr);
2367 break;
2368 }
2369}
868d8e32 2370
8e8a63d1 2371static bool
2372m32r_print_operand_punct_valid_p (unsigned char code)
2373{
2374 return m32r_punct_chars[code];
2375}
2376
868d8e32 2377/* Return true if the operands are the constants 0 and 1. */
aea2fd96 2378
868d8e32 2379int
aea2fd96 2380zero_and_one (rtx operand1, rtx operand2)
868d8e32 2381{
2382 return
452bfb8b 2383 CONST_INT_P (operand1)
2384 && CONST_INT_P (operand2)
868d8e32 2385 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2386 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2387}
2388
868d8e32 2389/* Generate the correct assembler code to handle the conditional loading of a
2390 value into a register. It is known that the operands satisfy the
2391 conditional_move_operand() function above. The destination is operand[0].
2392 The condition is operand [1]. The 'true' value is operand [2] and the
2393 'false' value is operand [3]. */
aea2fd96 2394
868d8e32 2395char *
aea2fd96 2396emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
868d8e32 2397{
2398 static char buffer [100];
08c762a3 2399 const char * dest = reg_names [REGNO (operands [0])];
58f4ce52 2400
868d8e32 2401 buffer [0] = 0;
58f4ce52 2402
868d8e32 2403 /* Destination must be a register. */
452bfb8b 2404 gcc_assert (REG_P (operands [0]));
7afac3c3 2405 gcc_assert (conditional_move_operand (operands [2], SImode));
2406 gcc_assert (conditional_move_operand (operands [3], SImode));
58f4ce52 2407
868d8e32 2408 /* Check to see if the test is reversed. */
2409 if (GET_CODE (operands [1]) == NE)
2410 {
2411 rtx tmp = operands [2];
2412 operands [2] = operands [3];
2413 operands [3] = tmp;
2414 }
2415
60bbc120 2416 sprintf (buffer, "mvfc %s, cbr", dest);
03033f8f 2417
60bbc120 2418 /* If the true value was '0' then we need to invert the results of the move. */
2419 if (INTVAL (operands [2]) == 0)
2420 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2421 dest, dest);
03033f8f 2422
868d8e32 2423 return buffer;
2424}
2425
947391dc 2426/* Returns true if the registers contained in the two
1d60d981 2427 rtl expressions are different. */
aea2fd96 2428
947391dc 2429int
aea2fd96 2430m32r_not_same_reg (rtx a, rtx b)
947391dc 2431{
2432 int reg_a = -1;
2433 int reg_b = -2;
58f4ce52 2434
947391dc 2435 while (GET_CODE (a) == SUBREG)
2436 a = SUBREG_REG (a);
58f4ce52 2437
452bfb8b 2438 if (REG_P (a))
947391dc 2439 reg_a = REGNO (a);
58f4ce52 2440
947391dc 2441 while (GET_CODE (b) == SUBREG)
2442 b = SUBREG_REG (b);
58f4ce52 2443
452bfb8b 2444 if (REG_P (b))
947391dc 2445 reg_b = REGNO (b);
58f4ce52 2446
947391dc 2447 return reg_a != reg_b;
2448}
173e37ab 2449
2450\f
fe34fa5a 2451rtx
2452m32r_function_symbol (const char *name)
2453{
2454 int extra_flags = 0;
2455 enum m32r_model model;
2456 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2457
2458 if (TARGET_MODEL_SMALL)
2459 model = M32R_MODEL_SMALL;
2460 else if (TARGET_MODEL_MEDIUM)
2461 model = M32R_MODEL_MEDIUM;
2462 else if (TARGET_MODEL_LARGE)
2463 model = M32R_MODEL_LARGE;
2464 else
7afac3c3 2465 gcc_unreachable (); /* Shouldn't happen. */
fe34fa5a 2466 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
58f4ce52 2467
fe34fa5a 2468 if (extra_flags)
2469 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2470
2471 return sym;
2472}
2473
173e37ab 2474/* Use a library function to move some bytes. */
aea2fd96 2475
173e37ab 2476static void
a11b18dd 2477block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
173e37ab 2478{
2479 /* We want to pass the size as Pmode, which will normally be SImode
c910419d 2480 but will be DImode if we are using 64-bit longs and pointers. */
173e37ab 2481 if (GET_MODE (bytes_rtx) != VOIDmode
2482 && GET_MODE (bytes_rtx) != Pmode)
2483 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2484
ef51d1e3 2485 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL,
173e37ab 2486 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2487 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
78a8ed03 2488 TYPE_UNSIGNED (sizetype)),
173e37ab 2489 TYPE_MODE (sizetype));
173e37ab 2490}
2491
173e37ab 2492/* Expand string/block move operations.
2493
2494 operands[0] is the pointer to the destination.
2495 operands[1] is the pointer to the source.
2496 operands[2] is the number of bytes to move.
9ca439fa 2497 operands[3] is the alignment.
173e37ab 2498
9ca439fa 2499 Returns 1 upon success, 0 otherwise. */
2500
2501int
aea2fd96 2502m32r_expand_block_move (rtx operands[])
173e37ab 2503{
2504 rtx orig_dst = operands[0];
2505 rtx orig_src = operands[1];
2506 rtx bytes_rtx = operands[2];
2507 rtx align_rtx = operands[3];
452bfb8b 2508 int constp = CONST_INT_P (bytes_rtx);
173e37ab 2509 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2510 int align = INTVAL (align_rtx);
2511 int leftover;
2512 rtx src_reg;
2513 rtx dst_reg;
2514
2515 if (constp && bytes <= 0)
9ca439fa 2516 return 1;
173e37ab 2517
2518 /* Move the address into scratch registers. */
2519 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2520 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2521
2522 if (align > UNITS_PER_WORD)
2523 align = UNITS_PER_WORD;
2524
2525 /* If we prefer size over speed, always use a function call.
2526 If we do not know the size, use a function call.
2527 If the blocks are not word aligned, use a function call. */
2528 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2529 {
2530 block_move_call (dst_reg, src_reg, bytes_rtx);
9ca439fa 2531 return 0;
173e37ab 2532 }
2533
2534 leftover = bytes % MAX_MOVE_BYTES;
2535 bytes -= leftover;
58f4ce52 2536
173e37ab 2537 /* If necessary, generate a loop to handle the bulk of the copy. */
2538 if (bytes)
2539 {
e51fa923 2540 rtx label = NULL_RTX;
2541 rtx final_src = NULL_RTX;
f4a9eadc 2542 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2543 rtx rounded_total = GEN_INT (bytes);
76dad66d 2544 rtx new_dst_reg = gen_reg_rtx (SImode);
2545 rtx new_src_reg = gen_reg_rtx (SImode);
173e37ab 2546
2547 /* If we are going to have to perform this loop more than
2548 once, then generate a label and compute the address the
2549 source register will contain upon completion of the final
dfd1079d 2550 iteration. */
173e37ab 2551 if (bytes > MAX_MOVE_BYTES)
2552 {
2553 final_src = gen_reg_rtx (Pmode);
2554
2555 if (INT16_P(bytes))
f4a9eadc 2556 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
173e37ab 2557 else
2558 {
f4a9eadc 2559 emit_insn (gen_movsi (final_src, rounded_total));
173e37ab 2560 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2561 }
2562
2563 label = gen_label_rtx ();
2564 emit_label (label);
2565 }
2566
2567 /* It is known that output_block_move() will update src_reg to point
2568 to the word after the end of the source block, and dst_reg to point
2569 to the last word of the destination block, provided that the block
2570 is MAX_MOVE_BYTES long. */
008c057d 2571 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
76dad66d 2572 new_dst_reg, new_src_reg));
2573 emit_move_insn (dst_reg, new_dst_reg);
2574 emit_move_insn (src_reg, new_src_reg);
173e37ab 2575 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
58f4ce52 2576
173e37ab 2577 if (bytes > MAX_MOVE_BYTES)
2578 {
74f4459c 2579 rtx test = gen_rtx_NE (VOIDmode, src_reg, final_src);
2580 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
173e37ab 2581 }
2582 }
2583
2584 if (leftover)
008c057d 2585 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
76dad66d 2586 gen_reg_rtx (SImode),
2587 gen_reg_rtx (SImode)));
9ca439fa 2588 return 1;
173e37ab 2589}
2590
2591\f
58f4ce52 2592/* Emit load/stores for a small constant word aligned block_move.
173e37ab 2593
2594 operands[0] is the memory address of the destination.
2595 operands[1] is the memory address of the source.
2596 operands[2] is the number of bytes to move.
2597 operands[3] is a temp register.
2598 operands[4] is a temp register. */
2599
03033f8f 2600void
aea2fd96 2601m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
173e37ab 2602{
2603 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2604 int first_time;
2605 int got_extra = 0;
58f4ce52 2606
7afac3c3 2607 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
58f4ce52 2608
173e37ab 2609 /* We do not have a post-increment store available, so the first set of
2610 stores are done without any increment, then the remaining ones can use
2611 the pre-increment addressing mode.
58f4ce52 2612
e911aedf 2613 Note: expand_block_move() also relies upon this behavior when building
173e37ab 2614 loops to copy large blocks. */
2615 first_time = 1;
58f4ce52 2616
173e37ab 2617 while (bytes > 0)
2618 {
2619 if (bytes >= 8)
2620 {
2621 if (first_time)
2622 {
76dad66d 2623 output_asm_insn ("ld\t%5, %p1", operands);
2624 output_asm_insn ("ld\t%6, %p1", operands);
2625 output_asm_insn ("st\t%5, @%0", operands);
2626 output_asm_insn ("st\t%6, %s0", operands);
173e37ab 2627 }
2628 else
2629 {
76dad66d 2630 output_asm_insn ("ld\t%5, %p1", operands);
2631 output_asm_insn ("ld\t%6, %p1", operands);
2632 output_asm_insn ("st\t%5, %s0", operands);
2633 output_asm_insn ("st\t%6, %s0", operands);
173e37ab 2634 }
2635
2636 bytes -= 8;
2637 }
2638 else if (bytes >= 4)
2639 {
2640 if (bytes > 4)
2641 got_extra = 1;
58f4ce52 2642
76dad66d 2643 output_asm_insn ("ld\t%5, %p1", operands);
58f4ce52 2644
173e37ab 2645 if (got_extra)
76dad66d 2646 output_asm_insn ("ld\t%6, %p1", operands);
58f4ce52 2647
173e37ab 2648 if (first_time)
76dad66d 2649 output_asm_insn ("st\t%5, @%0", operands);
173e37ab 2650 else
76dad66d 2651 output_asm_insn ("st\t%5, %s0", operands);
173e37ab 2652
2653 bytes -= 4;
2654 }
58f4ce52 2655 else
173e37ab 2656 {
2657 /* Get the entire next word, even though we do not want all of it.
2658 The saves us from doing several smaller loads, and we assume that
2659 we cannot cause a page fault when at least part of the word is in
f4a9eadc 2660 valid memory [since we don't get called if things aren't properly
2661 aligned]. */
2662 int dst_offset = first_time ? 0 : 4;
76dad66d 2663 /* The amount of increment we have to make to the
2664 destination pointer. */
2665 int dst_inc_amount = dst_offset + bytes - 4;
2666 /* The same for the source pointer. */
2667 int src_inc_amount = bytes;
f4a9eadc 2668 int last_shift;
2669 rtx my_operands[3];
2670
2671 /* If got_extra is true then we have already loaded
173e37ab 2672 the next word as part of loading and storing the previous word. */
2673 if (! got_extra)
76dad66d 2674 output_asm_insn ("ld\t%6, @%1", operands);
173e37ab 2675
2676 if (bytes >= 2)
2677 {
2678 bytes -= 2;
2679
76dad66d 2680 output_asm_insn ("sra3\t%5, %6, #16", operands);
2681 my_operands[0] = operands[5];
f4a9eadc 2682 my_operands[1] = GEN_INT (dst_offset);
2683 my_operands[2] = operands[0];
2684 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
58f4ce52 2685
173e37ab 2686 /* If there is a byte left to store then increment the
2687 destination address and shift the contents of the source
f4a9eadc 2688 register down by 8 bits. We could not do the address
173e37ab 2689 increment in the store half word instruction, because it does
2690 not have an auto increment mode. */
2691 if (bytes > 0) /* assert (bytes == 1) */
2692 {
f4a9eadc 2693 dst_offset += 2;
2694 last_shift = 8;
173e37ab 2695 }
2696 }
f4a9eadc 2697 else
2698 last_shift = 24;
2699
2700 if (bytes > 0)
2701 {
76dad66d 2702 my_operands[0] = operands[6];
f4a9eadc 2703 my_operands[1] = GEN_INT (last_shift);
2704 output_asm_insn ("srai\t%0, #%1", my_operands);
76dad66d 2705 my_operands[0] = operands[6];
f4a9eadc 2706 my_operands[1] = GEN_INT (dst_offset);
2707 my_operands[2] = operands[0];
2708 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2709 }
76dad66d 2710
2711 /* Update the destination pointer if needed. We have to do
2712 this so that the patterns matches what we output in this
2713 function. */
2714 if (dst_inc_amount
2715 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2716 {
2717 my_operands[0] = operands[0];
2718 my_operands[1] = GEN_INT (dst_inc_amount);
2719 output_asm_insn ("addi\t%0, #%1", my_operands);
2720 }
58f4ce52 2721
76dad66d 2722 /* Update the source pointer if needed. We have to do this
2723 so that the patterns matches what we output in this
2724 function. */
2725 if (src_inc_amount
2726 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2727 {
2728 my_operands[0] = operands[1];
2729 my_operands[1] = GEN_INT (src_inc_amount);
2730 output_asm_insn ("addi\t%0, #%1", my_operands);
2731 }
58f4ce52 2732
173e37ab 2733 bytes = 0;
2734 }
2735
2736 first_time = 0;
2737 }
173e37ab 2738}
2739
d741027b 2740/* Return true if using NEW_REG in place of OLD_REG is ok. */
2741
2742int
aea2fd96 2743m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2744 unsigned int new_reg)
d741027b 2745{
2746 /* Interrupt routines can't clobber any register that isn't already used. */
2747 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
3072d30e 2748 && !df_regs_ever_live_p (new_reg))
d741027b 2749 return 0;
2750
d741027b 2751 return 1;
2752}
6440ef45 2753
2754rtx
2755m32r_return_addr (int count)
2756{
2757 if (count != 0)
2758 return const0_rtx;
58f4ce52 2759
6440ef45 2760 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2761}
06b77609 2762
2763static void
2764m32r_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2765{
2766 emit_move_insn (adjust_address (m_tramp, SImode, 0),
2767 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2768 0x017e8e17 : 0x178e7e01, SImode));
2769 emit_move_insn (adjust_address (m_tramp, SImode, 4),
2770 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2771 0x0c00ae86 : 0x86ae000c, SImode));
2772 emit_move_insn (adjust_address (m_tramp, SImode, 8),
2773 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2774 0xe627871e : 0x1e8727e6, SImode));
2775 emit_move_insn (adjust_address (m_tramp, SImode, 12),
2776 gen_int_mode (TARGET_LITTLE_ENDIAN ?
2777 0xc616c626 : 0x26c61fc6, SImode));
2778 emit_move_insn (adjust_address (m_tramp, SImode, 16),
2779 chain_value);
2780 emit_move_insn (adjust_address (m_tramp, SImode, 20),
2781 XEXP (DECL_RTL (fndecl), 0));
2782
2783 if (m32r_cache_flush_trap >= 0)
2784 emit_insn (gen_flush_icache
2785 (validize_mem (adjust_address (m_tramp, SImode, 0)),
2786 gen_int_mode (m32r_cache_flush_trap, SImode)));
2787 else if (m32r_cache_flush_func && m32r_cache_flush_func[0])
2788 emit_library_call (m32r_function_symbol (m32r_cache_flush_func),
2789 LCT_NORMAL, VOIDmode, 3, XEXP (m_tramp, 0), Pmode,
2790 gen_int_mode (TRAMPOLINE_SIZE, SImode), SImode,
2791 GEN_INT (3), SImode);
2792}
b2d7ede1 2793
bb10104e 2794/* True if X is a reg that can be used as a base reg. */
2795
2796static bool
2797m32r_rtx_ok_for_base_p (const_rtx x, bool strict)
2798{
2799 if (! REG_P (x))
2800 return false;
2801
2802 if (strict)
2803 {
2804 if (GPR_P (REGNO (x)))
2805 return true;
2806 }
2807 else
2808 {
2809 if (GPR_P (REGNO (x))
2810 || REGNO (x) == ARG_POINTER_REGNUM
2811 || ! HARD_REGISTER_P (x))
2812 return true;
2813 }
2814
2815 return false;
2816}
2817
2818static inline bool
2819m32r_rtx_ok_for_offset_p (const_rtx x)
2820{
2821 return (CONST_INT_P (x) && INT16_P (INTVAL (x)));
2822}
2823
2824static inline bool
2825m32r_legitimate_offset_addres_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2826 const_rtx x, bool strict)
2827{
2828 if (GET_CODE (x) == PLUS
2829 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
2830 && m32r_rtx_ok_for_offset_p (XEXP (x, 1)))
2831 return true;
2832
2833 return false;
2834}
2835
2836/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2837 since more than one instruction will be required. */
2838
2839static inline bool
2840m32r_legitimate_lo_sum_addres_p (enum machine_mode mode, const_rtx x,
2841 bool strict)
2842{
2843 if (GET_CODE (x) == LO_SUM
2844 && (mode != BLKmode && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
2845 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
2846 && CONSTANT_P (XEXP (x, 1)))
2847 return true;
2848
2849 return false;
2850}
2851
2852/* Is this a load and increment operation. */
2853
2854static inline bool
2855m32r_load_postinc_p (enum machine_mode mode, const_rtx x, bool strict)
2856{
2857 if ((mode == SImode || mode == SFmode)
2858 && GET_CODE (x) == POST_INC
2859 && REG_P (XEXP (x, 0))
2860 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
2861 return true;
2862
2863 return false;
2864}
2865
2866/* Is this an increment/decrement and store operation. */
2867
2868static inline bool
2869m32r_store_preinc_predec_p (enum machine_mode mode, const_rtx x, bool strict)
2870{
2871 if ((mode == SImode || mode == SFmode)
2872 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
2873 && REG_P (XEXP (x, 0)) \
2874 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
2875 return true;
2876
2877 return false;
2878}
2879
2880/* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2881
2882static bool
2883m32r_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
2884{
2885 if (m32r_rtx_ok_for_base_p (x, strict)
2886 || m32r_legitimate_offset_addres_p (mode, x, strict)
2887 || m32r_legitimate_lo_sum_addres_p (mode, x, strict)
2888 || m32r_load_postinc_p (mode, x, strict)
2889 || m32r_store_preinc_predec_p (mode, x, strict))
2890 return true;
2891
2892 return false;
2893}
2894
b2d7ede1 2895static void
2896m32r_conditional_register_usage (void)
2897{
2898 if (flag_pic)
2899 {
2900 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2901 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2902 }
2903}
ca316360 2904
2905/* Implement TARGET_LEGITIMATE_CONSTANT_P
2906
2907 We don't allow (plus symbol large-constant) as the relocations can't
2908 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2909 We allow all CONST_DOUBLE's as the md file patterns will force the
2910 constant to memory if they can't handle them. */
2911
2912static bool
2913m32r_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2914{
2915 return !(GET_CODE (x) == CONST
2916 && GET_CODE (XEXP (x, 0)) == PLUS
2917 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2918 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
2919 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
2920 && UINTVAL (XEXP (XEXP (x, 0), 1)) > 32767);
2921}
Mirror of https://gcc.gnu.org/git/gcc.git