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1f92da87 | 1 | /* Definitions of target machine for GNU compiler, Renesas M32R cpu. |
7adcbafe | 2 | Copyright (C) 1996-2022 Free Software Foundation, Inc. |
8c5ca3b9 | 3 | |
1f92da87 | 4 | This file is part of GCC. |
8c5ca3b9 | 5 | |
1f92da87 NC |
6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 8 | by the Free Software Foundation; either version 3, or (at your |
1f92da87 | 9 | option) any later version. |
8c5ca3b9 | 10 | |
1f92da87 NC |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
8c5ca3b9 | 15 | |
1f92da87 | 16 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
8c5ca3b9 DE |
19 | |
20 | /* Things to do: | |
21 | - longlong.h? | |
22 | */ | |
23 | ||
8c5ca3b9 DE |
24 | #undef SIZE_TYPE |
25 | #undef PTRDIFF_TYPE | |
26 | #undef WCHAR_TYPE | |
27 | #undef WCHAR_TYPE_SIZE | |
56e2e762 NC |
28 | #undef CPP_SPEC |
29 | #undef ASM_SPEC | |
30 | #undef LINK_SPEC | |
31 | #undef STARTFILE_SPEC | |
32 | #undef ENDFILE_SPEC | |
ad126521 KI |
33 | |
34 | #undef ASM_APP_ON | |
35 | #undef ASM_APP_OFF | |
8c5ca3b9 | 36 | \f |
de41e41c BE |
37 | |
38 | /* M32R/X overrides. */ | |
de41e41c BE |
39 | |
40 | /* Additional flags for the preprocessor. */ | |
6975bd2c KI |
41 | #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ |
42 | %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ | |
43 | %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ | |
44 | " | |
45 | ||
de41e41c BE |
46 | /* Assembler switches. */ |
47 | #define ASM_CPU_SPEC \ | |
6975bd2c | 48 | "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" |
de41e41c BE |
49 | |
50 | /* Use m32rx specific crt0/crtinit/crtfini files. */ | |
51 | #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" | |
52 | #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" | |
53 | ||
de41e41c BE |
54 | /* Define this macro as a C expression for the initializer of an array of |
55 | strings to tell the driver program which options are defaults for this | |
56 | target and thus do not need to be handled specially when using | |
57 | `MULTILIB_OPTIONS'. */ | |
58 | #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" | |
59 | ||
60 | /* Number of additional registers the subtarget defines. */ | |
61 | #define SUBTARGET_NUM_REGISTERS 1 | |
62 | ||
63 | /* 1 for registers that cannot be allocated. */ | |
64 | #define SUBTARGET_FIXED_REGISTERS , 1 | |
65 | ||
66 | /* 1 for registers that are not available across function calls. */ | |
67 | #define SUBTARGET_CALL_USED_REGISTERS , 1 | |
68 | ||
69 | /* Order to allocate model specific registers. */ | |
70 | #define SUBTARGET_REG_ALLOC_ORDER , 19 | |
71 | ||
72 | /* Registers which are accumulators. */ | |
73 | #define SUBTARGET_REG_CLASS_ACCUM 0x80000 | |
74 | ||
75 | /* All registers added. */ | |
76 | #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM | |
77 | ||
78 | /* Additional accumulator registers. */ | |
79 | #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) | |
80 | ||
81 | /* Define additional register names. */ | |
82 | #define SUBTARGET_REGISTER_NAMES , "a1" | |
83 | /* end M32R/X overrides. */ | |
84 | ||
8c5ca3b9 DE |
85 | /* Names to predefine in the preprocessor for this target machine. */ |
86 | /* __M32R__ is defined by the existing compiler so we use that. */ | |
cc956ba2 NB |
87 | #define TARGET_CPU_CPP_BUILTINS() \ |
88 | do \ | |
89 | { \ | |
90 | builtin_define ("__M32R__"); \ | |
df68f43b | 91 | builtin_define ("__m32r__"); \ |
cc956ba2 NB |
92 | builtin_assert ("cpu=m32r"); \ |
93 | builtin_assert ("machine=m32r"); \ | |
ad126521 KI |
94 | builtin_define (TARGET_BIG_ENDIAN \ |
95 | ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ | |
cc956ba2 NB |
96 | } \ |
97 | while (0) | |
8c5ca3b9 | 98 | |
56e2e762 NC |
99 | /* This macro defines names of additional specifications to put in the specs |
100 | that can be used in various specifications like CC1_SPEC. Its definition | |
101 | is an initializer with a subgrouping for each command option. | |
8c5ca3b9 | 102 | |
56e2e762 | 103 | Each subgrouping contains a string constant, that defines the |
7ec022b2 | 104 | specification name, and a string constant that used by the GCC driver |
56e2e762 | 105 | program. |
8c5ca3b9 | 106 | |
56e2e762 | 107 | Do not define this macro if it does not need to do anything. */ |
2b7972b0 | 108 | |
56e2e762 NC |
109 | #ifndef SUBTARGET_EXTRA_SPECS |
110 | #define SUBTARGET_EXTRA_SPECS | |
8c5ca3b9 DE |
111 | #endif |
112 | ||
56e2e762 NC |
113 | #ifndef ASM_CPU_SPEC |
114 | #define ASM_CPU_SPEC "" | |
115 | #endif | |
8c5ca3b9 | 116 | |
56e2e762 NC |
117 | #ifndef CPP_CPU_SPEC |
118 | #define CPP_CPU_SPEC "" | |
119 | #endif | |
120 | ||
121 | #ifndef CC1_CPU_SPEC | |
122 | #define CC1_CPU_SPEC "" | |
123 | #endif | |
124 | ||
125 | #ifndef LINK_CPU_SPEC | |
126 | #define LINK_CPU_SPEC "" | |
127 | #endif | |
128 | ||
129 | #ifndef STARTFILE_CPU_SPEC | |
130 | #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" | |
131 | #endif | |
132 | ||
133 | #ifndef ENDFILE_CPU_SPEC | |
134 | #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" | |
135 | #endif | |
136 | ||
137 | #ifndef RELAX_SPEC | |
ad126521 | 138 | #if 0 /* Not supported yet. */ |
56e2e762 | 139 | #define RELAX_SPEC "%{mrelax:-relax}" |
8c5ca3b9 | 140 | #else |
56e2e762 NC |
141 | #define RELAX_SPEC "" |
142 | #endif | |
8c5ca3b9 DE |
143 | #endif |
144 | ||
56e2e762 NC |
145 | #define EXTRA_SPECS \ |
146 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
147 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
148 | { "cc1_cpu", CC1_CPU_SPEC }, \ | |
149 | { "link_cpu", LINK_CPU_SPEC }, \ | |
150 | { "startfile_cpu", STARTFILE_CPU_SPEC }, \ | |
151 | { "endfile_cpu", ENDFILE_CPU_SPEC }, \ | |
152 | { "relax", RELAX_SPEC }, \ | |
153 | SUBTARGET_EXTRA_SPECS | |
8c5ca3b9 | 154 | |
2a2001be IK |
155 | #define CPP_SPEC "%(cpp_cpu)" |
156 | ||
ad126521 | 157 | #undef CC1_SPEC |
56e2e762 | 158 | #define CC1_SPEC "%{G*} %(cc1_cpu)" |
2b7972b0 | 159 | |
56e2e762 NC |
160 | /* Options to pass on to the assembler. */ |
161 | #undef ASM_SPEC | |
428b3812 | 162 | #define ASM_SPEC "%(asm_cpu) %(relax) %{" FPIE_OR_FPIC_SPEC ":-K PIC}" |
56e2e762 | 163 | |
56e2e762 NC |
164 | #define LINK_SPEC "%{v} %(link_cpu) %(relax)" |
165 | ||
166 | #undef STARTFILE_SPEC | |
167 | #define STARTFILE_SPEC "%(startfile_cpu)" | |
168 | ||
169 | #undef ENDFILE_SPEC | |
170 | #define ENDFILE_SPEC "%(endfile_cpu)" | |
8c5ca3b9 DE |
171 | |
172 | #undef LIB_SPEC | |
173 | \f | |
174 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
175 | ||
6975bd2c KI |
176 | #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) |
177 | ||
97b73103 RS |
178 | #ifndef TARGET_LITTLE_ENDIAN |
179 | #define TARGET_LITTLE_ENDIAN 0 | |
8a897efe | 180 | #endif |
97b73103 | 181 | #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) |
8a897efe KI |
182 | |
183 | /* This defaults us to m32r. */ | |
184 | #ifndef TARGET_CPU_DEFAULT | |
185 | #define TARGET_CPU_DEFAULT 0 | |
ad126521 KI |
186 | #endif |
187 | ||
8a784afb JM |
188 | #ifndef M32R_OPTS_H |
189 | #include "config/m32r/m32r-opts.h" | |
56e2e762 | 190 | #endif |
8c5ca3b9 DE |
191 | |
192 | /* Define this macro as a C expression for the initializer of an array of | |
2b7972b0 | 193 | strings to tell the driver program which options are defaults for this |
8c5ca3b9 DE |
194 | target and thus do not need to be handled specially when using |
195 | `MULTILIB_OPTIONS'. */ | |
56e2e762 NC |
196 | #ifndef SUBTARGET_MULTILIB_DEFAULTS |
197 | #define SUBTARGET_MULTILIB_DEFAULTS | |
198 | #endif | |
199 | ||
200 | #ifndef MULTILIB_DEFAULTS | |
201 | #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } | |
202 | #endif | |
8c5ca3b9 | 203 | |
56e2e762 NC |
204 | #ifndef SUBTARGET_OVERRIDE_OPTIONS |
205 | #define SUBTARGET_OVERRIDE_OPTIONS | |
206 | #endif | |
8c5ca3b9 DE |
207 | \f |
208 | /* Target machine storage layout. */ | |
209 | ||
8c5ca3b9 DE |
210 | /* Define this if most significant bit is lowest numbered |
211 | in instructions that operate on numbered bit-fields. */ | |
212 | #define BITS_BIG_ENDIAN 1 | |
213 | ||
214 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
ad126521 | 215 | #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
8c5ca3b9 DE |
216 | |
217 | /* Define this if most significant word of a multiword number is the lowest | |
218 | numbered. */ | |
ad126521 | 219 | #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
8c5ca3b9 | 220 | |
8c5ca3b9 DE |
221 | /* Width of a word, in units (bytes). */ |
222 | #define UNITS_PER_WORD 4 | |
223 | ||
224 | /* Define this macro if it is advisable to hold scalars in registers | |
225 | in a wider mode than that declared by the program. In such cases, | |
226 | the value is constrained to be within the bounds of the declared | |
227 | type, but kept valid in the wider mode. The signedness of the | |
228 | extension may differ from that of the type. */ | |
56e2e762 NC |
229 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
230 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
231 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
232 | { \ | |
233 | (MODE) = SImode; \ | |
234 | } | |
8c5ca3b9 | 235 | |
8c5ca3b9 DE |
236 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
237 | #define PARM_BOUNDARY 32 | |
238 | ||
239 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
240 | #define STACK_BOUNDARY 32 | |
241 | ||
242 | /* ALIGN FRAMES on word boundaries */ | |
ad126521 | 243 | #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) |
8c5ca3b9 DE |
244 | |
245 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
246 | #define FUNCTION_BOUNDARY 32 | |
247 | ||
248 | /* Alignment of field after `int : 0' in a structure. */ | |
249 | #define EMPTY_FIELD_BOUNDARY 32 | |
250 | ||
251 | /* Every structure's size must be a multiple of this. */ | |
252 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
253 | ||
43a88a8c | 254 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
8c5ca3b9 DE |
255 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
256 | ||
257 | /* No data type wants to be aligned rounder than this. */ | |
258 | #define BIGGEST_ALIGNMENT 32 | |
259 | ||
260 | /* The best alignment to use in cases where we have a choice. */ | |
261 | #define FASTEST_ALIGNMENT 32 | |
262 | ||
8c5ca3b9 | 263 | /* Make arrays of chars word-aligned for the same reasons. */ |
56e2e762 NC |
264 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
265 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
266 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
8c5ca3b9 DE |
267 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
268 | ||
269 | /* Set this nonzero if move instructions will actually fail to work | |
270 | when given unaligned data. */ | |
271 | #define STRICT_ALIGNMENT 1 | |
ad126521 KI |
272 | |
273 | /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ | |
274 | #define LABEL_ALIGN(insn) 2 | |
8c5ca3b9 DE |
275 | \f |
276 | /* Layout of source language data types. */ | |
277 | ||
278 | #define SHORT_TYPE_SIZE 16 | |
279 | #define INT_TYPE_SIZE 32 | |
280 | #define LONG_TYPE_SIZE 32 | |
281 | #define LONG_LONG_TYPE_SIZE 64 | |
282 | #define FLOAT_TYPE_SIZE 32 | |
283 | #define DOUBLE_TYPE_SIZE 64 | |
284 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
285 | ||
286 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
287 | #define DEFAULT_SIGNED_CHAR 1 | |
288 | ||
289 | #define SIZE_TYPE "long unsigned int" | |
290 | #define PTRDIFF_TYPE "long int" | |
291 | #define WCHAR_TYPE "short unsigned int" | |
292 | #define WCHAR_TYPE_SIZE 16 | |
8c5ca3b9 DE |
293 | \f |
294 | /* Standard register usage. */ | |
295 | ||
296 | /* Number of actual hardware registers. | |
297 | The hardware registers are assigned numbers for the compiler | |
298 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
299 | All registers that the compiler knows about must be given numbers, | |
300 | even those that are not normally considered general registers. */ | |
56e2e762 NC |
301 | |
302 | #define M32R_NUM_REGISTERS 19 | |
303 | ||
304 | #ifndef SUBTARGET_NUM_REGISTERS | |
305 | #define SUBTARGET_NUM_REGISTERS 0 | |
306 | #endif | |
307 | ||
308 | #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) | |
2b7972b0 | 309 | |
8c5ca3b9 DE |
310 | /* 1 for registers that have pervasive standard uses |
311 | and are not available for the register allocator. | |
312 | ||
313 | 0-3 - arguments/results | |
314 | 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] | |
315 | 6 - call used, gptmp | |
316 | 7 - call used, static chain pointer | |
317 | 8-11 - call saved | |
318 | 12 - call saved [reserved for global pointer] | |
319 | 13 - frame pointer | |
320 | 14 - subroutine link register | |
321 | 15 - stack pointer | |
322 | 16 - arg pointer | |
323 | 17 - carry flag | |
56e2e762 | 324 | 18 - accumulator |
de41e41c | 325 | 19 - accumulator 1 in the m32r/x |
8c5ca3b9 DE |
326 | By default, the extension registers are not available. */ |
327 | ||
56e2e762 NC |
328 | #ifndef SUBTARGET_FIXED_REGISTERS |
329 | #define SUBTARGET_FIXED_REGISTERS | |
330 | #endif | |
8c5ca3b9 | 331 | |
56e2e762 NC |
332 | #define FIXED_REGISTERS \ |
333 | { \ | |
334 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
335 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
336 | 1, 1, 1 \ | |
337 | SUBTARGET_FIXED_REGISTERS \ | |
338 | } | |
2b7972b0 | 339 | |
8c5ca3b9 DE |
340 | /* 1 for registers not available across function calls. |
341 | These must include the FIXED_REGISTERS and also any | |
342 | registers that can be used without being saved. | |
343 | The latter must include the registers where values are returned | |
344 | and the register where structure-value addresses are passed. | |
345 | Aside from that, you can include as many other registers as you like. */ | |
346 | ||
56e2e762 NC |
347 | #ifndef SUBTARGET_CALL_USED_REGISTERS |
348 | #define SUBTARGET_CALL_USED_REGISTERS | |
349 | #endif | |
8c5ca3b9 | 350 | |
d7fb4c31 | 351 | #define CALL_REALLY_USED_REGISTERS \ |
56e2e762 NC |
352 | { \ |
353 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
354 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
355 | 1, 1, 1 \ | |
356 | SUBTARGET_CALL_USED_REGISTERS \ | |
357 | } | |
2b7972b0 | 358 | |
8c5ca3b9 | 359 | /* If defined, an initializer for a vector of integers, containing the |
7ec022b2 | 360 | numbers of hard registers in the order in which GCC should |
8c5ca3b9 | 361 | prefer to use them (from most preferred to least). */ |
56e2e762 NC |
362 | |
363 | #ifndef SUBTARGET_REG_ALLOC_ORDER | |
364 | #define SUBTARGET_REG_ALLOC_ORDER | |
365 | #endif | |
366 | ||
ad126521 | 367 | #if 1 /* Better for int code. */ |
56e2e762 NC |
368 | #define REG_ALLOC_ORDER \ |
369 | { \ | |
370 | 4, 5, 6, 7, 2, 3, 8, 9, 10, \ | |
371 | 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ | |
372 | SUBTARGET_REG_ALLOC_ORDER \ | |
373 | } | |
374 | ||
ad126521 | 375 | #else /* Better for fp code at expense of int code. */ |
56e2e762 NC |
376 | #define REG_ALLOC_ORDER \ |
377 | { \ | |
378 | 0, 1, 2, 3, 4, 5, 6, 7, 8, \ | |
379 | 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ | |
380 | SUBTARGET_REG_ALLOC_ORDER \ | |
381 | } | |
8c5ca3b9 DE |
382 | #endif |
383 | ||
a398a822 KI |
384 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ |
385 | m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
8c5ca3b9 DE |
386 | \f |
387 | /* Register classes and constants. */ | |
388 | ||
389 | /* Define the classes of registers for register constraints in the | |
390 | machine description. Also define ranges of constants. | |
391 | ||
392 | One of the classes must always be named ALL_REGS and include all hard regs. | |
393 | If there is more than one class, another class must be named NO_REGS | |
394 | and contain no registers. | |
395 | ||
396 | The name GENERAL_REGS must be the name of a class (or an alias for | |
397 | another name such as ALL_REGS). This is the class of registers | |
398 | that is allowed by "g" or "r" in a register constraint. | |
399 | Also, registers outside this class are allocated only when | |
400 | instructions express preferences for them. | |
401 | ||
402 | The classes must be numbered in nondecreasing order; that is, | |
403 | a larger-numbered class must never be contained completely | |
404 | in a smaller-numbered class. | |
405 | ||
406 | For any two classes, it is very desirable that there be another | |
407 | class that represents their union. | |
408 | ||
409 | It is important that any condition codes have class NO_REGS. | |
410 | See `register_operand'. */ | |
411 | ||
56e2e762 NC |
412 | enum reg_class |
413 | { | |
414 | NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES | |
8c5ca3b9 DE |
415 | }; |
416 | ||
56e2e762 | 417 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
8c5ca3b9 | 418 | |
71cc389b | 419 | /* Give names of register classes as strings for dump file. */ |
8c5ca3b9 | 420 | #define REG_CLASS_NAMES \ |
56e2e762 | 421 | { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } |
8c5ca3b9 DE |
422 | |
423 | /* Define which registers fit in which classes. | |
424 | This is an initializer for a vector of HARD_REG_SET | |
425 | of length N_REG_CLASSES. */ | |
426 | ||
56e2e762 NC |
427 | #ifndef SUBTARGET_REG_CLASS_CARRY |
428 | #define SUBTARGET_REG_CLASS_CARRY 0 | |
429 | #endif | |
430 | ||
431 | #ifndef SUBTARGET_REG_CLASS_ACCUM | |
432 | #define SUBTARGET_REG_CLASS_ACCUM 0 | |
433 | #endif | |
434 | ||
435 | #ifndef SUBTARGET_REG_CLASS_GENERAL | |
436 | #define SUBTARGET_REG_CLASS_GENERAL 0 | |
437 | #endif | |
438 | ||
439 | #ifndef SUBTARGET_REG_CLASS_ALL | |
440 | #define SUBTARGET_REG_CLASS_ALL 0 | |
441 | #endif | |
8c5ca3b9 | 442 | |
56e2e762 NC |
443 | #define REG_CLASS_CONTENTS \ |
444 | { \ | |
445 | { 0x00000 }, \ | |
446 | { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ | |
447 | { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ | |
448 | { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ | |
449 | { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ | |
450 | } | |
2b7972b0 | 451 | |
8c5ca3b9 DE |
452 | /* The same information, inverted: |
453 | Return the class number of the smallest class containing | |
454 | reg number REGNO. This could be a conditional expression | |
455 | or could index an array. */ | |
2b7972b0 | 456 | extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
56e2e762 | 457 | #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) |
8c5ca3b9 DE |
458 | |
459 | /* The class value for index registers, and the one for base regs. */ | |
460 | #define INDEX_REG_CLASS GENERAL_REGS | |
461 | #define BASE_REG_CLASS GENERAL_REGS | |
462 | ||
8c5ca3b9 DE |
463 | /* These assume that REGNO is a hard or pseudo reg number. |
464 | They give nonzero only if REGNO is a hard reg of the suitable class | |
465 | or a pseudo reg currently allocated to a suitable hard reg. | |
466 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
467 | has been allocated, which happens in reginfo.c during register |
468 | allocation. */ | |
8c5ca3b9 | 469 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
ad126521 KI |
470 | ((REGNO) < FIRST_PSEUDO_REGISTER \ |
471 | ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ | |
472 | : GPR_P (reg_renumber[REGNO])) | |
473 | ||
8c5ca3b9 DE |
474 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) |
475 | ||
56e2e762 | 476 | /* Return true if a value is inside a range. */ |
fbaeb717 KK |
477 | #define IN_RANGE_P(VALUE, LOW, HIGH) \ |
478 | (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ | |
56e2e762 NC |
479 | <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) |
480 | ||
fbaeb717 | 481 | /* Some range macros. */ |
ad126521 KI |
482 | #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) |
483 | #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) | |
ad126521 KI |
484 | #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) |
485 | #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) | |
8c5ca3b9 DE |
486 | \f |
487 | /* Stack layout and stack pointer usage. */ | |
488 | ||
489 | /* Define this macro if pushing a word onto the stack moves the stack | |
490 | pointer to a smaller address. */ | |
62f9f30b | 491 | #define STACK_GROWS_DOWNWARD 1 |
8c5ca3b9 | 492 | |
8c5ca3b9 DE |
493 | /* Offset from the stack pointer register to the first location at which |
494 | outgoing arguments are placed. */ | |
495 | #define STACK_POINTER_OFFSET 0 | |
496 | ||
497 | /* Offset of first parameter from the argument pointer register value. */ | |
498 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
499 | ||
8c5ca3b9 DE |
500 | /* Register to use for pushing function arguments. */ |
501 | #define STACK_POINTER_REGNUM 15 | |
502 | ||
503 | /* Base register for access to local variables of the function. */ | |
504 | #define FRAME_POINTER_REGNUM 13 | |
505 | ||
506 | /* Base register for access to arguments of the function. */ | |
507 | #define ARG_POINTER_REGNUM 16 | |
508 | ||
ad126521 KI |
509 | /* Register in which static-chain is passed to a function. |
510 | This must not be a register used by the prologue. */ | |
511 | #define STATIC_CHAIN_REGNUM 7 | |
8c5ca3b9 DE |
512 | |
513 | /* These aren't official macros. */ | |
ad126521 KI |
514 | #define PROLOGUE_TMP_REGNUM 4 |
515 | #define RETURN_ADDR_REGNUM 14 | |
516 | /* #define GP_REGNUM 12 */ | |
517 | #define CARRY_REGNUM 17 | |
518 | #define ACCUM_REGNUM 18 | |
519 | #define M32R_MAX_INT_REGS 16 | |
8c5ca3b9 | 520 | |
56e2e762 NC |
521 | #ifndef SUBTARGET_GPR_P |
522 | #define SUBTARGET_GPR_P(REGNO) 0 | |
523 | #endif | |
524 | ||
525 | #ifndef SUBTARGET_ACCUM_P | |
526 | #define SUBTARGET_ACCUM_P(REGNO) 0 | |
527 | #endif | |
528 | ||
529 | #ifndef SUBTARGET_CARRY_P | |
530 | #define SUBTARGET_CARRY_P(REGNO) 0 | |
531 | #endif | |
532 | ||
533 | #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) | |
534 | #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) | |
535 | #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) | |
8c5ca3b9 DE |
536 | \f |
537 | /* Eliminating the frame and arg pointers. */ | |
538 | ||
8c5ca3b9 DE |
539 | /* If defined, this macro specifies a table of register pairs used to |
540 | eliminate unneeded registers that point into the stack frame. If | |
541 | it is not defined, the only elimination attempted by the compiler | |
542 | is to replace references to the frame pointer with references to | |
543 | the stack pointer. | |
544 | ||
545 | Note that the elimination of the argument pointer with the stack | |
546 | pointer is specified first since that is the preferred elimination. */ | |
547 | ||
56e2e762 NC |
548 | #define ELIMINABLE_REGS \ |
549 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
550 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
551 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} | |
8c5ca3b9 | 552 | |
53680238 BE |
553 | /* This macro returns the initial difference between the specified pair |
554 | of registers. */ | |
8c5ca3b9 | 555 | |
ad126521 KI |
556 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
557 | do \ | |
558 | { \ | |
559 | int size = m32r_compute_frame_size (get_frame_size ()); \ | |
560 | \ | |
561 | if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
562 | (OFFSET) = 0; \ | |
563 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
38173d38 | 564 | (OFFSET) = size - crtl->args.pretend_args_size; \ |
ad126521 | 565 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ |
38173d38 | 566 | (OFFSET) = size - crtl->args.pretend_args_size; \ |
ad126521 | 567 | else \ |
75c3cfba | 568 | gcc_unreachable (); \ |
ad126521 KI |
569 | } \ |
570 | while (0) | |
8c5ca3b9 DE |
571 | \f |
572 | /* Function argument passing. */ | |
573 | ||
8c5ca3b9 DE |
574 | /* If defined, the maximum amount of space required for outgoing |
575 | arguments will be computed and placed into the variable | |
38173d38 | 576 | `crtl->outgoing_args_size'. No space will be pushed |
8c5ca3b9 DE |
577 | onto the stack for each call; instead, the function prologue should |
578 | increase the stack frame size by this amount. */ | |
f73ad30e | 579 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8c5ca3b9 | 580 | |
8c5ca3b9 DE |
581 | /* Define a data type for recording info about an argument list |
582 | during the scan of that argument list. This data type should | |
583 | hold all necessary information about the function itself | |
584 | and about the args processed so far, enough to enable macros | |
585 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
586 | #define CUMULATIVE_ARGS int | |
587 | ||
588 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
589 | for a call to a function whose data type is FNTYPE. | |
590 | For a library call, FNTYPE is 0. */ | |
0f6937fe | 591 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
56e2e762 | 592 | ((CUM) = 0) |
8c5ca3b9 DE |
593 | |
594 | /* The number of registers used for parameter passing. Local to this file. */ | |
595 | #define M32R_MAX_PARM_REGS 4 | |
596 | ||
597 | /* 1 if N is a possible register number for function argument passing. */ | |
598 | #define FUNCTION_ARG_REGNO_P(N) \ | |
56e2e762 | 599 | ((unsigned) (N) < M32R_MAX_PARM_REGS) |
8c5ca3b9 | 600 | |
8c5ca3b9 DE |
601 | \f |
602 | /* Function results. */ | |
603 | ||
bd5bd7ac | 604 | /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ |
8c5ca3b9 | 605 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
8c5ca3b9 DE |
606 | \f |
607 | /* Function entry and exit. */ | |
608 | ||
609 | /* Initialize data used by insn expanders. This is called from | |
610 | init_emit, once for each function, before code is generated. */ | |
611 | #define INIT_EXPANDERS m32r_init_expanders () | |
612 | ||
8c5ca3b9 DE |
613 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
614 | the stack pointer does not matter. The value is tested only in | |
615 | functions that have frame pointers. | |
616 | No definition is equivalent to always zero. */ | |
617 | #define EXIT_IGNORE_STACK 1 | |
618 | ||
8c5ca3b9 DE |
619 | /* Output assembler code to FILE to increment profiler label # LABELNO |
620 | for profiling a function entry. */ | |
ad126521 KI |
621 | #undef FUNCTION_PROFILER |
622 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
623 | do \ | |
624 | { \ | |
625 | if (flag_pic) \ | |
626 | { \ | |
627 | fprintf (FILE, "\tld24 r14,#mcount\n"); \ | |
628 | fprintf (FILE, "\tadd r14,r12\n"); \ | |
629 | fprintf (FILE, "\tld r14,@r14\n"); \ | |
630 | fprintf (FILE, "\tjl r14\n"); \ | |
631 | } \ | |
632 | else \ | |
633 | { \ | |
634 | if (TARGET_ADDR24) \ | |
635 | fprintf (FILE, "\tbl mcount\n"); \ | |
636 | else \ | |
637 | { \ | |
638 | fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ | |
639 | fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ | |
640 | fprintf (FILE, "\tjl r14\n"); \ | |
641 | } \ | |
642 | } \ | |
643 | fprintf (FILE, "\taddi sp,#4\n"); \ | |
644 | } \ | |
645 | while (0) | |
8c5ca3b9 DE |
646 | \f |
647 | /* Trampolines. */ | |
648 | ||
ad126521 | 649 | /* On the M32R, the trampoline is: |
8c5ca3b9 | 650 | |
ad126521 KI |
651 | mv r7, lr -> bl L1 ; 178e 7e01 |
652 | L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) | |
653 | mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 | |
654 | ld r6, @r6 -> jmp r6 ; 26c6 1fc6 | |
655 | L2: .word STATIC | |
656 | .word FUNCTION */ | |
8c5ca3b9 | 657 | |
ad126521 KI |
658 | #ifndef CACHE_FLUSH_FUNC |
659 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
660 | #endif | |
661 | #ifndef CACHE_FLUSH_TRAP | |
97b73103 | 662 | #define CACHE_FLUSH_TRAP 12 |
ad126521 | 663 | #endif |
8c5ca3b9 DE |
664 | |
665 | /* Length in bytes of the trampoline for entering a nested function. */ | |
f26ef713 | 666 | #define TRAMPOLINE_SIZE 24 |
8c5ca3b9 | 667 | |
8c5ca3b9 | 668 | \f |
7b14411a KI |
669 | #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) |
670 | ||
671 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) | |
672 | ||
8c5ca3b9 DE |
673 | /* Addressing modes, and classification of registers for them. */ |
674 | ||
675 | /* Maximum number of registers that can appear in a valid memory address. */ | |
676 | #define MAX_REGS_PER_ADDRESS 1 | |
677 | ||
678 | /* We have post-inc load and pre-dec,pre-inc store, | |
679 | but only for 4 byte vals. */ | |
ad126521 KI |
680 | #define HAVE_PRE_DECREMENT 1 |
681 | #define HAVE_PRE_INCREMENT 1 | |
940da324 | 682 | #define HAVE_POST_INCREMENT 1 |
8c5ca3b9 DE |
683 | |
684 | /* Recognize any constant value that is a valid address. */ | |
ad126521 KI |
685 | #define CONSTANT_ADDRESS_P(X) \ |
686 | ( GET_CODE (X) == LABEL_REF \ | |
687 | || GET_CODE (X) == SYMBOL_REF \ | |
d000f0d9 | 688 | || CONST_INT_P (X) \ |
ad126521 KI |
689 | || (GET_CODE (X) == CONST \ |
690 | && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) | |
8c5ca3b9 DE |
691 | \f |
692 | /* Condition code usage. */ | |
693 | ||
a0ab749a | 694 | /* Return nonzero if SELECT_CC_MODE will never return MODE for a |
8c5ca3b9 | 695 | floating point inequality comparison. */ |
18543a22 | 696 | #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ |
8c5ca3b9 DE |
697 | \f |
698 | /* Costs. */ | |
699 | ||
8c5ca3b9 DE |
700 | /* The cost of a branch insn. */ |
701 | /* A value of 2 here causes GCC to avoid using branches in comparisons like | |
702 | while (a < N && a). Branches aren't that expensive on the M32R so | |
703 | we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ | |
3a4fd356 | 704 | #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1) |
8c5ca3b9 | 705 | |
8c5ca3b9 DE |
706 | /* Nonzero if access to memory by bytes is slow and undesirable. |
707 | For RISC chips, it means that access to memory by bytes is no | |
708 | better than access by words when possible, so grab a whole word | |
709 | and maybe make use of that. */ | |
710 | #define SLOW_BYTE_ACCESS 1 | |
711 | ||
712 | /* Define this macro if it is as good or better to call a constant | |
713 | function address than to call an address kept in a register. */ | |
1e8552c2 | 714 | #define NO_FUNCTION_CSE 1 |
8c5ca3b9 DE |
715 | \f |
716 | /* Section selection. */ | |
717 | ||
718 | #define TEXT_SECTION_ASM_OP "\t.section .text" | |
719 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
8c5ca3b9 | 720 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
8c5ca3b9 | 721 | |
8c5ca3b9 DE |
722 | /* Define this macro if jump tables (for tablejump insns) should be |
723 | output in the text section, along with the assembler instructions. | |
724 | Otherwise, the readonly data section is used. | |
725 | This macro is irrelevant if there is no separate readonly data section. */ | |
ad126521 | 726 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) |
8c5ca3b9 | 727 | \f |
ad126521 | 728 | /* Position Independent Code. */ |
8c5ca3b9 DE |
729 | |
730 | /* The register number of the register used to address a table of static | |
731 | data addresses in memory. In some cases this register is defined by a | |
732 | processor's ``application binary interface'' (ABI). When this macro | |
733 | is defined, RTL is generated for this register once, as with the stack | |
734 | pointer and frame pointer registers. If this macro is not defined, it | |
735 | is up to the machine-dependent files to allocate such a register (if | |
736 | necessary). */ | |
ad126521 | 737 | #define PIC_OFFSET_TABLE_REGNUM 12 |
8c5ca3b9 DE |
738 | |
739 | /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is | |
740 | clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM | |
741 | is not defined. */ | |
742 | /* This register is call-saved on the M32R. */ | |
743 | /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ | |
744 | ||
8c5ca3b9 DE |
745 | /* A C expression that is nonzero if X is a legitimate immediate |
746 | operand on the target machine when generating position independent code. | |
747 | You can assume that X satisfies CONSTANT_P, so you need not | |
748 | check this. You can also assume `flag_pic' is true, so you need not | |
749 | check it either. You need not define this macro if all constants | |
750 | (including SYMBOL_REF) can be immediate operands when generating | |
751 | position independent code. */ | |
ad126521 | 752 | #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) |
8c5ca3b9 DE |
753 | \f |
754 | /* Control the assembler format that we output. */ | |
755 | ||
8c5ca3b9 DE |
756 | /* A C string constant describing how to begin a comment in the target |
757 | assembler language. The compiler assumes that the comment will | |
758 | end at the end of the line. */ | |
759 | #define ASM_COMMENT_START ";" | |
760 | ||
761 | /* Output to assembler file text saying following lines | |
762 | may contain character constants, extra white space, comments, etc. */ | |
763 | #define ASM_APP_ON "" | |
764 | ||
765 | /* Output to assembler file text saying following lines | |
766 | no longer contain unusual constructs. */ | |
767 | #define ASM_APP_OFF "" | |
768 | ||
506a61b1 KG |
769 | /* Globalizing directive for a label. */ |
770 | #define GLOBAL_ASM_OP "\t.global\t" | |
8c5ca3b9 | 771 | |
8c5ca3b9 DE |
772 | /* How to refer to registers in assembler output. |
773 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
56e2e762 NC |
774 | #ifndef SUBTARGET_REGISTER_NAMES |
775 | #define SUBTARGET_REGISTER_NAMES | |
776 | #endif | |
777 | ||
778 | #define REGISTER_NAMES \ | |
8c5ca3b9 DE |
779 | { \ |
780 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
781 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ | |
56e2e762 NC |
782 | "ap", "cbit", "a0" \ |
783 | SUBTARGET_REGISTER_NAMES \ | |
8c5ca3b9 DE |
784 | } |
785 | ||
786 | /* If defined, a C initializer for an array of structures containing | |
787 | a name and a register number. This macro defines additional names | |
788 | for hard registers, thus allowing the `asm' option in declarations | |
789 | to refer to registers using alternate names. */ | |
56e2e762 NC |
790 | #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES |
791 | #define SUBTARGET_ADDITIONAL_REGISTER_NAMES | |
792 | #endif | |
793 | ||
794 | #define ADDITIONAL_REGISTER_NAMES \ | |
8c5ca3b9 DE |
795 | { \ |
796 | /*{ "gp", GP_REGNUM },*/ \ | |
797 | { "r13", FRAME_POINTER_REGNUM }, \ | |
798 | { "r14", RETURN_ADDR_REGNUM }, \ | |
799 | { "r15", STACK_POINTER_REGNUM }, \ | |
56e2e762 | 800 | SUBTARGET_ADDITIONAL_REGISTER_NAMES \ |
8c5ca3b9 DE |
801 | } |
802 | ||
8c5ca3b9 DE |
803 | /* If defined, C string expressions to be used for the `%R', `%L', |
804 | `%U', and `%I' options of `asm_fprintf' (see `final.c'). These | |
805 | are useful when a single `md' file must support multiple assembler | |
806 | formats. In that case, the various `tm.h' files can define these | |
807 | macros differently. */ | |
ad126521 KI |
808 | #define REGISTER_PREFIX "" |
809 | #define LOCAL_LABEL_PREFIX ".L" | |
810 | #define USER_LABEL_PREFIX "" | |
811 | #define IMMEDIATE_PREFIX "#" | |
8c5ca3b9 DE |
812 | |
813 | /* This is how to output an element of a case-vector that is absolute. */ | |
56e2e762 NC |
814 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
815 | do \ | |
816 | { \ | |
817 | char label[30]; \ | |
818 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
819 | fprintf (FILE, "\t.word\t"); \ | |
820 | assemble_name (FILE, label); \ | |
821 | fprintf (FILE, "\n"); \ | |
822 | } \ | |
823 | while (0) | |
8c5ca3b9 DE |
824 | |
825 | /* This is how to output an element of a case-vector that is relative. */ | |
56e2e762 NC |
826 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ |
827 | do \ | |
828 | { \ | |
829 | char label[30]; \ | |
830 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
831 | fprintf (FILE, "\t.word\t"); \ | |
832 | assemble_name (FILE, label); \ | |
833 | fprintf (FILE, "-"); \ | |
834 | ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ | |
835 | assemble_name (FILE, label); \ | |
ad126521 | 836 | fprintf (FILE, "\n"); \ |
56e2e762 NC |
837 | } \ |
838 | while (0) | |
8c5ca3b9 | 839 | |
fc470718 R |
840 | /* The desired alignment for the location counter at the beginning |
841 | of a loop. */ | |
8c5ca3b9 DE |
842 | /* On the M32R, align loops to 32 byte boundaries (cache line size) |
843 | if -malign-loops. */ | |
e6de5335 ML |
844 | #define LOOP_ALIGN(LABEL) ((TARGET_ALIGN_LOOPS \ |
845 | ? align_flags (5) : align_flags ())) | |
8c5ca3b9 | 846 | |
56e2e762 NC |
847 | /* Define this to be the maximum number of insns to move around when moving |
848 | a loop test from the top of a loop to the bottom | |
849 | and seeing whether to duplicate it. The default is thirty. | |
850 | ||
851 | Loop unrolling currently doesn't like this optimization, so | |
852 | disable doing if we are unrolling loops and saving space. */ | |
853 | #define LOOP_TEST_THRESHOLD (optimize_size \ | |
854 | && !flag_unroll_loops \ | |
855 | && !flag_unroll_all_loops ? 2 : 30) | |
856 | ||
8c5ca3b9 DE |
857 | /* This is how to output an assembler line |
858 | that says to advance the location counter | |
859 | to a multiple of 2**LOG bytes. */ | |
860 | /* .balign is used to avoid confusion. */ | |
56e2e762 NC |
861 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
862 | do \ | |
863 | { \ | |
864 | if ((LOG) != 0) \ | |
865 | fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ | |
866 | } \ | |
867 | while (0) | |
8c5ca3b9 DE |
868 | |
869 | /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a | |
870 | separate, explicit argument. If you define this macro, it is used in | |
871 | place of `ASM_OUTPUT_COMMON', and gives you more flexibility in | |
872 | handling the required alignment of the variable. The alignment is | |
873 | specified as the number of bits. */ | |
874 | ||
6e7b07a7 | 875 | #define SCOMMON_ASM_OP "\t.scomm\t" |
8c5ca3b9 | 876 | |
56e2e762 NC |
877 | #undef ASM_OUTPUT_ALIGNED_COMMON |
878 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
879 | do \ | |
8c5ca3b9 | 880 | { \ |
56e2e762 | 881 | if (! TARGET_SDATA_NONE \ |
fa37ed29 JM |
882 | && (SIZE) > 0 \ |
883 | && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ | |
016c8440 | 884 | fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ |
56e2e762 | 885 | else \ |
016c8440 | 886 | fprintf ((FILE), "%s", COMMON_ASM_OP); \ |
8c5ca3b9 | 887 | assemble_name ((FILE), (NAME)); \ |
58e15542 | 888 | fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ |
8c5ca3b9 | 889 | } \ |
56e2e762 | 890 | while (0) |
8c5ca3b9 | 891 | |
cb1f9d03 KI |
892 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
893 | do \ | |
894 | { \ | |
895 | if (! TARGET_SDATA_NONE \ | |
fa37ed29 JM |
896 | && (SIZE) > 0 \ |
897 | && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ | |
d6b5193b | 898 | switch_to_section (get_named_section (NULL, ".sbss", 0)); \ |
cb1f9d03 | 899 | else \ |
d6b5193b | 900 | switch_to_section (bss_section); \ |
cb1f9d03 KI |
901 | ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ |
902 | last_assemble_variable_decl = DECL; \ | |
903 | ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ | |
904 | ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ | |
905 | } \ | |
56e2e762 | 906 | while (0) |
8c5ca3b9 DE |
907 | \f |
908 | /* Debugging information. */ | |
909 | ||
d158c3f7 | 910 | /* Generate DWARF debugging information. */ |
23532de9 | 911 | #define DWARF2_DEBUGGING_INFO 1 |
8c5ca3b9 | 912 | |
25941194 | 913 | /* Use DWARF2 debugging info by default. */ |
56e2e762 | 914 | #undef PREFERRED_DEBUGGING_TYPE |
25941194 | 915 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
8c5ca3b9 | 916 | |
8c5ca3b9 DE |
917 | \f |
918 | /* Miscellaneous. */ | |
919 | ||
920 | /* Specify the machine mode that this machine uses | |
921 | for the index in the tablejump instruction. */ | |
ad126521 | 922 | #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) |
8c5ca3b9 | 923 | |
8c5ca3b9 DE |
924 | /* Define if operations between registers always perform the operation |
925 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 926 | #define WORD_REGISTER_OPERATIONS 1 |
8c5ca3b9 DE |
927 | |
928 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
929 | will either zero-extend or sign-extend. The value of this macro should | |
930 | be the code that says which one of the two operations is implicitly | |
f822d252 | 931 | done, UNKNOWN if none. */ |
8c5ca3b9 DE |
932 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
933 | ||
ad126521 KI |
934 | /* Max number of bytes we can move from memory |
935 | to memory in one reasonably fast instruction. */ | |
8c5ca3b9 DE |
936 | #define MOVE_MAX 4 |
937 | ||
938 | /* Define this to be nonzero if shift instructions ignore all but the low-order | |
939 | few bits. */ | |
940 | #define SHIFT_COUNT_TRUNCATED 1 | |
941 | ||
8c5ca3b9 DE |
942 | /* Specify the machine mode that pointers have. |
943 | After generation of rtl, the compiler makes no further distinction | |
944 | between pointers and any other objects of this machine mode. */ | |
85f65093 | 945 | /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has |
f3b569ca | 946 | its own problems (you have to add extendpsisi2 and truncsipsi2). |
8c5ca3b9 DE |
947 | Try to avoid it. */ |
948 | #define Pmode SImode | |
949 | ||
950 | /* A function address in a call instruction. */ | |
951 | #define FUNCTION_MODE SImode | |
8c5ca3b9 | 952 | \f |
71cc389b | 953 | /* M32R function types. */ |
2b7972b0 MM |
954 | enum m32r_function_type |
955 | { | |
8c5ca3b9 DE |
956 | M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT |
957 | }; | |
56e2e762 NC |
958 | |
959 | #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) | |
2b7972b0 | 960 | |
22a14e0d KH |
961 | /* The maximum number of bytes to copy using pairs of load/store instructions. |
962 | If a block is larger than this then a loop will be generated to copy | |
963 | MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice. | |
964 | A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte | |
965 | string copy in it. */ | |
966 | #define MAX_MOVE_BYTES 32 |