]>
Commit | Line | Data |
---|---|---|
1f92da87 | 1 | /* Definitions of target machine for GNU compiler, Renesas M32R cpu. |
22a14e0d KH |
2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
3 | 2005 Free Software Foundation, Inc. | |
8c5ca3b9 | 4 | |
1f92da87 | 5 | This file is part of GCC. |
8c5ca3b9 | 6 | |
1f92da87 NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 2, or (at your | |
10 | option) any later version. | |
8c5ca3b9 | 11 | |
1f92da87 NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
8c5ca3b9 | 16 | |
1f92da87 NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
8c5ca3b9 DE |
21 | |
22 | /* Things to do: | |
23 | - longlong.h? | |
24 | */ | |
25 | ||
8c5ca3b9 DE |
26 | #undef SWITCH_TAKES_ARG |
27 | #undef WORD_SWITCH_TAKES_ARG | |
28 | #undef HANDLE_SYSV_PRAGMA | |
29 | #undef SIZE_TYPE | |
30 | #undef PTRDIFF_TYPE | |
31 | #undef WCHAR_TYPE | |
32 | #undef WCHAR_TYPE_SIZE | |
56e2e762 NC |
33 | #undef TARGET_VERSION |
34 | #undef CPP_SPEC | |
35 | #undef ASM_SPEC | |
36 | #undef LINK_SPEC | |
37 | #undef STARTFILE_SPEC | |
38 | #undef ENDFILE_SPEC | |
ad126521 KI |
39 | |
40 | #undef ASM_APP_ON | |
41 | #undef ASM_APP_OFF | |
8c5ca3b9 | 42 | \f |
de41e41c BE |
43 | |
44 | /* M32R/X overrides. */ | |
45 | /* Print subsidiary information on the compiler version in use. */ | |
6975bd2c | 46 | #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)"); |
de41e41c BE |
47 | |
48 | /* Additional flags for the preprocessor. */ | |
6975bd2c KI |
49 | #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ |
50 | %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ | |
51 | %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ | |
52 | " | |
53 | ||
de41e41c BE |
54 | /* Assembler switches. */ |
55 | #define ASM_CPU_SPEC \ | |
6975bd2c | 56 | "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" |
de41e41c BE |
57 | |
58 | /* Use m32rx specific crt0/crtinit/crtfini files. */ | |
59 | #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" | |
60 | #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" | |
61 | ||
de41e41c BE |
62 | /* Define this macro as a C expression for the initializer of an array of |
63 | strings to tell the driver program which options are defaults for this | |
64 | target and thus do not need to be handled specially when using | |
65 | `MULTILIB_OPTIONS'. */ | |
66 | #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" | |
67 | ||
68 | /* Number of additional registers the subtarget defines. */ | |
69 | #define SUBTARGET_NUM_REGISTERS 1 | |
70 | ||
71 | /* 1 for registers that cannot be allocated. */ | |
72 | #define SUBTARGET_FIXED_REGISTERS , 1 | |
73 | ||
74 | /* 1 for registers that are not available across function calls. */ | |
75 | #define SUBTARGET_CALL_USED_REGISTERS , 1 | |
76 | ||
77 | /* Order to allocate model specific registers. */ | |
78 | #define SUBTARGET_REG_ALLOC_ORDER , 19 | |
79 | ||
80 | /* Registers which are accumulators. */ | |
81 | #define SUBTARGET_REG_CLASS_ACCUM 0x80000 | |
82 | ||
83 | /* All registers added. */ | |
84 | #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM | |
85 | ||
86 | /* Additional accumulator registers. */ | |
87 | #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) | |
88 | ||
89 | /* Define additional register names. */ | |
90 | #define SUBTARGET_REGISTER_NAMES , "a1" | |
91 | /* end M32R/X overrides. */ | |
92 | ||
8c5ca3b9 | 93 | /* Print subsidiary information on the compiler version in use. */ |
56e2e762 | 94 | #ifndef TARGET_VERSION |
8c5ca3b9 | 95 | #define TARGET_VERSION fprintf (stderr, " (m32r)") |
56e2e762 | 96 | #endif |
2b7972b0 | 97 | |
ad126521 | 98 | /* Switch Recognition by gcc.c. Add -G xx support. */ |
8c5ca3b9 | 99 | |
56e2e762 | 100 | #undef SWITCH_TAKES_ARG |
8c5ca3b9 DE |
101 | #define SWITCH_TAKES_ARG(CHAR) \ |
102 | (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') | |
103 | ||
104 | /* Names to predefine in the preprocessor for this target machine. */ | |
105 | /* __M32R__ is defined by the existing compiler so we use that. */ | |
cc956ba2 NB |
106 | #define TARGET_CPU_CPP_BUILTINS() \ |
107 | do \ | |
108 | { \ | |
109 | builtin_define ("__M32R__"); \ | |
df68f43b | 110 | builtin_define ("__m32r__"); \ |
cc956ba2 NB |
111 | builtin_assert ("cpu=m32r"); \ |
112 | builtin_assert ("machine=m32r"); \ | |
ad126521 KI |
113 | builtin_define (TARGET_BIG_ENDIAN \ |
114 | ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ | |
115 | if (flag_pic) \ | |
116 | { \ | |
117 | builtin_define ("__pic__"); \ | |
118 | builtin_define ("__PIC__"); \ | |
119 | } \ | |
cc956ba2 NB |
120 | } \ |
121 | while (0) | |
8c5ca3b9 | 122 | |
56e2e762 NC |
123 | /* This macro defines names of additional specifications to put in the specs |
124 | that can be used in various specifications like CC1_SPEC. Its definition | |
125 | is an initializer with a subgrouping for each command option. | |
8c5ca3b9 | 126 | |
56e2e762 | 127 | Each subgrouping contains a string constant, that defines the |
7ec022b2 | 128 | specification name, and a string constant that used by the GCC driver |
56e2e762 | 129 | program. |
8c5ca3b9 | 130 | |
56e2e762 | 131 | Do not define this macro if it does not need to do anything. */ |
2b7972b0 | 132 | |
56e2e762 NC |
133 | #ifndef SUBTARGET_EXTRA_SPECS |
134 | #define SUBTARGET_EXTRA_SPECS | |
8c5ca3b9 DE |
135 | #endif |
136 | ||
56e2e762 NC |
137 | #ifndef ASM_CPU_SPEC |
138 | #define ASM_CPU_SPEC "" | |
139 | #endif | |
8c5ca3b9 | 140 | |
56e2e762 NC |
141 | #ifndef CPP_CPU_SPEC |
142 | #define CPP_CPU_SPEC "" | |
143 | #endif | |
144 | ||
145 | #ifndef CC1_CPU_SPEC | |
146 | #define CC1_CPU_SPEC "" | |
147 | #endif | |
148 | ||
149 | #ifndef LINK_CPU_SPEC | |
150 | #define LINK_CPU_SPEC "" | |
151 | #endif | |
152 | ||
153 | #ifndef STARTFILE_CPU_SPEC | |
154 | #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" | |
155 | #endif | |
156 | ||
157 | #ifndef ENDFILE_CPU_SPEC | |
158 | #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" | |
159 | #endif | |
160 | ||
161 | #ifndef RELAX_SPEC | |
ad126521 | 162 | #if 0 /* Not supported yet. */ |
56e2e762 | 163 | #define RELAX_SPEC "%{mrelax:-relax}" |
8c5ca3b9 | 164 | #else |
56e2e762 NC |
165 | #define RELAX_SPEC "" |
166 | #endif | |
8c5ca3b9 DE |
167 | #endif |
168 | ||
56e2e762 NC |
169 | #define EXTRA_SPECS \ |
170 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
171 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
172 | { "cc1_cpu", CC1_CPU_SPEC }, \ | |
173 | { "link_cpu", LINK_CPU_SPEC }, \ | |
174 | { "startfile_cpu", STARTFILE_CPU_SPEC }, \ | |
175 | { "endfile_cpu", ENDFILE_CPU_SPEC }, \ | |
176 | { "relax", RELAX_SPEC }, \ | |
177 | SUBTARGET_EXTRA_SPECS | |
8c5ca3b9 | 178 | |
2a2001be IK |
179 | #define CPP_SPEC "%(cpp_cpu)" |
180 | ||
ad126521 | 181 | #undef CC1_SPEC |
56e2e762 | 182 | #define CC1_SPEC "%{G*} %(cc1_cpu)" |
2b7972b0 | 183 | |
56e2e762 NC |
184 | /* Options to pass on to the assembler. */ |
185 | #undef ASM_SPEC | |
ad126521 | 186 | #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic:-K PIC} %{fPIC:-K PIC}" |
56e2e762 | 187 | |
56e2e762 NC |
188 | #define LINK_SPEC "%{v} %(link_cpu) %(relax)" |
189 | ||
190 | #undef STARTFILE_SPEC | |
191 | #define STARTFILE_SPEC "%(startfile_cpu)" | |
192 | ||
193 | #undef ENDFILE_SPEC | |
194 | #define ENDFILE_SPEC "%(endfile_cpu)" | |
8c5ca3b9 DE |
195 | |
196 | #undef LIB_SPEC | |
197 | \f | |
198 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
199 | ||
6975bd2c KI |
200 | #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) |
201 | ||
97b73103 RS |
202 | #ifndef TARGET_LITTLE_ENDIAN |
203 | #define TARGET_LITTLE_ENDIAN 0 | |
8a897efe | 204 | #endif |
97b73103 | 205 | #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) |
8a897efe KI |
206 | |
207 | /* This defaults us to m32r. */ | |
208 | #ifndef TARGET_CPU_DEFAULT | |
209 | #define TARGET_CPU_DEFAULT 0 | |
ad126521 KI |
210 | #endif |
211 | ||
ad126521 KI |
212 | /* Cache-flush support. */ |
213 | extern const char * m32r_cache_flush_func; | |
ad126521 KI |
214 | extern int m32r_cache_flush_trap; |
215 | ||
8c5ca3b9 DE |
216 | /* Code Models |
217 | ||
218 | Code models are used to select between two choices of two separate | |
219 | possibilities (address space size, call insn to use): | |
220 | ||
221 | small: addresses use 24 bits, use bl to make calls | |
222 | medium: addresses use 32 bits, use bl to make calls (*1) | |
223 | large: addresses use 32 bits, use seth/add3/jl to make calls (*2) | |
224 | ||
225 | The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but | |
226 | using this one doesn't make much sense. | |
227 | ||
228 | (*1) The linker may eventually be able to relax seth/add3 -> ld24. | |
229 | (*2) The linker may eventually be able to relax seth/add3/jl -> bl. | |
230 | ||
231 | Internally these are recorded as TARGET_ADDR{24,32} and | |
232 | TARGET_CALL{26,32}. | |
233 | ||
234 | The __model__ attribute can be used to select the code model to use when | |
235 | accessing particular objects. */ | |
236 | ||
237 | enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE }; | |
238 | ||
239 | extern enum m32r_model m32r_model; | |
ad126521 | 240 | #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL) |
8c5ca3b9 | 241 | #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM) |
ad126521 KI |
242 | #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE) |
243 | #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL) | |
244 | #define TARGET_ADDR32 (! TARGET_ADDR24) | |
245 | #define TARGET_CALL26 (! TARGET_CALL32) | |
246 | #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE) | |
8c5ca3b9 DE |
247 | |
248 | /* The default is the small model. */ | |
56e2e762 | 249 | #ifndef M32R_MODEL_DEFAULT |
97b73103 | 250 | #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL |
56e2e762 | 251 | #endif |
8c5ca3b9 DE |
252 | |
253 | /* Small Data Area | |
254 | ||
255 | The SDA consists of sections .sdata, .sbss, and .scommon. | |
256 | .scommon isn't a real section, symbols in it have their section index | |
257 | set to SHN_M32R_SCOMMON, though support for it exists in the linker script. | |
258 | ||
259 | Two switches control the SDA: | |
260 | ||
261 | -G NNN - specifies the maximum size of variable to go in the SDA | |
262 | ||
263 | -msdata=foo - specifies how such variables are handled | |
264 | ||
265 | -msdata=none - small data area is disabled | |
266 | ||
267 | -msdata=sdata - small data goes in the SDA, special code isn't | |
268 | generated to use it, and special relocs aren't | |
269 | generated | |
270 | ||
271 | -msdata=use - small data goes in the SDA, special code is generated | |
272 | to use the SDA and special relocs are generated | |
273 | ||
274 | The SDA is not multilib'd, it isn't necessary. | |
275 | MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd | |
276 | libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use | |
277 | -msdata=use will successfully link with them (references in header files | |
278 | will cause the compiler to emit code that refers to library objects in | |
279 | .data). ??? There can be a problem if the user passes a -G value greater | |
280 | than the default and a library object in a header file is that size. | |
281 | The default is 8 so this should be rare - if it occurs the user | |
ad126521 | 282 | is required to rebuild the libraries or use a smaller value for -G. */ |
8c5ca3b9 DE |
283 | |
284 | /* Maximum size of variables that go in .sdata/.sbss. | |
285 | The -msdata=foo switch also controls how small variables are handled. */ | |
56e2e762 | 286 | #ifndef SDATA_DEFAULT_SIZE |
8c5ca3b9 | 287 | #define SDATA_DEFAULT_SIZE 8 |
56e2e762 | 288 | #endif |
8c5ca3b9 | 289 | |
8c5ca3b9 DE |
290 | enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE }; |
291 | ||
292 | extern enum m32r_sdata m32r_sdata; | |
ad126521 | 293 | #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE) |
8c5ca3b9 | 294 | #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA) |
ad126521 | 295 | #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE) |
8c5ca3b9 DE |
296 | |
297 | /* Default is to disable the SDA | |
298 | [for upward compatibility with previous toolchains]. */ | |
56e2e762 | 299 | #ifndef M32R_SDATA_DEFAULT |
97b73103 | 300 | #define M32R_SDATA_DEFAULT M32R_SDATA_NONE |
56e2e762 | 301 | #endif |
8c5ca3b9 DE |
302 | |
303 | /* Define this macro as a C expression for the initializer of an array of | |
2b7972b0 | 304 | strings to tell the driver program which options are defaults for this |
8c5ca3b9 DE |
305 | target and thus do not need to be handled specially when using |
306 | `MULTILIB_OPTIONS'. */ | |
56e2e762 NC |
307 | #ifndef SUBTARGET_MULTILIB_DEFAULTS |
308 | #define SUBTARGET_MULTILIB_DEFAULTS | |
309 | #endif | |
310 | ||
311 | #ifndef MULTILIB_DEFAULTS | |
312 | #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } | |
313 | #endif | |
8c5ca3b9 DE |
314 | |
315 | /* Sometimes certain combinations of command options do not make | |
316 | sense on a particular target machine. You can define a macro | |
317 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
318 | defined, is executed once just after all the command options have | |
319 | been parsed. | |
320 | ||
321 | Don't use this macro to turn on various extra optimizations for | |
322 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
323 | ||
56e2e762 NC |
324 | #ifndef SUBTARGET_OVERRIDE_OPTIONS |
325 | #define SUBTARGET_OVERRIDE_OPTIONS | |
326 | #endif | |
327 | ||
328 | #define OVERRIDE_OPTIONS \ | |
329 | do \ | |
330 | { \ | |
331 | /* These need to be done at start up. \ | |
332 | It's convenient to do them here. */ \ | |
333 | m32r_init (); \ | |
334 | SUBTARGET_OVERRIDE_OPTIONS \ | |
335 | } \ | |
336 | while (0) | |
337 | ||
338 | #ifndef SUBTARGET_OPTIMIZATION_OPTIONS | |
339 | #define SUBTARGET_OPTIMIZATION_OPTIONS | |
340 | #endif | |
341 | ||
342 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ | |
343 | do \ | |
344 | { \ | |
345 | if (LEVEL == 1) \ | |
346 | flag_regmove = TRUE; \ | |
347 | \ | |
348 | if (SIZE) \ | |
349 | { \ | |
350 | flag_omit_frame_pointer = TRUE; \ | |
351 | flag_strength_reduce = FALSE; \ | |
352 | } \ | |
353 | \ | |
354 | SUBTARGET_OPTIMIZATION_OPTIONS \ | |
355 | } \ | |
356 | while (0) | |
8c5ca3b9 DE |
357 | |
358 | /* Define this macro if debugging can be performed even without a | |
7ec022b2 | 359 | frame pointer. If this macro is defined, GCC will turn on the |
8c5ca3b9 DE |
360 | `-fomit-frame-pointer' option whenever `-O' is specified. */ |
361 | #define CAN_DEBUG_WITHOUT_FP | |
362 | \f | |
363 | /* Target machine storage layout. */ | |
364 | ||
8c5ca3b9 DE |
365 | /* Define this if most significant bit is lowest numbered |
366 | in instructions that operate on numbered bit-fields. */ | |
367 | #define BITS_BIG_ENDIAN 1 | |
368 | ||
369 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
ad126521 | 370 | #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
8c5ca3b9 DE |
371 | |
372 | /* Define this if most significant word of a multiword number is the lowest | |
373 | numbered. */ | |
ad126521 | 374 | #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
8c5ca3b9 DE |
375 | |
376 | /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must | |
377 | be a constant value with the same meaning as WORDS_BIG_ENDIAN, | |
378 | which will be used only when compiling libgcc2.c. Typically the | |
379 | value will be set based on preprocessor defines. */ | |
380 | /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/ | |
381 | ||
8c5ca3b9 DE |
382 | /* Width of a word, in units (bytes). */ |
383 | #define UNITS_PER_WORD 4 | |
384 | ||
385 | /* Define this macro if it is advisable to hold scalars in registers | |
386 | in a wider mode than that declared by the program. In such cases, | |
387 | the value is constrained to be within the bounds of the declared | |
388 | type, but kept valid in the wider mode. The signedness of the | |
389 | extension may differ from that of the type. */ | |
56e2e762 NC |
390 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
391 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
392 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
393 | { \ | |
394 | (MODE) = SImode; \ | |
395 | } | |
8c5ca3b9 | 396 | |
8c5ca3b9 DE |
397 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
398 | #define PARM_BOUNDARY 32 | |
399 | ||
400 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
401 | #define STACK_BOUNDARY 32 | |
402 | ||
403 | /* ALIGN FRAMES on word boundaries */ | |
ad126521 | 404 | #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) |
8c5ca3b9 DE |
405 | |
406 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
407 | #define FUNCTION_BOUNDARY 32 | |
408 | ||
409 | /* Alignment of field after `int : 0' in a structure. */ | |
410 | #define EMPTY_FIELD_BOUNDARY 32 | |
411 | ||
412 | /* Every structure's size must be a multiple of this. */ | |
413 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
414 | ||
43a88a8c | 415 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
8c5ca3b9 DE |
416 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
417 | ||
418 | /* No data type wants to be aligned rounder than this. */ | |
419 | #define BIGGEST_ALIGNMENT 32 | |
420 | ||
421 | /* The best alignment to use in cases where we have a choice. */ | |
422 | #define FASTEST_ALIGNMENT 32 | |
423 | ||
424 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
56e2e762 | 425 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
8c5ca3b9 DE |
426 | ((TREE_CODE (EXP) == STRING_CST \ |
427 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
428 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
429 | ||
430 | /* Make arrays of chars word-aligned for the same reasons. */ | |
56e2e762 NC |
431 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
432 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
433 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
8c5ca3b9 DE |
434 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
435 | ||
436 | /* Set this nonzero if move instructions will actually fail to work | |
437 | when given unaligned data. */ | |
438 | #define STRICT_ALIGNMENT 1 | |
ad126521 KI |
439 | |
440 | /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ | |
441 | #define LABEL_ALIGN(insn) 2 | |
8c5ca3b9 DE |
442 | \f |
443 | /* Layout of source language data types. */ | |
444 | ||
445 | #define SHORT_TYPE_SIZE 16 | |
446 | #define INT_TYPE_SIZE 32 | |
447 | #define LONG_TYPE_SIZE 32 | |
448 | #define LONG_LONG_TYPE_SIZE 64 | |
449 | #define FLOAT_TYPE_SIZE 32 | |
450 | #define DOUBLE_TYPE_SIZE 64 | |
451 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
452 | ||
453 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
454 | #define DEFAULT_SIGNED_CHAR 1 | |
455 | ||
456 | #define SIZE_TYPE "long unsigned int" | |
457 | #define PTRDIFF_TYPE "long int" | |
458 | #define WCHAR_TYPE "short unsigned int" | |
459 | #define WCHAR_TYPE_SIZE 16 | |
8c5ca3b9 DE |
460 | \f |
461 | /* Standard register usage. */ | |
462 | ||
463 | /* Number of actual hardware registers. | |
464 | The hardware registers are assigned numbers for the compiler | |
465 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
466 | All registers that the compiler knows about must be given numbers, | |
467 | even those that are not normally considered general registers. */ | |
56e2e762 NC |
468 | |
469 | #define M32R_NUM_REGISTERS 19 | |
470 | ||
471 | #ifndef SUBTARGET_NUM_REGISTERS | |
472 | #define SUBTARGET_NUM_REGISTERS 0 | |
473 | #endif | |
474 | ||
475 | #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) | |
2b7972b0 | 476 | |
8c5ca3b9 DE |
477 | /* 1 for registers that have pervasive standard uses |
478 | and are not available for the register allocator. | |
479 | ||
480 | 0-3 - arguments/results | |
481 | 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] | |
482 | 6 - call used, gptmp | |
483 | 7 - call used, static chain pointer | |
484 | 8-11 - call saved | |
485 | 12 - call saved [reserved for global pointer] | |
486 | 13 - frame pointer | |
487 | 14 - subroutine link register | |
488 | 15 - stack pointer | |
489 | 16 - arg pointer | |
490 | 17 - carry flag | |
56e2e762 | 491 | 18 - accumulator |
de41e41c | 492 | 19 - accumulator 1 in the m32r/x |
8c5ca3b9 DE |
493 | By default, the extension registers are not available. */ |
494 | ||
56e2e762 NC |
495 | #ifndef SUBTARGET_FIXED_REGISTERS |
496 | #define SUBTARGET_FIXED_REGISTERS | |
497 | #endif | |
8c5ca3b9 | 498 | |
56e2e762 NC |
499 | #define FIXED_REGISTERS \ |
500 | { \ | |
501 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
502 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
503 | 1, 1, 1 \ | |
504 | SUBTARGET_FIXED_REGISTERS \ | |
505 | } | |
2b7972b0 | 506 | |
8c5ca3b9 DE |
507 | /* 1 for registers not available across function calls. |
508 | These must include the FIXED_REGISTERS and also any | |
509 | registers that can be used without being saved. | |
510 | The latter must include the registers where values are returned | |
511 | and the register where structure-value addresses are passed. | |
512 | Aside from that, you can include as many other registers as you like. */ | |
513 | ||
56e2e762 NC |
514 | #ifndef SUBTARGET_CALL_USED_REGISTERS |
515 | #define SUBTARGET_CALL_USED_REGISTERS | |
516 | #endif | |
8c5ca3b9 | 517 | |
56e2e762 NC |
518 | #define CALL_USED_REGISTERS \ |
519 | { \ | |
520 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
521 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
522 | 1, 1, 1 \ | |
523 | SUBTARGET_CALL_USED_REGISTERS \ | |
524 | } | |
2b7972b0 | 525 | |
69a53ee8 KI |
526 | #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS |
527 | ||
8c5ca3b9 DE |
528 | /* Zero or more C statements that may conditionally modify two variables |
529 | `fixed_regs' and `call_used_regs' (both of type `char []') after they | |
530 | have been initialized from the two preceding macros. | |
531 | ||
532 | This is necessary in case the fixed or call-clobbered registers depend | |
533 | on target flags. | |
534 | ||
535 | You need not define this macro if it has no work to do. */ | |
536 | ||
56e2e762 NC |
537 | #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
538 | #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
ad126521 KI |
539 | #else |
540 | #define CONDITIONAL_REGISTER_USAGE \ | |
541 | do \ | |
542 | { \ | |
543 | if (flag_pic) \ | |
69a53ee8 KI |
544 | { \ |
545 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
546 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
547 | } \ | |
ad126521 KI |
548 | } \ |
549 | while (0) | |
56e2e762 | 550 | #endif |
8c5ca3b9 DE |
551 | |
552 | /* If defined, an initializer for a vector of integers, containing the | |
7ec022b2 | 553 | numbers of hard registers in the order in which GCC should |
8c5ca3b9 | 554 | prefer to use them (from most preferred to least). */ |
56e2e762 NC |
555 | |
556 | #ifndef SUBTARGET_REG_ALLOC_ORDER | |
557 | #define SUBTARGET_REG_ALLOC_ORDER | |
558 | #endif | |
559 | ||
ad126521 | 560 | #if 1 /* Better for int code. */ |
56e2e762 NC |
561 | #define REG_ALLOC_ORDER \ |
562 | { \ | |
563 | 4, 5, 6, 7, 2, 3, 8, 9, 10, \ | |
564 | 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ | |
565 | SUBTARGET_REG_ALLOC_ORDER \ | |
566 | } | |
567 | ||
ad126521 | 568 | #else /* Better for fp code at expense of int code. */ |
56e2e762 NC |
569 | #define REG_ALLOC_ORDER \ |
570 | { \ | |
571 | 0, 1, 2, 3, 4, 5, 6, 7, 8, \ | |
572 | 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ | |
573 | SUBTARGET_REG_ALLOC_ORDER \ | |
574 | } | |
8c5ca3b9 DE |
575 | #endif |
576 | ||
577 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
578 | to hold something of mode MODE. | |
579 | This is ordinarily the length in words of a value of mode MODE | |
580 | but can be less for certain modes in special long registers. */ | |
581 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
ad126521 | 582 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
8c5ca3b9 DE |
583 | |
584 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
0139adca | 585 | extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; |
8c5ca3b9 DE |
586 | extern unsigned int m32r_mode_class[]; |
587 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
ad126521 | 588 | ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0) |
8c5ca3b9 DE |
589 | |
590 | /* A C expression that is nonzero if it is desirable to choose | |
591 | register allocation so as to avoid move instructions between a | |
592 | value of mode MODE1 and a value of mode MODE2. | |
593 | ||
594 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, | |
595 | MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, | |
596 | MODE2)' must be zero. */ | |
597 | ||
598 | /* Tie QI/HI/SI modes together. */ | |
ad126521 KI |
599 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
600 | ( GET_MODE_CLASS (MODE1) == MODE_INT \ | |
601 | && GET_MODE_CLASS (MODE2) == MODE_INT \ | |
602 | && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ | |
603 | && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) | |
a398a822 KI |
604 | |
605 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
606 | m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
8c5ca3b9 DE |
607 | \f |
608 | /* Register classes and constants. */ | |
609 | ||
610 | /* Define the classes of registers for register constraints in the | |
611 | machine description. Also define ranges of constants. | |
612 | ||
613 | One of the classes must always be named ALL_REGS and include all hard regs. | |
614 | If there is more than one class, another class must be named NO_REGS | |
615 | and contain no registers. | |
616 | ||
617 | The name GENERAL_REGS must be the name of a class (or an alias for | |
618 | another name such as ALL_REGS). This is the class of registers | |
619 | that is allowed by "g" or "r" in a register constraint. | |
620 | Also, registers outside this class are allocated only when | |
621 | instructions express preferences for them. | |
622 | ||
623 | The classes must be numbered in nondecreasing order; that is, | |
624 | a larger-numbered class must never be contained completely | |
625 | in a smaller-numbered class. | |
626 | ||
627 | For any two classes, it is very desirable that there be another | |
628 | class that represents their union. | |
629 | ||
630 | It is important that any condition codes have class NO_REGS. | |
631 | See `register_operand'. */ | |
632 | ||
56e2e762 NC |
633 | enum reg_class |
634 | { | |
635 | NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES | |
8c5ca3b9 DE |
636 | }; |
637 | ||
56e2e762 | 638 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
8c5ca3b9 | 639 | |
71cc389b | 640 | /* Give names of register classes as strings for dump file. */ |
8c5ca3b9 | 641 | #define REG_CLASS_NAMES \ |
56e2e762 | 642 | { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } |
8c5ca3b9 DE |
643 | |
644 | /* Define which registers fit in which classes. | |
645 | This is an initializer for a vector of HARD_REG_SET | |
646 | of length N_REG_CLASSES. */ | |
647 | ||
56e2e762 NC |
648 | #ifndef SUBTARGET_REG_CLASS_CARRY |
649 | #define SUBTARGET_REG_CLASS_CARRY 0 | |
650 | #endif | |
651 | ||
652 | #ifndef SUBTARGET_REG_CLASS_ACCUM | |
653 | #define SUBTARGET_REG_CLASS_ACCUM 0 | |
654 | #endif | |
655 | ||
656 | #ifndef SUBTARGET_REG_CLASS_GENERAL | |
657 | #define SUBTARGET_REG_CLASS_GENERAL 0 | |
658 | #endif | |
659 | ||
660 | #ifndef SUBTARGET_REG_CLASS_ALL | |
661 | #define SUBTARGET_REG_CLASS_ALL 0 | |
662 | #endif | |
8c5ca3b9 | 663 | |
56e2e762 NC |
664 | #define REG_CLASS_CONTENTS \ |
665 | { \ | |
666 | { 0x00000 }, \ | |
667 | { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ | |
668 | { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ | |
669 | { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ | |
670 | { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ | |
671 | } | |
2b7972b0 | 672 | |
8c5ca3b9 DE |
673 | /* The same information, inverted: |
674 | Return the class number of the smallest class containing | |
675 | reg number REGNO. This could be a conditional expression | |
676 | or could index an array. */ | |
2b7972b0 | 677 | extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
56e2e762 | 678 | #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) |
8c5ca3b9 DE |
679 | |
680 | /* The class value for index registers, and the one for base regs. */ | |
681 | #define INDEX_REG_CLASS GENERAL_REGS | |
682 | #define BASE_REG_CLASS GENERAL_REGS | |
683 | ||
ad126521 KI |
684 | #define REG_CLASS_FROM_LETTER(C) \ |
685 | ( (C) == 'c' ? CARRY_REG \ | |
686 | : (C) == 'a' ? ACCUM_REGS \ | |
687 | : NO_REGS) | |
8c5ca3b9 DE |
688 | |
689 | /* These assume that REGNO is a hard or pseudo reg number. | |
690 | They give nonzero only if REGNO is a hard reg of the suitable class | |
691 | or a pseudo reg currently allocated to a suitable hard reg. | |
692 | Since they use reg_renumber, they are safe only once reg_renumber | |
693 | has been allocated, which happens in local-alloc.c. */ | |
694 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
ad126521 KI |
695 | ((REGNO) < FIRST_PSEUDO_REGISTER \ |
696 | ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ | |
697 | : GPR_P (reg_renumber[REGNO])) | |
698 | ||
8c5ca3b9 DE |
699 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) |
700 | ||
701 | /* Given an rtx X being reloaded into a reg required to be | |
702 | in class CLASS, return the class of reg to actually use. | |
703 | In general this is just CLASS; but on some machines | |
704 | in some cases it is preferable to use a more restrictive class. */ | |
ad126521 | 705 | #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) |
8c5ca3b9 DE |
706 | |
707 | /* Return the maximum number of consecutive registers | |
708 | needed to represent mode MODE in a register of class CLASS. */ | |
709 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
ad126521 | 710 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
8c5ca3b9 DE |
711 | |
712 | /* The letters I, J, K, L, M, N, O, P in a register constraint string | |
713 | can be used to stand for particular ranges of immediate operands. | |
714 | This macro defines what the ranges are. | |
715 | C is the letter, and VALUE is a constant value. | |
716 | Return 1 if VALUE is in the range specified by C. */ | |
717 | /* 'I' is used for 8 bit signed immediates. | |
718 | 'J' is used for 16 bit signed immediates. | |
719 | 'K' is used for 16 bit unsigned immediates. | |
720 | 'L' is used for 16 bit immediates left shifted by 16 (sign ???). | |
721 | 'M' is used for 24 bit unsigned immediates. | |
722 | 'N' is used for any 32 bit non-symbolic value. | |
723 | 'O' is used for 5 bit unsigned immediates (shift count). | |
724 | 'P' is used for 16 bit signed immediates for compares | |
725 | (values in the range -32767 to +32768). */ | |
726 | ||
56e2e762 NC |
727 | /* Return true if a value is inside a range. */ |
728 | #define IN_RANGE_P(VALUE, LOW, HIGH) \ | |
729 | (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ | |
730 | <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) | |
731 | ||
732 | /* Local to this file. */ | |
ad126521 KI |
733 | #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f) |
734 | #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) | |
735 | #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) | |
736 | #define UPPER16_P(X) (((X) & 0xffff) == 0 \ | |
737 | && ((X) >> 16) >= - 0x8000 \ | |
738 | && ((X) >> 16) <= 0x7fff) | |
739 | #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) | |
740 | #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) | |
741 | #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff) | |
742 | #define UINT5_P(X) ((X) >= 0 && (X) < 32) | |
5b8ae21f | 743 | #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128) |
8c5ca3b9 | 744 | |
5b8ae21f | 745 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
ad126521 KI |
746 | ( (C) == 'I' ? INT8_P (VALUE) \ |
747 | : (C) == 'J' ? INT16_P (VALUE) \ | |
748 | : (C) == 'K' ? UINT16_P (VALUE) \ | |
749 | : (C) == 'L' ? UPPER16_P (VALUE) \ | |
750 | : (C) == 'M' ? UINT24_P (VALUE) \ | |
751 | : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \ | |
752 | : (C) == 'O' ? UINT5_P (VALUE) \ | |
753 | : (C) == 'P' ? CMP_INT16_P (VALUE) \ | |
754 | : 0) | |
8c5ca3b9 DE |
755 | |
756 | /* Similar, but for floating constants, and defining letters G and H. | |
757 | Here VALUE is the CONST_DOUBLE rtx itself. | |
758 | For the m32r, handle a few constants inline. | |
759 | ??? We needn't treat DI and DF modes differently, but for now we do. */ | |
ad126521 KI |
760 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
761 | ( (C) == 'G' ? easy_di_const (VALUE) \ | |
762 | : (C) == 'H' ? easy_df_const (VALUE) \ | |
763 | : 0) | |
8c5ca3b9 DE |
764 | |
765 | /* A C expression that defines the optional machine-dependent constraint | |
766 | letters that can be used to segregate specific types of operands, | |
767 | usually memory references, for the target machine. It should return 1 if | |
768 | VALUE corresponds to the operand type represented by the constraint letter | |
769 | C. If C is not defined as an extra constraint, the value returned should | |
770 | be 0 regardless of VALUE. */ | |
771 | /* Q is for symbolic addresses loadable with ld24. | |
2b7972b0 | 772 | R is for symbolic addresses when ld24 can't be used. |
56e2e762 | 773 | S is for stores with pre {inc,dec}rement |
5b8ae21f | 774 | T is for indirect of a pointer. |
56e2e762 | 775 | U is for loads with post increment. */ |
5b8ae21f MM |
776 | |
777 | #define EXTRA_CONSTRAINT(VALUE, C) \ | |
ad126521 | 778 | ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \ |
56e2e762 | 779 | || addr24_operand (VALUE, VOIDmode)) \ |
ad126521 | 780 | : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \ |
56e2e762 | 781 | || addr32_operand (VALUE, VOIDmode)) \ |
ad126521 | 782 | : (C) == 'S' ? (GET_CODE (VALUE) == MEM \ |
56e2e762 NC |
783 | && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \ |
784 | XEXP (VALUE, 0))) \ | |
ad126521 | 785 | : (C) == 'T' ? (GET_CODE (VALUE) == MEM \ |
56e2e762 | 786 | && memreg_operand (VALUE, GET_MODE (VALUE))) \ |
ad126521 | 787 | : (C) == 'U' ? (GET_CODE (VALUE) == MEM \ |
56e2e762 NC |
788 | && LOAD_POSTINC_P (GET_MODE (VALUE), \ |
789 | XEXP (VALUE, 0))) \ | |
ad126521 | 790 | : 0) |
8c5ca3b9 DE |
791 | \f |
792 | /* Stack layout and stack pointer usage. */ | |
793 | ||
794 | /* Define this macro if pushing a word onto the stack moves the stack | |
795 | pointer to a smaller address. */ | |
796 | #define STACK_GROWS_DOWNWARD | |
797 | ||
8c5ca3b9 DE |
798 | /* Offset from frame pointer to start allocating local variables at. |
799 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
800 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
801 | of the first local allocated. */ | |
802 | /* The frame pointer points at the same place as the stack pointer, except if | |
803 | alloca has been called. */ | |
804 | #define STARTING_FRAME_OFFSET \ | |
ad126521 | 805 | M32R_STACK_ALIGN (current_function_outgoing_args_size) |
8c5ca3b9 DE |
806 | |
807 | /* Offset from the stack pointer register to the first location at which | |
808 | outgoing arguments are placed. */ | |
809 | #define STACK_POINTER_OFFSET 0 | |
810 | ||
811 | /* Offset of first parameter from the argument pointer register value. */ | |
812 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
813 | ||
8c5ca3b9 DE |
814 | /* Register to use for pushing function arguments. */ |
815 | #define STACK_POINTER_REGNUM 15 | |
816 | ||
817 | /* Base register for access to local variables of the function. */ | |
818 | #define FRAME_POINTER_REGNUM 13 | |
819 | ||
820 | /* Base register for access to arguments of the function. */ | |
821 | #define ARG_POINTER_REGNUM 16 | |
822 | ||
ad126521 KI |
823 | /* Register in which static-chain is passed to a function. |
824 | This must not be a register used by the prologue. */ | |
825 | #define STATIC_CHAIN_REGNUM 7 | |
8c5ca3b9 DE |
826 | |
827 | /* These aren't official macros. */ | |
ad126521 KI |
828 | #define PROLOGUE_TMP_REGNUM 4 |
829 | #define RETURN_ADDR_REGNUM 14 | |
830 | /* #define GP_REGNUM 12 */ | |
831 | #define CARRY_REGNUM 17 | |
832 | #define ACCUM_REGNUM 18 | |
833 | #define M32R_MAX_INT_REGS 16 | |
8c5ca3b9 | 834 | |
56e2e762 NC |
835 | #ifndef SUBTARGET_GPR_P |
836 | #define SUBTARGET_GPR_P(REGNO) 0 | |
837 | #endif | |
838 | ||
839 | #ifndef SUBTARGET_ACCUM_P | |
840 | #define SUBTARGET_ACCUM_P(REGNO) 0 | |
841 | #endif | |
842 | ||
843 | #ifndef SUBTARGET_CARRY_P | |
844 | #define SUBTARGET_CARRY_P(REGNO) 0 | |
845 | #endif | |
846 | ||
847 | #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) | |
848 | #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) | |
849 | #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) | |
8c5ca3b9 DE |
850 | \f |
851 | /* Eliminating the frame and arg pointers. */ | |
852 | ||
853 | /* A C expression which is nonzero if a function must have and use a | |
854 | frame pointer. This expression is evaluated in the reload pass. | |
855 | If its value is nonzero the function will have a frame pointer. */ | |
56e2e762 | 856 | #define FRAME_POINTER_REQUIRED current_function_calls_alloca |
8c5ca3b9 DE |
857 | |
858 | #if 0 | |
859 | /* C statement to store the difference between the frame pointer | |
860 | and the stack pointer values immediately after the function prologue. | |
861 | If `ELIMINABLE_REGS' is defined, this macro will be not be used and | |
862 | need not be defined. */ | |
863 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
864 | ((VAR) = m32r_compute_frame_size (get_frame_size ())) | |
865 | #endif | |
866 | ||
867 | /* If defined, this macro specifies a table of register pairs used to | |
868 | eliminate unneeded registers that point into the stack frame. If | |
869 | it is not defined, the only elimination attempted by the compiler | |
870 | is to replace references to the frame pointer with references to | |
871 | the stack pointer. | |
872 | ||
873 | Note that the elimination of the argument pointer with the stack | |
874 | pointer is specified first since that is the preferred elimination. */ | |
875 | ||
56e2e762 NC |
876 | #define ELIMINABLE_REGS \ |
877 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
878 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
879 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} | |
8c5ca3b9 | 880 | |
a0ab749a | 881 | /* A C expression that returns nonzero if the compiler is allowed to |
8c5ca3b9 DE |
882 | try to replace register number FROM-REG with register number |
883 | TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is | |
884 | defined, and will usually be the constant 1, since most of the | |
885 | cases preventing register elimination are things that the compiler | |
886 | already knows about. */ | |
887 | ||
56e2e762 NC |
888 | #define CAN_ELIMINATE(FROM, TO) \ |
889 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
890 | ? ! frame_pointer_needed \ | |
891 | : 1) | |
8c5ca3b9 DE |
892 | |
893 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It | |
894 | specifies the initial difference between the specified pair of | |
895 | registers. This macro must be defined if `ELIMINABLE_REGS' is | |
896 | defined. */ | |
897 | ||
ad126521 KI |
898 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
899 | do \ | |
900 | { \ | |
901 | int size = m32r_compute_frame_size (get_frame_size ()); \ | |
902 | \ | |
903 | if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
904 | (OFFSET) = 0; \ | |
905 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
906 | (OFFSET) = size - current_function_pretend_args_size; \ | |
907 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
908 | (OFFSET) = size - current_function_pretend_args_size; \ | |
909 | else \ | |
910 | abort (); \ | |
911 | } \ | |
912 | while (0) | |
8c5ca3b9 DE |
913 | \f |
914 | /* Function argument passing. */ | |
915 | ||
8c5ca3b9 DE |
916 | /* If defined, the maximum amount of space required for outgoing |
917 | arguments will be computed and placed into the variable | |
918 | `current_function_outgoing_args_size'. No space will be pushed | |
919 | onto the stack for each call; instead, the function prologue should | |
920 | increase the stack frame size by this amount. */ | |
f73ad30e | 921 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8c5ca3b9 | 922 | |
8c5ca3b9 DE |
923 | /* Value is the number of bytes of arguments automatically |
924 | popped when returning from a subroutine call. | |
925 | FUNDECL is the declaration node of the function (as a tree), | |
926 | FUNTYPE is the data type of the function (as a tree), | |
927 | or for a library call it is an identifier node for the subroutine name. | |
928 | SIZE is the number of bytes of arguments passed on the stack. */ | |
929 | #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 | |
930 | ||
931 | /* Define a data type for recording info about an argument list | |
932 | during the scan of that argument list. This data type should | |
933 | hold all necessary information about the function itself | |
934 | and about the args processed so far, enough to enable macros | |
935 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
936 | #define CUMULATIVE_ARGS int | |
937 | ||
938 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
939 | for a call to a function whose data type is FNTYPE. | |
940 | For a library call, FNTYPE is 0. */ | |
0f6937fe | 941 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
56e2e762 | 942 | ((CUM) = 0) |
8c5ca3b9 DE |
943 | |
944 | /* The number of registers used for parameter passing. Local to this file. */ | |
945 | #define M32R_MAX_PARM_REGS 4 | |
946 | ||
947 | /* 1 if N is a possible register number for function argument passing. */ | |
948 | #define FUNCTION_ARG_REGNO_P(N) \ | |
56e2e762 | 949 | ((unsigned) (N) < M32R_MAX_PARM_REGS) |
8c5ca3b9 DE |
950 | |
951 | /* The ROUND_ADVANCE* macros are local to this file. */ | |
952 | /* Round SIZE up to a word boundary. */ | |
953 | #define ROUND_ADVANCE(SIZE) \ | |
56e2e762 | 954 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
8c5ca3b9 DE |
955 | |
956 | /* Round arg MODE/TYPE up to the next word boundary. */ | |
957 | #define ROUND_ADVANCE_ARG(MODE, TYPE) \ | |
56e2e762 | 958 | ((MODE) == BLKmode \ |
16f104b3 | 959 | ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \ |
9d303046 | 960 | : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE))) |
8c5ca3b9 DE |
961 | |
962 | /* Round CUM up to the necessary point for argument MODE/TYPE. */ | |
8c5ca3b9 | 963 | #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM) |
8c5ca3b9 DE |
964 | |
965 | /* Return boolean indicating arg of type TYPE and mode MODE will be passed in | |
966 | a reg. This includes arguments that have to be passed by reference as the | |
967 | pointer to them is passed in a reg if one is available (and that is what | |
968 | we're given). | |
969 | This macro is only used in this file. */ | |
6c535c69 | 970 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ |
56e2e762 | 971 | (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS) |
8c5ca3b9 DE |
972 | |
973 | /* Determine where to put an argument to a function. | |
974 | Value is zero to push the argument on the stack, | |
975 | or a hard register in which to store the argument. | |
976 | ||
977 | MODE is the argument's machine mode. | |
978 | TYPE is the data type of the argument (as a tree). | |
979 | This is null for libcalls where that information may | |
980 | not be available. | |
981 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
982 | the preceding args and about the function being called. | |
983 | NAMED is nonzero if this argument is a named parameter | |
984 | (otherwise it is an extra parameter matching an ellipsis). */ | |
985 | /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers | |
986 | and the rest are pushed. */ | |
987 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
6c535c69 | 988 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
56e2e762 NC |
989 | ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \ |
990 | : 0) | |
8c5ca3b9 | 991 | |
8c5ca3b9 DE |
992 | /* Update the data in CUM to advance over an argument |
993 | of mode MODE and data type TYPE. | |
994 | (TYPE is null for libcalls where that information may not be available.) */ | |
995 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
56e2e762 | 996 | ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ |
8c5ca3b9 DE |
997 | + ROUND_ADVANCE_ARG ((MODE), (TYPE)))) |
998 | ||
999 | /* If defined, a C expression that gives the alignment boundary, in bits, | |
1000 | of an argument with the specified mode and type. If it is not defined, | |
1001 | PARM_BOUNDARY is used for all arguments. */ | |
1002 | #if 0 | |
1003 | /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */ | |
1004 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
ad126521 KI |
1005 | (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ |
1006 | ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) | |
8c5ca3b9 | 1007 | #endif |
8c5ca3b9 DE |
1008 | \f |
1009 | /* Function results. */ | |
1010 | ||
1011 | /* Define how to find the value returned by a function. | |
1012 | VALTYPE is the data type of the value (as a tree). | |
1013 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1014 | otherwise, FUNC is 0. */ | |
c5c76735 | 1015 | #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0) |
8c5ca3b9 DE |
1016 | |
1017 | /* Define how to find the value returned by a library function | |
1018 | assuming the value has mode MODE. */ | |
c5c76735 | 1019 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) |
8c5ca3b9 DE |
1020 | |
1021 | /* 1 if N is a possible register number for a function value | |
1022 | as seen by the caller. */ | |
1023 | /* ??? What about r1 in DI/DF values. */ | |
1024 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
1025 | ||
bd5bd7ac | 1026 | /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ |
8c5ca3b9 | 1027 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
8c5ca3b9 DE |
1028 | \f |
1029 | /* Function entry and exit. */ | |
1030 | ||
1031 | /* Initialize data used by insn expanders. This is called from | |
1032 | init_emit, once for each function, before code is generated. */ | |
1033 | #define INIT_EXPANDERS m32r_init_expanders () | |
1034 | ||
8c5ca3b9 DE |
1035 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1036 | the stack pointer does not matter. The value is tested only in | |
1037 | functions that have frame pointers. | |
1038 | No definition is equivalent to always zero. */ | |
1039 | #define EXIT_IGNORE_STACK 1 | |
1040 | ||
8c5ca3b9 DE |
1041 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1042 | for profiling a function entry. */ | |
ad126521 KI |
1043 | #undef FUNCTION_PROFILER |
1044 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1045 | do \ | |
1046 | { \ | |
1047 | if (flag_pic) \ | |
1048 | { \ | |
1049 | fprintf (FILE, "\tld24 r14,#mcount\n"); \ | |
1050 | fprintf (FILE, "\tadd r14,r12\n"); \ | |
1051 | fprintf (FILE, "\tld r14,@r14\n"); \ | |
1052 | fprintf (FILE, "\tjl r14\n"); \ | |
1053 | } \ | |
1054 | else \ | |
1055 | { \ | |
1056 | if (TARGET_ADDR24) \ | |
1057 | fprintf (FILE, "\tbl mcount\n"); \ | |
1058 | else \ | |
1059 | { \ | |
1060 | fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ | |
1061 | fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ | |
1062 | fprintf (FILE, "\tjl r14\n"); \ | |
1063 | } \ | |
1064 | } \ | |
1065 | fprintf (FILE, "\taddi sp,#4\n"); \ | |
1066 | } \ | |
1067 | while (0) | |
8c5ca3b9 DE |
1068 | \f |
1069 | /* Trampolines. */ | |
1070 | ||
ad126521 | 1071 | /* On the M32R, the trampoline is: |
8c5ca3b9 | 1072 | |
ad126521 KI |
1073 | mv r7, lr -> bl L1 ; 178e 7e01 |
1074 | L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) | |
1075 | mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 | |
1076 | ld r6, @r6 -> jmp r6 ; 26c6 1fc6 | |
1077 | L2: .word STATIC | |
1078 | .word FUNCTION */ | |
8c5ca3b9 | 1079 | |
ad126521 KI |
1080 | #ifndef CACHE_FLUSH_FUNC |
1081 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
1082 | #endif | |
1083 | #ifndef CACHE_FLUSH_TRAP | |
97b73103 | 1084 | #define CACHE_FLUSH_TRAP 12 |
ad126521 | 1085 | #endif |
8c5ca3b9 DE |
1086 | |
1087 | /* Length in bytes of the trampoline for entering a nested function. */ | |
f26ef713 | 1088 | #define TRAMPOLINE_SIZE 24 |
8c5ca3b9 DE |
1089 | |
1090 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1091 | FNADDR is an RTX for the address of the function's pure code. | |
1092 | CXT is an RTX for the static chain value for the function. */ | |
ad126521 KI |
1093 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1094 | do \ | |
1095 | { \ | |
1096 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \ | |
1097 | GEN_INT \ | |
1098 | (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \ | |
1099 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \ | |
1100 | GEN_INT \ | |
1101 | (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \ | |
1102 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \ | |
1103 | GEN_INT \ | |
1104 | (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \ | |
1105 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \ | |
1106 | GEN_INT \ | |
1107 | (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \ | |
1108 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \ | |
1109 | (CXT)); \ | |
1110 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \ | |
1111 | (FNADDR)); \ | |
97b73103 | 1112 | if (m32r_cache_flush_trap >= 0) \ |
ad126521 KI |
1113 | emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\ |
1114 | GEN_INT (m32r_cache_flush_trap) )); \ | |
1115 | else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \ | |
767dec6b | 1116 | emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \ |
ad126521 KI |
1117 | 0, VOIDmode, 3, TRAMP, Pmode, \ |
1118 | GEN_INT (TRAMPOLINE_SIZE), SImode, \ | |
1119 | GEN_INT (3), SImode); \ | |
1120 | } \ | |
1121 | while (0) | |
8c5ca3b9 | 1122 | \f |
7b14411a KI |
1123 | #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) |
1124 | ||
1125 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) | |
1126 | ||
8c5ca3b9 DE |
1127 | /* Addressing modes, and classification of registers for them. */ |
1128 | ||
1129 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1130 | #define MAX_REGS_PER_ADDRESS 1 | |
1131 | ||
1132 | /* We have post-inc load and pre-dec,pre-inc store, | |
1133 | but only for 4 byte vals. */ | |
ad126521 KI |
1134 | #define HAVE_PRE_DECREMENT 1 |
1135 | #define HAVE_PRE_INCREMENT 1 | |
940da324 | 1136 | #define HAVE_POST_INCREMENT 1 |
8c5ca3b9 DE |
1137 | |
1138 | /* Recognize any constant value that is a valid address. */ | |
ad126521 KI |
1139 | #define CONSTANT_ADDRESS_P(X) \ |
1140 | ( GET_CODE (X) == LABEL_REF \ | |
1141 | || GET_CODE (X) == SYMBOL_REF \ | |
1142 | || GET_CODE (X) == CONST_INT \ | |
1143 | || (GET_CODE (X) == CONST \ | |
1144 | && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) | |
8c5ca3b9 DE |
1145 | |
1146 | /* Nonzero if the constant value X is a legitimate general operand. | |
1147 | We don't allow (plus symbol large-constant) as the relocations can't | |
1148 | describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations. | |
1149 | We allow all CONST_DOUBLE's as the md file patterns will force the | |
1150 | constant to memory if they can't handle them. */ | |
1151 | ||
56e2e762 | 1152 | #define LEGITIMATE_CONSTANT_P(X) \ |
ad126521 KI |
1153 | (! (GET_CODE (X) == CONST \ |
1154 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1155 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ | |
1156 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1157 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767)) | |
8c5ca3b9 DE |
1158 | |
1159 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1160 | and check its validity for a certain class. | |
1161 | We have two alternate definitions for each of them. | |
1162 | The usual definition accepts all pseudo regs; the other rejects | |
1163 | them unless they have been allocated suitable hard regs. | |
1164 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1165 | ||
1166 | Most source files want to accept pseudo regs in the hope that | |
1167 | they will get allocated to the class that the insn wants them to be in. | |
1168 | Source files for reload pass need to be strict. | |
1169 | After reload, it makes no difference, since pseudo regs have | |
1170 | been eliminated by then. */ | |
1171 | ||
1172 | #ifdef REG_OK_STRICT | |
1173 | ||
1174 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1175 | #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X)) | |
1176 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1177 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) | |
1178 | ||
1179 | #else | |
1180 | ||
1181 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1182 | or if it is a pseudo reg. */ | |
56e2e762 | 1183 | #define REG_OK_FOR_BASE_P(X) \ |
ad126521 KI |
1184 | (GPR_P (REGNO (X)) \ |
1185 | || (REGNO (X)) == ARG_POINTER_REGNUM \ | |
1186 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
8c5ca3b9 DE |
1187 | /* Nonzero if X is a hard reg that can be used as an index |
1188 | or if it is a pseudo reg. */ | |
1189 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) | |
1190 | ||
1191 | #endif | |
1192 | ||
1193 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1194 | that is a valid memory address for an instruction. | |
1195 | The MODE argument is the machine mode for the MEM expression | |
1196 | that wants to use this address. */ | |
1197 | ||
56e2e762 NC |
1198 | /* Local to this file. */ |
1199 | #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X)) | |
8c5ca3b9 | 1200 | |
56e2e762 | 1201 | /* Local to this file. */ |
8c5ca3b9 | 1202 | #define RTX_OK_FOR_OFFSET_P(X) \ |
ad126521 | 1203 | (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X))) |
8c5ca3b9 | 1204 | |
56e2e762 | 1205 | /* Local to this file. */ |
ad126521 KI |
1206 | #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ |
1207 | (GET_CODE (X) == PLUS \ | |
1208 | && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ | |
1209 | && RTX_OK_FOR_OFFSET_P (XEXP (X, 1))) | |
8c5ca3b9 | 1210 | |
56e2e762 | 1211 | /* Local to this file. */ |
5b8ae21f MM |
1212 | /* For LO_SUM addresses, do not allow them if the MODE is > 1 word, |
1213 | since more than one instruction will be required. */ | |
ad126521 KI |
1214 | #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \ |
1215 | (GET_CODE (X) == LO_SUM \ | |
1216 | && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\ | |
1217 | && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ | |
1218 | && CONSTANT_P (XEXP (X, 1))) | |
8c5ca3b9 | 1219 | |
56e2e762 NC |
1220 | /* Local to this file. */ |
1221 | /* Is this a load and increment operation. */ | |
ad126521 KI |
1222 | #define LOAD_POSTINC_P(MODE, X) \ |
1223 | (((MODE) == SImode || (MODE) == SFmode) \ | |
1224 | && GET_CODE (X) == POST_INC \ | |
1225 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1226 | && RTX_OK_FOR_BASE_P (XEXP (X, 0))) | |
56e2e762 NC |
1227 | |
1228 | /* Local to this file. */ | |
e03f5d43 | 1229 | /* Is this an increment/decrement and store operation. */ |
ad126521 KI |
1230 | #define STORE_PREINC_PREDEC_P(MODE, X) \ |
1231 | (((MODE) == SImode || (MODE) == SFmode) \ | |
1232 | && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \ | |
1233 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1234 | && RTX_OK_FOR_BASE_P (XEXP (X, 0))) | |
1235 | ||
1236 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1237 | do \ | |
1238 | { \ | |
1239 | if (RTX_OK_FOR_BASE_P (X)) \ | |
1240 | goto ADDR; \ | |
1241 | if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \ | |
1242 | goto ADDR; \ | |
1243 | if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \ | |
1244 | goto ADDR; \ | |
1245 | if (LOAD_POSTINC_P ((MODE), (X))) \ | |
1246 | goto ADDR; \ | |
1247 | if (STORE_PREINC_PREDEC_P ((MODE), (X))) \ | |
1248 | goto ADDR; \ | |
1249 | } \ | |
1250 | while (0) | |
8c5ca3b9 DE |
1251 | |
1252 | /* Try machine-dependent ways of modifying an illegitimate address | |
1253 | to be legitimate. If we find one, return the new, valid address. | |
1254 | This macro is used in only one place: `memory_address' in explow.c. | |
1255 | ||
1256 | OLDX is the address as it was before break_out_memory_refs was called. | |
1257 | In some cases it is useful to look at this to decide what needs to be done. | |
1258 | ||
1259 | MODE and WIN are passed so that this macro can use | |
1260 | GO_IF_LEGITIMATE_ADDRESS. | |
1261 | ||
1262 | It is always safe for this macro to do nothing. It exists to recognize | |
ad126521 KI |
1263 | opportunities to optimize the output. */ |
1264 | ||
1265 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
1266 | do \ | |
1267 | { \ | |
1268 | if (flag_pic) \ | |
1269 | (X) = m32r_legitimize_pic_address (X, NULL_RTX); \ | |
1270 | if (memory_address_p (MODE, X)) \ | |
1271 | goto WIN; \ | |
1272 | } \ | |
1273 | while (0) | |
8c5ca3b9 DE |
1274 | |
1275 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1276 | has an effect that depends on the machine mode it is used for. */ | |
ad126521 KI |
1277 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
1278 | do \ | |
1279 | { \ | |
1280 | if ( GET_CODE (ADDR) == PRE_DEC \ | |
1281 | || GET_CODE (ADDR) == PRE_INC \ | |
1282 | || GET_CODE (ADDR) == POST_INC \ | |
1283 | || GET_CODE (ADDR) == LO_SUM) \ | |
1284 | goto LABEL; \ | |
1285 | } \ | |
1286 | while (0) | |
8c5ca3b9 DE |
1287 | \f |
1288 | /* Condition code usage. */ | |
1289 | ||
a0ab749a | 1290 | /* Return nonzero if SELECT_CC_MODE will never return MODE for a |
8c5ca3b9 | 1291 | floating point inequality comparison. */ |
18543a22 | 1292 | #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ |
8c5ca3b9 DE |
1293 | \f |
1294 | /* Costs. */ | |
1295 | ||
8c5ca3b9 DE |
1296 | /* Compute extra cost of moving data between one register class |
1297 | and another. */ | |
cf011243 | 1298 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2 |
8c5ca3b9 DE |
1299 | |
1300 | /* Compute the cost of moving data between registers and memory. */ | |
1301 | /* Memory is 3 times as expensive as registers. | |
1302 | ??? Is that the right way to look at it? */ | |
5b8ae21f | 1303 | #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \ |
8c5ca3b9 DE |
1304 | (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) |
1305 | ||
1306 | /* The cost of a branch insn. */ | |
1307 | /* A value of 2 here causes GCC to avoid using branches in comparisons like | |
1308 | while (a < N && a). Branches aren't that expensive on the M32R so | |
1309 | we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ | |
56e2e762 | 1310 | #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1) |
8c5ca3b9 | 1311 | |
8c5ca3b9 DE |
1312 | /* Nonzero if access to memory by bytes is slow and undesirable. |
1313 | For RISC chips, it means that access to memory by bytes is no | |
1314 | better than access by words when possible, so grab a whole word | |
1315 | and maybe make use of that. */ | |
1316 | #define SLOW_BYTE_ACCESS 1 | |
1317 | ||
1318 | /* Define this macro if it is as good or better to call a constant | |
1319 | function address than to call an address kept in a register. */ | |
8c5ca3b9 | 1320 | #define NO_FUNCTION_CSE |
8c5ca3b9 DE |
1321 | \f |
1322 | /* Section selection. */ | |
1323 | ||
1324 | #define TEXT_SECTION_ASM_OP "\t.section .text" | |
1325 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
8c5ca3b9 | 1326 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
8c5ca3b9 | 1327 | |
8c5ca3b9 DE |
1328 | /* Define this macro if jump tables (for tablejump insns) should be |
1329 | output in the text section, along with the assembler instructions. | |
1330 | Otherwise, the readonly data section is used. | |
1331 | This macro is irrelevant if there is no separate readonly data section. */ | |
ad126521 | 1332 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) |
8c5ca3b9 | 1333 | \f |
ad126521 | 1334 | /* Position Independent Code. */ |
8c5ca3b9 DE |
1335 | |
1336 | /* The register number of the register used to address a table of static | |
1337 | data addresses in memory. In some cases this register is defined by a | |
1338 | processor's ``application binary interface'' (ABI). When this macro | |
1339 | is defined, RTL is generated for this register once, as with the stack | |
1340 | pointer and frame pointer registers. If this macro is not defined, it | |
1341 | is up to the machine-dependent files to allocate such a register (if | |
1342 | necessary). */ | |
ad126521 | 1343 | #define PIC_OFFSET_TABLE_REGNUM 12 |
8c5ca3b9 DE |
1344 | |
1345 | /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is | |
1346 | clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM | |
1347 | is not defined. */ | |
1348 | /* This register is call-saved on the M32R. */ | |
1349 | /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ | |
1350 | ||
1351 | /* By generating position-independent code, when two different programs (A | |
1352 | and B) share a common library (libC.a), the text of the library can be | |
1353 | shared whether or not the library is linked at the same address for both | |
1354 | programs. In some of these environments, position-independent code | |
1355 | requires not only the use of different addressing modes, but also | |
1356 | special code to enable the use of these addressing modes. | |
1357 | ||
1358 | The FINALIZE_PIC macro serves as a hook to emit these special | |
1359 | codes once the function is being compiled into assembly code, but not | |
1360 | before. (It is not done before, because in the case of compiling an | |
1361 | inline function, it would lead to multiple PIC prologues being | |
1362 | included in functions which used inline functions and were compiled to | |
1363 | assembly language.) */ | |
1364 | ||
ad126521 | 1365 | #define FINALIZE_PIC m32r_finalize_pic () |
8c5ca3b9 DE |
1366 | |
1367 | /* A C expression that is nonzero if X is a legitimate immediate | |
1368 | operand on the target machine when generating position independent code. | |
1369 | You can assume that X satisfies CONSTANT_P, so you need not | |
1370 | check this. You can also assume `flag_pic' is true, so you need not | |
1371 | check it either. You need not define this macro if all constants | |
1372 | (including SYMBOL_REF) can be immediate operands when generating | |
1373 | position independent code. */ | |
ad126521 | 1374 | #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) |
8c5ca3b9 DE |
1375 | \f |
1376 | /* Control the assembler format that we output. */ | |
1377 | ||
8c5ca3b9 DE |
1378 | /* A C string constant describing how to begin a comment in the target |
1379 | assembler language. The compiler assumes that the comment will | |
1380 | end at the end of the line. */ | |
1381 | #define ASM_COMMENT_START ";" | |
1382 | ||
1383 | /* Output to assembler file text saying following lines | |
1384 | may contain character constants, extra white space, comments, etc. */ | |
1385 | #define ASM_APP_ON "" | |
1386 | ||
1387 | /* Output to assembler file text saying following lines | |
1388 | no longer contain unusual constructs. */ | |
1389 | #define ASM_APP_OFF "" | |
1390 | ||
506a61b1 KG |
1391 | /* Globalizing directive for a label. */ |
1392 | #define GLOBAL_ASM_OP "\t.global\t" | |
8c5ca3b9 | 1393 | |
93a27b7b ZW |
1394 | /* We do not use DBX_LINES_FUNCTION_RELATIVE or |
1395 | dbxout_stab_value_internal_label_diff here because | |
1396 | we need to use .debugsym for the line label. */ | |
5b8ae21f | 1397 | |
3e487b21 | 1398 | #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \ |
56e2e762 NC |
1399 | do \ |
1400 | { \ | |
0b4828ef | 1401 | rtx begin_label = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);\ |
93a27b7b ZW |
1402 | char label[64]; \ |
1403 | ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \ | |
1404 | \ | |
1405 | dbxout_begin_stabn_sline (line); \ | |
1406 | assemble_name (file, label); \ | |
1407 | putc ('-', file); \ | |
1408 | assemble_name (file, begin_label); \ | |
1409 | fputs ("\n\t.debugsym ", file); \ | |
1410 | assemble_name (file, label); \ | |
1411 | putc ('\n', file); \ | |
e2cb732f ZW |
1412 | counter += 1; \ |
1413 | } \ | |
56e2e762 | 1414 | while (0) |
5b8ae21f | 1415 | |
8c5ca3b9 DE |
1416 | /* How to refer to registers in assembler output. |
1417 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
56e2e762 NC |
1418 | #ifndef SUBTARGET_REGISTER_NAMES |
1419 | #define SUBTARGET_REGISTER_NAMES | |
1420 | #endif | |
1421 | ||
1422 | #define REGISTER_NAMES \ | |
8c5ca3b9 DE |
1423 | { \ |
1424 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1425 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ | |
56e2e762 NC |
1426 | "ap", "cbit", "a0" \ |
1427 | SUBTARGET_REGISTER_NAMES \ | |
8c5ca3b9 DE |
1428 | } |
1429 | ||
1430 | /* If defined, a C initializer for an array of structures containing | |
1431 | a name and a register number. This macro defines additional names | |
1432 | for hard registers, thus allowing the `asm' option in declarations | |
1433 | to refer to registers using alternate names. */ | |
56e2e762 NC |
1434 | #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES |
1435 | #define SUBTARGET_ADDITIONAL_REGISTER_NAMES | |
1436 | #endif | |
1437 | ||
1438 | #define ADDITIONAL_REGISTER_NAMES \ | |
8c5ca3b9 DE |
1439 | { \ |
1440 | /*{ "gp", GP_REGNUM },*/ \ | |
1441 | { "r13", FRAME_POINTER_REGNUM }, \ | |
1442 | { "r14", RETURN_ADDR_REGNUM }, \ | |
1443 | { "r15", STACK_POINTER_REGNUM }, \ | |
56e2e762 | 1444 | SUBTARGET_ADDITIONAL_REGISTER_NAMES \ |
8c5ca3b9 DE |
1445 | } |
1446 | ||
1447 | /* A C expression which evaluates to true if CODE is a valid | |
1448 | punctuation character for use in the `PRINT_OPERAND' macro. */ | |
f540a7d3 | 1449 | extern char m32r_punct_chars[256]; |
8c5ca3b9 | 1450 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ |
56e2e762 | 1451 | m32r_punct_chars[(unsigned char) (CHAR)] |
8c5ca3b9 DE |
1452 | |
1453 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1454 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1455 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1456 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
56e2e762 | 1457 | m32r_print_operand (FILE, X, CODE) |
8c5ca3b9 DE |
1458 | |
1459 | /* A C compound statement to output to stdio stream STREAM the | |
1460 | assembler syntax for an instruction operand that is a memory | |
fb49053f | 1461 | reference whose address is ADDR. ADDR is an RTL expression. */ |
8c5ca3b9 | 1462 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
56e2e762 | 1463 | m32r_print_operand_address (FILE, ADDR) |
8c5ca3b9 DE |
1464 | |
1465 | /* If defined, C string expressions to be used for the `%R', `%L', | |
1466 | `%U', and `%I' options of `asm_fprintf' (see `final.c'). These | |
1467 | are useful when a single `md' file must support multiple assembler | |
1468 | formats. In that case, the various `tm.h' files can define these | |
1469 | macros differently. */ | |
ad126521 KI |
1470 | #define REGISTER_PREFIX "" |
1471 | #define LOCAL_LABEL_PREFIX ".L" | |
1472 | #define USER_LABEL_PREFIX "" | |
1473 | #define IMMEDIATE_PREFIX "#" | |
8c5ca3b9 DE |
1474 | |
1475 | /* This is how to output an element of a case-vector that is absolute. */ | |
56e2e762 NC |
1476 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
1477 | do \ | |
1478 | { \ | |
1479 | char label[30]; \ | |
1480 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1481 | fprintf (FILE, "\t.word\t"); \ | |
1482 | assemble_name (FILE, label); \ | |
1483 | fprintf (FILE, "\n"); \ | |
1484 | } \ | |
1485 | while (0) | |
8c5ca3b9 DE |
1486 | |
1487 | /* This is how to output an element of a case-vector that is relative. */ | |
56e2e762 NC |
1488 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ |
1489 | do \ | |
1490 | { \ | |
1491 | char label[30]; \ | |
1492 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1493 | fprintf (FILE, "\t.word\t"); \ | |
1494 | assemble_name (FILE, label); \ | |
1495 | fprintf (FILE, "-"); \ | |
1496 | ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ | |
1497 | assemble_name (FILE, label); \ | |
ad126521 | 1498 | fprintf (FILE, "\n"); \ |
56e2e762 NC |
1499 | } \ |
1500 | while (0) | |
8c5ca3b9 | 1501 | |
fc470718 R |
1502 | /* The desired alignment for the location counter at the beginning |
1503 | of a loop. */ | |
8c5ca3b9 DE |
1504 | /* On the M32R, align loops to 32 byte boundaries (cache line size) |
1505 | if -malign-loops. */ | |
fc470718 | 1506 | #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) |
8c5ca3b9 | 1507 | |
56e2e762 NC |
1508 | /* Define this to be the maximum number of insns to move around when moving |
1509 | a loop test from the top of a loop to the bottom | |
1510 | and seeing whether to duplicate it. The default is thirty. | |
1511 | ||
1512 | Loop unrolling currently doesn't like this optimization, so | |
1513 | disable doing if we are unrolling loops and saving space. */ | |
1514 | #define LOOP_TEST_THRESHOLD (optimize_size \ | |
1515 | && !flag_unroll_loops \ | |
1516 | && !flag_unroll_all_loops ? 2 : 30) | |
1517 | ||
8c5ca3b9 DE |
1518 | /* This is how to output an assembler line |
1519 | that says to advance the location counter | |
1520 | to a multiple of 2**LOG bytes. */ | |
1521 | /* .balign is used to avoid confusion. */ | |
56e2e762 NC |
1522 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
1523 | do \ | |
1524 | { \ | |
1525 | if ((LOG) != 0) \ | |
1526 | fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ | |
1527 | } \ | |
1528 | while (0) | |
8c5ca3b9 DE |
1529 | |
1530 | /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a | |
1531 | separate, explicit argument. If you define this macro, it is used in | |
1532 | place of `ASM_OUTPUT_COMMON', and gives you more flexibility in | |
1533 | handling the required alignment of the variable. The alignment is | |
1534 | specified as the number of bits. */ | |
1535 | ||
6e7b07a7 | 1536 | #define SCOMMON_ASM_OP "\t.scomm\t" |
8c5ca3b9 | 1537 | |
56e2e762 NC |
1538 | #undef ASM_OUTPUT_ALIGNED_COMMON |
1539 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
1540 | do \ | |
8c5ca3b9 | 1541 | { \ |
56e2e762 NC |
1542 | if (! TARGET_SDATA_NONE \ |
1543 | && (SIZE) > 0 && (SIZE) <= g_switch_value) \ | |
016c8440 | 1544 | fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ |
56e2e762 | 1545 | else \ |
016c8440 | 1546 | fprintf ((FILE), "%s", COMMON_ASM_OP); \ |
8c5ca3b9 | 1547 | assemble_name ((FILE), (NAME)); \ |
58e15542 | 1548 | fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ |
8c5ca3b9 | 1549 | } \ |
56e2e762 | 1550 | while (0) |
8c5ca3b9 | 1551 | |
cb1f9d03 KI |
1552 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
1553 | do \ | |
1554 | { \ | |
1555 | if (! TARGET_SDATA_NONE \ | |
1556 | && (SIZE) > 0 && (SIZE) <= g_switch_value) \ | |
1557 | named_section (0, ".sbss", 0); \ | |
1558 | else \ | |
1559 | bss_section (); \ | |
1560 | ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ | |
1561 | last_assemble_variable_decl = DECL; \ | |
1562 | ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ | |
1563 | ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ | |
1564 | } \ | |
56e2e762 | 1565 | while (0) |
8c5ca3b9 DE |
1566 | \f |
1567 | /* Debugging information. */ | |
1568 | ||
1569 | /* Generate DBX and DWARF debugging information. */ | |
ad126521 | 1570 | #define DBX_DEBUGGING_INFO 1 |
23532de9 | 1571 | #define DWARF2_DEBUGGING_INFO 1 |
8c5ca3b9 | 1572 | |
25941194 | 1573 | /* Use DWARF2 debugging info by default. */ |
56e2e762 | 1574 | #undef PREFERRED_DEBUGGING_TYPE |
25941194 | 1575 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
8c5ca3b9 | 1576 | |
8c5ca3b9 DE |
1577 | /* Turn off splitting of long stabs. */ |
1578 | #define DBX_CONTIN_LENGTH 0 | |
1579 | \f | |
1580 | /* Miscellaneous. */ | |
1581 | ||
1582 | /* Specify the machine mode that this machine uses | |
1583 | for the index in the tablejump instruction. */ | |
ad126521 | 1584 | #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) |
8c5ca3b9 | 1585 | |
8c5ca3b9 DE |
1586 | /* Define if operations between registers always perform the operation |
1587 | on the full register even if a narrower mode is specified. */ | |
1588 | #define WORD_REGISTER_OPERATIONS | |
1589 | ||
1590 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1591 | will either zero-extend or sign-extend. The value of this macro should | |
1592 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1593 | done, UNKNOWN if none. */ |
8c5ca3b9 DE |
1594 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
1595 | ||
ad126521 KI |
1596 | /* Max number of bytes we can move from memory |
1597 | to memory in one reasonably fast instruction. */ | |
8c5ca3b9 DE |
1598 | #define MOVE_MAX 4 |
1599 | ||
1600 | /* Define this to be nonzero if shift instructions ignore all but the low-order | |
1601 | few bits. */ | |
1602 | #define SHIFT_COUNT_TRUNCATED 1 | |
1603 | ||
1604 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1605 | is done just by pretending it is already truncated. */ | |
1606 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1607 | ||
8c5ca3b9 DE |
1608 | /* Specify the machine mode that pointers have. |
1609 | After generation of rtl, the compiler makes no further distinction | |
1610 | between pointers and any other objects of this machine mode. */ | |
1611 | /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has | |
56e2e762 | 1612 | it's own problems (you have to add extendpsisi2 and truncsipsi2). |
8c5ca3b9 DE |
1613 | Try to avoid it. */ |
1614 | #define Pmode SImode | |
1615 | ||
1616 | /* A function address in a call instruction. */ | |
1617 | #define FUNCTION_MODE SImode | |
8c5ca3b9 DE |
1618 | \f |
1619 | /* Define the information needed to generate branch and scc insns. This is | |
1620 | stored from the compare operation. Note that we can't use "rtx" here | |
1621 | since it hasn't been defined! */ | |
2b7972b0 MM |
1622 | extern struct rtx_def * m32r_compare_op0; |
1623 | extern struct rtx_def * m32r_compare_op1; | |
8c5ca3b9 | 1624 | |
71cc389b | 1625 | /* M32R function types. */ |
2b7972b0 MM |
1626 | enum m32r_function_type |
1627 | { | |
8c5ca3b9 DE |
1628 | M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT |
1629 | }; | |
56e2e762 NC |
1630 | |
1631 | #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) | |
2b7972b0 | 1632 | |
22a14e0d KH |
1633 | /* The maximum number of bytes to copy using pairs of load/store instructions. |
1634 | If a block is larger than this then a loop will be generated to copy | |
1635 | MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice. | |
1636 | A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte | |
1637 | string copy in it. */ | |
1638 | #define MAX_MOVE_BYTES 32 |