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1f92da87 | 1 | /* Definitions of target machine for GNU compiler, Renesas M32R cpu. |
22a14e0d | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
6a728a2d | 3 | 2005, 2006 Free Software Foundation, Inc. |
8c5ca3b9 | 4 | |
1f92da87 | 5 | This file is part of GCC. |
8c5ca3b9 | 6 | |
1f92da87 NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 2, or (at your | |
10 | option) any later version. | |
8c5ca3b9 | 11 | |
1f92da87 NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
8c5ca3b9 | 16 | |
1f92da87 NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING. If not, write to | |
39d14dda KC |
19 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
8c5ca3b9 DE |
21 | |
22 | /* Things to do: | |
23 | - longlong.h? | |
24 | */ | |
25 | ||
8c5ca3b9 DE |
26 | #undef SWITCH_TAKES_ARG |
27 | #undef WORD_SWITCH_TAKES_ARG | |
28 | #undef HANDLE_SYSV_PRAGMA | |
29 | #undef SIZE_TYPE | |
30 | #undef PTRDIFF_TYPE | |
31 | #undef WCHAR_TYPE | |
32 | #undef WCHAR_TYPE_SIZE | |
56e2e762 NC |
33 | #undef TARGET_VERSION |
34 | #undef CPP_SPEC | |
35 | #undef ASM_SPEC | |
36 | #undef LINK_SPEC | |
37 | #undef STARTFILE_SPEC | |
38 | #undef ENDFILE_SPEC | |
ad126521 KI |
39 | |
40 | #undef ASM_APP_ON | |
41 | #undef ASM_APP_OFF | |
8c5ca3b9 | 42 | \f |
de41e41c BE |
43 | |
44 | /* M32R/X overrides. */ | |
45 | /* Print subsidiary information on the compiler version in use. */ | |
6975bd2c | 46 | #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)"); |
de41e41c BE |
47 | |
48 | /* Additional flags for the preprocessor. */ | |
6975bd2c KI |
49 | #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ |
50 | %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ | |
51 | %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ | |
52 | " | |
53 | ||
de41e41c BE |
54 | /* Assembler switches. */ |
55 | #define ASM_CPU_SPEC \ | |
6975bd2c | 56 | "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" |
de41e41c BE |
57 | |
58 | /* Use m32rx specific crt0/crtinit/crtfini files. */ | |
59 | #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" | |
60 | #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" | |
61 | ||
de41e41c BE |
62 | /* Define this macro as a C expression for the initializer of an array of |
63 | strings to tell the driver program which options are defaults for this | |
64 | target and thus do not need to be handled specially when using | |
65 | `MULTILIB_OPTIONS'. */ | |
66 | #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" | |
67 | ||
68 | /* Number of additional registers the subtarget defines. */ | |
69 | #define SUBTARGET_NUM_REGISTERS 1 | |
70 | ||
71 | /* 1 for registers that cannot be allocated. */ | |
72 | #define SUBTARGET_FIXED_REGISTERS , 1 | |
73 | ||
74 | /* 1 for registers that are not available across function calls. */ | |
75 | #define SUBTARGET_CALL_USED_REGISTERS , 1 | |
76 | ||
77 | /* Order to allocate model specific registers. */ | |
78 | #define SUBTARGET_REG_ALLOC_ORDER , 19 | |
79 | ||
80 | /* Registers which are accumulators. */ | |
81 | #define SUBTARGET_REG_CLASS_ACCUM 0x80000 | |
82 | ||
83 | /* All registers added. */ | |
84 | #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM | |
85 | ||
86 | /* Additional accumulator registers. */ | |
87 | #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) | |
88 | ||
89 | /* Define additional register names. */ | |
90 | #define SUBTARGET_REGISTER_NAMES , "a1" | |
91 | /* end M32R/X overrides. */ | |
92 | ||
8c5ca3b9 | 93 | /* Print subsidiary information on the compiler version in use. */ |
56e2e762 | 94 | #ifndef TARGET_VERSION |
8c5ca3b9 | 95 | #define TARGET_VERSION fprintf (stderr, " (m32r)") |
56e2e762 | 96 | #endif |
2b7972b0 | 97 | |
ad126521 | 98 | /* Switch Recognition by gcc.c. Add -G xx support. */ |
8c5ca3b9 | 99 | |
56e2e762 | 100 | #undef SWITCH_TAKES_ARG |
8c5ca3b9 DE |
101 | #define SWITCH_TAKES_ARG(CHAR) \ |
102 | (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') | |
103 | ||
104 | /* Names to predefine in the preprocessor for this target machine. */ | |
105 | /* __M32R__ is defined by the existing compiler so we use that. */ | |
cc956ba2 NB |
106 | #define TARGET_CPU_CPP_BUILTINS() \ |
107 | do \ | |
108 | { \ | |
109 | builtin_define ("__M32R__"); \ | |
df68f43b | 110 | builtin_define ("__m32r__"); \ |
cc956ba2 NB |
111 | builtin_assert ("cpu=m32r"); \ |
112 | builtin_assert ("machine=m32r"); \ | |
ad126521 KI |
113 | builtin_define (TARGET_BIG_ENDIAN \ |
114 | ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ | |
cc956ba2 NB |
115 | } \ |
116 | while (0) | |
8c5ca3b9 | 117 | |
56e2e762 NC |
118 | /* This macro defines names of additional specifications to put in the specs |
119 | that can be used in various specifications like CC1_SPEC. Its definition | |
120 | is an initializer with a subgrouping for each command option. | |
8c5ca3b9 | 121 | |
56e2e762 | 122 | Each subgrouping contains a string constant, that defines the |
7ec022b2 | 123 | specification name, and a string constant that used by the GCC driver |
56e2e762 | 124 | program. |
8c5ca3b9 | 125 | |
56e2e762 | 126 | Do not define this macro if it does not need to do anything. */ |
2b7972b0 | 127 | |
56e2e762 NC |
128 | #ifndef SUBTARGET_EXTRA_SPECS |
129 | #define SUBTARGET_EXTRA_SPECS | |
8c5ca3b9 DE |
130 | #endif |
131 | ||
56e2e762 NC |
132 | #ifndef ASM_CPU_SPEC |
133 | #define ASM_CPU_SPEC "" | |
134 | #endif | |
8c5ca3b9 | 135 | |
56e2e762 NC |
136 | #ifndef CPP_CPU_SPEC |
137 | #define CPP_CPU_SPEC "" | |
138 | #endif | |
139 | ||
140 | #ifndef CC1_CPU_SPEC | |
141 | #define CC1_CPU_SPEC "" | |
142 | #endif | |
143 | ||
144 | #ifndef LINK_CPU_SPEC | |
145 | #define LINK_CPU_SPEC "" | |
146 | #endif | |
147 | ||
148 | #ifndef STARTFILE_CPU_SPEC | |
149 | #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" | |
150 | #endif | |
151 | ||
152 | #ifndef ENDFILE_CPU_SPEC | |
153 | #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" | |
154 | #endif | |
155 | ||
156 | #ifndef RELAX_SPEC | |
ad126521 | 157 | #if 0 /* Not supported yet. */ |
56e2e762 | 158 | #define RELAX_SPEC "%{mrelax:-relax}" |
8c5ca3b9 | 159 | #else |
56e2e762 NC |
160 | #define RELAX_SPEC "" |
161 | #endif | |
8c5ca3b9 DE |
162 | #endif |
163 | ||
56e2e762 NC |
164 | #define EXTRA_SPECS \ |
165 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
166 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
167 | { "cc1_cpu", CC1_CPU_SPEC }, \ | |
168 | { "link_cpu", LINK_CPU_SPEC }, \ | |
169 | { "startfile_cpu", STARTFILE_CPU_SPEC }, \ | |
170 | { "endfile_cpu", ENDFILE_CPU_SPEC }, \ | |
171 | { "relax", RELAX_SPEC }, \ | |
172 | SUBTARGET_EXTRA_SPECS | |
8c5ca3b9 | 173 | |
2a2001be IK |
174 | #define CPP_SPEC "%(cpp_cpu)" |
175 | ||
ad126521 | 176 | #undef CC1_SPEC |
56e2e762 | 177 | #define CC1_SPEC "%{G*} %(cc1_cpu)" |
2b7972b0 | 178 | |
56e2e762 NC |
179 | /* Options to pass on to the assembler. */ |
180 | #undef ASM_SPEC | |
29f9d52d | 181 | #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}" |
56e2e762 | 182 | |
56e2e762 NC |
183 | #define LINK_SPEC "%{v} %(link_cpu) %(relax)" |
184 | ||
185 | #undef STARTFILE_SPEC | |
186 | #define STARTFILE_SPEC "%(startfile_cpu)" | |
187 | ||
188 | #undef ENDFILE_SPEC | |
189 | #define ENDFILE_SPEC "%(endfile_cpu)" | |
8c5ca3b9 DE |
190 | |
191 | #undef LIB_SPEC | |
192 | \f | |
193 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
194 | ||
6975bd2c KI |
195 | #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) |
196 | ||
97b73103 RS |
197 | #ifndef TARGET_LITTLE_ENDIAN |
198 | #define TARGET_LITTLE_ENDIAN 0 | |
8a897efe | 199 | #endif |
97b73103 | 200 | #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) |
8a897efe KI |
201 | |
202 | /* This defaults us to m32r. */ | |
203 | #ifndef TARGET_CPU_DEFAULT | |
204 | #define TARGET_CPU_DEFAULT 0 | |
ad126521 KI |
205 | #endif |
206 | ||
8c5ca3b9 DE |
207 | /* Code Models |
208 | ||
209 | Code models are used to select between two choices of two separate | |
210 | possibilities (address space size, call insn to use): | |
211 | ||
212 | small: addresses use 24 bits, use bl to make calls | |
213 | medium: addresses use 32 bits, use bl to make calls (*1) | |
214 | large: addresses use 32 bits, use seth/add3/jl to make calls (*2) | |
215 | ||
216 | The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but | |
217 | using this one doesn't make much sense. | |
218 | ||
219 | (*1) The linker may eventually be able to relax seth/add3 -> ld24. | |
220 | (*2) The linker may eventually be able to relax seth/add3/jl -> bl. | |
221 | ||
222 | Internally these are recorded as TARGET_ADDR{24,32} and | |
223 | TARGET_CALL{26,32}. | |
224 | ||
225 | The __model__ attribute can be used to select the code model to use when | |
226 | accessing particular objects. */ | |
227 | ||
228 | enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE }; | |
229 | ||
230 | extern enum m32r_model m32r_model; | |
ad126521 | 231 | #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL) |
8c5ca3b9 | 232 | #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM) |
ad126521 KI |
233 | #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE) |
234 | #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL) | |
235 | #define TARGET_ADDR32 (! TARGET_ADDR24) | |
236 | #define TARGET_CALL26 (! TARGET_CALL32) | |
237 | #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE) | |
8c5ca3b9 DE |
238 | |
239 | /* The default is the small model. */ | |
56e2e762 | 240 | #ifndef M32R_MODEL_DEFAULT |
97b73103 | 241 | #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL |
56e2e762 | 242 | #endif |
8c5ca3b9 DE |
243 | |
244 | /* Small Data Area | |
245 | ||
246 | The SDA consists of sections .sdata, .sbss, and .scommon. | |
247 | .scommon isn't a real section, symbols in it have their section index | |
248 | set to SHN_M32R_SCOMMON, though support for it exists in the linker script. | |
249 | ||
250 | Two switches control the SDA: | |
251 | ||
252 | -G NNN - specifies the maximum size of variable to go in the SDA | |
253 | ||
254 | -msdata=foo - specifies how such variables are handled | |
255 | ||
256 | -msdata=none - small data area is disabled | |
257 | ||
258 | -msdata=sdata - small data goes in the SDA, special code isn't | |
259 | generated to use it, and special relocs aren't | |
260 | generated | |
261 | ||
262 | -msdata=use - small data goes in the SDA, special code is generated | |
263 | to use the SDA and special relocs are generated | |
264 | ||
265 | The SDA is not multilib'd, it isn't necessary. | |
266 | MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd | |
267 | libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use | |
268 | -msdata=use will successfully link with them (references in header files | |
269 | will cause the compiler to emit code that refers to library objects in | |
270 | .data). ??? There can be a problem if the user passes a -G value greater | |
271 | than the default and a library object in a header file is that size. | |
272 | The default is 8 so this should be rare - if it occurs the user | |
ad126521 | 273 | is required to rebuild the libraries or use a smaller value for -G. */ |
8c5ca3b9 DE |
274 | |
275 | /* Maximum size of variables that go in .sdata/.sbss. | |
276 | The -msdata=foo switch also controls how small variables are handled. */ | |
56e2e762 | 277 | #ifndef SDATA_DEFAULT_SIZE |
8c5ca3b9 | 278 | #define SDATA_DEFAULT_SIZE 8 |
56e2e762 | 279 | #endif |
8c5ca3b9 | 280 | |
8c5ca3b9 DE |
281 | enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE }; |
282 | ||
283 | extern enum m32r_sdata m32r_sdata; | |
ad126521 | 284 | #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE) |
8c5ca3b9 | 285 | #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA) |
ad126521 | 286 | #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE) |
8c5ca3b9 DE |
287 | |
288 | /* Default is to disable the SDA | |
289 | [for upward compatibility with previous toolchains]. */ | |
56e2e762 | 290 | #ifndef M32R_SDATA_DEFAULT |
97b73103 | 291 | #define M32R_SDATA_DEFAULT M32R_SDATA_NONE |
56e2e762 | 292 | #endif |
8c5ca3b9 DE |
293 | |
294 | /* Define this macro as a C expression for the initializer of an array of | |
2b7972b0 | 295 | strings to tell the driver program which options are defaults for this |
8c5ca3b9 DE |
296 | target and thus do not need to be handled specially when using |
297 | `MULTILIB_OPTIONS'. */ | |
56e2e762 NC |
298 | #ifndef SUBTARGET_MULTILIB_DEFAULTS |
299 | #define SUBTARGET_MULTILIB_DEFAULTS | |
300 | #endif | |
301 | ||
302 | #ifndef MULTILIB_DEFAULTS | |
303 | #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } | |
304 | #endif | |
8c5ca3b9 DE |
305 | |
306 | /* Sometimes certain combinations of command options do not make | |
307 | sense on a particular target machine. You can define a macro | |
308 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
309 | defined, is executed once just after all the command options have | |
310 | been parsed. | |
311 | ||
312 | Don't use this macro to turn on various extra optimizations for | |
313 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
314 | ||
56e2e762 NC |
315 | #ifndef SUBTARGET_OVERRIDE_OPTIONS |
316 | #define SUBTARGET_OVERRIDE_OPTIONS | |
317 | #endif | |
318 | ||
319 | #define OVERRIDE_OPTIONS \ | |
320 | do \ | |
321 | { \ | |
322 | /* These need to be done at start up. \ | |
323 | It's convenient to do them here. */ \ | |
324 | m32r_init (); \ | |
325 | SUBTARGET_OVERRIDE_OPTIONS \ | |
326 | } \ | |
327 | while (0) | |
328 | ||
329 | #ifndef SUBTARGET_OPTIMIZATION_OPTIONS | |
330 | #define SUBTARGET_OPTIMIZATION_OPTIONS | |
331 | #endif | |
332 | ||
333 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ | |
334 | do \ | |
335 | { \ | |
336 | if (LEVEL == 1) \ | |
337 | flag_regmove = TRUE; \ | |
338 | \ | |
339 | if (SIZE) \ | |
340 | { \ | |
341 | flag_omit_frame_pointer = TRUE; \ | |
56e2e762 NC |
342 | } \ |
343 | \ | |
344 | SUBTARGET_OPTIMIZATION_OPTIONS \ | |
345 | } \ | |
346 | while (0) | |
8c5ca3b9 DE |
347 | |
348 | /* Define this macro if debugging can be performed even without a | |
7ec022b2 | 349 | frame pointer. If this macro is defined, GCC will turn on the |
8c5ca3b9 DE |
350 | `-fomit-frame-pointer' option whenever `-O' is specified. */ |
351 | #define CAN_DEBUG_WITHOUT_FP | |
352 | \f | |
353 | /* Target machine storage layout. */ | |
354 | ||
8c5ca3b9 DE |
355 | /* Define this if most significant bit is lowest numbered |
356 | in instructions that operate on numbered bit-fields. */ | |
357 | #define BITS_BIG_ENDIAN 1 | |
358 | ||
359 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
ad126521 | 360 | #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
8c5ca3b9 DE |
361 | |
362 | /* Define this if most significant word of a multiword number is the lowest | |
363 | numbered. */ | |
ad126521 | 364 | #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
8c5ca3b9 DE |
365 | |
366 | /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must | |
367 | be a constant value with the same meaning as WORDS_BIG_ENDIAN, | |
368 | which will be used only when compiling libgcc2.c. Typically the | |
369 | value will be set based on preprocessor defines. */ | |
370 | /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/ | |
371 | ||
8c5ca3b9 DE |
372 | /* Width of a word, in units (bytes). */ |
373 | #define UNITS_PER_WORD 4 | |
374 | ||
375 | /* Define this macro if it is advisable to hold scalars in registers | |
376 | in a wider mode than that declared by the program. In such cases, | |
377 | the value is constrained to be within the bounds of the declared | |
378 | type, but kept valid in the wider mode. The signedness of the | |
379 | extension may differ from that of the type. */ | |
56e2e762 NC |
380 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
381 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
382 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
383 | { \ | |
384 | (MODE) = SImode; \ | |
385 | } | |
8c5ca3b9 | 386 | |
8c5ca3b9 DE |
387 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
388 | #define PARM_BOUNDARY 32 | |
389 | ||
390 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
391 | #define STACK_BOUNDARY 32 | |
392 | ||
393 | /* ALIGN FRAMES on word boundaries */ | |
ad126521 | 394 | #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) |
8c5ca3b9 DE |
395 | |
396 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
397 | #define FUNCTION_BOUNDARY 32 | |
398 | ||
399 | /* Alignment of field after `int : 0' in a structure. */ | |
400 | #define EMPTY_FIELD_BOUNDARY 32 | |
401 | ||
402 | /* Every structure's size must be a multiple of this. */ | |
403 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
404 | ||
43a88a8c | 405 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
8c5ca3b9 DE |
406 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
407 | ||
408 | /* No data type wants to be aligned rounder than this. */ | |
409 | #define BIGGEST_ALIGNMENT 32 | |
410 | ||
411 | /* The best alignment to use in cases where we have a choice. */ | |
412 | #define FASTEST_ALIGNMENT 32 | |
413 | ||
414 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
56e2e762 | 415 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
8c5ca3b9 DE |
416 | ((TREE_CODE (EXP) == STRING_CST \ |
417 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
418 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
419 | ||
420 | /* Make arrays of chars word-aligned for the same reasons. */ | |
56e2e762 NC |
421 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
422 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
423 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
8c5ca3b9 DE |
424 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
425 | ||
426 | /* Set this nonzero if move instructions will actually fail to work | |
427 | when given unaligned data. */ | |
428 | #define STRICT_ALIGNMENT 1 | |
ad126521 KI |
429 | |
430 | /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ | |
431 | #define LABEL_ALIGN(insn) 2 | |
8c5ca3b9 DE |
432 | \f |
433 | /* Layout of source language data types. */ | |
434 | ||
435 | #define SHORT_TYPE_SIZE 16 | |
436 | #define INT_TYPE_SIZE 32 | |
437 | #define LONG_TYPE_SIZE 32 | |
438 | #define LONG_LONG_TYPE_SIZE 64 | |
439 | #define FLOAT_TYPE_SIZE 32 | |
440 | #define DOUBLE_TYPE_SIZE 64 | |
441 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
442 | ||
443 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
444 | #define DEFAULT_SIGNED_CHAR 1 | |
445 | ||
446 | #define SIZE_TYPE "long unsigned int" | |
447 | #define PTRDIFF_TYPE "long int" | |
448 | #define WCHAR_TYPE "short unsigned int" | |
449 | #define WCHAR_TYPE_SIZE 16 | |
8c5ca3b9 DE |
450 | \f |
451 | /* Standard register usage. */ | |
452 | ||
453 | /* Number of actual hardware registers. | |
454 | The hardware registers are assigned numbers for the compiler | |
455 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
456 | All registers that the compiler knows about must be given numbers, | |
457 | even those that are not normally considered general registers. */ | |
56e2e762 NC |
458 | |
459 | #define M32R_NUM_REGISTERS 19 | |
460 | ||
461 | #ifndef SUBTARGET_NUM_REGISTERS | |
462 | #define SUBTARGET_NUM_REGISTERS 0 | |
463 | #endif | |
464 | ||
465 | #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) | |
2b7972b0 | 466 | |
8c5ca3b9 DE |
467 | /* 1 for registers that have pervasive standard uses |
468 | and are not available for the register allocator. | |
469 | ||
470 | 0-3 - arguments/results | |
471 | 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] | |
472 | 6 - call used, gptmp | |
473 | 7 - call used, static chain pointer | |
474 | 8-11 - call saved | |
475 | 12 - call saved [reserved for global pointer] | |
476 | 13 - frame pointer | |
477 | 14 - subroutine link register | |
478 | 15 - stack pointer | |
479 | 16 - arg pointer | |
480 | 17 - carry flag | |
56e2e762 | 481 | 18 - accumulator |
de41e41c | 482 | 19 - accumulator 1 in the m32r/x |
8c5ca3b9 DE |
483 | By default, the extension registers are not available. */ |
484 | ||
56e2e762 NC |
485 | #ifndef SUBTARGET_FIXED_REGISTERS |
486 | #define SUBTARGET_FIXED_REGISTERS | |
487 | #endif | |
8c5ca3b9 | 488 | |
56e2e762 NC |
489 | #define FIXED_REGISTERS \ |
490 | { \ | |
491 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
492 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
493 | 1, 1, 1 \ | |
494 | SUBTARGET_FIXED_REGISTERS \ | |
495 | } | |
2b7972b0 | 496 | |
8c5ca3b9 DE |
497 | /* 1 for registers not available across function calls. |
498 | These must include the FIXED_REGISTERS and also any | |
499 | registers that can be used without being saved. | |
500 | The latter must include the registers where values are returned | |
501 | and the register where structure-value addresses are passed. | |
502 | Aside from that, you can include as many other registers as you like. */ | |
503 | ||
56e2e762 NC |
504 | #ifndef SUBTARGET_CALL_USED_REGISTERS |
505 | #define SUBTARGET_CALL_USED_REGISTERS | |
506 | #endif | |
8c5ca3b9 | 507 | |
56e2e762 NC |
508 | #define CALL_USED_REGISTERS \ |
509 | { \ | |
510 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
511 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
512 | 1, 1, 1 \ | |
513 | SUBTARGET_CALL_USED_REGISTERS \ | |
514 | } | |
2b7972b0 | 515 | |
69a53ee8 KI |
516 | #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS |
517 | ||
8c5ca3b9 DE |
518 | /* Zero or more C statements that may conditionally modify two variables |
519 | `fixed_regs' and `call_used_regs' (both of type `char []') after they | |
520 | have been initialized from the two preceding macros. | |
521 | ||
522 | This is necessary in case the fixed or call-clobbered registers depend | |
523 | on target flags. | |
524 | ||
525 | You need not define this macro if it has no work to do. */ | |
526 | ||
56e2e762 NC |
527 | #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
528 | #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
ad126521 KI |
529 | #else |
530 | #define CONDITIONAL_REGISTER_USAGE \ | |
531 | do \ | |
532 | { \ | |
533 | if (flag_pic) \ | |
69a53ee8 KI |
534 | { \ |
535 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
536 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
537 | } \ | |
ad126521 KI |
538 | } \ |
539 | while (0) | |
56e2e762 | 540 | #endif |
8c5ca3b9 DE |
541 | |
542 | /* If defined, an initializer for a vector of integers, containing the | |
7ec022b2 | 543 | numbers of hard registers in the order in which GCC should |
8c5ca3b9 | 544 | prefer to use them (from most preferred to least). */ |
56e2e762 NC |
545 | |
546 | #ifndef SUBTARGET_REG_ALLOC_ORDER | |
547 | #define SUBTARGET_REG_ALLOC_ORDER | |
548 | #endif | |
549 | ||
ad126521 | 550 | #if 1 /* Better for int code. */ |
56e2e762 NC |
551 | #define REG_ALLOC_ORDER \ |
552 | { \ | |
553 | 4, 5, 6, 7, 2, 3, 8, 9, 10, \ | |
554 | 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ | |
555 | SUBTARGET_REG_ALLOC_ORDER \ | |
556 | } | |
557 | ||
ad126521 | 558 | #else /* Better for fp code at expense of int code. */ |
56e2e762 NC |
559 | #define REG_ALLOC_ORDER \ |
560 | { \ | |
561 | 0, 1, 2, 3, 4, 5, 6, 7, 8, \ | |
562 | 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ | |
563 | SUBTARGET_REG_ALLOC_ORDER \ | |
564 | } | |
8c5ca3b9 DE |
565 | #endif |
566 | ||
567 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
568 | to hold something of mode MODE. | |
569 | This is ordinarily the length in words of a value of mode MODE | |
570 | but can be less for certain modes in special long registers. */ | |
571 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
ad126521 | 572 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
8c5ca3b9 DE |
573 | |
574 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
0139adca | 575 | extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; |
8c5ca3b9 DE |
576 | extern unsigned int m32r_mode_class[]; |
577 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
ad126521 | 578 | ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0) |
8c5ca3b9 DE |
579 | |
580 | /* A C expression that is nonzero if it is desirable to choose | |
581 | register allocation so as to avoid move instructions between a | |
582 | value of mode MODE1 and a value of mode MODE2. | |
583 | ||
584 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, | |
585 | MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, | |
586 | MODE2)' must be zero. */ | |
587 | ||
588 | /* Tie QI/HI/SI modes together. */ | |
ad126521 KI |
589 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
590 | ( GET_MODE_CLASS (MODE1) == MODE_INT \ | |
591 | && GET_MODE_CLASS (MODE2) == MODE_INT \ | |
592 | && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ | |
593 | && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) | |
a398a822 KI |
594 | |
595 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
596 | m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
8c5ca3b9 DE |
597 | \f |
598 | /* Register classes and constants. */ | |
599 | ||
600 | /* Define the classes of registers for register constraints in the | |
601 | machine description. Also define ranges of constants. | |
602 | ||
603 | One of the classes must always be named ALL_REGS and include all hard regs. | |
604 | If there is more than one class, another class must be named NO_REGS | |
605 | and contain no registers. | |
606 | ||
607 | The name GENERAL_REGS must be the name of a class (or an alias for | |
608 | another name such as ALL_REGS). This is the class of registers | |
609 | that is allowed by "g" or "r" in a register constraint. | |
610 | Also, registers outside this class are allocated only when | |
611 | instructions express preferences for them. | |
612 | ||
613 | The classes must be numbered in nondecreasing order; that is, | |
614 | a larger-numbered class must never be contained completely | |
615 | in a smaller-numbered class. | |
616 | ||
617 | For any two classes, it is very desirable that there be another | |
618 | class that represents their union. | |
619 | ||
620 | It is important that any condition codes have class NO_REGS. | |
621 | See `register_operand'. */ | |
622 | ||
56e2e762 NC |
623 | enum reg_class |
624 | { | |
625 | NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES | |
8c5ca3b9 DE |
626 | }; |
627 | ||
56e2e762 | 628 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
8c5ca3b9 | 629 | |
71cc389b | 630 | /* Give names of register classes as strings for dump file. */ |
8c5ca3b9 | 631 | #define REG_CLASS_NAMES \ |
56e2e762 | 632 | { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } |
8c5ca3b9 DE |
633 | |
634 | /* Define which registers fit in which classes. | |
635 | This is an initializer for a vector of HARD_REG_SET | |
636 | of length N_REG_CLASSES. */ | |
637 | ||
56e2e762 NC |
638 | #ifndef SUBTARGET_REG_CLASS_CARRY |
639 | #define SUBTARGET_REG_CLASS_CARRY 0 | |
640 | #endif | |
641 | ||
642 | #ifndef SUBTARGET_REG_CLASS_ACCUM | |
643 | #define SUBTARGET_REG_CLASS_ACCUM 0 | |
644 | #endif | |
645 | ||
646 | #ifndef SUBTARGET_REG_CLASS_GENERAL | |
647 | #define SUBTARGET_REG_CLASS_GENERAL 0 | |
648 | #endif | |
649 | ||
650 | #ifndef SUBTARGET_REG_CLASS_ALL | |
651 | #define SUBTARGET_REG_CLASS_ALL 0 | |
652 | #endif | |
8c5ca3b9 | 653 | |
56e2e762 NC |
654 | #define REG_CLASS_CONTENTS \ |
655 | { \ | |
656 | { 0x00000 }, \ | |
657 | { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ | |
658 | { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ | |
659 | { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ | |
660 | { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ | |
661 | } | |
2b7972b0 | 662 | |
8c5ca3b9 DE |
663 | /* The same information, inverted: |
664 | Return the class number of the smallest class containing | |
665 | reg number REGNO. This could be a conditional expression | |
666 | or could index an array. */ | |
2b7972b0 | 667 | extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
56e2e762 | 668 | #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) |
8c5ca3b9 DE |
669 | |
670 | /* The class value for index registers, and the one for base regs. */ | |
671 | #define INDEX_REG_CLASS GENERAL_REGS | |
672 | #define BASE_REG_CLASS GENERAL_REGS | |
673 | ||
ad126521 KI |
674 | #define REG_CLASS_FROM_LETTER(C) \ |
675 | ( (C) == 'c' ? CARRY_REG \ | |
676 | : (C) == 'a' ? ACCUM_REGS \ | |
677 | : NO_REGS) | |
8c5ca3b9 DE |
678 | |
679 | /* These assume that REGNO is a hard or pseudo reg number. | |
680 | They give nonzero only if REGNO is a hard reg of the suitable class | |
681 | or a pseudo reg currently allocated to a suitable hard reg. | |
682 | Since they use reg_renumber, they are safe only once reg_renumber | |
683 | has been allocated, which happens in local-alloc.c. */ | |
684 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
ad126521 KI |
685 | ((REGNO) < FIRST_PSEUDO_REGISTER \ |
686 | ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ | |
687 | : GPR_P (reg_renumber[REGNO])) | |
688 | ||
8c5ca3b9 DE |
689 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) |
690 | ||
691 | /* Given an rtx X being reloaded into a reg required to be | |
692 | in class CLASS, return the class of reg to actually use. | |
693 | In general this is just CLASS; but on some machines | |
694 | in some cases it is preferable to use a more restrictive class. */ | |
ad126521 | 695 | #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) |
8c5ca3b9 DE |
696 | |
697 | /* Return the maximum number of consecutive registers | |
698 | needed to represent mode MODE in a register of class CLASS. */ | |
699 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
ad126521 | 700 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
8c5ca3b9 DE |
701 | |
702 | /* The letters I, J, K, L, M, N, O, P in a register constraint string | |
703 | can be used to stand for particular ranges of immediate operands. | |
704 | This macro defines what the ranges are. | |
705 | C is the letter, and VALUE is a constant value. | |
706 | Return 1 if VALUE is in the range specified by C. */ | |
707 | /* 'I' is used for 8 bit signed immediates. | |
708 | 'J' is used for 16 bit signed immediates. | |
709 | 'K' is used for 16 bit unsigned immediates. | |
710 | 'L' is used for 16 bit immediates left shifted by 16 (sign ???). | |
711 | 'M' is used for 24 bit unsigned immediates. | |
712 | 'N' is used for any 32 bit non-symbolic value. | |
713 | 'O' is used for 5 bit unsigned immediates (shift count). | |
714 | 'P' is used for 16 bit signed immediates for compares | |
715 | (values in the range -32767 to +32768). */ | |
716 | ||
56e2e762 NC |
717 | /* Return true if a value is inside a range. */ |
718 | #define IN_RANGE_P(VALUE, LOW, HIGH) \ | |
719 | (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ | |
720 | <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) | |
721 | ||
722 | /* Local to this file. */ | |
ad126521 KI |
723 | #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f) |
724 | #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) | |
725 | #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) | |
726 | #define UPPER16_P(X) (((X) & 0xffff) == 0 \ | |
727 | && ((X) >> 16) >= - 0x8000 \ | |
728 | && ((X) >> 16) <= 0x7fff) | |
729 | #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) | |
730 | #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) | |
731 | #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff) | |
732 | #define UINT5_P(X) ((X) >= 0 && (X) < 32) | |
5b8ae21f | 733 | #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128) |
8c5ca3b9 | 734 | |
5b8ae21f | 735 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
ad126521 KI |
736 | ( (C) == 'I' ? INT8_P (VALUE) \ |
737 | : (C) == 'J' ? INT16_P (VALUE) \ | |
738 | : (C) == 'K' ? UINT16_P (VALUE) \ | |
739 | : (C) == 'L' ? UPPER16_P (VALUE) \ | |
740 | : (C) == 'M' ? UINT24_P (VALUE) \ | |
741 | : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \ | |
742 | : (C) == 'O' ? UINT5_P (VALUE) \ | |
743 | : (C) == 'P' ? CMP_INT16_P (VALUE) \ | |
744 | : 0) | |
8c5ca3b9 DE |
745 | |
746 | /* Similar, but for floating constants, and defining letters G and H. | |
747 | Here VALUE is the CONST_DOUBLE rtx itself. | |
748 | For the m32r, handle a few constants inline. | |
749 | ??? We needn't treat DI and DF modes differently, but for now we do. */ | |
ad126521 KI |
750 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
751 | ( (C) == 'G' ? easy_di_const (VALUE) \ | |
752 | : (C) == 'H' ? easy_df_const (VALUE) \ | |
753 | : 0) | |
8c5ca3b9 DE |
754 | |
755 | /* A C expression that defines the optional machine-dependent constraint | |
756 | letters that can be used to segregate specific types of operands, | |
757 | usually memory references, for the target machine. It should return 1 if | |
758 | VALUE corresponds to the operand type represented by the constraint letter | |
759 | C. If C is not defined as an extra constraint, the value returned should | |
760 | be 0 regardless of VALUE. */ | |
761 | /* Q is for symbolic addresses loadable with ld24. | |
2b7972b0 | 762 | R is for symbolic addresses when ld24 can't be used. |
56e2e762 | 763 | S is for stores with pre {inc,dec}rement |
5b8ae21f | 764 | T is for indirect of a pointer. |
56e2e762 | 765 | U is for loads with post increment. */ |
5b8ae21f MM |
766 | |
767 | #define EXTRA_CONSTRAINT(VALUE, C) \ | |
ad126521 | 768 | ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \ |
56e2e762 | 769 | || addr24_operand (VALUE, VOIDmode)) \ |
ad126521 | 770 | : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \ |
56e2e762 | 771 | || addr32_operand (VALUE, VOIDmode)) \ |
ad126521 | 772 | : (C) == 'S' ? (GET_CODE (VALUE) == MEM \ |
56e2e762 NC |
773 | && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \ |
774 | XEXP (VALUE, 0))) \ | |
ad126521 | 775 | : (C) == 'T' ? (GET_CODE (VALUE) == MEM \ |
56e2e762 | 776 | && memreg_operand (VALUE, GET_MODE (VALUE))) \ |
ad126521 | 777 | : (C) == 'U' ? (GET_CODE (VALUE) == MEM \ |
56e2e762 NC |
778 | && LOAD_POSTINC_P (GET_MODE (VALUE), \ |
779 | XEXP (VALUE, 0))) \ | |
ad126521 | 780 | : 0) |
8c5ca3b9 DE |
781 | \f |
782 | /* Stack layout and stack pointer usage. */ | |
783 | ||
784 | /* Define this macro if pushing a word onto the stack moves the stack | |
785 | pointer to a smaller address. */ | |
786 | #define STACK_GROWS_DOWNWARD | |
787 | ||
8c5ca3b9 DE |
788 | /* Offset from frame pointer to start allocating local variables at. |
789 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
790 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
791 | of the first local allocated. */ | |
792 | /* The frame pointer points at the same place as the stack pointer, except if | |
793 | alloca has been called. */ | |
794 | #define STARTING_FRAME_OFFSET \ | |
ad126521 | 795 | M32R_STACK_ALIGN (current_function_outgoing_args_size) |
8c5ca3b9 DE |
796 | |
797 | /* Offset from the stack pointer register to the first location at which | |
798 | outgoing arguments are placed. */ | |
799 | #define STACK_POINTER_OFFSET 0 | |
800 | ||
801 | /* Offset of first parameter from the argument pointer register value. */ | |
802 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
803 | ||
8c5ca3b9 DE |
804 | /* Register to use for pushing function arguments. */ |
805 | #define STACK_POINTER_REGNUM 15 | |
806 | ||
807 | /* Base register for access to local variables of the function. */ | |
808 | #define FRAME_POINTER_REGNUM 13 | |
809 | ||
810 | /* Base register for access to arguments of the function. */ | |
811 | #define ARG_POINTER_REGNUM 16 | |
812 | ||
ad126521 KI |
813 | /* Register in which static-chain is passed to a function. |
814 | This must not be a register used by the prologue. */ | |
815 | #define STATIC_CHAIN_REGNUM 7 | |
8c5ca3b9 DE |
816 | |
817 | /* These aren't official macros. */ | |
ad126521 KI |
818 | #define PROLOGUE_TMP_REGNUM 4 |
819 | #define RETURN_ADDR_REGNUM 14 | |
820 | /* #define GP_REGNUM 12 */ | |
821 | #define CARRY_REGNUM 17 | |
822 | #define ACCUM_REGNUM 18 | |
823 | #define M32R_MAX_INT_REGS 16 | |
8c5ca3b9 | 824 | |
56e2e762 NC |
825 | #ifndef SUBTARGET_GPR_P |
826 | #define SUBTARGET_GPR_P(REGNO) 0 | |
827 | #endif | |
828 | ||
829 | #ifndef SUBTARGET_ACCUM_P | |
830 | #define SUBTARGET_ACCUM_P(REGNO) 0 | |
831 | #endif | |
832 | ||
833 | #ifndef SUBTARGET_CARRY_P | |
834 | #define SUBTARGET_CARRY_P(REGNO) 0 | |
835 | #endif | |
836 | ||
837 | #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) | |
838 | #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) | |
839 | #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) | |
8c5ca3b9 DE |
840 | \f |
841 | /* Eliminating the frame and arg pointers. */ | |
842 | ||
843 | /* A C expression which is nonzero if a function must have and use a | |
844 | frame pointer. This expression is evaluated in the reload pass. | |
845 | If its value is nonzero the function will have a frame pointer. */ | |
56e2e762 | 846 | #define FRAME_POINTER_REQUIRED current_function_calls_alloca |
8c5ca3b9 DE |
847 | |
848 | #if 0 | |
849 | /* C statement to store the difference between the frame pointer | |
850 | and the stack pointer values immediately after the function prologue. | |
851 | If `ELIMINABLE_REGS' is defined, this macro will be not be used and | |
852 | need not be defined. */ | |
853 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
854 | ((VAR) = m32r_compute_frame_size (get_frame_size ())) | |
855 | #endif | |
856 | ||
857 | /* If defined, this macro specifies a table of register pairs used to | |
858 | eliminate unneeded registers that point into the stack frame. If | |
859 | it is not defined, the only elimination attempted by the compiler | |
860 | is to replace references to the frame pointer with references to | |
861 | the stack pointer. | |
862 | ||
863 | Note that the elimination of the argument pointer with the stack | |
864 | pointer is specified first since that is the preferred elimination. */ | |
865 | ||
56e2e762 NC |
866 | #define ELIMINABLE_REGS \ |
867 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
868 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
869 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} | |
8c5ca3b9 | 870 | |
a0ab749a | 871 | /* A C expression that returns nonzero if the compiler is allowed to |
8c5ca3b9 DE |
872 | try to replace register number FROM-REG with register number |
873 | TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is | |
874 | defined, and will usually be the constant 1, since most of the | |
875 | cases preventing register elimination are things that the compiler | |
876 | already knows about. */ | |
877 | ||
56e2e762 NC |
878 | #define CAN_ELIMINATE(FROM, TO) \ |
879 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
880 | ? ! frame_pointer_needed \ | |
881 | : 1) | |
8c5ca3b9 DE |
882 | |
883 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It | |
884 | specifies the initial difference between the specified pair of | |
885 | registers. This macro must be defined if `ELIMINABLE_REGS' is | |
886 | defined. */ | |
887 | ||
ad126521 KI |
888 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
889 | do \ | |
890 | { \ | |
891 | int size = m32r_compute_frame_size (get_frame_size ()); \ | |
892 | \ | |
893 | if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
894 | (OFFSET) = 0; \ | |
895 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
896 | (OFFSET) = size - current_function_pretend_args_size; \ | |
897 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
898 | (OFFSET) = size - current_function_pretend_args_size; \ | |
899 | else \ | |
75c3cfba | 900 | gcc_unreachable (); \ |
ad126521 KI |
901 | } \ |
902 | while (0) | |
8c5ca3b9 DE |
903 | \f |
904 | /* Function argument passing. */ | |
905 | ||
8c5ca3b9 DE |
906 | /* If defined, the maximum amount of space required for outgoing |
907 | arguments will be computed and placed into the variable | |
908 | `current_function_outgoing_args_size'. No space will be pushed | |
909 | onto the stack for each call; instead, the function prologue should | |
910 | increase the stack frame size by this amount. */ | |
f73ad30e | 911 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8c5ca3b9 | 912 | |
8c5ca3b9 DE |
913 | /* Value is the number of bytes of arguments automatically |
914 | popped when returning from a subroutine call. | |
915 | FUNDECL is the declaration node of the function (as a tree), | |
916 | FUNTYPE is the data type of the function (as a tree), | |
917 | or for a library call it is an identifier node for the subroutine name. | |
918 | SIZE is the number of bytes of arguments passed on the stack. */ | |
919 | #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 | |
920 | ||
921 | /* Define a data type for recording info about an argument list | |
922 | during the scan of that argument list. This data type should | |
923 | hold all necessary information about the function itself | |
924 | and about the args processed so far, enough to enable macros | |
925 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
926 | #define CUMULATIVE_ARGS int | |
927 | ||
928 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
929 | for a call to a function whose data type is FNTYPE. | |
930 | For a library call, FNTYPE is 0. */ | |
0f6937fe | 931 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
56e2e762 | 932 | ((CUM) = 0) |
8c5ca3b9 DE |
933 | |
934 | /* The number of registers used for parameter passing. Local to this file. */ | |
935 | #define M32R_MAX_PARM_REGS 4 | |
936 | ||
937 | /* 1 if N is a possible register number for function argument passing. */ | |
938 | #define FUNCTION_ARG_REGNO_P(N) \ | |
56e2e762 | 939 | ((unsigned) (N) < M32R_MAX_PARM_REGS) |
8c5ca3b9 DE |
940 | |
941 | /* The ROUND_ADVANCE* macros are local to this file. */ | |
942 | /* Round SIZE up to a word boundary. */ | |
943 | #define ROUND_ADVANCE(SIZE) \ | |
56e2e762 | 944 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
8c5ca3b9 DE |
945 | |
946 | /* Round arg MODE/TYPE up to the next word boundary. */ | |
947 | #define ROUND_ADVANCE_ARG(MODE, TYPE) \ | |
56e2e762 | 948 | ((MODE) == BLKmode \ |
16f104b3 | 949 | ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \ |
9d303046 | 950 | : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE))) |
8c5ca3b9 DE |
951 | |
952 | /* Round CUM up to the necessary point for argument MODE/TYPE. */ | |
8c5ca3b9 | 953 | #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM) |
8c5ca3b9 DE |
954 | |
955 | /* Return boolean indicating arg of type TYPE and mode MODE will be passed in | |
956 | a reg. This includes arguments that have to be passed by reference as the | |
957 | pointer to them is passed in a reg if one is available (and that is what | |
958 | we're given). | |
959 | This macro is only used in this file. */ | |
6c535c69 | 960 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ |
56e2e762 | 961 | (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS) |
8c5ca3b9 DE |
962 | |
963 | /* Determine where to put an argument to a function. | |
964 | Value is zero to push the argument on the stack, | |
965 | or a hard register in which to store the argument. | |
966 | ||
967 | MODE is the argument's machine mode. | |
968 | TYPE is the data type of the argument (as a tree). | |
969 | This is null for libcalls where that information may | |
970 | not be available. | |
971 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
972 | the preceding args and about the function being called. | |
973 | NAMED is nonzero if this argument is a named parameter | |
974 | (otherwise it is an extra parameter matching an ellipsis). */ | |
975 | /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers | |
976 | and the rest are pushed. */ | |
977 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
6c535c69 | 978 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
56e2e762 NC |
979 | ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \ |
980 | : 0) | |
8c5ca3b9 | 981 | |
8c5ca3b9 DE |
982 | /* Update the data in CUM to advance over an argument |
983 | of mode MODE and data type TYPE. | |
984 | (TYPE is null for libcalls where that information may not be available.) */ | |
985 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
56e2e762 | 986 | ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ |
8c5ca3b9 DE |
987 | + ROUND_ADVANCE_ARG ((MODE), (TYPE)))) |
988 | ||
989 | /* If defined, a C expression that gives the alignment boundary, in bits, | |
990 | of an argument with the specified mode and type. If it is not defined, | |
991 | PARM_BOUNDARY is used for all arguments. */ | |
992 | #if 0 | |
993 | /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */ | |
994 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
ad126521 KI |
995 | (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ |
996 | ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) | |
8c5ca3b9 | 997 | #endif |
8c5ca3b9 DE |
998 | \f |
999 | /* Function results. */ | |
1000 | ||
1001 | /* Define how to find the value returned by a function. | |
1002 | VALTYPE is the data type of the value (as a tree). | |
1003 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1004 | otherwise, FUNC is 0. */ | |
c5c76735 | 1005 | #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0) |
8c5ca3b9 DE |
1006 | |
1007 | /* Define how to find the value returned by a library function | |
1008 | assuming the value has mode MODE. */ | |
c5c76735 | 1009 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) |
8c5ca3b9 DE |
1010 | |
1011 | /* 1 if N is a possible register number for a function value | |
1012 | as seen by the caller. */ | |
1013 | /* ??? What about r1 in DI/DF values. */ | |
1014 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
1015 | ||
bd5bd7ac | 1016 | /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ |
8c5ca3b9 | 1017 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
8c5ca3b9 DE |
1018 | \f |
1019 | /* Function entry and exit. */ | |
1020 | ||
1021 | /* Initialize data used by insn expanders. This is called from | |
1022 | init_emit, once for each function, before code is generated. */ | |
1023 | #define INIT_EXPANDERS m32r_init_expanders () | |
1024 | ||
8c5ca3b9 DE |
1025 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1026 | the stack pointer does not matter. The value is tested only in | |
1027 | functions that have frame pointers. | |
1028 | No definition is equivalent to always zero. */ | |
1029 | #define EXIT_IGNORE_STACK 1 | |
1030 | ||
8c5ca3b9 DE |
1031 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1032 | for profiling a function entry. */ | |
ad126521 KI |
1033 | #undef FUNCTION_PROFILER |
1034 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1035 | do \ | |
1036 | { \ | |
1037 | if (flag_pic) \ | |
1038 | { \ | |
1039 | fprintf (FILE, "\tld24 r14,#mcount\n"); \ | |
1040 | fprintf (FILE, "\tadd r14,r12\n"); \ | |
1041 | fprintf (FILE, "\tld r14,@r14\n"); \ | |
1042 | fprintf (FILE, "\tjl r14\n"); \ | |
1043 | } \ | |
1044 | else \ | |
1045 | { \ | |
1046 | if (TARGET_ADDR24) \ | |
1047 | fprintf (FILE, "\tbl mcount\n"); \ | |
1048 | else \ | |
1049 | { \ | |
1050 | fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ | |
1051 | fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ | |
1052 | fprintf (FILE, "\tjl r14\n"); \ | |
1053 | } \ | |
1054 | } \ | |
1055 | fprintf (FILE, "\taddi sp,#4\n"); \ | |
1056 | } \ | |
1057 | while (0) | |
8c5ca3b9 DE |
1058 | \f |
1059 | /* Trampolines. */ | |
1060 | ||
ad126521 | 1061 | /* On the M32R, the trampoline is: |
8c5ca3b9 | 1062 | |
ad126521 KI |
1063 | mv r7, lr -> bl L1 ; 178e 7e01 |
1064 | L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) | |
1065 | mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 | |
1066 | ld r6, @r6 -> jmp r6 ; 26c6 1fc6 | |
1067 | L2: .word STATIC | |
1068 | .word FUNCTION */ | |
8c5ca3b9 | 1069 | |
ad126521 KI |
1070 | #ifndef CACHE_FLUSH_FUNC |
1071 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
1072 | #endif | |
1073 | #ifndef CACHE_FLUSH_TRAP | |
97b73103 | 1074 | #define CACHE_FLUSH_TRAP 12 |
ad126521 | 1075 | #endif |
8c5ca3b9 DE |
1076 | |
1077 | /* Length in bytes of the trampoline for entering a nested function. */ | |
f26ef713 | 1078 | #define TRAMPOLINE_SIZE 24 |
8c5ca3b9 DE |
1079 | |
1080 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1081 | FNADDR is an RTX for the address of the function's pure code. | |
1082 | CXT is an RTX for the static chain value for the function. */ | |
ad126521 KI |
1083 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1084 | do \ | |
1085 | { \ | |
1086 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \ | |
1087 | GEN_INT \ | |
1088 | (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \ | |
1089 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \ | |
1090 | GEN_INT \ | |
1091 | (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \ | |
1092 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \ | |
1093 | GEN_INT \ | |
1094 | (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \ | |
1095 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \ | |
1096 | GEN_INT \ | |
1097 | (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \ | |
1098 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \ | |
1099 | (CXT)); \ | |
1100 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \ | |
1101 | (FNADDR)); \ | |
97b73103 | 1102 | if (m32r_cache_flush_trap >= 0) \ |
ad126521 KI |
1103 | emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\ |
1104 | GEN_INT (m32r_cache_flush_trap) )); \ | |
1105 | else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \ | |
767dec6b | 1106 | emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \ |
ad126521 KI |
1107 | 0, VOIDmode, 3, TRAMP, Pmode, \ |
1108 | GEN_INT (TRAMPOLINE_SIZE), SImode, \ | |
1109 | GEN_INT (3), SImode); \ | |
1110 | } \ | |
1111 | while (0) | |
8c5ca3b9 | 1112 | \f |
7b14411a KI |
1113 | #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) |
1114 | ||
1115 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) | |
1116 | ||
8c5ca3b9 DE |
1117 | /* Addressing modes, and classification of registers for them. */ |
1118 | ||
1119 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1120 | #define MAX_REGS_PER_ADDRESS 1 | |
1121 | ||
1122 | /* We have post-inc load and pre-dec,pre-inc store, | |
1123 | but only for 4 byte vals. */ | |
ad126521 KI |
1124 | #define HAVE_PRE_DECREMENT 1 |
1125 | #define HAVE_PRE_INCREMENT 1 | |
940da324 | 1126 | #define HAVE_POST_INCREMENT 1 |
8c5ca3b9 DE |
1127 | |
1128 | /* Recognize any constant value that is a valid address. */ | |
ad126521 KI |
1129 | #define CONSTANT_ADDRESS_P(X) \ |
1130 | ( GET_CODE (X) == LABEL_REF \ | |
1131 | || GET_CODE (X) == SYMBOL_REF \ | |
1132 | || GET_CODE (X) == CONST_INT \ | |
1133 | || (GET_CODE (X) == CONST \ | |
1134 | && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) | |
8c5ca3b9 DE |
1135 | |
1136 | /* Nonzero if the constant value X is a legitimate general operand. | |
1137 | We don't allow (plus symbol large-constant) as the relocations can't | |
1138 | describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations. | |
1139 | We allow all CONST_DOUBLE's as the md file patterns will force the | |
1140 | constant to memory if they can't handle them. */ | |
1141 | ||
56e2e762 | 1142 | #define LEGITIMATE_CONSTANT_P(X) \ |
ad126521 KI |
1143 | (! (GET_CODE (X) == CONST \ |
1144 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1145 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ | |
1146 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1147 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767)) | |
8c5ca3b9 DE |
1148 | |
1149 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1150 | and check its validity for a certain class. | |
1151 | We have two alternate definitions for each of them. | |
1152 | The usual definition accepts all pseudo regs; the other rejects | |
1153 | them unless they have been allocated suitable hard regs. | |
1154 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1155 | ||
1156 | Most source files want to accept pseudo regs in the hope that | |
1157 | they will get allocated to the class that the insn wants them to be in. | |
1158 | Source files for reload pass need to be strict. | |
1159 | After reload, it makes no difference, since pseudo regs have | |
1160 | been eliminated by then. */ | |
1161 | ||
1162 | #ifdef REG_OK_STRICT | |
1163 | ||
1164 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1165 | #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X)) | |
1166 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1167 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) | |
1168 | ||
1169 | #else | |
1170 | ||
1171 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1172 | or if it is a pseudo reg. */ | |
56e2e762 | 1173 | #define REG_OK_FOR_BASE_P(X) \ |
ad126521 KI |
1174 | (GPR_P (REGNO (X)) \ |
1175 | || (REGNO (X)) == ARG_POINTER_REGNUM \ | |
1176 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
8c5ca3b9 DE |
1177 | /* Nonzero if X is a hard reg that can be used as an index |
1178 | or if it is a pseudo reg. */ | |
1179 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) | |
1180 | ||
1181 | #endif | |
1182 | ||
1183 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1184 | that is a valid memory address for an instruction. | |
1185 | The MODE argument is the machine mode for the MEM expression | |
1186 | that wants to use this address. */ | |
1187 | ||
56e2e762 NC |
1188 | /* Local to this file. */ |
1189 | #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X)) | |
8c5ca3b9 | 1190 | |
56e2e762 | 1191 | /* Local to this file. */ |
8c5ca3b9 | 1192 | #define RTX_OK_FOR_OFFSET_P(X) \ |
ad126521 | 1193 | (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X))) |
8c5ca3b9 | 1194 | |
56e2e762 | 1195 | /* Local to this file. */ |
ad126521 KI |
1196 | #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ |
1197 | (GET_CODE (X) == PLUS \ | |
1198 | && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ | |
1199 | && RTX_OK_FOR_OFFSET_P (XEXP (X, 1))) | |
8c5ca3b9 | 1200 | |
56e2e762 | 1201 | /* Local to this file. */ |
5b8ae21f MM |
1202 | /* For LO_SUM addresses, do not allow them if the MODE is > 1 word, |
1203 | since more than one instruction will be required. */ | |
ad126521 KI |
1204 | #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \ |
1205 | (GET_CODE (X) == LO_SUM \ | |
1206 | && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\ | |
1207 | && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ | |
1208 | && CONSTANT_P (XEXP (X, 1))) | |
8c5ca3b9 | 1209 | |
56e2e762 NC |
1210 | /* Local to this file. */ |
1211 | /* Is this a load and increment operation. */ | |
ad126521 KI |
1212 | #define LOAD_POSTINC_P(MODE, X) \ |
1213 | (((MODE) == SImode || (MODE) == SFmode) \ | |
1214 | && GET_CODE (X) == POST_INC \ | |
1215 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1216 | && RTX_OK_FOR_BASE_P (XEXP (X, 0))) | |
56e2e762 NC |
1217 | |
1218 | /* Local to this file. */ | |
e03f5d43 | 1219 | /* Is this an increment/decrement and store operation. */ |
ad126521 KI |
1220 | #define STORE_PREINC_PREDEC_P(MODE, X) \ |
1221 | (((MODE) == SImode || (MODE) == SFmode) \ | |
1222 | && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \ | |
1223 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1224 | && RTX_OK_FOR_BASE_P (XEXP (X, 0))) | |
1225 | ||
1226 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1227 | do \ | |
1228 | { \ | |
1229 | if (RTX_OK_FOR_BASE_P (X)) \ | |
1230 | goto ADDR; \ | |
1231 | if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \ | |
1232 | goto ADDR; \ | |
1233 | if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \ | |
1234 | goto ADDR; \ | |
1235 | if (LOAD_POSTINC_P ((MODE), (X))) \ | |
1236 | goto ADDR; \ | |
1237 | if (STORE_PREINC_PREDEC_P ((MODE), (X))) \ | |
1238 | goto ADDR; \ | |
1239 | } \ | |
1240 | while (0) | |
8c5ca3b9 DE |
1241 | |
1242 | /* Try machine-dependent ways of modifying an illegitimate address | |
1243 | to be legitimate. If we find one, return the new, valid address. | |
1244 | This macro is used in only one place: `memory_address' in explow.c. | |
1245 | ||
1246 | OLDX is the address as it was before break_out_memory_refs was called. | |
1247 | In some cases it is useful to look at this to decide what needs to be done. | |
1248 | ||
1249 | MODE and WIN are passed so that this macro can use | |
1250 | GO_IF_LEGITIMATE_ADDRESS. | |
1251 | ||
1252 | It is always safe for this macro to do nothing. It exists to recognize | |
ad126521 KI |
1253 | opportunities to optimize the output. */ |
1254 | ||
1255 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
1256 | do \ | |
1257 | { \ | |
1258 | if (flag_pic) \ | |
1259 | (X) = m32r_legitimize_pic_address (X, NULL_RTX); \ | |
1260 | if (memory_address_p (MODE, X)) \ | |
1261 | goto WIN; \ | |
1262 | } \ | |
1263 | while (0) | |
8c5ca3b9 DE |
1264 | |
1265 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1266 | has an effect that depends on the machine mode it is used for. */ | |
ad126521 KI |
1267 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
1268 | do \ | |
1269 | { \ | |
b9a76028 | 1270 | if (GET_CODE (ADDR) == LO_SUM) \ |
ad126521 KI |
1271 | goto LABEL; \ |
1272 | } \ | |
1273 | while (0) | |
8c5ca3b9 DE |
1274 | \f |
1275 | /* Condition code usage. */ | |
1276 | ||
a0ab749a | 1277 | /* Return nonzero if SELECT_CC_MODE will never return MODE for a |
8c5ca3b9 | 1278 | floating point inequality comparison. */ |
18543a22 | 1279 | #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ |
8c5ca3b9 DE |
1280 | \f |
1281 | /* Costs. */ | |
1282 | ||
8c5ca3b9 DE |
1283 | /* Compute extra cost of moving data between one register class |
1284 | and another. */ | |
cf011243 | 1285 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2 |
8c5ca3b9 DE |
1286 | |
1287 | /* Compute the cost of moving data between registers and memory. */ | |
1288 | /* Memory is 3 times as expensive as registers. | |
1289 | ??? Is that the right way to look at it? */ | |
5b8ae21f | 1290 | #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \ |
8c5ca3b9 DE |
1291 | (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) |
1292 | ||
1293 | /* The cost of a branch insn. */ | |
1294 | /* A value of 2 here causes GCC to avoid using branches in comparisons like | |
1295 | while (a < N && a). Branches aren't that expensive on the M32R so | |
1296 | we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ | |
56e2e762 | 1297 | #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1) |
8c5ca3b9 | 1298 | |
8c5ca3b9 DE |
1299 | /* Nonzero if access to memory by bytes is slow and undesirable. |
1300 | For RISC chips, it means that access to memory by bytes is no | |
1301 | better than access by words when possible, so grab a whole word | |
1302 | and maybe make use of that. */ | |
1303 | #define SLOW_BYTE_ACCESS 1 | |
1304 | ||
1305 | /* Define this macro if it is as good or better to call a constant | |
1306 | function address than to call an address kept in a register. */ | |
8c5ca3b9 | 1307 | #define NO_FUNCTION_CSE |
8c5ca3b9 DE |
1308 | \f |
1309 | /* Section selection. */ | |
1310 | ||
1311 | #define TEXT_SECTION_ASM_OP "\t.section .text" | |
1312 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
8c5ca3b9 | 1313 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
8c5ca3b9 | 1314 | |
8c5ca3b9 DE |
1315 | /* Define this macro if jump tables (for tablejump insns) should be |
1316 | output in the text section, along with the assembler instructions. | |
1317 | Otherwise, the readonly data section is used. | |
1318 | This macro is irrelevant if there is no separate readonly data section. */ | |
ad126521 | 1319 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) |
8c5ca3b9 | 1320 | \f |
ad126521 | 1321 | /* Position Independent Code. */ |
8c5ca3b9 DE |
1322 | |
1323 | /* The register number of the register used to address a table of static | |
1324 | data addresses in memory. In some cases this register is defined by a | |
1325 | processor's ``application binary interface'' (ABI). When this macro | |
1326 | is defined, RTL is generated for this register once, as with the stack | |
1327 | pointer and frame pointer registers. If this macro is not defined, it | |
1328 | is up to the machine-dependent files to allocate such a register (if | |
1329 | necessary). */ | |
ad126521 | 1330 | #define PIC_OFFSET_TABLE_REGNUM 12 |
8c5ca3b9 DE |
1331 | |
1332 | /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is | |
1333 | clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM | |
1334 | is not defined. */ | |
1335 | /* This register is call-saved on the M32R. */ | |
1336 | /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ | |
1337 | ||
8c5ca3b9 DE |
1338 | /* A C expression that is nonzero if X is a legitimate immediate |
1339 | operand on the target machine when generating position independent code. | |
1340 | You can assume that X satisfies CONSTANT_P, so you need not | |
1341 | check this. You can also assume `flag_pic' is true, so you need not | |
1342 | check it either. You need not define this macro if all constants | |
1343 | (including SYMBOL_REF) can be immediate operands when generating | |
1344 | position independent code. */ | |
ad126521 | 1345 | #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) |
8c5ca3b9 DE |
1346 | \f |
1347 | /* Control the assembler format that we output. */ | |
1348 | ||
8c5ca3b9 DE |
1349 | /* A C string constant describing how to begin a comment in the target |
1350 | assembler language. The compiler assumes that the comment will | |
1351 | end at the end of the line. */ | |
1352 | #define ASM_COMMENT_START ";" | |
1353 | ||
1354 | /* Output to assembler file text saying following lines | |
1355 | may contain character constants, extra white space, comments, etc. */ | |
1356 | #define ASM_APP_ON "" | |
1357 | ||
1358 | /* Output to assembler file text saying following lines | |
1359 | no longer contain unusual constructs. */ | |
1360 | #define ASM_APP_OFF "" | |
1361 | ||
506a61b1 KG |
1362 | /* Globalizing directive for a label. */ |
1363 | #define GLOBAL_ASM_OP "\t.global\t" | |
8c5ca3b9 | 1364 | |
93a27b7b ZW |
1365 | /* We do not use DBX_LINES_FUNCTION_RELATIVE or |
1366 | dbxout_stab_value_internal_label_diff here because | |
1367 | we need to use .debugsym for the line label. */ | |
5b8ae21f | 1368 | |
3e487b21 | 1369 | #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \ |
56e2e762 NC |
1370 | do \ |
1371 | { \ | |
6a728a2d SB |
1372 | const char * begin_label = \ |
1373 | XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \ | |
93a27b7b ZW |
1374 | char label[64]; \ |
1375 | ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \ | |
1376 | \ | |
1377 | dbxout_begin_stabn_sline (line); \ | |
1378 | assemble_name (file, label); \ | |
1379 | putc ('-', file); \ | |
1380 | assemble_name (file, begin_label); \ | |
1381 | fputs ("\n\t.debugsym ", file); \ | |
1382 | assemble_name (file, label); \ | |
1383 | putc ('\n', file); \ | |
e2cb732f ZW |
1384 | counter += 1; \ |
1385 | } \ | |
56e2e762 | 1386 | while (0) |
5b8ae21f | 1387 | |
8c5ca3b9 DE |
1388 | /* How to refer to registers in assembler output. |
1389 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
56e2e762 NC |
1390 | #ifndef SUBTARGET_REGISTER_NAMES |
1391 | #define SUBTARGET_REGISTER_NAMES | |
1392 | #endif | |
1393 | ||
1394 | #define REGISTER_NAMES \ | |
8c5ca3b9 DE |
1395 | { \ |
1396 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1397 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ | |
56e2e762 NC |
1398 | "ap", "cbit", "a0" \ |
1399 | SUBTARGET_REGISTER_NAMES \ | |
8c5ca3b9 DE |
1400 | } |
1401 | ||
1402 | /* If defined, a C initializer for an array of structures containing | |
1403 | a name and a register number. This macro defines additional names | |
1404 | for hard registers, thus allowing the `asm' option in declarations | |
1405 | to refer to registers using alternate names. */ | |
56e2e762 NC |
1406 | #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES |
1407 | #define SUBTARGET_ADDITIONAL_REGISTER_NAMES | |
1408 | #endif | |
1409 | ||
1410 | #define ADDITIONAL_REGISTER_NAMES \ | |
8c5ca3b9 DE |
1411 | { \ |
1412 | /*{ "gp", GP_REGNUM },*/ \ | |
1413 | { "r13", FRAME_POINTER_REGNUM }, \ | |
1414 | { "r14", RETURN_ADDR_REGNUM }, \ | |
1415 | { "r15", STACK_POINTER_REGNUM }, \ | |
56e2e762 | 1416 | SUBTARGET_ADDITIONAL_REGISTER_NAMES \ |
8c5ca3b9 DE |
1417 | } |
1418 | ||
1419 | /* A C expression which evaluates to true if CODE is a valid | |
1420 | punctuation character for use in the `PRINT_OPERAND' macro. */ | |
f540a7d3 | 1421 | extern char m32r_punct_chars[256]; |
8c5ca3b9 | 1422 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ |
56e2e762 | 1423 | m32r_punct_chars[(unsigned char) (CHAR)] |
8c5ca3b9 DE |
1424 | |
1425 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1426 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1427 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1428 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
56e2e762 | 1429 | m32r_print_operand (FILE, X, CODE) |
8c5ca3b9 DE |
1430 | |
1431 | /* A C compound statement to output to stdio stream STREAM the | |
1432 | assembler syntax for an instruction operand that is a memory | |
fb49053f | 1433 | reference whose address is ADDR. ADDR is an RTL expression. */ |
8c5ca3b9 | 1434 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
56e2e762 | 1435 | m32r_print_operand_address (FILE, ADDR) |
8c5ca3b9 DE |
1436 | |
1437 | /* If defined, C string expressions to be used for the `%R', `%L', | |
1438 | `%U', and `%I' options of `asm_fprintf' (see `final.c'). These | |
1439 | are useful when a single `md' file must support multiple assembler | |
1440 | formats. In that case, the various `tm.h' files can define these | |
1441 | macros differently. */ | |
ad126521 KI |
1442 | #define REGISTER_PREFIX "" |
1443 | #define LOCAL_LABEL_PREFIX ".L" | |
1444 | #define USER_LABEL_PREFIX "" | |
1445 | #define IMMEDIATE_PREFIX "#" | |
8c5ca3b9 DE |
1446 | |
1447 | /* This is how to output an element of a case-vector that is absolute. */ | |
56e2e762 NC |
1448 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
1449 | do \ | |
1450 | { \ | |
1451 | char label[30]; \ | |
1452 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1453 | fprintf (FILE, "\t.word\t"); \ | |
1454 | assemble_name (FILE, label); \ | |
1455 | fprintf (FILE, "\n"); \ | |
1456 | } \ | |
1457 | while (0) | |
8c5ca3b9 DE |
1458 | |
1459 | /* This is how to output an element of a case-vector that is relative. */ | |
56e2e762 NC |
1460 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ |
1461 | do \ | |
1462 | { \ | |
1463 | char label[30]; \ | |
1464 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1465 | fprintf (FILE, "\t.word\t"); \ | |
1466 | assemble_name (FILE, label); \ | |
1467 | fprintf (FILE, "-"); \ | |
1468 | ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ | |
1469 | assemble_name (FILE, label); \ | |
ad126521 | 1470 | fprintf (FILE, "\n"); \ |
56e2e762 NC |
1471 | } \ |
1472 | while (0) | |
8c5ca3b9 | 1473 | |
fc470718 R |
1474 | /* The desired alignment for the location counter at the beginning |
1475 | of a loop. */ | |
8c5ca3b9 DE |
1476 | /* On the M32R, align loops to 32 byte boundaries (cache line size) |
1477 | if -malign-loops. */ | |
fc470718 | 1478 | #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) |
8c5ca3b9 | 1479 | |
56e2e762 NC |
1480 | /* Define this to be the maximum number of insns to move around when moving |
1481 | a loop test from the top of a loop to the bottom | |
1482 | and seeing whether to duplicate it. The default is thirty. | |
1483 | ||
1484 | Loop unrolling currently doesn't like this optimization, so | |
1485 | disable doing if we are unrolling loops and saving space. */ | |
1486 | #define LOOP_TEST_THRESHOLD (optimize_size \ | |
1487 | && !flag_unroll_loops \ | |
1488 | && !flag_unroll_all_loops ? 2 : 30) | |
1489 | ||
8c5ca3b9 DE |
1490 | /* This is how to output an assembler line |
1491 | that says to advance the location counter | |
1492 | to a multiple of 2**LOG bytes. */ | |
1493 | /* .balign is used to avoid confusion. */ | |
56e2e762 NC |
1494 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
1495 | do \ | |
1496 | { \ | |
1497 | if ((LOG) != 0) \ | |
1498 | fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ | |
1499 | } \ | |
1500 | while (0) | |
8c5ca3b9 DE |
1501 | |
1502 | /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a | |
1503 | separate, explicit argument. If you define this macro, it is used in | |
1504 | place of `ASM_OUTPUT_COMMON', and gives you more flexibility in | |
1505 | handling the required alignment of the variable. The alignment is | |
1506 | specified as the number of bits. */ | |
1507 | ||
6e7b07a7 | 1508 | #define SCOMMON_ASM_OP "\t.scomm\t" |
8c5ca3b9 | 1509 | |
56e2e762 NC |
1510 | #undef ASM_OUTPUT_ALIGNED_COMMON |
1511 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
1512 | do \ | |
8c5ca3b9 | 1513 | { \ |
56e2e762 NC |
1514 | if (! TARGET_SDATA_NONE \ |
1515 | && (SIZE) > 0 && (SIZE) <= g_switch_value) \ | |
016c8440 | 1516 | fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ |
56e2e762 | 1517 | else \ |
016c8440 | 1518 | fprintf ((FILE), "%s", COMMON_ASM_OP); \ |
8c5ca3b9 | 1519 | assemble_name ((FILE), (NAME)); \ |
58e15542 | 1520 | fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ |
8c5ca3b9 | 1521 | } \ |
56e2e762 | 1522 | while (0) |
8c5ca3b9 | 1523 | |
cb1f9d03 KI |
1524 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
1525 | do \ | |
1526 | { \ | |
1527 | if (! TARGET_SDATA_NONE \ | |
1528 | && (SIZE) > 0 && (SIZE) <= g_switch_value) \ | |
d6b5193b | 1529 | switch_to_section (get_named_section (NULL, ".sbss", 0)); \ |
cb1f9d03 | 1530 | else \ |
d6b5193b | 1531 | switch_to_section (bss_section); \ |
cb1f9d03 KI |
1532 | ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ |
1533 | last_assemble_variable_decl = DECL; \ | |
1534 | ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ | |
1535 | ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ | |
1536 | } \ | |
56e2e762 | 1537 | while (0) |
8c5ca3b9 DE |
1538 | \f |
1539 | /* Debugging information. */ | |
1540 | ||
1541 | /* Generate DBX and DWARF debugging information. */ | |
ad126521 | 1542 | #define DBX_DEBUGGING_INFO 1 |
23532de9 | 1543 | #define DWARF2_DEBUGGING_INFO 1 |
8c5ca3b9 | 1544 | |
25941194 | 1545 | /* Use DWARF2 debugging info by default. */ |
56e2e762 | 1546 | #undef PREFERRED_DEBUGGING_TYPE |
25941194 | 1547 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
8c5ca3b9 | 1548 | |
8c5ca3b9 DE |
1549 | /* Turn off splitting of long stabs. */ |
1550 | #define DBX_CONTIN_LENGTH 0 | |
1551 | \f | |
1552 | /* Miscellaneous. */ | |
1553 | ||
1554 | /* Specify the machine mode that this machine uses | |
1555 | for the index in the tablejump instruction. */ | |
ad126521 | 1556 | #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) |
8c5ca3b9 | 1557 | |
8c5ca3b9 DE |
1558 | /* Define if operations between registers always perform the operation |
1559 | on the full register even if a narrower mode is specified. */ | |
1560 | #define WORD_REGISTER_OPERATIONS | |
1561 | ||
1562 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1563 | will either zero-extend or sign-extend. The value of this macro should | |
1564 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1565 | done, UNKNOWN if none. */ |
8c5ca3b9 DE |
1566 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
1567 | ||
ad126521 KI |
1568 | /* Max number of bytes we can move from memory |
1569 | to memory in one reasonably fast instruction. */ | |
8c5ca3b9 DE |
1570 | #define MOVE_MAX 4 |
1571 | ||
1572 | /* Define this to be nonzero if shift instructions ignore all but the low-order | |
1573 | few bits. */ | |
1574 | #define SHIFT_COUNT_TRUNCATED 1 | |
1575 | ||
1576 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1577 | is done just by pretending it is already truncated. */ | |
1578 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1579 | ||
8c5ca3b9 DE |
1580 | /* Specify the machine mode that pointers have. |
1581 | After generation of rtl, the compiler makes no further distinction | |
1582 | between pointers and any other objects of this machine mode. */ | |
1583 | /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has | |
f3b569ca | 1584 | its own problems (you have to add extendpsisi2 and truncsipsi2). |
8c5ca3b9 DE |
1585 | Try to avoid it. */ |
1586 | #define Pmode SImode | |
1587 | ||
1588 | /* A function address in a call instruction. */ | |
1589 | #define FUNCTION_MODE SImode | |
8c5ca3b9 DE |
1590 | \f |
1591 | /* Define the information needed to generate branch and scc insns. This is | |
1592 | stored from the compare operation. Note that we can't use "rtx" here | |
1593 | since it hasn't been defined! */ | |
2b7972b0 MM |
1594 | extern struct rtx_def * m32r_compare_op0; |
1595 | extern struct rtx_def * m32r_compare_op1; | |
8c5ca3b9 | 1596 | |
71cc389b | 1597 | /* M32R function types. */ |
2b7972b0 MM |
1598 | enum m32r_function_type |
1599 | { | |
8c5ca3b9 DE |
1600 | M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT |
1601 | }; | |
56e2e762 NC |
1602 | |
1603 | #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) | |
2b7972b0 | 1604 | |
22a14e0d KH |
1605 | /* The maximum number of bytes to copy using pairs of load/store instructions. |
1606 | If a block is larger than this then a loop will be generated to copy | |
1607 | MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice. | |
1608 | A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte | |
1609 | string copy in it. */ | |
1610 | #define MAX_MOVE_BYTES 32 |