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385c9217 SC |
1 | /* Definitions of target machine for GNU compiler. |
2 | Motorola 68HC11 and 68HC12. | |
16c484c7 | 3 | Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
385c9217 SC |
4 | Contributed by Stephane Carrez (stcarrez@worldnet.fr) |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. | |
22 | ||
23 | Note: | |
24 | A first 68HC11 port was made by Otto Lind (otto@coactive.com) | |
25 | on gcc 2.6.3. I have used it as a starting point for this port. | |
26 | However, this new port is a complete re-write. Its internal | |
27 | design is completely different. The generated code is not | |
28 | compatible with the gcc 2.6.3 port. | |
29 | ||
30 | The gcc 2.6.3 port is available at: | |
31 | ||
32 | ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz | |
33 | ||
34 | */ | |
35 | ||
385c9217 SC |
36 | /***************************************************************************** |
37 | ** | |
38 | ** Controlling the Compilation Driver, `gcc' | |
39 | ** | |
40 | *****************************************************************************/ | |
41 | ||
42 | #undef ENDFILE_SPEC | |
43 | ||
44 | /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */ | |
45 | #ifndef ASM_SPEC | |
46 | #define ASM_SPEC "%{m68hc12:-m68hc12}%{!m68hc12:-m68hc11}" | |
47 | #endif | |
48 | ||
49 | /* We need to tell the linker the target elf format. Just pass an | |
50 | emulation option. This can be overriden by -Wl option of gcc. */ | |
51 | #ifndef LINK_SPEC | |
52 | #define LINK_SPEC "%{m68hc12:-m m68hc12elf}%{!m68hc12:-m m68hc11elf}" | |
53 | #endif | |
54 | ||
55 | #ifndef LIB_SPEC | |
56 | #define LIB_SPEC "" | |
57 | #endif | |
58 | ||
59 | #ifndef CC1_SPEC | |
60 | #define CC1_SPEC "" | |
61 | #endif | |
62 | ||
63 | #ifndef CPP_SPEC | |
64 | #define CPP_SPEC \ | |
65 | "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16 -D__INT_MAX__=32767}\ | |
66 | %{!mshort:-D__INT__=32 -D__INT_MAX__=2147483647}\ | |
67 | %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\ | |
3750bc81 SC |
68 | %{!m68hc12:-Dmc6811 -DMC6811 -Dmc68hc11}\ |
69 | %{fshort-double:-D__HAVE_SHORT_DOUBLE__}" | |
385c9217 SC |
70 | #endif |
71 | ||
72 | #undef STARTFILE_SPEC | |
73 | #define STARTFILE_SPEC "crt1%O%s" | |
74 | ||
75 | /* Names to predefine in the preprocessor for this target machine. */ | |
76 | #define CPP_PREDEFINES "-Dmc68hc1x" | |
77 | ||
0b29309a ZW |
78 | /* As an embedded target, we have no libc. */ |
79 | #define inhibit_libc | |
385c9217 SC |
80 | |
81 | /* Forward type declaration for prototypes definitions. | |
9caea35c | 82 | rtx_ptr is equivalent to rtx. Can't use the same name. */ |
385c9217 SC |
83 | struct rtx_def; |
84 | typedef struct rtx_def *rtx_ptr; | |
85 | ||
86 | union tree_node; | |
87 | typedef union tree_node *tree_ptr; | |
88 | ||
89 | /* We can't declare enum machine_mode forward nor include 'machmode.h' here. | |
90 | Prototypes defined here will use an int instead. It's better than no | |
9caea35c | 91 | prototype at all. */ |
385c9217 | 92 | typedef int enum_machine_mode; |
385c9217 SC |
93 | |
94 | /***************************************************************************** | |
95 | ** | |
96 | ** Run-time Target Specification | |
97 | ** | |
98 | *****************************************************************************/ | |
99 | ||
100 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
101 | ||
102 | extern int target_flags; | |
103 | ||
104 | extern short *reg_renumber; /* def in local_alloc.c */ | |
105 | ||
106 | /* Macros used in the machine description to test the flags. */ | |
107 | ||
108 | /* 6811 specific options | |
109 | * | |
110 | * For 68HC12, the auto inc/dec mode is disabled by default. The reason | |
111 | * is that for most programs, the reload pass will fail because it needs | |
112 | * more registers to save the value of the indexed register after the | |
113 | * memory access. For simple programs, you can enable this | |
114 | * with -mauto-incdec. | |
115 | */ | |
116 | ||
117 | #define MASK_SHORT 0002 /* Compile with 16-bit `int' */ | |
118 | #define MASK_AUTO_INC_DEC 0004 | |
119 | #define MASK_M6811 0010 | |
120 | #define MASK_M6812 0020 | |
121 | ||
122 | #define TARGET_OP_TIME (optimize && optimize_size == 0) | |
123 | #define TARGET_SHORT (target_flags & MASK_SHORT) | |
124 | #define TARGET_M6811 (target_flags & MASK_M6811) | |
125 | #define TARGET_M6812 (target_flags & MASK_M6812) | |
126 | #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC) | |
127 | ||
128 | /* Default target_flags if no switches specified. */ | |
129 | #ifndef TARGET_DEFAULT | |
130 | # define TARGET_DEFAULT (MASK_M6811) | |
131 | #endif | |
132 | ||
133 | /* Define this macro as a C expression for the initializer of an | |
134 | array of string to tell the driver program which options are | |
135 | defaults for this target and thus do not need to be handled | |
136 | specially when using `MULTILIB_OPTIONS'. */ | |
137 | #ifndef MULTILIB_DEFAULTS | |
138 | # if TARGET_DEFAULT & MASK_M6811 | |
139 | # define MULTILIB_DEFAULTS { "m68hc11" } | |
140 | # else | |
141 | # define MULTILIB_DEFAULTS { "m68hc12" } | |
142 | # endif | |
143 | #endif | |
144 | ||
145 | /* Macro to define tables used to set the flags. This is a list in braces of | |
146 | pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits | |
147 | to set or minus the bits to clear. An empty string NAME is used to | |
148 | identify the default VALUE. */ | |
149 | ||
150 | #define TARGET_SWITCHES \ | |
151 | { { "short", MASK_SHORT, \ | |
152 | N_("Compile with 16-bit integer mode")}, \ | |
153 | { "noshort", - MASK_SHORT, \ | |
154 | N_("Compile with 32-bit integer mode")}, \ | |
155 | { "auto-incdec", MASK_AUTO_INC_DEC, \ | |
156 | N_("Auto pre/post decrement increment allowed")}, \ | |
157 | { "noauto-incdec", - MASK_AUTO_INC_DEC, \ | |
158 | N_("Auto pre/post decrement increment not allowed")}, \ | |
159 | { "68hc11", MASK_M6811, \ | |
160 | N_("Compile for a 68HC11")}, \ | |
161 | { "68hc12", MASK_M6812, \ | |
162 | N_("Compile for a 68HC12")}, \ | |
163 | { "6811", MASK_M6811, \ | |
164 | N_("Compile for a 68HC11")}, \ | |
165 | { "6812", MASK_M6812, \ | |
166 | N_("Compile for a 68HC12")}, \ | |
167 | { "", TARGET_DEFAULT, 0 }} | |
168 | ||
169 | /* This macro is similar to `TARGET_SWITCHES' but defines names of | |
170 | command options that have values. Its definition is an | |
171 | initializer with a subgrouping for each command option. | |
172 | ||
173 | Each subgrouping contains a string constant, that defines the | |
174 | fixed part of the option name, and the address of a variable. The | |
175 | variable, type `char *', is set to the variable part of the given | |
176 | option if the fixed part matches. The actual option name is made | |
177 | by appending `-m' to the specified name. */ | |
178 | #define TARGET_OPTIONS \ | |
179 | { { "reg-alloc=", &m68hc11_reg_alloc_order, \ | |
180 | N_("Specify the register allocation order")}, \ | |
181 | { "soft-reg-count=", &m68hc11_soft_reg_count, \ | |
182 | N_("Indicate the number of soft registers available") }, \ | |
183 | SUBTARGET_OPTIONS \ | |
184 | } | |
185 | ||
186 | /* These are meant to be redefined in the host dependent files */ | |
187 | #define SUBTARGET_SWITCHES | |
188 | #define SUBTARGET_OPTIONS | |
189 | ||
190 | extern const char *m68hc11_regparm_string; | |
191 | extern const char *m68hc11_reg_alloc_order; | |
192 | extern const char *m68hc11_soft_reg_count; | |
193 | ||
194 | #ifndef TARGET_M68HC12 | |
195 | # define TARGET_M68HC11 1 | |
196 | #endif | |
197 | ||
198 | /* Print subsidiary information on the compiler version in use. */ | |
199 | #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12)") | |
200 | ||
201 | /* Sometimes certain combinations of command options do not make | |
202 | sense on a particular target machine. You can define a macro | |
203 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
204 | defined, is executed once just after all the command options have | |
205 | been parsed. | |
206 | ||
207 | Don't use this macro to turn on various extra optimizations for | |
208 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
209 | ||
210 | #define OVERRIDE_OPTIONS m68hc11_override_options (); | |
01beec65 SC |
211 | |
212 | \f | |
213 | /* Define cost parameters for a given processor variant. */ | |
214 | struct processor_costs { | |
8b60264b KG |
215 | const int add; /* cost of an add instruction */ |
216 | const int logical; /* cost of a logical instruction */ | |
217 | const int shift_var; | |
218 | const int shiftQI_const[8]; | |
219 | const int shiftHI_const[16]; | |
220 | const int multQI; | |
221 | const int multHI; | |
222 | const int multSI; | |
223 | const int divQI; | |
224 | const int divHI; | |
225 | const int divSI; | |
01beec65 SC |
226 | }; |
227 | ||
228 | /* Costs for the current processor. */ | |
8b60264b | 229 | extern const struct processor_costs *m68hc11_cost; |
385c9217 SC |
230 | \f |
231 | ||
232 | /* target machine storage layout */ | |
233 | ||
234 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
235 | #define BYTES_BIG_ENDIAN 1 | |
236 | ||
237 | /* Define this if most significant bit is lowest numbered | |
9caea35c | 238 | in instructions that operate on numbered bit-fields. */ |
385c9217 SC |
239 | #define BITS_BIG_ENDIAN 0 |
240 | ||
241 | /* Define this if most significant word of a multiword number is numbered. */ | |
242 | #define WORDS_BIG_ENDIAN 1 | |
243 | ||
244 | /* Number of bits in an addressible storage unit */ | |
245 | #define BITS_PER_UNIT 8 | |
246 | ||
247 | /* Number of bits in a word */ | |
248 | #define BITS_PER_WORD 16 | |
249 | ||
250 | /* Width of a word, in units (bytes). */ | |
251 | #define UNITS_PER_WORD (BITS_PER_WORD/8) | |
252 | ||
253 | /* Define if you don't want extended real, but do want to use the | |
254 | software floating point emulator for REAL_ARITHMETIC and | |
255 | decimal <-> binary conversion. */ | |
256 | #define REAL_ARITHMETIC | |
257 | ||
258 | /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ | |
259 | #define POINTER_SIZE 16 | |
260 | ||
261 | /* Definition of size_t. This is really an unsigned short as the | |
262 | 68hc11 only handles a 64K address space. */ | |
263 | #define SIZE_TYPE "short unsigned int" | |
264 | ||
265 | /* A C expression for a string describing the name of the data type | |
266 | to use for the result of subtracting two pointers. The typedef | |
267 | name `ptrdiff_t' is defined using the contents of the string. | |
268 | The 68hc11 only has a 64K address space. */ | |
269 | #define PTRDIFF_TYPE "short int" | |
270 | ||
271 | /* Allocation boundary (bits) for storing pointers in memory. */ | |
272 | #define POINTER_BOUNDARY 8 | |
273 | ||
274 | /* Normal alignment required for function parameters on the stack, in bits. | |
275 | This can't be less than BITS_PER_WORD */ | |
276 | #define PARM_BOUNDARY (BITS_PER_WORD) | |
277 | ||
278 | /* Boundary (bits) on which stack pointer should be aligned. */ | |
279 | #define STACK_BOUNDARY 8 | |
280 | ||
281 | /* Allocation boundary (bits) for the code of a function. */ | |
282 | #define FUNCTION_BOUNDARY 8 | |
283 | ||
385c9217 SC |
284 | #define BIGGEST_ALIGNMENT 8 |
285 | ||
286 | /* Alignment of field after `int : 0' in a structure. */ | |
287 | #define EMPTY_FIELD_BOUNDARY 8 | |
288 | ||
289 | /* Every structure's size must be a multiple of this. */ | |
290 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
291 | ||
292 | /* Define this if instructions will fail to work if given data not | |
293 | on the nominal alignment. If instructions will merely go slower | |
294 | in that case, do not define this macro. */ | |
295 | #define STRICT_ALIGNMENT 0 | |
296 | ||
297 | /* An integer expression for the size in bits of the largest integer | |
298 | machine mode that should actually be used. All integer machine modes of | |
299 | this size or smaller can be used for structures and unions with the | |
300 | appropriate sizes. */ | |
301 | #define MAX_FIXED_MODE_SIZE 64 | |
302 | ||
9caea35c | 303 | /* Floats are checked in a generic way. */ |
385c9217 SC |
304 | /* #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) */ |
305 | ||
306 | ||
307 | \f | |
308 | /* target machine storage layout */ | |
309 | ||
310 | /* Size (bits) of the type "int" on target machine | |
311 | (If undefined, default is BITS_PER_WORD). */ | |
312 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) | |
313 | ||
314 | /* Size (bits) of the type "short" on target machine */ | |
315 | #define SHORT_TYPE_SIZE 16 | |
316 | ||
317 | /* Size (bits) of the type "long" on target machine */ | |
318 | #define LONG_TYPE_SIZE 32 | |
319 | ||
320 | /* Size (bits) of the type "long long" on target machine */ | |
321 | #define LONG_LONG_TYPE_SIZE 64 | |
322 | ||
323 | /* Size (bits) of the type "char" on target machine */ | |
324 | #define CHAR_TYPE_SIZE 8 | |
325 | ||
326 | /* A C expression for the size in bits of the type `float' on the | |
327 | target machine. If you don't define this, the default is one word. | |
328 | Don't use default: a word is only 16. */ | |
329 | #define FLOAT_TYPE_SIZE 32 | |
330 | ||
331 | /* A C expression for the size in bits of the type double on the target | |
332 | machine. If you don't define this, the default is two words. | |
333 | Be IEEE compliant. */ | |
334 | #define DOUBLE_TYPE_SIZE 64 | |
335 | ||
336 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
337 | ||
338 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
339 | #define DEFAULT_SIGNED_CHAR 0 | |
340 | ||
341 | /* Define these to avoid dependence on meaning of `int'. | |
342 | Note that WCHAR_TYPE_SIZE is used in cexp.y, | |
343 | where TARGET_SHORT is not available. */ | |
344 | #define WCHAR_TYPE "short int" | |
345 | #define WCHAR_TYPE_SIZE 16 | |
385c9217 SC |
346 | \f |
347 | ||
348 | /* Standard register usage. */ | |
349 | ||
350 | #define HARD_REG_SIZE (UNITS_PER_WORD) | |
351 | ||
352 | /* Assign names to real MC68HC11 registers. | |
353 | A and B registers are not really used (A+B = D) | |
354 | X register is first so that GCC allocates X+D for 32-bit integers and | |
355 | the lowpart of that integer will be D. Having the lower part in D is | |
356 | better for 32<->16bit conversions and for many arithmetic operations. */ | |
357 | #define HARD_X_REGNUM 0 | |
358 | #define HARD_D_REGNUM 1 | |
359 | #define HARD_Y_REGNUM 2 | |
360 | #define HARD_SP_REGNUM 3 | |
361 | #define HARD_PC_REGNUM 4 | |
362 | #define HARD_A_REGNUM 5 | |
363 | #define HARD_B_REGNUM 6 | |
364 | #define HARD_CCR_REGNUM 7 | |
365 | ||
366 | /* The Z register does not really exist in the 68HC11. This a fake register | |
367 | for GCC. It is treated exactly as an index register (X or Y). It is only | |
368 | in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this | |
369 | register helps the reload pass of GCC. Otherwise, the reload often aborts | |
370 | with register spill failures. | |
371 | ||
372 | The Z register is replaced by either X or Y during the machine specific | |
373 | reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register | |
374 | when this is necessary. | |
375 | ||
376 | It's possible to tell GCC not to use this register with -ffixed-z. */ | |
377 | #define HARD_Z_REGNUM 8 | |
378 | ||
379 | /* The frame pointer is a soft-register. It's treated as such by GCC: | |
380 | it is not and must not be part of the BASE_REG_CLASS. */ | |
381 | #define DEFAULT_HARD_FP_REGNUM (9) | |
382 | #define HARD_FP_REGNUM (9) | |
383 | #define HARD_AP_REGNUM (HARD_FP_REGNUM) | |
384 | ||
385 | /* Temporary soft-register used in some cases when an operand came | |
386 | up into a bad register class (D, X, Y, SP) and gcc failed to | |
387 | recognize this. This register is never allocated by GCC. */ | |
388 | #define SOFT_TMP_REGNUM 10 | |
389 | ||
390 | /* The soft-register which is used to save the Z register | |
391 | (see Z register replacement notes in m68hc11.c). */ | |
392 | #define SOFT_Z_REGNUM 11 | |
393 | ||
9caea35c | 394 | /* The soft-register which is used to save either X or Y. */ |
385c9217 SC |
395 | #define SOFT_SAVED_XY_REGNUM 12 |
396 | ||
397 | /* A fake clobber register for 68HC12 patterns. */ | |
398 | #define FAKE_CLOBBER_REGNUM (13) | |
399 | ||
400 | /* Define 32 soft-registers of 16-bit each. By default, | |
401 | only 12 of them are enabled and can be used by GCC. The | |
402 | -msoft-reg-count=<n> option allows to control the number of valid | |
403 | soft-registers. GCC can put 32-bit values in them | |
404 | by allocating consecutive registers. The first 3 soft-registers | |
405 | are never allocated by GCC. They are used in case the insn template needs | |
406 | a temporary register, or for the Z register replacement. */ | |
407 | ||
408 | #define MAX_SOFT_REG_COUNT (32) | |
409 | #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \ | |
410 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
411 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
412 | 1, 1, 1, 1, 1, 1, 1, 1 | |
413 | #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \ | |
414 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
415 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
416 | 1, 1, 1, 1, 1, 1, 1, 1 | |
417 | #define SOFT_REG_ORDER \ | |
418 | SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\ | |
419 | SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\ | |
420 | SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\ | |
421 | SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\ | |
422 | SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\ | |
423 | SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\ | |
424 | SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\ | |
425 | SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31 | |
426 | ||
427 | #define SOFT_REG_NAMES \ | |
428 | "*_.d1", "*_.d2", "*_.d3", "*_.d4", \ | |
429 | "*_.d5", "*_.d6", "*_.d7", "*_.d8", \ | |
430 | "*_.d9", "*_.d10", "*_.d11", "*_.d12", \ | |
431 | "*_.d13", "*_.d14", "*_.d15", "*_.d16", \ | |
432 | "*_.d17", "*_.d18", "*_.d19", "*_.d20", \ | |
433 | "*_.d21", "*_.d22", "*_.d23", "*_.d24", \ | |
434 | "*_.d25", "*_.d26", "*_.d27", "*_.d28", \ | |
435 | "*_.d29", "*_.d30", "*_.d31", "*_.d32" | |
436 | ||
9caea35c | 437 | /* First available soft-register for GCC. */ |
385c9217 SC |
438 | #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2) |
439 | ||
9caea35c | 440 | /* Last available soft-register for GCC. */ |
385c9217 SC |
441 | #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT) |
442 | #define SOFT_FP_REGNUM (SOFT_REG_LAST) | |
443 | #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1) | |
444 | ||
445 | /* Number of actual hardware registers. The hardware registers are assigned | |
446 | numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. | |
447 | All registers that the compiler knows about must be given numbers, even | |
9caea35c | 448 | those that are not normally considered general registers. */ |
385c9217 SC |
449 | #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2) |
450 | ||
451 | /* 1 for registers that have pervasive standard uses and are not available | |
9caea35c | 452 | for the register allocator. */ |
385c9217 SC |
453 | #define FIXED_REGISTERS \ |
454 | {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1} | |
455 | /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */ | |
456 | ||
457 | /* 1 for registers not available across function calls. For our pseudo | |
458 | registers, all are available. */ | |
459 | #define CALL_USED_REGISTERS \ | |
460 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1} | |
461 | /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */ | |
462 | ||
463 | ||
464 | /* Define this macro to change register usage conditional on target flags. | |
465 | ||
466 | The soft-registers are disabled or enabled according to the | |
9caea35c | 467 | -msoft-reg-count=<n> option. */ |
385c9217 SC |
468 | |
469 | ||
470 | #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ()) | |
471 | ||
472 | /* List the order in which to allocate registers. Each register must be | |
473 | listed once, even those in FIXED_REGISTERS. */ | |
474 | #define REG_ALLOC_ORDER \ | |
475 | { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \ | |
476 | SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \ | |
477 | HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \ | |
478 | HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \ | |
479 | SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM } | |
480 | ||
481 | /* A C expression for the number of consecutive hard registers, | |
482 | starting at register number REGNO, required to hold a value of | |
483 | mode MODE. */ | |
484 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
485 | ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \ | |
486 | ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE)) | |
487 | ||
488 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
489 | - 8 bit values are stored anywhere (except the SP register). | |
490 | - 16 bit values can be stored in any register whose mode is 16 | |
491 | - 32 bit values can be stored in D, X registers or in a soft register | |
492 | (except the last one because we need 2 soft registers) | |
493 | - Values whose size is > 32 bit are not stored in real hard | |
494 | registers. They may be stored in soft registers if there are | |
495 | enough of them. */ | |
496 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
497 | hard_regno_mode_ok (REGNO,MODE) | |
498 | ||
499 | /* Value is 1 if it is a good idea to tie two pseudo registers when one has | |
500 | mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce | |
501 | different values for MODE1 and MODE2, for any hard reg, then this must be | |
502 | 0 for correct output. */ | |
503 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
504 | (((MODE1) == (MODE2)) \ | |
505 | || ((MODE1) == SImode && (MODE2) == HImode) \ | |
506 | || ((MODE1) == HImode && (MODE2) == SImode)) | |
507 | \f | |
508 | ||
509 | /* Define the classes of registers for register constraints in the | |
510 | machine description. Also define ranges of constants. | |
511 | ||
512 | One of the classes must always be named ALL_REGS and include all hard regs. | |
513 | If there is more than one class, another class must be named NO_REGS | |
514 | and contain no registers. | |
515 | ||
516 | The name GENERAL_REGS must be the name of a class (or an alias for | |
517 | another name such as ALL_REGS). This is the class of registers | |
518 | that is allowed by "g" or "r" in a register constraint. | |
519 | Also, registers outside this class are allocated only when | |
520 | instructions express preferences for them. | |
521 | ||
522 | The classes must be numbered in nondecreasing order; that is, | |
523 | a larger-numbered class must never be contained completely | |
524 | in a smaller-numbered class. | |
525 | ||
526 | For any two classes, it is very desirable that there be another | |
527 | class that represents their union. */ | |
528 | ||
529 | /* The M68hc11 has so fiew registers that it's not possible for GCC to | |
530 | do any register allocation without breaking. We extend the processor | |
531 | registers by having soft registers. These registers are treated as | |
532 | hard registers by GCC but they are located in memory and accessed by page0 | |
533 | accesses (IND mode). */ | |
534 | enum reg_class | |
535 | { | |
536 | NO_REGS, | |
537 | D_REGS, /* 16-bit data register */ | |
538 | X_REGS, /* 16-bit X register */ | |
539 | Y_REGS, /* 16-bit Y register */ | |
540 | SP_REGS, /* 16 bit stack pointer */ | |
9caea35c KH |
541 | DA_REGS, /* 8-bit A reg. */ |
542 | DB_REGS, /* 8-bit B reg. */ | |
385c9217 | 543 | Z_REGS, /* 16-bit fake Z register */ |
9caea35c | 544 | D8_REGS, /* 8-bit A or B reg. */ |
385c9217 SC |
545 | Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */ |
546 | D_OR_X_REGS, /* D or X register */ | |
547 | D_OR_Y_REGS, /* D or Y register */ | |
548 | D_OR_SP_REGS, /* D or SP register */ | |
549 | X_OR_Y_REGS, /* IX or Y register */ | |
550 | A_REGS, /* 16-bit address register (X, Y, Z) */ | |
551 | X_OR_SP_REGS, /* X or SP register */ | |
552 | Y_OR_SP_REGS, /* Y or SP register */ | |
553 | X_OR_Y_OR_D_REGS, /* X, Y or D */ | |
554 | A_OR_D_REGS, /* X, Y, Z or D */ | |
555 | A_OR_SP_REGS, /* X, Y, Z or SP */ | |
556 | H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */ | |
557 | S_REGS, /* 16-bit soft register */ | |
558 | D_OR_S_REGS, /* 16-bit soft register or D register */ | |
559 | X_OR_S_REGS, /* 16-bit soft register or X register */ | |
560 | Y_OR_S_REGS, /* 16-bit soft register or Y register */ | |
561 | SP_OR_S_REGS, /* 16-bit soft register or SP register */ | |
562 | D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */ | |
563 | D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */ | |
564 | D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */ | |
565 | A_OR_S_REGS, /* 16-bit soft register or X, Y registers */ | |
566 | D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */ | |
567 | TMP_REGS, /* 16 bit fake scratch register */ | |
568 | D_OR_A_OR_TMP_REGS, /* General scratch register */ | |
569 | G_REGS, /* 16-bit general register | |
570 | (H_REGS + soft registers) */ | |
571 | ALL_REGS, | |
572 | LIM_REG_CLASSES | |
573 | }; | |
574 | ||
9caea35c | 575 | /* alias GENERAL_REGS to G_REGS. */ |
385c9217 SC |
576 | #define GENERAL_REGS G_REGS |
577 | ||
578 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
579 | ||
9caea35c | 580 | /* Give names of register classes as strings for dump file. */ |
385c9217 SC |
581 | #define REG_CLASS_NAMES \ |
582 | { "NO_REGS", \ | |
583 | "D_REGS", \ | |
584 | "X_REGS", \ | |
585 | "Y_REGS", \ | |
586 | "SP_REGS", \ | |
587 | "DA_REGS", \ | |
588 | "DB_REGS", \ | |
589 | "D8_REGS", \ | |
590 | "Z_REGS", \ | |
591 | "Q_REGS", \ | |
592 | "D_OR_X_REGS", \ | |
593 | "D_OR_Y_REGS", \ | |
594 | "D_OR_SP_REGS", \ | |
595 | "X_OR_Y_REGS", \ | |
596 | "A_REGS", \ | |
597 | "X_OR_SP_REGS", \ | |
598 | "Y_OR_SP_REGS", \ | |
599 | "X_OR_Y_OR_D_REGS", \ | |
600 | "A_OR_D_REGS", \ | |
601 | "A_OR_SP_REGS", \ | |
602 | "H_REGS", \ | |
603 | "S_REGS", \ | |
604 | "D_OR_S_REGS", \ | |
605 | "X_OR_S_REGS", \ | |
606 | "Y_OR_S_REGS", \ | |
607 | "SP_OR_S_REGS", \ | |
608 | "D_OR_X_OR_S_REGS", \ | |
609 | "D_OR_Y_OR_S_REGS", \ | |
610 | "D_OR_SP_OR_S_REGS", \ | |
611 | "A_OR_S_REGS", \ | |
612 | "D_OR_A_OR_S_REGS", \ | |
613 | "TMP_REGS", \ | |
614 | "D_OR_A_OR_TMP_REGS", \ | |
615 | "G_REGS", \ | |
616 | "ALL_REGS" } | |
617 | ||
618 | /* An initializer containing the contents of the register classes, | |
619 | as integers which are bit masks. The Nth integer specifies the | |
620 | contents of class N. The way the integer MASK is interpreted is | |
621 | that register R is in the class if `MASK & (1 << R)' is 1. */ | |
622 | ||
623 | /*-------------------------------------------------------------- | |
624 | X 0x00000001 | |
625 | D 0x00000002 | |
626 | Y 0x00000004 | |
627 | SP 0x00000008 | |
628 | PC 0x00000010 | |
629 | A 0x00000020 | |
630 | B 0x00000040 | |
631 | CCR 0x00000080 | |
632 | Z 0x00000100 | |
633 | FRAME 0x00000200 | |
634 | ZTMP 0x00000400 | |
635 | ZREG 0x00000800 | |
636 | XYREG 0x00001000 | |
637 | FAKE 0x00002000 | |
638 | Di 0xFFFFc000, 0x03FFF | |
639 | SFRAME 0x00000000, 0x04000 | |
640 | AP 0x00000000, 0x08000 | |
641 | ||
642 | D_OR_X_REGS represents D+X. It is used for 32-bits numbers. | |
643 | A_REGS represents a valid base register for indexing. It represents | |
644 | X,Y and the Z register. | |
645 | S_REGS represents the soft-registers. This includes the hard frame | |
646 | and soft frame registers. | |
647 | --------------------------------------------------------------*/ | |
648 | ||
649 | #define REG_CLASS_CONTENTS \ | |
650 | /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \ | |
651 | /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \ | |
652 | /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \ | |
653 | /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \ | |
654 | /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \ | |
655 | /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \ | |
656 | /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \ | |
657 | /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \ | |
658 | /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \ | |
659 | /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \ | |
660 | /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \ | |
661 | /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \ | |
662 | /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \ | |
663 | /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \ | |
664 | /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \ | |
665 | /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \ | |
666 | /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \ | |
667 | /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \ | |
668 | /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \ | |
669 | /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \ | |
670 | /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \ | |
671 | /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \ | |
672 | /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \ | |
673 | /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \ | |
674 | /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \ | |
675 | /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \ | |
676 | /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \ | |
677 | /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \ | |
678 | /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \ | |
679 | /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \ | |
680 | /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \ | |
681 | /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \ | |
682 | /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \ | |
683 | /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \ | |
684 | /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }} | |
685 | ||
686 | ||
687 | /* set up a C expression whose value is a register class containing hard | |
688 | register REGNO */ | |
689 | #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \ | |
690 | || (REGNO) == HARD_B_REGNUM) | |
691 | #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X))) | |
692 | ||
693 | #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM) | |
694 | #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) | |
695 | ||
696 | #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM) | |
697 | #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X))) | |
698 | #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM) | |
699 | #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X))) | |
700 | ||
701 | #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM) | |
702 | #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X))) | |
703 | ||
704 | #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM) | |
705 | #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X))) | |
706 | ||
7bdf2c65 SC |
707 | #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) |
708 | #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) | |
709 | ||
385c9217 SC |
710 | #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM) |
711 | #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X))) | |
712 | ||
713 | /* Address register. */ | |
714 | #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \ | |
715 | || (REGNO) == HARD_Y_REGNUM \ | |
716 | || (REGNO) == HARD_Z_REGNUM) | |
717 | #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) | |
718 | ||
719 | /* M68hc11 hard registers. */ | |
720 | #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \ | |
721 | || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO)) | |
722 | #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X))) | |
723 | ||
724 | #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM) | |
725 | #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X))) | |
726 | ||
727 | /* Soft registers (or register emulation for gcc). The temporary register | |
728 | used by insn template must be part of the S_REGS class so that it | |
729 | matches the 'u' constraint. */ | |
730 | #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \ | |
731 | && (REGNO) <= SOFT_REG_LAST \ | |
732 | && (REGNO) != FAKE_CLOBBER_REGNUM) | |
733 | #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) | |
734 | ||
735 | #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) | |
736 | #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) | |
737 | ||
738 | /* General register. */ | |
739 | #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \ | |
740 | || ((REGNO) == HARD_PC_REGNUM) \ | |
741 | || ((REGNO) == HARD_FP_REGNUM) \ | |
742 | || ((REGNO) == SOFT_FP_REGNUM) \ | |
743 | || ((REGNO) == FAKE_CLOBBER_REGNUM) \ | |
744 | || ((REGNO) == SOFT_AP_REGNUM)) | |
745 | ||
746 | #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X))) | |
747 | ||
748 | #define REGNO_REG_CLASS(REGNO) \ | |
749 | (D_REGNO_P (REGNO) ? D_REGS : \ | |
750 | (X_REGNO_P (REGNO) ? X_REGS : \ | |
751 | (Y_REGNO_P (REGNO) ? Y_REGS : \ | |
752 | (SP_REGNO_P (REGNO) ? SP_REGS : \ | |
753 | (Z_REGNO_P (REGNO) ? Z_REGS : \ | |
754 | (H_REGNO_P (REGNO) ? H_REGS : \ | |
755 | (FAKE_REGNO_P (REGNO) ? TMP_REGS : \ | |
756 | (S_REGNO_P (REGNO) ? S_REGS : \ | |
757 | (DA_REGNO_P (REGNO) ? DA_REGS: \ | |
758 | (DB_REGNO_P (REGNO) ? DB_REGS: \ | |
759 | (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))) | |
760 | ||
761 | ||
762 | /* Get reg_class from a letter in the machine description. */ | |
763 | ||
764 | extern enum reg_class m68hc11_tmp_regs_class; | |
765 | #define REG_CLASS_FROM_LETTER(C) \ | |
766 | ((C) == 'a' ? DA_REGS : \ | |
767 | (C) == 'A' ? A_REGS : \ | |
768 | (C) == 'b' ? DB_REGS : \ | |
769 | (C) == 'B' ? X_OR_Y_REGS : \ | |
770 | (C) == 'd' ? D_REGS : \ | |
771 | (C) == 'D' ? D_OR_X_REGS : \ | |
772 | (C) == 'q' ? Q_REGS : \ | |
773 | (C) == 'h' ? H_REGS : \ | |
774 | (C) == 't' ? TMP_REGS : \ | |
775 | (C) == 'u' ? S_REGS : \ | |
776 | (C) == 'v' ? m68hc11_tmp_regs_class : \ | |
777 | (C) == 'w' ? SP_REGS : \ | |
778 | (C) == 'x' ? X_REGS : \ | |
779 | (C) == 'y' ? Y_REGS : \ | |
780 | (C) == 'z' ? Z_REGS : NO_REGS) | |
781 | ||
782 | #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS) | |
783 | ||
385c9217 SC |
784 | #define SMALL_REGISTER_CLASSES 1 |
785 | ||
786 | /* A C expression whose value is nonzero if pseudos that have been | |
787 | assigned to registers of class CLASS would likely be spilled | |
788 | because registers of CLASS are needed for spill registers. | |
789 | ||
790 | The default value of this macro returns 1 if CLASS has exactly one | |
791 | register and zero otherwise. On most machines, this default | |
792 | should be used. Only define this macro to some other expression | |
793 | if pseudo allocated by `local-alloc.c' end up in memory because | |
794 | their hard registers were needed for spill registers. If this | |
795 | macro returns nonzero for those classes, those pseudos will only | |
796 | be allocated by `global.c', which knows how to reallocate the | |
797 | pseudo to another register. If there would not be another | |
798 | register available for reallocation, you should not change the | |
799 | definition of this macro since the only effect of such a | |
800 | definition would be to slow down register allocation. */ | |
801 | ||
802 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
803 | (((CLASS) == D_REGS) \ | |
804 | || ((CLASS) == X_REGS) \ | |
805 | || ((CLASS) == Y_REGS) \ | |
806 | || ((CLASS) == A_REGS) \ | |
807 | || ((CLASS) == SP_REGS) \ | |
808 | || ((CLASS) == D_OR_X_REGS) \ | |
809 | || ((CLASS) == D_OR_Y_REGS) \ | |
810 | || ((CLASS) == X_OR_SP_REGS) \ | |
811 | || ((CLASS) == Y_OR_SP_REGS) \ | |
812 | || ((CLASS) == D_OR_SP_REGS)) | |
813 | ||
814 | /* Return the maximum number of consecutive registers needed to represent | |
815 | mode MODE in a register of class CLASS. */ | |
816 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
817 | (((CLASS) == DA_REGS || (CLASS) == DB_REGS \ | |
818 | || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \ | |
819 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
820 | ||
821 | /* The letters I, J, K, L and M in a register constraint string | |
822 | can be used to stand for particular ranges of immediate operands. | |
823 | This macro defines what the ranges are. | |
824 | C is the letter, and VALUE is a constant value. | |
825 | Return 1 if VALUE is in the range specified by C. | |
826 | ||
827 | `L' is for range -65536 to 65536 | |
828 | `M' is for values whose 16-bit low part is 0 | |
829 | 'N' is for +1 or -1. | |
830 | 'O' is for 16 (for rotate using swap). | |
831 | 'P' is for range -8 to 2 (used by addhi_sp) | |
832 | ||
833 | 'I', 'J', 'K' are not used. */ | |
834 | ||
835 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
836 | ((C) == 'L' ? (VALUE) >= -65536 && (VALUE) <= 65535 : \ | |
837 | (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \ | |
838 | (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1): \ | |
839 | (C) == 'O' ? (VALUE) == 16 : \ | |
840 | (C) == 'P' ? (VALUE) <= 2 && (VALUE) >= -8 : 0) | |
841 | ||
842 | /* Similar, but for floating constants, and defining letters G and H. | |
843 | No floating-point constants are valid on 68HC11. */ | |
844 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 | |
845 | ||
846 | /* 'U' represents certain kind of memory indexed operand for 68HC12. | |
847 | and any memory operand for 68HC11. */ | |
848 | #define EXTRA_CONSTRAINT(OP, C) \ | |
849 | ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) : 0) | |
850 | ||
851 | ||
852 | \f | |
853 | /* Stack layout; function entry, exit and calling. */ | |
854 | ||
855 | /* Define this if pushing a word on the stack | |
856 | makes the stack pointer a smaller address. */ | |
857 | #define STACK_GROWS_DOWNWARD | |
858 | ||
859 | /* Define this if the nominal address of the stack frame | |
860 | is at the high-address end of the local variables; | |
861 | that is, each additional local variable allocated | |
862 | goes at a more negative offset in the frame. | |
863 | ||
864 | Don't define for 68HC11, the frame pointer is the bottom | |
865 | of local variables. */ | |
866 | /* #define FRAME_GROWS_DOWNWARD */ | |
867 | ||
868 | /* Define this if successive arguments to a function occupy decreasing | |
869 | addresses in the stack. */ | |
870 | /* #define ARGS_GROW_DOWNWARD */ | |
871 | ||
872 | /* Offset within stack frame to start allocating local variables at. | |
873 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
874 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
875 | of the first local allocated. */ | |
8dd5d49d | 876 | #define STARTING_FRAME_OFFSET 0 |
385c9217 SC |
877 | |
878 | /* Offset of first parameter from the argument pointer register value. */ | |
879 | ||
880 | #define FIRST_PARM_OFFSET(FNDECL) 2 | |
881 | ||
35f0a736 | 882 | /* After the prologue, RA is at 0(AP) in the current frame. */ |
5becdf11 SC |
883 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
884 | ((COUNT) == 0 \ | |
35f0a736 | 885 | ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ |
5becdf11 SC |
886 | : 0) |
887 | ||
385c9217 SC |
888 | /* Before the prologue, the top of the frame is at 2(sp). */ |
889 | #define INCOMING_FRAME_SP_OFFSET 2 | |
890 | ||
891 | /* Define this if functions should assume that stack space has been | |
892 | allocated for arguments even when their values are passed in | |
893 | registers. | |
894 | ||
895 | The value of this macro is the size, in bytes, of the area reserved for | |
896 | arguments passed in registers. | |
897 | ||
898 | This space can either be allocated by the caller or be a part of the | |
899 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' | |
9caea35c | 900 | says which. */ |
385c9217 SC |
901 | /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */ |
902 | ||
903 | /* Define this macro if REG_PARM_STACK_SPACE is defined but stack | |
904 | parameters don't skip the area specified by REG_PARM_STACK_SPACE. | |
905 | Normally, when a parameter is not passed in registers, it is placed on | |
906 | the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro | |
907 | suppresses this behavior and causes the parameter to be passed on the | |
908 | stack in its natural location. */ | |
909 | /* #define STACK_PARMS_IN_REG_PARM_AREA */ | |
910 | ||
911 | /* Register to use for pushing function arguments. */ | |
912 | #define STACK_POINTER_REGNUM HARD_SP_REGNUM | |
913 | ||
914 | /* Base register for access to local variables of the function. */ | |
915 | #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM | |
916 | ||
917 | #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM | |
918 | ||
919 | /* Base register for access to arguments of the function. */ | |
920 | #define ARG_POINTER_REGNUM SOFT_AP_REGNUM | |
921 | ||
922 | /* Register in which static-chain is passed to a function. */ | |
7bdf2c65 | 923 | #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM |
385c9217 SC |
924 | |
925 | \f | |
926 | /* Definitions for register eliminations. | |
927 | ||
928 | This is an array of structures. Each structure initializes one pair | |
929 | of eliminable registers. The "from" register number is given first, | |
930 | followed by "to". Eliminations of the same "from" register are listed | |
931 | in order of preference. | |
932 | ||
933 | We have two registers that are eliminated on the 6811. The psuedo arg | |
934 | pointer and pseudo frame pointer registers can always be eliminated; | |
9caea35c | 935 | they are replaced with either the stack or the real frame pointer. */ |
385c9217 SC |
936 | |
937 | #define ELIMINABLE_REGS \ | |
938 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
939 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
940 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
941 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
942 | ||
943 | /* Value should be nonzero if functions must have frame pointers. | |
944 | Zero means the frame pointer need not be set up (and parms may be | |
945 | accessed via the stack pointer) in functions that seem suitable. | |
9caea35c | 946 | This is computed in `reload', in reload1.c. */ |
385c9217 SC |
947 | #define FRAME_POINTER_REQUIRED 0 |
948 | ||
949 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
950 | Frame pointer elimination is automatically handled. | |
951 | ||
952 | All other eliminations are valid. */ | |
953 | ||
954 | #define CAN_ELIMINATE(FROM, TO) \ | |
955 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
956 | ? ! frame_pointer_needed \ | |
957 | : 1) | |
958 | ||
959 | ||
960 | /* Define the offset between two registers, one to be eliminated, and the other | |
961 | its replacement, at the start of a routine. */ | |
962 | ||
963 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
964 | { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); } | |
965 | ||
385c9217 SC |
966 | \f |
967 | /* Passing Function Arguments on the Stack. */ | |
968 | ||
969 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
970 | /* #define PROMOTE_PROTOTYPES */ | |
971 | ||
972 | /* If we generate an insn to push BYTES bytes, this says how many the | |
973 | stack pointer really advances by. No rounding or alignment needed | |
9caea35c | 974 | for MC6811. */ |
385c9217 SC |
975 | #define PUSH_ROUNDING(BYTES) (BYTES) |
976 | ||
977 | /* Value is 1 if returning from a function call automatically pops the | |
978 | arguments described by the number-of-args field in the call. FUNTYPE is | |
979 | the data type of the function (as a tree), or for a library call it is | |
980 | an identifier node for the subroutine name. | |
981 | ||
982 | The standard MC6811 call, with arg count word, includes popping the | |
9caea35c | 983 | args as part of the call template. */ |
385c9217 SC |
984 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
985 | ||
986 | /* Nonzero if type TYPE should be returned in memory. | |
987 | Blocks and data types largers than 4 bytes cannot be returned | |
988 | in the register (D + X = 4). */ | |
989 | #define RETURN_IN_MEMORY(TYPE) \ | |
990 | ((TYPE_MODE (TYPE) == BLKmode) \ | |
991 | ? (int_size_in_bytes (TYPE) > 4) \ | |
992 | : (GET_MODE_SIZE (TYPE_MODE (TYPE)) > 4)) | |
993 | ||
994 | \f | |
995 | /* Passing Arguments in Registers. */ | |
996 | ||
997 | /* Define a data type for recording info about an argument list | |
998 | during the scan of that argument list. This data type should | |
999 | hold all necessary information about the function itself | |
1000 | and about the args processed so far, enough to enable macros | |
1001 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
1002 | ||
1003 | typedef struct m68hc11_args | |
1004 | { | |
1005 | int words; | |
1006 | int nregs; | |
1007 | } CUMULATIVE_ARGS; | |
1008 | ||
1009 | /* A C expression that indicates when an argument must be passed by reference. | |
1010 | If nonzero for an argument, a copy of that argument is made in memory and a | |
1011 | pointer to the argument is passed instead of the argument itself. | |
1012 | The pointer is passed in whatever way is appropriate for passing a pointer | |
1013 | to that type. | |
1014 | ||
9caea35c | 1015 | 64-bit numbers are passed by reference. */ |
385c9217 SC |
1016 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
1017 | m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) | |
1018 | ||
1019 | ||
1020 | /* If defined, a C expression which determines whether, and in which direction, | |
1021 | to pad out an argument with extra space. The value should be of type | |
1022 | `enum direction': either `upward' to pad above the argument, | |
1023 | `downward' to pad below, or `none' to inhibit padding. | |
1024 | ||
1025 | Structures are stored left shifted in their argument slot. */ | |
1026 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
1027 | m68hc11_function_arg_padding ((MODE), (TYPE)) | |
1028 | ||
1029 | /* A C expression that indicates when it is the called function's | |
1030 | responsibility to make a copy of arguments passed by invisible | |
1031 | reference. Normally, the caller makes a copy and passes the | |
1032 | address of the copy to the routine being called. When | |
1033 | FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller | |
1034 | does not make a copy. Instead, it passes a pointer to the "live" | |
1035 | value. The called function must not modify this value. If it can | |
1036 | be determined that the value won't be modified, it need not make a | |
9caea35c | 1037 | copy; otherwise a copy must be made. */ |
385c9217 SC |
1038 | #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ |
1039 | ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED)) | |
1040 | ||
1041 | /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a | |
9caea35c | 1042 | function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ |
385c9217 SC |
1043 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
1044 | (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) | |
1045 | ||
1046 | /* Update the data in CUM to advance over an argument of mode MODE and data | |
1047 | type TYPE. (TYPE is null for libcalls where that information may not be | |
1048 | available.) */ | |
1049 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1050 | (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED)) | |
1051 | ||
1052 | /* Define where to put the arguments to a function. | |
1053 | Value is zero to push the argument on the stack, | |
1054 | or a hard register in which to store the argument. | |
1055 | ||
1056 | MODE is the argument's machine mode. | |
1057 | TYPE is the data type of the argument (as a tree). | |
1058 | This is null for libcalls where that information may | |
1059 | not be available. | |
1060 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1061 | the preceding args and about the function being called. | |
1062 | NAMED is nonzero if this argument is a named parameter | |
1063 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1064 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1065 | (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED)) | |
1066 | ||
1067 | /* Define the profitability of saving registers around calls. | |
1068 | ||
1069 | Disable this because the saving instructions generated by | |
1070 | caller-save need a reload and the way it is implemented, | |
1071 | it forbids all spill registers at that point. Enabling | |
1072 | caller saving results in spill failure. */ | |
1073 | #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 | |
1074 | ||
1075 | /* Implement `va_arg'. */ | |
1076 | #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ | |
1077 | m68hc11_expand_builtin_va_start (stdarg, valist, nextarg) | |
1078 | ||
1079 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1080 | m68hc11_va_arg (valist, type) | |
1081 | ||
385c9217 SC |
1082 | /* For an arg passed partly in registers and partly in memory, |
1083 | this is the number of registers used. | |
1084 | For args passed entirely in registers or entirely in memory, zero. | |
1085 | ||
1086 | Passing an arg partly in register and memory does not work at all. | |
1087 | Don't do that. */ | |
1088 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) | |
1089 | ||
1090 | /* 1 if N is a possible register number for function argument passing. | |
1091 | D is for 16-bit values, X is for 32-bit (X+D). */ | |
1092 | #define FUNCTION_ARG_REGNO_P(N) \ | |
1093 | (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) | |
1094 | ||
1095 | /* All return values are in the D or X+D registers: | |
1096 | - 8 and 16-bit values are returned in D. | |
1097 | BLKmode are passed in D as pointer. | |
1098 | - 32-bit values are returned in X + D. | |
1099 | The high part is passed in X and the low part in D. | |
1100 | For GCC, the register number must be HARD_X_REGNUM. */ | |
1101 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1102 | gen_rtx (REG, TYPE_MODE (VALTYPE), \ | |
1103 | ((TYPE_MODE (VALTYPE) == BLKmode \ | |
1104 | || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \ | |
1105 | ? HARD_D_REGNUM : HARD_X_REGNUM)) | |
1106 | ||
1107 | #define LIBCALL_VALUE(MODE) \ | |
1108 | gen_rtx (REG, MODE, \ | |
1109 | (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \ | |
1110 | ? HARD_D_REGNUM : HARD_X_REGNUM)) | |
1111 | ||
1112 | /* 1 if N is a possible register number for a function value. */ | |
1113 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
1114 | ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM) | |
1115 | ||
1116 | /* Register in which address to store a structure value is passed to a | |
1117 | function. */ | |
1118 | #define STRUCT_VALUE_REGNUM HARD_D_REGNUM | |
1119 | ||
1120 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1121 | the stack pointer does not matter. The value is tested only in functions | |
1122 | that have frame pointers. No definition is equivalent to always zero. */ | |
1123 | #define EXIT_IGNORE_STACK 0 | |
1124 | ||
1125 | \f | |
1126 | /* Generating Code for Profiling. */ | |
1127 | ||
1128 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
1129 | for profiling a function entry. */ | |
1130 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
f4b00a9a | 1131 | asm_fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO)) |
385c9217 | 1132 | /* Length in units of the trampoline for entering a nested function. */ |
7bdf2c65 | 1133 | #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9) |
385c9217 SC |
1134 | |
1135 | /* A C statement to initialize the variable parts of a trampoline. | |
1136 | ADDR is an RTX for the address of the trampoline; FNADDR is an | |
1137 | RTX for the address of the nested function; STATIC_CHAIN is an | |
1138 | RTX for the static chain value that should be passed to the | |
1139 | function when it is called. */ | |
7bdf2c65 SC |
1140 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1141 | m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
1142 | ||
385c9217 | 1143 | \f |
385c9217 SC |
1144 | /* Define this macro if references to a symbol must be treated |
1145 | differently depending on something about the variable or function | |
1146 | named by the symbol (such as what section it is in). | |
1147 | ||
1148 | For the 68HC11, we want to recognize trap handlers so that we | |
1149 | handle calls to traps in a special manner (by issuing the trap). | |
1150 | This information is stored in SYMBOL_REF_FLAG. */ | |
1151 | ||
1152 | #define ENCODE_SECTION_INFO(DECL) m68hc11_encode_section_info (DECL) | |
1153 | ||
1154 | /* Override what GCC does for section info to let us recognize traps. */ | |
1155 | ||
1156 | #define REDO_SECTION_INFO_P(DECL) 1 | |
1157 | ||
1158 | /* `INIT_TARGET_OPTABS' | |
1159 | Define this macro as a C statement that declares additional library | |
1160 | routines renames existing ones. `init_optabs' calls this macro | |
1161 | after initializing all the normal library routines. | |
1162 | ||
1163 | Overrides the memcpy */ | |
1164 | ||
1165 | #define INIT_TARGET_OPTABS \ | |
1166 | do \ | |
1167 | { \ | |
1168 | memcpy_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcpy"); \ | |
1169 | memcmp_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcmp"); \ | |
1170 | memset_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memset"); \ | |
1171 | } \ | |
1172 | while (0) | |
1173 | ||
1174 | \f | |
1175 | /* Addressing modes, and classification of registers for them. */ | |
1176 | ||
1177 | /* The 68HC12 has all the post/pre increment/decrement modes. */ | |
1178 | #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1179 | #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1180 | #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1181 | #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1182 | ||
1183 | /* The class value for base registers. This depends on the target: | |
1184 | A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value | |
1185 | is stored at init time. */ | |
1186 | extern enum reg_class m68hc11_base_reg_class; | |
1187 | #define BASE_REG_CLASS m68hc11_base_reg_class | |
1188 | ||
1189 | /* The class value for index registers. This is NO_REGS for 68HC11. */ | |
1190 | ||
1191 | extern enum reg_class m68hc11_index_reg_class; | |
1192 | #define INDEX_REG_CLASS m68hc11_index_reg_class | |
1193 | ||
1194 | /* These assume that REGNO is a hard or pseudo reg number. They give nonzero | |
1195 | only if REGNO is a hard reg of the suitable class or a pseudo reg currently | |
1196 | allocated to a suitable hard reg. Since they use reg_renumber, they are | |
1197 | safe only once reg_renumber has been allocated, which happens in | |
1198 | local-alloc.c. */ | |
1199 | ||
1200 | ||
1201 | /* Internal macro, return 1 if REGNO is a valid base register. */ | |
0b29309a | 1202 | #define REG_VALID_P(REGNO) (1) /* ? */ |
385c9217 SC |
1203 | |
1204 | extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER]; | |
1205 | #define REG_VALID_FOR_BASE_P(REGNO) \ | |
1206 | (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \ | |
1207 | && m68hc11_reg_valid_for_base[REGNO]) | |
1208 | ||
1209 | /* Internal macro, return 1 if REGNO is a valid index register. */ | |
1210 | extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER]; | |
1211 | #define REG_VALID_FOR_INDEX_P(REGNO) \ | |
1212 | (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \ | |
1213 | && m68hc11_reg_valid_for_index[REGNO]) | |
1214 | ||
1215 | /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */ | |
1216 | #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ | |
1217 | ((REGNO) >= FIRST_PSEUDO_REGISTER \ | |
1218 | || REG_VALID_FOR_BASE_P (REGNO) \ | |
1219 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
1220 | || (REGNO) == HARD_FRAME_POINTER_REGNUM \ | |
1221 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1222 | || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) | |
1223 | ||
1224 | /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */ | |
1225 | #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ | |
1226 | (TARGET_M6812 \ | |
1227 | && ((REGNO) >= FIRST_PSEUDO_REGISTER \ | |
1228 | || REG_VALID_FOR_INDEX_P (REGNO) \ | |
1229 | || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) | |
1230 | ||
1231 | /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */ | |
1232 | #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \ | |
1233 | ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \ | |
1234 | : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) | |
1235 | ||
1236 | /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */ | |
1237 | #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \ | |
1238 | (TARGET_M6812 \ | |
1239 | && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \ | |
1240 | : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) | |
1241 | ||
1242 | #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \ | |
1243 | ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \ | |
1244 | : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO))) | |
1245 | ||
1246 | #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \ | |
1247 | ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \ | |
1248 | : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO))) | |
1249 | ||
1250 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO) | |
1251 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO) | |
1252 | ||
1253 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X)) | |
1254 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X)) | |
1255 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X)) | |
1256 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X)) | |
1257 | ||
1258 | /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */ | |
1259 | #define IS_STACK_PUSH(operand) \ | |
1260 | ((GET_CODE (operand) == MEM) \ | |
1261 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \ | |
1262 | && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) | |
1263 | ||
1264 | #define IS_STACK_POP(operand) \ | |
1265 | ((GET_CODE (operand) == MEM) \ | |
1266 | && (GET_CODE (XEXP (operand, 0)) == POST_INC) \ | |
1267 | && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) | |
1268 | ||
1269 | /* 1 if X is an rtx for a constant that is a valid address. */ | |
1270 | #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) | |
1271 | ||
1272 | /* Maximum number of registers that can appear in a valid memory address */ | |
1273 | #define MAX_REGS_PER_ADDRESS 2 | |
1274 | ||
1275 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a | |
1276 | valid memory address for an instruction. The MODE argument is the | |
1277 | machine mode for the MEM expression that wants to use this address. */ | |
1278 | ||
1279 | /*-------------------------------------------------------------- | |
1280 | Valid addresses are either direct or indirect (MEM) versions | |
1281 | of the following forms: | |
1282 | constant N | |
1283 | register ,X | |
1284 | indexed N,X | |
1285 | --------------------------------------------------------------*/ | |
1286 | ||
9caea35c | 1287 | /* The range of index that is allowed by indirect addressing. */ |
385c9217 SC |
1288 | |
1289 | #define VALID_MIN_OFFSET m68hc11_min_offset | |
1290 | #define VALID_MAX_OFFSET m68hc11_max_offset | |
1291 | ||
1292 | /* The offset values which are allowed by the n,x and n,y addressing modes. | |
1293 | Take into account the size of the mode because we may have to add | |
1294 | a mode offset to access the lowest part of the data. | |
1295 | (For example, for an SImode, the last valid offset is 252.) */ | |
1296 | #define VALID_CONSTANT_OFFSET_P(X,MODE) \ | |
1297 | ((GET_CODE (X) == CONST_INT) && \ | |
1298 | ((INTVAL (X) >= VALID_MIN_OFFSET) \ | |
1299 | && ((INTVAL (X) <= VALID_MAX_OFFSET \ | |
1300 | - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) | |
1301 | ||
1302 | /* This is included to allow stack push/pop operations. Special hacks in the | |
1303 | md and m6811.c files exist to support this. */ | |
1304 | #define PUSH_POP_ADDRESS_P(X) \ | |
1305 | (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \ | |
1306 | && SP_REG_P (XEXP (X, 0))) | |
1307 | ||
9caea35c | 1308 | /* Go to ADDR if X is a valid address. */ |
385c9217 SC |
1309 | #ifndef REG_OK_STRICT |
1310 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1311 | { \ | |
1312 | if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \ | |
1313 | } | |
1314 | #else | |
1315 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1316 | { \ | |
1317 | if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \ | |
1318 | } | |
1319 | #endif | |
1320 | ||
1321 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its | |
1322 | validity for a certain class. We have two alternate definitions for each | |
1323 | of them. The usual definition accepts all pseudo regs; the other rejects | |
1324 | them unless they have been allocated suitable hard regs. The symbol | |
1325 | REG_OK_STRICT causes the latter definition to be used. | |
1326 | ||
1327 | Most source files want to accept pseudo regs in the hope that they will | |
1328 | get allocated to the class that the insn wants them to be in. Source files | |
1329 | for reload pass need to be strict. After reload, it makes no difference, | |
1330 | since pseudo regs have been eliminated by then. */ | |
1331 | ||
1332 | #ifndef REG_OK_STRICT | |
1333 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1334 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
1335 | ||
1336 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1337 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
1338 | #else | |
1339 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
1340 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
1341 | #endif | |
1342 | ||
1343 | ||
1344 | /* Try machine-dependent ways of modifying an illegitimate address | |
1345 | to be legitimate. If we find one, return the new, valid address. | |
1346 | This macro is used in only one place: `memory_address' in explow.c. | |
1347 | ||
1348 | OLDX is the address as it was before break_out_memory_refs was called. | |
1349 | In some cases it is useful to look at this to decide what needs to be done. | |
1350 | ||
1351 | MODE and WIN are passed so that this macro can use | |
1352 | GO_IF_LEGITIMATE_ADDRESS. | |
1353 | ||
1354 | It is always safe for this macro to do nothing. | |
1355 | It exists to recognize opportunities to optimize the output. */ | |
1356 | ||
1357 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1358 | { rtx operand = (X); \ | |
1359 | if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \ | |
1360 | { \ | |
1361 | (X) = operand; \ | |
1362 | GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \ | |
1363 | } \ | |
1364 | } | |
1365 | ||
1366 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1367 | has an effect that depends on the machine mode it is used for. */ | |
1368 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1369 | { \ | |
1370 | if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ | |
1371 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
1372 | goto LABEL; \ | |
1373 | } | |
1374 | ||
1375 | /* Nonzero if the constant value X is a legitimate general operand. | |
1376 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1377 | ||
1378 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1379 | ||
1380 | \f | |
1381 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1382 | ||
1383 | #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
1384 | m68hc11_notice_update_cc ((EXP), (INSN)) | |
1385 | ||
1386 | /* Compute the cost of computing a constant rtl expression RTX whose rtx-code | |
1387 | is CODE. The body of this macro is a portion of a switch statement. If | |
01beec65 SC |
1388 | the code is computed here, return it with a return statement. Otherwise, |
1389 | break from the switch. | |
1390 | ||
1391 | Constants are cheap. Moving them in registers must be avoided | |
1392 | because most instructions do not handle two register operands. */ | |
1393 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ | |
1394 | case CONST_INT: \ | |
1395 | /* Logical and arithmetic operations with a constant */ \ | |
1396 | /* operand are better because they are not supported */ \ | |
1397 | /* with two registers. */ \ | |
1398 | /* 'clr' is slow */ \ | |
1399 | if ((OUTER_CODE) == SET && (RTX) == const0_rtx) \ | |
5a62a693 SC |
1400 | /* After reload, the reload_cse pass checks the cost */ \ |
1401 | /* to change a SET into a PLUS. Make const0 cheap. */ \ | |
1402 | return 1 - reload_completed; \ | |
01beec65 SC |
1403 | else \ |
1404 | return 0; \ | |
1405 | case CONST: \ | |
1406 | case LABEL_REF: \ | |
1407 | case SYMBOL_REF: \ | |
1408 | if ((OUTER_CODE) == SET) \ | |
5a62a693 | 1409 | return 1 - reload_completed; \ |
01beec65 SC |
1410 | return 0; \ |
1411 | case CONST_DOUBLE: \ | |
385c9217 SC |
1412 | return 0; |
1413 | ||
01beec65 SC |
1414 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1415 | case ROTATE: \ | |
1416 | case ROTATERT: \ | |
1417 | case ASHIFT: \ | |
1418 | case LSHIFTRT: \ | |
1419 | case ASHIFTRT: \ | |
1420 | case MINUS: \ | |
1421 | case PLUS: \ | |
1422 | case AND: \ | |
1423 | case XOR: \ | |
1424 | case IOR: \ | |
1425 | case UDIV: \ | |
1426 | case DIV: \ | |
1427 | case MOD: \ | |
1428 | case MULT: \ | |
1429 | case NEG: \ | |
1430 | case SIGN_EXTEND: \ | |
1431 | case NOT: \ | |
1432 | case COMPARE: \ | |
1433 | case ZERO_EXTEND: \ | |
1434 | case IF_THEN_ELSE: \ | |
1435 | return m68hc11_rtx_costs (X, CODE, OUTER_CODE); | |
385c9217 SC |
1436 | |
1437 | /* An expression giving the cost of an addressing mode that contains | |
1438 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
1439 | expression and the `CONST_COSTS' values. */ | |
1440 | ||
1441 | #define ADDRESS_COST(RTX) m68hc11_address_cost (RTX) | |
1442 | ||
1443 | /* Move costs between classes of registers */ | |
cf011243 | 1444 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
385c9217 SC |
1445 | (m68hc11_register_move_cost (CLASS1, CLASS2)) |
1446 | ||
1447 | /* Move cost between register and memory. | |
1448 | - Move to a 16-bit register is reasonable, | |
1449 | - Move to a soft register can be expensive. */ | |
1450 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
1451 | m68hc11_memory_move_cost ((MODE),(CLASS),(IN)) | |
1452 | ||
1453 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1454 | is the default; other values are interpreted relative to that. | |
1455 | ||
1456 | Pretend branches are cheap because GCC generates sub-optimal code | |
1457 | for the default value. */ | |
1458 | #define BRANCH_COST 0 | |
1459 | ||
1460 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1461 | #define SLOW_BYTE_ACCESS 0 | |
1462 | ||
1463 | /* It is as good to call a constant function address as to call an address | |
1464 | kept in a register. */ | |
1465 | #define NO_FUNCTION_CSE | |
1466 | ||
1467 | /* Try a machine-dependent way of reloading an illegitimate address | |
1468 | operand. If we find one, push the reload and jump to WIN. This | |
1469 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1470 | ||
1471 | For M68HC11, we handle large displacements of a base register | |
1472 | by splitting the addend accors an addhi3 insn. | |
1473 | ||
1474 | For M68HC12, the 64K offset range is available. | |
1475 | */ | |
1476 | ||
1477 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1478 | do { \ | |
1479 | /* We must recognize output that we have already generated ourselves. */ \ | |
1480 | if (GET_CODE (X) == PLUS \ | |
1481 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1482 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1483 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1484 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1485 | { \ | |
df4ae160 | 1486 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
385c9217 SC |
1487 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1488 | OPNUM, TYPE); \ | |
1489 | goto WIN; \ | |
1490 | } \ | |
1491 | if (GET_CODE (X) == PLUS \ | |
1492 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1493 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1494 | && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \ | |
1495 | { \ | |
1496 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1497 | HOST_WIDE_INT low, high; \ | |
1498 | high = val & (~0x0FF); \ | |
1499 | low = val & 0x00FF; \ | |
1500 | if (low >= 256-15) { high += 16; low -= 16; } \ | |
1501 | /* Reload the high part into a base reg; leave the low part \ | |
1502 | in the mem directly. */ \ | |
1503 | \ | |
1504 | X = gen_rtx_PLUS (Pmode, \ | |
1505 | gen_rtx_PLUS (Pmode, XEXP (X, 0), \ | |
1506 | GEN_INT (high)), \ | |
1507 | GEN_INT (low)); \ | |
1508 | \ | |
df4ae160 | 1509 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
385c9217 SC |
1510 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1511 | OPNUM, TYPE); \ | |
1512 | goto WIN; \ | |
1513 | } \ | |
1514 | } while (0) | |
1515 | ||
1516 | \f | |
1517 | /* Defining the Output Assembler Language. */ | |
1518 | ||
1519 | /* A default list of other sections which we might be "in" at any given | |
1520 | time. For targets that use additional sections (e.g. .tdesc) you | |
1521 | should override this definition in the target-specific file which | |
1522 | includes this file. */ | |
1523 | ||
1524 | /* Output before read-only data. */ | |
1525 | #define TEXT_SECTION_ASM_OP ("\t.sect\t.text") | |
1526 | ||
1527 | /* Output before writable data. */ | |
1528 | #define DATA_SECTION_ASM_OP ("\t.sect\t.data") | |
1529 | ||
1530 | /* Output before uninitialized data. */ | |
1531 | #define BSS_SECTION_ASM_OP ("\t.sect\t.bss") | |
1532 | ||
70a5787e SC |
1533 | /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. |
1534 | ||
1535 | Same as config/elfos.h but don't mark these section SHF_WRITE since | |
1536 | there is no shared library problem. */ | |
1537 | #undef CTORS_SECTION_ASM_OP | |
1538 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
1539 | ||
1540 | #undef DTORS_SECTION_ASM_OP | |
1541 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
1542 | ||
2cc07db4 RH |
1543 | #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor |
1544 | #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor | |
70a5787e | 1545 | |
385c9217 SC |
1546 | /* This is how to begin an assembly language file. Most svr4 assemblers want |
1547 | at least a .file directive to come first, and some want to see a .version | |
1548 | directive come right after that. Here we just establish a default | |
1549 | which generates only the .file directive. If you need a .version | |
1550 | directive for any specific target, you should override this definition | |
1551 | in the target-specific file which includes this one. */ | |
1552 | ||
1553 | #undef ASM_FILE_START | |
1554 | #define ASM_FILE_START(FILE) \ | |
1555 | m68hc11_asm_file_start ((FILE), main_input_filename) | |
1556 | ||
1557 | /* Comment character */ | |
1558 | #define ASM_COMMENT_START ";" | |
1559 | ||
1560 | /* Output to assembler file text saying following lines | |
1561 | may contain character constants, extra white space, comments, etc. */ | |
1562 | #define ASM_APP_ON "; Begin inline assembler code\n#APP\n" | |
1563 | ||
1564 | /* Output to assembler file text saying following lines | |
1565 | no longer contain unusual constructs. */ | |
1566 | #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n" | |
1567 | ||
1568 | /* Output #ident as a .ident. */ | |
1569 | ||
385c9217 SC |
1570 | /* This is how to output the definition of a user-level label named NAME, |
1571 | such as the label on a static function or variable NAME. */ | |
1572 | ||
1573 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1574 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1575 | ||
1576 | ||
1577 | /* This is how to output a command to make the user-level label named NAME | |
1578 | defined for reference from other files. */ | |
1579 | ||
1580 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
016c8440 | 1581 | do { fprintf (FILE, "%s", GLOBAL_ASM_OP); \ |
385c9217 SC |
1582 | assemble_name (FILE, NAME); \ |
1583 | fputs ("\n", FILE);} while (0) | |
1584 | ||
1585 | /* output external reference */ | |
1586 | #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ | |
1587 | {fputs ("\t; extern\t", FILE); \ | |
1588 | assemble_name (FILE, NAME); \ | |
1589 | fputs ("\n", FILE);} | |
1590 | ||
1591 | ||
1592 | ||
1593 | /* Store in OUTPUT a string (made with alloca) containing | |
1594 | an assembler-name for a local static variable named NAME. | |
1595 | LABELNO is an integer which is different for each call. */ | |
1596 | ||
1597 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1598 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1599 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1600 | ||
1601 | /* How to refer to registers in assembler output. This sequence is indexed | |
1602 | by compiler's hard-register-number (see above). */ | |
1603 | #define REGISTER_NAMES \ | |
1604 | { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \ | |
1605 | "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \ | |
1606 | SOFT_REG_NAMES, "*sframe", "*ap"} | |
1607 | ||
385c9217 SC |
1608 | /* Print an instruction operand X on file FILE. CODE is the code from the |
1609 | %-spec for printing this operand. If `%z3' was used to print operand | |
1610 | 3, then CODE is 'z'. */ | |
1611 | ||
1612 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1613 | print_operand (FILE, X, CODE) | |
1614 | ||
9caea35c | 1615 | /* Print a memory operand whose address is X, on file FILE. */ |
385c9217 SC |
1616 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
1617 | print_operand_address (FILE, ADDR) | |
1618 | ||
1619 | /* This is how to output an insn to push/pop a register on the stack. | |
1620 | It need not be very fast code. | |
1621 | ||
1622 | Don't define because we don't know how to handle that with | |
1623 | the STATIC_CHAIN_REGNUM (soft register). Saving the static | |
1624 | chain must be made inside FUNCTION_PROFILER. */ | |
1625 | ||
1626 | #undef ASM_OUTPUT_REG_PUSH | |
1627 | #undef ASM_OUTPUT_REG_POP | |
1628 | ||
9caea35c | 1629 | /* This is how to output an element of a case-vector that is relative. */ |
385c9217 SC |
1630 | |
1631 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
301d03af | 1632 | asm_fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL) |
385c9217 | 1633 | |
9caea35c | 1634 | /* This is how to output an element of a case-vector that is absolute. */ |
385c9217 | 1635 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
301d03af | 1636 | asm_fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE) |
385c9217 SC |
1637 | |
1638 | /* This is how to output an assembler line that says to advance the | |
1639 | location counter to a multiple of 2**LOG bytes. */ | |
1640 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1641 | do { \ | |
1642 | if ((LOG) > 1) \ | |
016c8440 | 1643 | asm_fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \ |
385c9217 SC |
1644 | } while (0) |
1645 | ||
1646 | \f | |
1647 | /* Assembler Commands for Exception Regions. */ | |
1648 | ||
1649 | /* Default values provided by GCC should be ok. Assumming that DWARF-2 | |
9caea35c | 1650 | frame unwind info is ok for this platform. */ |
385c9217 | 1651 | |
385c9217 SC |
1652 | #undef PREFERRED_DEBUGGING_TYPE |
1653 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1654 | ||
1655 | /* The prefix for local labels. You should be able to define this as | |
1656 | an empty string, or any arbitrary string (such as ".", ".L%", etc) | |
1657 | without having to make any other changes to account for the specific | |
1658 | definition. Note it is a string literal, not interpreted by printf | |
9caea35c | 1659 | and friends. */ |
385c9217 SC |
1660 | #define LOCAL_LABEL_PREFIX "." |
1661 | ||
1662 | /* The prefix for immediate operands. */ | |
1663 | #define IMMEDIATE_PREFIX "#" | |
6e7b07a7 | 1664 | #define GLOBAL_ASM_OP "\t.globl\t" |
385c9217 SC |
1665 | |
1666 | \f | |
1667 | /* Miscellaneous Parameters. */ | |
1668 | ||
1669 | /* Define the codes that are matched by predicates in m68hc11.c. */ | |
1670 | #define PREDICATE_CODES \ | |
1671 | {"stack_register_operand", {SUBREG, REG}}, \ | |
1672 | {"d_register_operand", {SUBREG, REG}}, \ | |
1673 | {"hard_addr_reg_operand", {SUBREG, REG}}, \ | |
1674 | {"hard_reg_operand", {SUBREG, REG}}, \ | |
1675 | {"m68hc11_logical_operator", {AND, IOR, XOR}}, \ | |
1676 | {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \ | |
1677 | ASHIFT, ASHIFTRT, LSHIFTRT, \ | |
1678 | ROTATE, ROTATERT }}, \ | |
1679 | {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \ | |
1680 | {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \ | |
1681 | {"non_push_operand", {SUBREG, REG, MEM}}, \ | |
1682 | {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \ | |
1683 | {"tst_operand", {SUBREG, REG, MEM}}, \ | |
1684 | {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \ | |
1685 | CONST_INT, CONST_DOUBLE}}, | |
1686 | ||
1687 | /* Specify the machine mode that this machine uses | |
1688 | for the index in the tablejump instruction. */ | |
1689 | #define CASE_VECTOR_MODE Pmode | |
1690 | ||
385c9217 SC |
1691 | /* This flag, if defined, says the same insns that convert to a signed fixnum |
1692 | also convert validly to an unsigned one. */ | |
1693 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
1694 | ||
385c9217 SC |
1695 | /* Max number of bytes we can move from memory to memory in one |
1696 | reasonably fast instruction. */ | |
1697 | #define MOVE_MAX 2 | |
1698 | ||
1699 | /* MOVE_RATIO is the number of move instructions that is better than a | |
1700 | block move. Make this small on 6811, since the code size grows very | |
1701 | large with each move. */ | |
1702 | #define MOVE_RATIO 3 | |
1703 | ||
1704 | /* Define if shifts truncate the shift count which implies one can omit | |
1705 | a sign-extension or zero-extension of a shift count. */ | |
1706 | #define SHIFT_COUNT_TRUNCATED 1 | |
1707 | ||
1708 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1709 | is done just by pretending it is already truncated. */ | |
1710 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1711 | ||
1712 | /* Specify the machine mode that pointers have. After generation of rtl, the | |
1713 | compiler makes no further distinction between pointers and any other | |
1714 | objects of this machine mode. */ | |
1715 | #define Pmode HImode | |
1716 | ||
1717 | /* A function address in a call instruction is a byte address (for indexing | |
1718 | purposes) so give the MEM rtx a byte's mode. */ | |
1719 | #define FUNCTION_MODE QImode | |
1720 | ||
1721 | /* define SCCS_DIRECTIVE if SCCS directives should be ignored */ | |
1722 | #define SCCS_DIRECTIVE 1 | |
1723 | ||
1724 | /* Allow $ in identifiers */ | |
1725 | #define DOLLARS_IN_IDENTIFIERS 1 | |
1726 | ||
1727 | /* Machine-dependent reorg pass. | |
1728 | Specific optimizations are defined here: | |
1729 | - this pass changes the Z register into either X or Y | |
1730 | (it preserves X/Y previous values in a memory slot in page0). | |
1731 | ||
1732 | When this pass is finished, the global variable | |
1733 | 'z_replacement_completed' is set to 2. */ | |
1734 | #define MACHINE_DEPENDENT_REORG(X) m68hc11_reorg (X) | |
1735 | ||
1736 | extern int debug_m6811; | |
1737 | extern int z_replacement_completed; | |
1738 | extern int current_function_interrupt; | |
1739 | extern int current_function_trap; |