]>
Commit | Line | Data |
---|---|---|
96fcacb7 | 1 | ;; ColdFire V1, V2, V3 and V4/V4e DFA description. |
a5544970 | 2 | ;; Copyright (C) 2007-2019 Free Software Foundation, Inc. |
96fcacb7 | 3 | ;; Contributed by CodeSourcery Inc., www.codesourcery.com |
b8c96320 MK |
4 | ;; |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
748086b7 | 9 | ;; the Free Software Foundation; either version 3, or (at your option) |
b8c96320 MK |
10 | ;; any later version. |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
748086b7 JJ |
18 | ;; along with this program; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
b8c96320 | 20 | |
b8c96320 | 21 | ;; Instruction Buffer |
96fcacb7 | 22 | (define_automaton "cfv123_ib") |
826fadba MK |
23 | |
24 | ;; These pseudo units are used to model instruction buffer of ColdFire cores. | |
25 | ;; Instruction of size N can be issued only when cf_ib_wN is available. | |
96fcacb7 | 26 | (define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cfv123_ib") |
826fadba MK |
27 | |
28 | ;; Instruction occupies 1 word in the instruction buffer. | |
29 | (define_reservation "cf_ib1" "cf_ib_w1") | |
30 | ;; Instruction occupies 2 words in the instruction buffer. | |
31 | (define_reservation "cf_ib2" "cf_ib_w1+cf_ib_w2") | |
32 | ;; Instruction occupies 3 words in the instruction buffer. | |
33 | (define_reservation "cf_ib3" "cf_ib_w1+cf_ib_w2+cf_ib_w3") | |
34 | ||
35 | ;; This reservation is used at the start of each cycle to setup the maximal | |
36 | ;; length of instruction that can be issued on current cycle. | |
37 | ;; E.g., when this reservation is applied for the first time, cf_ib_w3 | |
38 | ;; resource is marked busy, thus filtering out all 3-word insns. | |
39 | ;; | |
40 | ;; This reservation requires deterministic automaton. | |
41 | ;; | |
42 | ;; At each cycle, given that memory bus is available (i.e., there is no | |
43 | ;; pending memory operation), instruction fetch pipeline (IFP) prefetches | |
44 | ;; two instruction words into instruction buffer (IB). | |
45 | (define_insn_reservation "cf_ib1" 0 | |
46 | (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
b8c96320 | 47 | (eq_attr "type" "ib")) |
826fadba | 48 | "cf_ib_w3|cf_ib_w2|cf_ib_w1") |
b8c96320 MK |
49 | |
50 | ;; Operand Execution Pipeline | |
96fcacb7 | 51 | (define_automaton "cfv123_oep") |
b8c96320 | 52 | |
96fcacb7 | 53 | (define_cpu_unit "cf_dsoc,cf_agex" "cfv123_oep") |
b8c96320 | 54 | |
073a8998 | 55 | ;; A memory unit that is referred to as 'certain hardware resources' in |
b8c96320 MK |
56 | ;; ColdFire reference manuals. This unit remains occupied for two cycles |
57 | ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between | |
58 | ;; two consecutive stores. | |
96fcacb7 | 59 | (define_automaton "cfv123_chr") |
b8c96320 | 60 | |
96fcacb7 | 61 | (define_cpu_unit "cf_chr" "cfv123_chr") |
b8c96320 MK |
62 | |
63 | ;; Memory bus | |
96fcacb7 | 64 | (define_automaton "cfv123_mem") |
b8c96320 MK |
65 | |
66 | ;; When memory bus is subscribed, that implies that instruction buffer won't | |
826fadba | 67 | ;; get its portion this cycle. To model that we query if cf_mem unit is |
b8c96320 MK |
68 | ;; subscribed and adjust number of prefetched instruction words accordingly. |
69 | ;; | |
96fcacb7 | 70 | (define_query_cpu_unit "cf_mem1, cf_mem2" "cfv123_mem") |
826fadba MK |
71 | |
72 | (define_reservation "cf_mem" "cf_mem1+cf_mem2") | |
b8c96320 | 73 | |
96fcacb7 MK |
74 | (define_automaton "cf_mac") |
75 | ||
76 | (define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4" | |
77 | "cf_mac") | |
78 | ||
79 | (define_automaton "cfv123_guess") | |
80 | ||
81 | (define_query_cpu_unit "cfv123_guess" "cfv123_guess") | |
82 | ||
b8c96320 MK |
83 | ;; Register to register move. |
84 | ;; Takes 1 cycle. | |
826fadba MK |
85 | (define_reservation "cfv123_alu_00" |
86 | "cf_dsoc,cf_agex") | |
b8c96320 MK |
87 | |
88 | ;; Load from a memory location. | |
89 | ;; Takes 3 cycles. | |
826fadba MK |
90 | (define_reservation "cfv12_alu_10" |
91 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex") | |
b8c96320 | 92 | ;; Takes 2 cycles. |
826fadba MK |
93 | (define_reservation "cfv12_omove_10" |
94 | "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex") | |
95 | ;; Takes 4 cycles. | |
96 | (define_reservation "cfv3_alu_10" | |
97 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex") | |
98 | ;; Takes 3 cycles. | |
99 | (define_reservation "cfv3_omove_10" | |
100 | "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex") | |
b8c96320 MK |
101 | |
102 | ;; Load from an indexed location. | |
103 | ;; Takes 4 cycles. | |
826fadba MK |
104 | (define_reservation "cfv12_alu_i0" |
105 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex") | |
b8c96320 | 106 | ;; Takes 3 cycles. |
826fadba MK |
107 | (define_reservation "cfv12_omove_i0" |
108 | "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex") | |
109 | ;; Takes 5 cycles. | |
110 | (define_reservation "cfv3_alu_i0" | |
111 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex") | |
112 | ;; Takes 4 cycles. | |
113 | (define_reservation "cfv3_omove_i0" | |
114 | "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex") | |
b8c96320 MK |
115 | |
116 | ;; Store to a memory location. | |
117 | ;; Takes 1 cycle. | |
826fadba MK |
118 | (define_reservation "cfv12_alu_01" |
119 | "cf_dsoc+cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
120 | ;; Takes 1 cycle. | |
121 | (define_reservation "cfv3_alu_01" | |
122 | "cf_dsoc+cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
b8c96320 MK |
123 | |
124 | ;; Store to an indexed location. | |
826fadba MK |
125 | ;; Takes 2 cycles. |
126 | (define_reservation "cfv12_alu_0i" | |
127 | "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
128 | ;; Takes 2 cycles. | |
129 | (define_reservation "cfv3_alu_0i" | |
130 | "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
b8c96320 MK |
131 | |
132 | ;; Load from a memory location and store to a memory location. | |
133 | ;; Takes 3 cycles | |
826fadba MK |
134 | (define_reservation "cfv12_alu_11" |
135 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
b8c96320 | 136 | ;; Takes 2 cycles. |
826fadba MK |
137 | (define_reservation "cfv12_omove_11" |
138 | "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
139 | ;; Takes 4 cycles | |
140 | (define_reservation "cfv3_alu_11" | |
141 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
142 | ;; Takes 3 cycles. | |
143 | (define_reservation "cfv3_omove_11" | |
144 | "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
b8c96320 MK |
145 | |
146 | ;; Load from an indexed location and store to a memory location. | |
147 | ;; Takes 4 cycles. | |
826fadba MK |
148 | (define_reservation "cfv12_alu_i1" |
149 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
b8c96320 | 150 | ;; Takes 3 cycles. |
826fadba MK |
151 | (define_reservation "cfv12_omove_i1" |
152 | "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
153 | ;; Takes 5 cycles. | |
154 | (define_reservation "cfv3_alu_i1" | |
155 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
156 | ;; Takes 4 cycles. | |
157 | (define_reservation "cfv3_omove_i1" | |
158 | "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
b8c96320 MK |
159 | |
160 | ;; Load from a memory location and store to an indexed location. | |
161 | ;; Takes 4 cycles. | |
826fadba MK |
162 | (define_reservation "cfv12_alu_1i" |
163 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
b8c96320 | 164 | ;; Takes 3 cycles. |
826fadba MK |
165 | (define_reservation "cfv12_omove_1i" |
166 | "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
167 | ;; Takes 5 cycles. | |
168 | (define_reservation "cfv3_alu_1i" | |
169 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
170 | ;; Takes 4 cycles. | |
171 | (define_reservation "cfv3_omove_1i" | |
172 | "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
b8c96320 MK |
173 | |
174 | ;; Lea operation for a memory location. | |
175 | ;; Takes 1 cycle. | |
826fadba MK |
176 | (define_reservation "cfv123_lea_10" |
177 | "cf_dsoc,cf_agex") | |
b8c96320 MK |
178 | |
179 | ;; Lea operation for an indexed location. | |
180 | ;; Takes 2 cycles. | |
826fadba MK |
181 | (define_reservation "cfv123_lea_i0" |
182 | "cf_dsoc,cf_agex,cf_agex") | |
b8c96320 MK |
183 | |
184 | ;; Pea operation for a memory location. | |
826fadba MK |
185 | ;; Takes 2 cycles. |
186 | (define_reservation "cfv12_pea_11" | |
187 | "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
188 | ;; Takes 2 cycles. | |
189 | (define_reservation "cfv3_pea_11" | |
190 | "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
b8c96320 MK |
191 | |
192 | ;; Pea operation for an indexed location. | |
193 | ;; Takes 3 cycles. | |
826fadba MK |
194 | (define_reservation "cfv12_pea_i1" |
195 | "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr") | |
196 | ;; Takes 3 cycles. | |
197 | (define_reservation "cfv3_pea_i1" | |
198 | "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr") | |
199 | ||
200 | ;; Long multiplication with no mac. | |
201 | ;; Takes 9-18 cycles. | |
202 | (define_reservation "cfv123_mul_l_00" | |
203 | "cf_dsoc,(cf_agex+cf_dsoc)*17,cf_agex") | |
204 | ||
205 | ;; Word multiplication with no mac. | |
206 | ;; Takes 9 cycles. | |
207 | (define_reservation "cfv123_mul_w_00" | |
208 | "cf_dsoc,(cf_agex+cf_dsoc)*8,cf_agex") | |
209 | ||
210 | ;; Long multiplication with no mac. | |
211 | ;; Takes 11-20 cycles. | |
212 | (define_reservation "cfv12_mul_l_10" | |
213 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*17,cf_agex") | |
214 | ;; Takes 12-21 cycles. | |
215 | (define_reservation "cfv3_mul_l_10" | |
216 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*17,cf_agex") | |
217 | ||
218 | ;; Word multiplication with no mac. | |
219 | ;; Takes 11 cycles. | |
220 | (define_reservation "cfv12_mul_w_10" | |
221 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex") | |
222 | ;; Takes 12 cycles. | |
223 | (define_reservation "cfv3_mul_w_10" | |
224 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex") | |
225 | ||
226 | ;; Word multiplication with no mac. | |
227 | ;; Takes 12 cycles. | |
228 | (define_reservation "cfv12_mul_w_i0" | |
229 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex") | |
230 | ;; Takes 13 cycles. | |
231 | (define_reservation "cfv3_mul_w_i0" | |
232 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex") | |
233 | ||
826fadba MK |
234 | ;; Long multiplication with mac. |
235 | ;; Takes 5 cycles. | |
236 | (define_reservation "cfv123_mac_l_00" | |
237 | "cf_dsoc,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
238 | ||
239 | ;; Word multiplication with mac. | |
240 | ;; Takes 3 cycles. | |
241 | (define_reservation "cfv123_mac_w_00" | |
242 | "cf_dsoc,cf_agex,cf_mac1,cf_mac2") | |
b8c96320 | 243 | |
826fadba MK |
244 | ;; Long multiplication with mac. |
245 | ;; Takes 7 cycles. | |
246 | (define_reservation "cfv12_mac_l_10" | |
247 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
248 | ;; Takes 8 cycles. | |
249 | (define_reservation "cfv3_mac_l_10" | |
250 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
251 | ||
252 | ;; Word multiplication with mac. | |
253 | ;; Takes 5 cycles. | |
254 | (define_reservation "cfv12_mac_w_10" | |
255 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2") | |
256 | ;; Takes 6 cycles. | |
257 | (define_reservation "cfv3_mac_w_10" | |
258 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2") | |
b8c96320 | 259 | |
826fadba MK |
260 | ;; Word multiplication with mac. |
261 | ;; Takes 6 cycles. | |
262 | (define_reservation "cfv12_mac_w_i0" | |
263 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2") | |
264 | ;; Takes 7 cycles. | |
265 | (define_reservation "cfv3_mac_w_i0" | |
266 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2") | |
b8c96320 | 267 | |
826fadba | 268 | ;; Multiplication with emac. |
b8c96320 | 269 | ;; Takes 4 cycles. |
826fadba MK |
270 | (define_reservation "cfv123_emac_00" |
271 | "cf_dsoc,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
b8c96320 | 272 | |
826fadba | 273 | ;; Multiplication with emac. |
b8c96320 | 274 | ;; Takes 6 cycles. |
826fadba MK |
275 | (define_reservation "cfv12_emac_10" |
276 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
277 | ;; Takes 7 cycles. | |
278 | (define_reservation "cfv3_emac_10" | |
279 | "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
b8c96320 | 280 | |
826fadba | 281 | ;; Word multiplication with emac. |
b8c96320 | 282 | ;; Takes 7 cycles. |
826fadba MK |
283 | (define_reservation "cfv12_emac_w_i0" |
284 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
285 | ;; Takes 8 cycles. | |
286 | (define_reservation "cfv3_emac_w_i0" | |
287 | "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4") | |
288 | ||
289 | ;; Return instruction. | |
290 | ;; ??? As return reads target address from stack, use a mem-read reservation | |
291 | ;; ??? for it. | |
292 | ;; ??? It's not clear what the core does during these 5 cycles. | |
293 | ;; ??? Luckily, we don't care that much about an insn that won't be moved. | |
294 | ;; Takes 5 cycles. | |
295 | (define_reservation "cfv12_rts" "cfv12_alu_10") | |
296 | ;; Takes 8 cycles. | |
297 | (define_reservation "cfv3_rts" "cfv3_alu_10") | |
298 | ||
299 | ;; Call instruction. | |
300 | ;; ??? It's not clear what reservation is best to use for calls. | |
301 | ;; ??? For now we use mem-write + return reservations to reflect the fact of | |
302 | ;; ??? pushing and poping return address to and from the stack. | |
303 | ;; Takes 3 cycles. | |
304 | (define_reservation "cfv12_call" "cfv12_alu_01,cfv12_rts") | |
305 | ;; Takes 1/5 cycles. | |
306 | (define_reservation "cfv3_call" "cfv3_alu_01,cfv3_rts") | |
307 | ||
308 | ;; Conditional branch instruction. | |
309 | ;; ??? Branch reservations are unclear to me so far. Luckily, we don't care | |
310 | ;; ??? that much about branches. | |
311 | ;; Takes 2 cycles. | |
312 | (define_reservation "cfv12_bcc" "cfv123_alu_00") | |
313 | ;; Takes 1 cycles. | |
314 | (define_reservation "cfv3_bcc" "cfv123_alu_00") | |
315 | ||
316 | ;; Unconditional branch instruciton. | |
317 | ;; Takes 2 cycles. | |
318 | (define_reservation "cfv12_bra" "cfv12_alu_01") | |
319 | ;; Takes 1 cycles. | |
320 | (define_reservation "cfv3_bra" "cfv3_alu_01") | |
321 | ||
322 | ;; Computed jump instruction. | |
323 | ;; Takes 3 cycles. | |
324 | (define_reservation "cfv12_jmp" | |
325 | "(cf_dsoc+cf_agex)*3") | |
326 | ;; Takes 5 cycles. | |
327 | (define_reservation "cfv3_jmp" | |
328 | "(cf_dsoc+cf_agex)*5") | |
b8c96320 MK |
329 | |
330 | ;; Instruction reservations. | |
331 | ||
332 | ;; Below reservations are simple derivation from the above reservations. | |
333 | ;; Each reservation from the above expands into 3 reservations below - one | |
334 | ;; for each instruction size. | |
335 | ;; A number in the end of reservation's name is the size of the instruction. | |
336 | ||
826fadba MK |
337 | (define_insn_reservation "cfv123_alu_00_1" 1 |
338 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
339 | (eq_attr "type" " |
340 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
341 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
342 | move_l,tst_l")) | |
343 | (eq_attr "op_mem" "00")) | |
344 | (eq_attr "size" "1")) | |
826fadba | 345 | "cf_ib1+cfv123_alu_00") |
b8c96320 | 346 | |
826fadba MK |
347 | (define_insn_reservation "cfv123_alu_00_2" 1 |
348 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
349 | (eq_attr "type" " |
350 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
351 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
352 | move_l,tst_l")) | |
353 | (eq_attr "op_mem" "00")) | |
354 | (eq_attr "size" "2")) | |
826fadba | 355 | "cf_ib2+cfv123_alu_00") |
b8c96320 | 356 | |
826fadba MK |
357 | (define_insn_reservation "cfv123_alu_00_3" 1 |
358 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
359 | (eq_attr "type" " |
360 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
361 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
362 | move_l,tst_l")) | |
363 | (eq_attr "op_mem" "00")) | |
364 | (eq_attr "size" "3")) | |
826fadba MK |
365 | "cf_ib3+cfv123_alu_00") |
366 | ||
96fcacb7 MK |
367 | (define_insn_reservation "cfv1_alu_10_1" 3 |
368 | (and (and (and (eq_attr "cpu" "cfv1") | |
369 | (eq_attr "type" " | |
370 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
371 | (eq_attr "op_mem" "10")) | |
372 | (eq_attr "size" "1")) | |
826fadba MK |
373 | "cf_ib1+cfv12_alu_10") |
374 | ||
96fcacb7 MK |
375 | (define_insn_reservation "cfv1_alu_10_2" 3 |
376 | (and (and (and (eq_attr "cpu" "cfv1") | |
377 | (eq_attr "type" " | |
378 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
379 | (eq_attr "op_mem" "10")) | |
380 | (eq_attr "size" "2")) | |
826fadba | 381 | "cf_ib2+cfv12_alu_10") |
b8c96320 | 382 | |
96fcacb7 MK |
383 | (define_insn_reservation "cfv1_alu_10_3" 3 |
384 | (and (and (and (eq_attr "cpu" "cfv1") | |
385 | (eq_attr "type" " | |
386 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
387 | (eq_attr "op_mem" "10")) | |
388 | (eq_attr "size" "3")) | |
826fadba MK |
389 | "cf_ib3+cfv12_alu_10") |
390 | ||
96fcacb7 MK |
391 | (define_insn_reservation "cfv1_omove_10_1" 2 |
392 | (and (and (and (eq_attr "cpu" "cfv1") | |
393 | (eq_attr "type" " | |
394 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
395 | move_l,tst_l")) | |
396 | (eq_attr "op_mem" "10")) | |
397 | (eq_attr "size" "1")) | |
826fadba | 398 | "cf_ib1+cfv12_omove_10") |
b8c96320 | 399 | |
96fcacb7 MK |
400 | (define_insn_reservation "cfv1_omove_10_2" 2 |
401 | (and (and (and (eq_attr "cpu" "cfv1") | |
402 | (eq_attr "type" " | |
403 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
404 | move_l,tst_l")) | |
405 | (eq_attr "op_mem" "10")) | |
406 | (eq_attr "size" "2")) | |
826fadba | 407 | "cf_ib2+cfv12_omove_10") |
b8c96320 | 408 | |
96fcacb7 MK |
409 | (define_insn_reservation "cfv1_omove_10_3" 2 |
410 | (and (and (and (eq_attr "cpu" "cfv1") | |
411 | (eq_attr "type" " | |
412 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
413 | move_l,tst_l")) | |
414 | (eq_attr "op_mem" "10")) | |
415 | (eq_attr "size" "3")) | |
416 | "cf_ib3+cfv12_omove_10") | |
417 | ||
418 | (define_insn_reservation "cfv2_alu_10_1" 3 | |
419 | (and (and (and (eq_attr "cpu" "cfv2") | |
420 | (eq_attr "type" " | |
421 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
422 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
423 | (eq_attr "op_mem" "10")) | |
424 | (eq_attr "size" "1")) | |
425 | "cf_ib1+cfv12_alu_10") | |
426 | ||
427 | (define_insn_reservation "cfv2_alu_10_2" 3 | |
428 | (and (and (and (eq_attr "cpu" "cfv2") | |
429 | (eq_attr "type" " | |
430 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
431 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
432 | (eq_attr "op_mem" "10")) | |
433 | (eq_attr "size" "2")) | |
434 | "cf_ib2+cfv12_alu_10") | |
435 | ||
436 | (define_insn_reservation "cfv2_alu_10_3" 3 | |
437 | (and (and (and (eq_attr "cpu" "cfv2") | |
438 | (eq_attr "type" " | |
439 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
440 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
441 | (eq_attr "op_mem" "10")) | |
442 | (eq_attr "size" "3")) | |
443 | "cf_ib3+cfv12_alu_10") | |
444 | ||
445 | (define_insn_reservation "cfv2_omove_10_1" 2 | |
446 | (and (and (and (eq_attr "cpu" "cfv2") | |
447 | (eq_attr "type" " | |
448 | move_l,tst_l")) | |
449 | (eq_attr "op_mem" "10")) | |
450 | (eq_attr "size" "1")) | |
451 | "cf_ib1+cfv12_omove_10") | |
452 | ||
453 | (define_insn_reservation "cfv2_omove_10_2" 2 | |
454 | (and (and (and (eq_attr "cpu" "cfv2") | |
455 | (eq_attr "type" " | |
456 | move_l,tst_l")) | |
457 | (eq_attr "op_mem" "10")) | |
458 | (eq_attr "size" "2")) | |
459 | "cf_ib2+cfv12_omove_10") | |
460 | ||
461 | (define_insn_reservation "cfv2_omove_10_3" 2 | |
462 | (and (and (and (eq_attr "cpu" "cfv2") | |
463 | (eq_attr "type" " | |
464 | move_l,tst_l")) | |
465 | (eq_attr "op_mem" "10")) | |
466 | (eq_attr "size" "3")) | |
826fadba | 467 | "cf_ib3+cfv12_omove_10") |
b8c96320 | 468 | |
826fadba MK |
469 | (define_insn_reservation "cfv3_alu_10_1" 4 |
470 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
471 | (eq_attr "type" " |
472 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
473 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
474 | (eq_attr "op_mem" "10")) | |
475 | (eq_attr "size" "1")) | |
826fadba | 476 | "cf_ib1+cfv3_alu_10") |
b8c96320 | 477 | |
826fadba MK |
478 | (define_insn_reservation "cfv3_alu_10_2" 4 |
479 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
480 | (eq_attr "type" " |
481 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
482 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
483 | (eq_attr "op_mem" "10")) | |
484 | (eq_attr "size" "2")) | |
826fadba | 485 | "cf_ib2+cfv3_alu_10") |
b8c96320 | 486 | |
826fadba MK |
487 | (define_insn_reservation "cfv3_alu_10_3" 4 |
488 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
489 | (eq_attr "type" " |
490 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
491 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
492 | (eq_attr "op_mem" "10")) | |
493 | (eq_attr "size" "3")) | |
826fadba MK |
494 | "cf_ib3+cfv3_alu_10") |
495 | ||
496 | (define_insn_reservation "cfv3_omove_10_1" 3 | |
497 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
498 | (eq_attr "type" " |
499 | move_l,tst_l")) | |
500 | (eq_attr "op_mem" "10")) | |
501 | (eq_attr "size" "1")) | |
826fadba MK |
502 | "cf_ib1+cfv3_omove_10") |
503 | ||
504 | (define_insn_reservation "cfv3_omove_10_2" 3 | |
505 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
506 | (eq_attr "type" " |
507 | move_l,tst_l")) | |
508 | (eq_attr "op_mem" "10")) | |
509 | (eq_attr "size" "2")) | |
826fadba MK |
510 | "cf_ib2+cfv3_omove_10") |
511 | ||
512 | (define_insn_reservation "cfv3_omove_10_3" 3 | |
513 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
514 | (eq_attr "type" " |
515 | move_l,tst_l")) | |
516 | (eq_attr "op_mem" "10")) | |
517 | (eq_attr "size" "3")) | |
826fadba MK |
518 | "cf_ib3+cfv3_omove_10") |
519 | ||
96fcacb7 MK |
520 | (define_insn_reservation "cfv1_alu_i0_2" 4 |
521 | (and (and (and (eq_attr "cpu" "cfv1") | |
522 | (eq_attr "type" " | |
523 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
524 | (eq_attr "op_mem" "i0")) | |
525 | (eq_attr "size" "1,2")) | |
826fadba MK |
526 | "cf_ib2+cfv12_alu_i0") |
527 | ||
96fcacb7 MK |
528 | (define_insn_reservation "cfv1_alu_i0_3" 4 |
529 | (and (and (and (eq_attr "cpu" "cfv1") | |
530 | (eq_attr "type" " | |
531 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
532 | (eq_attr "op_mem" "i0")) | |
533 | (eq_attr "size" "3")) | |
826fadba | 534 | "cf_ib3+cfv12_alu_i0") |
b8c96320 | 535 | |
96fcacb7 MK |
536 | (define_insn_reservation "cfv1_omove_i0_2" 3 |
537 | (and (and (and (eq_attr "cpu" "cfv1") | |
538 | (eq_attr "type" " | |
539 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
540 | move_l,tst_l")) | |
541 | (eq_attr "op_mem" "i0")) | |
542 | (eq_attr "size" "1,2")) | |
826fadba | 543 | "cf_ib2+cfv12_omove_i0") |
b8c96320 | 544 | |
96fcacb7 MK |
545 | (define_insn_reservation "cfv1_omove_i0_3" 3 |
546 | (and (and (and (eq_attr "cpu" "cfv1") | |
547 | (eq_attr "type" " | |
548 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
549 | move_l,tst_l")) | |
550 | (eq_attr "op_mem" "i0")) | |
551 | (eq_attr "size" "3")) | |
552 | "cf_ib3+cfv12_omove_i0") | |
553 | ||
554 | (define_insn_reservation "cfv2_alu_i0_2" 4 | |
555 | (and (and (and (eq_attr "cpu" "cfv2") | |
556 | (eq_attr "type" " | |
557 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
558 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
559 | (eq_attr "op_mem" "i0")) | |
560 | (eq_attr "size" "1,2")) | |
561 | "cf_ib2+cfv12_alu_i0") | |
562 | ||
563 | (define_insn_reservation "cfv2_alu_i0_3" 4 | |
564 | (and (and (and (eq_attr "cpu" "cfv2") | |
565 | (eq_attr "type" " | |
566 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
567 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
568 | (eq_attr "op_mem" "i0")) | |
569 | (eq_attr "size" "3")) | |
570 | "cf_ib3+cfv12_alu_i0") | |
571 | ||
572 | (define_insn_reservation "cfv2_omove_i0_2" 3 | |
573 | (and (and (and (eq_attr "cpu" "cfv2") | |
574 | (eq_attr "type" " | |
575 | move_l,tst_l")) | |
576 | (eq_attr "op_mem" "i0")) | |
577 | (eq_attr "size" "1,2")) | |
578 | "cf_ib2+cfv12_omove_i0") | |
579 | ||
580 | (define_insn_reservation "cfv2_omove_i0_3" 3 | |
581 | (and (and (and (eq_attr "cpu" "cfv2") | |
582 | (eq_attr "type" " | |
583 | move_l,tst_l")) | |
584 | (eq_attr "op_mem" "i0")) | |
585 | (eq_attr "size" "3")) | |
826fadba | 586 | "cf_ib3+cfv12_omove_i0") |
b8c96320 | 587 | |
826fadba MK |
588 | (define_insn_reservation "cfv3_alu_i0_2" 5 |
589 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
590 | (eq_attr "type" " |
591 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
592 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
593 | (eq_attr "op_mem" "i0")) | |
594 | (eq_attr "size" "1,2")) | |
826fadba | 595 | "cf_ib2+cfv3_alu_i0") |
b8c96320 | 596 | |
826fadba MK |
597 | (define_insn_reservation "cfv3_alu_i0_3" 5 |
598 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
599 | (eq_attr "type" " |
600 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
601 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
602 | (eq_attr "op_mem" "i0")) | |
603 | (eq_attr "size" "3")) | |
826fadba MK |
604 | "cf_ib3+cfv3_alu_i0") |
605 | ||
606 | (define_insn_reservation "cfv3_omove_i0_2" 4 | |
607 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
608 | (eq_attr "type" " |
609 | move_l,tst_l")) | |
610 | (eq_attr "op_mem" "i0")) | |
611 | (eq_attr "size" "1,2")) | |
826fadba | 612 | "cf_ib2+cfv3_omove_i0") |
b8c96320 | 613 | |
826fadba MK |
614 | (define_insn_reservation "cfv3_omove_i0_3" 4 |
615 | (and (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
616 | (eq_attr "type" " |
617 | move_l,tst_l")) | |
618 | (eq_attr "op_mem" "i0")) | |
619 | (eq_attr "size" "3")) | |
826fadba MK |
620 | "cf_ib3+cfv3_omove_i0") |
621 | ||
96fcacb7 | 622 | (define_insn_reservation "cfv12_alu_01_1" 1 |
826fadba | 623 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
624 | (eq_attr "type" " |
625 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
626 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
627 | move_l,tst_l")) | |
628 | (eq_attr "op_mem" "01")) | |
629 | (eq_attr "size" "1")) | |
826fadba | 630 | "cf_ib1+cfv12_alu_01") |
b8c96320 | 631 | |
96fcacb7 | 632 | (define_insn_reservation "cfv12_alu_01_2" 1 |
826fadba | 633 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
634 | (eq_attr "type" " |
635 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
636 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
637 | move_l,tst_l")) | |
638 | (eq_attr "op_mem" "01")) | |
639 | (eq_attr "size" "2")) | |
826fadba | 640 | "cf_ib2+cfv12_alu_01") |
b8c96320 | 641 | |
96fcacb7 | 642 | (define_insn_reservation "cfv12_alu_01_3" 1 |
826fadba | 643 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
644 | (eq_attr "type" " |
645 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
646 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
647 | move_l,tst_l")) | |
648 | (eq_attr "op_mem" "01")) | |
649 | (eq_attr "size" "3")) | |
826fadba MK |
650 | "cf_ib3+cfv12_alu_01") |
651 | ||
96fcacb7 | 652 | (define_insn_reservation "cfv3_alu_01_1" 1 |
826fadba | 653 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
654 | (eq_attr "type" " |
655 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
656 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
657 | move_l,tst_l")) | |
658 | (eq_attr "op_mem" "01")) | |
659 | (eq_attr "size" "1")) | |
826fadba MK |
660 | "cf_ib1+cfv3_alu_01") |
661 | ||
96fcacb7 | 662 | (define_insn_reservation "cfv3_alu_01_2" 1 |
826fadba | 663 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
664 | (eq_attr "type" " |
665 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
666 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
667 | move_l,tst_l")) | |
668 | (eq_attr "op_mem" "01")) | |
669 | (eq_attr "size" "2")) | |
826fadba MK |
670 | "cf_ib2+cfv3_alu_01") |
671 | ||
96fcacb7 | 672 | (define_insn_reservation "cfv3_alu_01_3" 1 |
826fadba | 673 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
674 | (eq_attr "type" " |
675 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
676 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
677 | move_l,tst_l")) | |
678 | (eq_attr "op_mem" "01")) | |
679 | (eq_attr "size" "3")) | |
826fadba MK |
680 | "cf_ib3+cfv3_alu_01") |
681 | ||
96fcacb7 | 682 | (define_insn_reservation "cfv12_alu_0i_2" 2 |
826fadba | 683 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
684 | (eq_attr "type" " |
685 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
686 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
687 | move_l,tst_l")) | |
688 | (eq_attr "op_mem" "0i")) | |
689 | (eq_attr "size" "1,2")) | |
826fadba MK |
690 | "cf_ib2+cfv12_alu_0i") |
691 | ||
96fcacb7 | 692 | (define_insn_reservation "cfv12_alu_0i_3" 2 |
826fadba | 693 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
694 | (eq_attr "type" " |
695 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
696 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
697 | move_l,tst_l")) | |
698 | (eq_attr "op_mem" "0i")) | |
699 | (eq_attr "size" "3")) | |
826fadba | 700 | "cf_ib3+cfv12_alu_0i") |
b8c96320 | 701 | |
96fcacb7 | 702 | (define_insn_reservation "cfv3_alu_0i_2" 2 |
826fadba | 703 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
704 | (eq_attr "type" " |
705 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
706 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
707 | move_l,tst_l")) | |
708 | (eq_attr "op_mem" "0i")) | |
709 | (eq_attr "size" "1,2")) | |
826fadba | 710 | "cf_ib2+cfv3_alu_0i") |
b8c96320 | 711 | |
96fcacb7 | 712 | (define_insn_reservation "cfv3_alu_0i_3" 2 |
826fadba | 713 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
714 | (eq_attr "type" " |
715 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
716 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
717 | move_l,tst_l")) | |
718 | (eq_attr "op_mem" "0i")) | |
719 | (eq_attr "size" "3")) | |
826fadba | 720 | "cf_ib3+cfv3_alu_0i") |
b8c96320 | 721 | |
96fcacb7 MK |
722 | (define_insn_reservation "cfv1_alu_11_1" 1 |
723 | (and (and (and (eq_attr "cpu" "cfv1") | |
724 | (eq_attr "type" " | |
725 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
726 | (eq_attr "op_mem" "11")) | |
727 | (eq_attr "size" "1")) | |
826fadba | 728 | "cf_ib1+cfv12_alu_11") |
b8c96320 | 729 | |
96fcacb7 MK |
730 | (define_insn_reservation "cfv1_alu_11_2" 1 |
731 | (and (and (and (eq_attr "cpu" "cfv1") | |
732 | (eq_attr "type" " | |
733 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
734 | (eq_attr "op_mem" "11")) | |
735 | (eq_attr "size" "2")) | |
826fadba | 736 | "cf_ib2+cfv12_alu_11") |
b8c96320 | 737 | |
96fcacb7 MK |
738 | (define_insn_reservation "cfv1_alu_11_3" 1 |
739 | (and (and (and (eq_attr "cpu" "cfv1") | |
740 | (eq_attr "type" " | |
741 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
742 | (eq_attr "op_mem" "11")) | |
743 | (eq_attr "size" "3")) | |
826fadba | 744 | "cf_ib3+cfv12_alu_11") |
b8c96320 | 745 | |
96fcacb7 MK |
746 | (define_insn_reservation "cfv1_omove_11_1" 1 |
747 | (and (and (and (eq_attr "cpu" "cfv1") | |
748 | (eq_attr "type" " | |
749 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
750 | move_l,tst_l")) | |
751 | (eq_attr "op_mem" "11")) | |
752 | (eq_attr "size" "1")) | |
826fadba | 753 | "cf_ib1+cfv12_omove_11") |
b8c96320 | 754 | |
96fcacb7 MK |
755 | (define_insn_reservation "cfv1_omove_11_2" 1 |
756 | (and (and (and (eq_attr "cpu" "cfv1") | |
757 | (eq_attr "type" " | |
758 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
759 | move_l,tst_l")) | |
760 | (eq_attr "op_mem" "11")) | |
761 | (eq_attr "size" "2")) | |
826fadba | 762 | "cf_ib2+cfv12_omove_11") |
b8c96320 | 763 | |
96fcacb7 MK |
764 | (define_insn_reservation "cfv1_omove_11_3" 1 |
765 | (and (and (and (eq_attr "cpu" "cfv1") | |
766 | (eq_attr "type" " | |
767 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
768 | move_l,tst_l")) | |
769 | (eq_attr "op_mem" "11")) | |
770 | (eq_attr "size" "3")) | |
771 | "cf_ib3+cfv12_omove_11") | |
772 | ||
773 | (define_insn_reservation "cfv2_alu_11_1" 1 | |
774 | (and (and (and (eq_attr "cpu" "cfv2") | |
775 | (eq_attr "type" " | |
776 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
777 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
778 | (eq_attr "op_mem" "11")) | |
779 | (eq_attr "size" "1")) | |
780 | "cf_ib1+cfv12_alu_11") | |
781 | ||
782 | (define_insn_reservation "cfv2_alu_11_2" 1 | |
783 | (and (and (and (eq_attr "cpu" "cfv2") | |
784 | (eq_attr "type" " | |
785 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
786 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
787 | (eq_attr "op_mem" "11")) | |
788 | (eq_attr "size" "2")) | |
789 | "cf_ib2+cfv12_alu_11") | |
790 | ||
791 | (define_insn_reservation "cfv2_alu_11_3" 1 | |
792 | (and (and (and (eq_attr "cpu" "cfv2") | |
793 | (eq_attr "type" " | |
794 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
795 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
796 | (eq_attr "op_mem" "11")) | |
797 | (eq_attr "size" "3")) | |
798 | "cf_ib3+cfv12_alu_11") | |
799 | ||
800 | (define_insn_reservation "cfv2_omove_11_1" 1 | |
801 | (and (and (and (eq_attr "cpu" "cfv2") | |
802 | (eq_attr "type" " | |
803 | move_l,tst_l")) | |
804 | (eq_attr "op_mem" "11")) | |
805 | (eq_attr "size" "1")) | |
806 | "cf_ib1+cfv12_omove_11") | |
807 | ||
808 | (define_insn_reservation "cfv2_omove_11_2" 1 | |
809 | (and (and (and (eq_attr "cpu" "cfv2") | |
810 | (eq_attr "type" " | |
811 | move_l,tst_l")) | |
812 | (eq_attr "op_mem" "11")) | |
813 | (eq_attr "size" "2")) | |
814 | "cf_ib2+cfv12_omove_11") | |
815 | ||
816 | (define_insn_reservation "cfv2_omove_11_3" 1 | |
817 | (and (and (and (eq_attr "cpu" "cfv2") | |
818 | (eq_attr "type" " | |
819 | move_l,tst_l")) | |
820 | (eq_attr "op_mem" "11")) | |
821 | (eq_attr "size" "3")) | |
826fadba MK |
822 | "cf_ib3+cfv12_omove_11") |
823 | ||
96fcacb7 | 824 | (define_insn_reservation "cfv3_alu_11_1" 1 |
826fadba | 825 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
826 | (eq_attr "type" " |
827 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
828 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
829 | (eq_attr "op_mem" "11")) | |
830 | (eq_attr "size" "1")) | |
826fadba MK |
831 | "cf_ib1+cfv3_alu_11") |
832 | ||
96fcacb7 | 833 | (define_insn_reservation "cfv3_alu_11_2" 1 |
826fadba | 834 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
835 | (eq_attr "type" " |
836 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
837 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
838 | (eq_attr "size" "2")) | |
826fadba MK |
839 | (eq_attr "op_mem" "11")) |
840 | "cf_ib2+cfv3_alu_11") | |
841 | ||
96fcacb7 | 842 | (define_insn_reservation "cfv3_alu_11_3" 1 |
826fadba | 843 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
844 | (eq_attr "type" " |
845 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
846 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
847 | (eq_attr "op_mem" "11")) | |
848 | (eq_attr "size" "3")) | |
826fadba MK |
849 | "cf_ib3+cfv3_alu_11") |
850 | ||
96fcacb7 | 851 | (define_insn_reservation "cfv3_omove_11_1" 1 |
826fadba | 852 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
853 | (eq_attr "type" " |
854 | move_l,tst_l")) | |
855 | (eq_attr "op_mem" "11")) | |
856 | (eq_attr "size" "1")) | |
826fadba MK |
857 | "cf_ib1+cfv3_omove_11") |
858 | ||
96fcacb7 | 859 | (define_insn_reservation "cfv3_omove_11_2" 1 |
826fadba | 860 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
861 | (eq_attr "type" " |
862 | move_l,tst_l")) | |
863 | (eq_attr "size" "2")) | |
826fadba MK |
864 | (eq_attr "op_mem" "11")) |
865 | "cf_ib2+cfv3_omove_11") | |
866 | ||
96fcacb7 | 867 | (define_insn_reservation "cfv3_omove_11_3" 1 |
826fadba | 868 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
869 | (eq_attr "type" " |
870 | move_l,tst_l")) | |
871 | (eq_attr "op_mem" "11")) | |
872 | (eq_attr "size" "3")) | |
826fadba MK |
873 | "cf_ib3+cfv3_omove_11") |
874 | ||
96fcacb7 MK |
875 | (define_insn_reservation "cfv1_alu_i1_2" 2 |
876 | (and (and (and (eq_attr "cpu" "cfv1") | |
877 | (eq_attr "type" " | |
878 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
879 | (eq_attr "op_mem" "i1")) | |
880 | (eq_attr "size" "1,2")) | |
826fadba MK |
881 | "cf_ib2+cfv12_alu_i1") |
882 | ||
96fcacb7 MK |
883 | (define_insn_reservation "cfv1_alu_i1_3" 2 |
884 | (and (and (and (eq_attr "cpu" "cfv1") | |
885 | (eq_attr "type" " | |
886 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
887 | (eq_attr "op_mem" "i1")) | |
888 | (eq_attr "size" "3")) | |
826fadba | 889 | "cf_ib3+cfv12_alu_i1") |
b8c96320 | 890 | |
96fcacb7 MK |
891 | (define_insn_reservation "cfv1_omove_i1_2" 2 |
892 | (and (and (and (eq_attr "cpu" "cfv1") | |
893 | (eq_attr "type" " | |
894 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
895 | move_l,tst_l")) | |
896 | (eq_attr "op_mem" "i1")) | |
897 | (eq_attr "size" "1,2")) | |
826fadba | 898 | "cf_ib2+cfv12_omove_i1") |
b8c96320 | 899 | |
96fcacb7 MK |
900 | (define_insn_reservation "cfv1_omove_i1_3" 2 |
901 | (and (and (and (eq_attr "cpu" "cfv1") | |
902 | (eq_attr "type" " | |
903 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
904 | move_l,tst_l")) | |
905 | (eq_attr "op_mem" "i1")) | |
906 | (eq_attr "size" "3")) | |
826fadba | 907 | "cf_ib3+cfv12_omove_i1") |
b8c96320 | 908 | |
96fcacb7 MK |
909 | (define_insn_reservation "cfv2_alu_i1_2" 2 |
910 | (and (and (and (eq_attr "cpu" "cfv2") | |
911 | (eq_attr "type" " | |
912 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
913 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
914 | (eq_attr "op_mem" "i1")) | |
915 | (eq_attr "size" "1,2")) | |
916 | "cf_ib2+cfv12_alu_i1") | |
917 | ||
918 | (define_insn_reservation "cfv2_alu_i1_3" 2 | |
919 | (and (and (and (eq_attr "cpu" "cfv2") | |
920 | (eq_attr "type" " | |
921 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
922 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
923 | (eq_attr "op_mem" "i1")) | |
924 | (eq_attr "size" "3")) | |
925 | "cf_ib3+cfv12_alu_i1") | |
926 | ||
927 | (define_insn_reservation "cfv2_omove_i1_2" 2 | |
928 | (and (and (and (eq_attr "cpu" "cfv2") | |
929 | (eq_attr "type" " | |
930 | move_l,tst_l")) | |
931 | (eq_attr "op_mem" "i1")) | |
932 | (eq_attr "size" "1,2")) | |
933 | "cf_ib2+cfv12_omove_i1") | |
934 | ||
935 | (define_insn_reservation "cfv2_omove_i1_3" 2 | |
936 | (and (and (and (eq_attr "cpu" "cfv2") | |
937 | (eq_attr "type" " | |
938 | move_l,tst_l")) | |
939 | (eq_attr "op_mem" "i1")) | |
940 | (eq_attr "size" "3")) | |
941 | "cf_ib3+cfv12_omove_i1") | |
942 | ||
943 | (define_insn_reservation "cfv3_alu_i1_2" 2 | |
826fadba | 944 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
945 | (eq_attr "type" " |
946 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
947 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
948 | (eq_attr "op_mem" "i1")) | |
949 | (eq_attr "size" "1,2")) | |
826fadba | 950 | "cf_ib2+cfv3_alu_i1") |
b8c96320 | 951 | |
96fcacb7 | 952 | (define_insn_reservation "cfv3_alu_i1_3" 2 |
826fadba | 953 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
954 | (eq_attr "type" " |
955 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
956 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
957 | (eq_attr "op_mem" "i1")) | |
958 | (eq_attr "size" "3")) | |
826fadba MK |
959 | "cf_ib3+cfv3_alu_i1") |
960 | ||
96fcacb7 | 961 | (define_insn_reservation "cfv3_omove_i1_2" 2 |
826fadba | 962 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
963 | (eq_attr "type" " |
964 | move_l,tst_l")) | |
965 | (eq_attr "op_mem" "i1")) | |
966 | (eq_attr "size" "1,2")) | |
826fadba MK |
967 | "cf_ib2+cfv3_omove_i1") |
968 | ||
96fcacb7 | 969 | (define_insn_reservation "cfv3_omove_i1_3" 2 |
826fadba | 970 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
971 | (eq_attr "type" " |
972 | move_l,tst_l")) | |
973 | (eq_attr "op_mem" "i1")) | |
974 | (eq_attr "size" "3")) | |
826fadba MK |
975 | "cf_ib3+cfv3_omove_i1") |
976 | ||
96fcacb7 MK |
977 | (define_insn_reservation "cfv1_alu_1i_2" 2 |
978 | (and (and (and (eq_attr "cpu" "cfv1") | |
979 | (eq_attr "type" " | |
980 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
981 | (eq_attr "op_mem" "1i")) | |
982 | (eq_attr "size" "1,2")) | |
826fadba MK |
983 | "cf_ib2+cfv12_alu_1i") |
984 | ||
96fcacb7 MK |
985 | (define_insn_reservation "cfv1_alu_1i_3" 2 |
986 | (and (and (and (eq_attr "cpu" "cfv1") | |
987 | (eq_attr "type" " | |
988 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift")) | |
989 | (eq_attr "op_mem" "1i")) | |
990 | (eq_attr "size" "3")) | |
826fadba MK |
991 | "cf_ib3+cfv12_alu_1i") |
992 | ||
96fcacb7 MK |
993 | (define_insn_reservation "cfv1_omove_1i_2" 2 |
994 | (and (and (and (eq_attr "cpu" "cfv1") | |
995 | (eq_attr "type" " | |
996 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
997 | move_l,tst_l")) | |
998 | (eq_attr "op_mem" "1i")) | |
999 | (eq_attr "size" "1,2")) | |
826fadba MK |
1000 | "cf_ib2+cfv12_omove_1i") |
1001 | ||
96fcacb7 MK |
1002 | (define_insn_reservation "cfv1_omove_1i_3" 2 |
1003 | (and (and (and (eq_attr "cpu" "cfv1") | |
1004 | (eq_attr "type" " | |
1005 | clr,clr_l,mov3q_l,move,moveq_l,tst, | |
1006 | move_l,tst_l")) | |
1007 | (eq_attr "op_mem" "1i")) | |
1008 | (eq_attr "size" "3")) | |
1009 | "cf_ib3+cfv12_omove_1i") | |
1010 | ||
1011 | (define_insn_reservation "cfv2_alu_1i_2" 2 | |
1012 | (and (and (and (eq_attr "cpu" "cfv2") | |
1013 | (eq_attr "type" " | |
1014 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
1015 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
1016 | (eq_attr "op_mem" "1i")) | |
1017 | (eq_attr "size" "1,2")) | |
1018 | "cf_ib2+cfv12_alu_1i") | |
1019 | ||
1020 | (define_insn_reservation "cfv2_alu_1i_3" 2 | |
1021 | (and (and (and (eq_attr "cpu" "cfv2") | |
1022 | (eq_attr "type" " | |
1023 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
1024 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
1025 | (eq_attr "op_mem" "1i")) | |
1026 | (eq_attr "size" "3")) | |
1027 | "cf_ib3+cfv12_alu_1i") | |
1028 | ||
1029 | (define_insn_reservation "cfv2_omove_1i_2" 2 | |
1030 | (and (and (and (eq_attr "cpu" "cfv2") | |
1031 | (eq_attr "type" " | |
1032 | move_l,tst_l")) | |
1033 | (eq_attr "op_mem" "1i")) | |
1034 | (eq_attr "size" "1,2")) | |
1035 | "cf_ib2+cfv12_omove_1i") | |
1036 | ||
1037 | (define_insn_reservation "cfv2_omove_1i_3" 2 | |
1038 | (and (and (and (eq_attr "cpu" "cfv2") | |
1039 | (eq_attr "type" " | |
1040 | move_l,tst_l")) | |
1041 | (eq_attr "op_mem" "1i")) | |
1042 | (eq_attr "size" "3")) | |
826fadba | 1043 | "cf_ib3+cfv12_omove_1i") |
b8c96320 | 1044 | |
96fcacb7 | 1045 | (define_insn_reservation "cfv3_alu_1i_2" 2 |
826fadba | 1046 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1047 | (eq_attr "type" " |
1048 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
1049 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
1050 | (eq_attr "op_mem" "1i")) | |
1051 | (eq_attr "size" "1,2")) | |
826fadba | 1052 | "cf_ib2+cfv3_alu_1i") |
b8c96320 | 1053 | |
96fcacb7 | 1054 | (define_insn_reservation "cfv3_alu_1i_3" 2 |
826fadba | 1055 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1056 | (eq_attr "type" " |
1057 | alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift, | |
1058 | clr,clr_l,mov3q_l,move,moveq_l,tst")) | |
1059 | (eq_attr "op_mem" "1i")) | |
1060 | (eq_attr "size" "3")) | |
826fadba | 1061 | "cf_ib3+cfv3_alu_1i") |
b8c96320 | 1062 | |
96fcacb7 | 1063 | (define_insn_reservation "cfv3_omove_1i_2" 2 |
826fadba | 1064 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1065 | (eq_attr "type" " |
1066 | move_l,tst_l")) | |
1067 | (eq_attr "op_mem" "1i")) | |
1068 | (eq_attr "size" "1,2")) | |
826fadba | 1069 | "cf_ib2+cfv3_omove_1i") |
b8c96320 | 1070 | |
96fcacb7 | 1071 | (define_insn_reservation "cfv3_omove_1i_3" 2 |
826fadba | 1072 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1073 | (eq_attr "type" " |
1074 | move_l,tst_l")) | |
1075 | (eq_attr "op_mem" "1i")) | |
1076 | (eq_attr "size" "3")) | |
826fadba | 1077 | "cf_ib3+cfv3_omove_1i") |
b8c96320 | 1078 | |
826fadba MK |
1079 | (define_insn_reservation "cfv123_lea_10_1" 1 |
1080 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
1081 | (eq_attr "type" "lea")) |
1082 | (eq_attr "op_mem" "10,11,1i")) | |
1083 | (eq_attr "size" "1")) | |
826fadba | 1084 | "cf_ib1+cfv123_lea_10") |
b8c96320 | 1085 | |
826fadba MK |
1086 | (define_insn_reservation "cfv123_lea_10_2" 1 |
1087 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
1088 | (eq_attr "type" "lea")) |
1089 | (eq_attr "op_mem" "10,11,1i")) | |
1090 | (eq_attr "size" "2")) | |
826fadba | 1091 | "cf_ib2+cfv123_lea_10") |
b8c96320 | 1092 | |
826fadba MK |
1093 | (define_insn_reservation "cfv123_lea_10_3" 1 |
1094 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
1095 | (eq_attr "type" "lea")) |
1096 | (eq_attr "op_mem" "10,11,1i")) | |
1097 | (eq_attr "size" "3")) | |
826fadba | 1098 | "cf_ib3+cfv123_lea_10") |
b8c96320 | 1099 | |
826fadba MK |
1100 | (define_insn_reservation "cfv123_lea_i0_2" 2 |
1101 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
1102 | (eq_attr "type" "lea")) |
1103 | (eq_attr "op_mem" "i0,i1")) | |
1104 | (eq_attr "size" "1,2")) | |
826fadba | 1105 | "cf_ib2+cfv123_lea_i0") |
b8c96320 | 1106 | |
826fadba MK |
1107 | (define_insn_reservation "cfv123_lea_i0_3" 2 |
1108 | (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
96fcacb7 MK |
1109 | (eq_attr "type" "lea")) |
1110 | (eq_attr "op_mem" "i0,i1")) | |
1111 | (eq_attr "size" "3")) | |
826fadba | 1112 | "cf_ib3+cfv123_lea_i0") |
b8c96320 | 1113 | |
96fcacb7 | 1114 | (define_insn_reservation "cfv12_pea_11_1" 1 |
826fadba | 1115 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
1116 | (eq_attr "type" "pea")) |
1117 | (eq_attr "op_mem" "11")) | |
1118 | (eq_attr "size" "1")) | |
826fadba | 1119 | "cf_ib1+cfv12_pea_11") |
b8c96320 | 1120 | |
96fcacb7 | 1121 | (define_insn_reservation "cfv12_pea_11_2" 1 |
826fadba | 1122 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
1123 | (eq_attr "type" "pea")) |
1124 | (eq_attr "op_mem" "11")) | |
1125 | (eq_attr "size" "2")) | |
826fadba | 1126 | "cf_ib2+cfv12_pea_11") |
b8c96320 | 1127 | |
96fcacb7 | 1128 | (define_insn_reservation "cfv12_pea_11_3" 1 |
826fadba | 1129 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
1130 | (eq_attr "type" "pea")) |
1131 | (eq_attr "op_mem" "11")) | |
1132 | (eq_attr "size" "3")) | |
826fadba MK |
1133 | "cf_ib3+cfv12_pea_11") |
1134 | ||
96fcacb7 | 1135 | (define_insn_reservation "cfv3_pea_11_1" 1 |
826fadba | 1136 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1137 | (eq_attr "type" "pea")) |
1138 | (eq_attr "op_mem" "11")) | |
1139 | (eq_attr "size" "1")) | |
826fadba MK |
1140 | "cf_ib1+cfv3_pea_11") |
1141 | ||
96fcacb7 | 1142 | (define_insn_reservation "cfv3_pea_11_2" 1 |
826fadba | 1143 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1144 | (eq_attr "type" "pea")) |
1145 | (eq_attr "op_mem" "11")) | |
1146 | (eq_attr "size" "2")) | |
826fadba MK |
1147 | "cf_ib2+cfv3_pea_11") |
1148 | ||
96fcacb7 | 1149 | (define_insn_reservation "cfv3_pea_11_3" 1 |
826fadba | 1150 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1151 | (eq_attr "type" "pea")) |
1152 | (eq_attr "op_mem" "11")) | |
1153 | (eq_attr "size" "3")) | |
826fadba MK |
1154 | "cf_ib3+cfv3_pea_11") |
1155 | ||
96fcacb7 | 1156 | (define_insn_reservation "cfv12_pea_i1_2" 2 |
826fadba | 1157 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
1158 | (eq_attr "type" "pea")) |
1159 | (eq_attr "op_mem" "i1")) | |
1160 | (eq_attr "size" "1,2")) | |
826fadba MK |
1161 | "cf_ib2+cfv12_pea_i1") |
1162 | ||
96fcacb7 | 1163 | (define_insn_reservation "cfv12_pea_i1_3" 2 |
826fadba | 1164 | (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
96fcacb7 MK |
1165 | (eq_attr "type" "pea")) |
1166 | (eq_attr "op_mem" "i1")) | |
1167 | (eq_attr "size" "3")) | |
826fadba | 1168 | "cf_ib3+cfv12_pea_i1") |
b8c96320 | 1169 | |
96fcacb7 | 1170 | (define_insn_reservation "cfv3_pea_i1_2" 2 |
826fadba | 1171 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1172 | (eq_attr "type" "pea")) |
1173 | (eq_attr "op_mem" "i1")) | |
1174 | (eq_attr "size" "1,2")) | |
826fadba | 1175 | "cf_ib2+cfv3_pea_i1") |
b8c96320 | 1176 | |
96fcacb7 | 1177 | (define_insn_reservation "cfv3_pea_i1_3" 2 |
826fadba | 1178 | (and (and (and (eq_attr "cpu" "cfv3") |
96fcacb7 MK |
1179 | (eq_attr "type" "pea")) |
1180 | (eq_attr "op_mem" "i1")) | |
1181 | (eq_attr "size" "3")) | |
826fadba MK |
1182 | "cf_ib3+cfv3_pea_i1") |
1183 | ||
1184 | (define_insn_reservation "cfv123_mul_l_00_1" 18 | |
1185 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1186 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1187 | (eq_attr "type" "mul_l")) |
1188 | (eq_attr "op_mem" "00,01,0i")) | |
1189 | (eq_attr "size" "1")) | |
826fadba MK |
1190 | "cf_ib1+cfv123_mul_l_00") |
1191 | ||
1192 | (define_insn_reservation "cfv123_mul_l_00_2" 18 | |
1193 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1194 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1195 | (eq_attr "type" "mul_l")) |
1196 | (eq_attr "op_mem" "00,01,0i")) | |
1197 | (eq_attr "size" "2")) | |
826fadba MK |
1198 | "cf_ib2+cfv123_mul_l_00") |
1199 | ||
1200 | (define_insn_reservation "cfv123_mul_l_00_3" 18 | |
1201 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1202 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1203 | (eq_attr "type" "mul_l")) |
1204 | (eq_attr "op_mem" "00,01,0i")) | |
1205 | (eq_attr "size" "3")) | |
826fadba MK |
1206 | "cf_ib3+cfv123_mul_l_00") |
1207 | ||
1208 | (define_insn_reservation "cfv123_mul_w_00_1" 9 | |
1209 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1210 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1211 | (eq_attr "type" "mul_w")) |
1212 | (eq_attr "op_mem" "00,01,0i")) | |
1213 | (eq_attr "size" "1")) | |
826fadba MK |
1214 | "cf_ib1+cfv123_mul_w_00") |
1215 | ||
1216 | (define_insn_reservation "cfv123_mul_w_00_2" 9 | |
1217 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1218 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1219 | (eq_attr "type" "mul_w")) |
1220 | (eq_attr "op_mem" "00,01,0i")) | |
1221 | (eq_attr "size" "2")) | |
826fadba MK |
1222 | "cf_ib2+cfv123_mul_w_00") |
1223 | ||
1224 | (define_insn_reservation "cfv123_mul_w_00_3" 9 | |
1225 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1226 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1227 | (eq_attr "type" "mul_w")) |
1228 | (eq_attr "op_mem" "00,01,0i")) | |
1229 | (eq_attr "size" "3")) | |
826fadba MK |
1230 | "cf_ib3+cfv123_mul_w_00") |
1231 | ||
1232 | (define_insn_reservation "cfv12_mul_l_10_1" 20 | |
1233 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1234 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1235 | (eq_attr "type" "mul_l")) |
1236 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1237 | (eq_attr "size" "1")) | |
826fadba | 1238 | "cf_ib1+cfv12_mul_l_10") |
b8c96320 | 1239 | |
826fadba MK |
1240 | (define_insn_reservation "cfv12_mul_l_10_2" 20 |
1241 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1242 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1243 | (eq_attr "type" "mul_l")) |
1244 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1245 | (eq_attr "size" "2")) | |
826fadba MK |
1246 | "cf_ib2+cfv12_mul_l_10") |
1247 | ||
1248 | (define_insn_reservation "cfv12_mul_l_10_3" 20 | |
1249 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1250 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1251 | (eq_attr "type" "mul_l")) |
1252 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1253 | (eq_attr "size" "3")) | |
826fadba MK |
1254 | "cf_ib3+cfv12_mul_l_10") |
1255 | ||
1256 | (define_insn_reservation "cfv3_mul_l_10_1" 21 | |
1257 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1258 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1259 | (eq_attr "type" "mul_l")) |
1260 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1261 | (eq_attr "size" "1")) | |
826fadba MK |
1262 | "cf_ib1+cfv3_mul_l_10") |
1263 | ||
1264 | (define_insn_reservation "cfv3_mul_l_10_2" 21 | |
1265 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1266 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1267 | (eq_attr "type" "mul_l")) |
1268 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1269 | (eq_attr "size" "2")) | |
826fadba MK |
1270 | "cf_ib2+cfv3_mul_l_10") |
1271 | ||
1272 | (define_insn_reservation "cfv3_mul_l_10_3" 21 | |
1273 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1274 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1275 | (eq_attr "type" "mul_l")) |
1276 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1277 | (eq_attr "size" "3")) | |
826fadba MK |
1278 | "cf_ib3+cfv3_mul_l_10") |
1279 | ||
1280 | (define_insn_reservation "cfv12_mul_w_10_1" 11 | |
1281 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1282 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1283 | (eq_attr "type" "mul_w")) |
1284 | (eq_attr "op_mem" "10,11,1i")) | |
1285 | (eq_attr "size" "1")) | |
826fadba MK |
1286 | "cf_ib1+cfv12_mul_w_10") |
1287 | ||
1288 | (define_insn_reservation "cfv12_mul_w_10_2" 11 | |
1289 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1290 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1291 | (eq_attr "type" "mul_w")) |
1292 | (eq_attr "op_mem" "10,11,1i")) | |
1293 | (eq_attr "size" "2")) | |
826fadba MK |
1294 | "cf_ib2+cfv12_mul_w_10") |
1295 | ||
1296 | (define_insn_reservation "cfv12_mul_w_10_3" 11 | |
1297 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1298 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1299 | (eq_attr "type" "mul_w")) |
1300 | (eq_attr "op_mem" "10,11,1i")) | |
1301 | (eq_attr "size" "3")) | |
826fadba MK |
1302 | "cf_ib3+cfv12_mul_w_10") |
1303 | ||
1304 | (define_insn_reservation "cfv3_mul_w_10_1" 12 | |
1305 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1306 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1307 | (eq_attr "type" "mul_w")) |
1308 | (eq_attr "op_mem" "10,11,1i")) | |
1309 | (eq_attr "size" "1")) | |
826fadba MK |
1310 | "cf_ib1+cfv3_mul_w_10") |
1311 | ||
1312 | (define_insn_reservation "cfv3_mul_w_10_2" 12 | |
1313 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1314 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1315 | (eq_attr "type" "mul_w")) |
1316 | (eq_attr "op_mem" "10,11,1i")) | |
1317 | (eq_attr "size" "2")) | |
826fadba MK |
1318 | "cf_ib2+cfv3_mul_w_10") |
1319 | ||
1320 | (define_insn_reservation "cfv3_mul_w_10_3" 12 | |
1321 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1322 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1323 | (eq_attr "type" "mul_w")) |
1324 | (eq_attr "op_mem" "10,11,1i")) | |
1325 | (eq_attr "size" "3")) | |
826fadba MK |
1326 | "cf_ib3+cfv3_mul_w_10") |
1327 | ||
1328 | (define_insn_reservation "cfv12_mul_w_i0_2" 12 | |
1329 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1330 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1331 | (eq_attr "type" "mul_w")) |
1332 | (eq_attr "op_mem" "i0,i1")) | |
1333 | (eq_attr "size" "1,2")) | |
826fadba MK |
1334 | "cf_ib2+cfv12_mul_w_i0") |
1335 | ||
1336 | (define_insn_reservation "cfv12_mul_w_i0_3" 12 | |
1337 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1338 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1339 | (eq_attr "type" "mul_w")) |
1340 | (eq_attr "op_mem" "i0,i1")) | |
1341 | (eq_attr "size" "3")) | |
826fadba MK |
1342 | "cf_ib3+cfv12_mul_w_i0") |
1343 | ||
826fadba MK |
1344 | (define_insn_reservation "cfv3_mul_w_i0_2" 13 |
1345 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1346 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1347 | (eq_attr "type" "mul_w")) |
1348 | (eq_attr "op_mem" "i0,i1")) | |
1349 | (eq_attr "size" "1,2")) | |
826fadba MK |
1350 | "cf_ib2+cfv3_mul_w_i0") |
1351 | ||
1352 | (define_insn_reservation "cfv3_mul_w_i0_3" 13 | |
1353 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1354 | (eq_attr "mac" "no")) | |
96fcacb7 MK |
1355 | (eq_attr "type" "mul_w")) |
1356 | (eq_attr "op_mem" "i0,i1")) | |
1357 | (eq_attr "size" "3")) | |
826fadba MK |
1358 | "cf_ib3+cfv3_mul_w_i0") |
1359 | ||
1360 | (define_insn_reservation "cfv123_mac_l_00_1" 5 | |
1361 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1362 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1363 | (eq_attr "type" "mul_l")) |
1364 | (eq_attr "op_mem" "00,01,0i")) | |
1365 | (eq_attr "size" "1")) | |
826fadba | 1366 | "cf_ib1+cfv123_mac_l_00") |
b8c96320 | 1367 | |
826fadba MK |
1368 | (define_insn_reservation "cfv123_mac_l_00_2" 5 |
1369 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1370 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1371 | (eq_attr "type" "mul_l")) |
1372 | (eq_attr "op_mem" "00,01,0i")) | |
1373 | (eq_attr "size" "2")) | |
826fadba | 1374 | "cf_ib2+cfv123_mac_l_00") |
b8c96320 | 1375 | |
826fadba MK |
1376 | (define_insn_reservation "cfv123_mac_l_00_3" 5 |
1377 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1378 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1379 | (eq_attr "type" "mul_l")) |
1380 | (eq_attr "op_mem" "00,01,0i")) | |
1381 | (eq_attr "size" "3")) | |
826fadba MK |
1382 | "cf_ib3+cfv123_mac_l_00") |
1383 | ||
1384 | (define_insn_reservation "cfv123_mac_w_00_1" 3 | |
1385 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1386 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1387 | (eq_attr "type" "mul_w")) |
1388 | (eq_attr "op_mem" "00,01,0i")) | |
1389 | (eq_attr "size" "1")) | |
826fadba MK |
1390 | "cf_ib1+cfv123_mac_w_00") |
1391 | ||
1392 | (define_insn_reservation "cfv123_mac_w_00_2" 3 | |
1393 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1394 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1395 | (eq_attr "type" "mul_w")) |
1396 | (eq_attr "op_mem" "00,01,0i")) | |
1397 | (eq_attr "size" "2")) | |
826fadba MK |
1398 | "cf_ib2+cfv123_mac_w_00") |
1399 | ||
1400 | (define_insn_reservation "cfv123_mac_w_00_3" 3 | |
1401 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1402 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1403 | (eq_attr "type" "mul_w")) |
1404 | (eq_attr "op_mem" "00,01,0i")) | |
1405 | (eq_attr "size" "3")) | |
826fadba MK |
1406 | "cf_ib3+cfv123_mac_w_00") |
1407 | ||
1408 | (define_insn_reservation "cfv12_mac_l_10_1" 7 | |
1409 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1410 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1411 | (eq_attr "type" "mul_l")) |
1412 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1413 | (eq_attr "size" "1")) | |
826fadba MK |
1414 | "cf_ib1+cfv12_mac_l_10") |
1415 | ||
1416 | (define_insn_reservation "cfv12_mac_l_10_2" 7 | |
1417 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1418 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1419 | (eq_attr "type" "mul_l")) |
1420 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1421 | (eq_attr "size" "2")) | |
826fadba MK |
1422 | "cf_ib2+cfv12_mac_l_10") |
1423 | ||
1424 | (define_insn_reservation "cfv12_mac_l_10_3" 7 | |
1425 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1426 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1427 | (eq_attr "type" "mul_l")) |
1428 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1429 | (eq_attr "size" "3")) | |
826fadba | 1430 | "cf_ib3+cfv12_mac_l_10") |
b8c96320 | 1431 | |
826fadba MK |
1432 | (define_insn_reservation "cfv3_mac_l_10_1" 8 |
1433 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1434 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1435 | (eq_attr "type" "mul_l")) |
1436 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1437 | (eq_attr "size" "1")) | |
826fadba | 1438 | "cf_ib1+cfv3_mac_l_10") |
b8c96320 | 1439 | |
826fadba MK |
1440 | (define_insn_reservation "cfv3_mac_l_10_2" 8 |
1441 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1442 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1443 | (eq_attr "type" "mul_l")) |
1444 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1445 | (eq_attr "size" "2")) | |
826fadba | 1446 | "cf_ib2+cfv3_mac_l_10") |
b8c96320 | 1447 | |
826fadba MK |
1448 | (define_insn_reservation "cfv3_mac_l_10_3" 8 |
1449 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1450 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1451 | (eq_attr "type" "mul_l")) |
1452 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1453 | (eq_attr "size" "3")) | |
826fadba MK |
1454 | "cf_ib3+cfv3_mac_l_10") |
1455 | ||
1456 | (define_insn_reservation "cfv12_mac_w_10_1" 5 | |
1457 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1458 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1459 | (eq_attr "type" "mul_w")) |
1460 | (eq_attr "op_mem" "10,11,1i")) | |
1461 | (eq_attr "size" "1")) | |
826fadba | 1462 | "cf_ib1+cfv12_mac_w_10") |
b8c96320 | 1463 | |
826fadba MK |
1464 | (define_insn_reservation "cfv12_mac_w_10_2" 5 |
1465 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1466 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1467 | (eq_attr "type" "mul_w")) |
1468 | (eq_attr "op_mem" "10,11,1i")) | |
1469 | (eq_attr "size" "2")) | |
826fadba MK |
1470 | "cf_ib2+cfv12_mac_w_10") |
1471 | ||
1472 | (define_insn_reservation "cfv12_mac_w_10_3" 5 | |
1473 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1474 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1475 | (eq_attr "type" "mul_w")) |
1476 | (eq_attr "op_mem" "10,11,1i")) | |
1477 | (eq_attr "size" "3")) | |
826fadba MK |
1478 | "cf_ib3+cfv12_mac_w_10") |
1479 | ||
1480 | (define_insn_reservation "cfv3_mac_w_10_1" 6 | |
1481 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1482 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1483 | (eq_attr "type" "mul_w")) |
1484 | (eq_attr "op_mem" "10,11,1i")) | |
1485 | (eq_attr "size" "1")) | |
826fadba MK |
1486 | "cf_ib1+cfv3_mac_w_10") |
1487 | ||
1488 | (define_insn_reservation "cfv3_mac_w_10_2" 6 | |
1489 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1490 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1491 | (eq_attr "type" "mul_w")) |
1492 | (eq_attr "op_mem" "10,11,1i")) | |
1493 | (eq_attr "size" "2")) | |
826fadba MK |
1494 | "cf_ib2+cfv3_mac_w_10") |
1495 | ||
1496 | (define_insn_reservation "cfv3_mac_w_10_3" 6 | |
1497 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1498 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1499 | (eq_attr "type" "mul_w")) |
1500 | (eq_attr "op_mem" "10,11,1i")) | |
1501 | (eq_attr "size" "3")) | |
826fadba MK |
1502 | "cf_ib3+cfv3_mac_w_10") |
1503 | ||
1504 | (define_insn_reservation "cfv12_mac_w_i0_2" 6 | |
1505 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1506 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1507 | (eq_attr "type" "mul_w")) |
1508 | (eq_attr "op_mem" "i0,i1")) | |
1509 | (eq_attr "size" "1,2")) | |
826fadba | 1510 | "cf_ib2+cfv12_mac_w_i0") |
b8c96320 | 1511 | |
826fadba MK |
1512 | (define_insn_reservation "cfv12_mac_w_i0_3" 6 |
1513 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1514 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1515 | (eq_attr "type" "mul_w")) |
1516 | (eq_attr "op_mem" "i0,i1")) | |
1517 | (eq_attr "size" "3")) | |
826fadba | 1518 | "cf_ib3+cfv12_mac_w_i0") |
b8c96320 | 1519 | |
826fadba MK |
1520 | (define_insn_reservation "cfv3_mac_w_i0_2" 7 |
1521 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1522 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1523 | (eq_attr "type" "mul_w")) |
1524 | (eq_attr "op_mem" "i0,i1")) | |
1525 | (eq_attr "size" "1,2")) | |
826fadba | 1526 | "cf_ib2+cfv3_mac_w_i0") |
b8c96320 | 1527 | |
826fadba MK |
1528 | (define_insn_reservation "cfv3_mac_w_i0_3" 7 |
1529 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1530 | (eq_attr "mac" "cf_mac")) | |
96fcacb7 MK |
1531 | (eq_attr "type" "mul_w")) |
1532 | (eq_attr "op_mem" "i0,i1")) | |
1533 | (eq_attr "size" "3")) | |
826fadba MK |
1534 | "cf_ib3+cfv3_mac_w_i0") |
1535 | ||
1536 | (define_insn_reservation "cfv123_emac_00_1" 4 | |
1537 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1538 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1539 | (eq_attr "type" "mul_l,mul_w")) |
1540 | (eq_attr "op_mem" "00,01,0i")) | |
1541 | (eq_attr "size" "1")) | |
826fadba MK |
1542 | "cf_ib1+cfv123_emac_00") |
1543 | ||
1544 | (define_insn_reservation "cfv123_emac_00_2" 4 | |
1545 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1546 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1547 | (eq_attr "type" "mul_l,mul_w")) |
1548 | (eq_attr "op_mem" "00,01,0i")) | |
1549 | (eq_attr "size" "2")) | |
826fadba MK |
1550 | "cf_ib2+cfv123_emac_00") |
1551 | ||
1552 | (define_insn_reservation "cfv123_emac_00_3" 4 | |
1553 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1554 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1555 | (eq_attr "type" "mul_l,mul_w")) |
1556 | (eq_attr "op_mem" "00,01,0i")) | |
1557 | (eq_attr "size" "3")) | |
826fadba MK |
1558 | "cf_ib3+cfv123_emac_00") |
1559 | ||
96fcacb7 | 1560 | (define_insn_reservation "cfv12_emac_l_10_1" 6 |
826fadba MK |
1561 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
1562 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1563 | (eq_attr "type" "mul_l")) |
1564 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1565 | (eq_attr "size" "1")) | |
826fadba MK |
1566 | "cf_ib1+cfv12_emac_10") |
1567 | ||
96fcacb7 | 1568 | (define_insn_reservation "cfv12_emac_l_10_2" 6 |
826fadba MK |
1569 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
1570 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1571 | (eq_attr "type" "mul_l")) |
1572 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1573 | (eq_attr "size" "2")) | |
826fadba MK |
1574 | "cf_ib2+cfv12_emac_10") |
1575 | ||
96fcacb7 | 1576 | (define_insn_reservation "cfv12_emac_l_10_3" 6 |
826fadba MK |
1577 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") |
1578 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1579 | (eq_attr "type" "mul_l")) |
1580 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1581 | (eq_attr "size" "3")) | |
826fadba MK |
1582 | "cf_ib3+cfv12_emac_10") |
1583 | ||
96fcacb7 | 1584 | (define_insn_reservation "cfv3_emac_l_10_1" 7 |
826fadba MK |
1585 | (and (and (and (and (eq_attr "cpu" "cfv3") |
1586 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1587 | (eq_attr "type" "mul_l")) |
1588 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1589 | (eq_attr "size" "1")) | |
826fadba MK |
1590 | "cf_ib1+cfv3_emac_10") |
1591 | ||
96fcacb7 | 1592 | (define_insn_reservation "cfv3_emac_l_10_2" 7 |
826fadba MK |
1593 | (and (and (and (and (eq_attr "cpu" "cfv3") |
1594 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1595 | (eq_attr "type" "mul_l")) |
1596 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1597 | (eq_attr "size" "2")) | |
826fadba MK |
1598 | "cf_ib2+cfv3_emac_10") |
1599 | ||
96fcacb7 | 1600 | (define_insn_reservation "cfv3_emac_l_10_3" 7 |
826fadba MK |
1601 | (and (and (and (and (eq_attr "cpu" "cfv3") |
1602 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1603 | (eq_attr "type" "mul_l")) |
1604 | (eq_attr "op_mem" "10,i0,i1,11,1i")) | |
1605 | (eq_attr "size" "3")) | |
1606 | "cf_ib3+cfv3_emac_10") | |
1607 | ||
1608 | (define_insn_reservation "cfv12_emac_w_10_1" 6 | |
1609 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1610 | (eq_attr "mac" "cf_emac")) | |
1611 | (eq_attr "type" "mul_w")) | |
1612 | (eq_attr "op_mem" "10,11,1i")) | |
1613 | (eq_attr "size" "1")) | |
1614 | "cf_ib1+cfv12_emac_10") | |
1615 | ||
1616 | (define_insn_reservation "cfv12_emac_w_10_2" 6 | |
1617 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1618 | (eq_attr "mac" "cf_emac")) | |
1619 | (eq_attr "type" "mul_w")) | |
1620 | (eq_attr "op_mem" "10,11,1i")) | |
1621 | (eq_attr "size" "2")) | |
1622 | "cf_ib2+cfv12_emac_10") | |
1623 | ||
1624 | (define_insn_reservation "cfv12_emac_w_10_3" 6 | |
1625 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1626 | (eq_attr "mac" "cf_emac")) | |
1627 | (eq_attr "type" "mul_w")) | |
1628 | (eq_attr "op_mem" "10,11,1i")) | |
1629 | (eq_attr "size" "3")) | |
1630 | "cf_ib3+cfv12_emac_10") | |
1631 | ||
1632 | (define_insn_reservation "cfv3_emac_w_10_1" 7 | |
1633 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1634 | (eq_attr "mac" "cf_emac")) | |
1635 | (eq_attr "type" "mul_w")) | |
1636 | (eq_attr "op_mem" "10,11,1i")) | |
1637 | (eq_attr "size" "1")) | |
1638 | "cf_ib1+cfv3_emac_10") | |
1639 | ||
1640 | (define_insn_reservation "cfv3_emac_w_10_2" 7 | |
1641 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1642 | (eq_attr "mac" "cf_emac")) | |
1643 | (eq_attr "type" "mul_w")) | |
1644 | (eq_attr "op_mem" "10,11,1i")) | |
1645 | (eq_attr "size" "2")) | |
1646 | "cf_ib2+cfv3_emac_10") | |
1647 | ||
1648 | (define_insn_reservation "cfv3_emac_w_10_3" 7 | |
1649 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1650 | (eq_attr "mac" "cf_emac")) | |
1651 | (eq_attr "type" "mul_w")) | |
1652 | (eq_attr "op_mem" "10,11,1i")) | |
1653 | (eq_attr "size" "3")) | |
826fadba MK |
1654 | "cf_ib3+cfv3_emac_10") |
1655 | ||
1656 | (define_insn_reservation "cfv12_emac_w_i0_2" 7 | |
1657 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1658 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1659 | (eq_attr "type" "mul_w")) |
1660 | (eq_attr "op_mem" "i0,i1")) | |
1661 | (eq_attr "size" "1,2")) | |
826fadba MK |
1662 | "cf_ib2+cfv12_emac_w_i0") |
1663 | ||
1664 | (define_insn_reservation "cfv12_emac_w_i0_3" 7 | |
1665 | (and (and (and (and (eq_attr "cpu" "cfv1,cfv2") | |
1666 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1667 | (eq_attr "type" "mul_w")) |
1668 | (eq_attr "op_mem" "i0,i1")) | |
1669 | (eq_attr "size" "3")) | |
826fadba MK |
1670 | "cf_ib3+cfv12_emac_w_i0") |
1671 | ||
1672 | (define_insn_reservation "cfv3_emac_w_i0_2" 8 | |
1673 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1674 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1675 | (eq_attr "type" "mul_w")) |
1676 | (eq_attr "op_mem" "i0,i1")) | |
1677 | (eq_attr "size" "1,2")) | |
826fadba MK |
1678 | "cf_ib2+cfv3_emac_w_i0") |
1679 | ||
1680 | (define_insn_reservation "cfv3_emac_w_i0_3" 8 | |
1681 | (and (and (and (and (eq_attr "cpu" "cfv3") | |
1682 | (eq_attr "mac" "cf_emac")) | |
96fcacb7 MK |
1683 | (eq_attr "type" "mul_w")) |
1684 | (eq_attr "op_mem" "i0,i1")) | |
1685 | (eq_attr "size" "3")) | |
826fadba MK |
1686 | "cf_ib3+cfv3_emac_w_i0") |
1687 | ||
96fcacb7 MK |
1688 | (define_insn_reservation "cfv12_rts" 5 |
1689 | (and (eq_attr "cpu" "cfv1,cfv2") | |
1690 | (eq_attr "type" "rts")) | |
826fadba | 1691 | "cf_ib1+cfv12_rts") |
b8c96320 | 1692 | |
96fcacb7 MK |
1693 | (define_insn_reservation "cfv3_rts" 8 |
1694 | (and (eq_attr "cpu" "cfv3") | |
1695 | (eq_attr "type" "rts")) | |
826fadba | 1696 | "cf_ib1+cfv3_rts") |
b8c96320 | 1697 | |
826fadba MK |
1698 | (define_insn_reservation "cfv12_call_1" 3 |
1699 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1700 | (eq_attr "type" "bsr,jsr")) |
1701 | (eq_attr "size" "1")) | |
826fadba | 1702 | "cf_ib1+cfv12_call") |
b8c96320 | 1703 | |
826fadba MK |
1704 | (define_insn_reservation "cfv12_call_2" 3 |
1705 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1706 | (eq_attr "type" "bsr,jsr")) |
1707 | (eq_attr "size" "2")) | |
826fadba MK |
1708 | "cf_ib2+cfv12_call") |
1709 | ||
1710 | (define_insn_reservation "cfv12_call_3" 3 | |
1711 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1712 | (eq_attr "type" "bsr,jsr")) |
1713 | (eq_attr "size" "3")) | |
826fadba MK |
1714 | "cf_ib3+cfv12_call") |
1715 | ||
1716 | (define_insn_reservation "cfv3_call_1" 1 | |
1717 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1718 | (eq_attr "type" "bsr,jsr")) |
1719 | (eq_attr "size" "1")) | |
826fadba | 1720 | "cf_ib1+cfv3_call") |
b8c96320 | 1721 | |
826fadba MK |
1722 | (define_insn_reservation "cfv3_call_2" 1 |
1723 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1724 | (eq_attr "type" "bsr,jsr")) |
1725 | (eq_attr "size" "2")) | |
826fadba | 1726 | "cf_ib2+cfv3_call") |
b8c96320 | 1727 | |
826fadba MK |
1728 | (define_insn_reservation "cfv3_call_3" 1 |
1729 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1730 | (eq_attr "type" "bsr,jsr")) |
1731 | (eq_attr "size" "3")) | |
826fadba | 1732 | "cf_ib3+cfv3_call") |
b8c96320 | 1733 | |
826fadba MK |
1734 | (define_insn_reservation "cfv12_bcc_1" 2 |
1735 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1736 | (eq_attr "type" "bcc")) |
1737 | (eq_attr "size" "1")) | |
826fadba | 1738 | "cf_ib1+cfv12_bcc") |
b8c96320 | 1739 | |
826fadba MK |
1740 | (define_insn_reservation "cfv12_bcc_2" 2 |
1741 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1742 | (eq_attr "type" "bcc")) |
1743 | (eq_attr "size" "2")) | |
826fadba MK |
1744 | "cf_ib2+cfv12_bcc") |
1745 | ||
1746 | (define_insn_reservation "cfv12_bcc_3" 2 | |
1747 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1748 | (eq_attr "type" "bcc")) |
1749 | (eq_attr "size" "3")) | |
826fadba | 1750 | "cf_ib3+cfv12_bcc") |
b8c96320 | 1751 | |
826fadba MK |
1752 | (define_insn_reservation "cfv3_bcc_1" 1 |
1753 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1754 | (eq_attr "type" "bcc")) |
1755 | (eq_attr "size" "1")) | |
826fadba | 1756 | "cf_ib1+cfv3_bcc") |
b8c96320 | 1757 | |
826fadba MK |
1758 | (define_insn_reservation "cfv3_bcc_2" 1 |
1759 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1760 | (eq_attr "type" "bcc")) |
1761 | (eq_attr "size" "2")) | |
826fadba | 1762 | "cf_ib2+cfv3_bcc") |
b8c96320 | 1763 | |
826fadba MK |
1764 | (define_insn_reservation "cfv3_bcc_3" 1 |
1765 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1766 | (eq_attr "type" "bcc")) |
1767 | (eq_attr "size" "3")) | |
826fadba MK |
1768 | "cf_ib3+cfv3_bcc") |
1769 | ||
1770 | (define_insn_reservation "cfv12_bra_1" 2 | |
1771 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1772 | (eq_attr "type" "bra")) |
1773 | (eq_attr "size" "1")) | |
826fadba | 1774 | "cf_ib1+cfv12_bra") |
b8c96320 | 1775 | |
826fadba MK |
1776 | (define_insn_reservation "cfv12_bra_2" 2 |
1777 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1778 | (eq_attr "type" "bra")) |
1779 | (eq_attr "size" "2")) | |
826fadba | 1780 | "cf_ib2+cfv12_bra") |
b8c96320 | 1781 | |
826fadba MK |
1782 | (define_insn_reservation "cfv12_bra_3" 2 |
1783 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1784 | (eq_attr "type" "bra")) |
1785 | (eq_attr "size" "3")) | |
826fadba MK |
1786 | "cf_ib3+cfv12_bra") |
1787 | ||
1788 | (define_insn_reservation "cfv3_bra_1" 1 | |
1789 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1790 | (eq_attr "type" "bra")) |
1791 | (eq_attr "size" "1")) | |
826fadba | 1792 | "cf_ib1+cfv3_bra") |
b8c96320 | 1793 | |
826fadba MK |
1794 | (define_insn_reservation "cfv3_bra_2" 1 |
1795 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1796 | (eq_attr "type" "bra")) |
1797 | (eq_attr "size" "2")) | |
826fadba | 1798 | "cf_ib2+cfv3_bra") |
b8c96320 | 1799 | |
826fadba MK |
1800 | (define_insn_reservation "cfv3_bra_3" 1 |
1801 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1802 | (eq_attr "type" "bra")) |
1803 | (eq_attr "size" "3")) | |
826fadba | 1804 | "cf_ib3+cfv3_bra") |
b8c96320 | 1805 | |
826fadba MK |
1806 | (define_insn_reservation "cfv12_jmp_1" 3 |
1807 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1808 | (eq_attr "type" "jmp")) |
1809 | (eq_attr "size" "1")) | |
826fadba MK |
1810 | "cf_ib1+cfv12_jmp") |
1811 | ||
1812 | (define_insn_reservation "cfv12_jmp_2" 3 | |
1813 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1814 | (eq_attr "type" "jmp")) |
1815 | (eq_attr "size" "2")) | |
826fadba MK |
1816 | "cf_ib2+cfv12_jmp") |
1817 | ||
1818 | (define_insn_reservation "cfv12_jmp_3" 3 | |
1819 | (and (and (eq_attr "cpu" "cfv1,cfv2") | |
96fcacb7 MK |
1820 | (eq_attr "type" "jmp")) |
1821 | (eq_attr "size" "3")) | |
826fadba | 1822 | "cf_ib3+cfv12_jmp") |
b8c96320 | 1823 | |
826fadba MK |
1824 | (define_insn_reservation "cfv3_jmp_1" 5 |
1825 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1826 | (eq_attr "type" "jmp")) |
1827 | (eq_attr "size" "1")) | |
826fadba | 1828 | "cf_ib1+cfv3_jmp") |
b8c96320 | 1829 | |
826fadba MK |
1830 | (define_insn_reservation "cfv3_jmp_2" 5 |
1831 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1832 | (eq_attr "type" "jmp")) |
1833 | (eq_attr "size" "2")) | |
826fadba | 1834 | "cf_ib2+cfv3_jmp") |
b8c96320 | 1835 | |
826fadba MK |
1836 | (define_insn_reservation "cfv3_jmp_3" 5 |
1837 | (and (and (eq_attr "cpu" "cfv3") | |
96fcacb7 MK |
1838 | (eq_attr "type" "jmp")) |
1839 | (eq_attr "size" "3")) | |
826fadba | 1840 | "cf_ib3+cfv3_jmp") |
b8c96320 | 1841 | |
96fcacb7 MK |
1842 | (define_insn_reservation "cfv12_unlk" 2 |
1843 | (and (eq_attr "cpu" "cfv1,cfv2") | |
1844 | (eq_attr "type" "unlk")) | |
826fadba MK |
1845 | "cf_ib1+cfv12_alu_10") |
1846 | ||
96fcacb7 MK |
1847 | (define_insn_reservation "cfv3_unlk" 3 |
1848 | (and (eq_attr "cpu" "cfv3") | |
1849 | (eq_attr "type" "unlk")) | |
826fadba | 1850 | "cf_ib1+cfv3_alu_10") |
b8c96320 | 1851 | |
96fcacb7 MK |
1852 | ;; Dummy reservation for instructions that are not handled. |
1853 | (define_insn_reservation "cfv123_guess" 3 | |
1854 | (and (eq_attr "cpu" "cfv1,cfv2,cfv3") | |
1855 | (eq_attr "type" "falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst, | |
1856 | div_w,div_l,link,mvsz,nop,trap,unknown")) | |
1857 | "cf_ib3+cfv123_guess+cf_dsoc+cf_agex+cf_mem") | |
b8c96320 | 1858 | |
96fcacb7 MK |
1859 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
1860 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
1861 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
b8c96320 | 1862 | |
96fcacb7 MK |
1863 | ;; Below is pipeline description of ColdFire V4 core. |
1864 | ;; It is substantially different from the description of V1, V2 or V3 cores, | |
1865 | ;; primarily due to no need to model the instruction buffer. | |
1866 | ;; | |
1867 | ;; V4 pipeline model uses a completely separate set of cpu units. | |
1868 | ||
1869 | ;; Operand Execution Pipeline. | |
1870 | (define_automaton "cfv4_oep") | |
1871 | ||
1872 | (define_cpu_unit "cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da" | |
1873 | "cfv4_oep") | |
1874 | ||
96fcacb7 MK |
1875 | ;; V4 has 3 cases of dual-issue. |
1876 | ;; After issuing a cfv4_pOEPx instruction, it'll be possible to issue | |
1877 | ;; a cfv4_sOEPx instruction on the same cycle (see final_presence_sets below). | |
1878 | (define_cpu_unit "cfv4_pOEP1,cfv4_sOEP1, | |
1879 | cfv4_pOEP2,cfv4_sOEP2, | |
1244a8b7 | 1880 | cfv4_pOEP3,cfv4_sOEP3" "cfv4_oep") |
96fcacb7 MK |
1881 | |
1882 | (final_presence_set "cfv4_sOEP1" "cfv4_pOEP1") | |
1883 | (final_presence_set "cfv4_sOEP2" "cfv4_pOEP2") | |
1884 | (final_presence_set "cfv4_sOEP3" "cfv4_pOEP3") | |
1885 | ||
1886 | ;; Reservation for instructions that don't allow dual-issue. | |
1887 | (define_reservation "cfv4_ds" "cfv4_pOEP1+cfv4_sOEP1+ | |
1888 | cfv4_pOEP2+cfv4_sOEP2+ | |
1889 | cfv4_pOEP3+cfv4_sOEP3") | |
1890 | ||
1891 | ;; Memory access resource. | |
1892 | (define_automaton "cfv4_mem") | |
1893 | ||
1894 | (define_cpu_unit "cfv4_mem" "cfv4_mem") | |
1895 | ||
1896 | ;; EMAC. | |
1897 | (define_automaton "cfv4_emac") | |
1898 | ||
1899 | (define_cpu_unit "cfv4_emac" "cfv4_emac") | |
1900 | ||
1901 | ;; FPU. | |
1902 | (define_automaton "cfv4_fp") | |
1903 | ||
1904 | (define_cpu_unit "cfv4_fp" "cfv4_fp") | |
1905 | ||
1906 | ;; Automaton for unknown instruction. | |
1907 | (define_automaton "cfv4_guess") | |
1908 | ||
1909 | (define_query_cpu_unit "cfv4_guess" "cfv4_guess") | |
1910 | ||
1911 | ;; This bypass allows 1st case of dual-issue. | |
1912 | (define_bypass 0 "cfv4_00_oag_pOEP1,cfv4_10_pOEP1,cfv4_i0_pOEP1" | |
1913 | "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_pOEP1, | |
1914 | cfv4_00_oag_moveql,cfv4_00_ex_sOEP13") | |
1915 | ||
1916 | ;; The following bypasses decrease the latency of producers if it modifies | |
1917 | ;; a target register in the EX stage and the consumer also uses | |
1918 | ;; that register in the EX stage. | |
1919 | (define_bypass 1 "cfv4_00_ex" "cfv4_00_ex,cfv4_00_ex_sOEP13") | |
1920 | (define_bypass 1 "cfv4_00_ex" "cfv4_10,cfv4_10_pOEP1,cfv4_i0,cfv4_i0_pOEP1" | |
1921 | "!m68k_sched_address_bypass_p") | |
1922 | ||
1923 | ;; Indexed loads with scale factors 2 and 4 require an update of the index | |
1924 | ;; register in the register file. Considering that the index register is | |
1925 | ;; only needed at the second cycle of address generation, we get | |
1926 | ;; a latency of 4. | |
1927 | ;; Producers for indexed loads with scale factor 1 should have | |
1928 | ;; a latency of 3. Since we're only allowed one bypass, we handle it | |
1929 | ;; in the adjust_cost hook. | |
1930 | (define_bypass 4 | |
1931 | "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_lea,cfv4_00_oag_pOEP1, | |
1932 | cfv4_00_oag_moveql" | |
1933 | "cfv4_i0,cfv4_i0_pOEP1" | |
1934 | "m68k_sched_indexed_address_bypass_p") | |
1935 | ||
1936 | ;; First part of cfv4_00. | |
1937 | ;; If issued in pairs with cfv4_movel_?0, the cost should be increased. | |
1938 | ;; ??? Is it possible that combined cfv4_movel_00 and cfv4_oag_00 instructions | |
1939 | ;; have longer latency than the two instructions emitted sequentially? | |
1940 | ;; Due to register renaming, the result of the sequence would be available | |
1941 | ;; after 3 cycles, instead of 4 for combined instruction? | |
1942 | (define_insn_reservation "cfv4_00_oag" 1 | |
1943 | (and (and (eq_attr "cpu" "cfv4") | |
1944 | (eq_attr "type" "alu_l,aluq_l,clr_l,cmp_l,mov3q_l,neg_l")) | |
1945 | (eq_attr "op_mem" "00")) | |
1946 | "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") | |
1947 | ||
1948 | (define_insn_reservation "cfv4_00_oag_pOEP3_sOEP12" 1 | |
1949 | (and (and (eq_attr "cpu" "cfv4") | |
1950 | (eq_attr "type" "move_l,mov3q_l,clr_l")) | |
1951 | (and (eq_attr "op_mem" "00") | |
1952 | (and (eq_attr "opx_type" "Rn") | |
1953 | (eq_attr "opy_type" "none,imm_q,imm_w,imm_l")))) | |
1954 | "cfv4_sOEP1|cfv4_sOEP2|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") | |
1955 | ||
1956 | (define_insn_reservation "cfv4_00_oag_lea" 1 | |
1957 | (and (eq_attr "cpu" "cfv4") | |
1958 | (eq_attr "type" "lea")) | |
1959 | "cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") | |
1960 | ||
1961 | (define_insn_reservation "cfv4_00_oag_pOEP1" 1 | |
1962 | (and (and (eq_attr "cpu" "cfv4") | |
1963 | (eq_attr "type" "move_l,mov3q_l,clr_l")) | |
1964 | (and (eq_attr "op_mem" "00") | |
1965 | (ior (eq_attr "opx_type" "!Rn") | |
1966 | (eq_attr "opy_type" "!none,imm_q,imm_w,imm_l")))) | |
1967 | "cfv4_sOEP1|(cfv4_pOEP1,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") | |
1968 | ||
1969 | (define_insn_reservation "cfv4_00_oag_moveql" 1 | |
1970 | (and (and (eq_attr "cpu" "cfv4") | |
1971 | (eq_attr "type" "moveq_l")) | |
1972 | (eq_attr "op_mem" "00")) | |
1973 | "cfv4_sOEP1|cfv4_sOEP2|cfv4_sOEP3|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") | |
b8c96320 | 1974 | |
96fcacb7 MK |
1975 | ;; Second part of cfv4_00. |
1976 | ;; Latency is either 1 or 4 depending on which stage the consumer | |
1977 | ;; will need the data. | |
b8c96320 | 1978 | |
96fcacb7 MK |
1979 | (define_insn_reservation "cfv4_00_ex" 4 |
1980 | (and (and (eq_attr "cpu" "cfv4") | |
1981 | (eq_attr "type" "bitr,bitrw,clr,cmp,move,mvsz,scc,tst")) | |
1982 | (eq_attr "op_mem" "00")) | |
1983 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") | |
1984 | ||
1985 | (define_insn_reservation "cfv4_00_ex_sOEP13" 4 | |
1986 | (and (and (eq_attr "cpu" "cfv4") | |
1987 | (eq_attr "type" "alux_l,ext,shift,tst_l")) | |
1988 | (eq_attr "op_mem" "00")) | |
1989 | "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)") | |
1990 | ||
1991 | ;; Several types mentioned in this reservation (e.g., ext and shift) don't | |
1992 | ;; support implicit load. But we handle them anyway due to first scheduling | |
1993 | ;; pass, which handles non-strict rtl. | |
1994 | ;; | |
1995 | ;; Latency is either 1 or 4 depending in which stage the consumer | |
1996 | ;; will need the data. | |
1997 | (define_insn_reservation "cfv4_10" 4 | |
1998 | (and (and (eq_attr "cpu" "cfv4") | |
1999 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2000 | clr,clr_l,cmp,cmp_l,ext, | |
2001 | mov3q_l,move,moveq_l,mvsz,neg_l, | |
2002 | shift,tst,tst_l")) | |
2003 | (eq_attr "op_mem" "10")) | |
2004 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") | |
2005 | ||
2006 | ;; Specialization of cfv4_10. | |
2007 | ;; move.l has OC2-to-DS forwarding path, that saves one cycle of latency. | |
2008 | (define_insn_reservation "cfv4_10_pOEP1" 3 | |
2009 | (and (and (eq_attr "cpu" "cfv4") | |
2010 | (eq_attr "type" "move_l")) | |
2011 | (eq_attr "op_mem" "10")) | |
2012 | "cfv4_pOEP1,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") | |
2013 | ||
2014 | ;; Same here. But +1 to latency due to longer OAG. | |
2015 | (define_insn_reservation "cfv4_i0" 5 | |
2016 | (and (and (eq_attr "cpu" "cfv4") | |
2017 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2018 | clr,clr_l,cmp,cmp_l,ext, | |
2019 | mov3q_l,move,moveq_l,mvsz,neg_l, | |
2020 | shift,tst,tst_l")) | |
2021 | (eq_attr "op_mem" "i0")) | |
2022 | "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") | |
b8c96320 | 2023 | |
96fcacb7 MK |
2024 | ;; ??? Does indexed load trigger dual-issue? |
2025 | ;; ??? Does OC2-to-DS forwarding path saves a cycle? | |
2026 | (define_insn_reservation "cfv4_i0_pOEP1" 4 | |
2027 | (and (and (eq_attr "cpu" "cfv4") | |
2028 | (eq_attr "type" "move_l")) | |
2029 | (eq_attr "op_mem" "i0")) | |
2030 | "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") | |
2031 | ||
2032 | ;; This reservation is for moves and clr. Arithmetic instructions | |
2033 | ;; don't write to memory unless they also read from it. | |
2034 | ;; But, before reload we can have all sorts of things. | |
2035 | ;; With cfv4_pOEP2 allow dual-issue for type 2 cases. | |
2036 | (define_insn_reservation "cfv4_01" 1 | |
2037 | (and (and (eq_attr "cpu" "cfv4") | |
2038 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2039 | clr,clr_l,cmp,cmp_l,ext, | |
2040 | mov3q_l,move,move_l,moveq_l,mvsz,neg_l, | |
2041 | shift")) | |
2042 | (eq_attr "op_mem" "01")) | |
2043 | "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2044 | ||
2045 | ;; ??? Does indexed store trigger dual-issue? | |
2046 | (define_insn_reservation "cfv4_0i" 2 | |
2047 | (and (and (eq_attr "cpu" "cfv4") | |
2048 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2049 | clr,clr_l,cmp,cmp_l,ext, | |
2050 | mov3q_l,move,move_l,moveq_l,mvsz,neg_l, | |
2051 | shift")) | |
2052 | (eq_attr "op_mem" "0i")) | |
2053 | "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2054 | ||
2055 | (define_insn_reservation "cfv4_11" 1 | |
2056 | (and (and (eq_attr "cpu" "cfv4") | |
2057 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2058 | clr,clr_l,cmp,cmp_l,ext, | |
2059 | mov3q_l,move,move_l,moveq_l,mvsz,neg_l, | |
2060 | shift")) | |
2061 | (eq_attr "op_mem" "11")) | |
2062 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2063 | ||
2064 | ;; Latency is 2 due to long OAG stage. | |
2065 | (define_insn_reservation "cfv4_i1" 2 | |
2066 | (and (and (eq_attr "cpu" "cfv4") | |
2067 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2068 | clr,clr_l,cmp,cmp_l,ext, | |
2069 | mov3q_l,move,move_l,moveq_l,mvsz,neg_l, | |
2070 | shift")) | |
2071 | (eq_attr "op_mem" "i1")) | |
2072 | "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2073 | ||
2074 | ;; This one is the same as cfv4_i1. | |
2075 | ;; ??? Should it be different? | |
2076 | (define_insn_reservation "cfv4_1i" 2 | |
2077 | (and (and (eq_attr "cpu" "cfv4") | |
2078 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw, | |
2079 | clr,clr_l,cmp,cmp_l,ext, | |
2080 | mov3q_l,move,move_l,moveq_l,mvsz,neg_l, | |
2081 | shift")) | |
2082 | (eq_attr "op_mem" "1i")) | |
2083 | "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2084 | ||
2085 | ;; ??? Does pea indeed support case 2 of dual-issue? | |
2086 | (define_insn_reservation "cfv4_11_pea" 1 | |
2087 | (and (and (eq_attr "cpu" "cfv4") | |
2088 | (eq_attr "type" "pea")) | |
2089 | (eq_attr "op_mem" "11,00,01,0i,10")) | |
2090 | "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2091 | ||
2092 | ;; ??? Does pea indeed support case 2 of dual-issue? | |
2093 | ;; ??? Does indexed store trigger dual-issue? | |
2094 | (define_insn_reservation "cfv4_i1_pea" 1 | |
2095 | (and (and (eq_attr "cpu" "cfv4") | |
2096 | (eq_attr "type" "pea")) | |
2097 | (eq_attr "op_mem" "i1,1i")) | |
2098 | "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem") | |
2099 | ||
2100 | (define_insn_reservation "cfv4_link" 2 | |
2101 | (and (eq_attr "cpu" "cfv4") | |
2102 | (eq_attr "type" "link")) | |
2103 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_ex,cfv4_da,cfv4_mem") | |
2104 | ||
2105 | (define_insn_reservation "cfv4_unlink" 2 | |
2106 | (and (eq_attr "cpu" "cfv4") | |
2107 | (eq_attr "type" "unlk")) | |
2108 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") | |
2109 | ||
2110 | (define_insn_reservation "cfv4_divw_00" 20 | |
2111 | (and (and (eq_attr "cpu" "cfv4") | |
2112 | (eq_attr "type" "div_w")) | |
2113 | (eq_attr "op_mem" "00,01,0i")) | |
2114 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*15") | |
2115 | ||
2116 | (define_insn_reservation "cfv4_divw_10" 20 | |
2117 | (and (and (eq_attr "cpu" "cfv4") | |
2118 | (eq_attr "type" "div_w")) | |
2119 | (eq_attr "op_mem" "10,11,1i")) | |
2120 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15") | |
2121 | ||
2122 | (define_insn_reservation "cfv4_divw_i0" 21 | |
2123 | (and (and (eq_attr "cpu" "cfv4") | |
2124 | (eq_attr "type" "div_w")) | |
2125 | (eq_attr "op_mem" "i0,i1")) | |
2126 | "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15") | |
2127 | ||
2128 | (define_insn_reservation "cfv4_divl_00" 35 | |
2129 | (and (and (eq_attr "cpu" "cfv4") | |
2130 | (eq_attr "type" "div_l")) | |
2131 | (eq_attr "op_mem" "00,01,0i")) | |
2132 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*30") | |
2133 | ||
2134 | (define_insn_reservation "cfv4_divl_10" 35 | |
2135 | (and (and (eq_attr "cpu" "cfv4") | |
2136 | (eq_attr "type" "div_l")) | |
2137 | (eq_attr "op_mem" "10,11,1i,i0,i1")) | |
2138 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*30") | |
2139 | ||
2140 | (define_insn_reservation "cfv4_emac_mul_00" 7 | |
2141 | (and (and (eq_attr "cpu" "cfv4") | |
2142 | (eq_attr "type" "mul_w,mul_l")) | |
2143 | (eq_attr "op_mem" "00,01,0i")) | |
2144 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_emac") | |
2145 | ||
2146 | (define_insn_reservation "cfv4_emac_mul_10" 7 | |
2147 | (and (and (eq_attr "cpu" "cfv4") | |
2148 | (eq_attr "type" "mul_w,mul_l")) | |
2149 | (eq_attr "op_mem" "10,11,1i")) | |
2150 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac") | |
2151 | ||
2152 | (define_insn_reservation "cfv4_emac_mul_i0" 8 | |
2153 | (and (and (eq_attr "cpu" "cfv4") | |
2154 | (eq_attr "type" "mul_w,mul_l")) | |
2155 | (eq_attr "op_mem" "i0,i1")) | |
2156 | "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac") | |
2157 | ||
2158 | (define_insn_reservation "cfv4_falu_00" 7 | |
2159 | (and (and (eq_attr "cpu" "cfv4") | |
2160 | (eq_attr "type" "falu,fcmp,fmul")) | |
2161 | (eq_attr "op_mem" "00,01,0i")) | |
2162 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp") | |
2163 | ||
2164 | (define_insn_reservation "cfv4_falu_10" 7 | |
2165 | (and (and (eq_attr "cpu" "cfv4") | |
2166 | (eq_attr "type" "falu,fcmp,fmul")) | |
2167 | (eq_attr "op_mem" "10,i0,11,1i,i1")) | |
2168 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp") | |
2169 | ||
2170 | (define_insn_reservation "cfv4_fneg_00" 4 | |
2171 | (and (and (eq_attr "cpu" "cfv4") | |
2172 | (eq_attr "type" "fmove,fneg,ftst")) | |
2173 | (eq_attr "op_mem" "00")) | |
2174 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp") | |
2175 | ||
2176 | (define_insn_reservation "cfv4_fmove_fneg_10" 4 | |
2177 | (and (and (eq_attr "cpu" "cfv4") | |
2178 | (eq_attr "type" "fmove,fneg,ftst")) | |
2179 | (eq_attr "op_mem" "10,i0,11,1i,i1")) | |
2180 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp") | |
2181 | ||
2182 | (define_insn_reservation "cfv4_fmove_01" 1 | |
2183 | (and (and (eq_attr "cpu" "cfv4") | |
2184 | (eq_attr "type" "fmove,fneg,ftst")) | |
2185 | (eq_attr "op_mem" "01,0i")) | |
2186 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp,cfv4_da,cfv4_mem") | |
2187 | ||
2188 | (define_insn_reservation "cfv4_fdiv_00" 23 | |
2189 | (and (and (eq_attr "cpu" "cfv4") | |
2190 | (eq_attr "type" "fdiv")) | |
2191 | (eq_attr "op_mem" "00,01,0i")) | |
2192 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*17") | |
2193 | ||
2194 | (define_insn_reservation "cfv4_fdiv_10" 23 | |
2195 | (and (and (eq_attr "cpu" "cfv4") | |
2196 | (eq_attr "type" "fdiv")) | |
2197 | (eq_attr "op_mem" "10,i0,11,1i,i1")) | |
2198 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*17") | |
2199 | ||
2200 | (define_insn_reservation "cfv4_fsqrt_00" 56 | |
2201 | (and (and (eq_attr "cpu" "cfv4") | |
2202 | (eq_attr "type" "fsqrt")) | |
2203 | (eq_attr "op_mem" "00,01,0i")) | |
2204 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*50") | |
2205 | ||
2206 | (define_insn_reservation "cfv4_fsqrt_10" 56 | |
2207 | (and (and (eq_attr "cpu" "cfv4") | |
2208 | (eq_attr "type" "fsqrt")) | |
2209 | (eq_attr "op_mem" "10,i0,11,1i,i1")) | |
2210 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*50") | |
2211 | ||
2212 | (define_insn_reservation "cfv4_bcc" 0 | |
2213 | (and (eq_attr "cpu" "cfv4") | |
2214 | (eq_attr "type" "bcc")) | |
2215 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") | |
2216 | ||
2217 | (define_insn_reservation "cfv4_fbcc" 2 | |
2218 | (and (eq_attr "cpu" "cfv4") | |
2219 | (eq_attr "type" "fbcc")) | |
2220 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp") | |
2221 | ||
2222 | ;; ??? Why is bra said to write to memory: 1(0/1) ? | |
2223 | (define_insn_reservation "cfv4_bra_bsr" 1 | |
2224 | (and (eq_attr "cpu" "cfv4") | |
2225 | (eq_attr "type" "bra,bsr")) | |
2226 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") | |
2227 | ||
2228 | (define_insn_reservation "cfv4_jmp_jsr" 5 | |
2229 | (and (eq_attr "cpu" "cfv4") | |
2230 | (eq_attr "type" "jmp,jsr")) | |
2231 | "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex") | |
2232 | ||
2233 | (define_insn_reservation "cfv4_rts" 2 | |
2234 | (and (eq_attr "cpu" "cfv4") | |
2235 | (eq_attr "type" "rts")) | |
2236 | "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex") | |
2237 | ||
2238 | (define_insn_reservation "cfv4_nop" 1 | |
2239 | (and (eq_attr "cpu" "cfv4") | |
2240 | (eq_attr "type" "nop")) | |
2241 | "cfv4_ds+cfv4_oag+cfv4_oc1+cfv4_mem+cfv4_oc2+cfv4_ex") | |
2242 | ||
2243 | (define_insn_reservation "cfv4_guess" 10 | |
2244 | (and (eq_attr "cpu" "cfv4") | |
2245 | (eq_attr "type" "trap,unknown")) | |
2246 | "cfv4_guess+cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac+cfv4_fp") | |
2247 | ||
2248 | (define_insn_reservation "ignore" 0 | |
2249 | (eq_attr "type" "ignore") | |
2250 | "nothing") |