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5243fbff | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
aad93da1 | 2 | Copyright (C) 1987-2017 Free Software Foundation, Inc. |
5243fbff | 3 | |
187b36cf | 4 | This file is part of GCC. |
5243fbff | 5 | |
187b36cf | 6 | GCC is free software; you can redistribute it and/or modify |
5243fbff | 7 | it under the terms of the GNU General Public License as published by |
038d1e19 | 8 | the Free Software Foundation; either version 3, or (at your option) |
5243fbff | 9 | any later version. |
10 | ||
187b36cf | 11 | GCC is distributed in the hope that it will be useful, |
5243fbff | 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
5243fbff | 19 | |
5243fbff | 20 | #include "config.h" |
6c82faf1 | 21 | #include "system.h" |
805e22b2 | 22 | #include "coretypes.h" |
9ef16211 | 23 | #include "backend.h" |
d040a5b0 | 24 | #include "cfghooks.h" |
7720c877 | 25 | #include "tree.h" |
30a86690 | 26 | #include "stringpool.h" |
27 | #include "attribs.h" | |
9ef16211 | 28 | #include "rtl.h" |
29 | #include "df.h" | |
30 | #include "alias.h" | |
b20a8bb4 | 31 | #include "fold-const.h" |
9ed99284 | 32 | #include "calls.h" |
33 | #include "stor-layout.h" | |
34 | #include "varasm.h" | |
5243fbff | 35 | #include "regs.h" |
5243fbff | 36 | #include "insn-config.h" |
37 | #include "conditions.h" | |
5243fbff | 38 | #include "output.h" |
39 | #include "insn-attr.h" | |
e6b2f841 | 40 | #include "recog.h" |
0b205f4c | 41 | #include "diagnostic-core.h" |
d53441c8 | 42 | #include "flags.h" |
d53441c8 | 43 | #include "expmed.h" |
44 | #include "dojump.h" | |
45 | #include "explow.h" | |
ad7b10a2 | 46 | #include "memmodel.h" |
d53441c8 | 47 | #include "emit-rtl.h" |
48 | #include "stmt.h" | |
9ce40aae | 49 | #include "expr.h" |
50 | #include "reload.h" | |
f2fa409d | 51 | #include "tm_p.h" |
a767736d | 52 | #include "target.h" |
01d15dc5 | 53 | #include "debug.h" |
94ea8568 | 54 | #include "cfgrtl.h" |
55 | #include "cfganal.h" | |
56 | #include "lcm.h" | |
57 | #include "cfgbuild.h" | |
58 | #include "cfgcleanup.h" | |
15b9ea10 | 59 | /* ??? Need to add a dependency between m68k.o and sched-int.h. */ |
60 | #include "sched-int.h" | |
61 | #include "insn-codes.h" | |
fba5dd52 | 62 | #include "opts.h" |
5bb27b7c | 63 | #include "optabs.h" |
f7715905 | 64 | #include "builtins.h" |
d8ca5b53 | 65 | #include "rtl-iter.h" |
5243fbff | 66 | |
0c71fb4f | 67 | /* This file should be included last. */ |
4b498588 | 68 | #include "target-def.h" |
69 | ||
69d0a6ee | 70 | enum reg_class regno_reg_class[] = |
71 | { | |
72 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
73 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
74 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
75 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
76 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
77 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
78 | ADDR_REGS | |
79 | }; | |
80 | ||
81 | ||
9c47decb | 82 | /* The minimum number of integer registers that we want to save with the |
83 | movem instruction. Using two movel instructions instead of a single | |
84 | moveml is about 15% faster for the 68020 and 68030 at no expense in | |
85 | code size. */ | |
86 | #define MIN_MOVEM_REGS 3 | |
87 | ||
88 | /* The minimum number of floating point registers that we want to save | |
89 | with the fmovem instruction. */ | |
90 | #define MIN_FMOVEM_REGS 1 | |
91 | ||
1d60d981 | 92 | /* Structure describing stack frame layout. */ |
d02588f4 | 93 | struct m68k_frame |
94 | { | |
95 | /* Stack pointer to frame pointer offset. */ | |
7366b851 | 96 | HOST_WIDE_INT offset; |
d02588f4 | 97 | |
98 | /* Offset of FPU registers. */ | |
99 | HOST_WIDE_INT foffset; | |
100 | ||
101 | /* Frame size in bytes (rounded up). */ | |
7366b851 | 102 | HOST_WIDE_INT size; |
d02588f4 | 103 | |
104 | /* Data and address register. */ | |
7366b851 | 105 | int reg_no; |
106 | unsigned int reg_mask; | |
d02588f4 | 107 | |
108 | /* FPU registers. */ | |
7366b851 | 109 | int fpu_no; |
110 | unsigned int fpu_mask; | |
d02588f4 | 111 | |
112 | /* Offsets relative to ARG_POINTER. */ | |
7366b851 | 113 | HOST_WIDE_INT frame_pointer_offset; |
114 | HOST_WIDE_INT stack_pointer_offset; | |
d02588f4 | 115 | |
116 | /* Function which the above information refers to. */ | |
117 | int funcdef_no; | |
7366b851 | 118 | }; |
119 | ||
d02588f4 | 120 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
121 | static struct m68k_frame current_frame; | |
122 | ||
b97b0687 | 123 | /* Structure describing an m68k address. |
124 | ||
125 | If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, | |
126 | with null fields evaluating to 0. Here: | |
127 | ||
128 | - BASE satisfies m68k_legitimate_base_reg_p | |
129 | - INDEX satisfies m68k_legitimate_index_reg_p | |
130 | - OFFSET satisfies m68k_legitimate_constant_address_p | |
131 | ||
132 | INDEX is either HImode or SImode. The other fields are SImode. | |
133 | ||
134 | If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, | |
135 | the address is (BASE)+. */ | |
136 | struct m68k_address { | |
137 | enum rtx_code code; | |
138 | rtx base; | |
139 | rtx index; | |
140 | rtx offset; | |
141 | int scale; | |
142 | }; | |
143 | ||
99f52c2b | 144 | static int m68k_sched_adjust_cost (rtx_insn *, int, rtx_insn *, int, |
145 | unsigned int); | |
3c904dda | 146 | static int m68k_sched_issue_rate (void); |
18282db0 | 147 | static int m68k_sched_variable_issue (FILE *, int, rtx_insn *, int); |
15b9ea10 | 148 | static void m68k_sched_md_init_global (FILE *, int, int); |
149 | static void m68k_sched_md_finish_global (FILE *, int); | |
150 | static void m68k_sched_md_init (FILE *, int, int); | |
151 | static void m68k_sched_dfa_pre_advance_cycle (void); | |
152 | static void m68k_sched_dfa_post_advance_cycle (void); | |
3c904dda | 153 | static int m68k_sched_first_cycle_multipass_dfa_lookahead (void); |
15b9ea10 | 154 | |
cd90919d | 155 | static bool m68k_can_eliminate (const int, const int); |
b2d7ede1 | 156 | static void m68k_conditional_register_usage (void); |
3754d046 | 157 | static bool m68k_legitimate_address_p (machine_mode, rtx, bool); |
4c834714 | 158 | static void m68k_option_override (void); |
c2e7013d | 159 | static void m68k_override_options_after_change (void); |
821960c7 | 160 | static rtx find_addr_reg (rtx); |
161 | static const char *singlemove_string (rtx *); | |
821960c7 | 162 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
163 | HOST_WIDE_INT, tree); | |
c8c47ddf | 164 | static rtx m68k_struct_value_rtx (tree, int); |
7366b851 | 165 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, |
166 | tree args, int flags, | |
167 | bool *no_add_attrs); | |
d02588f4 | 168 | static void m68k_compute_frame_layout (void); |
7366b851 | 169 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
33fb08b8 | 170 | static bool m68k_ok_for_sibcall_p (tree, tree); |
869bde6b | 171 | static bool m68k_tls_symbol_p (rtx); |
3754d046 | 172 | static rtx m68k_legitimize_address (rtx, rtx, machine_mode); |
5ae4887d | 173 | static bool m68k_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
159cec75 | 174 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
33be53f9 | 175 | static bool m68k_return_in_memory (const_tree, const_tree); |
159cec75 | 176 | #endif |
869bde6b | 177 | static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
61fafd77 | 178 | static void m68k_trampoline_init (rtx, tree, rtx); |
f5bc28da | 179 | static int m68k_return_pops_args (tree, tree, int); |
1a1a6f69 | 180 | static rtx m68k_delegitimize_address (rtx); |
3754d046 | 181 | static void m68k_function_arg_advance (cumulative_args_t, machine_mode, |
385c19d1 | 182 | const_tree, bool); |
3754d046 | 183 | static rtx m68k_function_arg (cumulative_args_t, machine_mode, |
385c19d1 | 184 | const_tree, bool); |
3754d046 | 185 | static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x); |
27f5e69f | 186 | static bool m68k_output_addr_const_extra (FILE *, rtx); |
5bb27b7c | 187 | static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; |
41af789c | 188 | static enum flt_eval_method |
189 | m68k_excess_precision (enum excess_precision_type); | |
5243fbff | 190 | \f |
a767736d | 191 | /* Initialize the GCC target structure. */ |
58356836 | 192 | |
193 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
194 | #undef TARGET_ASM_ALIGNED_HI_OP | |
195 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
196 | #endif | |
197 | ||
198 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
199 | #undef TARGET_ASM_BYTE_OP | |
200 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
201 | #undef TARGET_ASM_ALIGNED_HI_OP | |
202 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
203 | #undef TARGET_ASM_ALIGNED_SI_OP | |
204 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
205 | #endif | |
206 | ||
207 | #if INT_OP_GROUP == INT_OP_DC | |
208 | #undef TARGET_ASM_BYTE_OP | |
209 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
210 | #undef TARGET_ASM_ALIGNED_HI_OP | |
211 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
212 | #undef TARGET_ASM_ALIGNED_SI_OP | |
213 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
214 | #endif | |
215 | ||
216 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
217 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
218 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
219 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
220 | ||
6988553d | 221 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
222 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
b712bf34 | 223 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
a9f1838b | 224 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
6988553d | 225 | |
92c473b8 | 226 | #undef TARGET_ASM_FILE_START_APP_OFF |
227 | #define TARGET_ASM_FILE_START_APP_OFF true | |
228 | ||
41e3a0c7 | 229 | #undef TARGET_LEGITIMIZE_ADDRESS |
230 | #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address | |
231 | ||
15b9ea10 | 232 | #undef TARGET_SCHED_ADJUST_COST |
233 | #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost | |
234 | ||
3c904dda | 235 | #undef TARGET_SCHED_ISSUE_RATE |
236 | #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate | |
237 | ||
15b9ea10 | 238 | #undef TARGET_SCHED_VARIABLE_ISSUE |
239 | #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue | |
240 | ||
241 | #undef TARGET_SCHED_INIT_GLOBAL | |
242 | #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global | |
243 | ||
244 | #undef TARGET_SCHED_FINISH_GLOBAL | |
245 | #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global | |
246 | ||
247 | #undef TARGET_SCHED_INIT | |
248 | #define TARGET_SCHED_INIT m68k_sched_md_init | |
249 | ||
250 | #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE | |
251 | #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle | |
252 | ||
253 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
254 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle | |
255 | ||
3c904dda | 256 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
257 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
258 | m68k_sched_first_cycle_multipass_dfa_lookahead | |
259 | ||
4c834714 | 260 | #undef TARGET_OPTION_OVERRIDE |
261 | #define TARGET_OPTION_OVERRIDE m68k_option_override | |
262 | ||
c2e7013d | 263 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
264 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change | |
265 | ||
fab7adbf | 266 | #undef TARGET_RTX_COSTS |
267 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
268 | ||
7366b851 | 269 | #undef TARGET_ATTRIBUTE_TABLE |
270 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
271 | ||
c8c47ddf | 272 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 273 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
c8c47ddf | 274 | |
275 | #undef TARGET_STRUCT_VALUE_RTX | |
276 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
277 | ||
e0ab7256 | 278 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
7d7d7bd2 | 279 | #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem |
e0ab7256 | 280 | |
33fb08b8 | 281 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
282 | #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p | |
283 | ||
159cec75 | 284 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
285 | #undef TARGET_RETURN_IN_MEMORY | |
286 | #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory | |
287 | #endif | |
288 | ||
869bde6b | 289 | #ifdef HAVE_AS_TLS |
290 | #undef TARGET_HAVE_TLS | |
291 | #define TARGET_HAVE_TLS (true) | |
292 | ||
293 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
294 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel | |
295 | #endif | |
296 | ||
e46fbef5 | 297 | #undef TARGET_LRA_P |
298 | #define TARGET_LRA_P hook_bool_void_false | |
299 | ||
fd50b071 | 300 | #undef TARGET_LEGITIMATE_ADDRESS_P |
301 | #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p | |
302 | ||
cd90919d | 303 | #undef TARGET_CAN_ELIMINATE |
304 | #define TARGET_CAN_ELIMINATE m68k_can_eliminate | |
305 | ||
b2d7ede1 | 306 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
307 | #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage | |
308 | ||
61fafd77 | 309 | #undef TARGET_TRAMPOLINE_INIT |
310 | #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init | |
311 | ||
f5bc28da | 312 | #undef TARGET_RETURN_POPS_ARGS |
313 | #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args | |
314 | ||
1a1a6f69 | 315 | #undef TARGET_DELEGITIMIZE_ADDRESS |
316 | #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address | |
317 | ||
385c19d1 | 318 | #undef TARGET_FUNCTION_ARG |
319 | #define TARGET_FUNCTION_ARG m68k_function_arg | |
320 | ||
321 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
322 | #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance | |
323 | ||
ca316360 | 324 | #undef TARGET_LEGITIMATE_CONSTANT_P |
325 | #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p | |
326 | ||
27f5e69f | 327 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
328 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra | |
329 | ||
41af789c | 330 | #undef TARGET_C_EXCESS_PRECISION |
331 | #define TARGET_C_EXCESS_PRECISION m68k_excess_precision | |
332 | ||
2a967206 | 333 | /* The value stored by TAS. */ |
334 | #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL | |
335 | #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128 | |
336 | ||
7366b851 | 337 | static const struct attribute_spec m68k_attribute_table[] = |
338 | { | |
ac86af5d | 339 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
340 | affects_type_identity } */ | |
341 | { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute, | |
342 | false }, | |
343 | { "interrupt_handler", 0, 0, true, false, false, | |
344 | m68k_handle_fndecl_attribute, false }, | |
345 | { "interrupt_thread", 0, 0, true, false, false, | |
346 | m68k_handle_fndecl_attribute, false }, | |
347 | { NULL, 0, 0, false, false, false, NULL, false } | |
7366b851 | 348 | }; |
349 | ||
57e4bbfb | 350 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 351 | \f |
8aed3cb3 | 352 | /* Base flags for 68k ISAs. */ |
353 | #define FL_FOR_isa_00 FL_ISA_68000 | |
354 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
355 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
356 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
357 | not to. */ | |
358 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
5980279a | 359 | | FL_BITFIELD | FL_68881 | FL_CAS) |
8aed3cb3 | 360 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) |
361 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
362 | ||
363 | /* Base flags for ColdFire ISAs. */ | |
364 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
365 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
366 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
367 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
7f2330d5 | 368 | /* ISA_C is not upwardly compatible with ISA_B. */ |
12877e83 | 369 | #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP) |
8aed3cb3 | 370 | |
371 | enum m68k_isa | |
372 | { | |
373 | /* Traditional 68000 instruction sets. */ | |
374 | isa_00, | |
375 | isa_10, | |
376 | isa_20, | |
377 | isa_40, | |
378 | isa_cpu32, | |
379 | /* ColdFire instruction set variants. */ | |
380 | isa_a, | |
381 | isa_aplus, | |
382 | isa_b, | |
383 | isa_c, | |
384 | isa_max | |
385 | }; | |
386 | ||
387 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
388 | struct m68k_target_selection | |
389 | { | |
390 | /* The argument being described. */ | |
391 | const char *name; | |
392 | ||
393 | /* For -mcpu, this is the device selected by the option. | |
394 | For -mtune and -march, it is a representative device | |
395 | for the microarchitecture or ISA respectively. */ | |
396 | enum target_device device; | |
397 | ||
398 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
399 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
400 | const char *family; | |
401 | enum uarch_type microarch; | |
402 | enum m68k_isa isa; | |
403 | unsigned long flags; | |
404 | }; | |
405 | ||
406 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
407 | static const struct m68k_target_selection all_devices[] = | |
408 | { | |
409 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
410 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
411 | #include "m68k-devices.def" | |
412 | #undef M68K_DEVICE | |
413 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
414 | }; | |
415 | ||
416 | /* A list of all ISAs, mapping each one to a representative device. | |
417 | Used for -march selection. */ | |
418 | static const struct m68k_target_selection all_isas[] = | |
419 | { | |
d078aadd | 420 | #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ |
421 | { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, | |
422 | #include "m68k-isas.def" | |
423 | #undef M68K_ISA | |
8aed3cb3 | 424 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
425 | }; | |
426 | ||
427 | /* A list of all microarchitectures, mapping each one to a representative | |
428 | device. Used for -mtune selection. */ | |
429 | static const struct m68k_target_selection all_microarchs[] = | |
430 | { | |
d078aadd | 431 | #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ |
432 | { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, | |
433 | #include "m68k-microarchs.def" | |
434 | #undef M68K_MICROARCH | |
8aed3cb3 | 435 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
436 | }; | |
437 | \f | |
438 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
439 | or null for options that have not been used. */ | |
440 | const struct m68k_target_selection *m68k_cpu_entry; | |
441 | const struct m68k_target_selection *m68k_arch_entry; | |
442 | const struct m68k_target_selection *m68k_tune_entry; | |
443 | ||
444 | /* Which CPU we are generating code for. */ | |
445 | enum target_device m68k_cpu; | |
446 | ||
447 | /* Which microarchitecture to tune for. */ | |
448 | enum uarch_type m68k_tune; | |
449 | ||
450 | /* Which FPU to use. */ | |
451 | enum fpu_type m68k_fpu; | |
fbdd0521 | 452 | |
8aed3cb3 | 453 | /* The set of FL_* flags that apply to the target processor. */ |
454 | unsigned int m68k_cpu_flags; | |
dd7218bb | 455 | |
53457e36 | 456 | /* The set of FL_* flags that apply to the processor to be tuned for. */ |
457 | unsigned int m68k_tune_flags; | |
458 | ||
dd7218bb | 459 | /* Asm templates for calling or jumping to an arbitrary symbolic address, |
460 | or NULL if such calls or jumps are not supported. The address is held | |
461 | in operand 0. */ | |
462 | const char *m68k_symbolic_call; | |
463 | const char *m68k_symbolic_jump; | |
1d86aeab | 464 | |
465 | /* Enum variable that corresponds to m68k_symbolic_call values. */ | |
466 | enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; | |
467 | ||
8aed3cb3 | 468 | \f |
4c834714 | 469 | /* Implement TARGET_OPTION_OVERRIDE. */ |
d0c0c9ac | 470 | |
4c834714 | 471 | static void |
472 | m68k_option_override (void) | |
d0c0c9ac | 473 | { |
8aed3cb3 | 474 | const struct m68k_target_selection *entry; |
475 | unsigned long target_mask; | |
476 | ||
d078aadd | 477 | if (global_options_set.x_m68k_arch_option) |
478 | m68k_arch_entry = &all_isas[m68k_arch_option]; | |
479 | ||
480 | if (global_options_set.x_m68k_cpu_option) | |
481 | m68k_cpu_entry = &all_devices[(int) m68k_cpu_option]; | |
482 | ||
483 | if (global_options_set.x_m68k_tune_option) | |
484 | m68k_tune_entry = &all_microarchs[(int) m68k_tune_option]; | |
485 | ||
8aed3cb3 | 486 | /* User can choose: |
487 | ||
488 | -mcpu= | |
489 | -march= | |
490 | -mtune= | |
491 | ||
492 | -march=ARCH should generate code that runs any processor | |
493 | implementing architecture ARCH. -mcpu=CPU should override -march | |
494 | and should generate code that runs on processor CPU, making free | |
495 | use of any instructions that CPU understands. -mtune=UARCH applies | |
f2b32076 | 496 | on top of -mcpu or -march and optimizes the code for UARCH. It does |
8aed3cb3 | 497 | not change the target architecture. */ |
498 | if (m68k_cpu_entry) | |
499 | { | |
500 | /* Complain if the -march setting is for a different microarchitecture, | |
501 | or includes flags that the -mcpu setting doesn't. */ | |
502 | if (m68k_arch_entry | |
503 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
504 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
505 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
506 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
507 | ||
508 | entry = m68k_cpu_entry; | |
509 | } | |
510 | else | |
511 | entry = m68k_arch_entry; | |
512 | ||
513 | if (!entry) | |
514 | entry = all_devices + TARGET_CPU_DEFAULT; | |
515 | ||
516 | m68k_cpu_flags = entry->flags; | |
517 | ||
518 | /* Use the architecture setting to derive default values for | |
519 | certain flags. */ | |
520 | target_mask = 0; | |
bf849667 | 521 | |
522 | /* ColdFire is lenient about alignment. */ | |
523 | if (!TARGET_COLDFIRE) | |
524 | target_mask |= MASK_STRICT_ALIGNMENT; | |
525 | ||
8aed3cb3 | 526 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) |
527 | target_mask |= MASK_BITFIELD; | |
528 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
529 | target_mask |= MASK_CF_HWDIV; | |
530 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
531 | target_mask |= MASK_HARD_FLOAT; | |
532 | target_flags |= target_mask & ~target_flags_explicit; | |
533 | ||
534 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
535 | m68k_cpu = entry->device; | |
536 | if (m68k_tune_entry) | |
53457e36 | 537 | { |
538 | m68k_tune = m68k_tune_entry->microarch; | |
539 | m68k_tune_flags = m68k_tune_entry->flags; | |
540 | } | |
8aed3cb3 | 541 | #ifdef M68K_DEFAULT_TUNE |
542 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
53457e36 | 543 | { |
544 | enum target_device dev; | |
545 | dev = all_microarchs[M68K_DEFAULT_TUNE].device; | |
aafc6adb | 546 | m68k_tune_flags = all_devices[dev].flags; |
53457e36 | 547 | } |
8aed3cb3 | 548 | #endif |
549 | else | |
53457e36 | 550 | { |
551 | m68k_tune = entry->microarch; | |
552 | m68k_tune_flags = entry->flags; | |
553 | } | |
8aed3cb3 | 554 | |
555 | /* Set the type of FPU. */ | |
556 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
557 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
558 | : FPUTYPE_68881); | |
559 | ||
b09faf5c | 560 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
561 | * both specified together. Doing so simply doesn't make sense. | |
562 | */ | |
563 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
564 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
565 | ||
566 | /* If we're generating code for a separate A5 relative data segment, | |
567 | * we've got to enable -fPIC as well. This might be relaxable to | |
568 | * -fpic but it hasn't been tested properly. | |
569 | */ | |
570 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
571 | flag_pic = 2; | |
572 | ||
f8200b2a | 573 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
574 | error if the target does not support them. */ | |
575 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
576 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
18fce2f0 | 577 | |
578 | /* ??? A historic way of turning on pic, or is this intended to | |
579 | be an embedded thing that doesn't have the same name binding | |
580 | significance that it does on hosted ELF systems? */ | |
581 | if (TARGET_PCREL && flag_pic == 0) | |
582 | flag_pic = 1; | |
583 | ||
dd7218bb | 584 | if (!flag_pic) |
585 | { | |
1d86aeab | 586 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR; |
587 | ||
dd7218bb | 588 | m68k_symbolic_jump = "jra %a0"; |
dd7218bb | 589 | } |
590 | else if (TARGET_ID_SHARED_LIBRARY) | |
591 | /* All addresses must be loaded from the GOT. */ | |
592 | ; | |
7f2330d5 | 593 | else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC) |
dd7218bb | 594 | { |
595 | if (TARGET_PCREL) | |
1d86aeab | 596 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C; |
7f2330d5 | 597 | else |
1d86aeab | 598 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P; |
599 | ||
7f2330d5 | 600 | if (TARGET_ISAC) |
601 | /* No unconditional long branch */; | |
602 | else if (TARGET_PCREL) | |
a1f3c748 | 603 | m68k_symbolic_jump = "bra%.l %c0"; |
dd7218bb | 604 | else |
a1f3c748 | 605 | m68k_symbolic_jump = "bra%.l %p0"; |
dd7218bb | 606 | /* Turn off function cse if we are doing PIC. We always want |
607 | function call to be done as `bsr foo@PLTPC'. */ | |
608 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
609 | clear how intentional that is. */ | |
610 | flag_no_function_cse = 1; | |
611 | } | |
18fce2f0 | 612 | |
1d86aeab | 613 | switch (m68k_symbolic_call_var) |
614 | { | |
615 | case M68K_SYMBOLIC_CALL_JSR: | |
1d86aeab | 616 | m68k_symbolic_call = "jsr %a0"; |
1d86aeab | 617 | break; |
618 | ||
619 | case M68K_SYMBOLIC_CALL_BSR_C: | |
a1f3c748 | 620 | m68k_symbolic_call = "bsr%.l %c0"; |
1d86aeab | 621 | break; |
622 | ||
623 | case M68K_SYMBOLIC_CALL_BSR_P: | |
a1f3c748 | 624 | m68k_symbolic_call = "bsr%.l %p0"; |
1d86aeab | 625 | break; |
626 | ||
627 | case M68K_SYMBOLIC_CALL_NONE: | |
628 | gcc_assert (m68k_symbolic_call == NULL); | |
629 | break; | |
630 | ||
631 | default: | |
632 | gcc_unreachable (); | |
633 | } | |
634 | ||
2e75116d | 635 | #ifndef ASM_OUTPUT_ALIGN_WITH_NOP |
636 | if (align_labels > 2) | |
637 | { | |
638 | warning (0, "-falign-labels=%d is not supported", align_labels); | |
639 | align_labels = 0; | |
640 | } | |
641 | if (align_loops > 2) | |
642 | { | |
643 | warning (0, "-falign-loops=%d is not supported", align_loops); | |
644 | align_loops = 0; | |
645 | } | |
646 | #endif | |
647 | ||
7a8fd205 | 648 | if ((opt_fstack_limit_symbol_arg != NULL || opt_fstack_limit_register_no >= 0) |
649 | && !TARGET_68020) | |
d229c219 | 650 | { |
651 | warning (0, "-fstack-limit- options are not supported on this cpu"); | |
7a8fd205 | 652 | opt_fstack_limit_symbol_arg = NULL; |
653 | opt_fstack_limit_register_no = -1; | |
d229c219 | 654 | } |
655 | ||
18fce2f0 | 656 | SUBTARGET_OVERRIDE_OPTIONS; |
1d86aeab | 657 | |
658 | /* Setup scheduling options. */ | |
2ccdedfd | 659 | if (TUNE_CFV1) |
660 | m68k_sched_cpu = CPU_CFV1; | |
661 | else if (TUNE_CFV2) | |
662 | m68k_sched_cpu = CPU_CFV2; | |
663 | else if (TUNE_CFV3) | |
664 | m68k_sched_cpu = CPU_CFV3; | |
3c904dda | 665 | else if (TUNE_CFV4) |
666 | m68k_sched_cpu = CPU_CFV4; | |
1d86aeab | 667 | else |
668 | { | |
669 | m68k_sched_cpu = CPU_UNKNOWN; | |
670 | flag_schedule_insns = 0; | |
671 | flag_schedule_insns_after_reload = 0; | |
672 | flag_modulo_sched = 0; | |
2bf2188d | 673 | flag_live_range_shrinkage = 0; |
1d86aeab | 674 | } |
2ccdedfd | 675 | |
676 | if (m68k_sched_cpu != CPU_UNKNOWN) | |
677 | { | |
678 | if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0) | |
679 | m68k_sched_mac = MAC_CF_EMAC; | |
680 | else if ((m68k_cpu_flags & FL_CF_MAC) != 0) | |
681 | m68k_sched_mac = MAC_CF_MAC; | |
682 | else | |
683 | m68k_sched_mac = MAC_NO; | |
684 | } | |
d0c0c9ac | 685 | } |
46e5dde5 | 686 | |
c2e7013d | 687 | /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */ |
688 | ||
689 | static void | |
690 | m68k_override_options_after_change (void) | |
691 | { | |
692 | if (m68k_sched_cpu == CPU_UNKNOWN) | |
693 | { | |
694 | flag_schedule_insns = 0; | |
695 | flag_schedule_insns_after_reload = 0; | |
696 | flag_modulo_sched = 0; | |
2bf2188d | 697 | flag_live_range_shrinkage = 0; |
c2e7013d | 698 | } |
699 | } | |
700 | ||
46e5dde5 | 701 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the |
702 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
703 | if -mcpu was not passed. */ | |
704 | ||
705 | const char * | |
706 | m68k_cpp_cpu_ident (const char *prefix) | |
707 | { | |
708 | if (!m68k_cpu_entry) | |
709 | return NULL; | |
710 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
711 | } | |
712 | ||
713 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
714 | given argument and NAME is the name of the representative device for | |
715 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
716 | ||
717 | const char * | |
718 | m68k_cpp_cpu_family (const char *prefix) | |
719 | { | |
720 | if (!m68k_cpu_entry) | |
721 | return NULL; | |
722 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
723 | } | |
5243fbff | 724 | \f |
29968436 | 725 | /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or |
726 | "interrupt_handler" attribute and interrupt_thread if FUNC has an | |
727 | "interrupt_thread" attribute. Otherwise, return | |
728 | m68k_fk_normal_function. */ | |
f9a44575 | 729 | |
730 | enum m68k_function_kind | |
731 | m68k_get_function_kind (tree func) | |
7366b851 | 732 | { |
733 | tree a; | |
734 | ||
e2809c90 | 735 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
736 | ||
29968436 | 737 | a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); |
738 | if (a != NULL_TREE) | |
739 | return m68k_fk_interrupt_handler; | |
740 | ||
7366b851 | 741 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
f9a44575 | 742 | if (a != NULL_TREE) |
743 | return m68k_fk_interrupt_handler; | |
744 | ||
745 | a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func)); | |
746 | if (a != NULL_TREE) | |
747 | return m68k_fk_interrupt_thread; | |
748 | ||
749 | return m68k_fk_normal_function; | |
7366b851 | 750 | } |
751 | ||
752 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
753 | struct attribute_spec.handler. */ | |
754 | static tree | |
755 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
756 | tree args ATTRIBUTE_UNUSED, | |
757 | int flags ATTRIBUTE_UNUSED, | |
758 | bool *no_add_attrs) | |
759 | { | |
760 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
761 | { | |
67a779df | 762 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
763 | name); | |
7366b851 | 764 | *no_add_attrs = true; |
765 | } | |
766 | ||
f9a44575 | 767 | if (m68k_get_function_kind (*node) != m68k_fk_normal_function) |
768 | { | |
769 | error ("multiple interrupt attributes not allowed"); | |
770 | *no_add_attrs = true; | |
771 | } | |
772 | ||
773 | if (!TARGET_FIDOA | |
774 | && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread")) | |
775 | { | |
776 | error ("interrupt_thread is available only on fido"); | |
777 | *no_add_attrs = true; | |
778 | } | |
779 | ||
7366b851 | 780 | return NULL_TREE; |
781 | } | |
2398df48 | 782 | |
783 | static void | |
d02588f4 | 784 | m68k_compute_frame_layout (void) |
2398df48 | 785 | { |
786 | int regno, saved; | |
9c47decb | 787 | unsigned int mask; |
f9a44575 | 788 | enum m68k_function_kind func_kind = |
789 | m68k_get_function_kind (current_function_decl); | |
790 | bool interrupt_handler = func_kind == m68k_fk_interrupt_handler; | |
791 | bool interrupt_thread = func_kind == m68k_fk_interrupt_thread; | |
2398df48 | 792 | |
d02588f4 | 793 | /* Only compute the frame once per function. |
794 | Don't cache information until reload has been completed. */ | |
795 | if (current_frame.funcdef_no == current_function_funcdef_no | |
796 | && reload_completed) | |
797 | return; | |
798 | ||
799 | current_frame.size = (get_frame_size () + 3) & -4; | |
2398df48 | 800 | |
9c47decb | 801 | mask = saved = 0; |
f9a44575 | 802 | |
803 | /* Interrupt thread does not need to save any register. */ | |
804 | if (!interrupt_thread) | |
805 | for (regno = 0; regno < 16; regno++) | |
806 | if (m68k_save_reg (regno, interrupt_handler)) | |
807 | { | |
808 | mask |= 1 << (regno - D0_REG); | |
809 | saved++; | |
810 | } | |
d02588f4 | 811 | current_frame.offset = saved * 4; |
812 | current_frame.reg_no = saved; | |
813 | current_frame.reg_mask = mask; | |
2398df48 | 814 | |
7a3ffbb5 | 815 | current_frame.foffset = 0; |
9c47decb | 816 | mask = saved = 0; |
58c23110 | 817 | if (TARGET_HARD_FLOAT) |
2398df48 | 818 | { |
f9a44575 | 819 | /* Interrupt thread does not need to save any register. */ |
820 | if (!interrupt_thread) | |
821 | for (regno = 16; regno < 24; regno++) | |
822 | if (m68k_save_reg (regno, interrupt_handler)) | |
823 | { | |
824 | mask |= 1 << (regno - FP0_REG); | |
825 | saved++; | |
826 | } | |
58c23110 | 827 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
d02588f4 | 828 | current_frame.offset += current_frame.foffset; |
2398df48 | 829 | } |
7a3ffbb5 | 830 | current_frame.fpu_no = saved; |
831 | current_frame.fpu_mask = mask; | |
d02588f4 | 832 | |
833 | /* Remember what function this frame refers to. */ | |
834 | current_frame.funcdef_no = current_function_funcdef_no; | |
2398df48 | 835 | } |
836 | ||
cd90919d | 837 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
838 | ||
839 | bool | |
840 | m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
841 | { | |
842 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
843 | } | |
844 | ||
2398df48 | 845 | HOST_WIDE_INT |
846 | m68k_initial_elimination_offset (int from, int to) | |
847 | { | |
e905c658 | 848 | int argptr_offset; |
849 | /* The arg pointer points 8 bytes before the start of the arguments, | |
850 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
851 | frame pointer in most frames. */ | |
852 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
2398df48 | 853 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
e905c658 | 854 | return argptr_offset; |
2398df48 | 855 | |
d02588f4 | 856 | m68k_compute_frame_layout (); |
2398df48 | 857 | |
84653e0f | 858 | gcc_assert (to == STACK_POINTER_REGNUM); |
859 | switch (from) | |
860 | { | |
065b42aa | 861 | case ARG_POINTER_REGNUM: |
e905c658 | 862 | return current_frame.offset + current_frame.size - argptr_offset; |
84653e0f | 863 | case FRAME_POINTER_REGNUM: |
864 | return current_frame.offset + current_frame.size; | |
865 | default: | |
866 | gcc_unreachable (); | |
867 | } | |
2398df48 | 868 | } |
869 | ||
274d52cf | 870 | /* Refer to the array `regs_ever_live' to determine which registers |
871 | to save; `regs_ever_live[I]' is nonzero if register number I | |
872 | is ever used in the function. This function is responsible for | |
873 | knowing which registers should not be saved even if used. | |
874 | Return true if we need to save REGNO. */ | |
875 | ||
7366b851 | 876 | static bool |
877 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
0056d78e | 878 | { |
e2182937 | 879 | if (flag_pic && regno == PIC_REG) |
7284415e | 880 | { |
18d50ae6 | 881 | if (crtl->saves_all_registers) |
5e19f315 | 882 | return true; |
18d50ae6 | 883 | if (crtl->uses_pic_offset_table) |
7284415e | 884 | return true; |
d68ee78f | 885 | /* Reload may introduce constant pool references into a function |
886 | that thitherto didn't need a PIC register. Note that the test | |
887 | above will not catch that case because we will only set | |
18d50ae6 | 888 | crtl->uses_pic_offset_table when emitting |
d68ee78f | 889 | the address reloads. */ |
18d50ae6 | 890 | if (crtl->uses_const_pool) |
d68ee78f | 891 | return true; |
7284415e | 892 | } |
0056d78e | 893 | |
18d50ae6 | 894 | if (crtl->calls_eh_return) |
0056d78e | 895 | { |
896 | unsigned int i; | |
897 | for (i = 0; ; i++) | |
898 | { | |
899 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
900 | if (test == INVALID_REGNUM) | |
901 | break; | |
902 | if (test == regno) | |
7366b851 | 903 | return true; |
0056d78e | 904 | } |
905 | } | |
906 | ||
7366b851 | 907 | /* Fixed regs we never touch. */ |
908 | if (fixed_regs[regno]) | |
909 | return false; | |
910 | ||
911 | /* The frame pointer (if it is such) is handled specially. */ | |
912 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
913 | return false; | |
914 | ||
915 | /* Interrupt handlers must also save call_used_regs | |
916 | if they are live or when calling nested functions. */ | |
917 | if (interrupt_handler) | |
065b42aa | 918 | { |
3072d30e | 919 | if (df_regs_ever_live_p (regno)) |
065b42aa | 920 | return true; |
7366b851 | 921 | |
d5bf7b64 | 922 | if (!crtl->is_leaf && call_used_regs[regno]) |
065b42aa | 923 | return true; |
924 | } | |
7366b851 | 925 | |
926 | /* Never need to save registers that aren't touched. */ | |
3072d30e | 927 | if (!df_regs_ever_live_p (regno)) |
7366b851 | 928 | return false; |
929 | ||
a58c6df6 | 930 | /* Otherwise save everything that isn't call-clobbered. */ |
7366b851 | 931 | return !call_used_regs[regno]; |
0056d78e | 932 | } |
933 | ||
9c47decb | 934 | /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents |
935 | the lowest memory address. COUNT is the number of registers to be | |
936 | moved, with register REGNO + I being moved if bit I of MASK is set. | |
937 | STORE_P specifies the direction of the move and ADJUST_STACK_P says | |
938 | whether or not this is pre-decrement (if STORE_P) or post-increment | |
939 | (if !STORE_P) operation. */ | |
940 | ||
9e9d6337 | 941 | static rtx_insn * |
9c47decb | 942 | m68k_emit_movem (rtx base, HOST_WIDE_INT offset, |
943 | unsigned int count, unsigned int regno, | |
944 | unsigned int mask, bool store_p, bool adjust_stack_p) | |
945 | { | |
946 | int i; | |
947 | rtx body, addr, src, operands[2]; | |
3754d046 | 948 | machine_mode mode; |
9c47decb | 949 | |
950 | body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); | |
951 | mode = reg_raw_mode[regno]; | |
952 | i = 0; | |
953 | ||
954 | if (adjust_stack_p) | |
955 | { | |
29c05e22 | 956 | src = plus_constant (Pmode, base, |
957 | (count | |
958 | * GET_MODE_SIZE (mode) | |
959 | * (HOST_WIDE_INT) (store_p ? -1 : 1))); | |
d1f9b275 | 960 | XVECEXP (body, 0, i++) = gen_rtx_SET (base, src); |
9c47decb | 961 | } |
962 | ||
963 | for (; mask != 0; mask >>= 1, regno++) | |
964 | if (mask & 1) | |
965 | { | |
29c05e22 | 966 | addr = plus_constant (Pmode, base, offset); |
9c47decb | 967 | operands[!store_p] = gen_frame_mem (mode, addr); |
968 | operands[store_p] = gen_rtx_REG (mode, regno); | |
969 | XVECEXP (body, 0, i++) | |
d1f9b275 | 970 | = gen_rtx_SET (operands[0], operands[1]); |
9c47decb | 971 | offset += GET_MODE_SIZE (mode); |
972 | } | |
973 | gcc_assert (i == XVECLEN (body, 0)); | |
974 | ||
975 | return emit_insn (body); | |
976 | } | |
977 | ||
978 | /* Make INSN a frame-related instruction. */ | |
5243fbff | 979 | |
17d9b0c3 | 980 | static void |
9e9d6337 | 981 | m68k_set_frame_related (rtx_insn *insn) |
9c47decb | 982 | { |
983 | rtx body; | |
984 | int i; | |
985 | ||
986 | RTX_FRAME_RELATED_P (insn) = 1; | |
987 | body = PATTERN (insn); | |
988 | if (GET_CODE (body) == PARALLEL) | |
989 | for (i = 0; i < XVECLEN (body, 0); i++) | |
990 | RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; | |
991 | } | |
992 | ||
993 | /* Emit RTL for the "prologue" define_expand. */ | |
994 | ||
995 | void | |
996 | m68k_expand_prologue (void) | |
5243fbff | 997 | { |
2398df48 | 998 | HOST_WIDE_INT fsize_with_regs; |
e26cf4d4 | 999 | rtx limit, src, dest; |
d02588f4 | 1000 | |
9c47decb | 1001 | m68k_compute_frame_layout (); |
d02588f4 | 1002 | |
8c0dd614 | 1003 | if (flag_stack_usage_info) |
611b3016 | 1004 | current_function_static_stack_size |
1005 | = current_frame.size + current_frame.offset; | |
1006 | ||
8f8ac140 | 1007 | /* If the stack limit is a symbol, we can check it here, |
1008 | before actually allocating the space. */ | |
18d50ae6 | 1009 | if (crtl->limit_stack |
8f8ac140 | 1010 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) |
9c47decb | 1011 | { |
29c05e22 | 1012 | limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4); |
ca316360 | 1013 | if (!m68k_legitimate_constant_p (Pmode, limit)) |
9c47decb | 1014 | { |
1015 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); | |
1016 | limit = gen_rtx_REG (Pmode, D0_REG); | |
1017 | } | |
74f4459c | 1018 | emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, |
1019 | stack_pointer_rtx, limit), | |
1020 | stack_pointer_rtx, limit, | |
1021 | const1_rtx)); | |
9c47decb | 1022 | } |
5243fbff | 1023 | |
09445e53 | 1024 | fsize_with_regs = current_frame.size; |
58c23110 | 1025 | if (TARGET_COLDFIRE) |
1026 | { | |
9c47decb | 1027 | /* ColdFire's move multiple instructions do not allow pre-decrement |
1028 | addressing. Add the size of movem saves to the initial stack | |
1029 | allocation instead. */ | |
1030 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1031 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1032 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1033 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
58c23110 | 1034 | } |
2398df48 | 1035 | |
5243fbff | 1036 | if (frame_pointer_needed) |
1037 | { | |
9c47decb | 1038 | if (fsize_with_regs == 0 && TUNE_68040) |
5243fbff | 1039 | { |
9c47decb | 1040 | /* On the 68040, two separate moves are faster than link.w 0. */ |
1041 | dest = gen_frame_mem (Pmode, | |
1042 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1043 | m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); | |
1044 | m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, | |
1045 | stack_pointer_rtx)); | |
5243fbff | 1046 | } |
9c47decb | 1047 | else if (fsize_with_regs < 0x8000 || TARGET_68020) |
1048 | m68k_set_frame_related | |
1049 | (emit_insn (gen_link (frame_pointer_rtx, | |
1050 | GEN_INT (-4 - fsize_with_regs)))); | |
54576bcb | 1051 | else |
9c47decb | 1052 | { |
1053 | m68k_set_frame_related | |
1054 | (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); | |
1055 | m68k_set_frame_related | |
1056 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1057 | stack_pointer_rtx, | |
1058 | GEN_INT (-fsize_with_regs)))); | |
1059 | } | |
3c904dda | 1060 | |
1061 | /* If the frame pointer is needed, emit a special barrier that | |
1062 | will prevent the scheduler from moving stores to the frame | |
1063 | before the stack adjustment. */ | |
1064 | emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx)); | |
54576bcb | 1065 | } |
9c47decb | 1066 | else if (fsize_with_regs != 0) |
1067 | m68k_set_frame_related | |
1068 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1069 | stack_pointer_rtx, | |
1070 | GEN_INT (-fsize_with_regs)))); | |
2398df48 | 1071 | |
7a3ffbb5 | 1072 | if (current_frame.fpu_mask) |
5243fbff | 1073 | { |
9c47decb | 1074 | gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); |
58c23110 | 1075 | if (TARGET_68881) |
9c47decb | 1076 | m68k_set_frame_related |
1077 | (m68k_emit_movem (stack_pointer_rtx, | |
1078 | current_frame.fpu_no * -GET_MODE_SIZE (XFmode), | |
1079 | current_frame.fpu_no, FP0_REG, | |
1080 | current_frame.fpu_mask, true, true)); | |
58c23110 | 1081 | else |
1082 | { | |
1083 | int offset; | |
1084 | ||
9c47decb | 1085 | /* If we're using moveml to save the integer registers, |
1086 | the stack pointer will point to the bottom of the moveml | |
1087 | save area. Find the stack offset of the first FP register. */ | |
1088 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
58c23110 | 1089 | offset = 0; |
1090 | else | |
9c47decb | 1091 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1092 | m68k_set_frame_related | |
1093 | (m68k_emit_movem (stack_pointer_rtx, offset, | |
1094 | current_frame.fpu_no, FP0_REG, | |
1095 | current_frame.fpu_mask, true, false)); | |
7fcf3afe | 1096 | } |
5243fbff | 1097 | } |
376273c1 | 1098 | |
16b4cb0d | 1099 | /* If the stack limit is not a symbol, check it here. |
8f8ac140 | 1100 | This has the disadvantage that it may be too late... */ |
18d50ae6 | 1101 | if (crtl->limit_stack) |
8f8ac140 | 1102 | { |
1103 | if (REG_P (stack_limit_rtx)) | |
74f4459c | 1104 | emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx, |
1105 | stack_limit_rtx), | |
1106 | stack_pointer_rtx, stack_limit_rtx, | |
1107 | const1_rtx)); | |
1108 | ||
8f8ac140 | 1109 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
c3ceba8e | 1110 | warning (0, "stack limit expression is not supported"); |
8f8ac140 | 1111 | } |
16b4cb0d | 1112 | |
9c47decb | 1113 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
5243fbff | 1114 | { |
9c47decb | 1115 | /* Store each register separately in the same order moveml does. */ |
5243fbff | 1116 | int i; |
1117 | ||
9c47decb | 1118 | for (i = 16; i-- > 0; ) |
1119 | if (current_frame.reg_mask & (1 << i)) | |
357cfda2 | 1120 | { |
9c47decb | 1121 | src = gen_rtx_REG (SImode, D0_REG + i); |
1122 | dest = gen_frame_mem (SImode, | |
1123 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1124 | m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); | |
357cfda2 | 1125 | } |
5243fbff | 1126 | } |
9c47decb | 1127 | else |
5243fbff | 1128 | { |
960e6739 | 1129 | if (TARGET_COLDFIRE) |
9c47decb | 1130 | /* The required register save space has already been allocated. |
1131 | The first register should be stored at (%sp). */ | |
1132 | m68k_set_frame_related | |
1133 | (m68k_emit_movem (stack_pointer_rtx, 0, | |
1134 | current_frame.reg_no, D0_REG, | |
1135 | current_frame.reg_mask, true, false)); | |
3524a08d | 1136 | else |
9c47decb | 1137 | m68k_set_frame_related |
1138 | (m68k_emit_movem (stack_pointer_rtx, | |
1139 | current_frame.reg_no * -GET_MODE_SIZE (SImode), | |
1140 | current_frame.reg_no, D0_REG, | |
1141 | current_frame.reg_mask, true, true)); | |
5243fbff | 1142 | } |
9c47decb | 1143 | |
869bde6b | 1144 | if (!TARGET_SEP_DATA |
18d50ae6 | 1145 | && crtl->uses_pic_offset_table) |
e26cf4d4 | 1146 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
5243fbff | 1147 | } |
1148 | \f | |
6571ac6e | 1149 | /* Return true if a simple (return) instruction is sufficient for this |
1150 | instruction (i.e. if no epilogue is needed). */ | |
5243fbff | 1151 | |
d02588f4 | 1152 | bool |
b38bcc54 | 1153 | m68k_use_return_insn (void) |
5243fbff | 1154 | { |
5243fbff | 1155 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
d02588f4 | 1156 | return false; |
1a2c33ec | 1157 | |
065b42aa | 1158 | m68k_compute_frame_layout (); |
6571ac6e | 1159 | return current_frame.offset == 0; |
5243fbff | 1160 | } |
1161 | ||
33fb08b8 | 1162 | /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; |
1163 | SIBCALL_P says which. | |
5243fbff | 1164 | |
1165 | The function epilogue should not depend on the current stack pointer! | |
1166 | It should use the frame pointer only, if there is a frame pointer. | |
1167 | This is mandatory because of alloca; we also take advantage of it to | |
1168 | omit stack adjustments before returning. */ | |
1169 | ||
9c47decb | 1170 | void |
33fb08b8 | 1171 | m68k_expand_epilogue (bool sibcall_p) |
17d9b0c3 | 1172 | { |
d02588f4 | 1173 | HOST_WIDE_INT fsize, fsize_with_regs; |
9c47decb | 1174 | bool big, restore_from_sp; |
d02588f4 | 1175 | |
065b42aa | 1176 | m68k_compute_frame_layout (); |
d02588f4 | 1177 | |
d02588f4 | 1178 | fsize = current_frame.size; |
9c47decb | 1179 | big = false; |
1180 | restore_from_sp = false; | |
d02588f4 | 1181 | |
d5bf7b64 | 1182 | /* FIXME : crtl->is_leaf below is too strong. |
e4cbd171 | 1183 | What we really need to know there is if there could be pending |
0c0492c9 | 1184 | stack adjustment needed at that point. */ |
9c47decb | 1185 | restore_from_sp = (!frame_pointer_needed |
d5bf7b64 | 1186 | || (!cfun->calls_alloca && crtl->is_leaf)); |
2398df48 | 1187 | |
1188 | /* fsize_with_regs is the size we need to adjust the sp when | |
274d52cf | 1189 | popping the frame. */ |
2398df48 | 1190 | fsize_with_regs = fsize; |
58c23110 | 1191 | if (TARGET_COLDFIRE && restore_from_sp) |
1192 | { | |
9c47decb | 1193 | /* ColdFire's move multiple instructions do not allow post-increment |
1194 | addressing. Add the size of movem loads to the final deallocation | |
1195 | instead. */ | |
1196 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1197 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1198 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1199 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
58c23110 | 1200 | } |
2398df48 | 1201 | |
d02588f4 | 1202 | if (current_frame.offset + fsize >= 0x8000 |
9c47decb | 1203 | && !restore_from_sp |
d02588f4 | 1204 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
5243fbff | 1205 | { |
9c47decb | 1206 | if (TARGET_COLDFIRE |
1207 | && (current_frame.reg_no >= MIN_MOVEM_REGS | |
1208 | || current_frame.fpu_no >= MIN_FMOVEM_REGS)) | |
1209 | { | |
1210 | /* ColdFire's move multiple instructions do not support the | |
1211 | (d8,Ax,Xi) addressing mode, so we're as well using a normal | |
1212 | stack-based restore. */ | |
1213 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), | |
1214 | GEN_INT (-(current_frame.offset + fsize))); | |
bf04fa3c | 1215 | emit_insn (gen_blockage ()); |
9c47decb | 1216 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1217 | gen_rtx_REG (Pmode, A1_REG), | |
1218 | frame_pointer_rtx)); | |
1219 | restore_from_sp = true; | |
1220 | } | |
1221 | else | |
1222 | { | |
1223 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); | |
1224 | fsize = 0; | |
1225 | big = true; | |
1226 | } | |
5243fbff | 1227 | } |
5243fbff | 1228 | |
9c47decb | 1229 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
1230 | { | |
1231 | /* Restore each register separately in the same order moveml does. */ | |
5243fbff | 1232 | int i; |
9c47decb | 1233 | HOST_WIDE_INT offset; |
5243fbff | 1234 | |
9c47decb | 1235 | offset = current_frame.offset + fsize; |
d02588f4 | 1236 | for (i = 0; i < 16; i++) |
1237 | if (current_frame.reg_mask & (1 << i)) | |
5243fbff | 1238 | { |
9c47decb | 1239 | rtx addr; |
1240 | ||
1241 | if (big) | |
5243fbff | 1242 | { |
9c47decb | 1243 | /* Generate the address -OFFSET(%fp,%a1.l). */ |
1244 | addr = gen_rtx_REG (Pmode, A1_REG); | |
1245 | addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); | |
29c05e22 | 1246 | addr = plus_constant (Pmode, addr, -offset); |
5243fbff | 1247 | } |
9c47decb | 1248 | else if (restore_from_sp) |
1249 | addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
1250 | else | |
29c05e22 | 1251 | addr = plus_constant (Pmode, frame_pointer_rtx, -offset); |
9c47decb | 1252 | emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), |
1253 | gen_frame_mem (SImode, addr)); | |
1254 | offset -= GET_MODE_SIZE (SImode); | |
1255 | } | |
5243fbff | 1256 | } |
d02588f4 | 1257 | else if (current_frame.reg_mask) |
5243fbff | 1258 | { |
9c47decb | 1259 | if (big) |
1260 | m68k_emit_movem (gen_rtx_PLUS (Pmode, | |
1261 | gen_rtx_REG (Pmode, A1_REG), | |
1262 | frame_pointer_rtx), | |
1263 | -(current_frame.offset + fsize), | |
1264 | current_frame.reg_no, D0_REG, | |
1265 | current_frame.reg_mask, false, false); | |
1266 | else if (restore_from_sp) | |
1267 | m68k_emit_movem (stack_pointer_rtx, 0, | |
1268 | current_frame.reg_no, D0_REG, | |
1269 | current_frame.reg_mask, false, | |
1270 | !TARGET_COLDFIRE); | |
1271 | else | |
1272 | m68k_emit_movem (frame_pointer_rtx, | |
1273 | -(current_frame.offset + fsize), | |
1274 | current_frame.reg_no, D0_REG, | |
1275 | current_frame.reg_mask, false, false); | |
5243fbff | 1276 | } |
9c47decb | 1277 | |
1278 | if (current_frame.fpu_no > 0) | |
5243fbff | 1279 | { |
1280 | if (big) | |
9c47decb | 1281 | m68k_emit_movem (gen_rtx_PLUS (Pmode, |
1282 | gen_rtx_REG (Pmode, A1_REG), | |
1283 | frame_pointer_rtx), | |
1284 | -(current_frame.foffset + fsize), | |
1285 | current_frame.fpu_no, FP0_REG, | |
1286 | current_frame.fpu_mask, false, false); | |
e4cd7d76 | 1287 | else if (restore_from_sp) |
5243fbff | 1288 | { |
58c23110 | 1289 | if (TARGET_COLDFIRE) |
1290 | { | |
1291 | int offset; | |
1292 | ||
9c47decb | 1293 | /* If we used moveml to restore the integer registers, the |
1294 | stack pointer will still point to the bottom of the moveml | |
1295 | save area. Find the stack offset of the first FP | |
1296 | register. */ | |
1297 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
58c23110 | 1298 | offset = 0; |
1299 | else | |
9c47decb | 1300 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1301 | m68k_emit_movem (stack_pointer_rtx, offset, | |
1302 | current_frame.fpu_no, FP0_REG, | |
1303 | current_frame.fpu_mask, false, false); | |
58c23110 | 1304 | } |
ef2ee7d3 | 1305 | else |
9c47decb | 1306 | m68k_emit_movem (stack_pointer_rtx, 0, |
1307 | current_frame.fpu_no, FP0_REG, | |
1308 | current_frame.fpu_mask, false, true); | |
5243fbff | 1309 | } |
1310 | else | |
9c47decb | 1311 | m68k_emit_movem (frame_pointer_rtx, |
1312 | -(current_frame.foffset + fsize), | |
1313 | current_frame.fpu_no, FP0_REG, | |
1314 | current_frame.fpu_mask, false, false); | |
5243fbff | 1315 | } |
9c47decb | 1316 | |
bf04fa3c | 1317 | emit_insn (gen_blockage ()); |
5243fbff | 1318 | if (frame_pointer_needed) |
9c47decb | 1319 | emit_insn (gen_unlink (frame_pointer_rtx)); |
2398df48 | 1320 | else if (fsize_with_regs) |
9c47decb | 1321 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1322 | stack_pointer_rtx, | |
1323 | GEN_INT (fsize_with_regs))); | |
1324 | ||
18d50ae6 | 1325 | if (crtl->calls_eh_return) |
9c47decb | 1326 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1327 | stack_pointer_rtx, | |
1328 | EH_RETURN_STACKADJ_RTX)); | |
1329 | ||
33fb08b8 | 1330 | if (!sibcall_p) |
1a860023 | 1331 | emit_jump_insn (ret_rtx); |
5243fbff | 1332 | } |
1333 | \f | |
821960c7 | 1334 | /* Return true if X is a valid comparison operator for the dbcc |
61405c07 | 1335 | instruction. |
1336 | ||
1337 | Note it rejects floating point comparison operators. | |
1338 | (In the future we could use Fdbcc). | |
1339 | ||
1340 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1341 | ||
1342 | int | |
3754d046 | 1343 | valid_dbcc_comparison_p_2 (rtx x, machine_mode mode ATTRIBUTE_UNUSED) |
61405c07 | 1344 | { |
61405c07 | 1345 | switch (GET_CODE (x)) |
1346 | { | |
61405c07 | 1347 | case EQ: case NE: case GTU: case LTU: |
1348 | case GEU: case LEU: | |
1349 | return 1; | |
1350 | ||
1351 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1352 | conservative */ | |
1353 | case GT: case LT: case GE: case LE: | |
1354 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1355 | default: | |
1356 | return 0; | |
1357 | } | |
1358 | } | |
1359 | ||
e911aedf | 1360 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
07bd8c0d | 1361 | int |
821960c7 | 1362 | flags_in_68881 (void) |
07bd8c0d | 1363 | { |
1364 | /* We could add support for these in the future */ | |
1365 | return cc_status.flags & CC_IN_68881; | |
1366 | } | |
1367 | ||
d09fd72c | 1368 | /* Return true if PARALLEL contains register REGNO. */ |
1369 | static bool | |
1370 | m68k_reg_present_p (const_rtx parallel, unsigned int regno) | |
1371 | { | |
1372 | int i; | |
1373 | ||
1374 | if (REG_P (parallel) && REGNO (parallel) == regno) | |
1375 | return true; | |
1376 | ||
1377 | if (GET_CODE (parallel) != PARALLEL) | |
1378 | return false; | |
1379 | ||
1380 | for (i = 0; i < XVECLEN (parallel, 0); ++i) | |
1381 | { | |
1382 | const_rtx x; | |
1383 | ||
1384 | x = XEXP (XVECEXP (parallel, 0, i), 0); | |
1385 | if (REG_P (x) && REGNO (x) == regno) | |
1386 | return true; | |
1387 | } | |
1388 | ||
1389 | return false; | |
1390 | } | |
1391 | ||
e2809c90 | 1392 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */ |
33fb08b8 | 1393 | |
1394 | static bool | |
e2809c90 | 1395 | m68k_ok_for_sibcall_p (tree decl, tree exp) |
33fb08b8 | 1396 | { |
e2809c90 | 1397 | enum m68k_function_kind kind; |
1398 | ||
1399 | /* We cannot use sibcalls for nested functions because we use the | |
1400 | static chain register for indirect calls. */ | |
1401 | if (CALL_EXPR_STATIC_CHAIN (exp)) | |
1402 | return false; | |
1403 | ||
d09fd72c | 1404 | if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) |
1405 | { | |
1406 | /* Check that the return value locations are the same. For | |
1407 | example that we aren't returning a value from the sibling in | |
1408 | a D0 register but then need to transfer it to a A0 register. */ | |
1409 | rtx cfun_value; | |
1410 | rtx call_value; | |
1411 | ||
1412 | cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)), | |
1413 | cfun->decl); | |
1414 | call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl); | |
1415 | ||
1416 | /* Check that the values are equal or that the result the callee | |
1417 | function returns is superset of what the current function returns. */ | |
1418 | if (!(rtx_equal_p (cfun_value, call_value) | |
1419 | || (REG_P (cfun_value) | |
1420 | && m68k_reg_present_p (call_value, REGNO (cfun_value))))) | |
1421 | return false; | |
1422 | } | |
1423 | ||
e2809c90 | 1424 | kind = m68k_get_function_kind (current_function_decl); |
1425 | if (kind == m68k_fk_normal_function) | |
1426 | /* We can always sibcall from a normal function, because it's | |
1427 | undefined if it is calling an interrupt function. */ | |
1428 | return true; | |
1429 | ||
1430 | /* Otherwise we can only sibcall if the function kind is known to be | |
1431 | the same. */ | |
1432 | if (decl && m68k_get_function_kind (decl) == kind) | |
1433 | return true; | |
1434 | ||
1435 | return false; | |
33fb08b8 | 1436 | } |
1437 | ||
385c19d1 | 1438 | /* On the m68k all args are always pushed. */ |
1439 | ||
1440 | static rtx | |
39cba157 | 1441 | m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, |
3754d046 | 1442 | machine_mode mode ATTRIBUTE_UNUSED, |
385c19d1 | 1443 | const_tree type ATTRIBUTE_UNUSED, |
1444 | bool named ATTRIBUTE_UNUSED) | |
1445 | { | |
1446 | return NULL_RTX; | |
1447 | } | |
1448 | ||
1449 | static void | |
3754d046 | 1450 | m68k_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
385c19d1 | 1451 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1452 | { | |
39cba157 | 1453 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1454 | ||
385c19d1 | 1455 | *cum += (mode != BLKmode |
1456 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1457 | : (int_size_in_bytes (type) + 3) & ~3); | |
1458 | } | |
1459 | ||
dd7218bb | 1460 | /* Convert X to a legitimate function call memory reference and return the |
1461 | result. */ | |
b09faf5c | 1462 | |
dd7218bb | 1463 | rtx |
1464 | m68k_legitimize_call_address (rtx x) | |
1465 | { | |
1466 | gcc_assert (MEM_P (x)); | |
1467 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1468 | return x; | |
1469 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
b09faf5c | 1470 | } |
1471 | ||
33fb08b8 | 1472 | /* Likewise for sibling calls. */ |
1473 | ||
1474 | rtx | |
1475 | m68k_legitimize_sibcall_address (rtx x) | |
1476 | { | |
1477 | gcc_assert (MEM_P (x)); | |
1478 | if (sibcall_operand (XEXP (x, 0), VOIDmode)) | |
1479 | return x; | |
1480 | ||
1481 | emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); | |
1482 | return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); | |
1483 | } | |
1484 | ||
41e3a0c7 | 1485 | /* Convert X to a legitimate address and return it if successful. Otherwise |
1486 | return X. | |
1487 | ||
1488 | For the 68000, we handle X+REG by loading X into a register R and | |
1489 | using R+REG. R will go in an address reg and indexing will be used. | |
1490 | However, if REG is a broken-out memory address or multiplication, | |
1491 | nothing needs to be done because REG can certainly go in an address reg. */ | |
1492 | ||
2a381450 | 1493 | static rtx |
3754d046 | 1494 | m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode) |
41e3a0c7 | 1495 | { |
869bde6b | 1496 | if (m68k_tls_symbol_p (x)) |
1497 | return m68k_legitimize_tls_address (x); | |
1498 | ||
41e3a0c7 | 1499 | if (GET_CODE (x) == PLUS) |
1500 | { | |
1501 | int ch = (x) != (oldx); | |
1502 | int copied = 0; | |
1503 | ||
1504 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } | |
1505 | ||
1506 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
1507 | { | |
1508 | COPY_ONCE (x); | |
1509 | XEXP (x, 0) = force_operand (XEXP (x, 0), 0); | |
1510 | } | |
1511 | if (GET_CODE (XEXP (x, 1)) == MULT) | |
1512 | { | |
1513 | COPY_ONCE (x); | |
1514 | XEXP (x, 1) = force_operand (XEXP (x, 1), 0); | |
1515 | } | |
1516 | if (ch) | |
1517 | { | |
1518 | if (GET_CODE (XEXP (x, 1)) == REG | |
1519 | && GET_CODE (XEXP (x, 0)) == REG) | |
1520 | { | |
1521 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1522 | { | |
1523 | COPY_ONCE (x); | |
1524 | x = force_operand (x, 0); | |
1525 | } | |
1526 | return x; | |
1527 | } | |
1528 | if (memory_address_p (mode, x)) | |
1529 | return x; | |
1530 | } | |
1531 | if (GET_CODE (XEXP (x, 0)) == REG | |
1532 | || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
1533 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1534 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)) | |
1535 | { | |
1536 | rtx temp = gen_reg_rtx (Pmode); | |
1537 | rtx val = force_operand (XEXP (x, 1), 0); | |
1538 | emit_move_insn (temp, val); | |
1539 | COPY_ONCE (x); | |
1540 | XEXP (x, 1) = temp; | |
1541 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1542 | && GET_CODE (XEXP (x, 0)) == REG) | |
1543 | x = force_operand (x, 0); | |
1544 | } | |
1545 | else if (GET_CODE (XEXP (x, 1)) == REG | |
1546 | || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND | |
1547 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
1548 | && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode)) | |
1549 | { | |
1550 | rtx temp = gen_reg_rtx (Pmode); | |
1551 | rtx val = force_operand (XEXP (x, 0), 0); | |
1552 | emit_move_insn (temp, val); | |
1553 | COPY_ONCE (x); | |
1554 | XEXP (x, 0) = temp; | |
1555 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1556 | && GET_CODE (XEXP (x, 1)) == REG) | |
1557 | x = force_operand (x, 0); | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | return x; | |
1562 | } | |
1563 | ||
1564 | ||
61405c07 | 1565 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1566 | floating point version of this sequence (Fdbcc). We also | |
1567 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
07bd8c0d | 1568 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1569 | kick those out before we get here. */ | |
61405c07 | 1570 | |
e6b2f841 | 1571 | void |
821960c7 | 1572 | output_dbcc_and_branch (rtx *operands) |
61405c07 | 1573 | { |
61405c07 | 1574 | switch (GET_CODE (operands[3])) |
1575 | { | |
1576 | case EQ: | |
a1f3c748 | 1577 | output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); |
9cbcee62 | 1578 | break; |
61405c07 | 1579 | |
1580 | case NE: | |
a1f3c748 | 1581 | output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); |
9cbcee62 | 1582 | break; |
61405c07 | 1583 | |
1584 | case GT: | |
a1f3c748 | 1585 | output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); |
9cbcee62 | 1586 | break; |
61405c07 | 1587 | |
1588 | case GTU: | |
a1f3c748 | 1589 | output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); |
9cbcee62 | 1590 | break; |
61405c07 | 1591 | |
1592 | case LT: | |
a1f3c748 | 1593 | output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); |
9cbcee62 | 1594 | break; |
61405c07 | 1595 | |
1596 | case LTU: | |
a1f3c748 | 1597 | output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); |
9cbcee62 | 1598 | break; |
61405c07 | 1599 | |
1600 | case GE: | |
a1f3c748 | 1601 | output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); |
9cbcee62 | 1602 | break; |
61405c07 | 1603 | |
1604 | case GEU: | |
a1f3c748 | 1605 | output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); |
9cbcee62 | 1606 | break; |
61405c07 | 1607 | |
1608 | case LE: | |
a1f3c748 | 1609 | output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); |
9cbcee62 | 1610 | break; |
61405c07 | 1611 | |
1612 | case LEU: | |
a1f3c748 | 1613 | output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); |
9cbcee62 | 1614 | break; |
61405c07 | 1615 | |
1616 | default: | |
84653e0f | 1617 | gcc_unreachable (); |
61405c07 | 1618 | } |
1619 | ||
1620 | /* If the decrement is to be done in SImode, then we have | |
0c0492c9 | 1621 | to compensate for the fact that dbcc decrements in HImode. */ |
61405c07 | 1622 | switch (GET_MODE (operands[0])) |
1623 | { | |
1624 | case SImode: | |
a1f3c748 | 1625 | output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands); |
61405c07 | 1626 | break; |
1627 | ||
1628 | case HImode: | |
1629 | break; | |
1630 | ||
1631 | default: | |
84653e0f | 1632 | gcc_unreachable (); |
61405c07 | 1633 | } |
1634 | } | |
1635 | ||
f2fa409d | 1636 | const char * |
84653e0f | 1637 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
3b8c85f3 | 1638 | { |
1639 | rtx loperands[7]; | |
c46628b1 | 1640 | enum rtx_code op_code = GET_CODE (op); |
3b8c85f3 | 1641 | |
8ef587dc | 1642 | /* This does not produce a useful cc. */ |
acef5d85 | 1643 | CC_STATUS_INIT; |
1644 | ||
c46628b1 | 1645 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1646 | below. Swap the operands and change the op if these requirements | |
1647 | are not fulfilled. */ | |
1648 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1649 | { | |
1650 | rtx tmp = operand1; | |
1651 | ||
1652 | operand1 = operand2; | |
1653 | operand2 = tmp; | |
1654 | op_code = swap_condition (op_code); | |
1655 | } | |
3b8c85f3 | 1656 | loperands[0] = operand1; |
1657 | if (GET_CODE (operand1) == REG) | |
e6b2f841 | 1658 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
3b8c85f3 | 1659 | else |
eafc6604 | 1660 | loperands[1] = adjust_address (operand1, SImode, 4); |
3b8c85f3 | 1661 | if (operand2 != const0_rtx) |
1662 | { | |
1663 | loperands[2] = operand2; | |
1664 | if (GET_CODE (operand2) == REG) | |
e6b2f841 | 1665 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
3b8c85f3 | 1666 | else |
eafc6604 | 1667 | loperands[3] = adjust_address (operand2, SImode, 4); |
3b8c85f3 | 1668 | } |
f5f2db69 | 1669 | loperands[4] = gen_label_rtx (); |
3b8c85f3 | 1670 | if (operand2 != const0_rtx) |
a1f3c748 | 1671 | output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands); |
f28a9fad | 1672 | else |
8ae4b10a | 1673 | { |
960e6739 | 1674 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
8ae4b10a | 1675 | output_asm_insn ("tst%.l %0", loperands); |
1676 | else | |
065b42aa | 1677 | output_asm_insn ("cmp%.w #0,%0", loperands); |
8ae4b10a | 1678 | |
a1f3c748 | 1679 | output_asm_insn ("jne %l4", loperands); |
8ae4b10a | 1680 | |
960e6739 | 1681 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
8ae4b10a | 1682 | output_asm_insn ("tst%.l %1", loperands); |
1683 | else | |
3acc77d9 | 1684 | output_asm_insn ("cmp%.w #0,%1", loperands); |
8ae4b10a | 1685 | } |
1686 | ||
3b8c85f3 | 1687 | loperands[5] = dest; |
3acc77d9 | 1688 | |
c46628b1 | 1689 | switch (op_code) |
3b8c85f3 | 1690 | { |
1691 | case EQ: | |
805e22b2 | 1692 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1693 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1694 | output_asm_insn ("seq %5", loperands); |
1695 | break; | |
1696 | ||
1697 | case NE: | |
805e22b2 | 1698 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1699 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1700 | output_asm_insn ("sne %5", loperands); |
1701 | break; | |
1702 | ||
1703 | case GT: | |
f5f2db69 | 1704 | loperands[6] = gen_label_rtx (); |
a1f3c748 | 1705 | output_asm_insn ("shi %5\n\tjra %l6", loperands); |
805e22b2 | 1706 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1707 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1708 | output_asm_insn ("sgt %5", loperands); |
805e22b2 | 1709 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1710 | CODE_LABEL_NUMBER (loperands[6])); |
3b8c85f3 | 1711 | break; |
1712 | ||
1713 | case GTU: | |
805e22b2 | 1714 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1715 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1716 | output_asm_insn ("shi %5", loperands); |
1717 | break; | |
1718 | ||
1719 | case LT: | |
f5f2db69 | 1720 | loperands[6] = gen_label_rtx (); |
a1f3c748 | 1721 | output_asm_insn ("scs %5\n\tjra %l6", loperands); |
805e22b2 | 1722 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1723 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1724 | output_asm_insn ("slt %5", loperands); |
805e22b2 | 1725 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1726 | CODE_LABEL_NUMBER (loperands[6])); |
3b8c85f3 | 1727 | break; |
1728 | ||
1729 | case LTU: | |
805e22b2 | 1730 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1731 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1732 | output_asm_insn ("scs %5", loperands); |
1733 | break; | |
1734 | ||
1735 | case GE: | |
f5f2db69 | 1736 | loperands[6] = gen_label_rtx (); |
a1f3c748 | 1737 | output_asm_insn ("scc %5\n\tjra %l6", loperands); |
805e22b2 | 1738 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1739 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1740 | output_asm_insn ("sge %5", loperands); |
805e22b2 | 1741 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1742 | CODE_LABEL_NUMBER (loperands[6])); |
3b8c85f3 | 1743 | break; |
1744 | ||
1745 | case GEU: | |
805e22b2 | 1746 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1747 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1748 | output_asm_insn ("scc %5", loperands); |
1749 | break; | |
1750 | ||
1751 | case LE: | |
f5f2db69 | 1752 | loperands[6] = gen_label_rtx (); |
a1f3c748 | 1753 | output_asm_insn ("sls %5\n\tjra %l6", loperands); |
805e22b2 | 1754 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1755 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1756 | output_asm_insn ("sle %5", loperands); |
805e22b2 | 1757 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1758 | CODE_LABEL_NUMBER (loperands[6])); |
3b8c85f3 | 1759 | break; |
1760 | ||
1761 | case LEU: | |
805e22b2 | 1762 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
065b42aa | 1763 | CODE_LABEL_NUMBER (loperands[4])); |
3b8c85f3 | 1764 | output_asm_insn ("sls %5", loperands); |
1765 | break; | |
1766 | ||
1767 | default: | |
84653e0f | 1768 | gcc_unreachable (); |
3b8c85f3 | 1769 | } |
1770 | return ""; | |
1771 | } | |
1772 | ||
f2fa409d | 1773 | const char * |
9e9d6337 | 1774 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos) |
5243fbff | 1775 | { |
1776 | operands[0] = countop; | |
1777 | operands[1] = dataop; | |
1778 | ||
1779 | if (GET_CODE (countop) == CONST_INT) | |
1780 | { | |
1781 | register int count = INTVAL (countop); | |
1782 | /* If COUNT is bigger than size of storage unit in use, | |
1783 | advance to the containing unit of same size. */ | |
1784 | if (count > signpos) | |
1785 | { | |
1786 | int offset = (count & ~signpos) / 8; | |
1787 | count = count & signpos; | |
eafc6604 | 1788 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
5243fbff | 1789 | } |
1790 | if (count == signpos) | |
1791 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1792 | else | |
1793 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1794 | ||
1795 | /* These three statements used to use next_insns_test_no... | |
1796 | but it appears that this should do the same job. */ | |
1797 | if (count == 31 | |
1798 | && next_insn_tests_no_inequality (insn)) | |
1799 | return "tst%.l %1"; | |
1800 | if (count == 15 | |
1801 | && next_insn_tests_no_inequality (insn)) | |
1802 | return "tst%.w %1"; | |
1803 | if (count == 7 | |
1804 | && next_insn_tests_no_inequality (insn)) | |
1805 | return "tst%.b %1"; | |
572d7bec | 1806 | /* Try to use `movew to ccr' followed by the appropriate branch insn. |
1807 | On some m68k variants unfortunately that's slower than btst. | |
1808 | On 68000 and higher, that should also work for all HImode operands. */ | |
1809 | if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size) | |
1810 | { | |
1811 | if (count == 3 && DATA_REG_P (operands[1]) | |
1812 | && next_insn_tests_no_inequality (insn)) | |
1813 | { | |
1814 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW; | |
1815 | return "move%.w %1,%%ccr"; | |
1816 | } | |
1817 | if (count == 2 && DATA_REG_P (operands[1]) | |
1818 | && next_insn_tests_no_inequality (insn)) | |
1819 | { | |
1820 | cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW; | |
1821 | return "move%.w %1,%%ccr"; | |
1822 | } | |
1823 | /* count == 1 followed by bvc/bvs and | |
1824 | count == 0 followed by bcc/bcs are also possible, but need | |
1825 | m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */ | |
1826 | } | |
5243fbff | 1827 | |
1828 | cc_status.flags = CC_NOT_NEGATIVE; | |
1829 | } | |
1830 | return "btst %0,%1"; | |
1831 | } | |
5243fbff | 1832 | \f |
b97b0687 | 1833 | /* Return true if X is a legitimate base register. STRICT_P says |
1834 | whether we need strict checking. */ | |
1835 | ||
1836 | bool | |
1837 | m68k_legitimate_base_reg_p (rtx x, bool strict_p) | |
1838 | { | |
1839 | /* Allow SUBREG everywhere we allow REG. This results in better code. */ | |
1840 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1841 | x = SUBREG_REG (x); | |
1842 | ||
1843 | return (REG_P (x) | |
1844 | && (strict_p | |
1845 | ? REGNO_OK_FOR_BASE_P (REGNO (x)) | |
979e5a71 | 1846 | : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x)))); |
b97b0687 | 1847 | } |
1848 | ||
1849 | /* Return true if X is a legitimate index register. STRICT_P says | |
1850 | whether we need strict checking. */ | |
1851 | ||
1852 | bool | |
1853 | m68k_legitimate_index_reg_p (rtx x, bool strict_p) | |
1854 | { | |
1855 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1856 | x = SUBREG_REG (x); | |
1857 | ||
1858 | return (REG_P (x) | |
1859 | && (strict_p | |
1860 | ? REGNO_OK_FOR_INDEX_P (REGNO (x)) | |
979e5a71 | 1861 | : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))); |
b97b0687 | 1862 | } |
1863 | ||
1864 | /* Return true if X is a legitimate index expression for a (d8,An,Xn) or | |
1865 | (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of | |
1866 | ADDRESS if so. STRICT_P says whether we need strict checking. */ | |
1867 | ||
1868 | static bool | |
1869 | m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) | |
1870 | { | |
1871 | int scale; | |
1872 | ||
1873 | /* Check for a scale factor. */ | |
1874 | scale = 1; | |
1875 | if ((TARGET_68020 || TARGET_COLDFIRE) | |
1876 | && GET_CODE (x) == MULT | |
1877 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1878 | && (INTVAL (XEXP (x, 1)) == 2 | |
1879 | || INTVAL (XEXP (x, 1)) == 4 | |
1880 | || (INTVAL (XEXP (x, 1)) == 8 | |
1881 | && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) | |
1882 | { | |
1883 | scale = INTVAL (XEXP (x, 1)); | |
1884 | x = XEXP (x, 0); | |
1885 | } | |
1886 | ||
1887 | /* Check for a word extension. */ | |
1888 | if (!TARGET_COLDFIRE | |
1889 | && GET_CODE (x) == SIGN_EXTEND | |
1890 | && GET_MODE (XEXP (x, 0)) == HImode) | |
1891 | x = XEXP (x, 0); | |
1892 | ||
1893 | if (m68k_legitimate_index_reg_p (x, strict_p)) | |
1894 | { | |
1895 | address->scale = scale; | |
1896 | address->index = x; | |
1897 | return true; | |
1898 | } | |
1899 | ||
1900 | return false; | |
1901 | } | |
1902 | ||
e0ab7256 | 1903 | /* Return true if X is an illegitimate symbolic constant. */ |
1904 | ||
1905 | bool | |
1906 | m68k_illegitimate_symbolic_constant_p (rtx x) | |
1907 | { | |
1908 | rtx base, offset; | |
1909 | ||
1910 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
1911 | { | |
1912 | split_const (x, &base, &offset); | |
1913 | if (GET_CODE (base) == SYMBOL_REF | |
1914 | && !offset_within_block_p (base, INTVAL (offset))) | |
1915 | return true; | |
1916 | } | |
869bde6b | 1917 | return m68k_tls_reference_p (x, false); |
e0ab7256 | 1918 | } |
1919 | ||
7d7d7bd2 | 1920 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
1921 | ||
1922 | static bool | |
3754d046 | 1923 | m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
7d7d7bd2 | 1924 | { |
1925 | return m68k_illegitimate_symbolic_constant_p (x); | |
1926 | } | |
1927 | ||
b97b0687 | 1928 | /* Return true if X is a legitimate constant address that can reach |
1929 | bytes in the range [X, X + REACH). STRICT_P says whether we need | |
1930 | strict checking. */ | |
1931 | ||
1932 | static bool | |
1933 | m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) | |
1934 | { | |
1935 | rtx base, offset; | |
1936 | ||
1937 | if (!CONSTANT_ADDRESS_P (x)) | |
1938 | return false; | |
1939 | ||
1940 | if (flag_pic | |
1941 | && !(strict_p && TARGET_PCREL) | |
1942 | && symbolic_operand (x, VOIDmode)) | |
1943 | return false; | |
1944 | ||
1945 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) | |
1946 | { | |
1947 | split_const (x, &base, &offset); | |
1948 | if (GET_CODE (base) == SYMBOL_REF | |
1949 | && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) | |
1950 | return false; | |
1951 | } | |
1952 | ||
869bde6b | 1953 | return !m68k_tls_reference_p (x, false); |
b97b0687 | 1954 | } |
1955 | ||
1956 | /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced | |
1957 | labels will become jump tables. */ | |
1958 | ||
1959 | static bool | |
1960 | m68k_jump_table_ref_p (rtx x) | |
1961 | { | |
1962 | if (GET_CODE (x) != LABEL_REF) | |
1963 | return false; | |
1964 | ||
91a55c11 | 1965 | rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0)); |
1966 | if (!NEXT_INSN (insn) && !PREV_INSN (insn)) | |
b97b0687 | 1967 | return true; |
1968 | ||
91a55c11 | 1969 | insn = next_nonnote_insn (insn); |
1970 | return insn && JUMP_TABLE_DATA_P (insn); | |
b97b0687 | 1971 | } |
1972 | ||
1973 | /* Return true if X is a legitimate address for values of mode MODE. | |
1974 | STRICT_P says whether strict checking is needed. If the address | |
1975 | is valid, describe its components in *ADDRESS. */ | |
1976 | ||
1977 | static bool | |
3754d046 | 1978 | m68k_decompose_address (machine_mode mode, rtx x, |
b97b0687 | 1979 | bool strict_p, struct m68k_address *address) |
1980 | { | |
1981 | unsigned int reach; | |
1982 | ||
1983 | memset (address, 0, sizeof (*address)); | |
1984 | ||
1985 | if (mode == BLKmode) | |
1986 | reach = 1; | |
1987 | else | |
1988 | reach = GET_MODE_SIZE (mode); | |
1989 | ||
1990 | /* Check for (An) (mode 2). */ | |
1991 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1992 | { | |
1993 | address->base = x; | |
1994 | return true; | |
1995 | } | |
1996 | ||
1997 | /* Check for -(An) and (An)+ (modes 3 and 4). */ | |
1998 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) | |
1999 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
2000 | { | |
2001 | address->code = GET_CODE (x); | |
2002 | address->base = XEXP (x, 0); | |
2003 | return true; | |
2004 | } | |
2005 | ||
2006 | /* Check for (d16,An) (mode 5). */ | |
2007 | if (GET_CODE (x) == PLUS | |
2008 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2009 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) | |
2010 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
2011 | { | |
2012 | address->base = XEXP (x, 0); | |
2013 | address->offset = XEXP (x, 1); | |
2014 | return true; | |
2015 | } | |
2016 | ||
2017 | /* Check for GOT loads. These are (bd,An,Xn) addresses if | |
2018 | TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) | |
2019 | addresses. */ | |
869bde6b | 2020 | if (GET_CODE (x) == PLUS |
2021 | && XEXP (x, 0) == pic_offset_table_rtx) | |
b97b0687 | 2022 | { |
869bde6b | 2023 | /* As we are processing a PLUS, do not unwrap RELOC32 symbols -- |
2024 | they are invalid in this context. */ | |
2025 | if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1)) | |
2026 | { | |
2027 | address->base = XEXP (x, 0); | |
2028 | address->offset = XEXP (x, 1); | |
2029 | return true; | |
2030 | } | |
b97b0687 | 2031 | } |
2032 | ||
2033 | /* The ColdFire FPU only accepts addressing modes 2-5. */ | |
2034 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2035 | return false; | |
2036 | ||
2037 | /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, | |
2038 | check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. | |
2039 | All these modes are variations of mode 7. */ | |
2040 | if (m68k_legitimate_constant_address_p (x, reach, strict_p)) | |
2041 | { | |
2042 | address->offset = x; | |
2043 | return true; | |
2044 | } | |
2045 | ||
2046 | /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for | |
2047 | tablejumps. | |
2048 | ||
2049 | ??? do_tablejump creates these addresses before placing the target | |
2050 | label, so we have to assume that unplaced labels are jump table | |
2051 | references. It seems unlikely that we would ever generate indexed | |
2052 | accesses to unplaced labels in other cases. */ | |
2053 | if (GET_CODE (x) == PLUS | |
2054 | && m68k_jump_table_ref_p (XEXP (x, 1)) | |
2055 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
2056 | { | |
2057 | address->offset = XEXP (x, 1); | |
2058 | return true; | |
2059 | } | |
2060 | ||
2061 | /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or | |
2062 | (bd,An,Xn.SIZE*SCALE) addresses. */ | |
2063 | ||
2064 | if (TARGET_68020) | |
2065 | { | |
2066 | /* Check for a nonzero base displacement. */ | |
2067 | if (GET_CODE (x) == PLUS | |
2068 | && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) | |
2069 | { | |
2070 | address->offset = XEXP (x, 1); | |
2071 | x = XEXP (x, 0); | |
2072 | } | |
2073 | ||
2074 | /* Check for a suppressed index register. */ | |
2075 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
2076 | { | |
2077 | address->base = x; | |
2078 | return true; | |
2079 | } | |
2080 | ||
2081 | /* Check for a suppressed base register. Do not allow this case | |
2082 | for non-symbolic offsets as it effectively gives gcc freedom | |
2083 | to treat data registers as base registers, which can generate | |
2084 | worse code. */ | |
2085 | if (address->offset | |
2086 | && symbolic_operand (address->offset, VOIDmode) | |
2087 | && m68k_decompose_index (x, strict_p, address)) | |
2088 | return true; | |
2089 | } | |
2090 | else | |
2091 | { | |
2092 | /* Check for a nonzero base displacement. */ | |
2093 | if (GET_CODE (x) == PLUS | |
2094 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2095 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) | |
2096 | { | |
2097 | address->offset = XEXP (x, 1); | |
2098 | x = XEXP (x, 0); | |
2099 | } | |
2100 | } | |
2101 | ||
2102 | /* We now expect the sum of a base and an index. */ | |
2103 | if (GET_CODE (x) == PLUS) | |
2104 | { | |
2105 | if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) | |
2106 | && m68k_decompose_index (XEXP (x, 1), strict_p, address)) | |
2107 | { | |
2108 | address->base = XEXP (x, 0); | |
2109 | return true; | |
2110 | } | |
2111 | ||
2112 | if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) | |
2113 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
2114 | { | |
2115 | address->base = XEXP (x, 1); | |
2116 | return true; | |
2117 | } | |
2118 | } | |
2119 | return false; | |
2120 | } | |
2121 | ||
2122 | /* Return true if X is a legitimate address for values of mode MODE. | |
2123 | STRICT_P says whether strict checking is needed. */ | |
2124 | ||
2125 | bool | |
3754d046 | 2126 | m68k_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) |
b97b0687 | 2127 | { |
2128 | struct m68k_address address; | |
2129 | ||
2130 | return m68k_decompose_address (mode, x, strict_p, &address); | |
2131 | } | |
2132 | ||
2133 | /* Return true if X is a memory, describing its address in ADDRESS if so. | |
2134 | Apply strict checking if called during or after reload. */ | |
2135 | ||
2136 | static bool | |
2137 | m68k_legitimate_mem_p (rtx x, struct m68k_address *address) | |
2138 | { | |
2139 | return (MEM_P (x) | |
2140 | && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), | |
2141 | reload_in_progress || reload_completed, | |
2142 | address)); | |
2143 | } | |
2144 | ||
ca316360 | 2145 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
2146 | ||
2147 | bool | |
3754d046 | 2148 | m68k_legitimate_constant_p (machine_mode mode, rtx x) |
ca316360 | 2149 | { |
2150 | return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x); | |
2151 | } | |
2152 | ||
b97b0687 | 2153 | /* Return true if X matches the 'Q' constraint. It must be a memory |
2154 | with a base address and no constant offset or index. */ | |
2155 | ||
2156 | bool | |
2157 | m68k_matches_q_p (rtx x) | |
2158 | { | |
2159 | struct m68k_address address; | |
2160 | ||
2161 | return (m68k_legitimate_mem_p (x, &address) | |
2162 | && address.code == UNKNOWN | |
2163 | && address.base | |
2164 | && !address.offset | |
2165 | && !address.index); | |
2166 | } | |
2167 | ||
2168 | /* Return true if X matches the 'U' constraint. It must be a base address | |
2169 | with a constant offset and no index. */ | |
2170 | ||
2171 | bool | |
2172 | m68k_matches_u_p (rtx x) | |
2173 | { | |
2174 | struct m68k_address address; | |
2175 | ||
2176 | return (m68k_legitimate_mem_p (x, &address) | |
2177 | && address.code == UNKNOWN | |
2178 | && address.base | |
2179 | && address.offset | |
2180 | && !address.index); | |
2181 | } | |
2182 | ||
869bde6b | 2183 | /* Return GOT pointer. */ |
2184 | ||
2185 | static rtx | |
2186 | m68k_get_gp (void) | |
2187 | { | |
2188 | if (pic_offset_table_rtx == NULL_RTX) | |
2189 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG); | |
2190 | ||
2191 | crtl->uses_pic_offset_table = 1; | |
2192 | ||
2193 | return pic_offset_table_rtx; | |
2194 | } | |
2195 | ||
2196 | /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC | |
2197 | wrappers. */ | |
2198 | enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO, | |
2199 | RELOC_TLSIE, RELOC_TLSLE }; | |
2200 | ||
2201 | #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT) | |
2202 | ||
2203 | /* Wrap symbol X into unspec representing relocation RELOC. | |
2204 | BASE_REG - register that should be added to the result. | |
2205 | TEMP_REG - if non-null, temporary register. */ | |
2206 | ||
2207 | static rtx | |
2208 | m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg) | |
2209 | { | |
2210 | bool use_x_p; | |
2211 | ||
2212 | use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS; | |
2213 | ||
2214 | if (TARGET_COLDFIRE && use_x_p) | |
2215 | /* When compiling with -mx{got, tls} switch the code will look like this: | |
2216 | ||
2217 | move.l <X>@<RELOC>,<TEMP_REG> | |
2218 | add.l <BASE_REG>,<TEMP_REG> */ | |
2219 | { | |
2220 | /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra | |
2221 | to put @RELOC after reference. */ | |
2222 | x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), | |
2223 | UNSPEC_RELOC32); | |
2224 | x = gen_rtx_CONST (Pmode, x); | |
2225 | ||
2226 | if (temp_reg == NULL) | |
2227 | { | |
2228 | gcc_assert (can_create_pseudo_p ()); | |
2229 | temp_reg = gen_reg_rtx (Pmode); | |
2230 | } | |
2231 | ||
2232 | emit_move_insn (temp_reg, x); | |
2233 | emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg)); | |
2234 | x = temp_reg; | |
2235 | } | |
2236 | else | |
2237 | { | |
2238 | x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), | |
2239 | UNSPEC_RELOC16); | |
2240 | x = gen_rtx_CONST (Pmode, x); | |
2241 | ||
2242 | x = gen_rtx_PLUS (Pmode, base_reg, x); | |
2243 | } | |
2244 | ||
2245 | return x; | |
2246 | } | |
2247 | ||
2248 | /* Helper for m68k_unwrap_symbol. | |
2249 | Also, if unwrapping was successful (that is if (ORIG != <return value>)), | |
2250 | sets *RELOC_PTR to relocation type for the symbol. */ | |
2251 | ||
2252 | static rtx | |
2253 | m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p, | |
2254 | enum m68k_reloc *reloc_ptr) | |
2255 | { | |
2256 | if (GET_CODE (orig) == CONST) | |
2257 | { | |
2258 | rtx x; | |
2259 | enum m68k_reloc dummy; | |
2260 | ||
2261 | x = XEXP (orig, 0); | |
2262 | ||
2263 | if (reloc_ptr == NULL) | |
2264 | reloc_ptr = &dummy; | |
2265 | ||
2266 | /* Handle an addend. */ | |
2267 | if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS) | |
2268 | && CONST_INT_P (XEXP (x, 1))) | |
2269 | x = XEXP (x, 0); | |
2270 | ||
2271 | if (GET_CODE (x) == UNSPEC) | |
2272 | { | |
2273 | switch (XINT (x, 1)) | |
2274 | { | |
2275 | case UNSPEC_RELOC16: | |
2276 | orig = XVECEXP (x, 0, 0); | |
2277 | *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); | |
2278 | break; | |
2279 | ||
2280 | case UNSPEC_RELOC32: | |
2281 | if (unwrap_reloc32_p) | |
2282 | { | |
2283 | orig = XVECEXP (x, 0, 0); | |
2284 | *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); | |
2285 | } | |
2286 | break; | |
2287 | ||
2288 | default: | |
2289 | break; | |
2290 | } | |
2291 | } | |
2292 | } | |
2293 | ||
2294 | return orig; | |
2295 | } | |
2296 | ||
2297 | /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p, | |
2298 | UNSPEC_RELOC32 wrappers. */ | |
2299 | ||
2300 | rtx | |
2301 | m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p) | |
2302 | { | |
2303 | return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL); | |
2304 | } | |
2305 | ||
869bde6b | 2306 | /* Prescan insn before outputing assembler for it. */ |
2307 | ||
2308 | void | |
9e9d6337 | 2309 | m68k_final_prescan_insn (rtx_insn *insn ATTRIBUTE_UNUSED, |
869bde6b | 2310 | rtx *operands, int n_operands) |
2311 | { | |
2312 | int i; | |
2313 | ||
2314 | /* Combine and, possibly, other optimizations may do good job | |
2315 | converting | |
2316 | (const (unspec [(symbol)])) | |
2317 | into | |
2318 | (const (plus (unspec [(symbol)]) | |
2319 | (const_int N))). | |
2320 | The problem with this is emitting @TLS or @GOT decorations. | |
2321 | The decoration is emitted when processing (unspec), so the | |
2322 | result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE". | |
2323 | ||
2324 | It seems that the easiest solution to this is to convert such | |
2325 | operands to | |
2326 | (const (unspec [(plus (symbol) | |
2327 | (const_int N))])). | |
2328 | Note, that the top level of operand remains intact, so we don't have | |
2329 | to patch up anything outside of the operand. */ | |
2330 | ||
d8ca5b53 | 2331 | subrtx_var_iterator::array_type array; |
869bde6b | 2332 | for (i = 0; i < n_operands; ++i) |
2333 | { | |
2334 | rtx op; | |
2335 | ||
2336 | op = operands[i]; | |
2337 | ||
d8ca5b53 | 2338 | FOR_EACH_SUBRTX_VAR (iter, array, op, ALL) |
2339 | { | |
2340 | rtx x = *iter; | |
2341 | if (m68k_unwrap_symbol (x, true) != x) | |
2342 | { | |
2343 | rtx plus; | |
2344 | ||
2345 | gcc_assert (GET_CODE (x) == CONST); | |
2346 | plus = XEXP (x, 0); | |
2347 | ||
2348 | if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS) | |
2349 | { | |
2350 | rtx unspec; | |
2351 | rtx addend; | |
2352 | ||
2353 | unspec = XEXP (plus, 0); | |
2354 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
2355 | addend = XEXP (plus, 1); | |
2356 | gcc_assert (CONST_INT_P (addend)); | |
2357 | ||
2358 | /* We now have all the pieces, rearrange them. */ | |
2359 | ||
2360 | /* Move symbol to plus. */ | |
2361 | XEXP (plus, 0) = XVECEXP (unspec, 0, 0); | |
2362 | ||
2363 | /* Move plus inside unspec. */ | |
2364 | XVECEXP (unspec, 0, 0) = plus; | |
2365 | ||
2366 | /* Move unspec to top level of const. */ | |
2367 | XEXP (x, 0) = unspec; | |
2368 | } | |
2369 | iter.skip_subrtxes (); | |
2370 | } | |
2371 | } | |
869bde6b | 2372 | } |
2373 | } | |
2374 | ||
2375 | /* Move X to a register and add REG_EQUAL note pointing to ORIG. | |
2376 | If REG is non-null, use it; generate new pseudo otherwise. */ | |
2377 | ||
2378 | static rtx | |
2379 | m68k_move_to_reg (rtx x, rtx orig, rtx reg) | |
2380 | { | |
9e9d6337 | 2381 | rtx_insn *insn; |
869bde6b | 2382 | |
2383 | if (reg == NULL_RTX) | |
2384 | { | |
2385 | gcc_assert (can_create_pseudo_p ()); | |
2386 | reg = gen_reg_rtx (Pmode); | |
2387 | } | |
2388 | ||
2389 | insn = emit_move_insn (reg, x); | |
2390 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2391 | by loop. */ | |
2392 | set_unique_reg_note (insn, REG_EQUAL, orig); | |
2393 | ||
2394 | return reg; | |
2395 | } | |
2396 | ||
2397 | /* Does the same as m68k_wrap_symbol, but returns a memory reference to | |
2398 | GOT slot. */ | |
2399 | ||
2400 | static rtx | |
2401 | m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg) | |
2402 | { | |
2403 | x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg); | |
2404 | ||
2405 | x = gen_rtx_MEM (Pmode, x); | |
2406 | MEM_READONLY_P (x) = 1; | |
2407 | ||
2408 | return x; | |
2409 | } | |
2410 | ||
5243fbff | 2411 | /* Legitimize PIC addresses. If the address is already |
2412 | position-independent, we return ORIG. Newly generated | |
2413 | position-independent addresses go to REG. If we need more | |
2414 | than one register, we lose. | |
2415 | ||
2416 | An address is legitimized by making an indirect reference | |
2417 | through the Global Offset Table with the name of the symbol | |
2418 | used as an offset. | |
2419 | ||
2420 | The assembler and linker are responsible for placing the | |
2421 | address of the symbol in the GOT. The function prologue | |
2422 | is responsible for initializing a5 to the starting address | |
2423 | of the GOT. | |
2424 | ||
2425 | The assembler is also responsible for translating a symbol name | |
2426 | into a constant displacement from the start of the GOT. | |
2427 | ||
2428 | A quick example may make things a little clearer: | |
2429 | ||
2430 | When not generating PIC code to store the value 12345 into _foo | |
2431 | we would generate the following code: | |
2432 | ||
2433 | movel #12345, _foo | |
2434 | ||
2435 | When generating PIC two transformations are made. First, the compiler | |
2436 | loads the address of foo into a register. So the first transformation makes: | |
2437 | ||
2438 | lea _foo, a0 | |
2439 | movel #12345, a0@ | |
2440 | ||
2441 | The code in movsi will intercept the lea instruction and call this | |
2442 | routine which will transform the instructions into: | |
2443 | ||
2444 | movel a5@(_foo:w), a0 | |
2445 | movel #12345, a0@ | |
2446 | ||
2447 | ||
2448 | That (in a nutshell) is how *all* symbol and label references are | |
2449 | handled. */ | |
2450 | ||
2451 | rtx | |
3754d046 | 2452 | legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, |
821960c7 | 2453 | rtx reg) |
5243fbff | 2454 | { |
2455 | rtx pic_ref = orig; | |
2456 | ||
2457 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
2458 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
2459 | { | |
84653e0f | 2460 | gcc_assert (reg); |
5243fbff | 2461 | |
869bde6b | 2462 | pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg); |
2463 | pic_ref = m68k_move_to_reg (pic_ref, orig, reg); | |
5243fbff | 2464 | } |
2465 | else if (GET_CODE (orig) == CONST) | |
2466 | { | |
e6b2f841 | 2467 | rtx base; |
5243fbff | 2468 | |
a58c6df6 | 2469 | /* Make sure this has not already been legitimized. */ |
869bde6b | 2470 | if (m68k_unwrap_symbol (orig, true) != orig) |
5243fbff | 2471 | return orig; |
2472 | ||
84653e0f | 2473 | gcc_assert (reg); |
5243fbff | 2474 | |
2475 | /* legitimize both operands of the PLUS */ | |
84653e0f | 2476 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
2477 | ||
2478 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2479 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2480 | base == reg ? 0 : reg); | |
5243fbff | 2481 | |
2482 | if (GET_CODE (orig) == CONST_INT) | |
29c05e22 | 2483 | pic_ref = plus_constant (Pmode, base, INTVAL (orig)); |
869bde6b | 2484 | else |
2485 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); | |
5243fbff | 2486 | } |
869bde6b | 2487 | |
5243fbff | 2488 | return pic_ref; |
2489 | } | |
2490 | ||
869bde6b | 2491 | /* The __tls_get_addr symbol. */ |
2492 | static GTY(()) rtx m68k_tls_get_addr; | |
2493 | ||
2494 | /* Return SYMBOL_REF for __tls_get_addr. */ | |
2495 | ||
2496 | static rtx | |
2497 | m68k_get_tls_get_addr (void) | |
2498 | { | |
2499 | if (m68k_tls_get_addr == NULL_RTX) | |
2500 | m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr"); | |
2501 | ||
2502 | return m68k_tls_get_addr; | |
2503 | } | |
2504 | ||
2505 | /* Return libcall result in A0 instead of usual D0. */ | |
2506 | static bool m68k_libcall_value_in_a0_p = false; | |
2507 | ||
2508 | /* Emit instruction sequence that calls __tls_get_addr. X is | |
2509 | the TLS symbol we are referencing and RELOC is the symbol type to use | |
2510 | (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence | |
2511 | emitted. A pseudo register with result of __tls_get_addr call is | |
2512 | returned. */ | |
2513 | ||
2514 | static rtx | |
2515 | m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc) | |
2516 | { | |
2517 | rtx a0; | |
9e9d6337 | 2518 | rtx_insn *insns; |
869bde6b | 2519 | rtx dest; |
2520 | ||
2521 | /* Emit the call sequence. */ | |
2522 | start_sequence (); | |
2523 | ||
2524 | /* FIXME: Unfortunately, emit_library_call_value does not | |
2525 | consider (plus (%a5) (const (unspec))) to be a good enough | |
2526 | operand for push, so it forces it into a register. The bad | |
2527 | thing about this is that combiner, due to copy propagation and other | |
2528 | optimizations, sometimes can not later fix this. As a consequence, | |
2529 | additional register may be allocated resulting in a spill. | |
2530 | For reference, see args processing loops in | |
2531 | calls.c:emit_library_call_value_1. | |
2532 | For testcase, see gcc.target/m68k/tls-{gd, ld}.c */ | |
2533 | x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX); | |
2534 | ||
2535 | /* __tls_get_addr() is not a libcall, but emitting a libcall_value | |
2536 | is the simpliest way of generating a call. The difference between | |
2537 | __tls_get_addr() and libcall is that the result is returned in D0 | |
2538 | instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p | |
2539 | which temporarily switches returning the result to A0. */ | |
2540 | ||
2541 | m68k_libcall_value_in_a0_p = true; | |
2542 | a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE, | |
2543 | Pmode, 1, x, Pmode); | |
2544 | m68k_libcall_value_in_a0_p = false; | |
2545 | ||
2546 | insns = get_insns (); | |
2547 | end_sequence (); | |
2548 | ||
2549 | gcc_assert (can_create_pseudo_p ()); | |
2550 | dest = gen_reg_rtx (Pmode); | |
2551 | emit_libcall_block (insns, dest, a0, eqv); | |
2552 | ||
2553 | return dest; | |
2554 | } | |
2555 | ||
2556 | /* The __tls_get_addr symbol. */ | |
2557 | static GTY(()) rtx m68k_read_tp; | |
2558 | ||
2559 | /* Return SYMBOL_REF for __m68k_read_tp. */ | |
2560 | ||
2561 | static rtx | |
2562 | m68k_get_m68k_read_tp (void) | |
2563 | { | |
2564 | if (m68k_read_tp == NULL_RTX) | |
2565 | m68k_read_tp = init_one_libfunc ("__m68k_read_tp"); | |
2566 | ||
2567 | return m68k_read_tp; | |
2568 | } | |
2569 | ||
2570 | /* Emit instruction sequence that calls __m68k_read_tp. | |
2571 | A pseudo register with result of __m68k_read_tp call is returned. */ | |
2572 | ||
2573 | static rtx | |
2574 | m68k_call_m68k_read_tp (void) | |
2575 | { | |
2576 | rtx a0; | |
2577 | rtx eqv; | |
9e9d6337 | 2578 | rtx_insn *insns; |
869bde6b | 2579 | rtx dest; |
2580 | ||
2581 | start_sequence (); | |
2582 | ||
2583 | /* __m68k_read_tp() is not a libcall, but emitting a libcall_value | |
2584 | is the simpliest way of generating a call. The difference between | |
2585 | __m68k_read_tp() and libcall is that the result is returned in D0 | |
2586 | instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p | |
2587 | which temporarily switches returning the result to A0. */ | |
2588 | ||
2589 | /* Emit the call sequence. */ | |
2590 | m68k_libcall_value_in_a0_p = true; | |
2591 | a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE, | |
2592 | Pmode, 0); | |
2593 | m68k_libcall_value_in_a0_p = false; | |
2594 | insns = get_insns (); | |
2595 | end_sequence (); | |
2596 | ||
2597 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2598 | share the m68k_read_tp result with other IE/LE model accesses. */ | |
2599 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32); | |
2600 | ||
2601 | gcc_assert (can_create_pseudo_p ()); | |
2602 | dest = gen_reg_rtx (Pmode); | |
2603 | emit_libcall_block (insns, dest, a0, eqv); | |
2604 | ||
2605 | return dest; | |
2606 | } | |
2607 | ||
2608 | /* Return a legitimized address for accessing TLS SYMBOL_REF X. | |
2609 | For explanations on instructions sequences see TLS/NPTL ABI for m68k and | |
2610 | ColdFire. */ | |
2611 | ||
2612 | rtx | |
2613 | m68k_legitimize_tls_address (rtx orig) | |
2614 | { | |
2615 | switch (SYMBOL_REF_TLS_MODEL (orig)) | |
2616 | { | |
2617 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
2618 | orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD); | |
2619 | break; | |
2620 | ||
2621 | case TLS_MODEL_LOCAL_DYNAMIC: | |
2622 | { | |
2623 | rtx eqv; | |
2624 | rtx a0; | |
2625 | rtx x; | |
2626 | ||
2627 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2628 | share the LDM result with other LD model accesses. */ | |
2629 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2630 | UNSPEC_RELOC32); | |
2631 | ||
2632 | a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM); | |
2633 | ||
2634 | x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX); | |
2635 | ||
2636 | if (can_create_pseudo_p ()) | |
2637 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2638 | ||
2639 | orig = x; | |
2640 | break; | |
2641 | } | |
2642 | ||
2643 | case TLS_MODEL_INITIAL_EXEC: | |
2644 | { | |
2645 | rtx a0; | |
2646 | rtx x; | |
2647 | ||
2648 | a0 = m68k_call_m68k_read_tp (); | |
2649 | ||
2650 | x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX); | |
2651 | x = gen_rtx_PLUS (Pmode, x, a0); | |
2652 | ||
2653 | if (can_create_pseudo_p ()) | |
2654 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2655 | ||
2656 | orig = x; | |
2657 | break; | |
2658 | } | |
2659 | ||
2660 | case TLS_MODEL_LOCAL_EXEC: | |
2661 | { | |
2662 | rtx a0; | |
2663 | rtx x; | |
2664 | ||
2665 | a0 = m68k_call_m68k_read_tp (); | |
2666 | ||
2667 | x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX); | |
2668 | ||
2669 | if (can_create_pseudo_p ()) | |
2670 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2671 | ||
2672 | orig = x; | |
2673 | break; | |
2674 | } | |
2675 | ||
2676 | default: | |
2677 | gcc_unreachable (); | |
2678 | } | |
2679 | ||
2680 | return orig; | |
2681 | } | |
2682 | ||
2683 | /* Return true if X is a TLS symbol. */ | |
2684 | ||
2685 | static bool | |
2686 | m68k_tls_symbol_p (rtx x) | |
2687 | { | |
2688 | if (!TARGET_HAVE_TLS) | |
2689 | return false; | |
2690 | ||
2691 | if (GET_CODE (x) != SYMBOL_REF) | |
2692 | return false; | |
2693 | ||
2694 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
2695 | } | |
2696 | ||
869bde6b | 2697 | /* If !LEGITIMATE_P, return true if X is a TLS symbol reference, |
2698 | though illegitimate one. | |
2699 | If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */ | |
2700 | ||
2701 | bool | |
2702 | m68k_tls_reference_p (rtx x, bool legitimate_p) | |
2703 | { | |
2704 | if (!TARGET_HAVE_TLS) | |
2705 | return false; | |
2706 | ||
2707 | if (!legitimate_p) | |
bcf1a9e0 | 2708 | { |
2709 | subrtx_var_iterator::array_type array; | |
2710 | FOR_EACH_SUBRTX_VAR (iter, array, x, ALL) | |
2711 | { | |
2712 | rtx x = *iter; | |
2713 | ||
2714 | /* Note: this is not the same as m68k_tls_symbol_p. */ | |
2715 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0) | |
2716 | return true; | |
2717 | ||
2718 | /* Don't recurse into legitimate TLS references. */ | |
2719 | if (m68k_tls_reference_p (x, true)) | |
2720 | iter.skip_subrtxes (); | |
2721 | } | |
2722 | return false; | |
2723 | } | |
869bde6b | 2724 | else |
2725 | { | |
2726 | enum m68k_reloc reloc = RELOC_GOT; | |
2727 | ||
2728 | return (m68k_unwrap_symbol_1 (x, true, &reloc) != x | |
2729 | && TLS_RELOC_P (reloc)); | |
2730 | } | |
2731 | } | |
2732 | ||
5243fbff | 2733 | \f |
1286b2d4 | 2734 | |
065b42aa | 2735 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
1286b2d4 | 2736 | |
92b2fb42 | 2737 | /* Return the type of move that should be used for integer I. */ |
2738 | ||
1d86aeab | 2739 | M68K_CONST_METHOD |
2740 | m68k_const_method (HOST_WIDE_INT i) | |
1286b2d4 | 2741 | { |
1286b2d4 | 2742 | unsigned u; |
2743 | ||
e4cd7d76 | 2744 | if (USE_MOVQ (i)) |
1286b2d4 | 2745 | return MOVQ; |
1f09b395 | 2746 | |
b14b4511 | 2747 | /* The ColdFire doesn't have byte or word operations. */ |
274d52cf | 2748 | /* FIXME: This may not be useful for the m68060 either. */ |
d2a91c7e | 2749 | if (!TARGET_COLDFIRE) |
1f09b395 | 2750 | { |
2751 | /* if -256 < N < 256 but N is not in range for a moveq | |
0c0492c9 | 2752 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
1f09b395 | 2753 | if (USE_MOVQ (i ^ 0xff)) |
2754 | return NOTB; | |
2755 | /* Likewise, try with not.w */ | |
2756 | if (USE_MOVQ (i ^ 0xffff)) | |
2757 | return NOTW; | |
2758 | /* This is the only value where neg.w is useful */ | |
2759 | if (i == -65408) | |
2760 | return NEGW; | |
1f09b395 | 2761 | } |
c3f7507d | 2762 | |
0c4bc85a | 2763 | /* Try also with swap. */ |
2764 | u = i; | |
2765 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
2766 | return SWAP; | |
2767 | ||
42af5438 | 2768 | if (TARGET_ISAB) |
c3f7507d | 2769 | { |
fb4883de | 2770 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
c3f7507d | 2771 | if (i >= 0 && i <= 65535) |
2772 | return MVZ; | |
2773 | if (i >= -32768 && i <= 32767) | |
2774 | return MVS; | |
2775 | } | |
2776 | ||
1286b2d4 | 2777 | /* Otherwise, use move.l */ |
2778 | return MOVL; | |
2779 | } | |
2780 | ||
92b2fb42 | 2781 | /* Return the cost of moving constant I into a data register. */ |
2782 | ||
fab7adbf | 2783 | static int |
92b2fb42 | 2784 | const_int_cost (HOST_WIDE_INT i) |
1286b2d4 | 2785 | { |
1d86aeab | 2786 | switch (m68k_const_method (i)) |
1286b2d4 | 2787 | { |
065b42aa | 2788 | case MOVQ: |
2789 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
2790 | return 0; | |
2791 | case MVZ: | |
2792 | case MVS: | |
2793 | case NOTB: | |
2794 | case NOTW: | |
2795 | case NEGW: | |
2796 | case SWAP: | |
2797 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
2798 | return 1; | |
2799 | case MOVL: | |
2800 | return 2; | |
2801 | default: | |
2802 | gcc_unreachable (); | |
1286b2d4 | 2803 | } |
2804 | } | |
2805 | ||
fab7adbf | 2806 | static bool |
5ae4887d | 2807 | m68k_rtx_costs (rtx x, machine_mode mode, int outer_code, |
2808 | int opno ATTRIBUTE_UNUSED, | |
20d892d1 | 2809 | int *total, bool speed ATTRIBUTE_UNUSED) |
fab7adbf | 2810 | { |
5ae4887d | 2811 | int code = GET_CODE (x); |
2812 | ||
fab7adbf | 2813 | switch (code) |
2814 | { | |
2815 | case CONST_INT: | |
2816 | /* Constant zero is super cheap due to clr instruction. */ | |
2817 | if (x == const0_rtx) | |
2818 | *total = 0; | |
2819 | else | |
92b2fb42 | 2820 | *total = const_int_cost (INTVAL (x)); |
fab7adbf | 2821 | return true; |
2822 | ||
2823 | case CONST: | |
2824 | case LABEL_REF: | |
2825 | case SYMBOL_REF: | |
2826 | *total = 3; | |
2827 | return true; | |
2828 | ||
2829 | case CONST_DOUBLE: | |
2830 | /* Make 0.0 cheaper than other floating constants to | |
2831 | encourage creating tstsf and tstdf insns. */ | |
2832 | if (outer_code == COMPARE | |
2833 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
2834 | *total = 4; | |
2835 | else | |
2836 | *total = 5; | |
2837 | return true; | |
2838 | ||
2839 | /* These are vaguely right for a 68020. */ | |
2840 | /* The costs for long multiply have been adjusted to work properly | |
2841 | in synth_mult on the 68020, relative to an average of the time | |
2842 | for add and the time for shift, taking away a little more because | |
2843 | sometimes move insns are needed. */ | |
065b42aa | 2844 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
2845 | terms. */ | |
bd40163f | 2846 | #define MULL_COST \ |
2847 | (TUNE_68060 ? 2 \ | |
2848 | : TUNE_68040 ? 5 \ | |
53457e36 | 2849 | : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ |
2850 | : (TUNE_CFV2 && TUNE_MAC) ? 4 \ | |
2851 | : TUNE_CFV2 ? 8 \ | |
bd40163f | 2852 | : TARGET_COLDFIRE ? 3 : 13) |
2853 | ||
2854 | #define MULW_COST \ | |
2855 | (TUNE_68060 ? 2 \ | |
2856 | : TUNE_68040 ? 3 \ | |
53457e36 | 2857 | : TUNE_68000_10 ? 5 \ |
2858 | : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ | |
2859 | : (TUNE_CFV2 && TUNE_MAC) ? 2 \ | |
2860 | : TUNE_CFV2 ? 8 \ | |
bd40163f | 2861 | : TARGET_COLDFIRE ? 2 : 8) |
2862 | ||
2863 | #define DIVW_COST \ | |
2864 | (TARGET_CF_HWDIV ? 11 \ | |
2865 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
fab7adbf | 2866 | |
2867 | case PLUS: | |
2868 | /* An lea costs about three times as much as a simple add. */ | |
5ae4887d | 2869 | if (mode == SImode |
fab7adbf | 2870 | && GET_CODE (XEXP (x, 1)) == REG |
2871 | && GET_CODE (XEXP (x, 0)) == MULT | |
2872 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2873 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2874 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
2875 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
2876 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
13ab0298 | 2877 | { |
2878 | /* lea an@(dx:l:i),am */ | |
2879 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
2880 | return true; | |
2881 | } | |
fab7adbf | 2882 | return false; |
2883 | ||
2884 | case ASHIFT: | |
2885 | case ASHIFTRT: | |
2886 | case LSHIFTRT: | |
bd40163f | 2887 | if (TUNE_68060) |
fab7adbf | 2888 | { |
2889 | *total = COSTS_N_INSNS(1); | |
2890 | return true; | |
2891 | } | |
bd40163f | 2892 | if (TUNE_68000_10) |
fab7adbf | 2893 | { |
2894 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2895 | { | |
2896 | if (INTVAL (XEXP (x, 1)) < 16) | |
2897 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
2898 | else | |
2899 | /* We're using clrw + swap for these cases. */ | |
2900 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
2901 | } | |
2902 | else | |
065b42aa | 2903 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
fab7adbf | 2904 | return true; |
2905 | } | |
2906 | /* A shift by a big integer takes an extra instruction. */ | |
2907 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2908 | && (INTVAL (XEXP (x, 1)) == 16)) | |
2909 | { | |
2910 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
2911 | return true; | |
2912 | } | |
2913 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2914 | && !(INTVAL (XEXP (x, 1)) > 0 | |
2915 | && INTVAL (XEXP (x, 1)) <= 8)) | |
2916 | { | |
13ab0298 | 2917 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
fab7adbf | 2918 | return true; |
2919 | } | |
2920 | return false; | |
2921 | ||
2922 | case MULT: | |
2923 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
2924 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
5ae4887d | 2925 | && mode == SImode) |
fab7adbf | 2926 | *total = COSTS_N_INSNS (MULW_COST); |
5ae4887d | 2927 | else if (mode == QImode || mode == HImode) |
fab7adbf | 2928 | *total = COSTS_N_INSNS (MULW_COST); |
2929 | else | |
2930 | *total = COSTS_N_INSNS (MULL_COST); | |
2931 | return true; | |
2932 | ||
2933 | case DIV: | |
2934 | case UDIV: | |
2935 | case MOD: | |
2936 | case UMOD: | |
5ae4887d | 2937 | if (mode == QImode || mode == HImode) |
fab7adbf | 2938 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ |
13ab0298 | 2939 | else if (TARGET_CF_HWDIV) |
2940 | *total = COSTS_N_INSNS (18); | |
fab7adbf | 2941 | else |
2942 | *total = COSTS_N_INSNS (43); /* div.l */ | |
2943 | return true; | |
2944 | ||
74f4459c | 2945 | case ZERO_EXTRACT: |
2946 | if (outer_code == COMPARE) | |
2947 | *total = 0; | |
2948 | return false; | |
2949 | ||
fab7adbf | 2950 | default: |
2951 | return false; | |
2952 | } | |
2953 | } | |
2954 | ||
0d424440 | 2955 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
92b2fb42 | 2956 | OPERANDS[0]. */ |
2957 | ||
2958 | static const char * | |
821960c7 | 2959 | output_move_const_into_data_reg (rtx *operands) |
1286b2d4 | 2960 | { |
92b2fb42 | 2961 | HOST_WIDE_INT i; |
1286b2d4 | 2962 | |
2963 | i = INTVAL (operands[1]); | |
1d86aeab | 2964 | switch (m68k_const_method (i)) |
1286b2d4 | 2965 | { |
c3f7507d | 2966 | case MVZ: |
c3f7507d | 2967 | return "mvzw %1,%0"; |
176f6408 | 2968 | case MVS: |
2969 | return "mvsw %1,%0"; | |
065b42aa | 2970 | case MOVQ: |
1286b2d4 | 2971 | return "moveq %1,%0"; |
065b42aa | 2972 | case NOTB: |
1f24a83f | 2973 | CC_STATUS_INIT; |
e6b2f841 | 2974 | operands[1] = GEN_INT (i ^ 0xff); |
1286b2d4 | 2975 | return "moveq %1,%0\n\tnot%.b %0"; |
065b42aa | 2976 | case NOTW: |
1f24a83f | 2977 | CC_STATUS_INIT; |
e6b2f841 | 2978 | operands[1] = GEN_INT (i ^ 0xffff); |
1286b2d4 | 2979 | return "moveq %1,%0\n\tnot%.w %0"; |
065b42aa | 2980 | case NEGW: |
1f24a83f | 2981 | CC_STATUS_INIT; |
3acc77d9 | 2982 | return "moveq #-128,%0\n\tneg%.w %0"; |
065b42aa | 2983 | case SWAP: |
1286b2d4 | 2984 | { |
2985 | unsigned u = i; | |
2986 | ||
e6b2f841 | 2987 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
1286b2d4 | 2988 | return "moveq %1,%0\n\tswap %0"; |
1286b2d4 | 2989 | } |
065b42aa | 2990 | case MOVL: |
92b2fb42 | 2991 | return "move%.l %1,%0"; |
065b42aa | 2992 | default: |
92b2fb42 | 2993 | gcc_unreachable (); |
1286b2d4 | 2994 | } |
2995 | } | |
2996 | ||
92b2fb42 | 2997 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
0c4bc85a | 2998 | |
92b2fb42 | 2999 | bool |
3000 | valid_mov3q_const (HOST_WIDE_INT i) | |
3001 | { | |
3002 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
0c4bc85a | 3003 | } |
3004 | ||
92b2fb42 | 3005 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
3006 | I is the value of OPERANDS[1]. */ | |
0c4bc85a | 3007 | |
92b2fb42 | 3008 | static const char * |
821960c7 | 3009 | output_move_simode_const (rtx *operands) |
24821a10 | 3010 | { |
92b2fb42 | 3011 | rtx dest; |
3012 | HOST_WIDE_INT src; | |
3013 | ||
3014 | dest = operands[0]; | |
3015 | src = INTVAL (operands[1]); | |
3016 | if (src == 0 | |
3017 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
374e1815 | 3018 | /* clr insns on 68000 read before writing. */ |
3019 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
92b2fb42 | 3020 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
24821a10 | 3021 | return "clr%.l %0"; |
92b2fb42 | 3022 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
065b42aa | 3023 | return "mov3q%.l %1,%0"; |
92b2fb42 | 3024 | else if (src == 0 && ADDRESS_REG_P (dest)) |
c96c8169 | 3025 | return "sub%.l %0,%0"; |
92b2fb42 | 3026 | else if (DATA_REG_P (dest)) |
24821a10 | 3027 | return output_move_const_into_data_reg (operands); |
92b2fb42 | 3028 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
0c4bc85a | 3029 | { |
92b2fb42 | 3030 | if (valid_mov3q_const (src)) |
0c4bc85a | 3031 | return "mov3q%.l %1,%0"; |
3032 | return "move%.w %1,%0"; | |
3033 | } | |
92b2fb42 | 3034 | else if (MEM_P (dest) |
3035 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
3036 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
3037 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
0c4bc85a | 3038 | { |
92b2fb42 | 3039 | if (valid_mov3q_const (src)) |
0c4bc85a | 3040 | return "mov3q%.l %1,%-"; |
3041 | return "pea %a1"; | |
3042 | } | |
24821a10 | 3043 | return "move%.l %1,%0"; |
3044 | } | |
3045 | ||
f2fa409d | 3046 | const char * |
821960c7 | 3047 | output_move_simode (rtx *operands) |
a923bd2f | 3048 | { |
3049 | if (GET_CODE (operands[1]) == CONST_INT) | |
3050 | return output_move_simode_const (operands); | |
3051 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
3052 | || GET_CODE (operands[1]) == CONST) | |
3053 | && push_operand (operands[0], SImode)) | |
3054 | return "pea %a1"; | |
3055 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
3056 | || GET_CODE (operands[1]) == CONST) | |
3057 | && ADDRESS_REG_P (operands[0])) | |
3058 | return "lea %a1,%0"; | |
3059 | return "move%.l %1,%0"; | |
3060 | } | |
3061 | ||
f2fa409d | 3062 | const char * |
821960c7 | 3063 | output_move_himode (rtx *operands) |
a923bd2f | 3064 | { |
3065 | if (GET_CODE (operands[1]) == CONST_INT) | |
3066 | { | |
3067 | if (operands[1] == const0_rtx | |
3068 | && (DATA_REG_P (operands[0]) | |
3069 | || GET_CODE (operands[0]) == MEM) | |
374e1815 | 3070 | /* clr insns on 68000 read before writing. */ |
3071 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
a923bd2f | 3072 | || !(GET_CODE (operands[0]) == MEM |
3073 | && MEM_VOLATILE_P (operands[0])))) | |
3074 | return "clr%.w %0"; | |
c96c8169 | 3075 | else if (operands[1] == const0_rtx |
3076 | && ADDRESS_REG_P (operands[0])) | |
3077 | return "sub%.l %0,%0"; | |
a923bd2f | 3078 | else if (DATA_REG_P (operands[0]) |
3079 | && INTVAL (operands[1]) < 128 | |
3080 | && INTVAL (operands[1]) >= -128) | |
065b42aa | 3081 | return "moveq %1,%0"; |
a923bd2f | 3082 | else if (INTVAL (operands[1]) < 0x8000 |
3083 | && INTVAL (operands[1]) >= -0x8000) | |
3084 | return "move%.w %1,%0"; | |
3085 | } | |
3086 | else if (CONSTANT_P (operands[1])) | |
3087 | return "move%.l %1,%0"; | |
a923bd2f | 3088 | return "move%.w %1,%0"; |
3089 | } | |
3090 | ||
f2fa409d | 3091 | const char * |
821960c7 | 3092 | output_move_qimode (rtx *operands) |
a923bd2f | 3093 | { |
2c806cfd | 3094 | /* 68k family always modifies the stack pointer by at least 2, even for |
b14b4511 | 3095 | byte pushes. The 5200 (ColdFire) does not do this. */ |
84653e0f | 3096 | |
065b42aa | 3097 | /* This case is generated by pushqi1 pattern now. */ |
84653e0f | 3098 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
3099 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
3100 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
3101 | && ! ADDRESS_REG_P (operands[1]) | |
3102 | && ! TARGET_COLDFIRE)); | |
a923bd2f | 3103 | |
374e1815 | 3104 | /* clr and st insns on 68000 read before writing. */ |
a923bd2f | 3105 | if (!ADDRESS_REG_P (operands[0]) |
374e1815 | 3106 | && ((TARGET_68010 || TARGET_COLDFIRE) |
a923bd2f | 3107 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3108 | { | |
3109 | if (operands[1] == const0_rtx) | |
3110 | return "clr%.b %0"; | |
960e6739 | 3111 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
a923bd2f | 3112 | && GET_CODE (operands[1]) == CONST_INT |
3113 | && (INTVAL (operands[1]) & 255) == 255) | |
3114 | { | |
3115 | CC_STATUS_INIT; | |
3116 | return "st %0"; | |
3117 | } | |
3118 | } | |
3119 | if (GET_CODE (operands[1]) == CONST_INT | |
3120 | && DATA_REG_P (operands[0]) | |
3121 | && INTVAL (operands[1]) < 128 | |
3122 | && INTVAL (operands[1]) >= -128) | |
065b42aa | 3123 | return "moveq %1,%0"; |
c96c8169 | 3124 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
3125 | return "sub%.l %0,%0"; | |
a923bd2f | 3126 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
3127 | return "move%.l %1,%0"; | |
b14b4511 | 3128 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
a0a4c749 | 3129 | from address registers. */ |
3130 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
a923bd2f | 3131 | return "move%.w %1,%0"; |
3132 | return "move%.b %1,%0"; | |
3133 | } | |
3134 | ||
f2fa409d | 3135 | const char * |
821960c7 | 3136 | output_move_stricthi (rtx *operands) |
8797980e | 3137 | { |
3138 | if (operands[1] == const0_rtx | |
374e1815 | 3139 | /* clr insns on 68000 read before writing. */ |
3140 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
8797980e | 3141 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3142 | return "clr%.w %0"; | |
3143 | return "move%.w %1,%0"; | |
3144 | } | |
3145 | ||
f2fa409d | 3146 | const char * |
821960c7 | 3147 | output_move_strictqi (rtx *operands) |
8797980e | 3148 | { |
3149 | if (operands[1] == const0_rtx | |
374e1815 | 3150 | /* clr insns on 68000 read before writing. */ |
3151 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
8797980e | 3152 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3153 | return "clr%.b %0"; | |
3154 | return "move%.b %1,%0"; | |
3155 | } | |
3156 | ||
5243fbff | 3157 | /* Return the best assembler insn template |
3158 | for moving operands[1] into operands[0] as a fullword. */ | |
3159 | ||
f2fa409d | 3160 | static const char * |
821960c7 | 3161 | singlemove_string (rtx *operands) |
5243fbff | 3162 | { |
24821a10 | 3163 | if (GET_CODE (operands[1]) == CONST_INT) |
3164 | return output_move_simode_const (operands); | |
3165 | return "move%.l %1,%0"; | |
5243fbff | 3166 | } |
3167 | ||
df86ba0c | 3168 | |
1d86aeab | 3169 | /* Output assembler or rtl code to perform a doubleword move insn |
3170 | with operands OPERANDS. | |
3171 | Pointers to 3 helper functions should be specified: | |
3172 | HANDLE_REG_ADJUST to adjust a register by a small value, | |
3173 | HANDLE_COMPADR to compute an address and | |
3174 | HANDLE_MOVSI to move 4 bytes. */ | |
5243fbff | 3175 | |
1d86aeab | 3176 | static void |
3177 | handle_move_double (rtx operands[2], | |
3178 | void (*handle_reg_adjust) (rtx, int), | |
3179 | void (*handle_compadr) (rtx [2]), | |
3180 | void (*handle_movsi) (rtx [2])) | |
5243fbff | 3181 | { |
df86ba0c | 3182 | enum |
3183 | { | |
3184 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
3185 | } optype0, optype1; | |
5243fbff | 3186 | rtx latehalf[2]; |
df86ba0c | 3187 | rtx middlehalf[2]; |
94cfb7c6 | 3188 | rtx xops[2]; |
5243fbff | 3189 | rtx addreg0 = 0, addreg1 = 0; |
94cfb7c6 | 3190 | int dest_overlapped_low = 0; |
7b6f576a | 3191 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
df86ba0c | 3192 | |
3193 | middlehalf[0] = 0; | |
3194 | middlehalf[1] = 0; | |
5243fbff | 3195 | |
3196 | /* First classify both operands. */ | |
3197 | ||
3198 | if (REG_P (operands[0])) | |
3199 | optype0 = REGOP; | |
3200 | else if (offsettable_memref_p (operands[0])) | |
3201 | optype0 = OFFSOP; | |
3202 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
3203 | optype0 = POPOP; | |
3204 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
3205 | optype0 = PUSHOP; | |
3206 | else if (GET_CODE (operands[0]) == MEM) | |
3207 | optype0 = MEMOP; | |
3208 | else | |
3209 | optype0 = RNDOP; | |
3210 | ||
3211 | if (REG_P (operands[1])) | |
3212 | optype1 = REGOP; | |
3213 | else if (CONSTANT_P (operands[1])) | |
3214 | optype1 = CNSTOP; | |
3215 | else if (offsettable_memref_p (operands[1])) | |
3216 | optype1 = OFFSOP; | |
3217 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
3218 | optype1 = POPOP; | |
3219 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
3220 | optype1 = PUSHOP; | |
3221 | else if (GET_CODE (operands[1]) == MEM) | |
3222 | optype1 = MEMOP; | |
3223 | else | |
3224 | optype1 = RNDOP; | |
3225 | ||
84653e0f | 3226 | /* Check for the cases that the operand constraints are not supposed |
3227 | to allow to happen. Generating code for these cases is | |
3228 | painful. */ | |
3229 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
5243fbff | 3230 | |
3231 | /* If one operand is decrementing and one is incrementing | |
3232 | decrement the former register explicitly | |
3233 | and change that operand into ordinary indexing. */ | |
3234 | ||
3235 | if (optype0 == PUSHOP && optype1 == POPOP) | |
3236 | { | |
3237 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
1d86aeab | 3238 | |
3239 | handle_reg_adjust (operands[0], -size); | |
3240 | ||
df86ba0c | 3241 | if (GET_MODE (operands[1]) == XFmode) |
e6b2f841 | 3242 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
df86ba0c | 3243 | else if (GET_MODE (operands[0]) == DFmode) |
e6b2f841 | 3244 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
df86ba0c | 3245 | else |
e6b2f841 | 3246 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
5243fbff | 3247 | optype0 = OFFSOP; |
3248 | } | |
3249 | if (optype0 == POPOP && optype1 == PUSHOP) | |
3250 | { | |
3251 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
1d86aeab | 3252 | |
3253 | handle_reg_adjust (operands[1], -size); | |
3254 | ||
df86ba0c | 3255 | if (GET_MODE (operands[1]) == XFmode) |
e6b2f841 | 3256 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
df86ba0c | 3257 | else if (GET_MODE (operands[1]) == DFmode) |
e6b2f841 | 3258 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
df86ba0c | 3259 | else |
e6b2f841 | 3260 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
5243fbff | 3261 | optype1 = OFFSOP; |
3262 | } | |
3263 | ||
3264 | /* If an operand is an unoffsettable memory ref, find a register | |
3265 | we can increment temporarily to make it refer to the second word. */ | |
3266 | ||
3267 | if (optype0 == MEMOP) | |
3268 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
3269 | ||
3270 | if (optype1 == MEMOP) | |
3271 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
3272 | ||
3273 | /* Ok, we can do one word at a time. | |
3274 | Normally we do the low-numbered word first, | |
3275 | but if either operand is autodecrementing then we | |
3276 | do the high-numbered word first. | |
3277 | ||
3278 | In either case, set up in LATEHALF the operands to use | |
3279 | for the high-numbered word and in some cases alter the | |
3280 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
3281 | ||
df86ba0c | 3282 | if (size == 12) |
3283 | { | |
3284 | if (optype0 == REGOP) | |
3285 | { | |
e6b2f841 | 3286 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
3287 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
df86ba0c | 3288 | } |
3289 | else if (optype0 == OFFSOP) | |
3290 | { | |
eafc6604 | 3291 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
3292 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
df86ba0c | 3293 | } |
3294 | else | |
3295 | { | |
1d86aeab | 3296 | middlehalf[0] = adjust_address (operands[0], SImode, 0); |
3297 | latehalf[0] = adjust_address (operands[0], SImode, 0); | |
df86ba0c | 3298 | } |
3299 | ||
3300 | if (optype1 == REGOP) | |
3301 | { | |
e6b2f841 | 3302 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
3303 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
df86ba0c | 3304 | } |
3305 | else if (optype1 == OFFSOP) | |
3306 | { | |
eafc6604 | 3307 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
3308 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
df86ba0c | 3309 | } |
3310 | else if (optype1 == CNSTOP) | |
3311 | { | |
3312 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
3313 | { | |
df86ba0c | 3314 | long l[3]; |
3315 | ||
945f7b03 | 3316 | REAL_VALUE_TO_TARGET_LONG_DOUBLE |
3317 | (*CONST_DOUBLE_REAL_VALUE (operands[1]), l); | |
df86ba0c | 3318 | operands[1] = GEN_INT (l[0]); |
3319 | middlehalf[1] = GEN_INT (l[1]); | |
3320 | latehalf[1] = GEN_INT (l[2]); | |
3321 | } | |
84653e0f | 3322 | else |
df86ba0c | 3323 | { |
84653e0f | 3324 | /* No non-CONST_DOUBLE constant should ever appear |
3325 | here. */ | |
3326 | gcc_assert (!CONSTANT_P (operands[1])); | |
df86ba0c | 3327 | } |
3328 | } | |
3329 | else | |
3330 | { | |
1d86aeab | 3331 | middlehalf[1] = adjust_address (operands[1], SImode, 0); |
3332 | latehalf[1] = adjust_address (operands[1], SImode, 0); | |
df86ba0c | 3333 | } |
3334 | } | |
5243fbff | 3335 | else |
df86ba0c | 3336 | /* size is not 12: */ |
3337 | { | |
3338 | if (optype0 == REGOP) | |
e6b2f841 | 3339 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
df86ba0c | 3340 | else if (optype0 == OFFSOP) |
eafc6604 | 3341 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
df86ba0c | 3342 | else |
1d86aeab | 3343 | latehalf[0] = adjust_address (operands[0], SImode, 0); |
df86ba0c | 3344 | |
3345 | if (optype1 == REGOP) | |
e6b2f841 | 3346 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
df86ba0c | 3347 | else if (optype1 == OFFSOP) |
eafc6604 | 3348 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
df86ba0c | 3349 | else if (optype1 == CNSTOP) |
3350 | split_double (operands[1], &operands[1], &latehalf[1]); | |
3351 | else | |
1d86aeab | 3352 | latehalf[1] = adjust_address (operands[1], SImode, 0); |
df86ba0c | 3353 | } |
5243fbff | 3354 | |
7e862b4e | 3355 | /* If insn is effectively movd N(REG),-(REG) then we will do the high |
3356 | word first. We should use the adjusted operand 1 (which is N+4(REG)) | |
3357 | for the low word as well, to compensate for the first decrement of | |
3358 | REG. */ | |
5243fbff | 3359 | if (optype0 == PUSHOP |
7e862b4e | 3360 | && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1])) |
2d2c2623 | 3361 | operands[1] = middlehalf[1] = latehalf[1]; |
5243fbff | 3362 | |
94cfb7c6 | 3363 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
3364 | if the upper part of reg N does not appear in the MEM, arrange to | |
3365 | emit the move late-half first. Otherwise, compute the MEM address | |
3366 | into the upper part of N and use that as a pointer to the memory | |
3367 | operand. */ | |
3368 | if (optype0 == REGOP | |
3369 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
3370 | { | |
e6b2f841 | 3371 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
25de1190 | 3372 | |
3373 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
8867c023 | 3374 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
94cfb7c6 | 3375 | { |
3376 | /* If both halves of dest are used in the src memory address, | |
25de1190 | 3377 | compute the address into latehalf of dest. |
3378 | Note that this can't happen if the dest is two data regs. */ | |
84653e0f | 3379 | compadr: |
94cfb7c6 | 3380 | xops[0] = latehalf[0]; |
3381 | xops[1] = XEXP (operands[1], 0); | |
1d86aeab | 3382 | |
3383 | handle_compadr (xops); | |
3384 | if (GET_MODE (operands[1]) == XFmode) | |
94cfb7c6 | 3385 | { |
e6b2f841 | 3386 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
eafc6604 | 3387 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
3388 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
94cfb7c6 | 3389 | } |
3390 | else | |
3391 | { | |
e6b2f841 | 3392 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
eafc6604 | 3393 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
94cfb7c6 | 3394 | } |
3395 | } | |
3396 | else if (size == 12 | |
8867c023 | 3397 | && reg_overlap_mentioned_p (middlehalf[0], |
3398 | XEXP (operands[1], 0))) | |
94cfb7c6 | 3399 | { |
25de1190 | 3400 | /* Check for two regs used by both source and dest. |
3401 | Note that this can't happen if the dest is all data regs. | |
3402 | It can happen if the dest is d6, d7, a0. | |
3403 | But in that case, latehalf is an addr reg, so | |
3404 | the code at compadr does ok. */ | |
3405 | ||
3406 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
8867c023 | 3407 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
3408 | goto compadr; | |
94cfb7c6 | 3409 | |
3410 | /* JRV says this can't happen: */ | |
84653e0f | 3411 | gcc_assert (!addreg0 && !addreg1); |
94cfb7c6 | 3412 | |
0c0492c9 | 3413 | /* Only the middle reg conflicts; simply put it last. */ |
1d86aeab | 3414 | handle_movsi (operands); |
3415 | handle_movsi (latehalf); | |
3416 | handle_movsi (middlehalf); | |
3417 | ||
3418 | return; | |
94cfb7c6 | 3419 | } |
f9ec812b | 3420 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
94cfb7c6 | 3421 | /* If the low half of dest is mentioned in the source memory |
3422 | address, the arrange to emit the move late half first. */ | |
3423 | dest_overlapped_low = 1; | |
3424 | } | |
3425 | ||
5243fbff | 3426 | /* If one or both operands autodecrementing, |
3427 | do the two words, high-numbered first. */ | |
3428 | ||
3429 | /* Likewise, the first move would clobber the source of the second one, | |
3430 | do them in the other order. This happens only for registers; | |
3431 | such overlap can't happen in memory unless the user explicitly | |
3432 | sets it up, and that is an undefined circumstance. */ | |
3433 | ||
3434 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
3435 | || (optype0 == REGOP && optype1 == REGOP | |
df86ba0c | 3436 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
94cfb7c6 | 3437 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
3438 | || dest_overlapped_low) | |
5243fbff | 3439 | { |
3440 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
3441 | if (addreg0) | |
1d86aeab | 3442 | handle_reg_adjust (addreg0, size - 4); |
5243fbff | 3443 | if (addreg1) |
1d86aeab | 3444 | handle_reg_adjust (addreg1, size - 4); |
5243fbff | 3445 | |
3446 | /* Do that word. */ | |
1d86aeab | 3447 | handle_movsi (latehalf); |
5243fbff | 3448 | |
3449 | /* Undo the adds we just did. */ | |
3450 | if (addreg0) | |
1d86aeab | 3451 | handle_reg_adjust (addreg0, -4); |
5243fbff | 3452 | if (addreg1) |
1d86aeab | 3453 | handle_reg_adjust (addreg1, -4); |
5243fbff | 3454 | |
df86ba0c | 3455 | if (size == 12) |
3456 | { | |
1d86aeab | 3457 | handle_movsi (middlehalf); |
3458 | ||
df86ba0c | 3459 | if (addreg0) |
1d86aeab | 3460 | handle_reg_adjust (addreg0, -4); |
df86ba0c | 3461 | if (addreg1) |
1d86aeab | 3462 | handle_reg_adjust (addreg1, -4); |
df86ba0c | 3463 | } |
3464 | ||
5243fbff | 3465 | /* Do low-numbered word. */ |
1d86aeab | 3466 | |
3467 | handle_movsi (operands); | |
3468 | return; | |
5243fbff | 3469 | } |
3470 | ||
3471 | /* Normal case: do the two words, low-numbered first. */ | |
3472 | ||
5734a3c5 | 3473 | m68k_final_prescan_insn (NULL, operands, 2); |
1d86aeab | 3474 | handle_movsi (operands); |
5243fbff | 3475 | |
df86ba0c | 3476 | /* Do the middle one of the three words for long double */ |
3477 | if (size == 12) | |
3478 | { | |
3479 | if (addreg0) | |
1d86aeab | 3480 | handle_reg_adjust (addreg0, 4); |
df86ba0c | 3481 | if (addreg1) |
1d86aeab | 3482 | handle_reg_adjust (addreg1, 4); |
df86ba0c | 3483 | |
5734a3c5 | 3484 | m68k_final_prescan_insn (NULL, middlehalf, 2); |
1d86aeab | 3485 | handle_movsi (middlehalf); |
df86ba0c | 3486 | } |
3487 | ||
5243fbff | 3488 | /* Make any unoffsettable addresses point at high-numbered word. */ |
3489 | if (addreg0) | |
1d86aeab | 3490 | handle_reg_adjust (addreg0, 4); |
5243fbff | 3491 | if (addreg1) |
1d86aeab | 3492 | handle_reg_adjust (addreg1, 4); |
5243fbff | 3493 | |
3494 | /* Do that word. */ | |
5734a3c5 | 3495 | m68k_final_prescan_insn (NULL, latehalf, 2); |
1d86aeab | 3496 | handle_movsi (latehalf); |
5243fbff | 3497 | |
3498 | /* Undo the adds we just did. */ | |
3499 | if (addreg0) | |
1d86aeab | 3500 | handle_reg_adjust (addreg0, -(size - 4)); |
3501 | if (addreg1) | |
3502 | handle_reg_adjust (addreg1, -(size - 4)); | |
3503 | ||
3504 | return; | |
3505 | } | |
3506 | ||
3507 | /* Output assembler code to adjust REG by N. */ | |
3508 | static void | |
3509 | output_reg_adjust (rtx reg, int n) | |
3510 | { | |
3511 | const char *s; | |
3512 | ||
3513 | gcc_assert (GET_MODE (reg) == SImode | |
3514 | && -12 <= n && n != 0 && n <= 12); | |
3515 | ||
3516 | switch (n) | |
df86ba0c | 3517 | { |
1d86aeab | 3518 | case 12: |
3519 | s = "add%.l #12,%0"; | |
3520 | break; | |
3521 | ||
3522 | case 8: | |
3523 | s = "addq%.l #8,%0"; | |
3524 | break; | |
3525 | ||
3526 | case 4: | |
3527 | s = "addq%.l #4,%0"; | |
3528 | break; | |
3529 | ||
3530 | case -12: | |
3531 | s = "sub%.l #12,%0"; | |
3532 | break; | |
3533 | ||
3534 | case -8: | |
3535 | s = "subq%.l #8,%0"; | |
3536 | break; | |
3537 | ||
3538 | case -4: | |
3539 | s = "subq%.l #4,%0"; | |
3540 | break; | |
3541 | ||
3542 | default: | |
3543 | gcc_unreachable (); | |
3544 | s = NULL; | |
df86ba0c | 3545 | } |
1d86aeab | 3546 | |
3547 | output_asm_insn (s, ®); | |
3548 | } | |
3549 | ||
3550 | /* Emit rtl code to adjust REG by N. */ | |
3551 | static void | |
3552 | emit_reg_adjust (rtx reg1, int n) | |
3553 | { | |
3554 | rtx reg2; | |
3555 | ||
3556 | gcc_assert (GET_MODE (reg1) == SImode | |
3557 | && -12 <= n && n != 0 && n <= 12); | |
3558 | ||
3559 | reg1 = copy_rtx (reg1); | |
3560 | reg2 = copy_rtx (reg1); | |
3561 | ||
3562 | if (n < 0) | |
3563 | emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n))); | |
3564 | else if (n > 0) | |
3565 | emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n))); | |
3566 | else | |
3567 | gcc_unreachable (); | |
3568 | } | |
3569 | ||
3570 | /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */ | |
3571 | static void | |
3572 | output_compadr (rtx operands[2]) | |
3573 | { | |
3574 | output_asm_insn ("lea %a1,%0", operands); | |
3575 | } | |
3576 | ||
3577 | /* Output the best assembler insn for moving operands[1] into operands[0] | |
3578 | as a fullword. */ | |
3579 | static void | |
3580 | output_movsi (rtx operands[2]) | |
3581 | { | |
3582 | output_asm_insn (singlemove_string (operands), operands); | |
3583 | } | |
3584 | ||
3585 | /* Copy OP and change its mode to MODE. */ | |
3586 | static rtx | |
3754d046 | 3587 | copy_operand (rtx op, machine_mode mode) |
1d86aeab | 3588 | { |
3589 | /* ??? This looks really ugly. There must be a better way | |
3590 | to change a mode on the operand. */ | |
3591 | if (GET_MODE (op) != VOIDmode) | |
df86ba0c | 3592 | { |
1d86aeab | 3593 | if (REG_P (op)) |
3594 | op = gen_rtx_REG (mode, REGNO (op)); | |
df86ba0c | 3595 | else |
1d86aeab | 3596 | { |
3597 | op = copy_rtx (op); | |
3598 | PUT_MODE (op, mode); | |
3599 | } | |
df86ba0c | 3600 | } |
5243fbff | 3601 | |
1d86aeab | 3602 | return op; |
3603 | } | |
3604 | ||
3605 | /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */ | |
3606 | static void | |
3607 | emit_movsi (rtx operands[2]) | |
3608 | { | |
3609 | operands[0] = copy_operand (operands[0], SImode); | |
3610 | operands[1] = copy_operand (operands[1], SImode); | |
3611 | ||
3612 | emit_insn (gen_movsi (operands[0], operands[1])); | |
3613 | } | |
3614 | ||
3615 | /* Output assembler code to perform a doubleword move insn | |
3616 | with operands OPERANDS. */ | |
3617 | const char * | |
3618 | output_move_double (rtx *operands) | |
3619 | { | |
3620 | handle_move_double (operands, | |
3621 | output_reg_adjust, output_compadr, output_movsi); | |
3622 | ||
5243fbff | 3623 | return ""; |
3624 | } | |
3625 | ||
1d86aeab | 3626 | /* Output rtl code to perform a doubleword move insn |
3627 | with operands OPERANDS. */ | |
3628 | void | |
3629 | m68k_emit_move_double (rtx operands[2]) | |
3630 | { | |
3631 | handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi); | |
3632 | } | |
58c23110 | 3633 | |
3634 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
3635 | new rtx with the correct mode. */ | |
3636 | ||
3637 | static rtx | |
3754d046 | 3638 | force_mode (machine_mode mode, rtx orig) |
58c23110 | 3639 | { |
3640 | if (mode == GET_MODE (orig)) | |
3641 | return orig; | |
3642 | ||
3643 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
3644 | abort (); | |
3645 | ||
3646 | return gen_rtx_REG (mode, REGNO (orig)); | |
3647 | } | |
3648 | ||
3649 | static int | |
3754d046 | 3650 | fp_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
58c23110 | 3651 | { |
3652 | return reg_renumber && FP_REG_P (op); | |
3653 | } | |
3654 | ||
3655 | /* Emit insns to move operands[1] into operands[0]. | |
3656 | ||
3657 | Return 1 if we have written out everything that needs to be done to | |
3658 | do the move. Otherwise, return 0 and the caller will emit the move | |
3659 | normally. | |
3660 | ||
3661 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
334ec2d8 | 3662 | will be used. This routine is responsible for creating a new copy |
58c23110 | 3663 | of SCRATCH_REG in the proper mode. */ |
3664 | ||
3665 | int | |
3754d046 | 3666 | emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) |
58c23110 | 3667 | { |
3668 | register rtx operand0 = operands[0]; | |
3669 | register rtx operand1 = operands[1]; | |
3670 | register rtx tem; | |
3671 | ||
3672 | if (scratch_reg | |
3673 | && reload_in_progress && GET_CODE (operand0) == REG | |
3674 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
1c654ff1 | 3675 | operand0 = reg_equiv_mem (REGNO (operand0)); |
58c23110 | 3676 | else if (scratch_reg |
3677 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
3678 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
3679 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
3680 | { | |
3681 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
3682 | the code which tracks sets/uses for delete_output_reload. */ | |
3683 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1c654ff1 | 3684 | reg_equiv_mem (REGNO (SUBREG_REG (operand0))), |
58c23110 | 3685 | SUBREG_BYTE (operand0)); |
c6a6cdaa | 3686 | operand0 = alter_subreg (&temp, true); |
58c23110 | 3687 | } |
3688 | ||
3689 | if (scratch_reg | |
3690 | && reload_in_progress && GET_CODE (operand1) == REG | |
3691 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
1c654ff1 | 3692 | operand1 = reg_equiv_mem (REGNO (operand1)); |
58c23110 | 3693 | else if (scratch_reg |
3694 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
3695 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
3696 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
3697 | { | |
3698 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
3699 | the code which tracks sets/uses for delete_output_reload. */ | |
3700 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1c654ff1 | 3701 | reg_equiv_mem (REGNO (SUBREG_REG (operand1))), |
58c23110 | 3702 | SUBREG_BYTE (operand1)); |
c6a6cdaa | 3703 | operand1 = alter_subreg (&temp, true); |
58c23110 | 3704 | } |
3705 | ||
3706 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
3707 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
3708 | != XEXP (operand0, 0))) | |
3709 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
3710 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
3711 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
3712 | != XEXP (operand1, 0))) | |
3713 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
3714 | ||
3715 | /* Handle secondary reloads for loads/stores of FP registers where | |
3716 | the address is symbolic by using the scratch register */ | |
3717 | if (fp_reg_operand (operand0, mode) | |
3718 | && ((GET_CODE (operand1) == MEM | |
3719 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
3720 | || ((GET_CODE (operand1) == SUBREG | |
3721 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
3722 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
3723 | && scratch_reg) | |
3724 | { | |
3725 | if (GET_CODE (operand1) == SUBREG) | |
3726 | operand1 = XEXP (operand1, 0); | |
3727 | ||
3728 | /* SCRATCH_REG will hold an address. We want | |
3729 | it in SImode regardless of what mode it was originally given | |
3730 | to us. */ | |
3731 | scratch_reg = force_mode (SImode, scratch_reg); | |
3732 | ||
3733 | /* D might not fit in 14 bits either; for such cases load D into | |
3734 | scratch reg. */ | |
3735 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
3736 | { | |
3737 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
3738 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
3739 | Pmode, | |
3740 | XEXP (XEXP (operand1, 0), 0), | |
3741 | scratch_reg)); | |
3742 | } | |
3743 | else | |
3744 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
d1f9b275 | 3745 | emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg))); |
58c23110 | 3746 | return 1; |
3747 | } | |
3748 | else if (fp_reg_operand (operand1, mode) | |
3749 | && ((GET_CODE (operand0) == MEM | |
3750 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
3751 | || ((GET_CODE (operand0) == SUBREG) | |
3752 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
3753 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
3754 | && scratch_reg) | |
3755 | { | |
3756 | if (GET_CODE (operand0) == SUBREG) | |
3757 | operand0 = XEXP (operand0, 0); | |
3758 | ||
3759 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3760 | it in SIMODE regardless of what mode it was originally given | |
3761 | to us. */ | |
3762 | scratch_reg = force_mode (SImode, scratch_reg); | |
3763 | ||
3764 | /* D might not fit in 14 bits either; for such cases load D into | |
3765 | scratch reg. */ | |
3766 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
3767 | { | |
3768 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
3769 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
3770 | 0)), | |
3771 | Pmode, | |
3772 | XEXP (XEXP (operand0, 0), | |
3773 | 0), | |
3774 | scratch_reg)); | |
3775 | } | |
3776 | else | |
3777 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
d1f9b275 | 3778 | emit_insn (gen_rtx_SET (gen_rtx_MEM (mode, scratch_reg), operand1)); |
58c23110 | 3779 | return 1; |
3780 | } | |
3781 | /* Handle secondary reloads for loads of FP registers from constant | |
3782 | expressions by forcing the constant into memory. | |
3783 | ||
3784 | use scratch_reg to hold the address of the memory location. | |
3785 | ||
3786 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
3787 | NO_REGS when presented with a const_int and an register class | |
3788 | containing only FP registers. Doing so unfortunately creates | |
3789 | more problems than it solves. Fix this for 2.5. */ | |
3790 | else if (fp_reg_operand (operand0, mode) | |
3791 | && CONSTANT_P (operand1) | |
3792 | && scratch_reg) | |
3793 | { | |
3794 | rtx xoperands[2]; | |
3795 | ||
3796 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3797 | it in SIMODE regardless of what mode it was originally given | |
3798 | to us. */ | |
3799 | scratch_reg = force_mode (SImode, scratch_reg); | |
3800 | ||
3801 | /* Force the constant into memory and put the address of the | |
3802 | memory location into scratch_reg. */ | |
3803 | xoperands[0] = scratch_reg; | |
3804 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
d1f9b275 | 3805 | emit_insn (gen_rtx_SET (scratch_reg, xoperands[1])); |
58c23110 | 3806 | |
3807 | /* Now load the destination register. */ | |
d1f9b275 | 3808 | emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg))); |
58c23110 | 3809 | return 1; |
3810 | } | |
3811 | ||
3812 | /* Now have insn-emit do whatever it normally does. */ | |
3813 | return 0; | |
3814 | } | |
3815 | ||
8ec9650e | 3816 | /* Split one or more DImode RTL references into pairs of SImode |
3817 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
3818 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
3819 | split and "num" is its length. lo_half and hi_half are output arrays | |
3820 | that parallel "operands". */ | |
3821 | ||
3822 | void | |
3823 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
3824 | { | |
3825 | while (num--) | |
3826 | { | |
3827 | rtx op = operands[num]; | |
3828 | ||
3829 | /* simplify_subreg refuses to split volatile memory addresses, | |
3830 | but we still have to handle it. */ | |
3831 | if (GET_CODE (op) == MEM) | |
3832 | { | |
3833 | lo_half[num] = adjust_address (op, SImode, 4); | |
3834 | hi_half[num] = adjust_address (op, SImode, 0); | |
3835 | } | |
3836 | else | |
3837 | { | |
3838 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
3839 | GET_MODE (op) == VOIDmode | |
3840 | ? DImode : GET_MODE (op), 4); | |
3841 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
3842 | GET_MODE (op) == VOIDmode | |
3843 | ? DImode : GET_MODE (op), 0); | |
3844 | } | |
3845 | } | |
3846 | } | |
3847 | ||
9c47decb | 3848 | /* Split X into a base and a constant offset, storing them in *BASE |
3849 | and *OFFSET respectively. */ | |
3850 | ||
3851 | static void | |
3852 | m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) | |
3853 | { | |
3854 | *offset = 0; | |
3855 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3856 | { | |
3857 | *offset += INTVAL (XEXP (x, 1)); | |
3858 | x = XEXP (x, 0); | |
3859 | } | |
3860 | *base = x; | |
3861 | } | |
3862 | ||
3863 | /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem | |
3864 | instruction. STORE_P says whether the move is a load or store. | |
3865 | ||
3866 | If the instruction uses post-increment or pre-decrement addressing, | |
3867 | AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total | |
3868 | adjustment. This adjustment will be made by the first element of | |
3869 | PARALLEL, with the loads or stores starting at element 1. If the | |
3870 | instruction does not use post-increment or pre-decrement addressing, | |
3871 | AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores | |
3872 | start at element 0. */ | |
3873 | ||
3874 | bool | |
3875 | m68k_movem_pattern_p (rtx pattern, rtx automod_base, | |
3876 | HOST_WIDE_INT automod_offset, bool store_p) | |
3877 | { | |
3878 | rtx base, mem_base, set, mem, reg, last_reg; | |
3879 | HOST_WIDE_INT offset, mem_offset; | |
3880 | int i, first, len; | |
3881 | enum reg_class rclass; | |
3882 | ||
3883 | len = XVECLEN (pattern, 0); | |
3884 | first = (automod_base != NULL); | |
3885 | ||
3886 | if (automod_base) | |
3887 | { | |
3888 | /* Stores must be pre-decrement and loads must be post-increment. */ | |
3889 | if (store_p != (automod_offset < 0)) | |
3890 | return false; | |
3891 | ||
3892 | /* Work out the base and offset for lowest memory location. */ | |
3893 | base = automod_base; | |
3894 | offset = (automod_offset < 0 ? automod_offset : 0); | |
3895 | } | |
3896 | else | |
3897 | { | |
3898 | /* Allow any valid base and offset in the first access. */ | |
3899 | base = NULL; | |
3900 | offset = 0; | |
3901 | } | |
3902 | ||
3903 | last_reg = NULL; | |
3904 | rclass = NO_REGS; | |
3905 | for (i = first; i < len; i++) | |
3906 | { | |
3907 | /* We need a plain SET. */ | |
3908 | set = XVECEXP (pattern, 0, i); | |
3909 | if (GET_CODE (set) != SET) | |
3910 | return false; | |
3911 | ||
3912 | /* Check that we have a memory location... */ | |
3913 | mem = XEXP (set, !store_p); | |
3914 | if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) | |
3915 | return false; | |
3916 | ||
3917 | /* ...with the right address. */ | |
3918 | if (base == NULL) | |
3919 | { | |
3920 | m68k_split_offset (XEXP (mem, 0), &base, &offset); | |
3921 | /* The ColdFire instruction only allows (An) and (d16,An) modes. | |
3922 | There are no mode restrictions for 680x0 besides the | |
3923 | automodification rules enforced above. */ | |
3924 | if (TARGET_COLDFIRE | |
3925 | && !m68k_legitimate_base_reg_p (base, reload_completed)) | |
3926 | return false; | |
3927 | } | |
3928 | else | |
3929 | { | |
3930 | m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); | |
3931 | if (!rtx_equal_p (base, mem_base) || offset != mem_offset) | |
3932 | return false; | |
3933 | } | |
3934 | ||
3935 | /* Check that we have a register of the required mode and class. */ | |
3936 | reg = XEXP (set, store_p); | |
3937 | if (!REG_P (reg) | |
3938 | || !HARD_REGISTER_P (reg) | |
3939 | || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) | |
3940 | return false; | |
3941 | ||
3942 | if (last_reg) | |
3943 | { | |
3944 | /* The register must belong to RCLASS and have a higher number | |
3945 | than the register in the previous SET. */ | |
3946 | if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) | |
3947 | || REGNO (last_reg) >= REGNO (reg)) | |
3948 | return false; | |
3949 | } | |
3950 | else | |
3951 | { | |
3952 | /* Work out which register class we need. */ | |
3953 | if (INT_REGNO_P (REGNO (reg))) | |
3954 | rclass = GENERAL_REGS; | |
3955 | else if (FP_REGNO_P (REGNO (reg))) | |
3956 | rclass = FP_REGS; | |
3957 | else | |
3958 | return false; | |
3959 | } | |
3960 | ||
3961 | last_reg = reg; | |
3962 | offset += GET_MODE_SIZE (GET_MODE (reg)); | |
3963 | } | |
3964 | ||
3965 | /* If we have an automodification, check whether the final offset is OK. */ | |
3966 | if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) | |
3967 | return false; | |
3968 | ||
3969 | /* Reject unprofitable cases. */ | |
3970 | if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) | |
3971 | return false; | |
3972 | ||
3973 | return true; | |
3974 | } | |
3975 | ||
3976 | /* Return the assembly code template for a movem or fmovem instruction | |
3977 | whose pattern is given by PATTERN. Store the template's operands | |
3978 | in OPERANDS. | |
3979 | ||
3980 | If the instruction uses post-increment or pre-decrement addressing, | |
3981 | AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P | |
3982 | is true if this is a store instruction. */ | |
3983 | ||
3984 | const char * | |
3985 | m68k_output_movem (rtx *operands, rtx pattern, | |
3986 | HOST_WIDE_INT automod_offset, bool store_p) | |
3987 | { | |
3988 | unsigned int mask; | |
3989 | int i, first; | |
3990 | ||
3991 | gcc_assert (GET_CODE (pattern) == PARALLEL); | |
3992 | mask = 0; | |
3993 | first = (automod_offset != 0); | |
3994 | for (i = first; i < XVECLEN (pattern, 0); i++) | |
3995 | { | |
3996 | /* When using movem with pre-decrement addressing, register X + D0_REG | |
3997 | is controlled by bit 15 - X. For all other addressing modes, | |
3998 | register X + D0_REG is controlled by bit X. Confusingly, the | |
3999 | register mask for fmovem is in the opposite order to that for | |
4000 | movem. */ | |
4001 | unsigned int regno; | |
4002 | ||
4003 | gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); | |
4004 | gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); | |
4005 | regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); | |
4006 | if (automod_offset < 0) | |
4007 | { | |
4008 | if (FP_REGNO_P (regno)) | |
4009 | mask |= 1 << (regno - FP0_REG); | |
4010 | else | |
4011 | mask |= 1 << (15 - (regno - D0_REG)); | |
4012 | } | |
4013 | else | |
4014 | { | |
4015 | if (FP_REGNO_P (regno)) | |
4016 | mask |= 1 << (7 - (regno - FP0_REG)); | |
4017 | else | |
4018 | mask |= 1 << (regno - D0_REG); | |
4019 | } | |
4020 | } | |
4021 | CC_STATUS_INIT; | |
4022 | ||
4023 | if (automod_offset == 0) | |
4024 | operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); | |
4025 | else if (automod_offset < 0) | |
4026 | operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
4027 | else | |
4028 | operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
4029 | operands[1] = GEN_INT (mask); | |
4030 | if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) | |
4031 | { | |
4032 | if (store_p) | |
97747e65 | 4033 | return "fmovem %1,%a0"; |
9c47decb | 4034 | else |
97747e65 | 4035 | return "fmovem %a0,%1"; |
9c47decb | 4036 | } |
4037 | else | |
4038 | { | |
4039 | if (store_p) | |
97747e65 | 4040 | return "movem%.l %1,%a0"; |
9c47decb | 4041 | else |
97747e65 | 4042 | return "movem%.l %a0,%1"; |
9c47decb | 4043 | } |
4044 | } | |
4045 | ||
5243fbff | 4046 | /* Return a REG that occurs in ADDR with coefficient 1. |
4047 | ADDR can be effectively incremented by incrementing REG. */ | |
4048 | ||
4049 | static rtx | |
821960c7 | 4050 | find_addr_reg (rtx addr) |
5243fbff | 4051 | { |
4052 | while (GET_CODE (addr) == PLUS) | |
4053 | { | |
4054 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
4055 | addr = XEXP (addr, 0); | |
4056 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
4057 | addr = XEXP (addr, 1); | |
4058 | else if (CONSTANT_P (XEXP (addr, 0))) | |
4059 | addr = XEXP (addr, 1); | |
4060 | else if (CONSTANT_P (XEXP (addr, 1))) | |
4061 | addr = XEXP (addr, 0); | |
4062 | else | |
84653e0f | 4063 | gcc_unreachable (); |
5243fbff | 4064 | } |
84653e0f | 4065 | gcc_assert (GET_CODE (addr) == REG); |
4066 | return addr; | |
5243fbff | 4067 | } |
ee808824 | 4068 | |
b14b4511 | 4069 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
ee808824 | 4070 | |
f2fa409d | 4071 | const char * |
821960c7 | 4072 | output_addsi3 (rtx *operands) |
ee808824 | 4073 | { |
4074 | if (! operands_match_p (operands[0], operands[1])) | |
4075 | { | |
4076 | if (!ADDRESS_REG_P (operands[1])) | |
4077 | { | |
4078 | rtx tmp = operands[1]; | |
4079 | ||
4080 | operands[1] = operands[2]; | |
4081 | operands[2] = tmp; | |
4082 | } | |
4083 | ||
4084 | /* These insns can result from reloads to access | |
4085 | stack slots over 64k from the frame pointer. */ | |
4086 | if (GET_CODE (operands[2]) == CONST_INT | |
5a6901d6 | 4087 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
af6ca061 | 4088 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
ee808824 | 4089 | if (GET_CODE (operands[2]) == REG) |
4ad53767 | 4090 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
4091 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
ee808824 | 4092 | } |
4093 | if (GET_CODE (operands[2]) == CONST_INT) | |
4094 | { | |
ee808824 | 4095 | if (INTVAL (operands[2]) > 0 |
4096 | && INTVAL (operands[2]) <= 8) | |
4097 | return "addq%.l %2,%0"; | |
4098 | if (INTVAL (operands[2]) < 0 | |
4099 | && INTVAL (operands[2]) >= -8) | |
4100 | { | |
7014838c | 4101 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
ee808824 | 4102 | return "subq%.l %2,%0"; |
4103 | } | |
4104 | /* On the CPU32 it is faster to use two addql instructions to | |
4105 | add a small integer (8 < N <= 16) to a register. | |
0c0492c9 | 4106 | Likewise for subql. */ |
bd40163f | 4107 | if (TUNE_CPU32 && REG_P (operands[0])) |
ee808824 | 4108 | { |
4109 | if (INTVAL (operands[2]) > 8 | |
4110 | && INTVAL (operands[2]) <= 16) | |
4111 | { | |
e6b2f841 | 4112 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3acc77d9 | 4113 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
ee808824 | 4114 | } |
4115 | if (INTVAL (operands[2]) < -8 | |
4116 | && INTVAL (operands[2]) >= -16) | |
4117 | { | |
7014838c | 4118 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3acc77d9 | 4119 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
ee808824 | 4120 | } |
4121 | } | |
ee808824 | 4122 | if (ADDRESS_REG_P (operands[0]) |
4123 | && INTVAL (operands[2]) >= -0x8000 | |
4124 | && INTVAL (operands[2]) < 0x8000) | |
4125 | { | |
bd40163f | 4126 | if (TUNE_68040) |
ee808824 | 4127 | return "add%.w %2,%0"; |
4128 | else | |
4ad53767 | 4129 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
ee808824 | 4130 | } |
4131 | } | |
4132 | return "add%.l %2,%0"; | |
4133 | } | |
5243fbff | 4134 | \f |
4135 | /* Store in cc_status the expressions that the condition codes will | |
4136 | describe after execution of an instruction whose pattern is EXP. | |
4137 | Do not alter them if the instruction would not alter the cc's. */ | |
4138 | ||
4139 | /* On the 68000, all the insns to store in an address register fail to | |
4140 | set the cc's. However, in some cases these instructions can make it | |
4141 | possibly invalid to use the saved cc's. In those cases we clear out | |
4142 | some or all of the saved cc's so they won't be used. */ | |
4143 | ||
e6b2f841 | 4144 | void |
821960c7 | 4145 | notice_update_cc (rtx exp, rtx insn) |
5243fbff | 4146 | { |
d2e633d7 | 4147 | if (GET_CODE (exp) == SET) |
5243fbff | 4148 | { |
4149 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
065b42aa | 4150 | CC_STATUS_INIT; |
5243fbff | 4151 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
4152 | { | |
c5aa1e92 | 4153 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
5243fbff | 4154 | cc_status.value1 = 0; |
c5aa1e92 | 4155 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
5243fbff | 4156 | cc_status.value2 = 0; |
4157 | } | |
12e6817c | 4158 | /* fmoves to memory or data registers do not set the condition |
4159 | codes. Normal moves _do_ set the condition codes, but not in | |
4160 | a way that is appropriate for comparison with 0, because -0.0 | |
4161 | would be treated as a negative nonzero number. Note that it | |
0d424440 | 4162 | isn't appropriate to conditionalize this restriction on |
12e6817c | 4163 | HONOR_SIGNED_ZEROS because that macro merely indicates whether |
4164 | we care about the difference between -0.0 and +0.0. */ | |
5243fbff | 4165 | else if (!FP_REG_P (SET_DEST (exp)) |
4166 | && SET_DEST (exp) != cc0_rtx | |
4167 | && (FP_REG_P (SET_SRC (exp)) | |
4168 | || GET_CODE (SET_SRC (exp)) == FIX | |
12e6817c | 4169 | || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) |
065b42aa | 4170 | CC_STATUS_INIT; |
5243fbff | 4171 | /* A pair of move insns doesn't produce a useful overall cc. */ |
4172 | else if (!FP_REG_P (SET_DEST (exp)) | |
4173 | && !FP_REG_P (SET_SRC (exp)) | |
4174 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
4175 | && (GET_CODE (SET_SRC (exp)) == REG | |
4176 | || GET_CODE (SET_SRC (exp)) == MEM | |
4177 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
065b42aa | 4178 | CC_STATUS_INIT; |
e16bddab | 4179 | else if (SET_DEST (exp) != pc_rtx) |
5243fbff | 4180 | { |
4181 | cc_status.flags = 0; | |
e16bddab | 4182 | cc_status.value1 = SET_DEST (exp); |
4183 | cc_status.value2 = SET_SRC (exp); | |
5243fbff | 4184 | } |
4185 | } | |
4186 | else if (GET_CODE (exp) == PARALLEL | |
4187 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
4188 | { | |
e16bddab | 4189 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
4190 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
4191 | ||
4192 | if (ADDRESS_REG_P (dest)) | |
5243fbff | 4193 | CC_STATUS_INIT; |
e16bddab | 4194 | else if (dest != pc_rtx) |
5243fbff | 4195 | { |
4196 | cc_status.flags = 0; | |
e16bddab | 4197 | cc_status.value1 = dest; |
4198 | cc_status.value2 = src; | |
5243fbff | 4199 | } |
4200 | } | |
4201 | else | |
4202 | CC_STATUS_INIT; | |
4203 | if (cc_status.value2 != 0 | |
4204 | && ADDRESS_REG_P (cc_status.value2) | |
4205 | && GET_MODE (cc_status.value2) == QImode) | |
4206 | CC_STATUS_INIT; | |
d2e633d7 | 4207 | if (cc_status.value2 != 0) |
5243fbff | 4208 | switch (GET_CODE (cc_status.value2)) |
4209 | { | |
9c532fac | 4210 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
5243fbff | 4211 | case ROTATE: case ROTATERT: |
64b70d26 | 4212 | /* These instructions always clear the overflow bit, and set |
4213 | the carry to the bit shifted out. */ | |
bf7cf42a | 4214 | cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; |
64b70d26 | 4215 | break; |
4216 | ||
4217 | case PLUS: case MINUS: case MULT: | |
4218 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
5243fbff | 4219 | if (GET_MODE (cc_status.value2) != VOIDmode) |
4220 | cc_status.flags |= CC_NO_OVERFLOW; | |
4221 | break; | |
4222 | case ZERO_EXTEND: | |
4223 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
4224 | ends with a move insn moving r2 in r2's mode. | |
4225 | Thus, the cc's are set for r2. | |
0c0492c9 | 4226 | This can set N bit spuriously. */ |
5243fbff | 4227 | cc_status.flags |= CC_NOT_NEGATIVE; |
e6b2f841 | 4228 | |
4229 | default: | |
4230 | break; | |
5243fbff | 4231 | } |
4232 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
4233 | && cc_status.value2 | |
4234 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
4235 | cc_status.value2 = 0; | |
910f39df | 4236 | /* Check for PRE_DEC in dest modifying a register used in src. */ |
4237 | if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM | |
4238 | && GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC | |
4239 | && cc_status.value2 | |
4240 | && reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0), | |
4241 | cc_status.value2)) | |
4242 | cc_status.value2 = 0; | |
5243fbff | 4243 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) |
d2e633d7 | 4244 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
5243fbff | 4245 | cc_status.flags = CC_IN_68881; |
e680c1ac | 4246 | if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE |
4247 | && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT) | |
4248 | { | |
4249 | cc_status.flags = CC_IN_68881; | |
c1aa8817 | 4250 | if (!FP_REG_P (XEXP (cc_status.value2, 0)) |
4251 | && FP_REG_P (XEXP (cc_status.value2, 1))) | |
e680c1ac | 4252 | cc_status.flags |= CC_REVERSED; |
4253 | } | |
5243fbff | 4254 | } |
4255 | \f | |
f2fa409d | 4256 | const char * |
821960c7 | 4257 | output_move_const_double (rtx *operands) |
5243fbff | 4258 | { |
d2e633d7 | 4259 | int code = standard_68881_constant_p (operands[1]); |
5243fbff | 4260 | |
d2e633d7 | 4261 | if (code != 0) |
5243fbff | 4262 | { |
d2e633d7 | 4263 | static char buf[40]; |
5243fbff | 4264 | |
3acc77d9 | 4265 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
d2e633d7 | 4266 | return buf; |
5243fbff | 4267 | } |
d2e633d7 | 4268 | return "fmove%.d %1,%0"; |
5243fbff | 4269 | } |
4270 | ||
f2fa409d | 4271 | const char * |
821960c7 | 4272 | output_move_const_single (rtx *operands) |
5243fbff | 4273 | { |
d2e633d7 | 4274 | int code = standard_68881_constant_p (operands[1]); |
5243fbff | 4275 | |
d2e633d7 | 4276 | if (code != 0) |
5243fbff | 4277 | { |
d2e633d7 | 4278 | static char buf[40]; |
5243fbff | 4279 | |
3acc77d9 | 4280 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
d2e633d7 | 4281 | return buf; |
5243fbff | 4282 | } |
d2e633d7 | 4283 | return "fmove%.s %f1,%0"; |
5243fbff | 4284 | } |
4285 | ||
4286 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
4287 | from the "fmovecr" instruction. | |
4288 | The value, anded with 0xff, gives the code to use in fmovecr | |
4289 | to get the desired constant. */ | |
4290 | ||
0c0492c9 | 4291 | /* This code has been fixed for cross-compilation. */ |
6205ab4b | 4292 | |
4293 | static int inited_68881_table = 0; | |
4294 | ||
f2fa409d | 4295 | static const char *const strings_68881[7] = { |
6205ab4b | 4296 | "0.0", |
4297 | "1.0", | |
4298 | "10.0", | |
4299 | "100.0", | |
4300 | "10000.0", | |
4301 | "1e8", | |
4302 | "1e16" | |
065b42aa | 4303 | }; |
6205ab4b | 4304 | |
e99c3a1d | 4305 | static const int codes_68881[7] = { |
6205ab4b | 4306 | 0x0f, |
4307 | 0x32, | |
4308 | 0x33, | |
4309 | 0x34, | |
4310 | 0x35, | |
4311 | 0x36, | |
4312 | 0x37 | |
065b42aa | 4313 | }; |
6205ab4b | 4314 | |
4315 | REAL_VALUE_TYPE values_68881[7]; | |
4316 | ||
4317 | /* Set up values_68881 array by converting the decimal values | |
0c0492c9 | 4318 | strings_68881 to binary. */ |
6205ab4b | 4319 | |
4320 | void | |
821960c7 | 4321 | init_68881_table (void) |
6205ab4b | 4322 | { |
4323 | int i; | |
4324 | REAL_VALUE_TYPE r; | |
3754d046 | 4325 | machine_mode mode; |
6205ab4b | 4326 | |
6a4dac78 | 4327 | mode = SFmode; |
6205ab4b | 4328 | for (i = 0; i < 7; i++) |
4329 | { | |
4330 | if (i == 6) | |
6a4dac78 | 4331 | mode = DFmode; |
6205ab4b | 4332 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
4333 | values_68881[i] = r; | |
4334 | } | |
4335 | inited_68881_table = 1; | |
4336 | } | |
5243fbff | 4337 | |
4338 | int | |
821960c7 | 4339 | standard_68881_constant_p (rtx x) |
5243fbff | 4340 | { |
945f7b03 | 4341 | const REAL_VALUE_TYPE *r; |
6205ab4b | 4342 | int i; |
5243fbff | 4343 | |
50d9d0ec | 4344 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
0c0492c9 | 4345 | used at all on those chips. */ |
f716b74b | 4346 | if (TUNE_68040_60) |
5243fbff | 4347 | return 0; |
4348 | ||
6205ab4b | 4349 | if (! inited_68881_table) |
4350 | init_68881_table (); | |
4351 | ||
945f7b03 | 4352 | r = CONST_DOUBLE_REAL_VALUE (x); |
6205ab4b | 4353 | |
a417188d | 4354 | /* Use real_identical instead of real_equal so that -0.0 is rejected. */ |
6205ab4b | 4355 | for (i = 0; i < 6; i++) |
4356 | { | |
945f7b03 | 4357 | if (real_identical (r, &values_68881[i])) |
6205ab4b | 4358 | return (codes_68881[i]); |
4359 | } | |
4360 | ||
5243fbff | 4361 | if (GET_MODE (x) == SFmode) |
4362 | return 0; | |
6205ab4b | 4363 | |
945f7b03 | 4364 | if (real_equal (r, &values_68881[6])) |
6205ab4b | 4365 | return (codes_68881[6]); |
4366 | ||
5243fbff | 4367 | /* larger powers of ten in the constants ram are not used |
4368 | because they are not equal to a `double' C constant. */ | |
4369 | return 0; | |
4370 | } | |
4371 | ||
4372 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
4373 | or 0 if X is not a power of 2. */ | |
4374 | ||
4375 | int | |
821960c7 | 4376 | floating_exact_log2 (rtx x) |
5243fbff | 4377 | { |
945f7b03 | 4378 | const REAL_VALUE_TYPE *r; |
4379 | REAL_VALUE_TYPE r1; | |
bd58682f | 4380 | int exp; |
5243fbff | 4381 | |
945f7b03 | 4382 | r = CONST_DOUBLE_REAL_VALUE (x); |
5243fbff | 4383 | |
945f7b03 | 4384 | if (real_less (r, &dconst1)) |
5243fbff | 4385 | return 0; |
4386 | ||
945f7b03 | 4387 | exp = real_exponent (r); |
4e6322c5 | 4388 | real_2expN (&r1, exp, DFmode); |
945f7b03 | 4389 | if (real_equal (&r1, r)) |
bd58682f | 4390 | return exp; |
4391 | ||
5243fbff | 4392 | return 0; |
4393 | } | |
4394 | \f | |
5243fbff | 4395 | /* A C compound statement to output to stdio stream STREAM the |
4396 | assembler syntax for an instruction operand X. X is an RTL | |
4397 | expression. | |
4398 | ||
4399 | CODE is a value that can be used to specify one of several ways | |
4400 | of printing the operand. It is used when identical operands | |
4401 | must be printed differently depending on the context. CODE | |
4402 | comes from the `%' specification that was used to request | |
4403 | printing of the operand. If the specification was just `%DIGIT' | |
4404 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
4405 | is the ASCII code for LTR. | |
4406 | ||
4407 | If X is a register, this macro should print the register's name. | |
4408 | The names can be found in an array `reg_names' whose type is | |
4409 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
4410 | ||
4411 | When the machine description has a specification `%PUNCT' (a `%' | |
4412 | followed by a punctuation character), this macro is called with | |
4413 | a null pointer for X and the punctuation character for CODE. | |
4414 | ||
4415 | The m68k specific codes are: | |
4416 | ||
4417 | '.' for dot needed in Motorola-style opcode names. | |
4418 | '-' for an operand pushing on the stack: | |
4419 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
4420 | '+' for an operand pushing on the stack: | |
4421 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
4422 | '@' for a reference to the top word on the stack: | |
4423 | sp@, (sp) or (%sp) depending on the style of syntax. | |
4424 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
2a458a3f | 4425 | but & in SGS syntax). |
5243fbff | 4426 | '!' for the cc register (used in an `and to cc' insn). |
4427 | '$' for the letter `s' in an op code, but only on the 68040. | |
4428 | '&' for the letter `d' in an op code, but only on the 68040. | |
f14f0b88 | 4429 | '/' for register prefix needed by longlong.h. |
9c47decb | 4430 | '?' for m68k_library_id_string |
5243fbff | 4431 | |
4432 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
4433 | 'd' to force memory addressing to be absolute, not relative. | |
4434 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
5243fbff | 4435 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
4436 | or print pair of registers as rx:ry. | |
dd7218bb | 4437 | 'p' print an address with @PLTPC attached, but only if the operand |
4438 | is not locally-bound. */ | |
5243fbff | 4439 | |
4440 | void | |
821960c7 | 4441 | print_operand (FILE *file, rtx op, int letter) |
5243fbff | 4442 | { |
5243fbff | 4443 | if (letter == '.') |
4444 | { | |
9cbcee62 | 4445 | if (MOTOROLA) |
4446 | fprintf (file, "."); | |
5243fbff | 4447 | } |
4448 | else if (letter == '#') | |
9cbcee62 | 4449 | asm_fprintf (file, "%I"); |
5243fbff | 4450 | else if (letter == '-') |
4ad53767 | 4451 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
5243fbff | 4452 | else if (letter == '+') |
4ad53767 | 4453 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
5243fbff | 4454 | else if (letter == '@') |
4ad53767 | 4455 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
5243fbff | 4456 | else if (letter == '!') |
9cbcee62 | 4457 | asm_fprintf (file, "%Rfpcr"); |
5243fbff | 4458 | else if (letter == '$') |
4459 | { | |
6e6d2086 | 4460 | if (TARGET_68040) |
9cbcee62 | 4461 | fprintf (file, "s"); |
5243fbff | 4462 | } |
4463 | else if (letter == '&') | |
4464 | { | |
6e6d2086 | 4465 | if (TARGET_68040) |
9cbcee62 | 4466 | fprintf (file, "d"); |
5243fbff | 4467 | } |
f14f0b88 | 4468 | else if (letter == '/') |
9cbcee62 | 4469 | asm_fprintf (file, "%R"); |
9c47decb | 4470 | else if (letter == '?') |
4471 | asm_fprintf (file, m68k_library_id_string); | |
dd7218bb | 4472 | else if (letter == 'p') |
f0ecff58 | 4473 | { |
dd7218bb | 4474 | output_addr_const (file, op); |
4475 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
4476 | fprintf (file, "@PLTPC"); | |
f0ecff58 | 4477 | } |
5243fbff | 4478 | else if (GET_CODE (op) == REG) |
4479 | { | |
d2e633d7 | 4480 | if (letter == 'R') |
4481 | /* Print out the second register name of a register pair. | |
4482 | I.e., R (6) => 7. */ | |
16b4cb0d | 4483 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
5243fbff | 4484 | else |
16b4cb0d | 4485 | fputs (M68K_REGNAME(REGNO (op)), file); |
5243fbff | 4486 | } |
4487 | else if (GET_CODE (op) == MEM) | |
4488 | { | |
3c047fe9 | 4489 | output_address (GET_MODE (op), XEXP (op, 0)); |
5243fbff | 4490 | if (letter == 'd' && ! TARGET_68020 |
4491 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
4492 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
4493 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
4494 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
4ad53767 | 4495 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
5243fbff | 4496 | } |
5243fbff | 4497 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
4498 | { | |
d54128c3 | 4499 | long l; |
945f7b03 | 4500 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
62e8616a | 4501 | asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF); |
6205ab4b | 4502 | } |
4503 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
4504 | { | |
d54128c3 | 4505 | long l[3]; |
945f7b03 | 4506 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
62e8616a | 4507 | asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF, |
4508 | l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF); | |
5243fbff | 4509 | } |
bbc6fd5f | 4510 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
5243fbff | 4511 | { |
d54128c3 | 4512 | long l[2]; |
945f7b03 | 4513 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
62e8616a | 4514 | asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF); |
5243fbff | 4515 | } |
4516 | else | |
4517 | { | |
f0ecff58 | 4518 | /* Use `print_operand_address' instead of `output_addr_const' |
4519 | to ensure that we print relevant PIC stuff. */ | |
b91e0dcb | 4520 | asm_fprintf (file, "%I"); |
f0ecff58 | 4521 | if (TARGET_PCREL |
4522 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
4523 | print_operand_address (file, op); | |
4524 | else | |
4525 | output_addr_const (file, op); | |
5243fbff | 4526 | } |
4527 | } | |
4528 | ||
869bde6b | 4529 | /* Return string for TLS relocation RELOC. */ |
4530 | ||
4531 | static const char * | |
4532 | m68k_get_reloc_decoration (enum m68k_reloc reloc) | |
4533 | { | |
4534 | /* To my knowledge, !MOTOROLA assemblers don't support TLS. */ | |
4535 | gcc_assert (MOTOROLA || reloc == RELOC_GOT); | |
4536 | ||
4537 | switch (reloc) | |
4538 | { | |
4539 | case RELOC_GOT: | |
4540 | if (MOTOROLA) | |
4541 | { | |
4542 | if (flag_pic == 1 && TARGET_68020) | |
4543 | return "@GOT.w"; | |
4544 | else | |
4545 | return "@GOT"; | |
4546 | } | |
4547 | else | |
4548 | { | |
4549 | if (TARGET_68020) | |
4550 | { | |
4551 | switch (flag_pic) | |
4552 | { | |
4553 | case 1: | |
4554 | return ":w"; | |
4555 | case 2: | |
4556 | return ":l"; | |
4557 | default: | |
4558 | return ""; | |
4559 | } | |
4560 | } | |
4561 | } | |
1fddbaea | 4562 | gcc_unreachable (); |
869bde6b | 4563 | |
4564 | case RELOC_TLSGD: | |
4565 | return "@TLSGD"; | |
4566 | ||
4567 | case RELOC_TLSLDM: | |
4568 | return "@TLSLDM"; | |
4569 | ||
4570 | case RELOC_TLSLDO: | |
4571 | return "@TLSLDO"; | |
4572 | ||
4573 | case RELOC_TLSIE: | |
4574 | return "@TLSIE"; | |
4575 | ||
4576 | case RELOC_TLSLE: | |
4577 | return "@TLSLE"; | |
4578 | ||
4579 | default: | |
4580 | gcc_unreachable (); | |
4581 | } | |
4582 | } | |
4583 | ||
27f5e69f | 4584 | /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */ |
6c19bc3c | 4585 | |
27f5e69f | 4586 | static bool |
6c19bc3c | 4587 | m68k_output_addr_const_extra (FILE *file, rtx x) |
4588 | { | |
869bde6b | 4589 | if (GET_CODE (x) == UNSPEC) |
4590 | { | |
4591 | switch (XINT (x, 1)) | |
4592 | { | |
4593 | case UNSPEC_RELOC16: | |
4594 | case UNSPEC_RELOC32: | |
4595 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
2a9840b1 | 4596 | fputs (m68k_get_reloc_decoration |
4597 | ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file); | |
869bde6b | 4598 | return true; |
6c19bc3c | 4599 | |
869bde6b | 4600 | default: |
4601 | break; | |
4602 | } | |
4603 | } | |
4604 | ||
4605 | return false; | |
4606 | } | |
4607 | ||
4608 | /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ | |
4609 | ||
4610 | static void | |
4611 | m68k_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
4612 | { | |
4613 | gcc_assert (size == 4); | |
4614 | fputs ("\t.long\t", file); | |
4615 | output_addr_const (file, x); | |
4616 | fputs ("@TLSLDO+0x8000", file); | |
6c19bc3c | 4617 | } |
4618 | ||
1a1a6f69 | 4619 | /* In the name of slightly smaller debug output, and to cater to |
4620 | general assembler lossage, recognize various UNSPEC sequences | |
4621 | and turn them back into a direct symbol reference. */ | |
4622 | ||
4623 | static rtx | |
d09e50a6 | 4624 | m68k_delegitimize_address (rtx orig_x) |
1a1a6f69 | 4625 | { |
d1741f8f | 4626 | rtx x; |
4627 | struct m68k_address addr; | |
4628 | rtx unspec; | |
1a1a6f69 | 4629 | |
d09e50a6 | 4630 | orig_x = delegitimize_mem_from_attrs (orig_x); |
d1741f8f | 4631 | x = orig_x; |
4632 | if (MEM_P (x)) | |
4633 | x = XEXP (x, 0); | |
4634 | ||
4635 | if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode) | |
d09e50a6 | 4636 | return orig_x; |
4637 | ||
d1741f8f | 4638 | if (!m68k_decompose_address (GET_MODE (x), x, false, &addr) |
4639 | || addr.offset == NULL_RTX | |
4640 | || GET_CODE (addr.offset) != CONST) | |
4641 | return orig_x; | |
1a1a6f69 | 4642 | |
d1741f8f | 4643 | unspec = XEXP (addr.offset, 0); |
4644 | if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1))) | |
4645 | unspec = XEXP (unspec, 0); | |
4646 | if (GET_CODE (unspec) != UNSPEC | |
4647 | || (XINT (unspec, 1) != UNSPEC_RELOC16 | |
4648 | && XINT (unspec, 1) != UNSPEC_RELOC32)) | |
4649 | return orig_x; | |
4650 | x = XVECEXP (unspec, 0, 0); | |
eceb989a | 4651 | gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF); |
d1741f8f | 4652 | if (unspec != XEXP (addr.offset, 0)) |
4653 | x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1)); | |
4654 | if (addr.index) | |
1a1a6f69 | 4655 | { |
d1741f8f | 4656 | rtx idx = addr.index; |
4657 | if (addr.scale != 1) | |
4658 | idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale)); | |
4659 | x = gen_rtx_PLUS (Pmode, idx, x); | |
1a1a6f69 | 4660 | } |
d1741f8f | 4661 | if (addr.base) |
4662 | x = gen_rtx_PLUS (Pmode, addr.base, x); | |
4663 | if (MEM_P (orig_x)) | |
4664 | x = replace_equiv_address_nv (orig_x, x); | |
4665 | return x; | |
1a1a6f69 | 4666 | } |
4667 | ||
5243fbff | 4668 | \f |
4669 | /* A C compound statement to output to stdio stream STREAM the | |
4670 | assembler syntax for an instruction operand that is a memory | |
4671 | reference whose address is ADDR. ADDR is an RTL expression. | |
4672 | ||
4673 | Note that this contains a kludge that knows that the only reason | |
4674 | we have an address (plus (label_ref...) (reg...)) when not generating | |
4675 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
4676 | generates a label LInnn: on such an insn. | |
4677 | ||
4678 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
4679 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
4680 | ||
5243fbff | 4681 | This routine is responsible for distinguishing between -fpic and -fPIC |
4682 | style relocations in an address. When generating -fpic code the | |
a361b456 | 4683 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
4684 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
5243fbff | 4685 | |
4686 | void | |
821960c7 | 4687 | print_operand_address (FILE *file, rtx addr) |
5243fbff | 4688 | { |
b97b0687 | 4689 | struct m68k_address address; |
4690 | ||
4691 | if (!m68k_decompose_address (QImode, addr, true, &address)) | |
4692 | gcc_unreachable (); | |
4693 | ||
4694 | if (address.code == PRE_DEC) | |
4ad53767 | 4695 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", |
4696 | M68K_REGNAME (REGNO (address.base))); | |
b97b0687 | 4697 | else if (address.code == POST_INC) |
4ad53767 | 4698 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", |
4699 | M68K_REGNAME (REGNO (address.base))); | |
b97b0687 | 4700 | else if (!address.base && !address.index) |
4701 | { | |
4702 | /* A constant address. */ | |
4703 | gcc_assert (address.offset == addr); | |
4704 | if (GET_CODE (addr) == CONST_INT) | |
4705 | { | |
4706 | /* (xxx).w or (xxx).l. */ | |
4707 | if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) | |
4ad53767 | 4708 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); |
065b42aa | 4709 | else |
b97b0687 | 4710 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
065b42aa | 4711 | } |
b97b0687 | 4712 | else if (TARGET_PCREL) |
065b42aa | 4713 | { |
b97b0687 | 4714 | /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ |
4715 | fputc ('(', file); | |
4716 | output_addr_const (file, addr); | |
4717 | asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); | |
065b42aa | 4718 | } |
b97b0687 | 4719 | else |
065b42aa | 4720 | { |
b97b0687 | 4721 | /* (xxx).l. We need a special case for SYMBOL_REF if the symbol |
4722 | name ends in `.<letter>', as the last 2 characters can be | |
4723 | mistaken as a size suffix. Put the name in parentheses. */ | |
4724 | if (GET_CODE (addr) == SYMBOL_REF | |
4725 | && strlen (XSTR (addr, 0)) > 2 | |
4726 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
065b42aa | 4727 | { |
b97b0687 | 4728 | putc ('(', file); |
4729 | output_addr_const (file, addr); | |
4730 | putc (')', file); | |
065b42aa | 4731 | } |
4732 | else | |
b97b0687 | 4733 | output_addr_const (file, addr); |
065b42aa | 4734 | } |
b97b0687 | 4735 | } |
4736 | else | |
4737 | { | |
4738 | int labelno; | |
4739 | ||
4740 | /* If ADDR is a (d8,pc,Xn) address, this is the number of the | |
f6a0d06f | 4741 | label being accessed, otherwise it is -1. */ |
b97b0687 | 4742 | labelno = (address.offset |
4743 | && !address.base | |
4744 | && GET_CODE (address.offset) == LABEL_REF | |
4745 | ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) | |
4746 | : -1); | |
4747 | if (MOTOROLA) | |
065b42aa | 4748 | { |
b97b0687 | 4749 | /* Print the "offset(base" component. */ |
4750 | if (labelno >= 0) | |
4bea814f | 4751 | asm_fprintf (file, "%LL%d(%Rpc,", labelno); |
b97b0687 | 4752 | else |
065b42aa | 4753 | { |
b97b0687 | 4754 | if (address.offset) |
869bde6b | 4755 | output_addr_const (file, address.offset); |
4756 | ||
b97b0687 | 4757 | putc ('(', file); |
4758 | if (address.base) | |
4759 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
065b42aa | 4760 | } |
b97b0687 | 4761 | /* Print the ",index" component, if any. */ |
4762 | if (address.index) | |
065b42aa | 4763 | { |
b97b0687 | 4764 | if (address.base) |
4765 | putc (',', file); | |
4766 | fprintf (file, "%s.%c", | |
4767 | M68K_REGNAME (REGNO (address.index)), | |
4768 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
4769 | if (address.scale != 1) | |
4770 | fprintf (file, "*%d", address.scale); | |
065b42aa | 4771 | } |
065b42aa | 4772 | putc (')', file); |
065b42aa | 4773 | } |
b97b0687 | 4774 | else /* !MOTOROLA */ |
065b42aa | 4775 | { |
b97b0687 | 4776 | if (!address.offset && !address.index) |
4777 | fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); | |
065b42aa | 4778 | else |
065b42aa | 4779 | { |
b97b0687 | 4780 | /* Print the "base@(offset" component. */ |
4781 | if (labelno >= 0) | |
4bea814f | 4782 | asm_fprintf (file, "%Rpc@(%LL%d", labelno); |
b97b0687 | 4783 | else |
4784 | { | |
4785 | if (address.base) | |
4786 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
4787 | fprintf (file, "@("); | |
4788 | if (address.offset) | |
869bde6b | 4789 | output_addr_const (file, address.offset); |
b97b0687 | 4790 | } |
4791 | /* Print the ",index" component, if any. */ | |
4792 | if (address.index) | |
4793 | { | |
4794 | fprintf (file, ",%s:%c", | |
4795 | M68K_REGNAME (REGNO (address.index)), | |
4796 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
4797 | if (address.scale != 1) | |
4798 | fprintf (file, ":%d", address.scale); | |
4799 | } | |
065b42aa | 4800 | putc (')', file); |
4801 | } | |
065b42aa | 4802 | } |
5243fbff | 4803 | } |
4804 | } | |
5b1c4249 | 4805 | \f |
4806 | /* Check for cases where a clr insns can be omitted from code using | |
4807 | strict_low_part sets. For example, the second clrl here is not needed: | |
4808 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
4809 | ||
4810 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
4811 | insn we are checking for redundancy. TARGET is the register set by the | |
4812 | clear insn. */ | |
4813 | ||
821960c7 | 4814 | bool |
3754d046 | 4815 | strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn, |
821960c7 | 4816 | rtx target) |
5b1c4249 | 4817 | { |
9e9d6337 | 4818 | rtx_insn *p = first_insn; |
5b1c4249 | 4819 | |
e64adf14 | 4820 | while ((p = PREV_INSN (p))) |
5b1c4249 | 4821 | { |
e64adf14 | 4822 | if (NOTE_INSN_BASIC_BLOCK_P (p)) |
4823 | return false; | |
4824 | ||
4825 | if (NOTE_P (p)) | |
4826 | continue; | |
4827 | ||
5b1c4249 | 4828 | /* If it isn't an insn, then give up. */ |
e64adf14 | 4829 | if (!INSN_P (p)) |
821960c7 | 4830 | return false; |
5b1c4249 | 4831 | |
4832 | if (reg_set_p (target, p)) | |
4833 | { | |
4834 | rtx set = single_set (p); | |
4835 | rtx dest; | |
4836 | ||
4837 | /* If it isn't an easy to recognize insn, then give up. */ | |
4838 | if (! set) | |
821960c7 | 4839 | return false; |
5b1c4249 | 4840 | |
4841 | dest = SET_DEST (set); | |
4842 | ||
4843 | /* If this sets the entire target register to zero, then our | |
4844 | first_insn is redundant. */ | |
4845 | if (rtx_equal_p (dest, target) | |
4846 | && SET_SRC (set) == const0_rtx) | |
821960c7 | 4847 | return true; |
5b1c4249 | 4848 | else if (GET_CODE (dest) == STRICT_LOW_PART |
4849 | && GET_CODE (XEXP (dest, 0)) == REG | |
4850 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
4851 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
4852 | <= GET_MODE_SIZE (mode))) | |
4853 | /* This is a strict low part set which modifies less than | |
4854 | we are using, so it is safe. */ | |
4855 | ; | |
4856 | else | |
821960c7 | 4857 | return false; |
5b1c4249 | 4858 | } |
5b1c4249 | 4859 | } |
4860 | ||
821960c7 | 4861 | return false; |
5b1c4249 | 4862 | } |
0c23ddd4 | 4863 | |
f0ecff58 | 4864 | /* Operand predicates for implementing asymmetric pc-relative addressing |
4865 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dfd1079d | 4866 | when used as a source operand, but not as a destination operand. |
f0ecff58 | 4867 | |
4868 | We model this by restricting the meaning of the basic predicates | |
4869 | (general_operand, memory_operand, etc) to forbid the use of this | |
4870 | addressing mode, and then define the following predicates that permit | |
4871 | this addressing mode. These predicates can then be used for the | |
4872 | source operands of the appropriate instructions. | |
4873 | ||
4874 | n.b. While it is theoretically possible to change all machine patterns | |
4875 | to use this addressing more where permitted by the architecture, | |
4876 | it has only been implemented for "common" cases: SImode, HImode, and | |
4877 | QImode operands, and only for the principle operations that would | |
4878 | require this addressing mode: data movement and simple integer operations. | |
4879 | ||
4880 | In parallel with these new predicates, two new constraint letters | |
4881 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
4882 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
4883 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
4884 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
4885 | of how these constraints are used. | |
4886 | ||
4887 | The use of these predicates is strictly optional, though patterns that | |
4888 | don't will cause an extra reload register to be allocated where one | |
4889 | was not necessary: | |
4890 | ||
4891 | lea (abc:w,%pc),%a0 ; need to reload address | |
4892 | moveq &1,%d1 ; since write to pc-relative space | |
4893 | movel %d1,%a0@ ; is not allowed | |
4894 | ... | |
4895 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
4896 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
4897 | ||
4898 | For more info, consult tiemann@cygnus.com. | |
4899 | ||
4900 | ||
4901 | All of the ugliness with predicates and constraints is due to the | |
4902 | simple fact that the m68k does not allow a pc-relative addressing | |
4903 | mode as a destination. gcc does not distinguish between source and | |
4904 | destination addresses. Hence, if we claim that pc-relative address | |
bc409cb4 | 4905 | modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we |
f0ecff58 | 4906 | end up with invalid code. To get around this problem, we left |
4907 | pc-relative modes as invalid addresses, and then added special | |
4908 | predicates and constraints to accept them. | |
4909 | ||
4910 | A cleaner way to handle this is to modify gcc to distinguish | |
4911 | between source and destination addresses. We can then say that | |
4912 | pc-relative is a valid source address but not a valid destination | |
4913 | address, and hopefully avoid a lot of the predicate and constraint | |
4914 | hackery. Unfortunately, this would be a pretty big change. It would | |
4915 | be a useful change for a number of ports, but there aren't any current | |
4916 | plans to undertake this. | |
4917 | ||
4918 | ***************************************************************************/ | |
4919 | ||
4920 | ||
f2fa409d | 4921 | const char * |
821960c7 | 4922 | output_andsi3 (rtx *operands) |
128cf854 | 4923 | { |
4924 | int logval; | |
4925 | if (GET_CODE (operands[2]) == CONST_INT | |
3e080e22 | 4926 | && (INTVAL (operands[2]) | 0xffff) == -1 |
128cf854 | 4927 | && (DATA_REG_P (operands[0]) |
4928 | || offsettable_memref_p (operands[0])) | |
960e6739 | 4929 | && !TARGET_COLDFIRE) |
128cf854 | 4930 | { |
4931 | if (GET_CODE (operands[0]) != REG) | |
eafc6604 | 4932 | operands[0] = adjust_address (operands[0], HImode, 2); |
e6b2f841 | 4933 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
128cf854 | 4934 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4935 | CC_STATUS_INIT; | |
4936 | if (operands[2] == const0_rtx) | |
4937 | return "clr%.w %0"; | |
4938 | return "and%.w %2,%0"; | |
4939 | } | |
4940 | if (GET_CODE (operands[2]) == CONST_INT | |
f422081b | 4941 | && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0 |
128cf854 | 4942 | && (DATA_REG_P (operands[0]) |
4943 | || offsettable_memref_p (operands[0]))) | |
4944 | { | |
4945 | if (DATA_REG_P (operands[0])) | |
065b42aa | 4946 | operands[1] = GEN_INT (logval); |
128cf854 | 4947 | else |
4948 | { | |
eafc6604 | 4949 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
e6b2f841 | 4950 | operands[1] = GEN_INT (logval % 8); |
128cf854 | 4951 | } |
4952 | /* This does not set condition codes in a standard way. */ | |
4953 | CC_STATUS_INIT; | |
4954 | return "bclr %1,%0"; | |
4955 | } | |
4956 | return "and%.l %2,%0"; | |
4957 | } | |
4958 | ||
f2fa409d | 4959 | const char * |
821960c7 | 4960 | output_iorsi3 (rtx *operands) |
128cf854 | 4961 | { |
4962 | register int logval; | |
4963 | if (GET_CODE (operands[2]) == CONST_INT | |
4964 | && INTVAL (operands[2]) >> 16 == 0 | |
4965 | && (DATA_REG_P (operands[0]) | |
4966 | || offsettable_memref_p (operands[0])) | |
960e6739 | 4967 | && !TARGET_COLDFIRE) |
128cf854 | 4968 | { |
4969 | if (GET_CODE (operands[0]) != REG) | |
eafc6604 | 4970 | operands[0] = adjust_address (operands[0], HImode, 2); |
128cf854 | 4971 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4972 | CC_STATUS_INIT; | |
4973 | if (INTVAL (operands[2]) == 0xffff) | |
4974 | return "mov%.w %2,%0"; | |
4975 | return "or%.w %2,%0"; | |
4976 | } | |
4977 | if (GET_CODE (operands[2]) == CONST_INT | |
f422081b | 4978 | && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 |
128cf854 | 4979 | && (DATA_REG_P (operands[0]) |
4980 | || offsettable_memref_p (operands[0]))) | |
4981 | { | |
4982 | if (DATA_REG_P (operands[0])) | |
eafc6604 | 4983 | operands[1] = GEN_INT (logval); |
128cf854 | 4984 | else |
4985 | { | |
eafc6604 | 4986 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
e6b2f841 | 4987 | operands[1] = GEN_INT (logval % 8); |
128cf854 | 4988 | } |
4989 | CC_STATUS_INIT; | |
4990 | return "bset %1,%0"; | |
4991 | } | |
4992 | return "or%.l %2,%0"; | |
4993 | } | |
4994 | ||
f2fa409d | 4995 | const char * |
821960c7 | 4996 | output_xorsi3 (rtx *operands) |
128cf854 | 4997 | { |
4998 | register int logval; | |
4999 | if (GET_CODE (operands[2]) == CONST_INT | |
5000 | && INTVAL (operands[2]) >> 16 == 0 | |
5001 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
960e6739 | 5002 | && !TARGET_COLDFIRE) |
128cf854 | 5003 | { |
5004 | if (! DATA_REG_P (operands[0])) | |
eafc6604 | 5005 | operands[0] = adjust_address (operands[0], HImode, 2); |
128cf854 | 5006 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
5007 | CC_STATUS_INIT; | |
5008 | if (INTVAL (operands[2]) == 0xffff) | |
5009 | return "not%.w %0"; | |
5010 | return "eor%.w %2,%0"; | |
5011 | } | |
5012 | if (GET_CODE (operands[2]) == CONST_INT | |
f422081b | 5013 | && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 |
128cf854 | 5014 | && (DATA_REG_P (operands[0]) |
5015 | || offsettable_memref_p (operands[0]))) | |
5016 | { | |
5017 | if (DATA_REG_P (operands[0])) | |
eafc6604 | 5018 | operands[1] = GEN_INT (logval); |
128cf854 | 5019 | else |
5020 | { | |
eafc6604 | 5021 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
e6b2f841 | 5022 | operands[1] = GEN_INT (logval % 8); |
128cf854 | 5023 | } |
5024 | CC_STATUS_INIT; | |
5025 | return "bchg %1,%0"; | |
5026 | } | |
5027 | return "eor%.l %2,%0"; | |
5028 | } | |
2cb4ac60 | 5029 | |
dd7218bb | 5030 | /* Return the instruction that should be used for a call to address X, |
5031 | which is known to be in operand 0. */ | |
5032 | ||
5033 | const char * | |
5034 | output_call (rtx x) | |
5035 | { | |
5036 | if (symbolic_operand (x, VOIDmode)) | |
5037 | return m68k_symbolic_call; | |
5038 | else | |
5039 | return "jsr %a0"; | |
5040 | } | |
5041 | ||
33fb08b8 | 5042 | /* Likewise sibling calls. */ |
5043 | ||
5044 | const char * | |
5045 | output_sibcall (rtx x) | |
5046 | { | |
5047 | if (symbolic_operand (x, VOIDmode)) | |
5048 | return m68k_symbolic_jump; | |
5049 | else | |
5050 | return "jmp %a0"; | |
5051 | } | |
5052 | ||
6988553d | 5053 | static void |
821960c7 | 5054 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
e2182937 | 5055 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
821960c7 | 5056 | tree function) |
c6933ba6 | 5057 | { |
9e9d6337 | 5058 | rtx this_slot, offset, addr, mem, tmp; |
5059 | rtx_insn *insn; | |
61fafd77 | 5060 | |
5061 | /* Avoid clobbering the struct value reg by using the | |
5062 | static chain reg as a temporary. */ | |
5063 | tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
e2182937 | 5064 | |
5065 | /* Pretend to be a post-reload pass while generating rtl. */ | |
e2182937 | 5066 | reload_completed = 1; |
e2182937 | 5067 | |
5068 | /* The "this" pointer is stored at 4(%sp). */ | |
29c05e22 | 5069 | this_slot = gen_rtx_MEM (Pmode, plus_constant (Pmode, |
5070 | stack_pointer_rtx, 4)); | |
e2182937 | 5071 | |
5072 | /* Add DELTA to THIS. */ | |
5073 | if (delta != 0) | |
5e0e9723 | 5074 | { |
e2182937 | 5075 | /* Make the offset a legitimate operand for memory addition. */ |
5076 | offset = GEN_INT (delta); | |
5077 | if ((delta < -8 || delta > 8) | |
5078 | && (TARGET_COLDFIRE || USE_MOVQ (delta))) | |
5079 | { | |
5080 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); | |
5081 | offset = gen_rtx_REG (Pmode, D0_REG); | |
5082 | } | |
5083 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
5084 | copy_rtx (this_slot), offset)); | |
5e0e9723 | 5085 | } |
6988553d | 5086 | |
e2182937 | 5087 | /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ |
5088 | if (vcall_offset != 0) | |
5089 | { | |
5090 | /* Set the static chain register to *THIS. */ | |
61fafd77 | 5091 | emit_move_insn (tmp, this_slot); |
5092 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
e2182937 | 5093 | |
5094 | /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ | |
29c05e22 | 5095 | addr = plus_constant (Pmode, tmp, vcall_offset); |
e2182937 | 5096 | if (!m68k_legitimate_address_p (Pmode, addr, true)) |
5097 | { | |
d1f9b275 | 5098 | emit_insn (gen_rtx_SET (tmp, addr)); |
61fafd77 | 5099 | addr = tmp; |
e2182937 | 5100 | } |
6988553d | 5101 | |
e2182937 | 5102 | /* Load the offset into %d0 and add it to THIS. */ |
5103 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), | |
5104 | gen_rtx_MEM (Pmode, addr)); | |
5105 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
5106 | copy_rtx (this_slot), | |
5107 | gen_rtx_REG (Pmode, D0_REG))); | |
5108 | } | |
dd7218bb | 5109 | |
e2182937 | 5110 | /* Jump to the target function. Use a sibcall if direct jumps are |
5111 | allowed, otherwise load the address into a register first. */ | |
5112 | mem = DECL_RTL (function); | |
5113 | if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) | |
5114 | { | |
5115 | gcc_assert (flag_pic); | |
6988553d | 5116 | |
e2182937 | 5117 | if (!TARGET_SEP_DATA) |
5118 | { | |
5119 | /* Use the static chain register as a temporary (call-clobbered) | |
5120 | GOT pointer for this function. We can use the static chain | |
5121 | register because it isn't live on entry to the thunk. */ | |
3072d30e | 5122 | SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM); |
e2182937 | 5123 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
5124 | } | |
61fafd77 | 5125 | legitimize_pic_address (XEXP (mem, 0), Pmode, tmp); |
5126 | mem = replace_equiv_address (mem, tmp); | |
e2182937 | 5127 | } |
5128 | insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); | |
5129 | SIBLING_CALL_P (insn) = 1; | |
5130 | ||
5131 | /* Run just enough of rest_of_compilation. */ | |
5132 | insn = get_insns (); | |
5133 | split_all_insns_noflow (); | |
5134 | final_start_function (insn, file, 1); | |
5135 | final (insn, file, 1); | |
5136 | final_end_function (); | |
5137 | ||
5138 | /* Clean up the vars set above. */ | |
5139 | reload_completed = 0; | |
e2182937 | 5140 | |
5141 | /* Restore the original PIC register. */ | |
5142 | if (flag_pic) | |
3072d30e | 5143 | SET_REGNO (pic_offset_table_rtx, PIC_REG); |
c6933ba6 | 5144 | } |
c8c47ddf | 5145 | |
5146 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
5147 | ||
5148 | static rtx | |
5149 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
5150 | int incoming ATTRIBUTE_UNUSED) | |
5151 | { | |
5152 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
5153 | } | |
b09edf9a | 5154 | |
5155 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
5156 | int | |
5157 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
5158 | unsigned int new_reg) | |
5159 | { | |
5160 | ||
5161 | /* Interrupt functions can only use registers that have already been | |
5162 | saved by the prologue, even if they would normally be | |
5163 | call-clobbered. */ | |
5164 | ||
f9a44575 | 5165 | if ((m68k_get_function_kind (current_function_decl) |
5166 | == m68k_fk_interrupt_handler) | |
3072d30e | 5167 | && !df_regs_ever_live_p (new_reg)) |
b09edf9a | 5168 | return 0; |
5169 | ||
5170 | return 1; | |
5171 | } | |
77236994 | 5172 | |
350e24f5 | 5173 | /* Value is true if hard register REGNO can hold a value of machine-mode |
5174 | MODE. On the 68000, we let the cpu registers can hold any mode, but | |
5175 | restrict the 68881 registers to floating-point modes. */ | |
5176 | ||
77236994 | 5177 | bool |
3754d046 | 5178 | m68k_regno_mode_ok (int regno, machine_mode mode) |
77236994 | 5179 | { |
0b93d200 | 5180 | if (DATA_REGNO_P (regno)) |
77236994 | 5181 | { |
065b42aa | 5182 | /* Data Registers, can hold aggregate if fits in. */ |
5183 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
5184 | return true; | |
77236994 | 5185 | } |
0b93d200 | 5186 | else if (ADDRESS_REGNO_P (regno)) |
77236994 | 5187 | { |
065b42aa | 5188 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) |
5189 | return true; | |
77236994 | 5190 | } |
0b93d200 | 5191 | else if (FP_REGNO_P (regno)) |
77236994 | 5192 | { |
5193 | /* FPU registers, hold float or complex float of long double or | |
065b42aa | 5194 | smaller. */ |
5195 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5196 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
58c23110 | 5197 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
065b42aa | 5198 | return true; |
77236994 | 5199 | } |
5200 | return false; | |
5201 | } | |
58c23110 | 5202 | |
350e24f5 | 5203 | /* Implement SECONDARY_RELOAD_CLASS. */ |
5204 | ||
5205 | enum reg_class | |
5206 | m68k_secondary_reload_class (enum reg_class rclass, | |
3754d046 | 5207 | machine_mode mode, rtx x) |
350e24f5 | 5208 | { |
5209 | int regno; | |
5210 | ||
5211 | regno = true_regnum (x); | |
5212 | ||
5213 | /* If one operand of a movqi is an address register, the other | |
5214 | operand must be a general register or constant. Other types | |
5215 | of operand must be reloaded through a data register. */ | |
5216 | if (GET_MODE_SIZE (mode) == 1 | |
5217 | && reg_classes_intersect_p (rclass, ADDR_REGS) | |
5218 | && !(INT_REGNO_P (regno) || CONSTANT_P (x))) | |
5219 | return DATA_REGS; | |
5220 | ||
5221 | /* PC-relative addresses must be loaded into an address register first. */ | |
5222 | if (TARGET_PCREL | |
5223 | && !reg_class_subset_p (rclass, ADDR_REGS) | |
5224 | && symbolic_operand (x, VOIDmode)) | |
5225 | return ADDR_REGS; | |
5226 | ||
5227 | return NO_REGS; | |
5228 | } | |
5229 | ||
5230 | /* Implement PREFERRED_RELOAD_CLASS. */ | |
5231 | ||
5232 | enum reg_class | |
5233 | m68k_preferred_reload_class (rtx x, enum reg_class rclass) | |
5234 | { | |
5235 | enum reg_class secondary_class; | |
5236 | ||
5237 | /* If RCLASS might need a secondary reload, try restricting it to | |
5238 | a class that doesn't. */ | |
5239 | secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); | |
5240 | if (secondary_class != NO_REGS | |
5241 | && reg_class_subset_p (secondary_class, rclass)) | |
5242 | return secondary_class; | |
5243 | ||
5244 | /* Prefer to use moveq for in-range constants. */ | |
5245 | if (GET_CODE (x) == CONST_INT | |
5246 | && reg_class_subset_p (DATA_REGS, rclass) | |
5247 | && IN_RANGE (INTVAL (x), -0x80, 0x7f)) | |
5248 | return DATA_REGS; | |
5249 | ||
5250 | /* ??? Do we really need this now? */ | |
5251 | if (GET_CODE (x) == CONST_DOUBLE | |
5252 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
5253 | { | |
5254 | if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) | |
5255 | return FP_REGS; | |
5256 | ||
5257 | return NO_REGS; | |
5258 | } | |
5259 | ||
5260 | return rclass; | |
5261 | } | |
5262 | ||
58c23110 | 5263 | /* Return floating point values in a 68881 register. This makes 68881 code |
5264 | a little bit faster. It also makes -msoft-float code incompatible with | |
5265 | hard-float code, so people have to be careful not to mix the two. | |
334ec2d8 | 5266 | For ColdFire it was decided the ABI incompatibility is undesirable. |
58c23110 | 5267 | If there is need for a hard-float ABI it is probably worth doing it |
5268 | properly and also passing function arguments in FP registers. */ | |
5269 | rtx | |
3754d046 | 5270 | m68k_libcall_value (machine_mode mode) |
58c23110 | 5271 | { |
5272 | switch (mode) { | |
5273 | case SFmode: | |
5274 | case DFmode: | |
5275 | case XFmode: | |
5276 | if (TARGET_68881) | |
dbaae14a | 5277 | return gen_rtx_REG (mode, FP0_REG); |
58c23110 | 5278 | break; |
5279 | default: | |
5280 | break; | |
5281 | } | |
869bde6b | 5282 | |
5283 | return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG); | |
58c23110 | 5284 | } |
5285 | ||
d09fd72c | 5286 | /* Location in which function value is returned. |
5287 | NOTE: Due to differences in ABIs, don't call this function directly, | |
5288 | use FUNCTION_VALUE instead. */ | |
58c23110 | 5289 | rtx |
fb80456a | 5290 | m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
58c23110 | 5291 | { |
3754d046 | 5292 | machine_mode mode; |
58c23110 | 5293 | |
5294 | mode = TYPE_MODE (valtype); | |
5295 | switch (mode) { | |
5296 | case SFmode: | |
5297 | case DFmode: | |
5298 | case XFmode: | |
5299 | if (TARGET_68881) | |
dbaae14a | 5300 | return gen_rtx_REG (mode, FP0_REG); |
58c23110 | 5301 | break; |
5302 | default: | |
5303 | break; | |
5304 | } | |
5305 | ||
2d329930 | 5306 | /* If the function returns a pointer, push that into %a0. */ |
5307 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
5308 | /* For compatibility with the large body of existing code which | |
5309 | does not always properly declare external functions returning | |
5310 | pointer types, the m68k/SVR4 convention is to copy the value | |
5311 | returned for pointer functions from a0 to d0 in the function | |
5312 | epilogue, so that callers that have neglected to properly | |
5313 | declare the callee can still find the correct return value in | |
5314 | d0. */ | |
5315 | return gen_rtx_PARALLEL | |
5316 | (mode, | |
5317 | gen_rtvec (2, | |
5318 | gen_rtx_EXPR_LIST (VOIDmode, | |
5319 | gen_rtx_REG (mode, A0_REG), | |
5320 | const0_rtx), | |
5321 | gen_rtx_EXPR_LIST (VOIDmode, | |
5322 | gen_rtx_REG (mode, D0_REG), | |
5323 | const0_rtx))); | |
5324 | else if (POINTER_TYPE_P (valtype)) | |
5325 | return gen_rtx_REG (mode, A0_REG); | |
58c23110 | 5326 | else |
2d329930 | 5327 | return gen_rtx_REG (mode, D0_REG); |
58c23110 | 5328 | } |
159cec75 | 5329 | |
5330 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
5331 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT | |
5332 | static bool | |
33be53f9 | 5333 | m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
159cec75 | 5334 | { |
3754d046 | 5335 | machine_mode mode = TYPE_MODE (type); |
159cec75 | 5336 | |
5337 | if (mode == BLKmode) | |
5338 | return true; | |
5339 | ||
5340 | /* If TYPE's known alignment is less than the alignment of MODE that | |
5341 | would contain the structure, then return in memory. We need to | |
5342 | do so to maintain the compatibility between code compiled with | |
5343 | -mstrict-align and that compiled with -mno-strict-align. */ | |
5344 | if (AGGREGATE_TYPE_P (type) | |
5345 | && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode)) | |
5346 | return true; | |
5347 | ||
5348 | return false; | |
5349 | } | |
5350 | #endif | |
1d86aeab | 5351 | |
5352 | /* CPU to schedule the program for. */ | |
5353 | enum attr_cpu m68k_sched_cpu; | |
5354 | ||
2ccdedfd | 5355 | /* MAC to schedule the program for. */ |
5356 | enum attr_mac m68k_sched_mac; | |
5357 | ||
1d86aeab | 5358 | /* Operand type. */ |
5359 | enum attr_op_type | |
5360 | { | |
5361 | /* No operand. */ | |
5362 | OP_TYPE_NONE, | |
5363 | ||
3c904dda | 5364 | /* Integer register. */ |
5365 | OP_TYPE_RN, | |
5366 | ||
5367 | /* FP register. */ | |
5368 | OP_TYPE_FPN, | |
1d86aeab | 5369 | |
5370 | /* Implicit mem reference (e.g. stack). */ | |
5371 | OP_TYPE_MEM1, | |
5372 | ||
5373 | /* Memory without offset or indexing. EA modes 2, 3 and 4. */ | |
5374 | OP_TYPE_MEM234, | |
5375 | ||
5376 | /* Memory with offset but without indexing. EA mode 5. */ | |
5377 | OP_TYPE_MEM5, | |
5378 | ||
5379 | /* Memory with indexing. EA mode 6. */ | |
5380 | OP_TYPE_MEM6, | |
5381 | ||
5382 | /* Memory referenced by absolute address. EA mode 7. */ | |
5383 | OP_TYPE_MEM7, | |
5384 | ||
5385 | /* Immediate operand that doesn't require extension word. */ | |
5386 | OP_TYPE_IMM_Q, | |
5387 | ||
5388 | /* Immediate 16 bit operand. */ | |
5389 | OP_TYPE_IMM_W, | |
5390 | ||
5391 | /* Immediate 32 bit operand. */ | |
5392 | OP_TYPE_IMM_L | |
5393 | }; | |
5394 | ||
1d86aeab | 5395 | /* Return type of memory ADDR_RTX refers to. */ |
5396 | static enum attr_op_type | |
3754d046 | 5397 | sched_address_type (machine_mode mode, rtx addr_rtx) |
1d86aeab | 5398 | { |
5399 | struct m68k_address address; | |
5400 | ||
3c904dda | 5401 | if (symbolic_operand (addr_rtx, VOIDmode)) |
5402 | return OP_TYPE_MEM7; | |
5403 | ||
1d86aeab | 5404 | if (!m68k_decompose_address (mode, addr_rtx, |
5405 | reload_completed, &address)) | |
5406 | { | |
3c904dda | 5407 | gcc_assert (!reload_completed); |
1d86aeab | 5408 | /* Reload will likely fix the address to be in the register. */ |
5409 | return OP_TYPE_MEM234; | |
5410 | } | |
5411 | ||
5412 | if (address.scale != 0) | |
5413 | return OP_TYPE_MEM6; | |
5414 | ||
5415 | if (address.base != NULL_RTX) | |
5416 | { | |
5417 | if (address.offset == NULL_RTX) | |
5418 | return OP_TYPE_MEM234; | |
5419 | ||
5420 | return OP_TYPE_MEM5; | |
5421 | } | |
5422 | ||
5423 | gcc_assert (address.offset != NULL_RTX); | |
5424 | ||
5425 | return OP_TYPE_MEM7; | |
5426 | } | |
5427 | ||
3c904dda | 5428 | /* Return X or Y (depending on OPX_P) operand of INSN. */ |
5429 | static rtx | |
ed3e6e5d | 5430 | sched_get_operand (rtx_insn *insn, bool opx_p) |
3c904dda | 5431 | { |
5432 | int i; | |
5433 | ||
5434 | if (recog_memoized (insn) < 0) | |
5435 | gcc_unreachable (); | |
5436 | ||
5437 | extract_constrain_insn_cached (insn); | |
5438 | ||
5439 | if (opx_p) | |
5440 | i = get_attr_opx (insn); | |
5441 | else | |
5442 | i = get_attr_opy (insn); | |
5443 | ||
5444 | if (i >= recog_data.n_operands) | |
5445 | return NULL; | |
5446 | ||
5447 | return recog_data.operand[i]; | |
5448 | } | |
5449 | ||
5450 | /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). | |
5451 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
1d86aeab | 5452 | static enum attr_op_type |
ed3e6e5d | 5453 | sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p) |
1d86aeab | 5454 | { |
3c904dda | 5455 | rtx op; |
5456 | ||
5457 | op = sched_get_operand (insn, opx_p); | |
5458 | ||
5459 | if (op == NULL) | |
5460 | { | |
5461 | gcc_assert (!reload_completed); | |
5462 | return OP_TYPE_RN; | |
5463 | } | |
1d86aeab | 5464 | |
5465 | if (address_p) | |
5466 | return sched_address_type (QImode, op); | |
5467 | ||
5468 | if (memory_operand (op, VOIDmode)) | |
5469 | return sched_address_type (GET_MODE (op), XEXP (op, 0)); | |
5470 | ||
5471 | if (register_operand (op, VOIDmode)) | |
3c904dda | 5472 | { |
5473 | if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op))) | |
5474 | || (reload_completed && FP_REG_P (op))) | |
5475 | return OP_TYPE_FPN; | |
5476 | ||
5477 | return OP_TYPE_RN; | |
5478 | } | |
1d86aeab | 5479 | |
5480 | if (GET_CODE (op) == CONST_INT) | |
5481 | { | |
3c904dda | 5482 | int ival; |
5483 | ||
5484 | ival = INTVAL (op); | |
5485 | ||
5486 | /* Check for quick constants. */ | |
5487 | switch (get_attr_type (insn)) | |
5488 | { | |
5489 | case TYPE_ALUQ_L: | |
5490 | if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1)) | |
5491 | return OP_TYPE_IMM_Q; | |
5492 | ||
5493 | gcc_assert (!reload_completed); | |
5494 | break; | |
5495 | ||
5496 | case TYPE_MOVEQ_L: | |
5497 | if (USE_MOVQ (ival)) | |
5498 | return OP_TYPE_IMM_Q; | |
5499 | ||
5500 | gcc_assert (!reload_completed); | |
5501 | break; | |
5502 | ||
5503 | case TYPE_MOV3Q_L: | |
5504 | if (valid_mov3q_const (ival)) | |
5505 | return OP_TYPE_IMM_Q; | |
5506 | ||
5507 | gcc_assert (!reload_completed); | |
5508 | break; | |
5509 | ||
5510 | default: | |
5511 | break; | |
5512 | } | |
5513 | ||
5514 | if (IN_RANGE (ival, -0x8000, 0x7fff)) | |
1d86aeab | 5515 | return OP_TYPE_IMM_W; |
5516 | ||
5517 | return OP_TYPE_IMM_L; | |
5518 | } | |
5519 | ||
5520 | if (GET_CODE (op) == CONST_DOUBLE) | |
5521 | { | |
5522 | switch (GET_MODE (op)) | |
5523 | { | |
5524 | case SFmode: | |
5525 | return OP_TYPE_IMM_W; | |
5526 | ||
5527 | case VOIDmode: | |
5528 | case DFmode: | |
5529 | return OP_TYPE_IMM_L; | |
5530 | ||
5531 | default: | |
5532 | gcc_unreachable (); | |
5533 | } | |
5534 | } | |
5535 | ||
dc941c53 | 5536 | if (GET_CODE (op) == CONST |
5537 | || symbolic_operand (op, VOIDmode) | |
1d86aeab | 5538 | || LABEL_P (op)) |
5539 | { | |
5540 | switch (GET_MODE (op)) | |
5541 | { | |
5542 | case QImode: | |
5543 | return OP_TYPE_IMM_Q; | |
5544 | ||
5545 | case HImode: | |
5546 | return OP_TYPE_IMM_W; | |
5547 | ||
5548 | case SImode: | |
5549 | return OP_TYPE_IMM_L; | |
5550 | ||
5551 | default: | |
869bde6b | 5552 | if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode)) |
5553 | /* Just a guess. */ | |
1d86aeab | 5554 | return OP_TYPE_IMM_W; |
5555 | ||
5556 | return OP_TYPE_IMM_L; | |
5557 | } | |
5558 | } | |
5559 | ||
3c904dda | 5560 | gcc_assert (!reload_completed); |
1d86aeab | 5561 | |
3c904dda | 5562 | if (FLOAT_MODE_P (GET_MODE (op))) |
5563 | return OP_TYPE_FPN; | |
1d86aeab | 5564 | |
3c904dda | 5565 | return OP_TYPE_RN; |
1d86aeab | 5566 | } |
5567 | ||
5568 | /* Implement opx_type attribute. | |
5569 | Return type of INSN's operand X. | |
5570 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
5571 | enum attr_opx_type | |
ed3e6e5d | 5572 | m68k_sched_attr_opx_type (rtx_insn *insn, int address_p) |
1d86aeab | 5573 | { |
1d86aeab | 5574 | switch (sched_attr_op_type (insn, true, address_p != 0)) |
5575 | { | |
3c904dda | 5576 | case OP_TYPE_RN: |
5577 | return OPX_TYPE_RN; | |
5578 | ||
5579 | case OP_TYPE_FPN: | |
5580 | return OPX_TYPE_FPN; | |
1d86aeab | 5581 | |
5582 | case OP_TYPE_MEM1: | |
5583 | return OPX_TYPE_MEM1; | |
5584 | ||
5585 | case OP_TYPE_MEM234: | |
5586 | return OPX_TYPE_MEM234; | |
5587 | ||
5588 | case OP_TYPE_MEM5: | |
5589 | return OPX_TYPE_MEM5; | |
5590 | ||
5591 | case OP_TYPE_MEM6: | |
5592 | return OPX_TYPE_MEM6; | |
5593 | ||
5594 | case OP_TYPE_MEM7: | |
5595 | return OPX_TYPE_MEM7; | |
5596 | ||
5597 | case OP_TYPE_IMM_Q: | |
5598 | return OPX_TYPE_IMM_Q; | |
5599 | ||
5600 | case OP_TYPE_IMM_W: | |
5601 | return OPX_TYPE_IMM_W; | |
5602 | ||
5603 | case OP_TYPE_IMM_L: | |
5604 | return OPX_TYPE_IMM_L; | |
5605 | ||
5606 | default: | |
5607 | gcc_unreachable (); | |
1d86aeab | 5608 | } |
5609 | } | |
5610 | ||
5611 | /* Implement opy_type attribute. | |
5612 | Return type of INSN's operand Y. | |
5613 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
5614 | enum attr_opy_type | |
ed3e6e5d | 5615 | m68k_sched_attr_opy_type (rtx_insn *insn, int address_p) |
1d86aeab | 5616 | { |
1d86aeab | 5617 | switch (sched_attr_op_type (insn, false, address_p != 0)) |
5618 | { | |
3c904dda | 5619 | case OP_TYPE_RN: |
5620 | return OPY_TYPE_RN; | |
5621 | ||
5622 | case OP_TYPE_FPN: | |
5623 | return OPY_TYPE_FPN; | |
1d86aeab | 5624 | |
5625 | case OP_TYPE_MEM1: | |
5626 | return OPY_TYPE_MEM1; | |
5627 | ||
5628 | case OP_TYPE_MEM234: | |
5629 | return OPY_TYPE_MEM234; | |
5630 | ||
5631 | case OP_TYPE_MEM5: | |
5632 | return OPY_TYPE_MEM5; | |
5633 | ||
5634 | case OP_TYPE_MEM6: | |
5635 | return OPY_TYPE_MEM6; | |
5636 | ||
5637 | case OP_TYPE_MEM7: | |
5638 | return OPY_TYPE_MEM7; | |
5639 | ||
5640 | case OP_TYPE_IMM_Q: | |
5641 | return OPY_TYPE_IMM_Q; | |
5642 | ||
5643 | case OP_TYPE_IMM_W: | |
5644 | return OPY_TYPE_IMM_W; | |
5645 | ||
5646 | case OP_TYPE_IMM_L: | |
5647 | return OPY_TYPE_IMM_L; | |
5648 | ||
5649 | default: | |
5650 | gcc_unreachable (); | |
1d86aeab | 5651 | } |
5652 | } | |
5653 | ||
3c904dda | 5654 | /* Return size of INSN as int. */ |
5655 | static int | |
d3ffa7b4 | 5656 | sched_get_attr_size_int (rtx_insn *insn) |
1d86aeab | 5657 | { |
5658 | int size; | |
5659 | ||
3c904dda | 5660 | switch (get_attr_type (insn)) |
1d86aeab | 5661 | { |
3c904dda | 5662 | case TYPE_IGNORE: |
5663 | /* There should be no references to m68k_sched_attr_size for 'ignore' | |
5664 | instructions. */ | |
5665 | gcc_unreachable (); | |
5666 | return 0; | |
5667 | ||
5668 | case TYPE_MUL_L: | |
1d86aeab | 5669 | size = 2; |
5670 | break; | |
5671 | ||
5672 | default: | |
5673 | size = 1; | |
5674 | break; | |
5675 | } | |
5676 | ||
5677 | switch (get_attr_opx_type (insn)) | |
5678 | { | |
5679 | case OPX_TYPE_NONE: | |
3c904dda | 5680 | case OPX_TYPE_RN: |
5681 | case OPX_TYPE_FPN: | |
1d86aeab | 5682 | case OPX_TYPE_MEM1: |
5683 | case OPX_TYPE_MEM234: | |
5684 | case OPY_TYPE_IMM_Q: | |
5685 | break; | |
5686 | ||
5687 | case OPX_TYPE_MEM5: | |
5688 | case OPX_TYPE_MEM6: | |
5689 | /* Here we assume that most absolute references are short. */ | |
5690 | case OPX_TYPE_MEM7: | |
5691 | case OPY_TYPE_IMM_W: | |
5692 | ++size; | |
5693 | break; | |
5694 | ||
5695 | case OPY_TYPE_IMM_L: | |
5696 | size += 2; | |
5697 | break; | |
5698 | ||
5699 | default: | |
5700 | gcc_unreachable (); | |
5701 | } | |
5702 | ||
5703 | switch (get_attr_opy_type (insn)) | |
5704 | { | |
5705 | case OPY_TYPE_NONE: | |
3c904dda | 5706 | case OPY_TYPE_RN: |
5707 | case OPY_TYPE_FPN: | |
1d86aeab | 5708 | case OPY_TYPE_MEM1: |
5709 | case OPY_TYPE_MEM234: | |
5710 | case OPY_TYPE_IMM_Q: | |
5711 | break; | |
5712 | ||
5713 | case OPY_TYPE_MEM5: | |
5714 | case OPY_TYPE_MEM6: | |
5715 | /* Here we assume that most absolute references are short. */ | |
5716 | case OPY_TYPE_MEM7: | |
5717 | case OPY_TYPE_IMM_W: | |
5718 | ++size; | |
5719 | break; | |
5720 | ||
5721 | case OPY_TYPE_IMM_L: | |
5722 | size += 2; | |
5723 | break; | |
5724 | ||
5725 | default: | |
5726 | gcc_unreachable (); | |
5727 | } | |
5728 | ||
5729 | if (size > 3) | |
5730 | { | |
3c904dda | 5731 | gcc_assert (!reload_completed); |
1d86aeab | 5732 | |
5733 | size = 3; | |
5734 | } | |
5735 | ||
5736 | return size; | |
5737 | } | |
5738 | ||
3c904dda | 5739 | /* Return size of INSN as attribute enum value. */ |
5740 | enum attr_size | |
d3ffa7b4 | 5741 | m68k_sched_attr_size (rtx_insn *insn) |
3c904dda | 5742 | { |
5743 | switch (sched_get_attr_size_int (insn)) | |
5744 | { | |
5745 | case 1: | |
5746 | return SIZE_1; | |
5747 | ||
5748 | case 2: | |
5749 | return SIZE_2; | |
5750 | ||
5751 | case 3: | |
5752 | return SIZE_3; | |
5753 | ||
5754 | default: | |
5755 | gcc_unreachable (); | |
3c904dda | 5756 | } |
5757 | } | |
5758 | ||
5759 | /* Return operand X or Y (depending on OPX_P) of INSN, | |
5760 | if it is a MEM, or NULL overwise. */ | |
5761 | static enum attr_op_type | |
d3ffa7b4 | 5762 | sched_get_opxy_mem_type (rtx_insn *insn, bool opx_p) |
3c904dda | 5763 | { |
5764 | if (opx_p) | |
5765 | { | |
5766 | switch (get_attr_opx_type (insn)) | |
5767 | { | |
5768 | case OPX_TYPE_NONE: | |
5769 | case OPX_TYPE_RN: | |
5770 | case OPX_TYPE_FPN: | |
5771 | case OPX_TYPE_IMM_Q: | |
5772 | case OPX_TYPE_IMM_W: | |
5773 | case OPX_TYPE_IMM_L: | |
5774 | return OP_TYPE_RN; | |
5775 | ||
5776 | case OPX_TYPE_MEM1: | |
5777 | case OPX_TYPE_MEM234: | |
5778 | case OPX_TYPE_MEM5: | |
5779 | case OPX_TYPE_MEM7: | |
5780 | return OP_TYPE_MEM1; | |
5781 | ||
5782 | case OPX_TYPE_MEM6: | |
5783 | return OP_TYPE_MEM6; | |
5784 | ||
5785 | default: | |
5786 | gcc_unreachable (); | |
3c904dda | 5787 | } |
5788 | } | |
5789 | else | |
5790 | { | |
5791 | switch (get_attr_opy_type (insn)) | |
5792 | { | |
5793 | case OPY_TYPE_NONE: | |
5794 | case OPY_TYPE_RN: | |
5795 | case OPY_TYPE_FPN: | |
5796 | case OPY_TYPE_IMM_Q: | |
5797 | case OPY_TYPE_IMM_W: | |
5798 | case OPY_TYPE_IMM_L: | |
5799 | return OP_TYPE_RN; | |
5800 | ||
5801 | case OPY_TYPE_MEM1: | |
5802 | case OPY_TYPE_MEM234: | |
5803 | case OPY_TYPE_MEM5: | |
5804 | case OPY_TYPE_MEM7: | |
5805 | return OP_TYPE_MEM1; | |
5806 | ||
5807 | case OPY_TYPE_MEM6: | |
5808 | return OP_TYPE_MEM6; | |
5809 | ||
5810 | default: | |
5811 | gcc_unreachable (); | |
3c904dda | 5812 | } |
5813 | } | |
5814 | } | |
5815 | ||
1d86aeab | 5816 | /* Implement op_mem attribute. */ |
5817 | enum attr_op_mem | |
d3ffa7b4 | 5818 | m68k_sched_attr_op_mem (rtx_insn *insn) |
1d86aeab | 5819 | { |
3c904dda | 5820 | enum attr_op_type opx; |
5821 | enum attr_op_type opy; | |
1d86aeab | 5822 | |
3c904dda | 5823 | opx = sched_get_opxy_mem_type (insn, true); |
5824 | opy = sched_get_opxy_mem_type (insn, false); | |
1d86aeab | 5825 | |
3c904dda | 5826 | if (opy == OP_TYPE_RN && opx == OP_TYPE_RN) |
1d86aeab | 5827 | return OP_MEM_00; |
5828 | ||
3c904dda | 5829 | if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1) |
1d86aeab | 5830 | { |
5831 | switch (get_attr_opx_access (insn)) | |
5832 | { | |
5833 | case OPX_ACCESS_R: | |
5834 | return OP_MEM_10; | |
5835 | ||
5836 | case OPX_ACCESS_W: | |
5837 | return OP_MEM_01; | |
5838 | ||
5839 | case OPX_ACCESS_RW: | |
5840 | return OP_MEM_11; | |
5841 | ||
5842 | default: | |
3c904dda | 5843 | gcc_unreachable (); |
1d86aeab | 5844 | } |
5845 | } | |
5846 | ||
3c904dda | 5847 | if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6) |
1d86aeab | 5848 | { |
5849 | switch (get_attr_opx_access (insn)) | |
5850 | { | |
5851 | case OPX_ACCESS_R: | |
5852 | return OP_MEM_I0; | |
5853 | ||
5854 | case OPX_ACCESS_W: | |
5855 | return OP_MEM_0I; | |
5856 | ||
5857 | case OPX_ACCESS_RW: | |
5858 | return OP_MEM_I1; | |
5859 | ||
5860 | default: | |
3c904dda | 5861 | gcc_unreachable (); |
1d86aeab | 5862 | } |
5863 | } | |
5864 | ||
3c904dda | 5865 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN) |
1d86aeab | 5866 | return OP_MEM_10; |
5867 | ||
3c904dda | 5868 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1) |
1d86aeab | 5869 | { |
5870 | switch (get_attr_opx_access (insn)) | |
5871 | { | |
5872 | case OPX_ACCESS_W: | |
5873 | return OP_MEM_11; | |
5874 | ||
5875 | default: | |
3c904dda | 5876 | gcc_assert (!reload_completed); |
5877 | return OP_MEM_11; | |
1d86aeab | 5878 | } |
5879 | } | |
5880 | ||
3c904dda | 5881 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6) |
1d86aeab | 5882 | { |
5883 | switch (get_attr_opx_access (insn)) | |
5884 | { | |
5885 | case OPX_ACCESS_W: | |
5886 | return OP_MEM_1I; | |
5887 | ||
5888 | default: | |
3c904dda | 5889 | gcc_assert (!reload_completed); |
5890 | return OP_MEM_1I; | |
1d86aeab | 5891 | } |
5892 | } | |
5893 | ||
3c904dda | 5894 | if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN) |
1d86aeab | 5895 | return OP_MEM_I0; |
5896 | ||
3c904dda | 5897 | if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1) |
1d86aeab | 5898 | { |
5899 | switch (get_attr_opx_access (insn)) | |
5900 | { | |
5901 | case OPX_ACCESS_W: | |
5902 | return OP_MEM_I1; | |
5903 | ||
5904 | default: | |
3c904dda | 5905 | gcc_assert (!reload_completed); |
5906 | return OP_MEM_I1; | |
1d86aeab | 5907 | } |
5908 | } | |
5909 | ||
3c904dda | 5910 | gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6); |
5911 | gcc_assert (!reload_completed); | |
5912 | return OP_MEM_I1; | |
1d86aeab | 5913 | } |
5914 | ||
3c904dda | 5915 | /* Data for ColdFire V4 index bypass. |
5916 | Producer modifies register that is used as index in consumer with | |
5917 | specified scale. */ | |
5918 | static struct | |
15b9ea10 | 5919 | { |
3c904dda | 5920 | /* Producer instruction. */ |
5921 | rtx pro; | |
2ccdedfd | 5922 | |
3c904dda | 5923 | /* Consumer instruction. */ |
5924 | rtx con; | |
15b9ea10 | 5925 | |
3c904dda | 5926 | /* Scale of indexed memory access within consumer. |
5927 | Or zero if bypass should not be effective at the moment. */ | |
5928 | int scale; | |
5929 | } sched_cfv4_bypass_data; | |
15b9ea10 | 5930 | |
5931 | /* An empty state that is used in m68k_sched_adjust_cost. */ | |
5932 | static state_t sched_adjust_cost_state; | |
5933 | ||
5934 | /* Implement adjust_cost scheduler hook. | |
5935 | Return adjusted COST of dependency LINK between DEF_INSN and INSN. */ | |
5936 | static int | |
99f52c2b | 5937 | m68k_sched_adjust_cost (rtx_insn *insn, int, rtx_insn *def_insn, int cost, |
5938 | unsigned int) | |
15b9ea10 | 5939 | { |
5940 | int delay; | |
5941 | ||
5942 | if (recog_memoized (def_insn) < 0 | |
5943 | || recog_memoized (insn) < 0) | |
5944 | return cost; | |
5945 | ||
3c904dda | 5946 | if (sched_cfv4_bypass_data.scale == 1) |
5947 | /* Handle ColdFire V4 bypass for indexed address with 1x scale. */ | |
5948 | { | |
5949 | /* haifa-sched.c: insn_cost () calls bypass_p () just before | |
5950 | targetm.sched.adjust_cost (). Hence, we can be relatively sure | |
5951 | that the data in sched_cfv4_bypass_data is up to date. */ | |
5952 | gcc_assert (sched_cfv4_bypass_data.pro == def_insn | |
5953 | && sched_cfv4_bypass_data.con == insn); | |
5954 | ||
5955 | if (cost < 3) | |
5956 | cost = 3; | |
5957 | ||
5958 | sched_cfv4_bypass_data.pro = NULL; | |
5959 | sched_cfv4_bypass_data.con = NULL; | |
5960 | sched_cfv4_bypass_data.scale = 0; | |
5961 | } | |
5962 | else | |
5963 | gcc_assert (sched_cfv4_bypass_data.pro == NULL | |
5964 | && sched_cfv4_bypass_data.con == NULL | |
5965 | && sched_cfv4_bypass_data.scale == 0); | |
5966 | ||
15b9ea10 | 5967 | /* Don't try to issue INSN earlier than DFA permits. |
5968 | This is especially useful for instructions that write to memory, | |
5969 | as their true dependence (default) latency is better to be set to 0 | |
5970 | to workaround alias analysis limitations. | |
5971 | This is, in fact, a machine independent tweak, so, probably, | |
5972 | it should be moved to haifa-sched.c: insn_cost (). */ | |
15b9ea10 | 5973 | delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn); |
5974 | if (delay > cost) | |
5975 | cost = delay; | |
5976 | ||
5977 | return cost; | |
5978 | } | |
5979 | ||
3c904dda | 5980 | /* Return maximal number of insns that can be scheduled on a single cycle. */ |
5981 | static int | |
5982 | m68k_sched_issue_rate (void) | |
5983 | { | |
5984 | switch (m68k_sched_cpu) | |
5985 | { | |
5986 | case CPU_CFV1: | |
5987 | case CPU_CFV2: | |
5988 | case CPU_CFV3: | |
5989 | return 1; | |
5990 | ||
5991 | case CPU_CFV4: | |
5992 | return 2; | |
5993 | ||
5994 | default: | |
5995 | gcc_unreachable (); | |
5996 | return 0; | |
5997 | } | |
5998 | } | |
5999 | ||
2ccdedfd | 6000 | /* Maximal length of instruction for current CPU. |
6001 | E.g. it is 3 for any ColdFire core. */ | |
6002 | static int max_insn_size; | |
6003 | ||
6004 | /* Data to model instruction buffer of CPU. */ | |
6005 | struct _sched_ib | |
6006 | { | |
3c904dda | 6007 | /* True if instruction buffer model is modeled for current CPU. */ |
6008 | bool enabled_p; | |
6009 | ||
2ccdedfd | 6010 | /* Size of the instruction buffer in words. */ |
6011 | int size; | |
6012 | ||
6013 | /* Number of filled words in the instruction buffer. */ | |
6014 | int filled; | |
6015 | ||
6016 | /* Additional information about instruction buffer for CPUs that have | |
6017 | a buffer of instruction records, rather then a plain buffer | |
6018 | of instruction words. */ | |
6019 | struct _sched_ib_records | |
6020 | { | |
6021 | /* Size of buffer in records. */ | |
6022 | int n_insns; | |
15b9ea10 | 6023 | |
2fbe7a32 | 6024 | /* Array to hold data on adjustments made to the size of the buffer. */ |
2ccdedfd | 6025 | int *adjust; |
15b9ea10 | 6026 | |
2ccdedfd | 6027 | /* Index of the above array. */ |
6028 | int adjust_index; | |
6029 | } records; | |
6030 | ||
6031 | /* An insn that reserves (marks empty) one word in the instruction buffer. */ | |
6032 | rtx insn; | |
6033 | }; | |
6034 | ||
6035 | static struct _sched_ib sched_ib; | |
15b9ea10 | 6036 | |
6037 | /* ID of memory unit. */ | |
6038 | static int sched_mem_unit_code; | |
6039 | ||
6040 | /* Implementation of the targetm.sched.variable_issue () hook. | |
6041 | It is called after INSN was issued. It returns the number of insns | |
6042 | that can possibly get scheduled on the current cycle. | |
6043 | It is used here to determine the effect of INSN on the instruction | |
6044 | buffer. */ | |
6045 | static int | |
6046 | m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6047 | int sched_verbose ATTRIBUTE_UNUSED, | |
18282db0 | 6048 | rtx_insn *insn, int can_issue_more) |
15b9ea10 | 6049 | { |
6050 | int insn_size; | |
6051 | ||
3c904dda | 6052 | if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE) |
15b9ea10 | 6053 | { |
2ccdedfd | 6054 | switch (m68k_sched_cpu) |
6055 | { | |
6056 | case CPU_CFV1: | |
6057 | case CPU_CFV2: | |
3c904dda | 6058 | insn_size = sched_get_attr_size_int (insn); |
2ccdedfd | 6059 | break; |
6060 | ||
6061 | case CPU_CFV3: | |
3c904dda | 6062 | insn_size = sched_get_attr_size_int (insn); |
2ccdedfd | 6063 | |
6064 | /* ColdFire V3 and V4 cores have instruction buffers that can | |
6065 | accumulate up to 8 instructions regardless of instructions' | |
6066 | sizes. So we should take care not to "prefetch" 24 one-word | |
6067 | or 12 two-words instructions. | |
6068 | To model this behavior we temporarily decrease size of the | |
6069 | buffer by (max_insn_size - insn_size) for next 7 instructions. */ | |
6070 | { | |
6071 | int adjust; | |
6072 | ||
6073 | adjust = max_insn_size - insn_size; | |
6074 | sched_ib.size -= adjust; | |
6075 | ||
6076 | if (sched_ib.filled > sched_ib.size) | |
6077 | sched_ib.filled = sched_ib.size; | |
6078 | ||
6079 | sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust; | |
6080 | } | |
6081 | ||
6082 | ++sched_ib.records.adjust_index; | |
6083 | if (sched_ib.records.adjust_index == sched_ib.records.n_insns) | |
6084 | sched_ib.records.adjust_index = 0; | |
6085 | ||
2fbe7a32 | 6086 | /* Undo adjustment we did 7 instructions ago. */ |
2ccdedfd | 6087 | sched_ib.size |
6088 | += sched_ib.records.adjust[sched_ib.records.adjust_index]; | |
6089 | ||
6090 | break; | |
15b9ea10 | 6091 | |
3c904dda | 6092 | case CPU_CFV4: |
6093 | gcc_assert (!sched_ib.enabled_p); | |
6094 | insn_size = 0; | |
6095 | break; | |
6096 | ||
2ccdedfd | 6097 | default: |
6098 | gcc_unreachable (); | |
6099 | } | |
15b9ea10 | 6100 | |
3dd7d6a7 | 6101 | if (insn_size > sched_ib.filled) |
6102 | /* Scheduling for register pressure does not always take DFA into | |
6103 | account. Workaround instruction buffer not being filled enough. */ | |
6104 | { | |
11189c7a | 6105 | gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED); |
3dd7d6a7 | 6106 | insn_size = sched_ib.filled; |
6107 | } | |
6108 | ||
15b9ea10 | 6109 | --can_issue_more; |
6110 | } | |
6111 | else if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6112 | || asm_noperands (PATTERN (insn)) >= 0) | |
2ccdedfd | 6113 | insn_size = sched_ib.filled; |
15b9ea10 | 6114 | else |
6115 | insn_size = 0; | |
6116 | ||
2ccdedfd | 6117 | sched_ib.filled -= insn_size; |
15b9ea10 | 6118 | |
6119 | return can_issue_more; | |
6120 | } | |
6121 | ||
3c904dda | 6122 | /* Return how many instructions should scheduler lookahead to choose the |
6123 | best one. */ | |
6124 | static int | |
6125 | m68k_sched_first_cycle_multipass_dfa_lookahead (void) | |
15b9ea10 | 6126 | { |
3c904dda | 6127 | return m68k_sched_issue_rate () - 1; |
15b9ea10 | 6128 | } |
6129 | ||
c8e5dcf5 | 6130 | /* Implementation of targetm.sched.init_global () hook. |
15b9ea10 | 6131 | It is invoked once per scheduling pass and is used here |
6132 | to initialize scheduler constants. */ | |
6133 | static void | |
6134 | m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6135 | int sched_verbose ATTRIBUTE_UNUSED, | |
6136 | int n_insns ATTRIBUTE_UNUSED) | |
6137 | { | |
3c904dda | 6138 | /* Check that all instructions have DFA reservations and |
6139 | that all instructions can be issued from a clean state. */ | |
1d674b45 | 6140 | if (flag_checking) |
6141 | { | |
6142 | rtx_insn *insn; | |
6143 | state_t state; | |
15b9ea10 | 6144 | |
1d674b45 | 6145 | state = alloca (state_size ()); |
15b9ea10 | 6146 | |
1d674b45 | 6147 | for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) |
6148 | { | |
6149 | if (INSN_P (insn) && recog_memoized (insn) >= 0) | |
6150 | { | |
6151 | gcc_assert (insn_has_dfa_reservation_p (insn)); | |
15b9ea10 | 6152 | |
1d674b45 | 6153 | state_reset (state); |
6154 | if (state_transition (state, insn) >= 0) | |
6155 | gcc_unreachable (); | |
6156 | } | |
6157 | } | |
6158 | } | |
15b9ea10 | 6159 | |
6160 | /* Setup target cpu. */ | |
3c904dda | 6161 | |
6162 | /* ColdFire V4 has a set of features to keep its instruction buffer full | |
6163 | (e.g., a separate memory bus for instructions) and, hence, we do not model | |
6164 | buffer for this CPU. */ | |
6165 | sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4); | |
6166 | ||
15b9ea10 | 6167 | switch (m68k_sched_cpu) |
6168 | { | |
3c904dda | 6169 | case CPU_CFV4: |
6170 | sched_ib.filled = 0; | |
6171 | ||
6172 | /* FALLTHRU */ | |
6173 | ||
2ccdedfd | 6174 | case CPU_CFV1: |
6175 | case CPU_CFV2: | |
6176 | max_insn_size = 3; | |
6177 | sched_ib.records.n_insns = 0; | |
6178 | sched_ib.records.adjust = NULL; | |
6179 | break; | |
6180 | ||
6181 | case CPU_CFV3: | |
6182 | max_insn_size = 3; | |
6183 | sched_ib.records.n_insns = 8; | |
225ab426 | 6184 | sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns); |
15b9ea10 | 6185 | break; |
6186 | ||
6187 | default: | |
6188 | gcc_unreachable (); | |
6189 | } | |
6190 | ||
2ccdedfd | 6191 | sched_mem_unit_code = get_cpu_unit_code ("cf_mem1"); |
6192 | ||
15b9ea10 | 6193 | sched_adjust_cost_state = xmalloc (state_size ()); |
6194 | state_reset (sched_adjust_cost_state); | |
6195 | ||
6196 | start_sequence (); | |
6197 | emit_insn (gen_ib ()); | |
2ccdedfd | 6198 | sched_ib.insn = get_insns (); |
15b9ea10 | 6199 | end_sequence (); |
6200 | } | |
6201 | ||
6202 | /* Scheduling pass is now finished. Free/reset static variables. */ | |
6203 | static void | |
6204 | m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
6205 | int verbose ATTRIBUTE_UNUSED) | |
6206 | { | |
2ccdedfd | 6207 | sched_ib.insn = NULL; |
15b9ea10 | 6208 | |
6209 | free (sched_adjust_cost_state); | |
6210 | sched_adjust_cost_state = NULL; | |
6211 | ||
6212 | sched_mem_unit_code = 0; | |
2ccdedfd | 6213 | |
6214 | free (sched_ib.records.adjust); | |
6215 | sched_ib.records.adjust = NULL; | |
6216 | sched_ib.records.n_insns = 0; | |
6217 | max_insn_size = 0; | |
15b9ea10 | 6218 | } |
6219 | ||
c8e5dcf5 | 6220 | /* Implementation of targetm.sched.init () hook. |
15b9ea10 | 6221 | It is invoked each time scheduler starts on the new block (basic block or |
6222 | extended basic block). */ | |
6223 | static void | |
6224 | m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6225 | int sched_verbose ATTRIBUTE_UNUSED, | |
6226 | int n_insns ATTRIBUTE_UNUSED) | |
6227 | { | |
2ccdedfd | 6228 | switch (m68k_sched_cpu) |
6229 | { | |
6230 | case CPU_CFV1: | |
6231 | case CPU_CFV2: | |
6232 | sched_ib.size = 6; | |
6233 | break; | |
6234 | ||
6235 | case CPU_CFV3: | |
6236 | sched_ib.size = sched_ib.records.n_insns * max_insn_size; | |
6237 | ||
6238 | memset (sched_ib.records.adjust, 0, | |
6239 | sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust)); | |
6240 | sched_ib.records.adjust_index = 0; | |
6241 | break; | |
6242 | ||
3c904dda | 6243 | case CPU_CFV4: |
6244 | gcc_assert (!sched_ib.enabled_p); | |
6245 | sched_ib.size = 0; | |
6246 | break; | |
6247 | ||
2ccdedfd | 6248 | default: |
6249 | gcc_unreachable (); | |
6250 | } | |
6251 | ||
3c904dda | 6252 | if (sched_ib.enabled_p) |
6253 | /* haifa-sched.c: schedule_block () calls advance_cycle () just before | |
6254 | the first cycle. Workaround that. */ | |
6255 | sched_ib.filled = -2; | |
15b9ea10 | 6256 | } |
6257 | ||
6258 | /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook. | |
6259 | It is invoked just before current cycle finishes and is used here | |
6260 | to track if instruction buffer got its two words this cycle. */ | |
6261 | static void | |
6262 | m68k_sched_dfa_pre_advance_cycle (void) | |
6263 | { | |
3c904dda | 6264 | if (!sched_ib.enabled_p) |
6265 | return; | |
6266 | ||
15b9ea10 | 6267 | if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code)) |
6268 | { | |
2ccdedfd | 6269 | sched_ib.filled += 2; |
15b9ea10 | 6270 | |
2ccdedfd | 6271 | if (sched_ib.filled > sched_ib.size) |
6272 | sched_ib.filled = sched_ib.size; | |
15b9ea10 | 6273 | } |
6274 | } | |
6275 | ||
6276 | /* Implementation of targetm.sched.dfa_post_advance_cycle () hook. | |
6277 | It is invoked just after new cycle begins and is used here | |
6278 | to setup number of filled words in the instruction buffer so that | |
6279 | instructions which won't have all their words prefetched would be | |
6280 | stalled for a cycle. */ | |
6281 | static void | |
6282 | m68k_sched_dfa_post_advance_cycle (void) | |
6283 | { | |
6284 | int i; | |
15b9ea10 | 6285 | |
3c904dda | 6286 | if (!sched_ib.enabled_p) |
6287 | return; | |
6288 | ||
15b9ea10 | 6289 | /* Setup number of prefetched instruction words in the instruction |
6290 | buffer. */ | |
2ccdedfd | 6291 | i = max_insn_size - sched_ib.filled; |
6292 | ||
6293 | while (--i >= 0) | |
15b9ea10 | 6294 | { |
2ccdedfd | 6295 | if (state_transition (curr_state, sched_ib.insn) >= 0) |
57248c05 | 6296 | /* Pick up scheduler state. */ |
6297 | ++sched_ib.filled; | |
15b9ea10 | 6298 | } |
6299 | } | |
3c904dda | 6300 | |
6301 | /* Return X or Y (depending on OPX_P) operand of INSN, | |
6302 | if it is an integer register, or NULL overwise. */ | |
6303 | static rtx | |
ed3e6e5d | 6304 | sched_get_reg_operand (rtx_insn *insn, bool opx_p) |
3c904dda | 6305 | { |
6306 | rtx op = NULL; | |
6307 | ||
6308 | if (opx_p) | |
6309 | { | |
6310 | if (get_attr_opx_type (insn) == OPX_TYPE_RN) | |
6311 | { | |
6312 | op = sched_get_operand (insn, true); | |
6313 | gcc_assert (op != NULL); | |
6314 | ||
6315 | if (!reload_completed && !REG_P (op)) | |
6316 | return NULL; | |
6317 | } | |
6318 | } | |
6319 | else | |
6320 | { | |
6321 | if (get_attr_opy_type (insn) == OPY_TYPE_RN) | |
6322 | { | |
6323 | op = sched_get_operand (insn, false); | |
6324 | gcc_assert (op != NULL); | |
6325 | ||
6326 | if (!reload_completed && !REG_P (op)) | |
6327 | return NULL; | |
6328 | } | |
6329 | } | |
6330 | ||
6331 | return op; | |
6332 | } | |
6333 | ||
6334 | /* Return true, if X or Y (depending on OPX_P) operand of INSN | |
6335 | is a MEM. */ | |
6336 | static bool | |
d3ffa7b4 | 6337 | sched_mem_operand_p (rtx_insn *insn, bool opx_p) |
3c904dda | 6338 | { |
6339 | switch (sched_get_opxy_mem_type (insn, opx_p)) | |
6340 | { | |
6341 | case OP_TYPE_MEM1: | |
6342 | case OP_TYPE_MEM6: | |
6343 | return true; | |
6344 | ||
6345 | default: | |
6346 | return false; | |
6347 | } | |
6348 | } | |
6349 | ||
6350 | /* Return X or Y (depending on OPX_P) operand of INSN, | |
6351 | if it is a MEM, or NULL overwise. */ | |
6352 | static rtx | |
ed3e6e5d | 6353 | sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p) |
3c904dda | 6354 | { |
6355 | bool opx_p; | |
6356 | bool opy_p; | |
6357 | ||
6358 | opx_p = false; | |
6359 | opy_p = false; | |
6360 | ||
6361 | if (must_read_p) | |
6362 | { | |
6363 | opx_p = true; | |
6364 | opy_p = true; | |
6365 | } | |
6366 | ||
6367 | if (must_write_p) | |
6368 | { | |
6369 | opx_p = true; | |
6370 | opy_p = false; | |
6371 | } | |
6372 | ||
6373 | if (opy_p && sched_mem_operand_p (insn, false)) | |
6374 | return sched_get_operand (insn, false); | |
6375 | ||
6376 | if (opx_p && sched_mem_operand_p (insn, true)) | |
6377 | return sched_get_operand (insn, true); | |
6378 | ||
6379 | gcc_unreachable (); | |
6380 | return NULL; | |
6381 | } | |
6382 | ||
6383 | /* Return non-zero if PRO modifies register used as part of | |
6384 | address in CON. */ | |
6385 | int | |
ed3e6e5d | 6386 | m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con) |
3c904dda | 6387 | { |
6388 | rtx pro_x; | |
6389 | rtx con_mem_read; | |
6390 | ||
6391 | pro_x = sched_get_reg_operand (pro, true); | |
6392 | if (pro_x == NULL) | |
6393 | return 0; | |
6394 | ||
6395 | con_mem_read = sched_get_mem_operand (con, true, false); | |
6396 | gcc_assert (con_mem_read != NULL); | |
6397 | ||
6398 | if (reg_mentioned_p (pro_x, con_mem_read)) | |
6399 | return 1; | |
6400 | ||
6401 | return 0; | |
6402 | } | |
6403 | ||
6404 | /* Helper function for m68k_sched_indexed_address_bypass_p. | |
6405 | if PRO modifies register used as index in CON, | |
6406 | return scale of indexed memory access in CON. Return zero overwise. */ | |
6407 | static int | |
ed3e6e5d | 6408 | sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con) |
3c904dda | 6409 | { |
6410 | rtx reg; | |
6411 | rtx mem; | |
6412 | struct m68k_address address; | |
6413 | ||
6414 | reg = sched_get_reg_operand (pro, true); | |
6415 | if (reg == NULL) | |
6416 | return 0; | |
6417 | ||
6418 | mem = sched_get_mem_operand (con, true, false); | |
6419 | gcc_assert (mem != NULL && MEM_P (mem)); | |
6420 | ||
6421 | if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed, | |
6422 | &address)) | |
6423 | gcc_unreachable (); | |
6424 | ||
6425 | if (REGNO (reg) == REGNO (address.index)) | |
6426 | { | |
6427 | gcc_assert (address.scale != 0); | |
6428 | return address.scale; | |
6429 | } | |
6430 | ||
6431 | return 0; | |
6432 | } | |
6433 | ||
6434 | /* Return non-zero if PRO modifies register used | |
6435 | as index with scale 2 or 4 in CON. */ | |
6436 | int | |
ed3e6e5d | 6437 | m68k_sched_indexed_address_bypass_p (rtx_insn *pro, rtx_insn *con) |
3c904dda | 6438 | { |
6439 | gcc_assert (sched_cfv4_bypass_data.pro == NULL | |
6440 | && sched_cfv4_bypass_data.con == NULL | |
6441 | && sched_cfv4_bypass_data.scale == 0); | |
6442 | ||
6443 | switch (sched_get_indexed_address_scale (pro, con)) | |
6444 | { | |
6445 | case 1: | |
6446 | /* We can't have a variable latency bypass, so | |
6447 | remember to adjust the insn cost in adjust_cost hook. */ | |
6448 | sched_cfv4_bypass_data.pro = pro; | |
6449 | sched_cfv4_bypass_data.con = con; | |
6450 | sched_cfv4_bypass_data.scale = 1; | |
6451 | return 0; | |
6452 | ||
6453 | case 2: | |
6454 | case 4: | |
6455 | return 1; | |
6456 | ||
6457 | default: | |
6458 | return 0; | |
6459 | } | |
6460 | } | |
869bde6b | 6461 | |
61fafd77 | 6462 | /* We generate a two-instructions program at M_TRAMP : |
6463 | movea.l &CHAIN_VALUE,%a0 | |
6464 | jmp FNADDR | |
6465 | where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */ | |
6466 | ||
6467 | static void | |
6468 | m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
6469 | { | |
6470 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
6471 | rtx mem; | |
6472 | ||
6473 | gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM)); | |
6474 | ||
6475 | mem = adjust_address (m_tramp, HImode, 0); | |
6476 | emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); | |
6477 | mem = adjust_address (m_tramp, SImode, 2); | |
6478 | emit_move_insn (mem, chain_value); | |
6479 | ||
6480 | mem = adjust_address (m_tramp, HImode, 6); | |
6481 | emit_move_insn (mem, GEN_INT(0x4EF9)); | |
6482 | mem = adjust_address (m_tramp, SImode, 8); | |
6483 | emit_move_insn (mem, fnaddr); | |
6484 | ||
6485 | FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0)); | |
6486 | } | |
6487 | ||
f5bc28da | 6488 | /* On the 68000, the RTS insn cannot pop anything. |
6489 | On the 68010, the RTD insn may be used to pop them if the number | |
6490 | of args is fixed, but if the number is variable then the caller | |
6491 | must pop them all. RTD can't be used for library calls now | |
6492 | because the library is compiled with the Unix compiler. | |
6493 | Use of RTD is a selectable option, since it is incompatible with | |
6494 | standard Unix calling sequences. If the option is not selected, | |
6495 | the caller must always pop the args. */ | |
6496 | ||
6497 | static int | |
6498 | m68k_return_pops_args (tree fundecl, tree funtype, int size) | |
6499 | { | |
6500 | return ((TARGET_RTD | |
6501 | && (!fundecl | |
6502 | || TREE_CODE (fundecl) != IDENTIFIER_NODE) | |
257d99c3 | 6503 | && (!stdarg_p (funtype))) |
f5bc28da | 6504 | ? size : 0); |
6505 | } | |
6506 | ||
b2d7ede1 | 6507 | /* Make sure everything's fine if we *don't* have a given processor. |
6508 | This assumes that putting a register in fixed_regs will keep the | |
6509 | compiler's mitts completely off it. We don't bother to zero it out | |
6510 | of register classes. */ | |
6511 | ||
6512 | static void | |
6513 | m68k_conditional_register_usage (void) | |
6514 | { | |
6515 | int i; | |
6516 | HARD_REG_SET x; | |
6517 | if (!TARGET_HARD_FLOAT) | |
6518 | { | |
6519 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); | |
6520 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
6521 | if (TEST_HARD_REG_BIT (x, i)) | |
6522 | fixed_regs[i] = call_used_regs[i] = 1; | |
6523 | } | |
6524 | if (flag_pic) | |
6525 | fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; | |
6526 | } | |
6527 | ||
5bb27b7c | 6528 | static void |
6529 | m68k_init_sync_libfuncs (void) | |
6530 | { | |
6531 | init_sync_libfuncs (UNITS_PER_WORD); | |
6532 | } | |
6533 | ||
df47af5a | 6534 | /* Implements EPILOGUE_USES. All registers are live on exit from an |
6535 | interrupt routine. */ | |
6536 | bool | |
6537 | m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED) | |
6538 | { | |
6539 | return (reload_completed | |
6540 | && (m68k_get_function_kind (current_function_decl) | |
6541 | == m68k_fk_interrupt_handler)); | |
6542 | } | |
6543 | ||
41af789c | 6544 | |
6545 | /* Implement TARGET_C_EXCESS_PRECISION. | |
6546 | ||
6547 | Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp | |
6548 | instructions, we get proper intermediate rounding, otherwise we | |
6549 | get extended precision results. */ | |
6550 | ||
6551 | static enum flt_eval_method | |
6552 | m68k_excess_precision (enum excess_precision_type type) | |
6553 | { | |
6554 | switch (type) | |
6555 | { | |
6556 | case EXCESS_PRECISION_TYPE_FAST: | |
6557 | /* The fastest type to promote to will always be the native type, | |
6558 | whether that occurs with implicit excess precision or | |
6559 | otherwise. */ | |
6560 | return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT; | |
6561 | case EXCESS_PRECISION_TYPE_STANDARD: | |
6562 | case EXCESS_PRECISION_TYPE_IMPLICIT: | |
6563 | /* Otherwise, the excess precision we want when we are | |
6564 | in a standards compliant mode, and the implicit precision we | |
6565 | provide can be identical. */ | |
6566 | if (TARGET_68040 || ! TARGET_68881) | |
6567 | return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT; | |
6568 | ||
6569 | return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE; | |
6570 | default: | |
6571 | gcc_unreachable (); | |
6572 | } | |
6573 | return FLT_EVAL_METHOD_UNPREDICTABLE; | |
6574 | } | |
6575 | ||
869bde6b | 6576 | #include "gt-m68k.h" |