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01bbf777 | 1 | /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. |
cf011243 | 2 | Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
2f83c7d6 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
25a1b918 | 4 | |
7ec022b2 | 5 | This file is part of GCC. |
3d339ad2 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
3d339ad2 | 8 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
3d339ad2 RS |
10 | any later version. |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
3d339ad2 RS |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
3d339ad2 | 20 | |
f082d7a9 GN |
21 | /* We need to have MOTOROLA always defined (either 0 or 1) because we use |
22 | if-statements and ?: on it. This way we have compile-time error checking | |
23 | for both the MOTOROLA and MIT code paths. We do rely on the host compiler | |
24 | to optimize away all constant tests. */ | |
a96533d5 | 25 | #if MOTOROLA /* Use the Motorola assembly syntax. */ |
f082d7a9 GN |
26 | # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") |
27 | #else | |
f082d7a9 | 28 | # define MOTOROLA 0 /* Use the MIT assembly syntax. */ |
a96533d5 | 29 | # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") |
f082d7a9 | 30 | #endif |
3d339ad2 | 31 | |
59fbf3cb NS |
32 | /* Handle --with-cpu default option from configure script. */ |
33 | #define OPTION_DEFAULT_SPECS \ | |
34 | { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\ | |
35 | %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\ | |
36 | %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\ | |
900ec02d | 37 | %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" }, |
59fbf3cb | 38 | |
0c004537 RS |
39 | /* Pass flags to gas indicating which type of processor we have. This |
40 | can be simplified when we can rely on the assembler supporting .cpu | |
41 | and .arch directives. */ | |
42 | ||
43 | #define ASM_CPU_SPEC "\ | |
44 | %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \ | |
45 | %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\ | |
46 | %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\ | |
47 | %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\ | |
900ec02d | 48 | %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ |
0c004537 | 49 | " |
bebb3a98 NS |
50 | #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \ |
51 | %{msep-data|mid-shared-library:--pcrel} \ | |
52 | " | |
0c004537 | 53 | |
bebb3a98 | 54 | #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)" |
0c004537 RS |
55 | |
56 | #define EXTRA_SPECS \ | |
57 | { "asm_cpu_spec", ASM_CPU_SPEC }, \ | |
bebb3a98 | 58 | { "asm_pcrel_spec", ASM_PCREL_SPEC }, \ |
0c004537 RS |
59 | SUBTARGET_EXTRA_SPECS |
60 | ||
61 | #define SUBTARGET_EXTRA_SPECS | |
62 | ||
3d339ad2 RS |
63 | /* Note that some other tm.h files include this one and then override |
64 | many of the definitions that relate to assembler syntax. */ | |
65 | ||
9c6de4a1 RS |
66 | #define TARGET_CPU_CPP_BUILTINS() \ |
67 | do \ | |
68 | { \ | |
69 | builtin_define ("__m68k__"); \ | |
70 | builtin_define_std ("mc68000"); \ | |
9321405c RS |
71 | /* The other mc680x0 macros have traditionally been derived \ |
72 | from the tuning setting. For example, -m68020-60 defines \ | |
73 | m68060, even though it generates pure 68020 code. */ \ | |
74 | switch (m68k_tune) \ | |
9c6de4a1 | 75 | { \ |
9321405c RS |
76 | case u68010: \ |
77 | builtin_define_std ("mc68010"); \ | |
78 | break; \ | |
79 | \ | |
80 | case u68020: \ | |
81 | builtin_define_std ("mc68020"); \ | |
82 | break; \ | |
83 | \ | |
84 | case u68030: \ | |
85 | builtin_define_std ("mc68030"); \ | |
86 | break; \ | |
87 | \ | |
88 | case u68040: \ | |
89 | builtin_define_std ("mc68040"); \ | |
90 | break; \ | |
91 | \ | |
92 | case u68060: \ | |
93 | builtin_define_std ("mc68060"); \ | |
94 | break; \ | |
95 | \ | |
96 | case u68020_60: \ | |
9c6de4a1 | 97 | builtin_define_std ("mc68060"); \ |
9321405c RS |
98 | /* Fall through. */ \ |
99 | case u68020_40: \ | |
9c6de4a1 RS |
100 | builtin_define_std ("mc68040"); \ |
101 | builtin_define_std ("mc68030"); \ | |
102 | builtin_define_std ("mc68020"); \ | |
9321405c RS |
103 | break; \ |
104 | \ | |
105 | case ucpu32: \ | |
106 | builtin_define_std ("mc68332"); \ | |
107 | builtin_define_std ("mcpu32"); \ | |
9c6de4a1 | 108 | builtin_define_std ("mc68020"); \ |
9321405c RS |
109 | break; \ |
110 | \ | |
7eb4f044 NS |
111 | case ucfv2: \ |
112 | builtin_define ("__mcfv2__"); \ | |
113 | break; \ | |
114 | \ | |
115 | case ucfv3: \ | |
116 | builtin_define ("__mcfv3__"); \ | |
117 | break; \ | |
118 | \ | |
119 | case ucfv4: \ | |
120 | builtin_define ("__mcfv4__"); \ | |
121 | break; \ | |
122 | \ | |
123 | case ucfv4e: \ | |
124 | builtin_define ("__mcfv4e__"); \ | |
125 | break; \ | |
126 | \ | |
127 | case ucfv5: \ | |
128 | builtin_define ("__mcfv5__"); \ | |
129 | break; \ | |
130 | \ | |
9321405c RS |
131 | default: \ |
132 | break; \ | |
9c6de4a1 | 133 | } \ |
9321405c | 134 | \ |
9c6de4a1 RS |
135 | if (TARGET_68881) \ |
136 | builtin_define ("__HAVE_68881__"); \ | |
9321405c | 137 | \ |
9c6de4a1 | 138 | if (TARGET_COLDFIRE) \ |
9c6de4a1 | 139 | { \ |
7eb4f044 NS |
140 | const char *tmp; \ |
141 | \ | |
142 | tmp = m68k_cpp_cpu_ident ("cf"); \ | |
143 | if (tmp) \ | |
144 | builtin_define (tmp); \ | |
145 | tmp = m68k_cpp_cpu_family ("cf"); \ | |
146 | if (tmp) \ | |
147 | builtin_define (tmp); \ | |
900ec02d | 148 | builtin_define ("__mcoldfire__"); \ |
7eb4f044 | 149 | \ |
900ec02d JB |
150 | if (TARGET_ISAC) \ |
151 | builtin_define ("__mcfisac__"); \ | |
152 | else if (TARGET_ISAB) \ | |
153 | { \ | |
154 | builtin_define ("__mcfisab__"); \ | |
155 | /* ISA_B: Legacy 5407 defines. */ \ | |
156 | builtin_define ("__mcf5400__"); \ | |
157 | builtin_define ("__mcf5407__"); \ | |
158 | } \ | |
159 | else if (TARGET_ISAAPLUS) \ | |
160 | { \ | |
161 | builtin_define ("__mcfisaaplus__"); \ | |
162 | /* ISA_A+: legacy defines. */ \ | |
163 | builtin_define ("__mcf528x__"); \ | |
164 | builtin_define ("__mcf5200__"); \ | |
165 | } \ | |
166 | else \ | |
167 | { \ | |
168 | builtin_define ("__mcfisaa__"); \ | |
169 | /* ISA_A: legacy defines. */ \ | |
170 | switch (m68k_tune) \ | |
171 | { \ | |
172 | case ucfv2: \ | |
173 | builtin_define ("__mcf5200__"); \ | |
174 | break; \ | |
175 | \ | |
176 | case ucfv3: \ | |
177 | builtin_define ("__mcf5307__"); \ | |
178 | builtin_define ("__mcf5300__"); \ | |
179 | break; \ | |
180 | \ | |
181 | default: \ | |
182 | break; \ | |
183 | } \ | |
184 | } \ | |
9c6de4a1 | 185 | } \ |
900ec02d | 186 | \ |
7eb4f044 NS |
187 | if (TARGET_COLDFIRE_FPU) \ |
188 | builtin_define ("__mcffpu__"); \ | |
189 | \ | |
9c6de4a1 RS |
190 | if (TARGET_CF_HWDIV) \ |
191 | builtin_define ("__mcfhwdiv__"); \ | |
900ec02d | 192 | \ |
7d33c31d KH |
193 | if (TARGET_FIDOA) \ |
194 | builtin_define ("__mfido__"); \ | |
195 | \ | |
9c6de4a1 RS |
196 | builtin_assert ("cpu=m68k"); \ |
197 | builtin_assert ("machine=m68k"); \ | |
198 | } \ | |
a7fbe404 NB |
199 | while (0) |
200 | ||
301d03af RS |
201 | /* Classify the groups of pseudo-ops used to assemble QI, HI and SI |
202 | quantities. */ | |
203 | #define INT_OP_STANDARD 0 /* .byte, .short, .long */ | |
204 | #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ | |
205 | #define INT_OP_NO_DOT 2 /* byte, short, long */ | |
206 | #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ | |
207 | ||
859711c5 | 208 | /* Set the default. */ |
301d03af RS |
209 | #define INT_OP_GROUP INT_OP_DOT_WORD |
210 | ||
900ec02d JB |
211 | /* Bit values used by m68k-devices.def to identify processor capabilities. */ |
212 | #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ | |
213 | #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ | |
214 | #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ | |
215 | #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ | |
216 | #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ | |
217 | #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ | |
218 | #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ | |
219 | #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ | |
220 | #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ | |
221 | #define FL_ISA_68000 (1 << 9) | |
222 | #define FL_ISA_68010 (1 << 10) | |
223 | #define FL_ISA_68020 (1 << 11) | |
224 | #define FL_ISA_68040 (1 << 12) | |
225 | #define FL_ISA_A (1 << 13) | |
226 | #define FL_ISA_APLUS (1 << 14) | |
227 | #define FL_ISA_B (1 << 15) | |
228 | #define FL_ISA_C (1 << 16) | |
7d33c31d | 229 | #define FL_FIDOA (1 << 17) |
900ec02d JB |
230 | #define FL_MMU 0 /* Used by multilib machinery. */ |
231 | ||
232 | #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) | |
233 | #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) | |
b101567e | 234 | #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) |
900ec02d JB |
235 | #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) |
236 | #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) | |
237 | #define TARGET_68881 (m68k_fpu == FPUTYPE_68881) | |
7d33c31d | 238 | #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0) |
9e62c7f2 | 239 | |
dcc21c4c PB |
240 | /* Size (in bytes) of FPU registers. */ |
241 | #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) | |
242 | ||
900ec02d JB |
243 | #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) |
244 | #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) | |
245 | #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) | |
246 | ||
59c92f76 NS |
247 | /* Some instructions are common to more than one ISA. */ |
248 | #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC) | |
249 | #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC) | |
250 | ||
900ec02d JB |
251 | #define TUNE_68000 (m68k_tune == u68000) |
252 | #define TUNE_68010 (m68k_tune == u68010) | |
253 | #define TUNE_68000_10 (TUNE_68000 || TUNE_68010) | |
254 | #define TUNE_68030 (m68k_tune == u68030 \ | |
255 | || m68k_tune == u68020_40 \ | |
256 | || m68k_tune == u68020_60) | |
257 | #define TUNE_68040 (m68k_tune == u68040 \ | |
258 | || m68k_tune == u68020_40 \ | |
259 | || m68k_tune == u68020_60) | |
260 | #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) | |
9cf106c8 | 261 | #define TUNE_68040_60 (TUNE_68040 || TUNE_68060) |
900ec02d JB |
262 | #define TUNE_CPU32 (m68k_tune == ucpu32) |
263 | #define TUNE_CFV2 (m68k_tune == ucfv2) | |
dcc21c4c | 264 | |
adf2ac37 | 265 | #define OVERRIDE_OPTIONS override_options() |
84ab3bfb | 266 | |
9e62c7f2 | 267 | /* These are meant to be redefined in the host dependent files */ |
84ab3bfb | 268 | #define SUBTARGET_OVERRIDE_OPTIONS |
3d339ad2 RS |
269 | \f |
270 | /* target machine storage layout */ | |
271 | ||
72120463 KH |
272 | /* "long double" is the same as "double" on ColdFire and fido |
273 | targets. */ | |
5189ab94 | 274 | |
72120463 KH |
275 | #define LONG_DOUBLE_TYPE_SIZE \ |
276 | ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80) | |
5189ab94 JB |
277 | |
278 | /* We need to know the size of long double at compile-time in libgcc2. */ | |
279 | ||
72120463 | 280 | #if defined(__mcoldfire__) || defined(__mfido__) |
5189ab94 JB |
281 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 |
282 | #else | |
283 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 | |
284 | #endif | |
ade83c33 BI |
285 | |
286 | /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp | |
287 | instructions, we get proper intermediate rounding, otherwise we | |
288 | get extended precision results. */ | |
b101567e | 289 | #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) |
d57a4b98 | 290 | |
3d339ad2 | 291 | #define BITS_BIG_ENDIAN 1 |
3d339ad2 | 292 | #define BYTES_BIG_ENDIAN 1 |
3d339ad2 RS |
293 | #define WORDS_BIG_ENDIAN 1 |
294 | ||
3d339ad2 RS |
295 | #define UNITS_PER_WORD 4 |
296 | ||
3d339ad2 | 297 | #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) |
3d339ad2 | 298 | #define STACK_BOUNDARY 16 |
225d221a | 299 | #define FUNCTION_BOUNDARY 16 |
3d339ad2 | 300 | #define EMPTY_FIELD_BOUNDARY 16 |
e3e093ec KH |
301 | /* ColdFire and fido strongly prefer a 32-bit aligned stack. */ |
302 | #define PREFERRED_STACK_BOUNDARY \ | |
303 | ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16) | |
3d339ad2 | 304 | |
859711c5 | 305 | /* No data type wants to be aligned rounder than this. |
85f65093 | 306 | Most published ABIs say that ints should be aligned on 16-bit |
859711c5 | 307 | boundaries, but CPUs with 32-bit busses get better performance |
c16eadc7 KH |
308 | aligned on 32-bit boundaries. ColdFires without a misalignment |
309 | module require 32-bit alignment. */ | |
dcd13066 | 310 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) |
3d339ad2 | 311 | |
b71733d5 | 312 | #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) |
3d339ad2 | 313 | |
3d339ad2 RS |
314 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) |
315 | ||
86702e31 | 316 | /* Define these to avoid dependence on meaning of `int'. */ |
3d339ad2 RS |
317 | #define WCHAR_TYPE "long int" |
318 | #define WCHAR_TYPE_SIZE 32 | |
859711c5 BI |
319 | |
320 | /* Maximum number of library IDs we permit with -mid-shared-library. */ | |
321 | #define MAX_LIBRARY_ID 255 | |
322 | ||
3d339ad2 RS |
323 | \f |
324 | /* Standard register usage. */ | |
325 | ||
859711c5 BI |
326 | /* For the m68k, we give the data registers numbers 0-7, |
327 | the address registers numbers 010-017 (8-15), | |
c8832aae AS |
328 | and the 68881 floating point registers numbers 020-027 (16-23). |
329 | We also have a fake `arg-pointer' register 030 (24) used for | |
859711c5 | 330 | register elimination. */ |
860c4900 | 331 | #define FIRST_PSEUDO_REGISTER 25 |
3d339ad2 | 332 | |
859711c5 | 333 | /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ |
4ab870f5 RS |
334 | #define PIC_OFFSET_TABLE_REGNUM \ |
335 | (!flag_pic ? INVALID_REGNUM \ | |
336 | : reload_completed ? REGNO (pic_offset_table_rtx) \ | |
337 | : PIC_REG) | |
3d339ad2 | 338 | |
3d339ad2 RS |
339 | /* 1 for registers that have pervasive standard uses |
340 | and are not available for the register allocator. | |
859711c5 BI |
341 | On the m68k, only the stack pointer is such. |
342 | Our fake arg-pointer is obviously fixed as well. */ | |
3d339ad2 RS |
343 | #define FIXED_REGISTERS \ |
344 | {/* Data registers. */ \ | |
345 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
346 | \ | |
347 | /* Address registers. */ \ | |
348 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
349 | \ | |
350 | /* Floating point registers \ | |
351 | (if available). */ \ | |
a4e9467d RZ |
352 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
353 | \ | |
354 | /* Arg pointer. */ \ | |
355 | 1 } | |
3d339ad2 RS |
356 | |
357 | /* 1 for registers not available across function calls. | |
358 | These must include the FIXED_REGISTERS and also any | |
359 | registers that can be used without being saved. | |
360 | The latter must include the registers where values are returned | |
361 | and the register where structure-value addresses are passed. | |
362 | Aside from that, you can include as many other registers as you like. */ | |
859711c5 BI |
363 | #define CALL_USED_REGISTERS \ |
364 | {/* Data registers. */ \ | |
365 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
366 | \ | |
367 | /* Address registers. */ \ | |
368 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
369 | \ | |
370 | /* Floating point registers \ | |
371 | (if available). */ \ | |
372 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
373 | \ | |
374 | /* Arg pointer. */ \ | |
375 | 1 } | |
a4e9467d RZ |
376 | |
377 | #define REG_ALLOC_ORDER \ | |
378 | { /* d0/d1/a0/a1 */ \ | |
379 | 0, 1, 8, 9, \ | |
380 | /* d2-d7 */ \ | |
381 | 2, 3, 4, 5, 6, 7, \ | |
382 | /* a2-a7/arg */ \ | |
383 | 10, 11, 12, 13, 14, 15, 24, \ | |
384 | /* fp0-fp7 */ \ | |
385 | 16, 17, 18, 19, 20, 21, 22, 23\ | |
386 | } | |
3d339ad2 | 387 | |
3d339ad2 RS |
388 | |
389 | /* Make sure everything's fine if we *don't* have a given processor. | |
390 | This assumes that putting a register in fixed_regs will keep the | |
391 | compiler's mitts completely off it. We don't bother to zero it out | |
15a17b72 | 392 | of register classes. */ |
5b43fed1 | 393 | #define CONDITIONAL_REGISTER_USAGE \ |
859711c5 BI |
394 | { \ |
395 | int i; \ | |
396 | HARD_REG_SET x; \ | |
dcc21c4c | 397 | if (!TARGET_HARD_FLOAT) \ |
859711c5 | 398 | { \ |
5b43fed1 | 399 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ |
859711c5 BI |
400 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
401 | if (TEST_HARD_REG_BIT (x, i)) \ | |
402 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
403 | } \ | |
4ab870f5 RS |
404 | if (flag_pic) \ |
405 | fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \ | |
3d339ad2 RS |
406 | } |
407 | ||
859711c5 | 408 | /* On the m68k, ordinary registers hold 32 bits worth; |
3d339ad2 RS |
409 | for the 68881 registers, a single register is always enough for |
410 | anything that can be stored in them at all. */ | |
411 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
412 | ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ | |
413 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
414 | ||
cfca21cb PB |
415 | /* A C expression that is nonzero if hard register NEW_REG can be |
416 | considered for use as a rename register for OLD_REG register. */ | |
417 | ||
418 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
419 | m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
420 | ||
3d339ad2 | 421 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
70028b61 | 422 | m68k_regno_mode_ok ((REGNO), (MODE)) |
3d339ad2 | 423 | |
ffa2596e RS |
424 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ |
425 | m68k_secondary_reload_class (CLASS, MODE, X) | |
426 | ||
3d339ad2 | 427 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
dcc21c4c | 428 | (! TARGET_HARD_FLOAT \ |
3d339ad2 RS |
429 | || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ |
430 | || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
431 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
432 | || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) | |
433 | ||
434 | /* Specify the registers used for certain standard purposes. | |
435 | The values of these macros are register numbers. */ | |
436 | ||
3bfe36dc | 437 | #define STACK_POINTER_REGNUM SP_REG |
3d339ad2 | 438 | |
859711c5 BI |
439 | /* Most m68k targets use %a6 as a frame pointer. The AmigaOS |
440 | ABI uses %a6 for shared library calls, therefore the frame | |
441 | pointer is shifted to %a5 on this target. */ | |
de41203b | 442 | #define FRAME_POINTER_REGNUM A6_REG |
3d339ad2 | 443 | |
3d339ad2 RS |
444 | #define FRAME_POINTER_REQUIRED 0 |
445 | ||
860c4900 BI |
446 | /* Base register for access to arguments of the function. |
447 | * This isn't a hardware register. It will be eliminated to the | |
448 | * stack pointer or frame pointer. | |
449 | */ | |
450 | #define ARG_POINTER_REGNUM 24 | |
3d339ad2 | 451 | |
3bfe36dc | 452 | #define STATIC_CHAIN_REGNUM A0_REG |
835b4008 | 453 | #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0" |
3d339ad2 RS |
454 | |
455 | /* Register in which address to store a structure value | |
456 | is passed to a function. */ | |
3bfe36dc | 457 | #define M68K_STRUCT_VALUE_REGNUM A1_REG |
3d339ad2 | 458 | |
859711c5 | 459 | \f |
3d339ad2 | 460 | |
859711c5 | 461 | /* The m68k has three kinds of registers, so eight classes would be |
3d339ad2 | 462 | a complete set. One of them is not needed. */ |
3d339ad2 RS |
463 | enum reg_class { |
464 | NO_REGS, DATA_REGS, | |
465 | ADDR_REGS, FP_REGS, | |
466 | GENERAL_REGS, DATA_OR_FP_REGS, | |
467 | ADDR_OR_FP_REGS, ALL_REGS, | |
468 | LIM_REG_CLASSES }; | |
469 | ||
470 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
471 | ||
3d339ad2 RS |
472 | #define REG_CLASS_NAMES \ |
473 | { "NO_REGS", "DATA_REGS", \ | |
474 | "ADDR_REGS", "FP_REGS", \ | |
475 | "GENERAL_REGS", "DATA_OR_FP_REGS", \ | |
476 | "ADDR_OR_FP_REGS", "ALL_REGS" } | |
477 | ||
3d339ad2 RS |
478 | #define REG_CLASS_CONTENTS \ |
479 | { \ | |
7a87758d AS |
480 | {0x00000000}, /* NO_REGS */ \ |
481 | {0x000000ff}, /* DATA_REGS */ \ | |
a4e9467d | 482 | {0x0100ff00}, /* ADDR_REGS */ \ |
7a87758d | 483 | {0x00ff0000}, /* FP_REGS */ \ |
a4e9467d | 484 | {0x0100ffff}, /* GENERAL_REGS */ \ |
7a87758d | 485 | {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ |
a4e9467d RZ |
486 | {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ |
487 | {0x01ffffff}, /* ALL_REGS */ \ | |
3d339ad2 RS |
488 | } |
489 | ||
a4e9467d RZ |
490 | extern enum reg_class regno_reg_class[]; |
491 | #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) | |
3d339ad2 RS |
492 | #define INDEX_REG_CLASS GENERAL_REGS |
493 | #define BASE_REG_CLASS ADDR_REGS | |
494 | ||
ffa2596e RS |
495 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
496 | m68k_preferred_reload_class (X, CLASS) | |
6c13d910 | 497 | |
859711c5 | 498 | /* On the m68k, this is the size of MODE in words, |
3d339ad2 | 499 | except in the FP regs, where a single reg is always enough. */ |
3d339ad2 RS |
500 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
501 | ((CLASS) == FP_REGS ? 1 \ | |
502 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
503 | ||
504 | /* Moves between fp regs and other regs are two insns. */ | |
cf011243 | 505 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
85dbf7e2 | 506 | ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) |
3d339ad2 RS |
507 | \f |
508 | /* Stack layout; function entry, exit and calling. */ | |
509 | ||
85dbf7e2 | 510 | #define STACK_GROWS_DOWNWARD 1 |
f62c8a5c | 511 | #define FRAME_GROWS_DOWNWARD 1 |
3d339ad2 RS |
512 | #define STARTING_FRAME_OFFSET 0 |
513 | ||
859711c5 BI |
514 | /* On the 680x0, sp@- in a byte insn really pushes a word. |
515 | On the ColdFire, sp@- in a byte insn pushes just a byte. */ | |
9425fb04 | 516 | #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) |
3d339ad2 | 517 | |
3d339ad2 RS |
518 | #define FIRST_PARM_OFFSET(FNDECL) 8 |
519 | ||
859711c5 | 520 | /* On the 68000, the RTS insn cannot pop anything. |
6b475ad5 BI |
521 | On the 68010, the RTD insn may be used to pop them if the number |
522 | of args is fixed, but if the number is variable then the caller | |
523 | must pop them all. RTD can't be used for library calls now | |
524 | because the library is compiled with the Unix compiler. | |
525 | Use of RTD is a selectable option, since it is incompatible with | |
526 | standard Unix calling sequences. If the option is not selected, | |
527 | the caller must always pop the args. */ | |
6b475ad5 BI |
528 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
529 | ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ | |
530 | && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ | |
531 | || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ | |
532 | == void_type_node))) \ | |
533 | ? (SIZE) : 0) | |
3d339ad2 | 534 | |
85dbf7e2 | 535 | /* On the m68k the return value defaults to D0. */ |
3d339ad2 | 536 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
3bfe36dc | 537 | gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG) |
3d339ad2 | 538 | |
85dbf7e2 | 539 | /* On the m68k the return value defaults to D0. */ |
3bfe36dc | 540 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG) |
3d339ad2 | 541 | |
85dbf7e2 | 542 | /* On the m68k, D0 is usually the only register used. */ |
3bfe36dc | 543 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG) |
3d339ad2 | 544 | |
7972af82 | 545 | /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for |
859711c5 BI |
546 | more than one register. |
547 | XXX This macro is m68k specific and used only for m68kemb.h. */ | |
7972af82 TW |
548 | #define NEEDS_UNTYPED_CALL 0 |
549 | ||
859711c5 | 550 | /* On the m68k, all arguments are usually pushed on the stack. */ |
3d339ad2 RS |
551 | #define FUNCTION_ARG_REGNO_P(N) 0 |
552 | \f | |
859711c5 | 553 | /* On the m68k, this is a single integer, which is a number of bytes |
3d339ad2 | 554 | of arguments scanned so far. */ |
3d339ad2 RS |
555 | #define CUMULATIVE_ARGS int |
556 | ||
859711c5 | 557 | /* On the m68k, the offset starts at 0. */ |
0f6937fe | 558 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
3d339ad2 RS |
559 | ((CUM) = 0) |
560 | ||
3d339ad2 RS |
561 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
562 | ((CUM) += ((MODE) != BLKmode \ | |
563 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
564 | : (int_size_in_bytes (TYPE) + 3) & ~3)) | |
565 | ||
859711c5 | 566 | /* On the m68k all args are always pushed. */ |
0988b758 | 567 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 |
3d339ad2 | 568 | |
3d339ad2 RS |
569 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
570 | asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) | |
571 | ||
3d339ad2 RS |
572 | #define EXIT_IGNORE_STACK 1 |
573 | ||
3d339ad2 | 574 | /* Output assembler code for a block containing the constant parts |
859711c5 | 575 | of a trampoline, leaving space for the variable parts. |
3d339ad2 | 576 | |
859711c5 | 577 | On the m68k, the trampoline looks like this: |
27a55d6b RK |
578 | movl #STATIC,a0 |
579 | jmp FUNCTION | |
580 | ||
581 | WARNING: Targets that may run on 68040+ cpus must arrange for | |
582 | the instruction cache to be flushed. Previous incarnations of | |
583 | the m68k trampoline code attempted to get around this by either | |
584 | using an out-of-line transfer function or pc-relative data, but | |
585 | the fact remains that the code to jump to the transfer function | |
586 | or the code to load the pc-relative data needs to be flushed | |
859711c5 | 587 | just as much as the "variable" portion of the trampoline. |
27a55d6b | 588 | Recognizing that a cache flush is going to be required anyway, |
859711c5 | 589 | dispense with such notions and build a smaller trampoline. |
27a55d6b | 590 | |
859711c5 | 591 | Since more instructions are required to move a template into |
27a55d6b | 592 | place than to create it on the spot, don't use a template. */ |
3d339ad2 | 593 | |
27a55d6b | 594 | #define TRAMPOLINE_SIZE 12 |
27a55d6b | 595 | #define TRAMPOLINE_ALIGNMENT 16 |
3d339ad2 | 596 | |
27a55d6b RK |
597 | /* Targets redefine this to invoke code to either flush the cache, |
598 | or enable stack execution (or both). */ | |
27a55d6b RK |
599 | #ifndef FINALIZE_TRAMPOLINE |
600 | #define FINALIZE_TRAMPOLINE(TRAMP) | |
601 | #endif | |
3d339ad2 | 602 | |
859711c5 | 603 | /* We generate a two-instructions program at address TRAMP : |
c85f7c16 | 604 | movea.l &CXT,%a0 |
859711c5 | 605 | jmp FNADDR */ |
3d339ad2 RS |
606 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
607 | { \ | |
835b4008 NS |
608 | emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \ |
609 | GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \ | |
1d8eaa6b AS |
610 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ |
611 | emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ | |
27a55d6b | 612 | GEN_INT(0x4EF9)); \ |
1d8eaa6b | 613 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ |
27a55d6b | 614 | FINALIZE_TRAMPOLINE(TRAMP); \ |
3d339ad2 RS |
615 | } |
616 | ||
859711c5 BI |
617 | /* This is the library routine that is used to transfer control from the |
618 | trampoline to the actual nested function. It is defined for backward | |
619 | compatibility, for linking with object code that used the old trampoline | |
620 | definition. | |
3d339ad2 | 621 | |
859711c5 BI |
622 | A colon is used with no explicit operands to cause the template string |
623 | to be scanned for %-constructs. | |
624 | ||
625 | The function name __transfer_from_trampoline is not actually used. | |
3d339ad2 RS |
626 | The function definition just permits use of "asm with operands" |
627 | (though the operand list is empty). */ | |
628 | #define TRANSFER_FROM_TRAMPOLINE \ | |
629 | void \ | |
630 | __transfer_from_trampoline () \ | |
631 | { \ | |
835b4008 | 632 | register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \ |
016c8440 | 633 | asm (GLOBAL_ASM_OP "___trampoline"); \ |
3d339ad2 | 634 | asm ("___trampoline:"); \ |
338818c7 RK |
635 | asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ |
636 | asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ | |
3d339ad2 RS |
637 | asm ("rts":); \ |
638 | } | |
639 | \f | |
859711c5 | 640 | /* There are two registers that can always be eliminated on the m68k. |
860c4900 BI |
641 | The frame pointer and the arg pointer can be replaced by either the |
642 | hard frame pointer or to the stack pointer, depending upon the | |
643 | circumstances. The hard frame pointer is not used before reload and | |
644 | so it is not eligible for elimination. */ | |
860c4900 BI |
645 | #define ELIMINABLE_REGS \ |
646 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
859711c5 | 647 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ |
860c4900 BI |
648 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} |
649 | ||
860c4900 BI |
650 | #define CAN_ELIMINATE(FROM, TO) \ |
651 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
652 | ||
860c4900 BI |
653 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
654 | (OFFSET) = m68k_initial_elimination_offset(FROM, TO) | |
655 | \f | |
3d339ad2 RS |
656 | /* Addressing modes, and classification of registers for them. */ |
657 | ||
940da324 | 658 | #define HAVE_POST_INCREMENT 1 |
940da324 | 659 | #define HAVE_PRE_DECREMENT 1 |
3d339ad2 RS |
660 | |
661 | /* Macros to check register numbers against specific register classes. */ | |
662 | ||
36e04090 | 663 | /* True for data registers, D0 through D7. */ |
bf32249e | 664 | #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7) |
36e04090 KH |
665 | |
666 | /* True for address registers, A0 through A7. */ | |
bf32249e | 667 | #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15) |
36e04090 KH |
668 | |
669 | /* True for integer registers, D0 through D7 and A0 through A7. */ | |
bf32249e | 670 | #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15) |
36e04090 KH |
671 | |
672 | /* True for floating point registers, FP0 through FP7. */ | |
bf32249e | 673 | #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23) |
36e04090 KH |
674 | |
675 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
676 | (INT_REGNO_P (REGNO) \ | |
677 | || INT_REGNO_P (reg_renumber[REGNO])) | |
678 | ||
679 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
680 | (ADDRESS_REGNO_P (REGNO) \ | |
681 | || ADDRESS_REGNO_P (reg_renumber[REGNO])) | |
682 | ||
bf32249e RZ |
683 | #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ |
684 | (INT_REGNO_P (REGNO) \ | |
685 | || REGNO == ARG_POINTER_REGNUM \ | |
686 | || REGNO >= FIRST_PSEUDO_REGISTER) | |
36e04090 | 687 | |
bf32249e RZ |
688 | #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ |
689 | (ADDRESS_REGNO_P (REGNO) \ | |
690 | || REGNO == ARG_POINTER_REGNUM \ | |
691 | || REGNO >= FIRST_PSEUDO_REGISTER) | |
3d339ad2 RS |
692 | |
693 | /* Now macros that check whether X is a register and also, | |
694 | strictly, whether it is in a specified class. | |
695 | ||
859711c5 | 696 | These macros are specific to the m68k, and may be used only |
3d339ad2 RS |
697 | in code for printing assembler insns and in conditions for |
698 | define_optimization. */ | |
699 | ||
700 | /* 1 if X is a data register. */ | |
bf32249e | 701 | #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X))) |
3d339ad2 RS |
702 | |
703 | /* 1 if X is an fp register. */ | |
bf32249e | 704 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
3d339ad2 RS |
705 | |
706 | /* 1 if X is an address register */ | |
bf32249e | 707 | #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X))) |
3d339ad2 | 708 | \f |
7ffb5e78 RS |
709 | /* True if SYMBOL + OFFSET constants must refer to something within |
710 | SYMBOL's section. */ | |
711 | #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P | |
712 | #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
713 | #endif | |
3d339ad2 RS |
714 | |
715 | #define MAX_REGS_PER_ADDRESS 2 | |
716 | ||
7ffb5e78 RS |
717 | #define CONSTANT_ADDRESS_P(X) \ |
718 | ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
719 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
720 | || GET_CODE (X) == HIGH) \ | |
721 | && LEGITIMATE_CONSTANT_P (X)) | |
3d339ad2 RS |
722 | |
723 | /* Nonzero if the constant value X is a legitimate general operand. | |
724 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
7ffb5e78 RS |
725 | #define LEGITIMATE_CONSTANT_P(X) \ |
726 | (GET_MODE (X) != XFmode \ | |
727 | && !m68k_illegitimate_symbolic_constant_p (X)) | |
3d339ad2 | 728 | |
2c8ec431 | 729 | #ifndef REG_OK_STRICT |
fc2241eb | 730 | #define REG_STRICT_P 0 |
2c8ec431 | 731 | #else |
fc2241eb | 732 | #define REG_STRICT_P 1 |
2c8ec431 | 733 | #endif |
3d339ad2 | 734 | |
fc2241eb RS |
735 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
736 | (!symbolic_operand (X, VOIDmode) \ | |
737 | || (TARGET_PCREL && REG_STRICT_P)) | |
3d339ad2 | 738 | |
36e04090 | 739 | #define REG_OK_FOR_BASE_P(X) \ |
fc2241eb | 740 | m68k_legitimate_base_reg_p (X, REG_STRICT_P) |
3d339ad2 | 741 | |
fc2241eb RS |
742 | #define REG_OK_FOR_INDEX_P(X) \ |
743 | m68k_legitimate_index_reg_p (X, REG_STRICT_P) | |
3d339ad2 | 744 | |
04e61bd4 | 745 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
fc2241eb | 746 | do \ |
dcc21c4c | 747 | { \ |
fc2241eb RS |
748 | if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P)) \ |
749 | goto ADDR; \ | |
dcc21c4c | 750 | } \ |
fc2241eb | 751 | while (0) |
04e61bd4 RS |
752 | |
753 | /* Don't call memory_address_noforce for the address to fetch | |
fc2241eb | 754 | the switch offset. This address is ok as it stands, |
04e61bd4 RS |
755 | but memory_address_noforce would alter it. */ |
756 | #define PIC_CASE_VECTOR_ADDRESS(index) index | |
3d339ad2 | 757 | \f |
859711c5 | 758 | /* For the 68000, we handle X+REG by loading X into a register R and |
3d339ad2 RS |
759 | using R+REG. R will go in an address reg and indexing will be used. |
760 | However, if REG is a broken-out memory address or multiplication, | |
761 | nothing needs to be done because REG can certainly go in an address reg. */ | |
3d339ad2 RS |
762 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } |
763 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
764 | { register int ch = (X) != (OLDX); \ | |
765 | if (GET_CODE (X) == PLUS) \ | |
766 | { int copied = 0; \ | |
767 | if (GET_CODE (XEXP (X, 0)) == MULT) \ | |
768 | { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ | |
769 | if (GET_CODE (XEXP (X, 1)) == MULT) \ | |
770 | { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ | |
771 | if (ch && GET_CODE (XEXP (X, 1)) == REG \ | |
772 | && GET_CODE (XEXP (X, 0)) == REG) \ | |
bb5bdf70 JB |
773 | { if (TARGET_COLDFIRE_FPU \ |
774 | && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ | |
dcc21c4c PB |
775 | { COPY_ONCE (X); X = force_operand (X, 0);} \ |
776 | goto WIN; } \ | |
3d339ad2 RS |
777 | if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ |
778 | if (GET_CODE (XEXP (X, 0)) == REG \ | |
779 | || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ | |
780 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
781 | && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ | |
782 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
783 | register rtx val = force_operand (XEXP (X, 1), 0); \ | |
784 | emit_move_insn (temp, val); \ | |
785 | COPY_ONCE (X); \ | |
786 | XEXP (X, 1) = temp; \ | |
dcc21c4c PB |
787 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
788 | && GET_CODE (XEXP (X, 0)) == REG) \ | |
789 | X = force_operand (X, 0); \ | |
3d339ad2 RS |
790 | goto WIN; } \ |
791 | else if (GET_CODE (XEXP (X, 1)) == REG \ | |
792 | || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ | |
793 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ | |
794 | && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ | |
795 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
796 | register rtx val = force_operand (XEXP (X, 0), 0); \ | |
797 | emit_move_insn (temp, val); \ | |
798 | COPY_ONCE (X); \ | |
799 | XEXP (X, 0) = temp; \ | |
dcc21c4c PB |
800 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
801 | && GET_CODE (XEXP (X, 1)) == REG) \ | |
802 | X = force_operand (X, 0); \ | |
3d339ad2 RS |
803 | goto WIN; }}} |
804 | ||
859711c5 | 805 | /* On the 68000, only predecrement and postincrement address depend thus |
b9a76028 MS |
806 | (the amount of decrement or increment being the length of the operand). |
807 | These are now treated generically in recog.c. */ | |
808 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
3d339ad2 | 809 | \f |
3d339ad2 | 810 | #define CASE_VECTOR_MODE HImode |
18543a22 | 811 | #define CASE_VECTOR_PC_RELATIVE 1 |
3d339ad2 | 812 | |
3d339ad2 | 813 | #define DEFAULT_SIGNED_CHAR 1 |
3d339ad2 | 814 | #define MOVE_MAX 4 |
3d339ad2 RS |
815 | #define SLOW_BYTE_ACCESS 0 |
816 | ||
3d339ad2 RS |
817 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
818 | ||
7a6525d6 SL |
819 | /* The ColdFire FF1 instruction returns 32 for zero. */ |
820 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
821 | ||
37941398 | 822 | #define STORE_FLAG_VALUE (-1) |
3d339ad2 | 823 | |
3d339ad2 | 824 | #define Pmode SImode |
3d339ad2 RS |
825 | #define FUNCTION_MODE QImode |
826 | ||
3d339ad2 RS |
827 | \f |
828 | /* Tell final.c how to eliminate redundant test instructions. */ | |
829 | ||
830 | /* Here we define machine-dependent flags and fields in cc_status | |
831 | (see `conditions.h'). */ | |
832 | ||
833 | /* Set if the cc value is actually in the 68881, so a floating point | |
834 | conditional branch must be output. */ | |
835 | #define CC_IN_68881 04000 | |
836 | ||
3d339ad2 RS |
837 | /* On the 68000, all the insns to store in an address register fail to |
838 | set the cc's. However, in some cases these instructions can make it | |
839 | possibly invalid to use the saved cc's. In those cases we clear out | |
840 | some or all of the saved cc's so they won't be used. */ | |
3d339ad2 RS |
841 | #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) |
842 | ||
843 | #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ | |
f082d7a9 | 844 | do { if (cc_prev_status.flags & CC_IN_68881) \ |
3d339ad2 RS |
845 | return FLOAT; \ |
846 | if (cc_prev_status.flags & CC_NO_OVERFLOW) \ | |
847 | return NO_OV; \ | |
f082d7a9 | 848 | return NORMAL; } while (0) |
3d339ad2 RS |
849 | \f |
850 | /* Control the assembler format that we output. */ | |
851 | ||
3d339ad2 | 852 | #define ASM_APP_ON "#APP\n" |
3d339ad2 | 853 | #define ASM_APP_OFF "#NO_APP\n" |
6e7b07a7 | 854 | #define TEXT_SECTION_ASM_OP "\t.text" |
6e7b07a7 | 855 | #define DATA_SECTION_ASM_OP "\t.data" |
2cff4a6e | 856 | #define GLOBAL_ASM_OP "\t.globl\t" |
3d339ad2 | 857 | #define REGISTER_PREFIX "" |
3d339ad2 | 858 | #define LOCAL_LABEL_PREFIX "" |
3d339ad2 | 859 | #define USER_LABEL_PREFIX "_" |
3d339ad2 RS |
860 | #define IMMEDIATE_PREFIX "#" |
861 | ||
3d339ad2 | 862 | #define REGISTER_NAMES \ |
cfe084c8 BI |
863 | {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \ |
864 | REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \ | |
865 | REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \ | |
866 | REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \ | |
867 | REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \ | |
868 | REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \ | |
869 | REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \ | |
870 | REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \ | |
871 | REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" } | |
872 | ||
873 | #define M68K_FP_REG_NAME REGISTER_PREFIX"fp" | |
874 | ||
875 | /* Return a register name by index, handling %fp nicely. | |
876 | We don't replace %fp for targets that don't map it to %a6 | |
877 | since it may confuse GAS. */ | |
878 | #define M68K_REGNAME(r) ( \ | |
de41203b | 879 | ((FRAME_POINTER_REGNUM == A6_REG) \ |
cfe084c8 BI |
880 | && ((r) == FRAME_POINTER_REGNUM) \ |
881 | && frame_pointer_needed) ? \ | |
882 | M68K_FP_REG_NAME : reg_names[(r)]) | |
3d339ad2 | 883 | |
859711c5 | 884 | /* On the Sun-3, the floating point registers have numbers |
3d339ad2 | 885 | 18 to 25, not 16 to 23 as they do in the compiler. */ |
3d339ad2 RS |
886 | #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) |
887 | ||
078e983e AS |
888 | /* Before the prologue, RA is at 0(%sp). */ |
889 | #define INCOMING_RETURN_ADDR_RTX \ | |
1d8eaa6b | 890 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
078e983e | 891 | |
42b67c06 PB |
892 | /* After the prologue, RA is at 4(AP) in the current frame. */ |
893 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
894 | ((COUNT) == 0 \ | |
895 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \ | |
896 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
897 | ||
078e983e AS |
898 | /* We must not use the DBX register numbers for the DWARF 2 CFA column |
899 | numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
900 | Instead use the identity mapping. */ | |
5cd0f915 RS |
901 | #define DWARF_FRAME_REGNUM(REG) \ |
902 | (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM) | |
903 | ||
904 | /* The return column was originally 24, but gcc used 25 for a while too. | |
905 | Define both registers 24 and 25 as Pmode ones and use 24 in our own | |
906 | unwind information. */ | |
907 | #define DWARF_FRAME_REGISTERS 25 | |
908 | #define DWARF_FRAME_RETURN_COLUMN 24 | |
909 | #define DWARF_ALT_FRAME_RETURN_COLUMN 25 | |
078e983e AS |
910 | |
911 | /* Before the prologue, the top of the frame is at 4(%sp). */ | |
912 | #define INCOMING_FRAME_SP_OFFSET 4 | |
913 | ||
a40ed0f3 | 914 | /* All registers are live on exit from an interrupt routine. */ |
a4242737 KH |
915 | #define EPILOGUE_USES(REGNO) \ |
916 | (reload_completed \ | |
917 | && (m68k_get_function_kind (current_function_decl) \ | |
918 | == m68k_fk_interrupt_handler)) | |
a40ed0f3 | 919 | |
2cff4a6e AS |
920 | /* Describe how we implement __builtin_eh_return. */ |
921 | #define EH_RETURN_DATA_REGNO(N) \ | |
922 | ((N) < 2 ? (N) : INVALID_REGNUM) | |
36e04090 | 923 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) |
2cff4a6e AS |
924 | #define EH_RETURN_HANDLER_RTX \ |
925 | gen_rtx_MEM (Pmode, \ | |
926 | gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ | |
927 | plus_constant (EH_RETURN_STACKADJ_RTX, \ | |
928 | UNITS_PER_WORD))) | |
929 | ||
930 | /* Select a format to encode pointers in exception handling data. CODE | |
931 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
abe92a04 RS |
932 | true if the symbol may be affected by dynamic relocations. |
933 | ||
934 | TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support | |
935 | a read-only text segment without imposing a fixed gap between the | |
936 | text and data segments. As a result, the text segment cannot refer | |
937 | to anything in the data segment, even in PC-relative form. Because | |
938 | .eh_frame refers to both code and data, it follows that .eh_frame | |
939 | must be in the data segment itself, and that the offset between | |
940 | .eh_frame and code will not be a link-time constant. | |
941 | ||
942 | In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel | |
943 | | DW_EH_PE_indirect for all code references. However, gcc currently | |
944 | handles indirect references using a per-TU constant pool. This means | |
945 | that if a function and its eh_frame are removed by the linker, the | |
946 | eh_frame's indirect references to the removed function will not be | |
947 | removed, leading to an unresolved symbol error. | |
948 | ||
949 | It isn't clear that any -msep-data or -mid-shared-library target | |
950 | would benefit from a read-only .eh_frame anyway. In particular, | |
951 | no known target that supports these options has a feature like | |
952 | PT_GNU_RELRO. Without any such feature to motivate them, indirect | |
953 | references would be unnecessary bloat, so we simply use an absolute | |
954 | pointer for code and global references. We still use pc-relative | |
955 | references to data, as this avoids a relocation. */ | |
859711c5 | 956 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
2cff4a6e | 957 | (flag_pic \ |
abe92a04 RS |
958 | && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ |
959 | && ((GLOBAL) || (CODE))) \ | |
2cff4a6e AS |
960 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ |
961 | : DW_EH_PE_absptr) | |
3d339ad2 | 962 | |
3d339ad2 | 963 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ |
1f85a612 | 964 | asm_fprintf (FILE, "%U%s", NAME) |
3d339ad2 | 965 | |
3d339ad2 | 966 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
e59f7d3d | 967 | sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) |
3d339ad2 | 968 | |
ba5f7c88 RS |
969 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ |
970 | asm_fprintf (FILE, (MOTOROLA \ | |
971 | ? "\tmove.l %s,-(%Rsp)\n" \ | |
972 | : "\tmovel %s,%Rsp@-\n"), \ | |
973 | reg_names[REGNO]) | |
974 | ||
975 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
976 | asm_fprintf (FILE, (MOTOROLA \ | |
977 | ? "\tmove.l (%Rsp)+,%s\n" \ | |
978 | : "\tmovel %Rsp@+,%s\n"), \ | |
979 | reg_names[REGNO]) | |
3d339ad2 | 980 | |
859711c5 BI |
981 | /* The m68k does not use absolute case-vectors, but we must define this macro |
982 | anyway. */ | |
3d339ad2 RS |
983 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
984 | asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) | |
985 | ||
33f7f353 | 986 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3d339ad2 RS |
987 | asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) |
988 | ||
b4ac57ab RS |
989 | /* We don't have a way to align to more than a two-byte boundary, so do the |
990 | best we can and don't complain. */ | |
3d339ad2 | 991 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
b4ac57ab RS |
992 | if ((LOG) >= 1) \ |
993 | fprintf (FILE, "\t.even\n"); | |
3d339ad2 RS |
994 | |
995 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 996 | fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) |
3d339ad2 | 997 | |
3d339ad2 RS |
998 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
999 | ( fputs (".comm ", (FILE)), \ | |
1000 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1001 | fprintf ((FILE), ",%u\n", (int)(ROUNDED))) |
3d339ad2 | 1002 | |
3d339ad2 RS |
1003 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ |
1004 | ( fputs (".lcomm ", (FILE)), \ | |
1005 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1006 | fprintf ((FILE), ",%u\n", (int)(ROUNDED))) |
3d339ad2 | 1007 | |
3d339ad2 | 1008 | /* Output a float value (represented as a C double) as an immediate operand. |
859711c5 | 1009 | This macro is m68k-specific. */ |
f6ba6a91 RS |
1010 | #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ |
1011 | do { \ | |
1012 | if (CODE == 'f') \ | |
1013 | { \ | |
1014 | char dstr[30]; \ | |
859711c5 | 1015 | real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ |
f6ba6a91 RS |
1016 | asm_fprintf ((FILE), "%I0r%s", dstr); \ |
1017 | } \ | |
1018 | else \ | |
1019 | { \ | |
1020 | long l; \ | |
1021 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
97b57a81 | 1022 | asm_fprintf ((FILE), "%I0x%lx", l); \ |
f6ba6a91 RS |
1023 | } \ |
1024 | } while (0) | |
3d339ad2 RS |
1025 | |
1026 | /* Output a double value (represented as a C double) as an immediate operand. | |
859711c5 | 1027 | This macro is m68k-specific. */ |
3d339ad2 | 1028 | #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ |
f6ba6a91 | 1029 | do { char dstr[30]; \ |
da6eec72 | 1030 | real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ |
f6ba6a91 RS |
1031 | asm_fprintf (FILE, "%I0r%s", dstr); \ |
1032 | } while (0) | |
1033 | ||
1034 | /* Note, long double immediate operands are not actually | |
1035 | generated by m68k.md. */ | |
1036 | #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ | |
1037 | do { char dstr[30]; \ | |
da6eec72 | 1038 | real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ |
f6ba6a91 RS |
1039 | asm_fprintf (FILE, "%I0r%s", dstr); \ |
1040 | } while (0) | |
3d339ad2 | 1041 | |
859711c5 | 1042 | /* On the 68000, we use several CODE characters: |
3d339ad2 RS |
1043 | '.' for dot needed in Motorola-style opcode names. |
1044 | '-' for an operand pushing on the stack: | |
1045 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
1046 | '+' for an operand pushing on the stack: | |
1047 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
1048 | '@' for a reference to the top word on the stack: | |
1049 | sp@, (sp) or (%sp) depending on the style of syntax. | |
ac5f9961 BI |
1050 | '#' for an immediate operand prefix (# in MIT and Motorola syntax |
1051 | but & in SGS syntax). | |
7c129456 | 1052 | '!' for the fpcr register (used in some float-to-fixed conversions). |
3d339ad2 RS |
1053 | '$' for the letter `s' in an op code, but only on the 68040. |
1054 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 1055 | '/' for register prefix needed by longlong.h. |
a40ed0f3 | 1056 | '?' for m68k_library_id_string |
3d339ad2 RS |
1057 | |
1058 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
1059 | 'd' to force memory addressing to be absolute, not relative. | |
1060 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
3d339ad2 | 1061 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
1a8965c4 | 1062 | or print pair of registers as rx:ry. */ |
3d339ad2 RS |
1063 | |
1064 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
ac5f9961 BI |
1065 | ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ |
1066 | || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ | |
a40ed0f3 | 1067 | || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?') |
3d339ad2 | 1068 | |
3d339ad2 | 1069 | |
859711c5 | 1070 | /* See m68k.c for the m68k specific codes. */ |
3d339ad2 RS |
1071 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
1072 | ||
3d339ad2 RS |
1073 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
1074 | ||
900ec02d JB |
1075 | /* Values used in the MICROARCH argument to M68K_DEVICE. */ |
1076 | enum uarch_type | |
1077 | { | |
1078 | u68000, | |
1079 | u68010, | |
1080 | u68020, | |
1081 | u68020_40, | |
1082 | u68020_60, | |
1083 | u68030, | |
1084 | u68040, | |
1085 | u68060, | |
1086 | ucpu32, | |
1087 | ucfv2, | |
1088 | ucfv3, | |
1089 | ucfv4, | |
1090 | ucfv4e, | |
1091 | ucfv5, | |
1092 | unk_arch | |
1093 | }; | |
1094 | ||
1095 | /* An enumeration of all supported target devices. */ | |
1096 | enum target_device | |
1097 | { | |
1098 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
1099 | ENUM_VALUE, | |
1100 | #include "m68k-devices.def" | |
1101 | #undef M68K_DEVICE | |
1102 | unk_device | |
1103 | }; | |
1104 | ||
1105 | enum fpu_type | |
1106 | { | |
1107 | FPUTYPE_NONE, | |
1108 | FPUTYPE_68881, | |
1109 | FPUTYPE_COLDFIRE | |
1110 | }; | |
1111 | ||
a4242737 KH |
1112 | enum m68k_function_kind |
1113 | { | |
1114 | m68k_fk_normal_function, | |
1115 | m68k_fk_interrupt_handler, | |
1116 | m68k_fk_interrupt_thread | |
1117 | }; | |
1118 | ||
900ec02d | 1119 | /* Variables in m68k.c; see there for details. */ |
a2ef3db7 | 1120 | extern const char *m68k_library_id_string; |
2b3600ac | 1121 | extern int m68k_last_compare_had_fp_operands; |
900ec02d JB |
1122 | extern enum target_device m68k_cpu; |
1123 | extern enum uarch_type m68k_tune; | |
1124 | extern enum fpu_type m68k_fpu; | |
1125 | extern unsigned int m68k_cpu_flags; | |
29ca003a RS |
1126 | extern const char *m68k_symbolic_call; |
1127 | extern const char *m68k_symbolic_jump; |