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01bbf777 | 1 | /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. |
cf011243 | 2 | Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
8636be86 | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
25a1b918 | 4 | |
7ec022b2 | 5 | This file is part of GCC. |
3d339ad2 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
3d339ad2 RS |
8 | it under the terms of the GNU General Public License as published by |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
3d339ad2 RS |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 18 | along with GCC; see the file COPYING. If not, write to |
0e29e3c9 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
3d339ad2 | 21 | |
f082d7a9 GN |
22 | /* We need to have MOTOROLA always defined (either 0 or 1) because we use |
23 | if-statements and ?: on it. This way we have compile-time error checking | |
24 | for both the MOTOROLA and MIT code paths. We do rely on the host compiler | |
25 | to optimize away all constant tests. */ | |
26 | #ifdef MOTOROLA | |
27 | # undef MOTOROLA | |
28 | # define MOTOROLA 1 /* Use the Motorola assembly syntax. */ | |
29 | # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") | |
30 | #else | |
31 | # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") | |
32 | # define MOTOROLA 0 /* Use the MIT assembly syntax. */ | |
33 | #endif | |
3d339ad2 RS |
34 | |
35 | /* Note that some other tm.h files include this one and then override | |
36 | many of the definitions that relate to assembler syntax. */ | |
37 | ||
a7fbe404 NB |
38 | #define TARGET_CPU_CPP_BUILTINS() \ |
39 | do \ | |
40 | { \ | |
0988b758 BI |
41 | builtin_define ("__m68k__"); \ |
42 | builtin_define_std ("mc68000"); \ | |
43 | if (TARGET_68040_ONLY) \ | |
44 | { \ | |
45 | if (TARGET_68060) \ | |
46 | builtin_define_std ("mc68060"); \ | |
47 | else \ | |
48 | builtin_define_std ("mc68040"); \ | |
49 | } \ | |
50 | else if (TARGET_68060) /* -m68020-60 */ \ | |
51 | { \ | |
e2ffd796 | 52 | builtin_define_std ("mc68060"); \ |
e2ffd796 | 53 | builtin_define_std ("mc68040"); \ |
0988b758 BI |
54 | builtin_define_std ("mc68030"); \ |
55 | builtin_define_std ("mc68020"); \ | |
56 | } \ | |
57 | else if (TARGET_68040) /* -m68020-40 */ \ | |
58 | { \ | |
59 | builtin_define_std ("mc68040"); \ | |
60 | builtin_define_std ("mc68030"); \ | |
859711c5 | 61 | builtin_define_std ("mc68020"); \ |
0988b758 BI |
62 | } \ |
63 | else if (TARGET_68030) \ | |
64 | builtin_define_std ("mc68030"); \ | |
65 | else if (TARGET_68020) \ | |
66 | builtin_define_std ("mc68020"); \ | |
67 | if (TARGET_68881) \ | |
68 | builtin_define ("__HAVE_68881__"); \ | |
69 | if (TARGET_CPU32) \ | |
70 | { \ | |
71 | builtin_define_std ("mc68332"); \ | |
72 | builtin_define_std ("mcpu32"); \ | |
73 | } \ | |
74 | if (TARGET_COLDFIRE) \ | |
75 | builtin_define ("__mcoldfire__"); \ | |
76 | if (TARGET_5200) \ | |
77 | builtin_define ("__mcf5200__"); \ | |
78 | if (TARGET_528x) \ | |
79 | { \ | |
80 | builtin_define ("__mcf528x__"); \ | |
e2ffd796 | 81 | builtin_define ("__mcf5200__"); \ |
0988b758 BI |
82 | } \ |
83 | if (TARGET_CFV3) \ | |
84 | { \ | |
85 | builtin_define ("__mcf5300__"); \ | |
86 | builtin_define ("__mcf5307__"); \ | |
87 | } \ | |
88 | if (TARGET_CFV4) \ | |
89 | { \ | |
90 | builtin_define ("__mcf5400__"); \ | |
91 | builtin_define ("__mcf5407__"); \ | |
92 | } \ | |
93 | if (TARGET_CF_HWDIV) \ | |
94 | builtin_define ("__mcfhwdiv__"); \ | |
95 | if (flag_pic) \ | |
a2ef3db7 BI |
96 | { \ |
97 | builtin_define ("__pic__"); \ | |
98 | if (flag_pic > 1) \ | |
99 | builtin_define ("__PIC__"); \ | |
100 | } \ | |
0988b758 BI |
101 | builtin_assert ("cpu=m68k"); \ |
102 | builtin_assert ("machine=m68k"); \ | |
a7fbe404 NB |
103 | } \ |
104 | while (0) | |
105 | ||
301d03af RS |
106 | /* Classify the groups of pseudo-ops used to assemble QI, HI and SI |
107 | quantities. */ | |
108 | #define INT_OP_STANDARD 0 /* .byte, .short, .long */ | |
109 | #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ | |
110 | #define INT_OP_NO_DOT 2 /* byte, short, long */ | |
111 | #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ | |
112 | ||
859711c5 | 113 | /* Set the default. */ |
301d03af RS |
114 | #define INT_OP_GROUP INT_OP_DOT_WORD |
115 | ||
3d339ad2 RS |
116 | /* Run-time compilation parameters selecting different hardware subsets. */ |
117 | ||
118 | extern int target_flags; | |
119 | ||
120 | /* Macros used in the machine description to test the flags. */ | |
121 | ||
122 | /* Compile for a 68020 (not a 68000 or 68010). */ | |
0988b758 | 123 | #define MASK_68020 (1<<0) |
7a1b98a9 | 124 | #define TARGET_68020 (target_flags & MASK_68020) |
3d339ad2 | 125 | |
0988b758 BI |
126 | /* Compile for a 68030. This does not really make a difference in GCC, |
127 | it just enables the __mc68030__ predefine. */ | |
128 | #define MASK_68030 (1<<1) | |
129 | #define TARGET_68030 (target_flags & MASK_68030) | |
3d339ad2 | 130 | |
b4281273 RS |
131 | /* Optimize for 68040, but still allow execution on 68020 |
132 | (-m68020-40 or -m68040). | |
b4ac57ab | 133 | The 68040 will execute all 68030 and 68881/2 instructions, but some |
3d339ad2 RS |
134 | of them must be emulated in software by the OS. When TARGET_68040 is |
135 | turned on, these instructions won't be used. This code will still | |
7a1929e1 | 136 | run on a 68030 and 68881/2. */ |
859711c5 | 137 | #define MASK_68040 (1<<2) |
7a1b98a9 | 138 | #define TARGET_68040 (target_flags & MASK_68040) |
3d339ad2 | 139 | |
30e6bc63 | 140 | /* Use the 68040-only fp instructions (-m68040 or -m68060). */ |
0988b758 | 141 | #define MASK_68040_ONLY (1<<3) |
7a1b98a9 | 142 | #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) |
3d339ad2 | 143 | |
30e6bc63 | 144 | /* Optimize for 68060, but still allow execution on 68020 |
35bcca7b | 145 | (-m68020-60 or -m68060). |
30e6bc63 RK |
146 | The 68060 will execute all 68030 and 68881/2 instructions, but some |
147 | of them must be emulated in software by the OS. When TARGET_68060 is | |
148 | turned on, these instructions won't be used. This code will still | |
7a1929e1 | 149 | run on a 68030 and 68881/2. */ |
0988b758 | 150 | #define MASK_68060 (1<<4) |
7a1b98a9 | 151 | #define TARGET_68060 (target_flags & MASK_68060) |
30e6bc63 | 152 | |
106bee4b | 153 | /* Compile for mcf5200 */ |
0988b758 | 154 | #define MASK_5200 (1<<5) |
106bee4b RK |
155 | #define TARGET_5200 (target_flags & MASK_5200) |
156 | ||
0988b758 BI |
157 | /* Build for ColdFire v3 */ |
158 | #define MASK_CFV3 (1<<6) | |
159 | #define TARGET_CFV3 (target_flags & MASK_CFV3) | |
160 | ||
161 | /* Build for ColdFire v4 */ | |
162 | #define MASK_CFV4 (1<<7) | |
163 | #define TARGET_CFV4 (target_flags & MASK_CFV4) | |
164 | ||
165 | /* Compile for ColdFire 528x */ | |
166 | #define MASK_528x (1<<8) | |
167 | #define TARGET_528x (target_flags & MASK_528x) | |
168 | ||
169 | /* Divide support for ColdFire */ | |
170 | #define MASK_CF_HWDIV (1<<9) | |
171 | #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV) | |
172 | ||
173 | /* Compile 68881 insns for floating point (not library calls). */ | |
174 | #define MASK_68881 (1<<10) | |
175 | #define TARGET_68881 (target_flags & MASK_68881) | |
176 | ||
177 | /* Compile using 68020 bit-field insns. */ | |
178 | #define MASK_BITFIELD (1<<11) | |
179 | #define TARGET_BITFIELD (target_flags & MASK_BITFIELD) | |
180 | ||
181 | /* Compile with 16-bit `int'. */ | |
182 | #define MASK_SHORT (1<<12) | |
183 | #define TARGET_SHORT (target_flags & MASK_SHORT) | |
184 | ||
225d221a | 185 | /* Align ints to a word boundary. This breaks compatibility with the |
dcd13066 | 186 | published ABI's for structures containing ints, but produces faster |
c16eadc7 KH |
187 | code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire). |
188 | It's required for ColdFire cpus without a misalignment module. */ | |
0988b758 | 189 | #define MASK_ALIGN_INT (1<<13) |
dcd13066 RK |
190 | #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) |
191 | ||
2c8ec431 DL |
192 | /* Use PC-relative addressing modes (without using a global offset table). |
193 | The m68000 supports 16-bit PC-relative addressing. | |
194 | The m68020 supports 32-bit PC-relative addressing | |
195 | (using outer displacements). | |
196 | ||
197 | Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are | |
198 | treated as all containing an implicit PC-relative component, and hence | |
199 | cannot be used directly as addresses for memory writes. See the comments | |
200 | in m68k.c for more information. */ | |
0988b758 | 201 | #define MASK_PCREL (1<<14) |
2c8ec431 DL |
202 | #define TARGET_PCREL (target_flags & MASK_PCREL) |
203 | ||
7a1929e1 | 204 | /* Relax strict alignment. */ |
0988b758 | 205 | #define MASK_NO_STRICT_ALIGNMENT (1<<15) |
b71733d5 GM |
206 | #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) |
207 | ||
6b475ad5 BI |
208 | /* Compile using rtd insn calling sequence. |
209 | This will not work unless you use prototypes at least | |
210 | for all functions that can take varying numbers of args. */ | |
211 | #define MASK_RTD (1<<16) | |
212 | #define TARGET_RTD (target_flags & MASK_RTD) | |
9425fb04 | 213 | |
839a4992 | 214 | /* Support A5 relative data separate from text. |
eb0e0173 BI |
215 | * This option implies -fPIC, however it inhibits the generation of the |
216 | * A5 save/restore in functions and the loading of a5 with a got pointer. | |
217 | */ | |
218 | #define MASK_SEP_DATA (1<<17) | |
219 | #define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA) | |
220 | ||
221 | /* Compile using library ID based shared libraries. | |
222 | * Set a specific ID using the -mshared-library-id=xxx option. | |
223 | */ | |
224 | #define MASK_ID_SHARED_LIBRARY (1<<18) | |
225 | #define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY) | |
226 | ||
0988b758 BI |
227 | /* Compile for a CPU32. A 68020 without bitfields is a good |
228 | heuristic for a CPU32. */ | |
229 | #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) | |
9425fb04 | 230 | |
0988b758 | 231 | /* Is the target a ColdFire? */ |
9425fb04 PB |
232 | #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4) |
233 | #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE) | |
234 | ||
c16eadc7 | 235 | /* Which bits can be set by specifying a ColdFire */ |
9425fb04 PB |
236 | #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV) |
237 | ||
f18bff15 | 238 | #define TARGET_SWITCHES \ |
9425fb04 | 239 | { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ |
f18bff15 | 240 | N_("Generate code for a 68020") }, \ |
9425fb04 | 241 | { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ |
f18bff15 RZ |
242 | N_("Generate code for a 68020") }, \ |
243 | { "68020", (MASK_68020|MASK_BITFIELD), "" }, \ | |
244 | { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ | |
9425fb04 | 245 | { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
246 | |MASK_68020|MASK_BITFIELD|MASK_68881), \ |
247 | N_("Generate code for a 68000") }, \ | |
9425fb04 | 248 | { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
249 | |MASK_68020|MASK_BITFIELD|MASK_68881), \ |
250 | N_("Generate code for a 68000") }, \ | |
251 | { "bitfield", MASK_BITFIELD, \ | |
252 | N_("Use the bit-field instructions") }, \ | |
253 | { "nobitfield", - MASK_BITFIELD, \ | |
254 | N_("Do not use the bit-field instructions") }, \ | |
f18bff15 | 255 | { "short", MASK_SHORT, \ |
9e637a26 | 256 | N_("Consider type 'int' to be 16 bits wide") }, \ |
f18bff15 | 257 | { "noshort", - MASK_SHORT, \ |
9e637a26 | 258 | N_("Consider type 'int' to be 32 bits wide") }, \ |
f18bff15 | 259 | { "68881", MASK_68881, "" }, \ |
a7d840c7 | 260 | { "soft-float", - MASK_68881, \ |
f18bff15 | 261 | N_("Generate code with library calls for floating point") }, \ |
0988b758 | 262 | { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \ |
f18bff15 RZ |
263 | N_("Generate code for a 68040, without any new instructions") }, \ |
264 | { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ | |
0988b758 | 265 | { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \ |
f18bff15 | 266 | N_("Generate code for a 68060, without any new instructions") }, \ |
8309458a | 267 | { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ |
f18bff15 | 268 | |MASK_68060), "" }, \ |
9425fb04 | 269 | { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ |
f18bff15 | 270 | N_("Generate code for a 68030") }, \ |
0988b758 | 271 | { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \ |
9425fb04 | 272 | { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \ |
f18bff15 | 273 | N_("Generate code for a 68040") }, \ |
35bcca7b | 274 | { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ |
f18bff15 | 275 | |MASK_68040_ONLY|MASK_68040), "" }, \ |
9425fb04 | 276 | { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \ |
f18bff15 | 277 | N_("Generate code for a 68060") }, \ |
7a1b98a9 | 278 | { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ |
f18bff15 | 279 | |MASK_68040_ONLY|MASK_68060), "" }, \ |
9425fb04 | 280 | { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
f18bff15 RZ |
281 | |MASK_BITFIELD|MASK_68881), \ |
282 | N_("Generate code for a 520X") }, \ | |
283 | { "5200", (MASK_5200), "" }, \ | |
9425fb04 PB |
284 | { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
285 | |MASK_BITFIELD|MASK_68881), \ | |
0988b758 BI |
286 | N_("Generate code for a 5206e") }, \ |
287 | { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \ | |
9425fb04 PB |
288 | { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
289 | |MASK_BITFIELD|MASK_68881), \ | |
290 | N_("Generate code for a 528x") }, \ | |
0988b758 | 291 | { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \ |
9425fb04 PB |
292 | { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
293 | |MASK_BITFIELD|MASK_68881), \ | |
294 | N_("Generate code for a 5307") }, \ | |
0988b758 | 295 | { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \ |
9425fb04 PB |
296 | { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
297 | |MASK_BITFIELD|MASK_68881), \ | |
298 | N_("Generate code for a 5407") }, \ | |
0988b758 | 299 | { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \ |
f18bff15 RZ |
300 | { "68851", 0, \ |
301 | N_("Generate code for a 68851") }, \ | |
302 | { "no-68851", 0, \ | |
303 | N_("Do no generate code for a 68851") }, \ | |
9425fb04 | 304 | { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
305 | |MASK_68020|MASK_BITFIELD|MASK_68881), \ |
306 | N_("Generate code for a 68302") }, \ | |
9425fb04 | 307 | { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
308 | |MASK_BITFIELD|MASK_68881), \ |
309 | N_("Generate code for a 68332") }, \ | |
310 | { "68332", MASK_68020, "" }, \ | |
9425fb04 | 311 | { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
312 | |MASK_BITFIELD|MASK_68881), \ |
313 | N_("Generate code for a cpu32") }, \ | |
314 | { "cpu32", MASK_68020, "" }, \ | |
859711c5 | 315 | { "align-int", MASK_ALIGN_INT, \ |
f18bff15 | 316 | N_("Align variables on a 32-bit boundary") }, \ |
859711c5 | 317 | { "no-align-int", -MASK_ALIGN_INT, \ |
f18bff15 | 318 | N_("Align variables on a 16-bit boundary") }, \ |
a2ef3db7 BI |
319 | { "sep-data", MASK_SEP_DATA, \ |
320 | N_("Enable separate data segment") }, \ | |
321 | { "no-sep-data", -MASK_SEP_DATA, \ | |
322 | N_("Disable separate data segment") }, \ | |
323 | { "id-shared-library", MASK_ID_SHARED_LIBRARY, \ | |
324 | N_("Enable ID based shared library") }, \ | |
325 | { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \ | |
326 | N_("Disable ID based shared library") }, \ | |
f18bff15 RZ |
327 | { "pcrel", MASK_PCREL, \ |
328 | N_("Generate pc-relative code") }, \ | |
329 | { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \ | |
330 | N_("Do not use unaligned memory references") }, \ | |
331 | { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \ | |
332 | N_("Use unaligned memory references") }, \ | |
6b475ad5 BI |
333 | { "rtd", MASK_RTD, \ |
334 | N_("Use different calling convention using 'rtd'") }, \ | |
335 | { "nortd", - MASK_RTD, \ | |
336 | N_("Use normal calling convention") }, \ | |
7a1b98a9 | 337 | SUBTARGET_SWITCHES \ |
f18bff15 | 338 | { "", TARGET_DEFAULT, "" }} |
0988b758 | 339 | /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */ |
882ed710 | 340 | |
9e62c7f2 | 341 | #define TARGET_OPTIONS \ |
225d221a | 342 | { \ |
a2ef3db7 BI |
343 | { "shared-library-id=", &m68k_library_id_string, \ |
344 | N_("ID of shared library to build"), 0}, \ | |
9e62c7f2 RK |
345 | SUBTARGET_OPTIONS \ |
346 | } | |
347 | ||
adf2ac37 | 348 | #define OVERRIDE_OPTIONS override_options() |
84ab3bfb | 349 | |
9e62c7f2 RK |
350 | /* These are meant to be redefined in the host dependent files */ |
351 | #define SUBTARGET_SWITCHES | |
352 | #define SUBTARGET_OPTIONS | |
84ab3bfb | 353 | #define SUBTARGET_OVERRIDE_OPTIONS |
3d339ad2 RS |
354 | \f |
355 | /* target machine storage layout */ | |
356 | ||
968a7562 | 357 | #define LONG_DOUBLE_TYPE_SIZE 80 |
ade83c33 BI |
358 | |
359 | /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp | |
360 | instructions, we get proper intermediate rounding, otherwise we | |
361 | get extended precision results. */ | |
a7d840c7 | 362 | #define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2) |
d57a4b98 | 363 | |
3d339ad2 | 364 | #define BITS_BIG_ENDIAN 1 |
3d339ad2 | 365 | #define BYTES_BIG_ENDIAN 1 |
3d339ad2 RS |
366 | #define WORDS_BIG_ENDIAN 1 |
367 | ||
3d339ad2 RS |
368 | #define UNITS_PER_WORD 4 |
369 | ||
3d339ad2 | 370 | #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) |
3d339ad2 | 371 | #define STACK_BOUNDARY 16 |
225d221a | 372 | #define FUNCTION_BOUNDARY 16 |
3d339ad2 RS |
373 | #define EMPTY_FIELD_BOUNDARY 16 |
374 | ||
859711c5 | 375 | /* No data type wants to be aligned rounder than this. |
dcd13066 | 376 | Most published ABIs say that ints should be aligned on 16 bit |
859711c5 | 377 | boundaries, but CPUs with 32-bit busses get better performance |
c16eadc7 KH |
378 | aligned on 32-bit boundaries. ColdFires without a misalignment |
379 | module require 32-bit alignment. */ | |
dcd13066 | 380 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) |
3d339ad2 | 381 | |
b71733d5 | 382 | #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) |
3d339ad2 | 383 | |
3d339ad2 RS |
384 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) |
385 | ||
86702e31 | 386 | /* Define these to avoid dependence on meaning of `int'. */ |
3d339ad2 RS |
387 | #define WCHAR_TYPE "long int" |
388 | #define WCHAR_TYPE_SIZE 32 | |
859711c5 BI |
389 | |
390 | /* Maximum number of library IDs we permit with -mid-shared-library. */ | |
391 | #define MAX_LIBRARY_ID 255 | |
392 | ||
3d339ad2 RS |
393 | \f |
394 | /* Standard register usage. */ | |
395 | ||
859711c5 BI |
396 | /* For the m68k, we give the data registers numbers 0-7, |
397 | the address registers numbers 010-017 (8-15), | |
398 | and the 68881 floating point registers numbers 020-027 (16-24). | |
399 | We also have a fake `arg-pointer' register 030 (25) used for | |
400 | register elimination. */ | |
860c4900 | 401 | #define FIRST_PSEUDO_REGISTER 25 |
3d339ad2 | 402 | |
859711c5 | 403 | /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ |
5b43fed1 | 404 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM) |
3d339ad2 | 405 | |
3d339ad2 RS |
406 | /* 1 for registers that have pervasive standard uses |
407 | and are not available for the register allocator. | |
859711c5 BI |
408 | On the m68k, only the stack pointer is such. |
409 | Our fake arg-pointer is obviously fixed as well. */ | |
3d339ad2 RS |
410 | #define FIXED_REGISTERS \ |
411 | {/* Data registers. */ \ | |
412 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
413 | \ | |
414 | /* Address registers. */ \ | |
415 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
416 | \ | |
417 | /* Floating point registers \ | |
418 | (if available). */ \ | |
a4e9467d RZ |
419 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
420 | \ | |
421 | /* Arg pointer. */ \ | |
422 | 1 } | |
3d339ad2 RS |
423 | |
424 | /* 1 for registers not available across function calls. | |
425 | These must include the FIXED_REGISTERS and also any | |
426 | registers that can be used without being saved. | |
427 | The latter must include the registers where values are returned | |
428 | and the register where structure-value addresses are passed. | |
429 | Aside from that, you can include as many other registers as you like. */ | |
859711c5 BI |
430 | #define CALL_USED_REGISTERS \ |
431 | {/* Data registers. */ \ | |
432 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
433 | \ | |
434 | /* Address registers. */ \ | |
435 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
436 | \ | |
437 | /* Floating point registers \ | |
438 | (if available). */ \ | |
439 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
440 | \ | |
441 | /* Arg pointer. */ \ | |
442 | 1 } | |
a4e9467d RZ |
443 | |
444 | #define REG_ALLOC_ORDER \ | |
445 | { /* d0/d1/a0/a1 */ \ | |
446 | 0, 1, 8, 9, \ | |
447 | /* d2-d7 */ \ | |
448 | 2, 3, 4, 5, 6, 7, \ | |
449 | /* a2-a7/arg */ \ | |
450 | 10, 11, 12, 13, 14, 15, 24, \ | |
451 | /* fp0-fp7 */ \ | |
452 | 16, 17, 18, 19, 20, 21, 22, 23\ | |
453 | } | |
3d339ad2 | 454 | |
3d339ad2 RS |
455 | |
456 | /* Make sure everything's fine if we *don't* have a given processor. | |
457 | This assumes that putting a register in fixed_regs will keep the | |
458 | compiler's mitts completely off it. We don't bother to zero it out | |
15a17b72 | 459 | of register classes. */ |
5b43fed1 | 460 | #define CONDITIONAL_REGISTER_USAGE \ |
859711c5 BI |
461 | { \ |
462 | int i; \ | |
463 | HARD_REG_SET x; \ | |
5b43fed1 | 464 | if (! TARGET_68881) \ |
859711c5 | 465 | { \ |
5b43fed1 | 466 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ |
859711c5 BI |
467 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
468 | if (TEST_HARD_REG_BIT (x, i)) \ | |
469 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
470 | } \ | |
5b43fed1 RH |
471 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
472 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
473 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
3d339ad2 RS |
474 | } |
475 | ||
859711c5 | 476 | /* On the m68k, ordinary registers hold 32 bits worth; |
3d339ad2 RS |
477 | for the 68881 registers, a single register is always enough for |
478 | anything that can be stored in them at all. */ | |
479 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
480 | ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ | |
481 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
482 | ||
cfca21cb PB |
483 | /* A C expression that is nonzero if hard register NEW_REG can be |
484 | considered for use as a rename register for OLD_REG register. */ | |
485 | ||
486 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
487 | m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
488 | ||
859711c5 | 489 | /* On the m68k, the cpu registers can hold any mode but the 68881 registers |
15a17b72 | 490 | can hold only SFmode or DFmode. */ |
3d339ad2 | 491 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
71380ac6 | 492 | (((REGNO) < 16 \ |
619aeb96 JW |
493 | && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \ |
494 | || ((REGNO) >= 16 && (REGNO) < 24 \ | |
3d339ad2 | 495 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
b621b712 AS |
496 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ |
497 | && GET_MODE_UNIT_SIZE (MODE) <= 12)) | |
3d339ad2 | 498 | |
3d339ad2 RS |
499 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
500 | (! TARGET_68881 \ | |
501 | || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
502 | || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
503 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
504 | || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) | |
505 | ||
506 | /* Specify the registers used for certain standard purposes. | |
507 | The values of these macros are register numbers. */ | |
508 | ||
3d339ad2 RS |
509 | #define STACK_POINTER_REGNUM 15 |
510 | ||
859711c5 BI |
511 | /* Most m68k targets use %a6 as a frame pointer. The AmigaOS |
512 | ABI uses %a6 for shared library calls, therefore the frame | |
513 | pointer is shifted to %a5 on this target. */ | |
3d339ad2 RS |
514 | #define FRAME_POINTER_REGNUM 14 |
515 | ||
3d339ad2 RS |
516 | #define FRAME_POINTER_REQUIRED 0 |
517 | ||
860c4900 BI |
518 | /* Base register for access to arguments of the function. |
519 | * This isn't a hardware register. It will be eliminated to the | |
520 | * stack pointer or frame pointer. | |
521 | */ | |
522 | #define ARG_POINTER_REGNUM 24 | |
3d339ad2 | 523 | |
3d339ad2 RS |
524 | #define STATIC_CHAIN_REGNUM 8 |
525 | ||
526 | /* Register in which address to store a structure value | |
527 | is passed to a function. */ | |
8636be86 | 528 | #define M68K_STRUCT_VALUE_REGNUM 9 |
3d339ad2 | 529 | |
859711c5 | 530 | \f |
3d339ad2 | 531 | |
859711c5 | 532 | /* The m68k has three kinds of registers, so eight classes would be |
3d339ad2 | 533 | a complete set. One of them is not needed. */ |
3d339ad2 RS |
534 | enum reg_class { |
535 | NO_REGS, DATA_REGS, | |
536 | ADDR_REGS, FP_REGS, | |
537 | GENERAL_REGS, DATA_OR_FP_REGS, | |
538 | ADDR_OR_FP_REGS, ALL_REGS, | |
539 | LIM_REG_CLASSES }; | |
540 | ||
541 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
542 | ||
3d339ad2 RS |
543 | #define REG_CLASS_NAMES \ |
544 | { "NO_REGS", "DATA_REGS", \ | |
545 | "ADDR_REGS", "FP_REGS", \ | |
546 | "GENERAL_REGS", "DATA_OR_FP_REGS", \ | |
547 | "ADDR_OR_FP_REGS", "ALL_REGS" } | |
548 | ||
3d339ad2 RS |
549 | #define REG_CLASS_CONTENTS \ |
550 | { \ | |
7a87758d AS |
551 | {0x00000000}, /* NO_REGS */ \ |
552 | {0x000000ff}, /* DATA_REGS */ \ | |
a4e9467d | 553 | {0x0100ff00}, /* ADDR_REGS */ \ |
7a87758d | 554 | {0x00ff0000}, /* FP_REGS */ \ |
a4e9467d | 555 | {0x0100ffff}, /* GENERAL_REGS */ \ |
7a87758d | 556 | {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ |
a4e9467d RZ |
557 | {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ |
558 | {0x01ffffff}, /* ALL_REGS */ \ | |
3d339ad2 RS |
559 | } |
560 | ||
a4e9467d RZ |
561 | extern enum reg_class regno_reg_class[]; |
562 | #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) | |
3d339ad2 RS |
563 | #define INDEX_REG_CLASS GENERAL_REGS |
564 | #define BASE_REG_CLASS ADDR_REGS | |
565 | ||
859711c5 | 566 | /* We do a trick here to modify the effective constraints on the |
3d339ad2 RS |
567 | machine description; we zorch the constraint letters that aren't |
568 | appropriate for a specific target. This allows us to guarantee | |
569 | that a specific kind of register will not be used for a given target | |
7a1929e1 | 570 | without fiddling with the register classes above. */ |
3d339ad2 RS |
571 | #define REG_CLASS_FROM_LETTER(C) \ |
572 | ((C) == 'a' ? ADDR_REGS : \ | |
573 | ((C) == 'd' ? DATA_REGS : \ | |
574 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
575 | NO_REGS) : \ | |
576 | NO_REGS))) | |
577 | ||
859711c5 | 578 | /* For the m68k, `I' is used for the range 1 to 8 |
3d339ad2 RS |
579 | allowed as immediate shift counts and in addq. |
580 | `J' is used for the range of signed numbers that fit in 16 bits. | |
581 | `K' is for numbers that moveq can't handle. | |
a9f6f5aa | 582 | `L' is for range -8 to -1, range of values that can be added with subq. |
d8fa884b RK |
583 | `M' is for numbers that moveq+notb can't handle. |
584 | 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. | |
585 | 'O' is for 16 (for rotate using swap). | |
586 | 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ | |
a9f6f5aa RK |
587 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
588 | ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ | |
589 | (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ | |
590 | (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ | |
591 | (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ | |
68137318 | 592 | (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ |
d8fa884b RK |
593 | (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ |
594 | (C) == 'O' ? (VALUE) == 16 : \ | |
595 | (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) | |
3d339ad2 | 596 | |
859711c5 BI |
597 | /* "G" defines all of the floating constants that are *NOT* 68881 |
598 | constants. This is so 68881 constants get reloaded and the | |
599 | fpmovecr is used. */ | |
3d339ad2 RS |
600 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
601 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) | |
3d339ad2 | 602 | |
859711c5 | 603 | /* `Q' means address register indirect addressing mode. |
2c8ec431 | 604 | `S' is for operands that satisfy 'm' when -mpcrel is in effect. |
d1fe6168 PB |
605 | `T' is for operands that satisfy 's' when -mpcrel is not in effect. |
606 | `U' is for register offset addressing. */ | |
2c8ec431 DL |
607 | #define EXTRA_CONSTRAINT(OP,CODE) \ |
608 | (((CODE) == 'S') \ | |
609 | ? (TARGET_PCREL \ | |
610 | && GET_CODE (OP) == MEM \ | |
611 | && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
612 | || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ | |
613 | || GET_CODE (XEXP (OP, 0)) == CONST)) \ | |
614 | : \ | |
615 | (((CODE) == 'T') \ | |
616 | ? ( !TARGET_PCREL \ | |
617 | && (GET_CODE (OP) == SYMBOL_REF \ | |
618 | || GET_CODE (OP) == LABEL_REF \ | |
619 | || GET_CODE (OP) == CONST)) \ | |
620 | : \ | |
621 | (((CODE) == 'Q') \ | |
622 | ? (GET_CODE (OP) == MEM \ | |
623 | && GET_CODE (XEXP (OP, 0)) == REG) \ | |
624 | : \ | |
d1fe6168 PB |
625 | (((CODE) == 'U') \ |
626 | ? (GET_CODE (OP) == MEM \ | |
627 | && GET_CODE (XEXP (OP, 0)) == PLUS \ | |
628 | && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ | |
629 | && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ | |
630 | : \ | |
631 | 0)))) | |
02385fc5 | 632 | |
859711c5 | 633 | /* On the m68k, use a data reg if possible when the |
3d339ad2 | 634 | value is a constant in the range where moveq could be used |
9839cd62 | 635 | and we ensure that QImodes are reloaded into data regs. */ |
3d339ad2 RS |
636 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
637 | ((GET_CODE (X) == CONST_INT \ | |
638 | && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ | |
639 | && (CLASS) != ADDR_REGS) \ | |
640 | ? DATA_REGS \ | |
641 | : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ | |
642 | ? DATA_REGS \ | |
9839cd62 RH |
643 | : (GET_CODE (X) == CONST_DOUBLE \ |
644 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
645 | ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ | |
646 | ? FP_REGS : NO_REGS) \ | |
2c8ec431 DL |
647 | : (TARGET_PCREL \ |
648 | && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
649 | || GET_CODE (X) == LABEL_REF)) \ | |
650 | ? ADDR_REGS \ | |
3d339ad2 RS |
651 | : (CLASS)) |
652 | ||
6c13d910 JW |
653 | /* Force QImode output reloads from subregs to be allocated to data regs, |
654 | since QImode stores from address regs are not supported. We make the | |
655 | assumption that if the class is not ADDR_REGS, then it must be a superset | |
656 | of DATA_REGS. */ | |
6c13d910 JW |
657 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
658 | (((MODE) == QImode && (CLASS) != ADDR_REGS) \ | |
659 | ? DATA_REGS \ | |
660 | : (CLASS)) | |
661 | ||
859711c5 | 662 | /* On the m68k, this is the size of MODE in words, |
3d339ad2 | 663 | except in the FP regs, where a single reg is always enough. */ |
3d339ad2 RS |
664 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
665 | ((CLASS) == FP_REGS ? 1 \ | |
666 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
667 | ||
668 | /* Moves between fp regs and other regs are two insns. */ | |
cf011243 | 669 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
3d339ad2 RS |
670 | (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ |
671 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
672 | ? 4 : 2) | |
3d339ad2 RS |
673 | \f |
674 | /* Stack layout; function entry, exit and calling. */ | |
675 | ||
3d339ad2 | 676 | #define STACK_GROWS_DOWNWARD |
3d339ad2 | 677 | #define FRAME_GROWS_DOWNWARD |
3d339ad2 RS |
678 | #define STARTING_FRAME_OFFSET 0 |
679 | ||
859711c5 BI |
680 | /* On the 680x0, sp@- in a byte insn really pushes a word. |
681 | On the ColdFire, sp@- in a byte insn pushes just a byte. */ | |
9425fb04 | 682 | #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) |
3d339ad2 | 683 | |
3d339ad2 RS |
684 | #define FIRST_PARM_OFFSET(FNDECL) 8 |
685 | ||
859711c5 | 686 | /* On the 68000, the RTS insn cannot pop anything. |
6b475ad5 BI |
687 | On the 68010, the RTD insn may be used to pop them if the number |
688 | of args is fixed, but if the number is variable then the caller | |
689 | must pop them all. RTD can't be used for library calls now | |
690 | because the library is compiled with the Unix compiler. | |
691 | Use of RTD is a selectable option, since it is incompatible with | |
692 | standard Unix calling sequences. If the option is not selected, | |
693 | the caller must always pop the args. */ | |
6b475ad5 BI |
694 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
695 | ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ | |
696 | && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ | |
697 | || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ | |
698 | == void_type_node))) \ | |
699 | ? (SIZE) : 0) | |
3d339ad2 | 700 | |
859711c5 | 701 | /* On the m68k the return value is always in D0. */ |
3d339ad2 | 702 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
1d8eaa6b | 703 | gen_rtx_REG (TYPE_MODE (VALTYPE), 0) |
3d339ad2 | 704 | |
859711c5 | 705 | /* On the m68k the return value is always in D0. */ |
1d8eaa6b | 706 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) |
3d339ad2 | 707 | |
859711c5 | 708 | /* On the m68k, D0 is the only register used. */ |
3d339ad2 RS |
709 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) |
710 | ||
7972af82 | 711 | /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for |
859711c5 BI |
712 | more than one register. |
713 | XXX This macro is m68k specific and used only for m68kemb.h. */ | |
7972af82 TW |
714 | #define NEEDS_UNTYPED_CALL 0 |
715 | ||
3d339ad2 RS |
716 | #define PCC_STATIC_STRUCT_RETURN |
717 | ||
859711c5 | 718 | /* On the m68k, all arguments are usually pushed on the stack. */ |
3d339ad2 RS |
719 | #define FUNCTION_ARG_REGNO_P(N) 0 |
720 | \f | |
859711c5 | 721 | /* On the m68k, this is a single integer, which is a number of bytes |
3d339ad2 | 722 | of arguments scanned so far. */ |
3d339ad2 RS |
723 | #define CUMULATIVE_ARGS int |
724 | ||
859711c5 | 725 | /* On the m68k, the offset starts at 0. */ |
0f6937fe | 726 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
3d339ad2 RS |
727 | ((CUM) = 0) |
728 | ||
3d339ad2 RS |
729 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
730 | ((CUM) += ((MODE) != BLKmode \ | |
731 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
732 | : (int_size_in_bytes (TYPE) + 3) & ~3)) | |
733 | ||
859711c5 | 734 | /* On the m68k all args are always pushed. */ |
0988b758 | 735 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 |
0988b758 | 736 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
3d339ad2 | 737 | |
3d339ad2 RS |
738 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
739 | asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) | |
740 | ||
3d339ad2 RS |
741 | #define EXIT_IGNORE_STACK 1 |
742 | ||
3d339ad2 | 743 | /* Determine if the epilogue should be output as RTL. |
859711c5 BI |
744 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. |
745 | ||
746 | XXX This macro is m68k-specific and only used in m68k.md. */ | |
3d339ad2 RS |
747 | #define USE_RETURN_INSN use_return_insn () |
748 | ||
3d339ad2 | 749 | /* Output assembler code for a block containing the constant parts |
859711c5 | 750 | of a trampoline, leaving space for the variable parts. |
3d339ad2 | 751 | |
859711c5 | 752 | On the m68k, the trampoline looks like this: |
27a55d6b RK |
753 | movl #STATIC,a0 |
754 | jmp FUNCTION | |
755 | ||
756 | WARNING: Targets that may run on 68040+ cpus must arrange for | |
757 | the instruction cache to be flushed. Previous incarnations of | |
758 | the m68k trampoline code attempted to get around this by either | |
759 | using an out-of-line transfer function or pc-relative data, but | |
760 | the fact remains that the code to jump to the transfer function | |
761 | or the code to load the pc-relative data needs to be flushed | |
859711c5 | 762 | just as much as the "variable" portion of the trampoline. |
27a55d6b | 763 | Recognizing that a cache flush is going to be required anyway, |
859711c5 | 764 | dispense with such notions and build a smaller trampoline. |
27a55d6b | 765 | |
859711c5 | 766 | Since more instructions are required to move a template into |
27a55d6b | 767 | place than to create it on the spot, don't use a template. */ |
3d339ad2 | 768 | |
27a55d6b | 769 | #define TRAMPOLINE_SIZE 12 |
27a55d6b | 770 | #define TRAMPOLINE_ALIGNMENT 16 |
3d339ad2 | 771 | |
27a55d6b RK |
772 | /* Targets redefine this to invoke code to either flush the cache, |
773 | or enable stack execution (or both). */ | |
27a55d6b RK |
774 | #ifndef FINALIZE_TRAMPOLINE |
775 | #define FINALIZE_TRAMPOLINE(TRAMP) | |
776 | #endif | |
3d339ad2 | 777 | |
859711c5 | 778 | /* We generate a two-instructions program at address TRAMP : |
c85f7c16 | 779 | movea.l &CXT,%a0 |
859711c5 | 780 | jmp FNADDR */ |
3d339ad2 RS |
781 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
782 | { \ | |
1d8eaa6b AS |
783 | emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ |
784 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ | |
785 | emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ | |
27a55d6b | 786 | GEN_INT(0x4EF9)); \ |
1d8eaa6b | 787 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ |
27a55d6b | 788 | FINALIZE_TRAMPOLINE(TRAMP); \ |
3d339ad2 RS |
789 | } |
790 | ||
859711c5 BI |
791 | /* This is the library routine that is used to transfer control from the |
792 | trampoline to the actual nested function. It is defined for backward | |
793 | compatibility, for linking with object code that used the old trampoline | |
794 | definition. | |
3d339ad2 | 795 | |
859711c5 BI |
796 | A colon is used with no explicit operands to cause the template string |
797 | to be scanned for %-constructs. | |
798 | ||
799 | The function name __transfer_from_trampoline is not actually used. | |
3d339ad2 RS |
800 | The function definition just permits use of "asm with operands" |
801 | (though the operand list is empty). */ | |
802 | #define TRANSFER_FROM_TRAMPOLINE \ | |
803 | void \ | |
804 | __transfer_from_trampoline () \ | |
805 | { \ | |
806 | register char *a0 asm ("%a0"); \ | |
016c8440 | 807 | asm (GLOBAL_ASM_OP "___trampoline"); \ |
3d339ad2 | 808 | asm ("___trampoline:"); \ |
338818c7 RK |
809 | asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ |
810 | asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ | |
3d339ad2 RS |
811 | asm ("rts":); \ |
812 | } | |
813 | \f | |
859711c5 | 814 | /* There are two registers that can always be eliminated on the m68k. |
860c4900 BI |
815 | The frame pointer and the arg pointer can be replaced by either the |
816 | hard frame pointer or to the stack pointer, depending upon the | |
817 | circumstances. The hard frame pointer is not used before reload and | |
818 | so it is not eligible for elimination. */ | |
860c4900 BI |
819 | #define ELIMINABLE_REGS \ |
820 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
859711c5 | 821 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ |
860c4900 BI |
822 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} |
823 | ||
860c4900 BI |
824 | #define CAN_ELIMINATE(FROM, TO) \ |
825 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
826 | ||
860c4900 BI |
827 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
828 | (OFFSET) = m68k_initial_elimination_offset(FROM, TO) | |
829 | \f | |
3d339ad2 RS |
830 | /* Addressing modes, and classification of registers for them. */ |
831 | ||
940da324 | 832 | #define HAVE_POST_INCREMENT 1 |
940da324 | 833 | #define HAVE_PRE_DECREMENT 1 |
3d339ad2 RS |
834 | |
835 | /* Macros to check register numbers against specific register classes. */ | |
836 | ||
3d339ad2 RS |
837 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
838 | ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) | |
839 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
840 | (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) | |
841 | #define REGNO_OK_FOR_DATA_P(REGNO) \ | |
842 | ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
843 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
844 | (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) | |
3d339ad2 RS |
845 | |
846 | /* Now macros that check whether X is a register and also, | |
847 | strictly, whether it is in a specified class. | |
848 | ||
859711c5 | 849 | These macros are specific to the m68k, and may be used only |
3d339ad2 RS |
850 | in code for printing assembler insns and in conditions for |
851 | define_optimization. */ | |
852 | ||
853 | /* 1 if X is a data register. */ | |
3d339ad2 RS |
854 | #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) |
855 | ||
856 | /* 1 if X is an fp register. */ | |
3d339ad2 RS |
857 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) |
858 | ||
859 | /* 1 if X is an address register */ | |
3d339ad2 | 860 | #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) |
3d339ad2 | 861 | \f |
3d339ad2 RS |
862 | |
863 | #define MAX_REGS_PER_ADDRESS 2 | |
864 | ||
6eff269e BK |
865 | #define CONSTANT_ADDRESS_P(X) \ |
866 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
867 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
868 | || GET_CODE (X) == HIGH) | |
3d339ad2 RS |
869 | |
870 | /* Nonzero if the constant value X is a legitimate general operand. | |
871 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
8338d44d | 872 | #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode) |
3d339ad2 | 873 | |
2c8ec431 DL |
874 | #ifndef REG_OK_STRICT |
875 | #define PCREL_GENERAL_OPERAND_OK 0 | |
876 | #else | |
877 | #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) | |
878 | #endif | |
3d339ad2 RS |
879 | |
880 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
8338d44d JW |
881 | (! symbolic_operand (X, VOIDmode) \ |
882 | || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ | |
2c8ec431 | 883 | || PCREL_GENERAL_OPERAND_OK) |
3d339ad2 | 884 | |
3d339ad2 RS |
885 | #ifndef REG_OK_STRICT |
886 | ||
887 | /* Nonzero if X is a hard reg that can be used as an index | |
888 | or if it is a pseudo reg. */ | |
889 | #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) | |
890 | /* Nonzero if X is a hard reg that can be used as a base reg | |
891 | or if it is a pseudo reg. */ | |
892 | #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) | |
893 | ||
894 | #else | |
895 | ||
896 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
897 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
898 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
899 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
900 | ||
901 | #endif | |
902 | \f | |
903 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
904 | that is a valid memory address for an instruction. | |
905 | The MODE argument is the machine mode for the MEM expression | |
906 | that wants to use this address. | |
907 | ||
908 | When generating PIC, an address involving a SYMBOL_REF is legitimate | |
909 | if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. | |
910 | We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, | |
911 | and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. | |
912 | ||
913 | Likewise for a LABEL_REF when generating PIC. | |
914 | ||
915 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
916 | ||
22291e2f JW |
917 | /* Allow SUBREG everywhere we allow REG. This results in better code. It |
918 | also makes function inlining work when inline functions are called with | |
919 | arguments that are SUBREGs. */ | |
920 | ||
921 | #define LEGITIMATE_BASE_REG_P(X) \ | |
922 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
923 | || (GET_CODE (X) == SUBREG \ | |
924 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
925 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
926 | ||
3d339ad2 RS |
927 | #define INDIRECTABLE_1_ADDRESS_P(X) \ |
928 | ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ | |
22291e2f | 929 | || LEGITIMATE_BASE_REG_P (X) \ |
3d339ad2 | 930 | || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ |
22291e2f | 931 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ |
3d339ad2 | 932 | || (GET_CODE (X) == PLUS \ |
22291e2f | 933 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ |
3d339ad2 | 934 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ |
8b83b2a7 PJ |
935 | && (TARGET_68020 \ |
936 | || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ | |
3d339ad2 RS |
937 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ |
938 | && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ | |
939 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ | |
2c8ec431 | 940 | && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) |
3d339ad2 | 941 | |
3d339ad2 RS |
942 | #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ |
943 | { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } | |
944 | ||
875c5a31 RS |
945 | /* Only labels on dispatch tables are valid for indexing from. */ |
946 | #define GO_IF_INDEXABLE_BASE(X, ADDR) \ | |
947 | { rtx temp; \ | |
948 | if (GET_CODE (X) == LABEL_REF \ | |
949 | && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ | |
950 | && GET_CODE (temp) == JUMP_INSN \ | |
951 | && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ | |
952 | || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ | |
953 | goto ADDR; \ | |
22291e2f | 954 | if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } |
3d339ad2 RS |
955 | |
956 | #define GO_IF_INDEXING(X, ADDR) \ | |
957 | { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ | |
958 | { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ | |
959 | if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ | |
960 | { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } | |
961 | ||
962 | #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ | |
963 | { GO_IF_INDEXING (X, ADDR); \ | |
964 | if (GET_CODE (X) == PLUS) \ | |
965 | { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
9cf3ae46 | 966 | && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ |
3d339ad2 RS |
967 | { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ |
968 | if (GET_CODE (XEXP (X, 0)) == CONST_INT \ | |
9cf3ae46 | 969 | && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ |
3d339ad2 RS |
970 | { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } |
971 | ||
c16eadc7 | 972 | /* ColdFire/5200 does not allow HImode index registers. */ |
3d339ad2 RS |
973 | #define LEGITIMATE_INDEX_REG_P(X) \ |
974 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
9425fb04 | 975 | || (! TARGET_COLDFIRE \ |
03db53b1 | 976 | && GET_CODE (X) == SIGN_EXTEND \ |
3d339ad2 RS |
977 | && GET_CODE (XEXP (X, 0)) == REG \ |
978 | && GET_MODE (XEXP (X, 0)) == HImode \ | |
22291e2f JW |
979 | && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
980 | || (GET_CODE (X) == SUBREG \ | |
981 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
982 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
3d339ad2 RS |
983 | |
984 | #define LEGITIMATE_INDEX_P(X) \ | |
985 | (LEGITIMATE_INDEX_REG_P (X) \ | |
9425fb04 | 986 | || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \ |
3d339ad2 RS |
987 | && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ |
988 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
989 | && (INTVAL (XEXP (X, 1)) == 2 \ | |
990 | || INTVAL (XEXP (X, 1)) == 4 \ | |
9425fb04 | 991 | || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE)))) |
3d339ad2 | 992 | |
04e61bd4 RS |
993 | /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ |
994 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
995 | { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ | |
996 | GO_IF_INDEXED_ADDRESS (X, ADDR); \ | |
997 | if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ | |
998 | && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ | |
999 | && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ | |
1000 | goto ADDR; } | |
1001 | ||
1002 | /* Don't call memory_address_noforce for the address to fetch | |
1003 | the switch offset. This address is ok as it stands (see above), | |
1004 | but memory_address_noforce would alter it. */ | |
1005 | #define PIC_CASE_VECTOR_ADDRESS(index) index | |
3d339ad2 | 1006 | \f |
859711c5 | 1007 | /* For the 68000, we handle X+REG by loading X into a register R and |
3d339ad2 RS |
1008 | using R+REG. R will go in an address reg and indexing will be used. |
1009 | However, if REG is a broken-out memory address or multiplication, | |
1010 | nothing needs to be done because REG can certainly go in an address reg. */ | |
3d339ad2 RS |
1011 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } |
1012 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1013 | { register int ch = (X) != (OLDX); \ | |
1014 | if (GET_CODE (X) == PLUS) \ | |
1015 | { int copied = 0; \ | |
1016 | if (GET_CODE (XEXP (X, 0)) == MULT) \ | |
1017 | { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ | |
1018 | if (GET_CODE (XEXP (X, 1)) == MULT) \ | |
1019 | { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ | |
1020 | if (ch && GET_CODE (XEXP (X, 1)) == REG \ | |
1021 | && GET_CODE (XEXP (X, 0)) == REG) \ | |
1022 | goto WIN; \ | |
1023 | if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ | |
1024 | if (GET_CODE (XEXP (X, 0)) == REG \ | |
1025 | || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ | |
1026 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1027 | && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ | |
1028 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1029 | register rtx val = force_operand (XEXP (X, 1), 0); \ | |
1030 | emit_move_insn (temp, val); \ | |
1031 | COPY_ONCE (X); \ | |
1032 | XEXP (X, 1) = temp; \ | |
1033 | goto WIN; } \ | |
1034 | else if (GET_CODE (XEXP (X, 1)) == REG \ | |
1035 | || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ | |
1036 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ | |
1037 | && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ | |
1038 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1039 | register rtx val = force_operand (XEXP (X, 0), 0); \ | |
1040 | emit_move_insn (temp, val); \ | |
1041 | COPY_ONCE (X); \ | |
1042 | XEXP (X, 0) = temp; \ | |
1043 | goto WIN; }}} | |
1044 | ||
859711c5 | 1045 | /* On the 68000, only predecrement and postincrement address depend thus |
3d339ad2 | 1046 | (the amount of decrement or increment being the length of the operand). */ |
3d339ad2 RS |
1047 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ |
1048 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL | |
1049 | \f | |
3d339ad2 | 1050 | #define CASE_VECTOR_MODE HImode |
18543a22 | 1051 | #define CASE_VECTOR_PC_RELATIVE 1 |
3d339ad2 | 1052 | |
3d339ad2 | 1053 | #define DEFAULT_SIGNED_CHAR 1 |
3d339ad2 | 1054 | #define MOVE_MAX 4 |
3d339ad2 RS |
1055 | #define SLOW_BYTE_ACCESS 0 |
1056 | ||
3d339ad2 RS |
1057 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
1058 | ||
37941398 | 1059 | #define STORE_FLAG_VALUE (-1) |
3d339ad2 | 1060 | |
3d339ad2 | 1061 | #define Pmode SImode |
3d339ad2 RS |
1062 | #define FUNCTION_MODE QImode |
1063 | ||
3d339ad2 RS |
1064 | \f |
1065 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1066 | ||
1067 | /* Here we define machine-dependent flags and fields in cc_status | |
1068 | (see `conditions.h'). */ | |
1069 | ||
1070 | /* Set if the cc value is actually in the 68881, so a floating point | |
1071 | conditional branch must be output. */ | |
1072 | #define CC_IN_68881 04000 | |
1073 | ||
3d339ad2 RS |
1074 | /* On the 68000, all the insns to store in an address register fail to |
1075 | set the cc's. However, in some cases these instructions can make it | |
1076 | possibly invalid to use the saved cc's. In those cases we clear out | |
1077 | some or all of the saved cc's so they won't be used. */ | |
3d339ad2 RS |
1078 | #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) |
1079 | ||
1080 | #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ | |
f082d7a9 | 1081 | do { if (cc_prev_status.flags & CC_IN_68881) \ |
3d339ad2 RS |
1082 | return FLOAT; \ |
1083 | if (cc_prev_status.flags & CC_NO_OVERFLOW) \ | |
1084 | return NO_OV; \ | |
f082d7a9 | 1085 | return NORMAL; } while (0) |
3d339ad2 RS |
1086 | \f |
1087 | /* Control the assembler format that we output. */ | |
1088 | ||
3d339ad2 | 1089 | #define ASM_APP_ON "#APP\n" |
3d339ad2 | 1090 | #define ASM_APP_OFF "#NO_APP\n" |
6e7b07a7 | 1091 | #define TEXT_SECTION_ASM_OP "\t.text" |
6e7b07a7 | 1092 | #define DATA_SECTION_ASM_OP "\t.data" |
2cff4a6e | 1093 | #define GLOBAL_ASM_OP "\t.globl\t" |
3d339ad2 | 1094 | #define REGISTER_PREFIX "" |
3d339ad2 | 1095 | #define LOCAL_LABEL_PREFIX "" |
3d339ad2 | 1096 | #define USER_LABEL_PREFIX "_" |
3d339ad2 RS |
1097 | #define IMMEDIATE_PREFIX "#" |
1098 | ||
3d339ad2 | 1099 | #define REGISTER_NAMES \ |
cfe084c8 BI |
1100 | {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \ |
1101 | REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \ | |
1102 | REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \ | |
1103 | REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \ | |
1104 | REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \ | |
1105 | REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \ | |
1106 | REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \ | |
1107 | REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \ | |
1108 | REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" } | |
1109 | ||
1110 | #define M68K_FP_REG_NAME REGISTER_PREFIX"fp" | |
1111 | ||
1112 | /* Return a register name by index, handling %fp nicely. | |
1113 | We don't replace %fp for targets that don't map it to %a6 | |
1114 | since it may confuse GAS. */ | |
1115 | #define M68K_REGNAME(r) ( \ | |
1116 | ((FRAME_POINTER_REGNUM == 14) \ | |
1117 | && ((r) == FRAME_POINTER_REGNUM) \ | |
1118 | && frame_pointer_needed) ? \ | |
1119 | M68K_FP_REG_NAME : reg_names[(r)]) | |
3d339ad2 | 1120 | |
859711c5 | 1121 | /* On the Sun-3, the floating point registers have numbers |
3d339ad2 | 1122 | 18 to 25, not 16 to 23 as they do in the compiler. */ |
3d339ad2 RS |
1123 | #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) |
1124 | ||
078e983e AS |
1125 | /* Before the prologue, RA is at 0(%sp). */ |
1126 | #define INCOMING_RETURN_ADDR_RTX \ | |
1d8eaa6b | 1127 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
078e983e AS |
1128 | |
1129 | /* We must not use the DBX register numbers for the DWARF 2 CFA column | |
1130 | numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
1131 | Instead use the identity mapping. */ | |
1132 | #define DWARF_FRAME_REGNUM(REG) REG | |
1133 | ||
1134 | /* Before the prologue, the top of the frame is at 4(%sp). */ | |
1135 | #define INCOMING_FRAME_SP_OFFSET 4 | |
1136 | ||
2cff4a6e AS |
1137 | /* Describe how we implement __builtin_eh_return. */ |
1138 | #define EH_RETURN_DATA_REGNO(N) \ | |
1139 | ((N) < 2 ? (N) : INVALID_REGNUM) | |
1140 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) | |
1141 | #define EH_RETURN_HANDLER_RTX \ | |
1142 | gen_rtx_MEM (Pmode, \ | |
1143 | gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ | |
1144 | plus_constant (EH_RETURN_STACKADJ_RTX, \ | |
1145 | UNITS_PER_WORD))) | |
1146 | ||
1147 | /* Select a format to encode pointers in exception handling data. CODE | |
1148 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
1149 | true if the symbol may be affected by dynamic relocations. */ | |
859711c5 | 1150 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
2cff4a6e AS |
1151 | (flag_pic \ |
1152 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
1153 | : DW_EH_PE_absptr) | |
3d339ad2 | 1154 | |
3d339ad2 | 1155 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ |
1f85a612 | 1156 | asm_fprintf (FILE, "%U%s", NAME) |
3d339ad2 | 1157 | |
3d339ad2 | 1158 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
e59f7d3d | 1159 | sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) |
3d339ad2 | 1160 | |
3d339ad2 RS |
1161 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ |
1162 | asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) | |
3d339ad2 RS |
1163 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ |
1164 | asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) | |
1165 | ||
859711c5 BI |
1166 | /* The m68k does not use absolute case-vectors, but we must define this macro |
1167 | anyway. */ | |
3d339ad2 RS |
1168 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
1169 | asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) | |
1170 | ||
33f7f353 | 1171 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3d339ad2 RS |
1172 | asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) |
1173 | ||
b4ac57ab RS |
1174 | /* We don't have a way to align to more than a two-byte boundary, so do the |
1175 | best we can and don't complain. */ | |
3d339ad2 | 1176 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
b4ac57ab RS |
1177 | if ((LOG) >= 1) \ |
1178 | fprintf (FILE, "\t.even\n"); | |
3d339ad2 RS |
1179 | |
1180 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 1181 | fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) |
3d339ad2 | 1182 | |
3d339ad2 RS |
1183 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
1184 | ( fputs (".comm ", (FILE)), \ | |
1185 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1186 | fprintf ((FILE), ",%u\n", (int)(ROUNDED))) |
3d339ad2 | 1187 | |
3d339ad2 RS |
1188 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ |
1189 | ( fputs (".lcomm ", (FILE)), \ | |
1190 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1191 | fprintf ((FILE), ",%u\n", (int)(ROUNDED))) |
3d339ad2 | 1192 | |
3d339ad2 | 1193 | /* Output a float value (represented as a C double) as an immediate operand. |
859711c5 | 1194 | This macro is m68k-specific. */ |
f6ba6a91 RS |
1195 | #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ |
1196 | do { \ | |
1197 | if (CODE == 'f') \ | |
1198 | { \ | |
1199 | char dstr[30]; \ | |
859711c5 | 1200 | real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ |
f6ba6a91 RS |
1201 | asm_fprintf ((FILE), "%I0r%s", dstr); \ |
1202 | } \ | |
1203 | else \ | |
1204 | { \ | |
1205 | long l; \ | |
1206 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
97b57a81 | 1207 | asm_fprintf ((FILE), "%I0x%lx", l); \ |
f6ba6a91 RS |
1208 | } \ |
1209 | } while (0) | |
3d339ad2 RS |
1210 | |
1211 | /* Output a double value (represented as a C double) as an immediate operand. | |
859711c5 | 1212 | This macro is m68k-specific. */ |
3d339ad2 | 1213 | #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ |
f6ba6a91 | 1214 | do { char dstr[30]; \ |
da6eec72 | 1215 | real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ |
f6ba6a91 RS |
1216 | asm_fprintf (FILE, "%I0r%s", dstr); \ |
1217 | } while (0) | |
1218 | ||
1219 | /* Note, long double immediate operands are not actually | |
1220 | generated by m68k.md. */ | |
1221 | #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ | |
1222 | do { char dstr[30]; \ | |
da6eec72 | 1223 | real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ |
f6ba6a91 RS |
1224 | asm_fprintf (FILE, "%I0r%s", dstr); \ |
1225 | } while (0) | |
3d339ad2 | 1226 | |
859711c5 | 1227 | /* On the 68000, we use several CODE characters: |
3d339ad2 RS |
1228 | '.' for dot needed in Motorola-style opcode names. |
1229 | '-' for an operand pushing on the stack: | |
1230 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
1231 | '+' for an operand pushing on the stack: | |
1232 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
1233 | '@' for a reference to the top word on the stack: | |
1234 | sp@, (sp) or (%sp) depending on the style of syntax. | |
ac5f9961 BI |
1235 | '#' for an immediate operand prefix (# in MIT and Motorola syntax |
1236 | but & in SGS syntax). | |
7c129456 | 1237 | '!' for the fpcr register (used in some float-to-fixed conversions). |
3d339ad2 RS |
1238 | '$' for the letter `s' in an op code, but only on the 68040. |
1239 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 1240 | '/' for register prefix needed by longlong.h. |
3d339ad2 RS |
1241 | |
1242 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
1243 | 'd' to force memory addressing to be absolute, not relative. | |
1244 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
2c8ec431 DL |
1245 | 'o' for operands to go directly to output_operand_address (bypassing |
1246 | print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) | |
3d339ad2 | 1247 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
1a8965c4 | 1248 | or print pair of registers as rx:ry. */ |
3d339ad2 RS |
1249 | |
1250 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
ac5f9961 BI |
1251 | ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ |
1252 | || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ | |
1253 | || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') | |
3d339ad2 | 1254 | |
3d339ad2 | 1255 | |
859711c5 | 1256 | /* See m68k.c for the m68k specific codes. */ |
3d339ad2 RS |
1257 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
1258 | ||
3d339ad2 RS |
1259 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
1260 | ||
9e62c7f2 | 1261 | /* Variables in m68k.c */ |
a2ef3db7 | 1262 | extern const char *m68k_library_id_string; |
2b3600ac | 1263 | extern int m68k_last_compare_had_fp_operands; |
9e62c7f2 | 1264 | |
1062f15a AS |
1265 | \f |
1266 | /* Define the codes that are matched by predicates in m68k.c. */ | |
1267 | ||
1268 | #define PREDICATE_CODES \ | |
1269 | {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ | |
1270 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
1271 | {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \ | |
1272 | {"memory_src_operand", {SUBREG, MEM}}, \ | |
1273 | {"not_sp_operand", {SUBREG, REG, MEM}}, \ | |
1274 | {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \ | |
1275 | {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
1276 | {"const_sint32_operand", {CONST_INT}}, \ | |
1277 | {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \ | |
1278 | GT, LT, GE, LE}}, \ | |
428511bb | 1279 | {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, \ |
9652c531 RZ |
1280 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ |
1281 | {"post_inc_operand", {MEM}}, \ | |
1282 | {"pre_dec_operand", {MEM}}, |