]>
Commit | Line | Data |
---|---|---|
cf011243 AO |
1 | /* Definitions of target machine for GNU compiler. |
2 | Sun 68000/68020 version. | |
3 | Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, | |
16c484c7 | 4 | 2000, 2001, 2002 Free Software Foundation, Inc. |
25a1b918 | 5 | |
3d339ad2 RS |
6 | This file is part of GNU CC. |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
0e29e3c9 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
3d339ad2 RS |
22 | |
23 | ||
24 | /* Note that some other tm.h files include this one and then override | |
25 | many of the definitions that relate to assembler syntax. */ | |
26 | ||
27 | ||
301d03af RS |
28 | /* Classify the groups of pseudo-ops used to assemble QI, HI and SI |
29 | quantities. */ | |
30 | #define INT_OP_STANDARD 0 /* .byte, .short, .long */ | |
31 | #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ | |
32 | #define INT_OP_NO_DOT 2 /* byte, short, long */ | |
33 | #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ | |
34 | ||
35 | /* Set the default */ | |
36 | #define INT_OP_GROUP INT_OP_DOT_WORD | |
37 | ||
3d339ad2 RS |
38 | /* Names to predefine in the preprocessor for this target machine. */ |
39 | ||
40 | /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ | |
41 | ||
42 | /* Print subsidiary information on the compiler version in use. */ | |
43 | #ifdef MOTOROLA | |
44 | #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); | |
45 | #else | |
46 | #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); | |
47 | #endif | |
48 | ||
49 | /* Define SUPPORT_SUN_FPA to include support for generating code for | |
50 | the Sun Floating Point Accelerator, an optional product for Sun 3 | |
51 | machines. By default, it is not defined. Avoid defining it unless | |
52 | you need to output code for the Sun3+FPA architecture, as it has the | |
53 | effect of slowing down the register set operations in hard-reg-set.h | |
54 | (total number of registers will exceed number of bits in a long, | |
55 | if defined, causing the set operations to expand to loops). | |
56 | SUPPORT_SUN_FPA is typically defined in sun3.h. */ | |
57 | ||
58 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
59 | ||
60 | extern int target_flags; | |
61 | ||
62 | /* Macros used in the machine description to test the flags. */ | |
63 | ||
64 | /* Compile for a 68020 (not a 68000 or 68010). */ | |
7a1b98a9 RK |
65 | #define MASK_68020 1 |
66 | #define TARGET_68020 (target_flags & MASK_68020) | |
3d339ad2 RS |
67 | |
68 | /* Compile 68881 insns for floating point (not library calls). */ | |
7a1b98a9 RK |
69 | #define MASK_68881 2 |
70 | #define TARGET_68881 (target_flags & MASK_68881) | |
3d339ad2 RS |
71 | |
72 | /* Compile using 68020 bitfield insns. */ | |
7a1b98a9 RK |
73 | #define MASK_BITFIELD 4 |
74 | #define TARGET_BITFIELD (target_flags & MASK_BITFIELD) | |
3d339ad2 RS |
75 | |
76 | /* Compile using rtd insn calling sequence. | |
77 | This will not work unless you use prototypes at least | |
78 | for all functions that can take varying numbers of args. */ | |
7a1b98a9 RK |
79 | #define MASK_RTD 8 |
80 | #define TARGET_RTD (target_flags & MASK_RTD) | |
3d339ad2 RS |
81 | |
82 | /* Compile passing first two args in regs 0 and 1. | |
83 | This exists only to test compiler features that will | |
84 | be needed for RISC chips. It is not usable | |
85 | and is not intended to be usable on this cpu. */ | |
7a1b98a9 RK |
86 | #define MASK_REGPARM 16 |
87 | #define TARGET_REGPARM (target_flags & MASK_REGPARM) | |
3d339ad2 RS |
88 | |
89 | /* Compile with 16-bit `int'. */ | |
7a1b98a9 RK |
90 | #define MASK_SHORT 32 |
91 | #define TARGET_SHORT (target_flags & MASK_SHORT) | |
3d339ad2 RS |
92 | |
93 | /* Compile with special insns for Sun FPA. */ | |
7a1b98a9 RK |
94 | #define MASK_FPA 64 |
95 | #define TARGET_FPA (target_flags & MASK_FPA) | |
3d339ad2 RS |
96 | |
97 | /* Compile (actually, link) for Sun SKY board. */ | |
7a1b98a9 RK |
98 | #define MASK_SKY 128 |
99 | #define TARGET_SKY (target_flags & MASK_SKY) | |
3d339ad2 | 100 | |
b4281273 RS |
101 | /* Optimize for 68040, but still allow execution on 68020 |
102 | (-m68020-40 or -m68040). | |
b4ac57ab | 103 | The 68040 will execute all 68030 and 68881/2 instructions, but some |
3d339ad2 RS |
104 | of them must be emulated in software by the OS. When TARGET_68040 is |
105 | turned on, these instructions won't be used. This code will still | |
7a1929e1 | 106 | run on a 68030 and 68881/2. */ |
35bcca7b | 107 | #define MASK_68040 256 |
7a1b98a9 | 108 | #define TARGET_68040 (target_flags & MASK_68040) |
3d339ad2 | 109 | |
30e6bc63 | 110 | /* Use the 68040-only fp instructions (-m68040 or -m68060). */ |
7a1b98a9 RK |
111 | #define MASK_68040_ONLY 512 |
112 | #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) | |
3d339ad2 | 113 | |
30e6bc63 | 114 | /* Optimize for 68060, but still allow execution on 68020 |
35bcca7b | 115 | (-m68020-60 or -m68060). |
30e6bc63 RK |
116 | The 68060 will execute all 68030 and 68881/2 instructions, but some |
117 | of them must be emulated in software by the OS. When TARGET_68060 is | |
118 | turned on, these instructions won't be used. This code will still | |
7a1929e1 | 119 | run on a 68030 and 68881/2. */ |
7a1b98a9 RK |
120 | #define MASK_68060 1024 |
121 | #define TARGET_68060 (target_flags & MASK_68060) | |
30e6bc63 | 122 | |
106bee4b RK |
123 | /* Compile for mcf5200 */ |
124 | #define MASK_5200 2048 | |
125 | #define TARGET_5200 (target_flags & MASK_5200) | |
126 | ||
dcd13066 RK |
127 | /* Align ints to a word boundary. This breaks compatibility with the |
128 | published ABI's for structures containing ints, but produces faster | |
129 | code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire). | |
130 | It's required for coldfire cpus without a misalignment module. */ | |
131 | #define MASK_ALIGN_INT 4096 | |
132 | #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) | |
133 | ||
b686ee30 RK |
134 | /* Compile for a CPU32 */ |
135 | /* A 68020 without bitfields is a good heuristic for a CPU32 */ | |
136 | #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) | |
137 | ||
2c8ec431 DL |
138 | /* Use PC-relative addressing modes (without using a global offset table). |
139 | The m68000 supports 16-bit PC-relative addressing. | |
140 | The m68020 supports 32-bit PC-relative addressing | |
141 | (using outer displacements). | |
142 | ||
143 | Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are | |
144 | treated as all containing an implicit PC-relative component, and hence | |
145 | cannot be used directly as addresses for memory writes. See the comments | |
146 | in m68k.c for more information. */ | |
b71733d5 | 147 | #define MASK_PCREL 8192 |
2c8ec431 DL |
148 | #define TARGET_PCREL (target_flags & MASK_PCREL) |
149 | ||
7a1929e1 | 150 | /* Relax strict alignment. */ |
b71733d5 GM |
151 | #define MASK_NO_STRICT_ALIGNMENT 16384 |
152 | #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) | |
153 | ||
3d339ad2 RS |
154 | /* Macro to define tables used to set the flags. |
155 | This is a list in braces of pairs in braces, | |
156 | each pair being { "NAME", VALUE } | |
157 | where VALUE is the bits to set or minus the bits to clear. | |
158 | An empty string NAME is used to identify the default VALUE. */ | |
159 | ||
f18bff15 RZ |
160 | #define TARGET_SWITCHES \ |
161 | { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ | |
162 | N_("Generate code for a 68020") }, \ | |
163 | { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ | |
164 | N_("Generate code for a 68020") }, \ | |
165 | { "68020", (MASK_68020|MASK_BITFIELD), "" }, \ | |
166 | { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ | |
35bcca7b | 167 | { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
168 | |MASK_68020|MASK_BITFIELD|MASK_68881), \ |
169 | N_("Generate code for a 68000") }, \ | |
35bcca7b | 170 | { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
171 | |MASK_68020|MASK_BITFIELD|MASK_68881), \ |
172 | N_("Generate code for a 68000") }, \ | |
173 | { "bitfield", MASK_BITFIELD, \ | |
174 | N_("Use the bit-field instructions") }, \ | |
175 | { "nobitfield", - MASK_BITFIELD, \ | |
176 | N_("Do not use the bit-field instructions") }, \ | |
177 | { "rtd", MASK_RTD, \ | |
178 | N_("Use different calling convention using 'rtd'") }, \ | |
179 | { "nortd", - MASK_RTD, \ | |
180 | N_("Use normal calling convention") }, \ | |
181 | { "short", MASK_SHORT, \ | |
182 | N_("Consider type `int' to be 16 bits wide") }, \ | |
183 | { "noshort", - MASK_SHORT, \ | |
184 | N_("Consider type `int' to be 32 bits wide") }, \ | |
185 | { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881), \ | |
186 | N_("Generate code for a Sun FPA") }, \ | |
187 | { "fpa", MASK_FPA, "" }, \ | |
188 | { "nofpa", - MASK_FPA, \ | |
189 | N_("Do not generate code for a Sun FPA") }, \ | |
190 | { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881), \ | |
5b7874aa | 191 | N_("Generate code for a Sun Sky board") }, \ |
f18bff15 | 192 | { "sky", MASK_SKY, \ |
5b7874aa | 193 | N_("Generate code for a Sun Sky board") }, \ |
f18bff15 | 194 | { "nosky", - MASK_SKY, \ |
5b7874aa | 195 | N_("Do not use Sky linkage convention") }, \ |
f18bff15 RZ |
196 | { "68881", - (MASK_FPA|MASK_SKY), \ |
197 | N_("Generate code for a 68881") }, \ | |
198 | { "68881", MASK_68881, "" }, \ | |
199 | { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881), \ | |
200 | N_("Generate code with library calls for floating point") }, \ | |
201 | { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \ | |
202 | N_("Generate code for a 68040, without any new instructions") }, \ | |
203 | { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ | |
204 | { "68020-60", -(MASK_5200|MASK_68040_ONLY), \ | |
205 | N_("Generate code for a 68060, without any new instructions") }, \ | |
8309458a | 206 | { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ |
f18bff15 RZ |
207 | |MASK_68060), "" }, \ |
208 | { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ | |
209 | N_("Generate code for a 68030") }, \ | |
210 | { "68030", (MASK_68020|MASK_BITFIELD), "" }, \ | |
211 | { "68040", - (MASK_5200|MASK_68060), \ | |
212 | N_("Generate code for a 68040") }, \ | |
35bcca7b | 213 | { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ |
f18bff15 RZ |
214 | |MASK_68040_ONLY|MASK_68040), "" }, \ |
215 | { "68060", - (MASK_5200|MASK_68040), \ | |
216 | N_("Generate code for a 68060") }, \ | |
7a1b98a9 | 217 | { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ |
f18bff15 | 218 | |MASK_68040_ONLY|MASK_68060), "" }, \ |
e8d16166 | 219 | { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
f18bff15 RZ |
220 | |MASK_BITFIELD|MASK_68881), \ |
221 | N_("Generate code for a 520X") }, \ | |
222 | { "5200", (MASK_5200), "" }, \ | |
223 | { "68851", 0, \ | |
224 | N_("Generate code for a 68851") }, \ | |
225 | { "no-68851", 0, \ | |
226 | N_("Do no generate code for a 68851") }, \ | |
239e68f6 | 227 | { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
228 | |MASK_68020|MASK_BITFIELD|MASK_68881), \ |
229 | N_("Generate code for a 68302") }, \ | |
239e68f6 | 230 | { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
231 | |MASK_BITFIELD|MASK_68881), \ |
232 | N_("Generate code for a 68332") }, \ | |
233 | { "68332", MASK_68020, "" }, \ | |
239e68f6 | 234 | { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
f18bff15 RZ |
235 | |MASK_BITFIELD|MASK_68881), \ |
236 | N_("Generate code for a cpu32") }, \ | |
237 | { "cpu32", MASK_68020, "" }, \ | |
238 | { "align-int", MASK_ALIGN_INT, \ | |
239 | N_("Align variables on a 32-bit boundary") }, \ | |
240 | { "no-align-int", -MASK_ALIGN_INT, \ | |
241 | N_("Align variables on a 16-bit boundary") }, \ | |
242 | { "pcrel", MASK_PCREL, \ | |
243 | N_("Generate pc-relative code") }, \ | |
244 | { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \ | |
245 | N_("Do not use unaligned memory references") }, \ | |
246 | { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \ | |
247 | N_("Use unaligned memory references") }, \ | |
7a1b98a9 | 248 | SUBTARGET_SWITCHES \ |
f18bff15 | 249 | { "", TARGET_DEFAULT, "" }} |
3d339ad2 | 250 | /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ |
882ed710 | 251 | |
9e62c7f2 RK |
252 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
253 | command options that have values. Its definition is an | |
254 | initializer with a subgrouping for each command option. | |
255 | ||
256 | Each subgrouping contains a string constant, that defines the | |
257 | fixed part of the option name, and the address of a variable. The | |
258 | variable, type `char *', is set to the variable part of the given | |
259 | option if the fixed part matches. The actual option name is made | |
260 | by appending `-m' to the specified name. */ | |
261 | #define TARGET_OPTIONS \ | |
f18bff15 RZ |
262 | { { "align-loops=", &m68k_align_loops_string, \ |
263 | N_("Loop code aligned to this power of 2") }, \ | |
264 | { "align-jumps=", &m68k_align_jumps_string, \ | |
265 | N_("Jump targets are aligned to this power of 2") }, \ | |
266 | { "align-functions=", &m68k_align_funcs_string, \ | |
267 | N_("Function starts are aligned to this power of 2") }, \ | |
9e62c7f2 RK |
268 | SUBTARGET_OPTIONS \ |
269 | } | |
270 | ||
271 | /* Sometimes certain combinations of command options do not make | |
272 | sense on a particular target machine. You can define a macro | |
273 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
274 | defined, is executed once just after all the command options have | |
275 | been parsed. | |
276 | ||
277 | Don't use this macro to turn on various extra optimizations for | |
278 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
84ab3bfb | 279 | |
3d339ad2 RS |
280 | #define OVERRIDE_OPTIONS \ |
281 | { \ | |
9e62c7f2 | 282 | override_options(); \ |
3d339ad2 RS |
283 | if (! TARGET_68020 && flag_pic == 2) \ |
284 | error("-fPIC is not currently supported on the 68000 or 68010\n"); \ | |
2c8ec431 DL |
285 | if (TARGET_PCREL && flag_pic == 0) \ |
286 | flag_pic = 1; \ | |
cf9be6f0 | 287 | SUBTARGET_OVERRIDE_OPTIONS; \ |
3d339ad2 | 288 | } |
84ab3bfb | 289 | |
9e62c7f2 RK |
290 | /* These are meant to be redefined in the host dependent files */ |
291 | #define SUBTARGET_SWITCHES | |
292 | #define SUBTARGET_OPTIONS | |
84ab3bfb | 293 | #define SUBTARGET_OVERRIDE_OPTIONS |
3d339ad2 RS |
294 | \f |
295 | /* target machine storage layout */ | |
296 | ||
ba31d94e | 297 | /* Define for XFmode extended real floating point support. */ |
f6ba6a91 RS |
298 | #define LONG_DOUBLE_TYPE_SIZE 96 |
299 | ||
3d339ad2 RS |
300 | /* Define this if most significant bit is lowest numbered |
301 | in instructions that operate on numbered bit-fields. | |
302 | This is true for 68020 insns such as bfins and bfexts. | |
303 | We make it true always by avoiding using the single-bit insns | |
304 | except in special cases with constant bit numbers. */ | |
305 | #define BITS_BIG_ENDIAN 1 | |
306 | ||
307 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
308 | /* That is true on the 68000. */ | |
309 | #define BYTES_BIG_ENDIAN 1 | |
310 | ||
311 | /* Define this if most significant word of a multiword number is the lowest | |
312 | numbered. */ | |
313 | /* For 68000 we can decide arbitrarily | |
314 | since there are no machine instructions for them. | |
315 | So let's be consistent. */ | |
316 | #define WORDS_BIG_ENDIAN 1 | |
317 | ||
3d339ad2 RS |
318 | /* Width of a word, in units (bytes). */ |
319 | #define UNITS_PER_WORD 4 | |
320 | ||
3d339ad2 RS |
321 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
322 | #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) | |
323 | ||
324 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
325 | #define STACK_BOUNDARY 16 | |
326 | ||
327 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9e62c7f2 | 328 | #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3)) |
3d339ad2 RS |
329 | |
330 | /* Alignment of field after `int : 0' in a structure. */ | |
331 | #define EMPTY_FIELD_BOUNDARY 16 | |
332 | ||
dcd13066 RK |
333 | /* No data type wants to be aligned rounder than this. |
334 | Most published ABIs say that ints should be aligned on 16 bit | |
956d6950 JL |
335 | boundaries, but cpus with 32 bit busses get better performance |
336 | aligned on 32 bit boundaries. Coldfires without a misalignment | |
7a1929e1 | 337 | module require 32 bit alignment. */ |
dcd13066 | 338 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) |
3d339ad2 | 339 | |
b4ac57ab | 340 | /* Set this nonzero if move instructions will actually fail to work |
3d339ad2 | 341 | when given unaligned data. */ |
b71733d5 | 342 | #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) |
3d339ad2 | 343 | |
9e62c7f2 RK |
344 | /* Maximum power of 2 that code can be aligned to. */ |
345 | #define MAX_CODE_ALIGN 2 /* 4 byte alignment */ | |
346 | ||
347 | /* Align loop starts for optimal branching. */ | |
fc470718 | 348 | #define LOOP_ALIGN(LABEL) (m68k_align_loops) |
9e62c7f2 | 349 | |
7a1929e1 | 350 | /* This is how to align an instruction for optimal branching. */ |
fc470718 | 351 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps) |
9e62c7f2 | 352 | |
3d339ad2 RS |
353 | /* Define number of bits in most basic integer type. |
354 | (If undefined, default is BITS_PER_WORD). */ | |
355 | ||
356 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) | |
357 | ||
86702e31 ZW |
358 | /* Define these to avoid dependence on meaning of `int'. */ |
359 | ||
3d339ad2 RS |
360 | #define WCHAR_TYPE "long int" |
361 | #define WCHAR_TYPE_SIZE 32 | |
362 | \f | |
363 | /* Standard register usage. */ | |
364 | ||
365 | /* Number of actual hardware registers. | |
366 | The hardware registers are assigned numbers for the compiler | |
367 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
368 | All registers that the compiler knows about must be given numbers, | |
369 | even those that are not normally considered general registers. | |
370 | For the 68000, we give the data registers numbers 0-7, | |
371 | the address registers numbers 010-017, | |
372 | and the 68881 floating point registers numbers 020-027. */ | |
373 | #ifndef SUPPORT_SUN_FPA | |
374 | #define FIRST_PSEUDO_REGISTER 24 | |
375 | #else | |
376 | #define FIRST_PSEUDO_REGISTER 56 | |
377 | #endif | |
378 | ||
7a1929e1 | 379 | /* This defines the register which is used to hold the offset table for PIC. */ |
5b43fed1 | 380 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM) |
3d339ad2 | 381 | |
3d339ad2 RS |
382 | #ifndef SUPPORT_SUN_FPA |
383 | ||
384 | /* 1 for registers that have pervasive standard uses | |
385 | and are not available for the register allocator. | |
386 | On the 68000, only the stack pointer is such. */ | |
387 | ||
388 | #define FIXED_REGISTERS \ | |
389 | {/* Data registers. */ \ | |
390 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
391 | \ | |
392 | /* Address registers. */ \ | |
393 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
394 | \ | |
395 | /* Floating point registers \ | |
396 | (if available). */ \ | |
397 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
398 | ||
399 | /* 1 for registers not available across function calls. | |
400 | These must include the FIXED_REGISTERS and also any | |
401 | registers that can be used without being saved. | |
402 | The latter must include the registers where values are returned | |
403 | and the register where structure-value addresses are passed. | |
404 | Aside from that, you can include as many other registers as you like. */ | |
405 | #define CALL_USED_REGISTERS \ | |
406 | {1, 1, 0, 0, 0, 0, 0, 0, \ | |
407 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
408 | 1, 1, 0, 0, 0, 0, 0, 0 } | |
409 | ||
410 | #else /* SUPPORT_SUN_FPA */ | |
411 | ||
412 | /* 1 for registers that have pervasive standard uses | |
413 | and are not available for the register allocator. | |
414 | On the 68000, only the stack pointer is such. */ | |
415 | ||
956d6950 | 416 | /* fpa0 is also reserved so that it can be used to move data back and |
7a1929e1 | 417 | forth between high fpa regs and everything else. */ |
3d339ad2 RS |
418 | |
419 | #define FIXED_REGISTERS \ | |
420 | {/* Data registers. */ \ | |
421 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
422 | \ | |
423 | /* Address registers. */ \ | |
424 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
425 | \ | |
426 | /* Floating point registers \ | |
427 | (if available). */ \ | |
428 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
429 | \ | |
430 | /* Sun3 FPA registers. */ \ | |
431 | 1, 0, 0, 0, 0, 0, 0, 0, \ | |
432 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
433 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
434 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
435 | ||
436 | /* 1 for registers not available across function calls. | |
437 | These must include the FIXED_REGISTERS and also any | |
438 | registers that can be used without being saved. | |
439 | The latter must include the registers where values are returned | |
440 | and the register where structure-value addresses are passed. | |
441 | Aside from that, you can include as many other registers as you like. */ | |
442 | #define CALL_USED_REGISTERS \ | |
443 | {1, 1, 0, 0, 0, 0, 0, 0, \ | |
444 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
445 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
446 | /* FPA registers. */ \ | |
447 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
448 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
449 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
450 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
451 | ||
452 | #endif /* defined SUPPORT_SUN_FPA */ | |
453 | ||
454 | ||
455 | /* Make sure everything's fine if we *don't* have a given processor. | |
456 | This assumes that putting a register in fixed_regs will keep the | |
457 | compiler's mitts completely off it. We don't bother to zero it out | |
15a17b72 | 458 | of register classes. */ |
3d339ad2 | 459 | |
eb939872 | 460 | #ifdef SUPPORT_SUN_FPA |
3d339ad2 | 461 | |
5b43fed1 RH |
462 | #define CONDITIONAL_REGISTER_USAGE \ |
463 | { \ | |
464 | int i; \ | |
465 | HARD_REG_SET x; \ | |
466 | if (! TARGET_FPA) \ | |
467 | { \ | |
468 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ | |
469 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
470 | if (TEST_HARD_REG_BIT (x, i)) \ | |
471 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
472 | } \ | |
473 | if (! TARGET_68881) \ | |
474 | { \ | |
475 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ | |
476 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
477 | if (TEST_HARD_REG_BIT (x, i)) \ | |
478 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
479 | } \ | |
480 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ | |
481 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
482 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
44e3d967 JL |
483 | } |
484 | #else | |
5b43fed1 RH |
485 | #define CONDITIONAL_REGISTER_USAGE \ |
486 | { \ | |
487 | int i; \ | |
488 | HARD_REG_SET x; \ | |
489 | if (! TARGET_68881) \ | |
490 | { \ | |
491 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ | |
492 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
493 | if (TEST_HARD_REG_BIT (x, i)) \ | |
494 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
495 | } \ | |
496 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ | |
497 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
498 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
3d339ad2 RS |
499 | } |
500 | ||
501 | #endif /* defined SUPPORT_SUN_FPA */ | |
502 | ||
503 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
504 | to hold something of mode MODE. | |
505 | This is ordinarily the length in words of a value of mode MODE | |
506 | but can be less for certain modes in special long registers. | |
507 | ||
508 | On the 68000, ordinary registers hold 32 bits worth; | |
509 | for the 68881 registers, a single register is always enough for | |
510 | anything that can be stored in them at all. */ | |
511 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
512 | ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ | |
513 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
514 | ||
515 | #ifndef SUPPORT_SUN_FPA | |
516 | ||
517 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
518 | On the 68000, the cpu registers can hold any mode but the 68881 registers | |
15a17b72 | 519 | can hold only SFmode or DFmode. */ |
3d339ad2 RS |
520 | |
521 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
71380ac6 | 522 | (((REGNO) < 16 \ |
619aeb96 JW |
523 | && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \ |
524 | || ((REGNO) >= 16 && (REGNO) < 24 \ | |
3d339ad2 | 525 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
b621b712 AS |
526 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ |
527 | && GET_MODE_UNIT_SIZE (MODE) <= 12)) | |
3d339ad2 RS |
528 | |
529 | #else /* defined SUPPORT_SUN_FPA */ | |
530 | ||
531 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
532 | On the 68000, the cpu registers can hold any mode but the 68881 registers | |
15a17b72 | 533 | can hold only SFmode or DFmode. However, the Sun FPA register can |
3d339ad2 RS |
534 | (apparently) hold whatever you feel like putting in them. |
535 | If using the fpa, don't put a double in d7/a0. */ | |
536 | ||
619aeb96 JW |
537 | /* ??? This is confused. The check to prohibit d7/a0 overlaps should always |
538 | be enabled regardless of whether TARGET_FPA is specified. It isn't clear | |
539 | what the other d/a register checks are for. Every check using REGNO | |
540 | actually needs to use a range, e.g. 24>=X<56 not <56. There is probably | |
15a17b72 GK |
541 | no one using this code anymore. |
542 | This code used to be used to suppress register usage for the 68881 by | |
543 | saying that the 68881 registers couldn't hold values of any mode if there | |
544 | was no 68881. This was wrong, because reload (etc.) will still try | |
545 | to save and restore call-saved registers during, for instance, non-local | |
546 | goto. */ | |
3d339ad2 RS |
547 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
548 | (((REGNO) < 16 \ | |
549 | && !(TARGET_FPA \ | |
550 | && GET_MODE_CLASS ((MODE)) != MODE_INT \ | |
551 | && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ | |
552 | && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ | |
553 | && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ | |
15a17b72 GK |
554 | || ((REGNO) >= 16 && (REGNO) < 24 \ |
555 | ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
556 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
b621b712 AS |
557 | && GET_MODE_UNIT_SIZE (MODE) <= 12) \ |
558 | : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0))) | |
3d339ad2 RS |
559 | |
560 | #endif /* defined SUPPORT_SUN_FPA */ | |
561 | ||
562 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
563 | when one has mode MODE1 and one has mode MODE2. | |
564 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
565 | for any hard reg, then this must be 0 for correct output. */ | |
566 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
567 | (! TARGET_68881 \ | |
568 | || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
569 | || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
570 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
571 | || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) | |
572 | ||
573 | /* Specify the registers used for certain standard purposes. | |
574 | The values of these macros are register numbers. */ | |
575 | ||
576 | /* m68000 pc isn't overloaded on a register. */ | |
577 | /* #define PC_REGNUM */ | |
578 | ||
579 | /* Register to use for pushing function arguments. */ | |
580 | #define STACK_POINTER_REGNUM 15 | |
581 | ||
582 | /* Base register for access to local variables of the function. */ | |
583 | #define FRAME_POINTER_REGNUM 14 | |
584 | ||
585 | /* Value should be nonzero if functions must have frame pointers. | |
586 | Zero means the frame pointer need not be set up (and parms | |
587 | may be accessed via the stack pointer) in functions that seem suitable. | |
588 | This is computed in `reload', in reload1.c. */ | |
589 | #define FRAME_POINTER_REQUIRED 0 | |
590 | ||
591 | /* Base register for access to arguments of the function. */ | |
592 | #define ARG_POINTER_REGNUM 14 | |
593 | ||
594 | /* Register in which static-chain is passed to a function. */ | |
595 | #define STATIC_CHAIN_REGNUM 8 | |
596 | ||
597 | /* Register in which address to store a structure value | |
598 | is passed to a function. */ | |
599 | #define STRUCT_VALUE_REGNUM 9 | |
600 | \f | |
601 | /* Define the classes of registers for register constraints in the | |
602 | machine description. Also define ranges of constants. | |
603 | ||
604 | One of the classes must always be named ALL_REGS and include all hard regs. | |
605 | If there is more than one class, another class must be named NO_REGS | |
606 | and contain no registers. | |
607 | ||
608 | The name GENERAL_REGS must be the name of a class (or an alias for | |
609 | another name such as ALL_REGS). This is the class of registers | |
610 | that is allowed by "g" or "r" in a register constraint. | |
611 | Also, registers outside this class are allocated only when | |
612 | instructions express preferences for them. | |
613 | ||
614 | The classes must be numbered in nondecreasing order; that is, | |
615 | a larger-numbered class must never be contained completely | |
616 | in a smaller-numbered class. | |
617 | ||
618 | For any two classes, it is very desirable that there be another | |
619 | class that represents their union. */ | |
620 | ||
621 | /* The 68000 has three kinds of registers, so eight classes would be | |
622 | a complete set. One of them is not needed. */ | |
623 | ||
624 | #ifndef SUPPORT_SUN_FPA | |
625 | ||
626 | enum reg_class { | |
627 | NO_REGS, DATA_REGS, | |
628 | ADDR_REGS, FP_REGS, | |
629 | GENERAL_REGS, DATA_OR_FP_REGS, | |
630 | ADDR_OR_FP_REGS, ALL_REGS, | |
631 | LIM_REG_CLASSES }; | |
632 | ||
633 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
634 | ||
7a1929e1 | 635 | /* Give names of register classes as strings for dump file. */ |
3d339ad2 RS |
636 | |
637 | #define REG_CLASS_NAMES \ | |
638 | { "NO_REGS", "DATA_REGS", \ | |
639 | "ADDR_REGS", "FP_REGS", \ | |
640 | "GENERAL_REGS", "DATA_OR_FP_REGS", \ | |
641 | "ADDR_OR_FP_REGS", "ALL_REGS" } | |
642 | ||
643 | /* Define which registers fit in which classes. | |
644 | This is an initializer for a vector of HARD_REG_SET | |
645 | of length N_REG_CLASSES. */ | |
646 | ||
647 | #define REG_CLASS_CONTENTS \ | |
648 | { \ | |
7a87758d AS |
649 | {0x00000000}, /* NO_REGS */ \ |
650 | {0x000000ff}, /* DATA_REGS */ \ | |
651 | {0x0000ff00}, /* ADDR_REGS */ \ | |
652 | {0x00ff0000}, /* FP_REGS */ \ | |
653 | {0x0000ffff}, /* GENERAL_REGS */ \ | |
654 | {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ | |
655 | {0x00ffff00}, /* ADDR_OR_FP_REGS */ \ | |
656 | {0x00ffffff}, /* ALL_REGS */ \ | |
3d339ad2 RS |
657 | } |
658 | ||
659 | /* The same information, inverted: | |
660 | Return the class number of the smallest class containing | |
661 | reg number REGNO. This could be a conditional expression | |
662 | or could index an array. */ | |
663 | ||
664 | #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) | |
665 | ||
666 | #else /* defined SUPPORT_SUN_FPA */ | |
667 | ||
668 | /* | |
669 | * Notes on final choices: | |
670 | * | |
671 | * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything | |
672 | * else. | |
673 | * 2) Removed all unions that involve address registers with | |
674 | * floating point registers (left in unions of address and data with | |
675 | * floating point). | |
676 | * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. | |
677 | * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. | |
678 | * 4) Left in everything else. | |
679 | */ | |
680 | enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, | |
681 | FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, | |
682 | DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, | |
683 | GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, | |
684 | LIM_REG_CLASSES }; | |
685 | ||
686 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
687 | ||
7a1929e1 | 688 | /* Give names of register classes as strings for dump file. */ |
3d339ad2 RS |
689 | |
690 | #define REG_CLASS_NAMES \ | |
691 | { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ | |
692 | "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ | |
693 | "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ | |
694 | "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } | |
695 | ||
696 | /* Define which registers fit in which classes. | |
697 | This is an initializer for a vector of HARD_REG_SET | |
698 | of length N_REG_CLASSES. */ | |
699 | ||
700 | #define REG_CLASS_CONTENTS \ | |
701 | { \ | |
702 | {0, 0}, /* NO_REGS */ \ | |
703 | {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ | |
704 | {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ | |
705 | {0x00ff0000, 0x00000000}, /* FP_REGS */ \ | |
706 | {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ | |
707 | {0x000000ff, 0x00000000}, /* DATA_REGS */ \ | |
708 | {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ | |
709 | {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ | |
710 | {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ | |
711 | {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ | |
712 | {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ | |
713 | {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ | |
714 | {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ | |
715 | {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ | |
716 | } | |
717 | ||
718 | /* The same information, inverted: | |
719 | Return the class number of the smallest class containing | |
720 | reg number REGNO. This could be a conditional expression | |
721 | or could index an array. */ | |
722 | ||
0b5826ac | 723 | extern const enum reg_class regno_reg_class[]; |
3d339ad2 RS |
724 | #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) |
725 | ||
726 | #endif /* SUPPORT_SUN_FPA */ | |
727 | ||
728 | /* The class value for index registers, and the one for base regs. */ | |
729 | ||
730 | #define INDEX_REG_CLASS GENERAL_REGS | |
731 | #define BASE_REG_CLASS ADDR_REGS | |
732 | ||
733 | /* Get reg_class from a letter such as appears in the machine description. | |
734 | We do a trick here to modify the effective constraints on the | |
735 | machine description; we zorch the constraint letters that aren't | |
736 | appropriate for a specific target. This allows us to guarantee | |
737 | that a specific kind of register will not be used for a given target | |
7a1929e1 | 738 | without fiddling with the register classes above. */ |
3d339ad2 RS |
739 | |
740 | #ifndef SUPPORT_SUN_FPA | |
741 | ||
742 | #define REG_CLASS_FROM_LETTER(C) \ | |
743 | ((C) == 'a' ? ADDR_REGS : \ | |
744 | ((C) == 'd' ? DATA_REGS : \ | |
745 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
746 | NO_REGS) : \ | |
747 | NO_REGS))) | |
748 | ||
749 | #else /* defined SUPPORT_SUN_FPA */ | |
750 | ||
751 | #define REG_CLASS_FROM_LETTER(C) \ | |
752 | ((C) == 'a' ? ADDR_REGS : \ | |
753 | ((C) == 'd' ? DATA_REGS : \ | |
754 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
755 | NO_REGS) : \ | |
756 | ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ | |
757 | NO_REGS) : \ | |
758 | ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ | |
759 | NO_REGS) : \ | |
760 | NO_REGS))))) | |
761 | ||
762 | #endif /* defined SUPPORT_SUN_FPA */ | |
763 | ||
764 | /* The letters I, J, K, L and M in a register constraint string | |
765 | can be used to stand for particular ranges of immediate operands. | |
766 | This macro defines what the ranges are. | |
767 | C is the letter, and VALUE is a constant value. | |
768 | Return 1 if VALUE is in the range specified by C. | |
769 | ||
770 | For the 68000, `I' is used for the range 1 to 8 | |
771 | allowed as immediate shift counts and in addq. | |
772 | `J' is used for the range of signed numbers that fit in 16 bits. | |
773 | `K' is for numbers that moveq can't handle. | |
a9f6f5aa | 774 | `L' is for range -8 to -1, range of values that can be added with subq. |
d8fa884b RK |
775 | `M' is for numbers that moveq+notb can't handle. |
776 | 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. | |
777 | 'O' is for 16 (for rotate using swap). | |
778 | 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ | |
a9f6f5aa RK |
779 | |
780 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
781 | ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ | |
782 | (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ | |
783 | (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ | |
784 | (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ | |
68137318 | 785 | (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ |
d8fa884b RK |
786 | (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ |
787 | (C) == 'O' ? (VALUE) == 16 : \ | |
788 | (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) | |
3d339ad2 RS |
789 | |
790 | /* | |
791 | * A small bit of explanation: | |
792 | * "G" defines all of the floating constants that are *NOT* 68881 | |
793 | * constants. this is so 68881 constants get reloaded and the | |
794 | * fpmovecr is used. "H" defines *only* the class of constants that | |
795 | * the fpa can use, because these can be gotten at in any fpa | |
796 | * instruction and there is no need to force reloads. | |
797 | */ | |
798 | #ifndef SUPPORT_SUN_FPA | |
799 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
800 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) | |
801 | #else /* defined SUPPORT_SUN_FPA */ | |
802 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
803 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ | |
804 | (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) | |
805 | #endif /* defined SUPPORT_SUN_FPA */ | |
806 | ||
02385fc5 RK |
807 | /* A C expression that defines the optional machine-dependent constraint |
808 | letters that can be used to segregate specific types of operands, | |
809 | usually memory references, for the target machine. It should return 1 if | |
810 | VALUE corresponds to the operand type represented by the constraint letter | |
811 | C. If C is not defined as an extra constraint, the value returned should | |
812 | be 0 regardless of VALUE. */ | |
813 | ||
2c8ec431 DL |
814 | /* Letters in the range `Q' through `U' may be defined in a |
815 | machine-dependent fashion to stand for arbitrary operand types. | |
816 | The machine description macro `EXTRA_CONSTRAINT' is passed the | |
817 | operand as its first argument and the constraint letter as its | |
818 | second operand. | |
819 | ||
820 | `Q' means address register indirect addressing mode. | |
821 | `S' is for operands that satisfy 'm' when -mpcrel is in effect. | |
822 | `T' is for operands that satisfy 's' when -mpcrel is not in effect. */ | |
823 | ||
824 | #define EXTRA_CONSTRAINT(OP,CODE) \ | |
825 | (((CODE) == 'S') \ | |
826 | ? (TARGET_PCREL \ | |
827 | && GET_CODE (OP) == MEM \ | |
828 | && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
829 | || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ | |
830 | || GET_CODE (XEXP (OP, 0)) == CONST)) \ | |
831 | : \ | |
832 | (((CODE) == 'T') \ | |
833 | ? ( !TARGET_PCREL \ | |
834 | && (GET_CODE (OP) == SYMBOL_REF \ | |
835 | || GET_CODE (OP) == LABEL_REF \ | |
836 | || GET_CODE (OP) == CONST)) \ | |
837 | : \ | |
838 | (((CODE) == 'Q') \ | |
839 | ? (GET_CODE (OP) == MEM \ | |
840 | && GET_CODE (XEXP (OP, 0)) == REG) \ | |
841 | : \ | |
842 | 0))) | |
02385fc5 | 843 | |
3d339ad2 RS |
844 | /* Given an rtx X being reloaded into a reg required to be |
845 | in class CLASS, return the class of reg to actually use. | |
846 | In general this is just CLASS; but on some machines | |
847 | in some cases it is preferable to use a more restrictive class. | |
848 | On the 68000 series, use a data reg if possible when the | |
849 | value is a constant in the range where moveq could be used | |
9839cd62 | 850 | and we ensure that QImodes are reloaded into data regs. */ |
3d339ad2 RS |
851 | |
852 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
853 | ((GET_CODE (X) == CONST_INT \ | |
854 | && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ | |
855 | && (CLASS) != ADDR_REGS) \ | |
856 | ? DATA_REGS \ | |
857 | : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ | |
858 | ? DATA_REGS \ | |
9839cd62 RH |
859 | : (GET_CODE (X) == CONST_DOUBLE \ |
860 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
861 | ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ | |
862 | ? FP_REGS : NO_REGS) \ | |
2c8ec431 DL |
863 | : (TARGET_PCREL \ |
864 | && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
865 | || GET_CODE (X) == LABEL_REF)) \ | |
866 | ? ADDR_REGS \ | |
3d339ad2 RS |
867 | : (CLASS)) |
868 | ||
6c13d910 JW |
869 | /* Force QImode output reloads from subregs to be allocated to data regs, |
870 | since QImode stores from address regs are not supported. We make the | |
871 | assumption that if the class is not ADDR_REGS, then it must be a superset | |
872 | of DATA_REGS. */ | |
873 | ||
874 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
875 | (((MODE) == QImode && (CLASS) != ADDR_REGS) \ | |
876 | ? DATA_REGS \ | |
877 | : (CLASS)) | |
878 | ||
3d339ad2 RS |
879 | /* Return the maximum number of consecutive registers |
880 | needed to represent mode MODE in a register of class CLASS. */ | |
881 | /* On the 68000, this is the size of MODE in words, | |
882 | except in the FP regs, where a single reg is always enough. */ | |
883 | #ifndef SUPPORT_SUN_FPA | |
884 | ||
885 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
886 | ((CLASS) == FP_REGS ? 1 \ | |
887 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
888 | ||
889 | /* Moves between fp regs and other regs are two insns. */ | |
cf011243 | 890 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
3d339ad2 RS |
891 | (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ |
892 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
893 | ? 4 : 2) | |
894 | ||
895 | #else /* defined SUPPORT_SUN_FPA */ | |
896 | ||
897 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
898 | ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ | |
899 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
900 | ||
901 | /* Moves between fp regs and other regs are two insns. */ | |
902 | /* Likewise for high fpa regs and other regs. */ | |
cf011243 | 903 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
3d339ad2 RS |
904 | ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ |
905 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
906 | || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ | |
907 | || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ | |
908 | ? 4 : 2) | |
909 | ||
910 | #endif /* define SUPPORT_SUN_FPA */ | |
911 | \f | |
912 | /* Stack layout; function entry, exit and calling. */ | |
913 | ||
914 | /* Define this if pushing a word on the stack | |
915 | makes the stack pointer a smaller address. */ | |
916 | #define STACK_GROWS_DOWNWARD | |
917 | ||
918 | /* Nonzero if we need to generate stack-probe insns. | |
919 | On most systems they are not needed. | |
920 | When they are needed, define this as the stack offset to probe at. */ | |
921 | #define NEED_PROBE 0 | |
922 | ||
923 | /* Define this if the nominal address of the stack frame | |
924 | is at the high-address end of the local variables; | |
925 | that is, each additional local variable allocated | |
926 | goes at a more negative offset in the frame. */ | |
927 | #define FRAME_GROWS_DOWNWARD | |
928 | ||
929 | /* Offset within stack frame to start allocating local variables at. | |
930 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
931 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
932 | of the first local allocated. */ | |
933 | #define STARTING_FRAME_OFFSET 0 | |
934 | ||
935 | /* If we generate an insn to push BYTES bytes, | |
936 | this says how many the stack pointer really advances by. | |
6d808a73 JW |
937 | On the 68000, sp@- in a byte insn really pushes a word. |
938 | On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */ | |
939 | #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1) | |
3d339ad2 | 940 | |
7a1929e1 | 941 | /* We want to avoid trying to push bytes. */ |
d676911f DD |
942 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ |
943 | (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ | |
944 | && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200))) | |
945 | ||
3d339ad2 RS |
946 | /* Offset of first parameter from the argument pointer register value. */ |
947 | #define FIRST_PARM_OFFSET(FNDECL) 8 | |
948 | ||
949 | /* Value is the number of byte of arguments automatically | |
950 | popped when returning from a subroutine call. | |
8b109b37 | 951 | FUNDECL is the declaration node of the function (as a tree), |
3d339ad2 RS |
952 | FUNTYPE is the data type of the function (as a tree), |
953 | or for a library call it is an identifier node for the subroutine name. | |
954 | SIZE is the number of bytes of arguments passed on the stack. | |
955 | ||
956 | On the 68000, the RTS insn cannot pop anything. | |
957 | On the 68010, the RTD insn may be used to pop them if the number | |
958 | of args is fixed, but if the number is variable then the caller | |
959 | must pop them all. RTD can't be used for library calls now | |
960 | because the library is compiled with the Unix compiler. | |
961 | Use of RTD is a selectable option, since it is incompatible with | |
962 | standard Unix calling sequences. If the option is not selected, | |
963 | the caller must always pop the args. */ | |
964 | ||
8b109b37 | 965 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
2033a41a | 966 | ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ |
3d339ad2 RS |
967 | && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ |
968 | || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ | |
969 | == void_type_node))) \ | |
970 | ? (SIZE) : 0) | |
971 | ||
972 | /* Define how to find the value returned by a function. | |
973 | VALTYPE is the data type of the value (as a tree). | |
974 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
975 | otherwise, FUNC is 0. */ | |
976 | ||
977 | /* On the 68000 the return value is in D0 regardless. */ | |
978 | ||
979 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1d8eaa6b | 980 | gen_rtx_REG (TYPE_MODE (VALTYPE), 0) |
3d339ad2 RS |
981 | |
982 | /* Define how to find the value returned by a library function | |
983 | assuming the value has mode MODE. */ | |
984 | ||
985 | /* On the 68000 the return value is in D0 regardless. */ | |
986 | ||
1d8eaa6b | 987 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) |
3d339ad2 RS |
988 | |
989 | /* 1 if N is a possible register number for a function value. | |
990 | On the 68000, d0 is the only register thus used. */ | |
991 | ||
992 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
993 | ||
7972af82 TW |
994 | /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for |
995 | more than one register. */ | |
996 | ||
997 | #define NEEDS_UNTYPED_CALL 0 | |
998 | ||
3d339ad2 RS |
999 | /* Define this if PCC uses the nonreentrant convention for returning |
1000 | structure and union values. */ | |
1001 | ||
1002 | #define PCC_STATIC_STRUCT_RETURN | |
1003 | ||
1004 | /* 1 if N is a possible register number for function argument passing. | |
1005 | On the 68000, no registers are used in this way. */ | |
1006 | ||
1007 | #define FUNCTION_ARG_REGNO_P(N) 0 | |
1008 | \f | |
1009 | /* Define a data type for recording info about an argument list | |
1010 | during the scan of that argument list. This data type should | |
1011 | hold all necessary information about the function itself | |
1012 | and about the args processed so far, enough to enable macros | |
1013 | such as FUNCTION_ARG to determine where the next arg should go. | |
1014 | ||
1015 | On the m68k, this is a single integer, which is a number of bytes | |
1016 | of arguments scanned so far. */ | |
1017 | ||
1018 | #define CUMULATIVE_ARGS int | |
1019 | ||
1020 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1021 | for a call to a function whose data type is FNTYPE. | |
1022 | For a library call, FNTYPE is 0. | |
1023 | ||
1024 | On the m68k, the offset starts at 0. */ | |
1025 | ||
2c7ee1a6 | 1026 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
3d339ad2 RS |
1027 | ((CUM) = 0) |
1028 | ||
1029 | /* Update the data in CUM to advance over an argument | |
1030 | of mode MODE and data type TYPE. | |
1031 | (TYPE is null for libcalls where that information may not be available.) */ | |
1032 | ||
1033 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1034 | ((CUM) += ((MODE) != BLKmode \ | |
1035 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
1036 | : (int_size_in_bytes (TYPE) + 3) & ~3)) | |
1037 | ||
1038 | /* Define where to put the arguments to a function. | |
1039 | Value is zero to push the argument on the stack, | |
1040 | or a hard register in which to store the argument. | |
1041 | ||
1042 | MODE is the argument's machine mode. | |
1043 | TYPE is the data type of the argument (as a tree). | |
1044 | This is null for libcalls where that information may | |
1045 | not be available. | |
1046 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1047 | the preceding args and about the function being called. | |
1048 | NAMED is nonzero if this argument is a named parameter | |
1049 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1050 | ||
1051 | /* On the 68000 all args are pushed, except if -mregparm is specified | |
1052 | then the first two words of arguments are passed in d0, d1. | |
1053 | *NOTE* -mregparm does not work. | |
1054 | It exists only to test register calling conventions. */ | |
1055 | ||
1056 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1d8eaa6b | 1057 | ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0) |
3d339ad2 RS |
1058 | |
1059 | /* For an arg passed partly in registers and partly in memory, | |
1060 | this is the number of registers used. | |
1061 | For args passed entirely in registers or entirely in memory, zero. */ | |
1062 | ||
1063 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1064 | ((TARGET_REGPARM && (CUM) < 8 \ | |
1065 | && 8 < ((CUM) + ((MODE) == BLKmode \ | |
1066 | ? int_size_in_bytes (TYPE) \ | |
1067 | : GET_MODE_SIZE (MODE)))) \ | |
1068 | ? 2 - (CUM) / 4 : 0) | |
1069 | ||
3d339ad2 RS |
1070 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1071 | for profiling a function entry. */ | |
1072 | ||
1073 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1074 | asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) | |
1075 | ||
3d339ad2 RS |
1076 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1077 | the stack pointer does not matter. The value is tested only in | |
1078 | functions that have frame pointers. | |
1079 | No definition is equivalent to always zero. */ | |
1080 | ||
1081 | #define EXIT_IGNORE_STACK 1 | |
1082 | ||
3d339ad2 RS |
1083 | /* This is a hook for other tm files to change. */ |
1084 | /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ | |
1085 | ||
1086 | /* Determine if the epilogue should be output as RTL. | |
1087 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
1088 | #define USE_RETURN_INSN use_return_insn () | |
1089 | ||
1090 | /* Store in the variable DEPTH the initial difference between the | |
1091 | frame pointer reg contents and the stack pointer reg contents, | |
1092 | as of the start of the function body. This depends on the layout | |
1093 | of the fixed parts of the stack frame and on how registers are saved. | |
1094 | ||
1095 | On the 68k, if we have a frame, we must add one word to its length | |
1096 | to allow for the place that a6 is stored when we do have a frame pointer. | |
1097 | Otherwise, we would need to compute the offset from the frame pointer | |
1098 | of a local variable as a function of frame_pointer_needed, which | |
1099 | is hard. */ | |
1100 | ||
1101 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ | |
1102 | { int regno; \ | |
1103 | int offset = -4; \ | |
1104 | for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ | |
1105 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1106 | offset += 12; \ | |
1107 | for (regno = 0; regno < 16; regno++) \ | |
1108 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1109 | offset += 4; \ | |
d3f4f2d6 AS |
1110 | if (flag_pic && current_function_uses_pic_offset_table) \ |
1111 | offset += 4; \ | |
3d339ad2 RS |
1112 | (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ |
1113 | + (get_frame_size () == 0 ? 0 : 4)); \ | |
1114 | } | |
1115 | ||
1116 | /* Output assembler code for a block containing the constant parts | |
1117 | of a trampoline, leaving space for the variable parts. */ | |
1118 | ||
1119 | /* On the 68k, the trampoline looks like this: | |
27a55d6b RK |
1120 | movl #STATIC,a0 |
1121 | jmp FUNCTION | |
1122 | ||
1123 | WARNING: Targets that may run on 68040+ cpus must arrange for | |
1124 | the instruction cache to be flushed. Previous incarnations of | |
1125 | the m68k trampoline code attempted to get around this by either | |
1126 | using an out-of-line transfer function or pc-relative data, but | |
1127 | the fact remains that the code to jump to the transfer function | |
1128 | or the code to load the pc-relative data needs to be flushed | |
1129 | just as much as the "variable" portion of the trampoline. | |
1130 | Recognizing that a cache flush is going to be required anyway, | |
1131 | dispense with such notions and build a smaller trampoline. */ | |
1132 | ||
1133 | /* Since more instructions are required to move a template into | |
1134 | place than to create it on the spot, don't use a template. */ | |
3d339ad2 RS |
1135 | |
1136 | /* Length in units of the trampoline for entering a nested function. */ | |
1137 | ||
27a55d6b RK |
1138 | #define TRAMPOLINE_SIZE 12 |
1139 | ||
1140 | /* Alignment required for a trampoline in bits. */ | |
3d339ad2 | 1141 | |
27a55d6b | 1142 | #define TRAMPOLINE_ALIGNMENT 16 |
3d339ad2 | 1143 | |
27a55d6b RK |
1144 | /* Targets redefine this to invoke code to either flush the cache, |
1145 | or enable stack execution (or both). */ | |
1146 | ||
1147 | #ifndef FINALIZE_TRAMPOLINE | |
1148 | #define FINALIZE_TRAMPOLINE(TRAMP) | |
1149 | #endif | |
3d339ad2 RS |
1150 | |
1151 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1152 | FNADDR is an RTX for the address of the function's pure code. | |
c85f7c16 JL |
1153 | CXT is an RTX for the static chain value for the function. |
1154 | ||
1155 | We generate a two-instructions program at address TRAMP : | |
1156 | movea.l &CXT,%a0 | |
1157 | jmp FNADDR */ | |
3d339ad2 RS |
1158 | |
1159 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1160 | { \ | |
1d8eaa6b AS |
1161 | emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ |
1162 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ | |
1163 | emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ | |
27a55d6b | 1164 | GEN_INT(0x4EF9)); \ |
1d8eaa6b | 1165 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ |
27a55d6b | 1166 | FINALIZE_TRAMPOLINE(TRAMP); \ |
3d339ad2 RS |
1167 | } |
1168 | ||
1169 | /* This is the library routine that is used | |
1170 | to transfer control from the trampoline | |
e73cbb04 RK |
1171 | to the actual nested function. |
1172 | It is defined for backward compatibility, | |
1173 | for linking with object code that used the old | |
1174 | trampoline definition. */ | |
3d339ad2 RS |
1175 | |
1176 | /* A colon is used with no explicit operands | |
1177 | to cause the template string to be scanned for %-constructs. */ | |
1178 | /* The function name __transfer_from_trampoline is not actually used. | |
1179 | The function definition just permits use of "asm with operands" | |
1180 | (though the operand list is empty). */ | |
1181 | #define TRANSFER_FROM_TRAMPOLINE \ | |
1182 | void \ | |
1183 | __transfer_from_trampoline () \ | |
1184 | { \ | |
1185 | register char *a0 asm ("%a0"); \ | |
016c8440 | 1186 | asm (GLOBAL_ASM_OP "___trampoline"); \ |
3d339ad2 | 1187 | asm ("___trampoline:"); \ |
338818c7 RK |
1188 | asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ |
1189 | asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ | |
3d339ad2 RS |
1190 | asm ("rts":); \ |
1191 | } | |
1192 | \f | |
1193 | /* Addressing modes, and classification of registers for them. */ | |
1194 | ||
940da324 JL |
1195 | #define HAVE_POST_INCREMENT 1 |
1196 | /* #define HAVE_POST_DECREMENT 0 */ | |
3d339ad2 | 1197 | |
940da324 JL |
1198 | #define HAVE_PRE_DECREMENT 1 |
1199 | /* #define HAVE_PRE_INCREMENT 0 */ | |
3d339ad2 RS |
1200 | |
1201 | /* Macros to check register numbers against specific register classes. */ | |
1202 | ||
1203 | /* These assume that REGNO is a hard or pseudo reg number. | |
1204 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1205 | or a pseudo reg currently allocated to a suitable hard reg. | |
1206 | Since they use reg_renumber, they are safe only once reg_renumber | |
1207 | has been allocated, which happens in local-alloc.c. */ | |
1208 | ||
1209 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1210 | ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) | |
1211 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1212 | (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) | |
1213 | #define REGNO_OK_FOR_DATA_P(REGNO) \ | |
1214 | ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
1215 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1216 | (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) | |
1217 | #ifdef SUPPORT_SUN_FPA | |
1218 | #define REGNO_OK_FOR_FPA_P(REGNO) \ | |
1219 | (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) | |
1220 | #endif | |
1221 | ||
1222 | /* Now macros that check whether X is a register and also, | |
1223 | strictly, whether it is in a specified class. | |
1224 | ||
1225 | These macros are specific to the 68000, and may be used only | |
1226 | in code for printing assembler insns and in conditions for | |
1227 | define_optimization. */ | |
1228 | ||
1229 | /* 1 if X is a data register. */ | |
1230 | ||
1231 | #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) | |
1232 | ||
1233 | /* 1 if X is an fp register. */ | |
1234 | ||
1235 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1236 | ||
1237 | /* 1 if X is an address register */ | |
1238 | ||
1239 | #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1240 | ||
1241 | #ifdef SUPPORT_SUN_FPA | |
1242 | /* 1 if X is a register in the Sun FPA. */ | |
1243 | #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) | |
1244 | #else | |
1245 | /* Answer must be no if we don't have an FPA. */ | |
1246 | #define FPA_REG_P(X) 0 | |
1247 | #endif | |
1248 | \f | |
1249 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1250 | ||
1251 | #define MAX_REGS_PER_ADDRESS 2 | |
1252 | ||
1253 | /* Recognize any constant value that is a valid address. */ | |
1254 | ||
6eff269e BK |
1255 | #define CONSTANT_ADDRESS_P(X) \ |
1256 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1257 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1258 | || GET_CODE (X) == HIGH) | |
3d339ad2 RS |
1259 | |
1260 | /* Nonzero if the constant value X is a legitimate general operand. | |
1261 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1262 | ||
1263 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1264 | ||
1265 | /* Nonzero if the constant value X is a legitimate general operand | |
1266 | when generating PIC code. It is given that flag_pic is on and | |
2c8ec431 DL |
1267 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. |
1268 | ||
1269 | PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are | |
1270 | accepted by insn predicates, but which would otherwise fail the | |
1271 | `general_operand' test. */ | |
1272 | ||
1273 | #ifndef REG_OK_STRICT | |
1274 | #define PCREL_GENERAL_OPERAND_OK 0 | |
1275 | #else | |
1276 | #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) | |
1277 | #endif | |
3d339ad2 RS |
1278 | |
1279 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
c57eee67 | 1280 | ((! symbolic_operand (X, VOIDmode) \ |
03f54026 RK |
1281 | && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \ |
1282 | && GET_CODE (mem_for_const_double (X)) == MEM \ | |
1283 | && symbolic_operand (XEXP (mem_for_const_double (X), 0), \ | |
1284 | VOIDmode))) \ | |
1285 | || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ | |
2c8ec431 | 1286 | || PCREL_GENERAL_OPERAND_OK) |
3d339ad2 RS |
1287 | |
1288 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1289 | and check its validity for a certain class. | |
1290 | We have two alternate definitions for each of them. | |
1291 | The usual definition accepts all pseudo regs; the other rejects | |
1292 | them unless they have been allocated suitable hard regs. | |
1293 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1294 | ||
1295 | Most source files want to accept pseudo regs in the hope that | |
1296 | they will get allocated to the class that the insn wants them to be in. | |
1297 | Source files for reload pass need to be strict. | |
1298 | After reload, it makes no difference, since pseudo regs have | |
1299 | been eliminated by then. */ | |
1300 | ||
1301 | #ifndef REG_OK_STRICT | |
1302 | ||
1303 | /* Nonzero if X is a hard reg that can be used as an index | |
1304 | or if it is a pseudo reg. */ | |
1305 | #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) | |
1306 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1307 | or if it is a pseudo reg. */ | |
1308 | #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) | |
1309 | ||
1310 | #else | |
1311 | ||
1312 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1313 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1314 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1315 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1316 | ||
1317 | #endif | |
1318 | \f | |
1319 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1320 | that is a valid memory address for an instruction. | |
1321 | The MODE argument is the machine mode for the MEM expression | |
1322 | that wants to use this address. | |
1323 | ||
1324 | When generating PIC, an address involving a SYMBOL_REF is legitimate | |
1325 | if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. | |
1326 | We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, | |
1327 | and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. | |
1328 | ||
1329 | Likewise for a LABEL_REF when generating PIC. | |
1330 | ||
1331 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
1332 | ||
22291e2f JW |
1333 | /* Allow SUBREG everywhere we allow REG. This results in better code. It |
1334 | also makes function inlining work when inline functions are called with | |
1335 | arguments that are SUBREGs. */ | |
1336 | ||
1337 | #define LEGITIMATE_BASE_REG_P(X) \ | |
1338 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1339 | || (GET_CODE (X) == SUBREG \ | |
1340 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1341 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1342 | ||
3d339ad2 RS |
1343 | #define INDIRECTABLE_1_ADDRESS_P(X) \ |
1344 | ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ | |
22291e2f | 1345 | || LEGITIMATE_BASE_REG_P (X) \ |
3d339ad2 | 1346 | || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ |
22291e2f | 1347 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ |
3d339ad2 | 1348 | || (GET_CODE (X) == PLUS \ |
22291e2f | 1349 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ |
3d339ad2 | 1350 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ |
8b83b2a7 PJ |
1351 | && (TARGET_68020 \ |
1352 | || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ | |
3d339ad2 RS |
1353 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ |
1354 | && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ | |
1355 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ | |
2c8ec431 | 1356 | && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) |
3d339ad2 | 1357 | |
3d339ad2 RS |
1358 | #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ |
1359 | { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } | |
1360 | ||
875c5a31 RS |
1361 | /* Only labels on dispatch tables are valid for indexing from. */ |
1362 | #define GO_IF_INDEXABLE_BASE(X, ADDR) \ | |
1363 | { rtx temp; \ | |
1364 | if (GET_CODE (X) == LABEL_REF \ | |
1365 | && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ | |
1366 | && GET_CODE (temp) == JUMP_INSN \ | |
1367 | && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ | |
1368 | || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ | |
1369 | goto ADDR; \ | |
22291e2f | 1370 | if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } |
3d339ad2 RS |
1371 | |
1372 | #define GO_IF_INDEXING(X, ADDR) \ | |
1373 | { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ | |
1374 | { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ | |
1375 | if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ | |
1376 | { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } | |
1377 | ||
1378 | #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ | |
1379 | { GO_IF_INDEXING (X, ADDR); \ | |
1380 | if (GET_CODE (X) == PLUS) \ | |
1381 | { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
9cf3ae46 | 1382 | && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ |
3d339ad2 RS |
1383 | { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ |
1384 | if (GET_CODE (XEXP (X, 0)) == CONST_INT \ | |
9cf3ae46 | 1385 | && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ |
3d339ad2 RS |
1386 | { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } |
1387 | ||
03db53b1 | 1388 | /* coldfire/5200 does not allow HImode index registers. */ |
3d339ad2 RS |
1389 | #define LEGITIMATE_INDEX_REG_P(X) \ |
1390 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
03db53b1 JW |
1391 | || (! TARGET_5200 \ |
1392 | && GET_CODE (X) == SIGN_EXTEND \ | |
3d339ad2 RS |
1393 | && GET_CODE (XEXP (X, 0)) == REG \ |
1394 | && GET_MODE (XEXP (X, 0)) == HImode \ | |
22291e2f JW |
1395 | && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
1396 | || (GET_CODE (X) == SUBREG \ | |
1397 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1398 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
3d339ad2 RS |
1399 | |
1400 | #define LEGITIMATE_INDEX_P(X) \ | |
1401 | (LEGITIMATE_INDEX_REG_P (X) \ | |
106bee4b | 1402 | || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \ |
3d339ad2 RS |
1403 | && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ |
1404 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1405 | && (INTVAL (XEXP (X, 1)) == 2 \ | |
1406 | || INTVAL (XEXP (X, 1)) == 4 \ | |
1c4e4dc4 | 1407 | || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200)))) |
3d339ad2 | 1408 | |
04e61bd4 RS |
1409 | /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ |
1410 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1411 | { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ | |
1412 | GO_IF_INDEXED_ADDRESS (X, ADDR); \ | |
1413 | if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ | |
1414 | && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ | |
1415 | && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ | |
1416 | goto ADDR; } | |
1417 | ||
1418 | /* Don't call memory_address_noforce for the address to fetch | |
1419 | the switch offset. This address is ok as it stands (see above), | |
1420 | but memory_address_noforce would alter it. */ | |
1421 | #define PIC_CASE_VECTOR_ADDRESS(index) index | |
3d339ad2 RS |
1422 | \f |
1423 | /* Try machine-dependent ways of modifying an illegitimate address | |
1424 | to be legitimate. If we find one, return the new, valid address. | |
1425 | This macro is used in only one place: `memory_address' in explow.c. | |
1426 | ||
1427 | OLDX is the address as it was before break_out_memory_refs was called. | |
1428 | In some cases it is useful to look at this to decide what needs to be done. | |
1429 | ||
1430 | MODE and WIN are passed so that this macro can use | |
1431 | GO_IF_LEGITIMATE_ADDRESS. | |
1432 | ||
1433 | It is always safe for this macro to do nothing. It exists to recognize | |
1434 | opportunities to optimize the output. | |
1435 | ||
1436 | For the 68000, we handle X+REG by loading X into a register R and | |
1437 | using R+REG. R will go in an address reg and indexing will be used. | |
1438 | However, if REG is a broken-out memory address or multiplication, | |
1439 | nothing needs to be done because REG can certainly go in an address reg. */ | |
1440 | ||
1441 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } | |
1442 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1443 | { register int ch = (X) != (OLDX); \ | |
1444 | if (GET_CODE (X) == PLUS) \ | |
1445 | { int copied = 0; \ | |
1446 | if (GET_CODE (XEXP (X, 0)) == MULT) \ | |
1447 | { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ | |
1448 | if (GET_CODE (XEXP (X, 1)) == MULT) \ | |
1449 | { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ | |
1450 | if (ch && GET_CODE (XEXP (X, 1)) == REG \ | |
1451 | && GET_CODE (XEXP (X, 0)) == REG) \ | |
1452 | goto WIN; \ | |
1453 | if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ | |
1454 | if (GET_CODE (XEXP (X, 0)) == REG \ | |
1455 | || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ | |
1456 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1457 | && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ | |
1458 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1459 | register rtx val = force_operand (XEXP (X, 1), 0); \ | |
1460 | emit_move_insn (temp, val); \ | |
1461 | COPY_ONCE (X); \ | |
1462 | XEXP (X, 1) = temp; \ | |
1463 | goto WIN; } \ | |
1464 | else if (GET_CODE (XEXP (X, 1)) == REG \ | |
1465 | || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ | |
1466 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ | |
1467 | && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ | |
1468 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1469 | register rtx val = force_operand (XEXP (X, 0), 0); \ | |
1470 | emit_move_insn (temp, val); \ | |
1471 | COPY_ONCE (X); \ | |
1472 | XEXP (X, 0) = temp; \ | |
1473 | goto WIN; }}} | |
1474 | ||
1475 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1476 | has an effect that depends on the machine mode it is used for. | |
1477 | On the 68000, only predecrement and postincrement address depend thus | |
1478 | (the amount of decrement or increment being the length of the operand). */ | |
1479 | ||
1480 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1481 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL | |
1482 | \f | |
1483 | /* Specify the machine mode that this machine uses | |
1484 | for the index in the tablejump instruction. */ | |
1485 | #define CASE_VECTOR_MODE HImode | |
1486 | ||
18543a22 ILT |
1487 | /* Define as C expression which evaluates to nonzero if the tablejump |
1488 | instruction expects the table to contain offsets from the address of the | |
1489 | table. | |
7a1929e1 | 1490 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1491 | #define CASE_VECTOR_PC_RELATIVE 1 |
3d339ad2 | 1492 | |
3d339ad2 RS |
1493 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1494 | #define DEFAULT_SIGNED_CHAR 1 | |
1495 | ||
1496 | /* Don't cse the address of the function being compiled. */ | |
1497 | #define NO_RECURSIVE_FUNCTION_CSE | |
1498 | ||
1499 | /* Max number of bytes we can move from memory to memory | |
1500 | in one reasonably fast instruction. */ | |
1501 | #define MOVE_MAX 4 | |
1502 | ||
3d339ad2 RS |
1503 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
1504 | #define SLOW_BYTE_ACCESS 0 | |
1505 | ||
3d339ad2 RS |
1506 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1507 | is done just by pretending it is already truncated. */ | |
1508 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1509 | ||
1510 | /* We assume that the store-condition-codes instructions store 0 for false | |
1511 | and some other value for true. This is the value stored for true. */ | |
1512 | ||
37941398 | 1513 | #define STORE_FLAG_VALUE (-1) |
3d339ad2 RS |
1514 | |
1515 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
cb560352 | 1516 | #define PROMOTE_PROTOTYPES 1 |
3d339ad2 RS |
1517 | |
1518 | /* Specify the machine mode that pointers have. | |
1519 | After generation of rtl, the compiler makes no further distinction | |
1520 | between pointers and any other objects of this machine mode. */ | |
1521 | #define Pmode SImode | |
1522 | ||
1523 | /* A function address in a call instruction | |
1524 | is a byte address (for indexing purposes) | |
1525 | so give the MEM rtx a byte's mode. */ | |
1526 | #define FUNCTION_MODE QImode | |
1527 | ||
1528 | /* Compute the cost of computing a constant rtl expression RTX | |
1529 | whose rtx-code is CODE. The body of this macro is a portion | |
1530 | of a switch statement. If the code is computed here, | |
1531 | return it with a return statement. Otherwise, break from the switch. */ | |
1532 | ||
3bb22aee | 1533 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
3d339ad2 RS |
1534 | case CONST_INT: \ |
1535 | /* Constant zero is super cheap due to clr instruction. */ \ | |
1536 | if (RTX == const0_rtx) return 0; \ | |
8dbda09a RK |
1537 | /* if ((OUTER_CODE) == SET) */ \ |
1538 | return const_int_cost(RTX); \ | |
3d339ad2 RS |
1539 | case CONST: \ |
1540 | case LABEL_REF: \ | |
1541 | case SYMBOL_REF: \ | |
1542 | return 3; \ | |
1543 | case CONST_DOUBLE: \ | |
31d0dd4f JL |
1544 | /* Make 0.0 cheaper than other floating constants to \ |
1545 | encourage creating tstsf and tstdf insns. */ \ | |
1546 | if ((OUTER_CODE) == COMPARE \ | |
1547 | && ((RTX) == CONST0_RTX (SFmode) \ | |
1548 | || (RTX) == CONST0_RTX (DFmode))) \ | |
1549 | return 4; \ | |
3d339ad2 RS |
1550 | return 5; |
1551 | ||
1552 | /* Compute the cost of various arithmetic operations. | |
1553 | These are vaguely right for a 68020. */ | |
1554 | /* The costs for long multiply have been adjusted to | |
1555 | work properly in synth_mult on the 68020, | |
1556 | relative to an average of the time for add and the time for shift, | |
1557 | taking away a little more because sometimes move insns are needed. */ | |
3296aff4 | 1558 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ |
7a13fe96 RK |
1559 | #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13) |
1560 | #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5) | |
3296aff4 | 1561 | #define DIVW_COST (TARGET_68020 ? 27 : 12) |
3d339ad2 | 1562 | |
3bb22aee | 1563 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
3d339ad2 RS |
1564 | case PLUS: \ |
1565 | /* An lea costs about three times as much as a simple add. */ \ | |
1566 | if (GET_MODE (X) == SImode \ | |
8df73827 TG |
1567 | && GET_CODE (XEXP (X, 1)) == REG \ |
1568 | && GET_CODE (XEXP (X, 0)) == MULT \ | |
1569 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1570 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1571 | && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \ | |
1572 | || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \ | |
1573 | || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \ | |
3d339ad2 RS |
1574 | return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ |
1575 | break; \ | |
1576 | case ASHIFT: \ | |
1577 | case ASHIFTRT: \ | |
7a13fe96 RK |
1578 | case LSHIFTRT: \ |
1579 | if (TARGET_68060) \ | |
1580 | return COSTS_N_INSNS(1); \ | |
3296aff4 TG |
1581 | if (! TARGET_68020) \ |
1582 | { \ | |
1583 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1584 | { \ | |
1585 | if (INTVAL (XEXP (X, 1)) < 16) \ | |
1586 | return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \ | |
1587 | else \ | |
1588 | /* We're using clrw + swap for these cases. */ \ | |
bd2e6d53 | 1589 | return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \ |
3296aff4 TG |
1590 | } \ |
1591 | return COSTS_N_INSNS (10); /* worst case */ \ | |
1592 | } \ | |
3d339ad2 | 1593 | /* A shift by a big integer takes an extra instruction. */ \ |
b4ac57ab RS |
1594 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1595 | && (INTVAL (XEXP (X, 1)) == 16)) \ | |
1596 | return COSTS_N_INSNS (2); /* clrw;swap */ \ | |
3d339ad2 RS |
1597 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1598 | && !(INTVAL (XEXP (X, 1)) > 0 \ | |
1599 | && INTVAL (XEXP (X, 1)) <= 8)) \ | |
1600 | return COSTS_N_INSNS (3); /* lsr #i,dn */ \ | |
1601 | break; \ | |
1602 | case MULT: \ | |
3296aff4 TG |
1603 | if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \ |
1604 | || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \ | |
1605 | && GET_MODE (X) == SImode) \ | |
1606 | return COSTS_N_INSNS (MULW_COST); \ | |
5d195441 | 1607 | if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ |
9fd3fbd0 | 1608 | return COSTS_N_INSNS (MULW_COST); \ |
3d339ad2 | 1609 | else \ |
9fd3fbd0 | 1610 | return COSTS_N_INSNS (MULL_COST); \ |
3d339ad2 RS |
1611 | case DIV: \ |
1612 | case UDIV: \ | |
1613 | case MOD: \ | |
1614 | case UMOD: \ | |
1615 | if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ | |
3296aff4 | 1616 | return COSTS_N_INSNS (DIVW_COST); /* div.w */ \ |
3d339ad2 RS |
1617 | return COSTS_N_INSNS (43); /* div.l */ |
1618 | \f | |
1619 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1620 | ||
1621 | /* Here we define machine-dependent flags and fields in cc_status | |
1622 | (see `conditions.h'). */ | |
1623 | ||
1624 | /* Set if the cc value is actually in the 68881, so a floating point | |
1625 | conditional branch must be output. */ | |
1626 | #define CC_IN_68881 04000 | |
1627 | ||
1628 | /* Store in cc_status the expressions that the condition codes will | |
1629 | describe after execution of an instruction whose pattern is EXP. | |
1630 | Do not alter them if the instruction would not alter the cc's. */ | |
1631 | ||
1632 | /* On the 68000, all the insns to store in an address register fail to | |
1633 | set the cc's. However, in some cases these instructions can make it | |
1634 | possibly invalid to use the saved cc's. In those cases we clear out | |
1635 | some or all of the saved cc's so they won't be used. */ | |
1636 | ||
1637 | #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) | |
1638 | ||
1639 | #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ | |
1640 | { if (cc_prev_status.flags & CC_IN_68881) \ | |
1641 | return FLOAT; \ | |
1642 | if (cc_prev_status.flags & CC_NO_OVERFLOW) \ | |
1643 | return NO_OV; \ | |
1644 | return NORMAL; } | |
1645 | \f | |
1646 | /* Control the assembler format that we output. */ | |
1647 | ||
1648 | /* Output at beginning of assembler file. */ | |
1649 | ||
1650 | #define ASM_FILE_START(FILE) \ | |
1651 | fprintf (FILE, "#NO_APP\n"); | |
1652 | ||
1653 | /* Output to assembler file text saying following lines | |
1654 | may contain character constants, extra white space, comments, etc. */ | |
1655 | ||
1656 | #define ASM_APP_ON "#APP\n" | |
1657 | ||
1658 | /* Output to assembler file text saying following lines | |
1659 | no longer contain unusual constructs. */ | |
1660 | ||
1661 | #define ASM_APP_OFF "#NO_APP\n" | |
1662 | ||
1663 | /* Output before read-only data. */ | |
1664 | ||
6e7b07a7 | 1665 | #define TEXT_SECTION_ASM_OP "\t.text" |
3d339ad2 RS |
1666 | |
1667 | /* Output before writable data. */ | |
1668 | ||
6e7b07a7 | 1669 | #define DATA_SECTION_ASM_OP "\t.data" |
3d339ad2 RS |
1670 | |
1671 | /* Here are four prefixes that are used by asm_fprintf to | |
1672 | facilitate customization for alternate assembler syntaxes. | |
1673 | Machines with no likelihood of an alternate syntax need not | |
1674 | define these and need not use asm_fprintf. */ | |
1675 | ||
1676 | /* The prefix for register names. Note that REGISTER_NAMES | |
1677 | is supposed to include this prefix. */ | |
1678 | ||
1679 | #define REGISTER_PREFIX "" | |
1680 | ||
1681 | /* The prefix for local labels. You should be able to define this as | |
1682 | an empty string, or any arbitrary string (such as ".", ".L%", etc) | |
1683 | without having to make any other changes to account for the specific | |
1684 | definition. Note it is a string literal, not interpreted by printf | |
7a1929e1 | 1685 | and friends. */ |
3d339ad2 RS |
1686 | |
1687 | #define LOCAL_LABEL_PREFIX "" | |
1688 | ||
1689 | /* The prefix to add to user-visible assembler symbols. */ | |
1690 | ||
1691 | #define USER_LABEL_PREFIX "_" | |
1692 | ||
1693 | /* The prefix for immediate operands. */ | |
1694 | ||
1695 | #define IMMEDIATE_PREFIX "#" | |
1696 | ||
1697 | /* How to refer to registers in assembler output. | |
1698 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1699 | ||
1700 | #ifndef SUPPORT_SUN_FPA | |
1701 | ||
1702 | #define REGISTER_NAMES \ | |
1703 | {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ | |
1704 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ | |
1705 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } | |
1706 | ||
1707 | #else /* SUPPORTED_SUN_FPA */ | |
1708 | ||
1709 | #define REGISTER_NAMES \ | |
1710 | {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ | |
1711 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ | |
1712 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ | |
1713 | "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ | |
1714 | "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ | |
1715 | "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ | |
1716 | "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } | |
1717 | ||
1718 | #endif /* defined SUPPORT_SUN_FPA */ | |
1719 | ||
1720 | /* How to renumber registers for dbx and gdb. | |
1721 | On the Sun-3, the floating point registers have numbers | |
1722 | 18 to 25, not 16 to 23 as they do in the compiler. */ | |
1723 | ||
1724 | #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) | |
1725 | ||
078e983e AS |
1726 | /* Before the prologue, RA is at 0(%sp). */ |
1727 | #define INCOMING_RETURN_ADDR_RTX \ | |
1d8eaa6b | 1728 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
078e983e AS |
1729 | |
1730 | /* We must not use the DBX register numbers for the DWARF 2 CFA column | |
1731 | numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
1732 | Instead use the identity mapping. */ | |
1733 | #define DWARF_FRAME_REGNUM(REG) REG | |
1734 | ||
1735 | /* Before the prologue, the top of the frame is at 4(%sp). */ | |
1736 | #define INCOMING_FRAME_SP_OFFSET 4 | |
1737 | ||
3d339ad2 RS |
1738 | /* This is how to output the definition of a user-level label named NAME, |
1739 | such as the label on a static function or variable NAME. */ | |
1740 | ||
1741 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1742 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1743 | ||
1744 | /* This is how to output a command to make the user-level label named NAME | |
1745 | defined for reference from other files. */ | |
1746 | ||
6e7b07a7 | 1747 | #define GLOBAL_ASM_OP "\t.globl\t" |
3d339ad2 | 1748 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ |
016c8440 | 1749 | do { fprintf (FILE, "%s", GLOBAL_ASM_OP); \ |
9fd3fbd0 RS |
1750 | assemble_name (FILE, NAME); \ |
1751 | fputs ("\n", FILE);} while (0) | |
3d339ad2 RS |
1752 | |
1753 | /* This is how to output a reference to a user-level label named NAME. | |
1754 | `assemble_name' uses this. */ | |
1755 | ||
1756 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
338818c7 | 1757 | asm_fprintf (FILE, "%0U%s", NAME) |
3d339ad2 RS |
1758 | |
1759 | /* This is how to output an internal numbered label where | |
1760 | PREFIX is the class of label and NUM is the number within the class. */ | |
1761 | ||
1762 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
338818c7 | 1763 | asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) |
3d339ad2 RS |
1764 | |
1765 | /* This is how to store into the string LABEL | |
1766 | the symbol_ref name of an internal numbered label where | |
1767 | PREFIX is the class of label and NUM is the number within the class. | |
1768 | This is suitable for output with `assemble_name'. */ | |
1769 | ||
1770 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
e59f7d3d | 1771 | sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) |
3d339ad2 | 1772 | |
3d339ad2 RS |
1773 | /* This is how to output an insn to push a register on the stack. |
1774 | It need not be very fast code. */ | |
1775 | ||
1776 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1777 | asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) | |
1778 | ||
1779 | /* This is how to output an insn to pop a register from the stack. | |
1780 | It need not be very fast code. */ | |
1781 | ||
1782 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1783 | asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) | |
1784 | ||
1785 | /* This is how to output an element of a case-vector that is absolute. | |
1786 | (The 68000 does not use such vectors, | |
1787 | but we must define this macro anyway.) */ | |
1788 | ||
1789 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1790 | asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) | |
1791 | ||
1792 | /* This is how to output an element of a case-vector that is relative. */ | |
1793 | ||
33f7f353 | 1794 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3d339ad2 RS |
1795 | asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) |
1796 | ||
1797 | /* This is how to output an assembler line | |
1798 | that says to advance the location counter | |
1799 | to a multiple of 2**LOG bytes. */ | |
1800 | ||
b4ac57ab RS |
1801 | /* We don't have a way to align to more than a two-byte boundary, so do the |
1802 | best we can and don't complain. */ | |
3d339ad2 | 1803 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
b4ac57ab RS |
1804 | if ((LOG) >= 1) \ |
1805 | fprintf (FILE, "\t.even\n"); | |
3d339ad2 RS |
1806 | |
1807 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1808 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
1809 | ||
1810 | /* This says how to output an assembler line | |
1811 | to define a global common symbol. */ | |
1812 | ||
1813 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1814 | ( fputs (".comm ", (FILE)), \ | |
1815 | assemble_name ((FILE), (NAME)), \ | |
1816 | fprintf ((FILE), ",%u\n", (ROUNDED))) | |
1817 | ||
1818 | /* This says how to output an assembler line | |
1819 | to define a local common symbol. */ | |
1820 | ||
1821 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1822 | ( fputs (".lcomm ", (FILE)), \ | |
1823 | assemble_name ((FILE), (NAME)), \ | |
1824 | fprintf ((FILE), ",%u\n", (ROUNDED))) | |
1825 | ||
1826 | /* Store in OUTPUT a string (made with alloca) containing | |
1827 | an assembler-name for a local static variable named NAME. | |
1828 | LABELNO is an integer which is different for each call. */ | |
1829 | ||
1830 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1831 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1832 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1833 | ||
3d339ad2 RS |
1834 | /* Output a float value (represented as a C double) as an immediate operand. |
1835 | This macro is a 68k-specific macro. */ | |
f6ba6a91 RS |
1836 | |
1837 | #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ | |
1838 | do { \ | |
1839 | if (CODE == 'f') \ | |
1840 | { \ | |
1841 | char dstr[30]; \ | |
1842 | REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ | |
1843 | asm_fprintf ((FILE), "%I0r%s", dstr); \ | |
1844 | } \ | |
1845 | else \ | |
1846 | { \ | |
1847 | long l; \ | |
1848 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
97b57a81 | 1849 | asm_fprintf ((FILE), "%I0x%lx", l); \ |
f6ba6a91 RS |
1850 | } \ |
1851 | } while (0) | |
3d339ad2 RS |
1852 | |
1853 | /* Output a double value (represented as a C double) as an immediate operand. | |
1854 | This macro is a 68k-specific macro. */ | |
1855 | #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ | |
f6ba6a91 RS |
1856 | do { char dstr[30]; \ |
1857 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
1858 | asm_fprintf (FILE, "%I0r%s", dstr); \ | |
1859 | } while (0) | |
1860 | ||
1861 | /* Note, long double immediate operands are not actually | |
1862 | generated by m68k.md. */ | |
1863 | #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ | |
1864 | do { char dstr[30]; \ | |
1865 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
1866 | asm_fprintf (FILE, "%I0r%s", dstr); \ | |
1867 | } while (0) | |
3d339ad2 RS |
1868 | |
1869 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1870 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1871 | For `%' followed by punctuation, CODE is the punctuation and X is null. | |
1872 | ||
1873 | On the 68000, we use several CODE characters: | |
1874 | '.' for dot needed in Motorola-style opcode names. | |
1875 | '-' for an operand pushing on the stack: | |
1876 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
1877 | '+' for an operand pushing on the stack: | |
1878 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
1879 | '@' for a reference to the top word on the stack: | |
1880 | sp@, (sp) or (%sp) depending on the style of syntax. | |
1881 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
1882 | but & in SGS syntax). | |
7c129456 | 1883 | '!' for the fpcr register (used in some float-to-fixed conversions). |
3d339ad2 RS |
1884 | '$' for the letter `s' in an op code, but only on the 68040. |
1885 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 1886 | '/' for register prefix needed by longlong.h. |
3d339ad2 RS |
1887 | |
1888 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
1889 | 'd' to force memory addressing to be absolute, not relative. | |
1890 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
2c8ec431 DL |
1891 | 'o' for operands to go directly to output_operand_address (bypassing |
1892 | print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) | |
3d339ad2 RS |
1893 | 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather |
1894 | than directly). Second part of 'y' below. | |
1895 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), | |
1896 | or print pair of registers as rx:ry. | |
1897 | 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs | |
1898 | CONST_DOUBLE's as SunFPA constant RAM registers if | |
7a1929e1 | 1899 | possible, so it should not be used except for the SunFPA. */ |
3d339ad2 RS |
1900 | |
1901 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
1902 | ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ | |
1903 | || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ | |
2ac5f14a | 1904 | || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') |
3d339ad2 | 1905 | |
3d339ad2 RS |
1906 | /* A C compound statement to output to stdio stream STREAM the |
1907 | assembler syntax for an instruction operand X. X is an RTL | |
1908 | expression. | |
1909 | ||
1910 | CODE is a value that can be used to specify one of several ways | |
1911 | of printing the operand. It is used when identical operands | |
1912 | must be printed differently depending on the context. CODE | |
1913 | comes from the `%' specification that was used to request | |
1914 | printing of the operand. If the specification was just `%DIGIT' | |
1915 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
1916 | is the ASCII code for LTR. | |
1917 | ||
1918 | If X is a register, this macro should print the register's name. | |
1919 | The names can be found in an array `reg_names' whose type is | |
1920 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
1921 | ||
1922 | When the machine description has a specification `%PUNCT' (a `%' | |
1923 | followed by a punctuation character), this macro is called with | |
1924 | a null pointer for X and the punctuation character for CODE. | |
1925 | ||
1926 | See m68k.c for the m68k specific codes. */ | |
1927 | ||
1928 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1929 | ||
1930 | /* A C compound statement to output to stdio stream STREAM the | |
1931 | assembler syntax for an instruction operand that is a memory | |
1932 | reference whose address is ADDR. ADDR is an RTL expression. | |
1933 | ||
1934 | On some machines, the syntax for a symbolic address depends on | |
1935 | the section that the address refers to. On these machines, | |
1936 | define the macro `ENCODE_SECTION_INFO' to store the information | |
1937 | into the `symbol_ref', and then check for it here. */ | |
1938 | ||
1939 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
1940 | ||
9e62c7f2 | 1941 | /* Variables in m68k.c */ |
577c6ece AS |
1942 | extern const char *m68k_align_loops_string; |
1943 | extern const char *m68k_align_jumps_string; | |
1944 | extern const char *m68k_align_funcs_string; | |
9e62c7f2 RK |
1945 | extern int m68k_align_loops; |
1946 | extern int m68k_align_jumps; | |
1947 | extern int m68k_align_funcs; | |
2b3600ac | 1948 | extern int m68k_last_compare_had_fp_operands; |
9e62c7f2 | 1949 | |
3d339ad2 RS |
1950 | \f |
1951 | /* | |
1952 | Local variables: | |
1953 | version-control: t | |
1954 | End: | |
1955 | */ |