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9c532fac | 1 | ;;- Machine description for GNU compiler, Motorola 68000 Version |
f1717362 | 2 | ;; Copyright (C) 1987-2016 Free Software Foundation, Inc. |
c1dbe9ae | 3 | |
187b36cf | 4 | ;; This file is part of GCC. |
c1dbe9ae | 5 | |
187b36cf | 6 | ;; GCC is free software; you can redistribute it and/or modify |
c1dbe9ae | 7 | ;; it under the terms of the GNU General Public License as published by |
038d1e19 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
c1dbe9ae | 9 | ;; any later version. |
10 | ||
187b36cf | 11 | ;; GCC is distributed in the hope that it will be useful, |
c1dbe9ae | 12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ||
16 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
c1dbe9ae | 19 | |
c1f64c40 | 20 | ;;- Information about MCF5200 port. |
21 | ||
22 | ;;- The MCF5200 "ColdFire" architecture is a reduced version of the | |
23 | ;;- 68k ISA. Differences include reduced support for byte and word | |
24 | ;;- operands and the removal of BCD, bitfield, rotate, and integer | |
960e6739 | 25 | ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the |
c1f64c40 | 26 | ;;- removed opcodes and addressing modes off. |
27 | ;;- | |
28 | ||
c1dbe9ae | 29 | |
30 | ;;- instruction definitions | |
31 | ||
32 | ;;- @@The original PO technology requires these to be ordered by speed, | |
33 | ;;- @@ so that assigner will pick the fastest. | |
34 | ||
35 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
36 | ||
37 | ;;- When naming insn's (operand 0 of define_insn) be careful about using | |
38 | ;;- names from other targets machine descriptions. | |
39 | ||
40 | ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code | |
41 | ;;- updates for most instructions. | |
42 | ||
43 | ;;- Operand classes for the register allocator: | |
44 | ;;- 'a' one of the address registers can be used. | |
45 | ;;- 'd' one of the data registers can be used. | |
58c23110 | 46 | ;;- 'f' one of the m68881/fpu registers can be used |
c1dbe9ae | 47 | ;;- 'r' either a data or an address register can be used. |
c1dbe9ae | 48 | |
49 | ;;- Immediate Floating point operator constraints | |
50 | ;;- 'G' a floating point constant that is *NOT* one of the standard | |
51 | ;; 68881 constant values (to force calling output_move_const_double | |
52 | ;; to get it from rom if it is a 68881 constant). | |
c1dbe9ae | 53 | ;; |
54 | ;; See the functions standard_XXX_constant_p in output-m68k.c for more | |
55 | ;; info. | |
56 | ||
57 | ;;- Immediate integer operand constraints: | |
58 | ;;- 'I' 1 .. 8 | |
59 | ;;- 'J' -32768 .. 32767 | |
60 | ;;- 'K' all integers EXCEPT -128 .. 127 | |
61 | ;;- 'L' -8 .. -1 | |
b2142e18 | 62 | ;;- 'M' all integers EXCEPT -256 .. 255 |
c68c8763 | 63 | ;;- 'N' 24 .. 31 |
64 | ;;- 'O' 16 | |
65 | ;;- 'P' 8 .. 15 | |
c1dbe9ae | 66 | |
67 | ;;- Assembler specs: | |
68 | ;;- "%." size separator ("." or "") move%.l d0,d1 | |
c1dbe9ae | 69 | ;;- "%-" push operand "sp@-" move%.l d0,%- |
70 | ;;- "%+" pop operand "sp@+" move%.l d0,%+ | |
71 | ;;- "%@" top of stack "sp@" move%.l d0,%@ | |
1d6c8988 | 72 | ;;- "%!" fpcr register |
c1dbe9ae | 73 | ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1 |
74 | ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1 | |
75 | ||
76 | ;;- Information about 68040 port. | |
77 | ||
78 | ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must | |
79 | ;;- be emulated in software by the OS. It is faster to avoid these | |
80 | ;;- instructions and issue a library call rather than trapping into | |
81 | ;;- the kernel. The affected instructions are fintrz and fscale. The | |
bd40163f | 82 | ;;- TUNE_68040 flag turns the use of the opcodes off. |
c1dbe9ae | 83 | |
84 | ;;- The '040 also implements a set of new floating-point instructions | |
85 | ;;- which specify the rounding precision in the opcode. This finally | |
86 | ;;- permit the 68k series to be truly IEEE compliant, and solves all | |
87 | ;;- issues of excess precision accumulating in the extended registers. | |
88 | ;;- By default, GCC does not use these instructions, since such code will | |
89 | ;;- not run on an '030. To use these instructions, use the -m68040-only | |
f84195ec | 90 | ;;- switch. |
c1dbe9ae | 91 | |
92 | ;;- These new instructions aren't directly in the md. They are brought | |
93 | ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather | |
94 | ;;- than "". | |
95 | ||
9f2ac74a | 96 | ;;- Information about 68060 port. |
97 | ||
98 | ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must | |
3f6dfb87 | 99 | ;;- be emulated in software by the OS. It is faster to avoid these |
100 | ;;- instructions and issue a library call rather than trapping into | |
9f2ac74a | 101 | ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq; |
aa076a66 | 102 | ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and |
bd40163f | 103 | ;;- fscale. The TUNE_68060 flag turns the use of the opcodes off. |
9f2ac74a | 104 | |
c1dbe9ae | 105 | ;;- Some of these insn's are composites of several m68000 op codes. |
106 | ;;- The assembler (or final @@??) insures that the appropriate one is | |
107 | ;;- selected. | |
104e421a | 108 | |
109 | ;; UNSPEC usage: | |
110 | ||
111 | (define_constants | |
9c47decb | 112 | [(UNSPEC_SIN 1) |
113 | (UNSPEC_COS 2) | |
114 | (UNSPEC_GOT 3) | |
1d86aeab | 115 | (UNSPEC_IB 4) |
3c904dda | 116 | (UNSPEC_TIE 5) |
869bde6b | 117 | (UNSPEC_RELOC16 6) |
118 | (UNSPEC_RELOC32 7) | |
104e421a | 119 | ]) |
120 | ||
121 | ;; UNSPEC_VOLATILE usage: | |
122 | ||
123 | (define_constants | |
124 | [(UNSPECV_BLOCKAGE 0) | |
ee2d89e9 | 125 | (UNSPECV_CAS_1 1) |
126 | (UNSPECV_CAS_2 2) | |
127 | (UNSPECV_TAS_1 3) | |
128 | (UNSPECV_TAS_2 4) | |
104e421a | 129 | ]) |
f5f2db69 | 130 | |
131 | ;; Registers by name. | |
132 | (define_constants | |
2d329930 | 133 | [(D0_REG 0) |
134 | (A0_REG 8) | |
9c47decb | 135 | (A1_REG 9) |
136 | (PIC_REG 13) | |
47313d14 | 137 | (A6_REG 14) |
f5f2db69 | 138 | (SP_REG 15) |
9c47decb | 139 | (FP0_REG 16) |
f5f2db69 | 140 | ]) |
5e3eb9c7 | 141 | |
142 | (include "predicates.md") | |
584f29ac | 143 | (include "constraints.md") |
c1dbe9ae | 144 | \f |
1d86aeab | 145 | ;; :::::::::::::::::::: |
146 | ;; :: | |
147 | ;; :: Attributes | |
148 | ;; :: | |
149 | ;; :::::::::::::::::::: | |
150 | ||
151 | ;; Processor type. | |
3c904dda | 152 | (define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown" |
2ccdedfd | 153 | (const (symbol_ref "m68k_sched_cpu"))) |
154 | ||
155 | ;; MAC type. | |
156 | (define_attr "mac" "no, cf_mac, cf_emac" | |
157 | (const (symbol_ref "m68k_sched_mac"))) | |
1d86aeab | 158 | |
1d86aeab | 159 | ;; Instruction type for use in scheduling description. |
160 | ;; _l and _w suffixes indicate size of the operands of instruction. | |
161 | ;; alu - usual arithmetic or logic instruction. | |
1d86aeab | 162 | ;; aluq - arithmetic or logic instruction which has a quick immediate (the one |
163 | ;; that is encoded in the instruction word) for its Y operand. | |
3c904dda | 164 | ;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx). |
165 | ;; bcc - conditional branch. | |
166 | ;; bitr - bit operation that only updates flags. | |
167 | ;; bitrw - bit operation that updates flags and output operand. | |
168 | ;; bra, bsr, clr, cmp, div, ext - corresponding instruction. | |
169 | ;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding | |
170 | ;; instruction. | |
171 | ;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction | |
172 | ;; buffer. | |
173 | ;; ignore - fake instruction. | |
174 | ;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction. | |
175 | ;; mvsz - mvs or mvz instruction. | |
176 | ;; neg, nop, pea, rts, scc - corresponding instruction. | |
177 | ;; shift - arithmetic or logical shift instruction. | |
178 | ;; trap, tst, unlk - corresponding instruction. | |
179 | (define_attr "type" | |
180 | "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l, | |
181 | div_w,div_l,ext, | |
182 | falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst, | |
183 | ib,ignore, | |
184 | jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop, | |
185 | pea,rts,scc,shift, | |
186 | trap,tst,tst_l,unlk, | |
1d86aeab | 187 | unknown" |
3c904dda | 188 | (const_string "unknown")) |
1d86aeab | 189 | |
190 | ;; Index of the X or Y operand in recog_data.operand[]. | |
191 | ;; Should be used only within opx_type and opy_type. | |
192 | (define_attr "opx" "" (const_int 0)) | |
193 | (define_attr "opy" "" (const_int 1)) | |
194 | ||
1d86aeab | 195 | ;; Type of the Y operand. |
196 | ;; See m68k.c: enum attr_op_type. | |
197 | (define_attr "opy_type" | |
3c904dda | 198 | "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l" |
199 | (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore, | |
200 | jmp,jsr,nop,rts,scc,trap,tst,tst_l, | |
201 | unlk,unknown") (const_string "none") | |
202 | (eq_attr "type" "lea,pea") | |
1d86aeab | 203 | (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")] |
204 | (symbol_ref "m68k_sched_attr_opy_type (insn, 0)"))) | |
205 | ||
3c904dda | 206 | ;; Type of the X operand. |
207 | ;; See m68k.c: enum attr_op_type. | |
208 | (define_attr "opx_type" | |
209 | "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l" | |
210 | (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk, | |
211 | unknown") (const_string "none") | |
212 | (eq_attr "type" "pea") (const_string "mem1") | |
213 | (eq_attr "type" "jmp,jsr") | |
214 | (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")] | |
215 | (symbol_ref "m68k_sched_attr_opx_type (insn, 0)"))) | |
1d86aeab | 216 | |
217 | ;; Access to the X operand: none, read, write, read/write, unknown. | |
218 | ;; Access to the Y operand is either none (if opy_type is none) | |
219 | ;; or read otherwise. | |
3c904dda | 220 | (define_attr "opx_access" "none, r, w, rw" |
221 | (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk, | |
222 | unknown") (const_string "none") | |
223 | (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst, | |
224 | jmp,jsr,tst,tst_l") (const_string "r") | |
225 | (eq_attr "type" "clr,clr_l,fneg,fmove,lea, | |
226 | mov3q_l,move,move_l,moveq_l,mvsz, | |
227 | pea,scc") (const_string "w") | |
228 | (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext, | |
229 | falu,fdiv,fmul,fsqrt,link,mul_w,mul_l, | |
230 | neg_l,shift") (const_string "rw")] | |
231 | ;; Should never be used. | |
232 | (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)"))) | |
1d86aeab | 233 | |
234 | ;; Memory accesses of the insn. | |
235 | ;; 00 - no memory references | |
236 | ;; 10 - memory is read | |
3c904dda | 237 | ;; i0 - indexed memory is read |
1d86aeab | 238 | ;; 01 - memory is written |
3c904dda | 239 | ;; 0i - indexed memory is written |
1d86aeab | 240 | ;; 11 - memory is read, memory is written |
3c904dda | 241 | ;; i1 - indexed memory is read, memory is written |
242 | ;; 1i - memory is read, indexed memory is written | |
243 | (define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i" | |
1d86aeab | 244 | (symbol_ref "m68k_sched_attr_op_mem (insn)")) |
245 | ||
3c904dda | 246 | ;; Instruction size in words. |
247 | (define_attr "size" "1,2,3" | |
248 | (symbol_ref "m68k_sched_attr_size (insn)")) | |
249 | ||
06817dd5 | 250 | ;; Alternative is OK for ColdFire. |
251 | (define_attr "ok_for_coldfire" "yes,no" (const_string "yes")) | |
252 | ||
253 | ;; Define 'enabled' attribute. | |
254 | (define_attr "enabled" "" | |
10adf167 | 255 | (cond [(and (match_test "TARGET_COLDFIRE") |
06817dd5 | 256 | (eq_attr "ok_for_coldfire" "no")) |
257 | (const_int 0)] | |
258 | (const_int 1))) | |
1d86aeab | 259 | \f |
ee2d89e9 | 260 | ;; Mode macros for integer operations. |
261 | (define_mode_iterator I [QI HI SI]) | |
262 | (define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")]) | |
263 | ||
58c23110 | 264 | ;; Mode macros for floating point operations. |
265 | ;; Valid floating point modes | |
fd781bb2 | 266 | (define_mode_iterator FP [SF DF (XF "TARGET_68881")]) |
58c23110 | 267 | ;; Mnemonic infix to round result |
268 | (define_mode_attr round [(SF "%$") (DF "%&") (XF "")]) | |
269 | ;; Mnemonic infix to round result for mul or div instruction | |
270 | (define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")]) | |
334ec2d8 | 271 | ;; Suffix specifying source operand format |
58c23110 | 272 | (define_mode_attr prec [(SF "s") (DF "d") (XF "x")]) |
273 | ;; Allowable D registers | |
274 | (define_mode_attr dreg [(SF "d") (DF "") (XF "")]) | |
275 | ;; Allowable 68881 constant constraints | |
276 | (define_mode_attr const [(SF "F") (DF "G") (XF "")]) | |
277 | \f | |
1d86aeab | 278 | |
279 | (define_insn_and_split "*movdf_internal" | |
280 | [(set (match_operand:DF 0 "push_operand" "=m, m") | |
281 | (match_operand:DF 1 "general_operand" "f, ro<>E"))] | |
c1dbe9ae | 282 | "" |
1d86aeab | 283 | "@ |
284 | fmove%.d %f1,%0 | |
285 | #" | |
286 | "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 1)" | |
287 | [(const_int 0)] | |
c1dbe9ae | 288 | { |
1d86aeab | 289 | m68k_emit_move_double (operands); |
290 | DONE; | |
291 | } | |
3c904dda | 292 | [(set_attr "type" "fmove,*")]) |
c1dbe9ae | 293 | |
1d86aeab | 294 | (define_insn_and_split "pushdi" |
c1dbe9ae | 295 | [(set (match_operand:DI 0 "push_operand" "=m") |
22f6d4d0 | 296 | (match_operand:DI 1 "general_operand" "ro<>Fi"))] |
c1dbe9ae | 297 | "" |
1d86aeab | 298 | "#" |
299 | "&& reload_completed" | |
300 | [(const_int 0)] | |
c1dbe9ae | 301 | { |
1d86aeab | 302 | m68k_emit_move_double (operands); |
303 | DONE; | |
2de9355b | 304 | }) |
c1dbe9ae | 305 | \f |
306 | ;; We don't want to allow a constant operand for test insns because | |
307 | ;; (set (cc0) (const_int foo)) has no mode information. Such insns will | |
308 | ;; be folded while optimizing anyway. | |
d08c9ad7 | 309 | |
74f4459c | 310 | (define_insn "tstdi" |
d08c9ad7 | 311 | [(set (cc0) |
74f4459c | 312 | (compare (match_operand:DI 0 "nonimmediate_operand" "am,d") |
313 | (const_int 0))) | |
3f6dfb87 | 314 | (clobber (match_scratch:SI 1 "=X,d")) |
315 | (clobber (match_scratch:DI 2 "=d,X"))] | |
d08c9ad7 | 316 | "" |
d08c9ad7 | 317 | { |
3f6dfb87 | 318 | if (which_alternative == 0) |
319 | { | |
320 | rtx xoperands[2]; | |
321 | ||
322 | xoperands[0] = operands[2]; | |
323 | xoperands[1] = operands[0]; | |
324 | output_move_double (xoperands); | |
1d86aeab | 325 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 326 | return "neg%.l %R2\;negx%.l %2"; |
3f6dfb87 | 327 | } |
328 | if (find_reg_note (insn, REG_DEAD, operands[0])) | |
329 | { | |
1d86aeab | 330 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 331 | return "neg%.l %R0\;negx%.l %0"; |
3f6dfb87 | 332 | } |
333 | else | |
334 | /* | |
2de9355b | 335 | 'sub' clears %1, and also clears the X cc bit |
336 | 'tst' sets the Z cc bit according to the low part of the DImode operand | |
337 | 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part. | |
3f6dfb87 | 338 | */ |
2de9355b | 339 | return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0"; |
340 | }) | |
d08c9ad7 | 341 | |
1d86aeab | 342 | ;; If you think that the 68020 does not support tstl a0, |
343 | ;; reread page B-167 of the 68020 manual more carefully. | |
344 | (define_insn "*tstsi_internal_68020_cf" | |
c1dbe9ae | 345 | [(set (cc0) |
74f4459c | 346 | (compare (match_operand:SI 0 "nonimmediate_operand" "rm") |
347 | (const_int 0)))] | |
1d86aeab | 348 | "TARGET_68020 || TARGET_COLDFIRE" |
349 | "tst%.l %0" | |
350 | [(set_attr "type" "tst_l")]) | |
351 | ||
352 | ;; On an address reg, cmpw may replace cmpl. | |
353 | (define_insn "*tstsi_internal" | |
354 | [(set (cc0) | |
74f4459c | 355 | (compare (match_operand:SI 0 "nonimmediate_operand" "dm,r") |
356 | (const_int 0)))] | |
1d86aeab | 357 | "!(TARGET_68020 || TARGET_COLDFIRE)" |
358 | "@ | |
359 | tst%.l %0 | |
360 | cmp%.w #0,%0" | |
3c904dda | 361 | [(set_attr "type" "tst_l,cmp")]) |
c1dbe9ae | 362 | |
363 | ;; This can't use an address register, because comparisons | |
364 | ;; with address registers as second operand always test the whole word. | |
1d86aeab | 365 | (define_insn "*tsthi_internal" |
c1dbe9ae | 366 | [(set (cc0) |
74f4459c | 367 | (compare (match_operand:HI 0 "nonimmediate_operand" "dm") |
368 | (const_int 0)))] | |
c1dbe9ae | 369 | "" |
1d86aeab | 370 | "tst%.w %0" |
3c904dda | 371 | [(set_attr "type" "tst")]) |
c1dbe9ae | 372 | |
1d86aeab | 373 | (define_insn "*tstqi_internal" |
c1dbe9ae | 374 | [(set (cc0) |
74f4459c | 375 | (compare (match_operand:QI 0 "nonimmediate_operand" "dm") |
376 | (const_int 0)))] | |
c1dbe9ae | 377 | "" |
1d86aeab | 378 | "tst%.b %0" |
3c904dda | 379 | [(set_attr "type" "tst")]) |
3f6dfb87 | 380 | |
58c23110 | 381 | (define_insn "tst<mode>_68881" |
c1dbe9ae | 382 | [(set (cc0) |
74f4459c | 383 | (compare (match_operand:FP 0 "general_operand" "f<FP:dreg>m") |
384 | (match_operand:FP 1 "const0_operand" "H")))] | |
c1dbe9ae | 385 | "TARGET_68881" |
c1dbe9ae | 386 | { |
387 | cc_status.flags = CC_IN_68881; | |
388 | if (FP_REG_P (operands[0])) | |
2de9355b | 389 | return "ftst%.x %0"; |
58c23110 | 390 | return "ftst%.<FP:prec> %0"; |
3c904dda | 391 | } |
392 | [(set_attr "type" "ftst")]) | |
c1dbe9ae | 393 | |
58c23110 | 394 | (define_insn "tst<mode>_cf" |
c1dbe9ae | 395 | [(set (cc0) |
74f4459c | 396 | (compare (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U") |
397 | (match_operand:FP 1 "const0_operand" "H")))] | |
58c23110 | 398 | "TARGET_COLDFIRE_FPU" |
c1dbe9ae | 399 | { |
400 | cc_status.flags = CC_IN_68881; | |
401 | if (FP_REG_P (operands[0])) | |
58c23110 | 402 | return "ftst%.d %0"; |
403 | return "ftst%.<FP:prec> %0"; | |
1d86aeab | 404 | } |
405 | [(set_attr "type" "ftst")]) | |
58c23110 | 406 | |
c1dbe9ae | 407 | \f |
408 | ;; compare instructions. | |
409 | ||
74f4459c | 410 | (define_insn "*cmpdi_internal" |
411 | [(set (cc0) | |
412 | (compare (match_operand:DI 1 "nonimmediate_operand" "0,d") | |
413 | (match_operand:DI 2 "general_operand" "d,0"))) | |
414 | (clobber (match_scratch:DI 0 "=d,d"))] | |
d08c9ad7 | 415 | "" |
d08c9ad7 | 416 | { |
aa86686b | 417 | if (rtx_equal_p (operands[0], operands[1])) |
2de9355b | 418 | return "sub%.l %R2,%R0\;subx%.l %2,%0"; |
d08c9ad7 | 419 | else |
aa86686b | 420 | { |
1d86aeab | 421 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 422 | return "sub%.l %R1,%R0\;subx%.l %1,%0"; |
aa86686b | 423 | } |
2de9355b | 424 | }) |
d08c9ad7 | 425 | |
74f4459c | 426 | (define_insn "cmpdi" |
427 | [(set (cc0) | |
428 | (compare (match_operand:DI 0 "nonimmediate_operand") | |
429 | (match_operand:DI 1 "general_operand"))) | |
430 | (clobber (match_scratch:DI 2))] | |
431 | "" | |
432 | "") | |
433 | ||
434 | ||
435 | (define_expand "cbranchdi4" | |
436 | [(set (pc) | |
437 | (if_then_else (match_operator 0 "ordered_comparison_operator" | |
438 | [(match_operand:DI 1 "nonimmediate_operand") | |
439 | (match_operand:DI 2 "general_operand")]) | |
440 | (label_ref (match_operand 3 "")) | |
441 | (pc)))] | |
ee128251 | 442 | "" |
ee128251 | 443 | { |
74f4459c | 444 | if (operands[2] == const0_rtx) |
445 | emit_insn (gen_tstdi (operands[1])); | |
446 | else | |
447 | emit_insn (gen_cmpdi (operands[1], operands[2])); | |
448 | operands[1] = cc0_rtx; | |
449 | operands[2] = const0_rtx; | |
450 | }) | |
451 | ||
452 | (define_expand "cstoredi4" | |
453 | [(set (match_operand:QI 0 "register_operand") | |
454 | (match_operator:QI 1 "ordered_comparison_operator" | |
455 | [(match_operand:DI 2 "nonimmediate_operand") | |
456 | (match_operand:DI 3 "general_operand")]))] | |
457 | "" | |
458 | { | |
459 | if (operands[3] == const0_rtx) | |
460 | emit_insn (gen_tstdi (operands[2])); | |
461 | else | |
462 | emit_insn (gen_cmpdi (operands[2], operands[3])); | |
463 | operands[2] = cc0_rtx; | |
464 | operands[3] = const0_rtx; | |
f5f2db69 | 465 | }) |
ee128251 | 466 | |
74f4459c | 467 | |
468 | (define_expand "cbranchsi4" | |
469 | [(set (cc0) | |
470 | (compare (match_operand:SI 1 "nonimmediate_operand" "") | |
471 | (match_operand:SI 2 "general_operand" ""))) | |
472 | (set (pc) | |
473 | (if_then_else (match_operator 0 "ordered_comparison_operator" | |
474 | [(cc0) (const_int 0)]) | |
475 | (label_ref (match_operand 3 "")) | |
476 | (pc)))] | |
477 | "" | |
478 | "") | |
479 | ||
480 | (define_expand "cstoresi4" | |
481 | [(set (cc0) | |
482 | (compare (match_operand:SI 2 "nonimmediate_operand" "") | |
483 | (match_operand:SI 3 "general_operand" ""))) | |
484 | (set (match_operand:QI 0 "register_operand") | |
485 | (match_operator:QI 1 "ordered_comparison_operator" | |
486 | [(cc0) (const_int 0)]))] | |
487 | "" | |
488 | "") | |
489 | ||
490 | ||
00474a72 | 491 | ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes. |
9ba76f64 | 492 | ;; |
493 | ;; In theory we ought to be able to use some 'S' constraints and | |
494 | ;; operand predicates that allow PC-rel addressing modes in the | |
495 | ;; comparison patterns and expanders below. But we would have to be | |
496 | ;; cognizant of the fact that PC-rel addresses are not allowed for | |
497 | ;; both operands and determining whether or not we emit the operands in | |
498 | ;; order or reversed is not trivial to do just based on the constraints | |
499 | ;; and operand predicates. So to be safe, just don't allow the PC-rel | |
500 | ;; versions in the various comparison expanders, patterns, for comparisons. | |
ee128251 | 501 | (define_insn "" |
c1dbe9ae | 502 | [(set (cc0) |
9ba76f64 | 503 | (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mr,ma,>") |
504 | (match_operand:SI 1 "general_operand" "mr,ma,KTr,Ksr,>")))] | |
960e6739 | 505 | "!TARGET_COLDFIRE" |
c1dbe9ae | 506 | { |
507 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
2de9355b | 508 | return "cmpm%.l %1,%0"; |
c1dbe9ae | 509 | if (REG_P (operands[1]) |
510 | || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) | |
3acc77d9 | 511 | { |
1d86aeab | 512 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 513 | return "cmp%.l %d0,%d1"; |
92a23dbb | 514 | } |
515 | if (ADDRESS_REG_P (operands[0]) | |
516 | && GET_CODE (operands[1]) == CONST_INT | |
517 | && INTVAL (operands[1]) < 0x8000 | |
518 | && INTVAL (operands[1]) >= -0x8000) | |
3acc77d9 | 519 | return "cmp%.w %1,%0"; |
2de9355b | 520 | return "cmp%.l %d1,%d0"; |
2de9355b | 521 | }) |
00474a72 | 522 | |
1d86aeab | 523 | (define_insn "*cmpsi_cf" |
00474a72 | 524 | [(set (cc0) |
525 | (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r") | |
526 | (match_operand:SI 1 "general_operand" "r,mrKs")))] | |
960e6739 | 527 | "TARGET_COLDFIRE" |
00474a72 | 528 | { |
529 | if (REG_P (operands[1]) | |
530 | || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) | |
3acc77d9 | 531 | { |
1d86aeab | 532 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 533 | return "cmp%.l %d0,%d1"; |
c1dbe9ae | 534 | } |
2de9355b | 535 | return "cmp%.l %d1,%d0"; |
1d86aeab | 536 | } |
537 | [(set_attr "type" "cmp_l")]) | |
c1dbe9ae | 538 | |
74f4459c | 539 | (define_expand "cbranchhi4" |
83843a0b | 540 | [(set (cc0) |
9ba76f64 | 541 | (compare (match_operand:HI 1 "nonimmediate_operand" "") |
74f4459c | 542 | (match_operand:HI 2 "m68k_subword_comparison_operand" ""))) |
543 | (set (pc) | |
544 | (if_then_else (match_operator 0 "ordered_comparison_operator" | |
545 | [(cc0) (const_int 0)]) | |
546 | (label_ref (match_operand 3 "")) | |
547 | (pc)))] | |
548 | "" | |
549 | "") | |
550 | ||
551 | (define_expand "cstorehi4" | |
552 | [(set (cc0) | |
553 | (compare (match_operand:HI 2 "nonimmediate_operand" "") | |
554 | (match_operand:HI 3 "m68k_subword_comparison_operand" ""))) | |
555 | (set (match_operand:QI 0 "register_operand") | |
556 | (match_operator:QI 1 "ordered_comparison_operator" | |
557 | [(cc0) (const_int 0)]))] | |
558 | "" | |
559 | "") | |
83843a0b | 560 | |
561 | (define_insn "" | |
c1dbe9ae | 562 | [(set (cc0) |
9ba76f64 | 563 | (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>") |
564 | (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))] | |
960e6739 | 565 | "!TARGET_COLDFIRE" |
c1dbe9ae | 566 | { |
567 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
2de9355b | 568 | return "cmpm%.w %1,%0"; |
c1dbe9ae | 569 | if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) |
570 | || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) | |
3acc77d9 | 571 | { |
3c904dda | 572 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 573 | return "cmp%.w %d0,%d1"; |
c1dbe9ae | 574 | } |
2de9355b | 575 | return "cmp%.w %d1,%d0"; |
2de9355b | 576 | }) |
c1dbe9ae | 577 | |
74f4459c | 578 | (define_expand "cbranchqi4" |
83843a0b | 579 | [(set (cc0) |
9ba76f64 | 580 | (compare (match_operand:QI 1 "nonimmediate_operand" "") |
74f4459c | 581 | (match_operand:QI 2 "m68k_subword_comparison_operand" ""))) |
582 | (set (pc) | |
583 | (if_then_else (match_operator 0 "ordered_comparison_operator" | |
584 | [(cc0) (const_int 0)]) | |
585 | (label_ref (match_operand 3 "")) | |
586 | (pc)))] | |
587 | "" | |
588 | "") | |
589 | ||
590 | (define_expand "cstoreqi4" | |
591 | [(set (cc0) | |
9ba76f64 | 592 | (compare (match_operand:QI 2 "nonimmediate_operand" "") |
74f4459c | 593 | (match_operand:QI 3 "m68k_subword_comparison_operand" ""))) |
594 | (set (match_operand:QI 0 "register_operand") | |
595 | (match_operator:QI 1 "ordered_comparison_operator" | |
596 | [(cc0) (const_int 0)]))] | |
597 | "" | |
598 | "") | |
83843a0b | 599 | |
600 | (define_insn "" | |
c1dbe9ae | 601 | [(set (cc0) |
9ba76f64 | 602 | (compare (match_operand:QI 0 "nonimmediate_operand" "dn,dm,>") |
603 | (match_operand:QI 1 "general_operand" "dm,nd,>")))] | |
960e6739 | 604 | "!TARGET_COLDFIRE" |
c1dbe9ae | 605 | { |
606 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
2de9355b | 607 | return "cmpm%.b %1,%0"; |
c1dbe9ae | 608 | if (REG_P (operands[1]) |
609 | || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) | |
3acc77d9 | 610 | { |
1d86aeab | 611 | cc_status.flags |= CC_REVERSED; /*|*/ |
2de9355b | 612 | return "cmp%.b %d0,%d1"; |
c1dbe9ae | 613 | } |
2de9355b | 614 | return "cmp%.b %d1,%d0"; |
2de9355b | 615 | }) |
c1dbe9ae | 616 | |
74f4459c | 617 | (define_expand "cbranch<mode>4" |
c1dbe9ae | 618 | [(set (cc0) |
74f4459c | 619 | (compare (match_operand:FP 1 "register_operand" "") |
620 | (match_operand:FP 2 "fp_src_operand" ""))) | |
621 | (set (pc) | |
622 | (if_then_else (match_operator 0 "comparison_operator" | |
623 | [(cc0) (const_int 0)]) | |
624 | (label_ref (match_operand 3 "")) | |
625 | (pc)))] | |
58c23110 | 626 | "TARGET_HARD_FLOAT" |
74f4459c | 627 | "") |
628 | ||
629 | (define_expand "cstore<mode>4" | |
630 | [(set (cc0) | |
631 | (compare (match_operand:FP 2 "register_operand" "") | |
632 | (match_operand:FP 3 "fp_src_operand" ""))) | |
633 | (set (match_operand:QI 0 "register_operand") | |
634 | (match_operator:QI 1 "m68k_cstore_comparison_operator" | |
635 | [(cc0) (const_int 0)]))] | |
636 | "TARGET_HARD_FLOAT && !(TUNE_68060 || TARGET_COLDFIRE_FPU)" | |
637 | "if (TARGET_COLDFIRE && operands[2] != const0_rtx) | |
638 | FAIL;") | |
c1dbe9ae | 639 | |
e680c1ac | 640 | (define_insn "*cmp<mode>_68881" |
c1dbe9ae | 641 | [(set (cc0) |
e680c1ac | 642 | (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF") |
643 | (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))] | |
644 | "TARGET_68881 | |
645 | && (register_operand (operands[0], <MODE>mode) | |
646 | || register_operand (operands[1], <MODE>mode))" | |
647 | "@ | |
648 | fcmp%.x %1,%0 | |
649 | fcmp%.<FP:prec> %f1,%0 | |
650 | fcmp%.<FP:prec> %0,%f1" | |
1d86aeab | 651 | [(set_attr "type" "fcmp")]) |
c1dbe9ae | 652 | |
e680c1ac | 653 | (define_insn "*cmp<mode>_cf" |
c1dbe9ae | 654 | [(set (cc0) |
e680c1ac | 655 | (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U") |
656 | (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))] | |
657 | "TARGET_COLDFIRE_FPU | |
658 | && (register_operand (operands[0], <MODE>mode) | |
659 | || register_operand (operands[1], <MODE>mode))" | |
660 | "@ | |
661 | fcmp%.d %1,%0 | |
662 | fcmp%.<FP:prec> %f1,%0 | |
663 | fcmp%.<FP:prec> %0,%f1" | |
1d86aeab | 664 | [(set_attr "type" "fcmp")]) |
c1dbe9ae | 665 | \f |
666 | ;; Recognizers for btst instructions. | |
667 | ||
b14b4511 | 668 | ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is |
d0ee5aa9 | 669 | ;; specified as a constant, so we must disable all patterns that may extract |
670 | ;; from a MEM at a constant bit position if we can't use this as a constraint. | |
671 | ||
c1dbe9ae | 672 | (define_insn "" |
74f4459c | 673 | [(set |
674 | (cc0) | |
675 | (compare (zero_extract:SI (match_operand:QI 0 "memory_src_operand" "oS") | |
676 | (const_int 1) | |
677 | (minus:SI (const_int 7) | |
678 | (match_operand:SI 1 "general_operand" "di"))) | |
679 | (const_int 0)))] | |
960e6739 | 680 | "!TARGET_COLDFIRE" |
2de9355b | 681 | { |
682 | return output_btst (operands, operands[1], operands[0], insn, 7); | |
683 | }) | |
d0ee5aa9 | 684 | |
685 | ;; This is the same as the above pattern except for the constraints. The 'i' | |
686 | ;; has been deleted. | |
687 | ||
688 | (define_insn "" | |
74f4459c | 689 | [(set |
690 | (cc0) | |
691 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") | |
692 | (const_int 1) | |
693 | (minus:SI (const_int 7) | |
694 | (match_operand:SI 1 "general_operand" "d"))) | |
695 | (const_int 0)))] | |
960e6739 | 696 | "TARGET_COLDFIRE" |
2de9355b | 697 | { |
698 | return output_btst (operands, operands[1], operands[0], insn, 7); | |
699 | }) | |
c1dbe9ae | 700 | |
701 | (define_insn "" | |
74f4459c | 702 | [(set |
703 | (cc0) | |
704 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") | |
705 | (const_int 1) | |
706 | (minus:SI (const_int 31) | |
707 | (match_operand:SI 1 "general_operand" "di"))) | |
708 | (const_int 0)))] | |
c1dbe9ae | 709 | "" |
2de9355b | 710 | { |
711 | return output_btst (operands, operands[1], operands[0], insn, 31); | |
712 | }) | |
c1dbe9ae | 713 | |
714 | ;; The following two patterns are like the previous two | |
715 | ;; except that they use the fact that bit-number operands | |
716 | ;; are automatically masked to 3 or 5 bits. | |
717 | ||
718 | (define_insn "" | |
74f4459c | 719 | [(set |
720 | (cc0) | |
721 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") | |
722 | (const_int 1) | |
723 | (minus:SI (const_int 7) | |
724 | (and:SI | |
725 | (match_operand:SI 1 "register_operand" "d") | |
726 | (const_int 7)))) | |
727 | (const_int 0)))] | |
c1dbe9ae | 728 | "" |
2de9355b | 729 | { |
730 | return output_btst (operands, operands[1], operands[0], insn, 7); | |
731 | }) | |
c1dbe9ae | 732 | |
733 | (define_insn "" | |
74f4459c | 734 | [(set |
735 | (cc0) | |
736 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") | |
737 | (const_int 1) | |
738 | (minus:SI (const_int 31) | |
739 | (and:SI | |
740 | (match_operand:SI 1 "register_operand" "d") | |
741 | (const_int 31)))) | |
742 | (const_int 0)))] | |
c1dbe9ae | 743 | "" |
2de9355b | 744 | { |
745 | return output_btst (operands, operands[1], operands[0], insn, 31); | |
746 | }) | |
c1dbe9ae | 747 | |
748 | ;; Nonoffsettable mem refs are ok in this one pattern | |
749 | ;; since we don't try to adjust them. | |
750 | (define_insn "" | |
74f4459c | 751 | [(set |
752 | (cc0) | |
753 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") | |
754 | (const_int 1) | |
755 | (match_operand:SI 1 "const_int_operand" "n")) | |
756 | (const_int 0)))] | |
960e6739 | 757 | "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE" |
c1dbe9ae | 758 | { |
e6b2f841 | 759 | operands[1] = GEN_INT (7 - INTVAL (operands[1])); |
c1dbe9ae | 760 | return output_btst (operands, operands[1], operands[0], insn, 7); |
2de9355b | 761 | }) |
c1dbe9ae | 762 | |
763 | (define_insn "" | |
74f4459c | 764 | [(set |
765 | (cc0) | |
766 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do") | |
767 | (const_int 1) | |
768 | (match_operand:SI 1 "const_int_operand" "n")) | |
769 | (const_int 0)))] | |
960e6739 | 770 | "!TARGET_COLDFIRE" |
d0ee5aa9 | 771 | { |
772 | if (GET_CODE (operands[0]) == MEM) | |
773 | { | |
eafc6604 | 774 | operands[0] = adjust_address (operands[0], QImode, |
775 | INTVAL (operands[1]) / 8); | |
e6b2f841 | 776 | operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8); |
d0ee5aa9 | 777 | return output_btst (operands, operands[1], operands[0], insn, 7); |
778 | } | |
e6b2f841 | 779 | operands[1] = GEN_INT (31 - INTVAL (operands[1])); |
d0ee5aa9 | 780 | return output_btst (operands, operands[1], operands[0], insn, 31); |
2de9355b | 781 | }) |
d0ee5aa9 | 782 | |
783 | ;; This is the same as the above pattern except for the constraints. | |
784 | ;; The 'o' has been replaced with 'Q'. | |
785 | ||
786 | (define_insn "" | |
74f4459c | 787 | [(set |
788 | (cc0) | |
789 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ") | |
790 | (const_int 1) | |
791 | (match_operand:SI 1 "const_int_operand" "n")) | |
792 | (const_int 0)))] | |
960e6739 | 793 | "TARGET_COLDFIRE" |
c1dbe9ae | 794 | { |
795 | if (GET_CODE (operands[0]) == MEM) | |
796 | { | |
eafc6604 | 797 | operands[0] = adjust_address (operands[0], QImode, |
798 | INTVAL (operands[1]) / 8); | |
e6b2f841 | 799 | operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8); |
c1dbe9ae | 800 | return output_btst (operands, operands[1], operands[0], insn, 7); |
801 | } | |
e6b2f841 | 802 | operands[1] = GEN_INT (31 - INTVAL (operands[1])); |
c1dbe9ae | 803 | return output_btst (operands, operands[1], operands[0], insn, 31); |
2de9355b | 804 | }) |
c1dbe9ae | 805 | |
806 | \f | |
807 | ;; move instructions | |
808 | ||
809 | ;; A special case in which it is not desirable | |
810 | ;; to reload the constant into a data register. | |
b2142e18 | 811 | (define_insn "pushexthisi_const" |
1d86aeab | 812 | [(set (match_operand:SI 0 "push_operand" "=m,m,m") |
813 | (match_operand:SI 1 "const_int_operand" "C0,R,J"))] | |
68048623 | 814 | "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000" |
1d86aeab | 815 | "@ |
816 | clr%.l %0 | |
817 | mov3q%.l %1,%- | |
818 | pea %a1" | |
3c904dda | 819 | [(set_attr "type" "clr_l,mov3q_l,pea")]) |
c1dbe9ae | 820 | |
821 | ;This is never used. | |
822 | ;(define_insn "swapsi" | |
c4af10f0 | 823 | ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r") |
e78a1575 | 824 | ; (match_operand:SI 1 "general_operand" "+r")) |
c1dbe9ae | 825 | ; (set (match_dup 1) (match_dup 0))] |
826 | ; "" | |
827 | ; "exg %1,%0") | |
828 | ||
1d86aeab | 829 | ;; Special case of fullword move when source is zero for 68000_10. |
830 | ;; moveq is faster on the 68000. | |
831 | (define_insn "*movsi_const0_68000_10" | |
832 | [(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g") | |
833 | (const_int 0))] | |
834 | "TUNE_68000_10" | |
835 | "@ | |
836 | moveq #0,%0 | |
837 | sub%.l %0,%0 | |
838 | clr%.l %0" | |
3c904dda | 839 | [(set_attr "type" "moveq_l,alu_l,clr_l") |
840 | (set_attr "opy" "*,0,*")]) | |
1d86aeab | 841 | |
842 | ;; Special case of fullword move when source is zero for 68040_60. | |
843 | ;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 | |
844 | (define_insn "*movsi_const0_68040_60" | |
845 | [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g") | |
c1dbe9ae | 846 | (const_int 0))] |
1d86aeab | 847 | "TUNE_68040_60" |
c1dbe9ae | 848 | { |
1d86aeab | 849 | if (which_alternative == 0) |
4ad53767 | 850 | return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0"; |
1d86aeab | 851 | else if (which_alternative == 1) |
852 | return "clr%.l %0"; | |
853 | else | |
975368ac | 854 | { |
1d86aeab | 855 | gcc_unreachable (); |
856 | return ""; | |
975368ac | 857 | } |
1d86aeab | 858 | } |
3c904dda | 859 | [(set_attr "type" "lea,clr_l")]) |
1d86aeab | 860 | |
861 | ;; Special case of fullword move when source is zero. | |
862 | (define_insn "*movsi_const0" | |
863 | [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g") | |
864 | (const_int 0))] | |
865 | "!(TUNE_68000_10 || TUNE_68040_60)" | |
866 | "@ | |
867 | sub%.l %0,%0 | |
868 | clr%.l %0" | |
3c904dda | 869 | [(set_attr "type" "alu_l,clr_l") |
870 | (set_attr "opy" "0,*")]) | |
c1dbe9ae | 871 | |
3f6dfb87 | 872 | ;; General case of fullword move. |
c1dbe9ae | 873 | ;; |
874 | ;; This is the main "hook" for PIC code. When generating | |
875 | ;; PIC, movsi is responsible for determining when the source address | |
bdf74c8a | 876 | ;; needs PIC relocation and appropriately calling legitimize_pic_address |
c1dbe9ae | 877 | ;; to perform the actual relocation. |
878 | ;; | |
879 | ;; In both the PIC and non-PIC cases the patterns generated will | |
3f6dfb87 | 880 | ;; matched by the next define_insn. |
c1dbe9ae | 881 | (define_expand "movsi" |
e0ab7256 | 882 | [(set (match_operand:SI 0 "" "") |
883 | (match_operand:SI 1 "" ""))] | |
c1dbe9ae | 884 | "" |
c1dbe9ae | 885 | { |
e0ab7256 | 886 | rtx tmp, base, offset; |
887 | ||
869bde6b | 888 | /* Recognize the case where operand[1] is a reference to thread-local |
889 | data and load its address to a register. */ | |
890 | if (!TARGET_PCREL && m68k_tls_reference_p (operands[1], false)) | |
891 | { | |
892 | rtx tmp = operands[1]; | |
893 | rtx addend = NULL; | |
894 | ||
895 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
896 | { | |
897 | addend = XEXP (XEXP (tmp, 0), 1); | |
898 | tmp = XEXP (XEXP (tmp, 0), 0); | |
899 | } | |
900 | ||
901 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
902 | gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0); | |
903 | ||
904 | tmp = m68k_legitimize_tls_address (tmp); | |
905 | ||
906 | if (addend) | |
907 | { | |
908 | if (!REG_P (tmp)) | |
909 | { | |
910 | rtx reg; | |
911 | ||
912 | reg = gen_reg_rtx (Pmode); | |
913 | emit_move_insn (reg, tmp); | |
914 | tmp = reg; | |
915 | } | |
916 | ||
917 | tmp = gen_rtx_PLUS (SImode, tmp, addend); | |
918 | } | |
919 | ||
920 | operands[1] = tmp; | |
921 | } | |
922 | else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode)) | |
c1dbe9ae | 923 | { |
3f6dfb87 | 924 | /* The source is an address which requires PIC relocation. |
c1dbe9ae | 925 | Call legitimize_pic_address with the source, mode, and a relocation |
926 | register (a new pseudo, or the final destination if reload_in_progress | |
927 | is set). Then fall through normally */ | |
c1dbe9ae | 928 | rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); |
929 | operands[1] = legitimize_pic_address (operands[1], SImode, temp); | |
930 | } | |
f0ecff58 | 931 | else if (flag_pic && TARGET_PCREL && ! reload_in_progress) |
932 | { | |
933 | /* Don't allow writes to memory except via a register; | |
934 | the m68k doesn't consider PC-relative addresses to be writable. */ | |
935 | if (symbolic_operand (operands[0], SImode)) | |
936 | operands[0] = force_reg (SImode, XEXP (operands[0], 0)); | |
937 | else if (GET_CODE (operands[0]) == MEM | |
938 | && symbolic_operand (XEXP (operands[0], 0), SImode)) | |
1a83b3ff | 939 | operands[0] = gen_rtx_MEM (SImode, |
f0ecff58 | 940 | force_reg (SImode, XEXP (operands[0], 0))); |
941 | } | |
e0ab7256 | 942 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) |
943 | { | |
944 | split_const (operands[1], &base, &offset); | |
945 | if (GET_CODE (base) == SYMBOL_REF | |
946 | && !offset_within_block_p (base, INTVAL (offset))) | |
947 | { | |
e1ba4a27 | 948 | tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode); |
e0ab7256 | 949 | emit_move_insn (tmp, base); |
950 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
951 | DONE; | |
952 | } | |
953 | } | |
f5f2db69 | 954 | }) |
c1dbe9ae | 955 | |
e64adf14 | 956 | ;; General case of fullword move. |
957 | (define_insn "*movsi_m68k" | |
c1dbe9ae | 958 | ;; Notes: make sure no alternative allows g vs g. |
959 | ;; We don't allow f-regs since fixed point cannot go in them. | |
e64adf14 | 960 | [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<") |
961 | (match_operand:SI 1 "general_src_operand" "damSnT,n,i"))] | |
962 | "!TARGET_COLDFIRE && reload_completed" | |
963 | { | |
964 | return output_move_simode (operands); | |
965 | }) | |
966 | ||
967 | ;; Before reload is completed the register constraints | |
968 | ;; force integer constants in range for a moveq to be reloaded | |
969 | ;; if they are headed for memory. | |
970 | (define_insn "*movsi_m68k2" | |
d2e633d7 | 971 | [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<") |
22f6d4d0 | 972 | (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))] |
f0ecff58 | 973 | |
960e6739 | 974 | "!TARGET_COLDFIRE" |
c1dbe9ae | 975 | { |
e7b0a23f | 976 | return output_move_simode (operands); |
2de9355b | 977 | }) |
c1dbe9ae | 978 | |
9b84b1a0 | 979 | ;; ColdFire move instructions can have at most one operand of mode >= 6. |
0c4bc85a | 980 | (define_insn "*movsi_cf" |
1d86aeab | 981 | [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,Ap, a, r<Q>,g, U") |
982 | (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J Cs,Cs, g, Rr<Q>,U"))] | |
9b84b1a0 | 983 | "TARGET_COLDFIRE" |
1d86aeab | 984 | { |
985 | switch (which_alternative) | |
986 | { | |
987 | case 0: | |
988 | return "mov3q%.l %1,%0"; | |
989 | ||
990 | case 1: | |
991 | return "moveq %1,%0"; | |
992 | ||
993 | case 2: | |
994 | { | |
995 | unsigned u = INTVAL (operands[1]); | |
996 | ||
997 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); /*|*/ | |
998 | return "moveq %1,%0\n\tswap %0"; | |
999 | } | |
1000 | ||
1001 | case 3: | |
1002 | return "mvz%.w %1,%0"; | |
1003 | ||
1004 | case 4: | |
1005 | return "mvs%.w %1,%0"; | |
1006 | ||
1007 | case 5: | |
1008 | return "move%.l %1,%0"; | |
1009 | ||
1010 | case 6: | |
1011 | return "move%.w %1,%0"; | |
1012 | ||
1013 | case 7: | |
1014 | return "pea %a1"; | |
1015 | ||
1016 | case 8: | |
1017 | return "lea %a1,%0"; | |
1018 | ||
1019 | case 9: | |
1020 | case 10: | |
1021 | case 11: | |
1022 | return "move%.l %1,%0"; | |
1023 | ||
1024 | default: | |
1025 | gcc_unreachable (); | |
1026 | return ""; | |
1027 | } | |
1028 | } | |
3c904dda | 1029 | [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")]) |
e7b0a23f | 1030 | |
f0ecff58 | 1031 | ;; Special case of fullword move, where we need to get a non-GOT PIC |
1032 | ;; reference into an address register. | |
1033 | (define_insn "" | |
c4af10f0 | 1034 | [(set (match_operand:SI 0 "nonimmediate_operand" "=a<") |
f0ecff58 | 1035 | (match_operand:SI 1 "pcrel_address" ""))] |
1036 | "TARGET_PCREL" | |
f0ecff58 | 1037 | { |
1038 | if (push_operand (operands[0], SImode)) | |
2de9355b | 1039 | return "pea %a1"; |
1040 | return "lea %a1,%0"; | |
1041 | }) | |
f0ecff58 | 1042 | |
e7b0a23f | 1043 | (define_expand "movhi" |
c4af10f0 | 1044 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
e7b0a23f | 1045 | (match_operand:HI 1 "general_operand" ""))] |
1046 | "" | |
1047 | "") | |
1048 | ||
1049 | (define_insn "" | |
c4af10f0 | 1050 | [(set (match_operand:HI 0 "nonimmediate_operand" "=g") |
f0ecff58 | 1051 | (match_operand:HI 1 "general_src_operand" "gS"))] |
960e6739 | 1052 | "!TARGET_COLDFIRE" |
e7b0a23f | 1053 | "* return output_move_himode (operands);") |
1054 | ||
84653e0f | 1055 | (define_insn "" |
23391c74 | 1056 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U") |
1057 | (match_operand:HI 1 "general_operand" "g,r<Q>,U"))] | |
960e6739 | 1058 | "TARGET_COLDFIRE" |
e7b0a23f | 1059 | "* return output_move_himode (operands);") |
c1dbe9ae | 1060 | |
b103611b | 1061 | (define_expand "movstricthi" |
c4af10f0 | 1062 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) |
f0ecff58 | 1063 | (match_operand:HI 1 "general_src_operand" ""))] |
b103611b | 1064 | "" |
1065 | "") | |
1066 | ||
1067 | (define_insn "" | |
c4af10f0 | 1068 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) |
f0ecff58 | 1069 | (match_operand:HI 1 "general_src_operand" "rmSn"))] |
960e6739 | 1070 | "!TARGET_COLDFIRE" |
b103611b | 1071 | "* return output_move_stricthi (operands);") |
1072 | ||
1073 | (define_insn "" | |
c4af10f0 | 1074 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m")) |
f0ecff58 | 1075 | (match_operand:HI 1 "general_src_operand" "rmn,r"))] |
960e6739 | 1076 | "TARGET_COLDFIRE" |
b103611b | 1077 | "* return output_move_stricthi (operands);") |
c1dbe9ae | 1078 | |
e7b0a23f | 1079 | (define_expand "movqi" |
c4af10f0 | 1080 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
f0ecff58 | 1081 | (match_operand:QI 1 "general_src_operand" ""))] |
e7b0a23f | 1082 | "" |
1083 | "") | |
1084 | ||
1085 | (define_insn "" | |
c4af10f0 | 1086 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m") |
f0ecff58 | 1087 | (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))] |
960e6739 | 1088 | "!TARGET_COLDFIRE" |
e7b0a23f | 1089 | "* return output_move_qimode (operands);") |
c1dbe9ae | 1090 | |
e7b0a23f | 1091 | (define_insn "" |
23391c74 | 1092 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a") |
1093 | (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))] | |
960e6739 | 1094 | "TARGET_COLDFIRE" |
e7b0a23f | 1095 | "* return output_move_qimode (operands);") |
c1dbe9ae | 1096 | |
b103611b | 1097 | (define_expand "movstrictqi" |
c4af10f0 | 1098 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) |
f0ecff58 | 1099 | (match_operand:QI 1 "general_src_operand" ""))] |
b103611b | 1100 | "" |
1101 | "") | |
1102 | ||
1103 | (define_insn "" | |
c4af10f0 | 1104 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) |
f0ecff58 | 1105 | (match_operand:QI 1 "general_src_operand" "dmSn"))] |
960e6739 | 1106 | "!TARGET_COLDFIRE" |
b103611b | 1107 | "* return output_move_strictqi (operands);") |
1108 | ||
1d86aeab | 1109 | (define_insn "*movstrictqi_cf" |
1110 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d, Ac, d,m")) | |
1111 | (match_operand:QI 1 "general_src_operand" "C0,C0, dmn,d"))] | |
960e6739 | 1112 | "TARGET_COLDFIRE" |
1d86aeab | 1113 | "@ |
1114 | clr%.b %0 | |
1115 | clr%.b %0 | |
1116 | move%.b %1,%0 | |
1117 | move%.b %1,%0" | |
3c904dda | 1118 | [(set_attr "type" "clr,clr,move,move")]) |
c1dbe9ae | 1119 | |
00f41fc3 | 1120 | (define_expand "pushqi1" |
f5f2db69 | 1121 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2))) |
1122 | (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1))) | |
00f41fc3 | 1123 | (match_operand:QI 0 "general_operand" ""))] |
960e6739 | 1124 | "!TARGET_COLDFIRE" |
00f41fc3 | 1125 | "") |
1126 | ||
58c23110 | 1127 | (define_expand "reload_insf" |
1128 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f") | |
1129 | (match_operand:SF 1 "general_operand" "mf")) | |
1130 | (clobber (match_operand:SI 2 "register_operand" "=&a"))] | |
1131 | "TARGET_COLDFIRE_FPU" | |
1132 | { | |
1133 | if (emit_move_sequence (operands, SFmode, operands[2])) | |
1134 | DONE; | |
1135 | ||
1136 | /* We don't want the clobber emitted, so handle this ourselves. */ | |
d1f9b275 | 1137 | emit_insn (gen_rtx_SET (operands[0], operands[1])); |
58c23110 | 1138 | DONE; |
1139 | }) | |
1140 | ||
1141 | (define_expand "reload_outsf" | |
1142 | [(set (match_operand:SF 0 "general_operand" "") | |
1143 | (match_operand:SF 1 "register_operand" "f")) | |
1144 | (clobber (match_operand:SI 2 "register_operand" "=&a"))] | |
1145 | "TARGET_COLDFIRE_FPU" | |
1146 | { | |
1147 | if (emit_move_sequence (operands, SFmode, operands[2])) | |
1148 | DONE; | |
1149 | ||
1150 | /* We don't want the clobber emitted, so handle this ourselves. */ | |
d1f9b275 | 1151 | emit_insn (gen_rtx_SET (operands[0], operands[1])); |
58c23110 | 1152 | DONE; |
1153 | }) | |
1154 | ||
e7b0a23f | 1155 | (define_expand "movsf" |
c4af10f0 | 1156 | [(set (match_operand:SF 0 "nonimmediate_operand" "") |
e7b0a23f | 1157 | (match_operand:SF 1 "general_operand" ""))] |
1158 | "" | |
1159 | "") | |
1160 | ||
1161 | (define_insn "" | |
d2e633d7 | 1162 | [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf") |
1163 | (match_operand:SF 1 "general_operand" "rmfF"))] | |
960e6739 | 1164 | "!TARGET_COLDFIRE" |
c1dbe9ae | 1165 | { |
c1dbe9ae | 1166 | if (FP_REG_P (operands[0])) |
1167 | { | |
1168 | if (FP_REG_P (operands[1])) | |
2de9355b | 1169 | return "f%$move%.x %1,%0"; |
c1dbe9ae | 1170 | else if (ADDRESS_REG_P (operands[1])) |
2de9355b | 1171 | return "move%.l %1,%-\;f%$move%.s %+,%0"; |
c1dbe9ae | 1172 | else if (GET_CODE (operands[1]) == CONST_DOUBLE) |
1173 | return output_move_const_single (operands); | |
2de9355b | 1174 | return "f%$move%.s %f1,%0"; |
c1dbe9ae | 1175 | } |
1176 | if (FP_REG_P (operands[1])) | |
1177 | { | |
1178 | if (ADDRESS_REG_P (operands[0])) | |
2de9355b | 1179 | return "fmove%.s %1,%-\;move%.l %+,%0"; |
1180 | return "fmove%.s %f1,%0"; | |
c1dbe9ae | 1181 | } |
2de5355b | 1182 | if (operands[1] == CONST0_RTX (SFmode) |
374e1815 | 1183 | /* clr insns on 68000 read before writing. */ |
1184 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
2de5355b | 1185 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
1186 | { | |
1187 | if (ADDRESS_REG_P (operands[0])) | |
1188 | { | |
1189 | /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */ | |
f716b74b | 1190 | if (TUNE_68040_60) |
4ad53767 | 1191 | return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0"; |
f716b74b | 1192 | else |
1193 | return "sub%.l %0,%0"; | |
2de5355b | 1194 | } |
1195 | /* moveq is faster on the 68000. */ | |
bd40163f | 1196 | if (DATA_REG_P (operands[0]) && TUNE_68000_10) |
1197 | return "moveq #0,%0"; | |
2de9355b | 1198 | return "clr%.l %0"; |
2de5355b | 1199 | } |
2de9355b | 1200 | return "move%.l %1,%0"; |
1201 | }) | |
c1dbe9ae | 1202 | |
58c23110 | 1203 | (define_insn "movsf_cf_soft" |
e333f915 | 1204 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U") |
1205 | (match_operand:SF 1 "general_operand" "g,r<Q>,U"))] | |
58c23110 | 1206 | "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU" |
1d86aeab | 1207 | "move%.l %1,%0" |
1208 | [(set_attr "type" "move_l")]) | |
e7b0a23f | 1209 | |
e333f915 | 1210 | ;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU. |
1211 | ;; The move instructions can handle all combinations. | |
58c23110 | 1212 | (define_insn "movsf_cf_hard" |
1213 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f | |
1214 | ,m") | |
1215 | (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m | |
1216 | ,f"))] | |
1217 | "TARGET_COLDFIRE_FPU" | |
1218 | { | |
1219 | if (which_alternative == 4 || which_alternative == 5) { | |
1220 | rtx xoperands[2]; | |
58c23110 | 1221 | long l; |
945f7b03 | 1222 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), l); |
58c23110 | 1223 | xoperands[0] = operands[0]; |
1224 | xoperands[1] = GEN_INT (l); | |
1225 | if (which_alternative == 5) { | |
1226 | if (l == 0) { | |
1227 | if (ADDRESS_REG_P (xoperands[0])) | |
1228 | output_asm_insn ("sub%.l %0,%0", xoperands); | |
1229 | else | |
1230 | output_asm_insn ("clr%.l %0", xoperands); | |
1231 | } else | |
1232 | if (GET_CODE (operands[0]) == MEM | |
1233 | && symbolic_operand (XEXP (operands[0], 0), SImode)) | |
1234 | output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands); | |
1235 | else | |
1236 | output_asm_insn ("move%.l %1,%0", xoperands); | |
1237 | return ""; | |
1238 | } | |
1239 | if (l != 0) | |
1240 | output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands); | |
1241 | else | |
1242 | output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands); | |
1243 | return ""; | |
1244 | } | |
1245 | if (FP_REG_P (operands[0])) | |
1246 | { | |
1247 | if (ADDRESS_REG_P (operands[1])) | |
6026414c | 1248 | return "move%.l %1,%-;fsmove%.s %+,%0"; |
58c23110 | 1249 | if (FP_REG_P (operands[1])) |
6026414c | 1250 | return "fsmove%.d %1,%0"; |
1251 | return "fsmove%.s %f1,%0"; | |
58c23110 | 1252 | } |
1253 | if (FP_REG_P (operands[1])) | |
1254 | { | |
1255 | if (ADDRESS_REG_P (operands[0])) | |
1256 | return "fmove%.s %1,%-;move%.l %+,%0"; | |
1257 | return "fmove%.s %f1,%0"; | |
1258 | } | |
1259 | if (operands[1] == CONST0_RTX (SFmode)) | |
1260 | { | |
1261 | if (ADDRESS_REG_P (operands[0])) | |
1262 | return "sub%.l %0,%0"; | |
1263 | return "clr%.l %0"; | |
1264 | } | |
1265 | return "move%.l %1,%0"; | |
1266 | }) | |
1267 | ||
1268 | (define_expand "reload_indf" | |
1269 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f") | |
1270 | (match_operand:DF 1 "general_operand" "mf")) | |
1271 | (clobber (match_operand:SI 2 "register_operand" "=&a"))] | |
1272 | "TARGET_COLDFIRE_FPU" | |
1273 | { | |
1274 | if (emit_move_sequence (operands, DFmode, operands[2])) | |
1275 | DONE; | |
1276 | ||
1277 | /* We don't want the clobber emitted, so handle this ourselves. */ | |
d1f9b275 | 1278 | emit_insn (gen_rtx_SET (operands[0], operands[1])); |
58c23110 | 1279 | DONE; |
1280 | }) | |
1281 | ||
1282 | (define_expand "reload_outdf" | |
1283 | [(set (match_operand:DF 0 "general_operand" "") | |
1284 | (match_operand:DF 1 "register_operand" "f")) | |
1285 | (clobber (match_operand:SI 2 "register_operand" "=&a"))] | |
1286 | "TARGET_COLDFIRE_FPU" | |
1287 | { | |
1288 | if (emit_move_sequence (operands, DFmode, operands[2])) | |
1289 | DONE; | |
1290 | ||
1291 | /* We don't want the clobber emitted, so handle this ourselves. */ | |
d1f9b275 | 1292 | emit_insn (gen_rtx_SET (operands[0], operands[1])); |
58c23110 | 1293 | DONE; |
1294 | }) | |
1295 | ||
e7b0a23f | 1296 | (define_expand "movdf" |
c4af10f0 | 1297 | [(set (match_operand:DF 0 "nonimmediate_operand" "") |
e7b0a23f | 1298 | (match_operand:DF 1 "general_operand" ""))] |
1299 | "" | |
58c23110 | 1300 | { |
1301 | if (TARGET_COLDFIRE_FPU) | |
1302 | if (emit_move_sequence (operands, DFmode, 0)) | |
1303 | DONE; | |
1304 | }) | |
e7b0a23f | 1305 | |
1306 | (define_insn "" | |
d2e633d7 | 1307 | [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>") |
1308 | (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))] | |
c4af10f0 | 1309 | ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>") |
c1dbe9ae | 1310 | ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] |
960e6739 | 1311 | "!TARGET_COLDFIRE" |
c1dbe9ae | 1312 | { |
c1dbe9ae | 1313 | if (FP_REG_P (operands[0])) |
1314 | { | |
1315 | if (FP_REG_P (operands[1])) | |
2de9355b | 1316 | return "f%&move%.x %1,%0"; |
c1dbe9ae | 1317 | if (REG_P (operands[1])) |
1318 | { | |
1319 | rtx xoperands[2]; | |
e6b2f841 | 1320 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2de9355b | 1321 | output_asm_insn ("move%.l %1,%-", xoperands); |
1322 | output_asm_insn ("move%.l %1,%-", operands); | |
1323 | return "f%&move%.d %+,%0"; | |
c1dbe9ae | 1324 | } |
1325 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1326 | return output_move_const_double (operands); | |
2de9355b | 1327 | return "f%&move%.d %f1,%0"; |
c1dbe9ae | 1328 | } |
1329 | else if (FP_REG_P (operands[1])) | |
1330 | { | |
1331 | if (REG_P (operands[0])) | |
1332 | { | |
2de9355b | 1333 | output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); |
e6b2f841 | 1334 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1335 | return "move%.l %+,%0"; |
c1dbe9ae | 1336 | } |
1337 | else | |
2de9355b | 1338 | return "fmove%.d %f1,%0"; |
c1dbe9ae | 1339 | } |
1340 | return output_move_double (operands); | |
2de9355b | 1341 | }) |
e7b0a23f | 1342 | |
1d86aeab | 1343 | (define_insn_and_split "movdf_cf_soft" |
c4af10f0 | 1344 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g") |
e7b0a23f | 1345 | (match_operand:DF 1 "general_operand" "g,r"))] |
58c23110 | 1346 | "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU" |
1d86aeab | 1347 | "#" |
1348 | "&& reload_completed" | |
1349 | [(const_int 0)] | |
2de9355b | 1350 | { |
1d86aeab | 1351 | m68k_emit_move_double (operands); |
1352 | DONE; | |
2de9355b | 1353 | }) |
c1dbe9ae | 1354 | |
58c23110 | 1355 | (define_insn "movdf_cf_hard" |
1356 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f") | |
1357 | (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))] | |
1358 | "TARGET_COLDFIRE_FPU" | |
1359 | { | |
1360 | rtx xoperands[3]; | |
58c23110 | 1361 | long l[2]; |
1362 | ||
1363 | switch (which_alternative) | |
1364 | { | |
1365 | default: | |
6026414c | 1366 | return "fdmove%.d %1,%0"; |
1367 | case 1: | |
58c23110 | 1368 | return "fmove%.d %1,%0"; |
1369 | case 2: | |
1370 | return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0"; | |
1371 | case 3: | |
6026414c | 1372 | return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0"; |
301b951b | 1373 | case 4: case 5: case 6: |
58c23110 | 1374 | return output_move_double (operands); |
1375 | case 7: | |
945f7b03 | 1376 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), l); |
58c23110 | 1377 | xoperands[0] = operands[0]; |
1378 | xoperands[1] = GEN_INT (l[0]); | |
1379 | xoperands[2] = GEN_INT (l[1]); | |
1380 | if (operands[1] == CONST0_RTX (DFmode)) | |
1381 | output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0", | |
1382 | xoperands); | |
1383 | else | |
1384 | if (l[1] == 0) | |
1385 | output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0", | |
1386 | xoperands); | |
1387 | else | |
1388 | output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0", | |
1389 | xoperands); | |
1390 | return ""; | |
1391 | } | |
1392 | }) | |
1393 | ||
4ea9b6f3 | 1394 | ;; ??? The XFmode patterns are schizophrenic about whether constants are |
1395 | ;; allowed. Most but not all have predicates and constraint that disallow | |
1396 | ;; constants. Most but not all have output templates that handle constants. | |
ca316360 | 1397 | ;; See also TARGET_LEGITIMATE_CONSTANT_P. |
4ea9b6f3 | 1398 | |
03189682 | 1399 | (define_expand "movxf" |
1400 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
1401 | (match_operand:XF 1 "general_operand" ""))] | |
fcd8c3bc | 1402 | "" |
03189682 | 1403 | { |
4ea9b6f3 | 1404 | /* We can't rewrite operands during reload. */ |
1405 | if (! reload_in_progress) | |
f0ecff58 | 1406 | { |
4ea9b6f3 | 1407 | if (CONSTANT_P (operands[1])) |
1408 | { | |
1409 | operands[1] = force_const_mem (XFmode, operands[1]); | |
1410 | if (! memory_address_p (XFmode, XEXP (operands[1], 0))) | |
1411 | operands[1] = adjust_address (operands[1], XFmode, 0); | |
1412 | } | |
1413 | if (flag_pic && TARGET_PCREL) | |
1414 | { | |
1415 | /* Don't allow writes to memory except via a register; the | |
1416 | m68k doesn't consider PC-relative addresses to be writable. */ | |
1417 | if (GET_CODE (operands[0]) == MEM | |
1418 | && symbolic_operand (XEXP (operands[0], 0), SImode)) | |
1a83b3ff | 1419 | operands[0] = gen_rtx_MEM (XFmode, |
4ea9b6f3 | 1420 | force_reg (SImode, XEXP (operands[0], 0))); |
1421 | } | |
f0ecff58 | 1422 | } |
f5f2db69 | 1423 | }) |
03189682 | 1424 | |
1425 | (define_insn "" | |
463b8e0b | 1426 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r") |
1427 | (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))] | |
03189682 | 1428 | "TARGET_68881" |
03189682 | 1429 | { |
1430 | if (FP_REG_P (operands[0])) | |
1431 | { | |
1432 | if (FP_REG_P (operands[1])) | |
2de9355b | 1433 | return "fmove%.x %1,%0"; |
03189682 | 1434 | if (REG_P (operands[1])) |
1435 | { | |
1436 | rtx xoperands[2]; | |
e6b2f841 | 1437 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2de9355b | 1438 | output_asm_insn ("move%.l %1,%-", xoperands); |
e6b2f841 | 1439 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2de9355b | 1440 | output_asm_insn ("move%.l %1,%-", xoperands); |
1441 | output_asm_insn ("move%.l %1,%-", operands); | |
1442 | return "fmove%.x %+,%0"; | |
03189682 | 1443 | } |
1444 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2de9355b | 1445 | return "fmove%.x %1,%0"; |
1446 | return "fmove%.x %f1,%0"; | |
03189682 | 1447 | } |
c9ff1a07 | 1448 | if (FP_REG_P (operands[1])) |
03189682 | 1449 | { |
c9ff1a07 | 1450 | if (REG_P (operands[0])) |
1451 | { | |
2de9355b | 1452 | output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands); |
c9ff1a07 | 1453 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1454 | output_asm_insn ("move%.l %+,%0", operands); |
c9ff1a07 | 1455 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1456 | return "move%.l %+,%0"; |
c9ff1a07 | 1457 | } |
1458 | /* Must be memory destination. */ | |
2de9355b | 1459 | return "fmove%.x %f1,%0"; |
03189682 | 1460 | } |
c9ff1a07 | 1461 | return output_move_double (operands); |
2de9355b | 1462 | }) |
03189682 | 1463 | |
fcd8c3bc | 1464 | (define_insn "" |
3aa4a7c9 | 1465 | [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>") |
fcd8c3bc | 1466 | (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] |
960e6739 | 1467 | "! TARGET_68881 && ! TARGET_COLDFIRE" |
fcd8c3bc | 1468 | { |
1469 | if (FP_REG_P (operands[0])) | |
1470 | { | |
1471 | if (FP_REG_P (operands[1])) | |
2de9355b | 1472 | return "fmove%.x %1,%0"; |
fcd8c3bc | 1473 | if (REG_P (operands[1])) |
1474 | { | |
1475 | rtx xoperands[2]; | |
e6b2f841 | 1476 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2de9355b | 1477 | output_asm_insn ("move%.l %1,%-", xoperands); |
e6b2f841 | 1478 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2de9355b | 1479 | output_asm_insn ("move%.l %1,%-", xoperands); |
1480 | output_asm_insn ("move%.l %1,%-", operands); | |
1481 | return "fmove%.x %+,%0"; | |
fcd8c3bc | 1482 | } |
1483 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2de9355b | 1484 | return "fmove%.x %1,%0"; |
1485 | return "fmove%.x %f1,%0"; | |
fcd8c3bc | 1486 | } |
1487 | if (FP_REG_P (operands[1])) | |
1488 | { | |
1489 | if (REG_P (operands[0])) | |
1490 | { | |
2de9355b | 1491 | output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands); |
e6b2f841 | 1492 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1493 | output_asm_insn ("move%.l %+,%0", operands); |
e6b2f841 | 1494 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1495 | return "move%.l %+,%0"; |
fcd8c3bc | 1496 | } |
1497 | else | |
2de9355b | 1498 | return "fmove%.x %f1,%0"; |
fcd8c3bc | 1499 | } |
1500 | return output_move_double (operands); | |
2de9355b | 1501 | }) |
fcd8c3bc | 1502 | |
6dbf3211 | 1503 | (define_insn "" |
1504 | [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g") | |
1505 | (match_operand:XF 1 "nonimmediate_operand" "g,r"))] | |
960e6739 | 1506 | "! TARGET_68881 && TARGET_COLDFIRE" |
6dbf3211 | 1507 | "* return output_move_double (operands);") |
1508 | ||
e7b0a23f | 1509 | (define_expand "movdi" |
1510 | ;; Let's see if it really still needs to handle fp regs, and, if so, why. | |
c4af10f0 | 1511 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
e7b0a23f | 1512 | (match_operand:DI 1 "general_operand" ""))] |
1513 | "" | |
1514 | "") | |
1515 | ||
c1dbe9ae | 1516 | ;; movdi can apply to fp regs in some cases |
e7b0a23f | 1517 | (define_insn "" |
c1dbe9ae | 1518 | ;; Let's see if it really still needs to handle fp regs, and, if so, why. |
d2e633d7 | 1519 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>") |
1520 | (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))] | |
1521 | ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f") | |
1522 | ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))] | |
c4af10f0 | 1523 | ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f") |
c1dbe9ae | 1524 | ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] |
960e6739 | 1525 | "!TARGET_COLDFIRE" |
c1dbe9ae | 1526 | { |
c1dbe9ae | 1527 | if (FP_REG_P (operands[0])) |
1528 | { | |
1529 | if (FP_REG_P (operands[1])) | |
2de9355b | 1530 | return "fmove%.x %1,%0"; |
c1dbe9ae | 1531 | if (REG_P (operands[1])) |
1532 | { | |
1533 | rtx xoperands[2]; | |
e6b2f841 | 1534 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2de9355b | 1535 | output_asm_insn ("move%.l %1,%-", xoperands); |
1536 | output_asm_insn ("move%.l %1,%-", operands); | |
1537 | return "fmove%.d %+,%0"; | |
c1dbe9ae | 1538 | } |
1539 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1540 | return output_move_const_double (operands); | |
2de9355b | 1541 | return "fmove%.d %f1,%0"; |
c1dbe9ae | 1542 | } |
1543 | else if (FP_REG_P (operands[1])) | |
1544 | { | |
1545 | if (REG_P (operands[0])) | |
1546 | { | |
2de9355b | 1547 | output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); |
e6b2f841 | 1548 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1549 | return "move%.l %+,%0"; |
c1dbe9ae | 1550 | } |
1551 | else | |
2de9355b | 1552 | return "fmove%.d %f1,%0"; |
c1dbe9ae | 1553 | } |
1554 | return output_move_double (operands); | |
2de9355b | 1555 | }) |
e7b0a23f | 1556 | |
1557 | (define_insn "" | |
c4af10f0 | 1558 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g") |
e7b0a23f | 1559 | (match_operand:DI 1 "general_operand" "g,r"))] |
960e6739 | 1560 | "TARGET_COLDFIRE" |
e7b0a23f | 1561 | "* return output_move_double (operands);") |
c1dbe9ae | 1562 | |
1563 | ;; Thus goes after the move instructions | |
1564 | ;; because the move instructions are better (require no spilling) | |
1565 | ;; when they can apply. It goes before the add/sub insns | |
1566 | ;; so we will prefer it to them. | |
1567 | ||
1568 | (define_insn "pushasi" | |
1569 | [(set (match_operand:SI 0 "push_operand" "=m") | |
1570 | (match_operand:SI 1 "address_operand" "p"))] | |
1571 | "" | |
1d86aeab | 1572 | "pea %a1" |
1573 | [(set_attr "type" "pea")]) | |
c1dbe9ae | 1574 | \f |
1575 | ;; truncation instructions | |
1576 | (define_insn "truncsiqi2" | |
c4af10f0 | 1577 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d") |
c1dbe9ae | 1578 | (truncate:QI |
f0ecff58 | 1579 | (match_operand:SI 1 "general_src_operand" "doJS,i")))] |
9680dd14 | 1580 | "!TARGET_COLDFIRE" |
c1dbe9ae | 1581 | { |
1582 | if (GET_CODE (operands[0]) == REG) | |
1583 | { | |
bdf74c8a | 1584 | /* Must clear condition codes, since the move.l bases them on |
c1dbe9ae | 1585 | the entire 32 bits, not just the desired 8 bits. */ |
1586 | CC_STATUS_INIT; | |
2de9355b | 1587 | return "move%.l %1,%0"; |
c1dbe9ae | 1588 | } |
1589 | if (GET_CODE (operands[1]) == MEM) | |
eafc6604 | 1590 | operands[1] = adjust_address (operands[1], QImode, 3); |
2de9355b | 1591 | return "move%.b %1,%0"; |
1592 | }) | |
c1dbe9ae | 1593 | |
1594 | (define_insn "trunchiqi2" | |
c4af10f0 | 1595 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d") |
c1dbe9ae | 1596 | (truncate:QI |
f0ecff58 | 1597 | (match_operand:HI 1 "general_src_operand" "doJS,i")))] |
9680dd14 | 1598 | "!TARGET_COLDFIRE" |
c1dbe9ae | 1599 | { |
1600 | if (GET_CODE (operands[0]) == REG | |
1601 | && (GET_CODE (operands[1]) == MEM | |
1602 | || GET_CODE (operands[1]) == CONST_INT)) | |
1603 | { | |
bdf74c8a | 1604 | /* Must clear condition codes, since the move.w bases them on |
c1dbe9ae | 1605 | the entire 16 bits, not just the desired 8 bits. */ |
1606 | CC_STATUS_INIT; | |
2de9355b | 1607 | return "move%.w %1,%0"; |
c1dbe9ae | 1608 | } |
1609 | if (GET_CODE (operands[0]) == REG) | |
1610 | { | |
bdf74c8a | 1611 | /* Must clear condition codes, since the move.l bases them on |
c1dbe9ae | 1612 | the entire 32 bits, not just the desired 8 bits. */ |
1613 | CC_STATUS_INIT; | |
2de9355b | 1614 | return "move%.l %1,%0"; |
c1dbe9ae | 1615 | } |
1616 | if (GET_CODE (operands[1]) == MEM) | |
eafc6604 | 1617 | operands[1] = adjust_address (operands[1], QImode, 1); |
2de9355b | 1618 | return "move%.b %1,%0"; |
1619 | }) | |
c1dbe9ae | 1620 | |
1621 | (define_insn "truncsihi2" | |
c4af10f0 | 1622 | [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d") |
c1dbe9ae | 1623 | (truncate:HI |
f0ecff58 | 1624 | (match_operand:SI 1 "general_src_operand" "roJS,i")))] |
9680dd14 | 1625 | "!TARGET_COLDFIRE" |
c1dbe9ae | 1626 | { |
1627 | if (GET_CODE (operands[0]) == REG) | |
1628 | { | |
bdf74c8a | 1629 | /* Must clear condition codes, since the move.l bases them on |
c1dbe9ae | 1630 | the entire 32 bits, not just the desired 8 bits. */ |
1631 | CC_STATUS_INIT; | |
2de9355b | 1632 | return "move%.l %1,%0"; |
c1dbe9ae | 1633 | } |
1634 | if (GET_CODE (operands[1]) == MEM) | |
eafc6604 | 1635 | operands[1] = adjust_address (operands[1], QImode, 2); |
2de9355b | 1636 | return "move%.w %1,%0"; |
1637 | }) | |
c1dbe9ae | 1638 | \f |
1639 | ;; zero extension instructions | |
1640 | ||
e2eeb731 | 1641 | ;; two special patterns to match various post_inc/pre_dec patterns |
1642 | (define_insn_and_split "*zero_extend_inc" | |
1643 | [(set (match_operand 0 "post_inc_operand" "") | |
1644 | (zero_extend (match_operand 1 "register_operand" "")))] | |
1645 | "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT && | |
1646 | GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT && | |
1647 | GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2" | |
1648 | "#" | |
43b24f37 | 1649 | "" |
e2eeb731 | 1650 | [(set (match_dup 0) |
1651 | (const_int 0)) | |
1652 | (set (match_dup 0) | |
1653 | (match_dup 1))] | |
43b24f37 | 1654 | { |
e2eeb731 | 1655 | operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0); |
2de9355b | 1656 | }) |
43b24f37 | 1657 | |
e2eeb731 | 1658 | (define_insn_and_split "*zero_extend_dec" |
1659 | [(set (match_operand 0 "pre_dec_operand" "") | |
1660 | (zero_extend (match_operand 1 "register_operand" "")))] | |
1661 | "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) && | |
1662 | GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT && | |
1663 | GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT && | |
1664 | GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2" | |
1665 | "#" | |
43b24f37 | 1666 | "" |
e2eeb731 | 1667 | [(set (match_dup 0) |
1668 | (match_dup 1)) | |
1669 | (set (match_dup 0) | |
1670 | (const_int 0))] | |
43b24f37 | 1671 | { |
e2eeb731 | 1672 | operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0); |
2de9355b | 1673 | }) |
43b24f37 | 1674 | |
e2eeb731 | 1675 | (define_insn_and_split "zero_extendqidi2" |
1676 | [(set (match_operand:DI 0 "register_operand" "") | |
1677 | (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))] | |
5e4c76b7 | 1678 | "" |
e2eeb731 | 1679 | "#" |
1680 | "" | |
1681 | [(set (match_dup 2) | |
1682 | (zero_extend:SI (match_dup 1))) | |
1683 | (set (match_dup 3) | |
1684 | (const_int 0))] | |
e5afe6e7 | 1685 | { |
e2eeb731 | 1686 | operands[2] = gen_lowpart (SImode, operands[0]); |
1687 | operands[3] = gen_highpart (SImode, operands[0]); | |
2de9355b | 1688 | }) |
e5afe6e7 | 1689 | |
e2eeb731 | 1690 | (define_insn_and_split "zero_extendhidi2" |
1691 | [(set (match_operand:DI 0 "register_operand" "") | |
1692 | (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))] | |
1693 | "" | |
1694 | "#" | |
1695 | "" | |
1696 | [(set (match_dup 2) | |
1697 | (zero_extend:SI (match_dup 1))) | |
1698 | (set (match_dup 3) | |
1699 | (const_int 0))] | |
5e4c76b7 | 1700 | { |
e2eeb731 | 1701 | operands[2] = gen_lowpart (SImode, operands[0]); |
1702 | operands[3] = gen_highpart (SImode, operands[0]); | |
2de9355b | 1703 | }) |
5e4c76b7 | 1704 | |
e2eeb731 | 1705 | (define_expand "zero_extendsidi2" |
1706 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1707 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))] | |
c1dbe9ae | 1708 | "" |
c3c043d7 | 1709 | { |
1710 | if (GET_CODE (operands[0]) == MEM | |
1711 | && GET_CODE (operands[1]) == MEM) | |
1712 | operands[1] = force_reg (SImode, operands[1]); | |
1713 | }) | |
c1dbe9ae | 1714 | |
e2eeb731 | 1715 | (define_insn_and_split "*zero_extendsidi2" |
1716 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1717 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))] | |
1718 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" | |
1719 | "#" | |
c1dbe9ae | 1720 | "" |
e2eeb731 | 1721 | [(set (match_dup 2) |
1722 | (match_dup 1)) | |
1723 | (set (match_dup 3) | |
1724 | (const_int 0))] | |
c1dbe9ae | 1725 | { |
e2eeb731 | 1726 | operands[2] = gen_lowpart (SImode, operands[0]); |
1727 | operands[3] = gen_highpart (SImode, operands[0]); | |
1728 | }) | |
c1dbe9ae | 1729 | |
e2eeb731 | 1730 | (define_insn "*zero_extendhisi2_cf" |
1731 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1732 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] | |
da8fbdfe | 1733 | "ISA_HAS_MVS_MVZ" |
1d86aeab | 1734 | "mvz%.w %1,%0" |
3c904dda | 1735 | [(set_attr "type" "mvsz")]) |
e2eeb731 | 1736 | |
1737 | (define_insn "zero_extendhisi2" | |
1738 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1739 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] | |
c1dbe9ae | 1740 | "" |
e2eeb731 | 1741 | "#") |
c1dbe9ae | 1742 | |
e2eeb731 | 1743 | (define_expand "zero_extendqihi2" |
1744 | [(set (match_operand:HI 0 "register_operand" "") | |
1745 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))] | |
1746 | "!TARGET_COLDFIRE" | |
1747 | "") | |
c1dbe9ae | 1748 | |
e2eeb731 | 1749 | (define_insn "*zero_extendqihi2" |
1750 | [(set (match_operand:HI 0 "register_operand" "=d") | |
1751 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] | |
1752 | "!TARGET_COLDFIRE" | |
1753 | "#") | |
c1dbe9ae | 1754 | |
e2eeb731 | 1755 | (define_insn "*zero_extendqisi2_cfv4" |
1756 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1757 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] | |
da8fbdfe | 1758 | "ISA_HAS_MVS_MVZ" |
1d86aeab | 1759 | "mvz%.b %1,%0" |
3c904dda | 1760 | [(set_attr "type" "mvsz")]) |
e2eeb731 | 1761 | |
1762 | (define_insn "zero_extendqisi2" | |
1763 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1764 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] | |
1765 | "" | |
1766 | "#") | |
1767 | ||
1768 | ;; these two pattern split everything else which isn't matched by | |
1769 | ;; something else above | |
1770 | (define_split | |
1771 | [(set (match_operand 0 "register_operand" "") | |
1772 | (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))] | |
da8fbdfe | 1773 | "!ISA_HAS_MVS_MVZ |
42af5438 | 1774 | && reload_completed |
1775 | && reg_mentioned_p (operands[0], operands[1])" | |
e2eeb731 | 1776 | [(set (strict_low_part (match_dup 2)) |
1777 | (match_dup 1)) | |
1778 | (set (match_dup 0) | |
1779 | (match_op_dup 4 [(match_dup 0) (match_dup 3)]))] | |
1780 | { | |
1781 | operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]); | |
1782 | operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1]))); | |
1783 | operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]); | |
1784 | }) | |
1785 | ||
1786 | (define_split | |
1787 | [(set (match_operand 0 "register_operand" "") | |
1788 | (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))] | |
da8fbdfe | 1789 | "!ISA_HAS_MVS_MVZ && reload_completed" |
e2eeb731 | 1790 | [(set (match_dup 0) |
1791 | (const_int 0)) | |
1792 | (set (strict_low_part (match_dup 2)) | |
1793 | (match_dup 1))] | |
c1dbe9ae | 1794 | { |
e2eeb731 | 1795 | operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]); |
2de9355b | 1796 | }) |
c1dbe9ae | 1797 | \f |
1798 | ;; sign extension instructions | |
1799 | ||
5e4c76b7 | 1800 | (define_insn "extendqidi2" |
c4af10f0 | 1801 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") |
f0ecff58 | 1802 | (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))] |
5e4c76b7 | 1803 | "" |
5e4c76b7 | 1804 | { |
1805 | CC_STATUS_INIT; | |
e6b2f841 | 1806 | operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
da8fbdfe | 1807 | if (ISA_HAS_MVS_MVZ) |
0c4bc85a | 1808 | return "mvs%.b %1,%2\;smi %0\;extb%.l %0"; |
960e6739 | 1809 | if (TARGET_68020 || TARGET_COLDFIRE) |
c4be82cc | 1810 | { |
1811 | if (ADDRESS_REG_P (operands[1])) | |
1812 | return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0"; | |
1813 | else | |
1814 | return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0"; | |
1815 | } | |
5e4c76b7 | 1816 | else |
c4be82cc | 1817 | { |
1818 | if (ADDRESS_REG_P (operands[1])) | |
1819 | return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0"; | |
1820 | else | |
1821 | return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0"; | |
1822 | } | |
2de9355b | 1823 | }) |
5e4c76b7 | 1824 | |
1825 | (define_insn "extendhidi2" | |
c4af10f0 | 1826 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") |
5e4c76b7 | 1827 | (sign_extend:DI |
f0ecff58 | 1828 | (match_operand:HI 1 "general_src_operand" "rmS")))] |
5e4c76b7 | 1829 | "" |
5e4c76b7 | 1830 | { |
1831 | CC_STATUS_INIT; | |
e6b2f841 | 1832 | operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
da8fbdfe | 1833 | if (ISA_HAS_MVS_MVZ) |
0c4bc85a | 1834 | return "mvs%.w %1,%2\;smi %0\;extb%.l %0"; |
960e6739 | 1835 | if (TARGET_68020 || TARGET_COLDFIRE) |
2de9355b | 1836 | return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0"; |
5e4c76b7 | 1837 | else |
2de9355b | 1838 | return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0"; |
1839 | }) | |
5e4c76b7 | 1840 | |
1841 | (define_insn "extendsidi2" | |
f081d7b0 | 1842 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<") |
1843 | (sign_extend:DI | |
1844 | (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r<Q>,rm"))) | |
1845 | (clobber (match_scratch:SI 2 "=X,d,d,d"))] | |
5e4c76b7 | 1846 | "" |
5e4c76b7 | 1847 | { |
1848 | CC_STATUS_INIT; | |
8ec9650e | 1849 | |
f081d7b0 | 1850 | if (which_alternative == 0) |
1851 | /* Handle alternative 0. */ | |
1852 | { | |
1853 | if (TARGET_68020 || TARGET_COLDFIRE) | |
1854 | return "move%.l %1,%R0\;smi %0\;extb%.l %0"; | |
1855 | else | |
1856 | return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0"; | |
1857 | } | |
1858 | ||
1859 | /* Handle alternatives 1, 2 and 3. We don't need to adjust address by 4 | |
1860 | in alternative 3 because autodecrement will do that for us. */ | |
8ec9650e | 1861 | operands[3] = adjust_address (operands[0], SImode, |
f081d7b0 | 1862 | which_alternative == 3 ? 0 : 4); |
8ec9650e | 1863 | operands[0] = adjust_address (operands[0], SImode, 0); |
f081d7b0 | 1864 | |
8ec9650e | 1865 | if (TARGET_68020 || TARGET_COLDFIRE) |
1866 | return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0"; | |
5e4c76b7 | 1867 | else |
8ec9650e | 1868 | return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0"; |
f081d7b0 | 1869 | } |
1870 | [(set_attr "ok_for_coldfire" "yes,no,yes,yes")]) | |
5e4c76b7 | 1871 | |
1872 | ;; Special case when one can avoid register clobbering, copy and test | |
1873 | ;; Maybe there is a way to make that the general case, by forcing the | |
1874 | ;; result of the SI tree to be in the lower register of the DI target | |
1875 | ||
dd1b652b | 1876 | ;; Don't allow memory for operand 1 as that would require an earlyclobber |
1877 | ;; which results in worse code | |
5e4c76b7 | 1878 | (define_insn "extendplussidi" |
1879 | [(set (match_operand:DI 0 "register_operand" "=d") | |
dd1b652b | 1880 | (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rn") |
5e4c76b7 | 1881 | (match_operand:SI 2 "general_operand" "rmn"))))] |
1882 | "" | |
5e4c76b7 | 1883 | { |
1884 | CC_STATUS_INIT; | |
e6b2f841 | 1885 | operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
5e4c76b7 | 1886 | if (GET_CODE (operands[1]) == CONST_INT |
1887 | && (unsigned) INTVAL (operands[1]) > 8) | |
1888 | { | |
1889 | rtx tmp = operands[1]; | |
1890 | ||
1891 | operands[1] = operands[2]; | |
1892 | operands[2] = tmp; | |
1893 | } | |
3f6dfb87 | 1894 | if (GET_CODE (operands[1]) == REG |
1895 | && REGNO (operands[1]) == REGNO (operands[3])) | |
2de9355b | 1896 | output_asm_insn ("add%.l %2,%3", operands); |
3f6dfb87 | 1897 | else |
2de9355b | 1898 | output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands); |
960e6739 | 1899 | if (TARGET_68020 || TARGET_COLDFIRE) |
2de9355b | 1900 | return "smi %0\;extb%.l %0"; |
5e4c76b7 | 1901 | else |
2de9355b | 1902 | return "smi %0\;ext%.w %0\;ext%.l %0"; |
1903 | }) | |
5e4c76b7 | 1904 | |
0c4bc85a | 1905 | (define_expand "extendhisi2" |
1906 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
1907 | (sign_extend:SI | |
1908 | (match_operand:HI 1 "nonimmediate_src_operand" "")))] | |
1909 | "" | |
1910 | "") | |
1911 | ||
1912 | (define_insn "*cfv4_extendhisi2" | |
1913 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
1914 | (sign_extend:SI | |
1915 | (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] | |
da8fbdfe | 1916 | "ISA_HAS_MVS_MVZ" |
1d86aeab | 1917 | "mvs%.w %1,%0" |
3c904dda | 1918 | [(set_attr "type" "mvsz")]) |
0c4bc85a | 1919 | |
1920 | (define_insn "*68k_extendhisi2" | |
c4af10f0 | 1921 | [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a") |
c1dbe9ae | 1922 | (sign_extend:SI |
f0ecff58 | 1923 | (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))] |
da8fbdfe | 1924 | "!ISA_HAS_MVS_MVZ" |
1d86aeab | 1925 | "@ |
1926 | ext%.l %0 | |
1927 | move%.w %1,%0" | |
3c904dda | 1928 | [(set_attr "type" "ext,move")]) |
c1dbe9ae | 1929 | |
1930 | (define_insn "extendqihi2" | |
c4af10f0 | 1931 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 1932 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] |
1933 | "" | |
1d86aeab | 1934 | "ext%.w %0" |
3c904dda | 1935 | [(set_attr "type" "ext")]) |
c1dbe9ae | 1936 | |
0c4bc85a | 1937 | (define_expand "extendqisi2" |
1938 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
1939 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
1940 | "TARGET_68020 || TARGET_COLDFIRE" | |
1941 | "") | |
1942 | ||
1943 | (define_insn "*cfv4_extendqisi2" | |
f5f2db69 | 1944 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
0c4bc85a | 1945 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))] |
da8fbdfe | 1946 | "ISA_HAS_MVS_MVZ" |
1d86aeab | 1947 | "mvs%.b %1,%0" |
3c904dda | 1948 | [(set_attr "type" "mvsz")]) |
0c4bc85a | 1949 | |
1950 | (define_insn "*68k_extendqisi2" | |
c4af10f0 | 1951 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 1952 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] |
da8fbdfe | 1953 | "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)" |
1d86aeab | 1954 | "extb%.l %0" |
3c904dda | 1955 | [(set_attr "type" "ext")]) |
c1dbe9ae | 1956 | \f |
1957 | ;; Conversions between float and double. | |
1958 | ||
1959 | (define_expand "extendsfdf2" | |
c4af10f0 | 1960 | [(set (match_operand:DF 0 "nonimmediate_operand" "") |
c1dbe9ae | 1961 | (float_extend:DF |
1962 | (match_operand:SF 1 "general_operand" "")))] | |
58c23110 | 1963 | "TARGET_HARD_FLOAT" |
c1dbe9ae | 1964 | "") |
1965 | ||
c1dbe9ae | 1966 | (define_insn "" |
c4af10f0 | 1967 | [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f") |
c1dbe9ae | 1968 | (float_extend:DF |
1969 | (match_operand:SF 1 "general_operand" "f,dmF")))] | |
1970 | "TARGET_68881" | |
c1dbe9ae | 1971 | { |
1972 | if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) | |
1973 | { | |
1974 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
1975 | { | |
1976 | /* Extending float to double in an fp-reg is a no-op. | |
1977 | NOTICE_UPDATE_CC has already assumed that the | |
1978 | cc will be set. So cancel what it did. */ | |
1979 | cc_status = cc_prev_status; | |
2de9355b | 1980 | return ""; |
c1dbe9ae | 1981 | } |
2de9355b | 1982 | return "f%&move%.x %1,%0"; |
c1dbe9ae | 1983 | } |
1984 | if (FP_REG_P (operands[0])) | |
2de9355b | 1985 | return "f%&move%.s %f1,%0"; |
c1dbe9ae | 1986 | if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) |
1987 | { | |
2de9355b | 1988 | output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); |
e6b2f841 | 1989 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 1990 | return "move%.l %+,%0"; |
c1dbe9ae | 1991 | } |
2de9355b | 1992 | return "fmove%.d %f1,%0"; |
1993 | }) | |
c1dbe9ae | 1994 | |
58c23110 | 1995 | (define_insn "extendsfdf2_cf" |
1996 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f") | |
1997 | (float_extend:DF | |
1998 | (match_operand:SF 1 "general_operand" "f,<Q>U")))] | |
1999 | "TARGET_COLDFIRE_FPU" | |
2000 | { | |
2001 | if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) | |
2002 | { | |
2003 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
2004 | { | |
2005 | /* Extending float to double in an fp-reg is a no-op. | |
2006 | NOTICE_UPDATE_CC has already assumed that the | |
2007 | cc will be set. So cancel what it did. */ | |
2008 | cc_status = cc_prev_status; | |
2009 | return ""; | |
2010 | } | |
6026414c | 2011 | return "fdmove%.d %1,%0"; |
58c23110 | 2012 | } |
6026414c | 2013 | return "fdmove%.s %f1,%0"; |
58c23110 | 2014 | }) |
2015 | ||
c1dbe9ae | 2016 | ;; This cannot output into an f-reg because there is no way to be |
2017 | ;; sure of truncating in that case. | |
c1dbe9ae | 2018 | (define_expand "truncdfsf2" |
c4af10f0 | 2019 | [(set (match_operand:SF 0 "nonimmediate_operand" "") |
c1dbe9ae | 2020 | (float_truncate:SF |
2021 | (match_operand:DF 1 "general_operand" "")))] | |
58c23110 | 2022 | "TARGET_HARD_FLOAT" |
c1dbe9ae | 2023 | "") |
2024 | ||
c1dbe9ae | 2025 | ;; On the '040 we can truncate in a register accurately and easily. |
2026 | (define_insn "" | |
c4af10f0 | 2027 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f") |
c1dbe9ae | 2028 | (float_truncate:SF |
2029 | (match_operand:DF 1 "general_operand" "fmG")))] | |
6e6d2086 | 2030 | "TARGET_68881 && TARGET_68040" |
c1dbe9ae | 2031 | { |
2032 | if (FP_REG_P (operands[1])) | |
2de9355b | 2033 | return "f%$move%.x %1,%0"; |
2034 | return "f%$move%.d %f1,%0"; | |
2035 | }) | |
c1dbe9ae | 2036 | |
58c23110 | 2037 | (define_insn "truncdfsf2_cf" |
2038 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U") | |
2039 | (float_truncate:SF | |
2040 | (match_operand:DF 1 "general_operand" "<Q>U,f")))] | |
2041 | "TARGET_COLDFIRE_FPU" | |
2042 | "@ | |
6026414c | 2043 | fsmove%.d %1,%0 |
1d86aeab | 2044 | fmove%.s %1,%0" |
2045 | [(set_attr "type" "fmove")]) | |
58c23110 | 2046 | |
1d86aeab | 2047 | (define_insn "*truncdfsf2_68881" |
c4af10f0 | 2048 | [(set (match_operand:SF 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 2049 | (float_truncate:SF |
2050 | (match_operand:DF 1 "general_operand" "f")))] | |
2051 | "TARGET_68881" | |
1d86aeab | 2052 | "fmove%.s %f1,%0" |
2053 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2054 | \f |
2055 | ;; Conversion between fixed point and floating point. | |
2056 | ;; Note that among the fix-to-float insns | |
2057 | ;; the ones that start with SImode come first. | |
2058 | ;; That is so that an operand that is a CONST_INT | |
2059 | ;; (and therefore lacks a specific machine mode). | |
2060 | ;; will be recognized as SImode (which is always valid) | |
2061 | ;; rather than as QImode or HImode. | |
2062 | ||
58c23110 | 2063 | (define_expand "floatsi<mode>2" |
2064 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
2065 | (float:FP (match_operand:SI 1 "general_operand" "")))] | |
2066 | "TARGET_HARD_FLOAT" | |
c1dbe9ae | 2067 | "") |
2068 | ||
58c23110 | 2069 | (define_insn "floatsi<mode>2_68881" |
2070 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2071 | (float:FP (match_operand:SI 1 "general_operand" "dmi")))] | |
c1dbe9ae | 2072 | "TARGET_68881" |
3c904dda | 2073 | "f<FP:round>move%.l %1,%0" |
2074 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2075 | |
58c23110 | 2076 | (define_insn "floatsi<mode>2_cf" |
2077 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2078 | (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))] | |
2079 | "TARGET_COLDFIRE_FPU" | |
1d86aeab | 2080 | "f<FP:prec>move%.l %1,%0" |
2081 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2082 | |
c1dbe9ae | 2083 | |
58c23110 | 2084 | (define_expand "floathi<mode>2" |
2085 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
2086 | (float:FP (match_operand:HI 1 "general_operand" "")))] | |
2087 | "TARGET_HARD_FLOAT" | |
2088 | "") | |
c1dbe9ae | 2089 | |
58c23110 | 2090 | (define_insn "floathi<mode>2_68881" |
2091 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2092 | (float:FP (match_operand:HI 1 "general_operand" "dmn")))] | |
c1dbe9ae | 2093 | "TARGET_68881" |
1d86aeab | 2094 | "fmove%.w %1,%0" |
2095 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2096 | |
58c23110 | 2097 | (define_insn "floathi<mode>2_cf" |
2098 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2099 | (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))] | |
2100 | "TARGET_COLDFIRE_FPU" | |
1d86aeab | 2101 | "fmove%.w %1,%0" |
2102 | [(set_attr "type" "fmove")]) | |
58c23110 | 2103 | |
2104 | ||
2105 | (define_expand "floatqi<mode>2" | |
2106 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
2107 | (float:FP (match_operand:QI 1 "general_operand" "")))] | |
2108 | "TARGET_HARD_FLOAT" | |
2109 | "") | |
2110 | ||
2111 | (define_insn "floatqi<mode>2_68881" | |
2112 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2113 | (float:FP (match_operand:QI 1 "general_operand" "dmn")))] | |
c1dbe9ae | 2114 | "TARGET_68881" |
1d86aeab | 2115 | "fmove%.b %1,%0" |
2116 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2117 | |
58c23110 | 2118 | (define_insn "floatqi<mode>2_cf" |
2119 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2120 | (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))] | |
2121 | "TARGET_COLDFIRE_FPU" | |
1d86aeab | 2122 | "fmove%.b %1,%0" |
2123 | [(set_attr "type" "fmove")]) | |
58c23110 | 2124 | |
c1dbe9ae | 2125 | |
2126 | ;; New routines to convert floating-point values to integers | |
2127 | ;; to be used on the '040. These should be faster than trapping | |
2128 | ;; into the kernel to emulate fintrz. They should also be faster | |
03189682 | 2129 | ;; than calling the subroutines fixsfsi or fixdfsi. |
c1dbe9ae | 2130 | |
2131 | (define_insn "fix_truncdfsi2" | |
c4af10f0 | 2132 | [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 2133 | (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) |
2134 | (clobber (match_scratch:SI 2 "=d")) | |
2135 | (clobber (match_scratch:SI 3 "=d"))] | |
bd40163f | 2136 | "TARGET_68881 && TUNE_68040" |
c1dbe9ae | 2137 | { |
2138 | CC_STATUS_INIT; | |
3acc77d9 | 2139 | return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!"; |
2de9355b | 2140 | }) |
c1dbe9ae | 2141 | |
2142 | (define_insn "fix_truncdfhi2" | |
c4af10f0 | 2143 | [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 2144 | (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) |
2145 | (clobber (match_scratch:SI 2 "=d")) | |
2146 | (clobber (match_scratch:SI 3 "=d"))] | |
bd40163f | 2147 | "TARGET_68881 && TUNE_68040" |
c1dbe9ae | 2148 | { |
2149 | CC_STATUS_INIT; | |
3acc77d9 | 2150 | return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!"; |
2de9355b | 2151 | }) |
c1dbe9ae | 2152 | |
2153 | (define_insn "fix_truncdfqi2" | |
c4af10f0 | 2154 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 2155 | (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) |
2156 | (clobber (match_scratch:SI 2 "=d")) | |
2157 | (clobber (match_scratch:SI 3 "=d"))] | |
bd40163f | 2158 | "TARGET_68881 && TUNE_68040" |
c1dbe9ae | 2159 | { |
2160 | CC_STATUS_INIT; | |
3acc77d9 | 2161 | return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!"; |
2de9355b | 2162 | }) |
c1dbe9ae | 2163 | |
2164 | ;; Convert a float to a float whose value is an integer. | |
2165 | ;; This is the first stage of converting it to an integer type. | |
2166 | ||
58c23110 | 2167 | (define_expand "ftrunc<mode>2" |
2168 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
2169 | (fix:FP (match_operand:FP 1 "general_operand" "")))] | |
bd40163f | 2170 | "TARGET_HARD_FLOAT && !TUNE_68040" |
58c23110 | 2171 | "") |
2172 | ||
2173 | (define_insn "ftrunc<mode>2_68881" | |
2174 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2175 | (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))] | |
bd40163f | 2176 | "TARGET_68881 && !TUNE_68040" |
c1dbe9ae | 2177 | { |
2178 | if (FP_REG_P (operands[1])) | |
2de9355b | 2179 | return "fintrz%.x %f1,%0"; |
58c23110 | 2180 | return "fintrz%.<FP:prec> %f1,%0"; |
3c904dda | 2181 | } |
2182 | [(set_attr "type" "falu")]) | |
c1dbe9ae | 2183 | |
58c23110 | 2184 | (define_insn "ftrunc<mode>2_cf" |
2185 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2186 | (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))] | |
2187 | "TARGET_COLDFIRE_FPU" | |
c1dbe9ae | 2188 | { |
2189 | if (FP_REG_P (operands[1])) | |
58c23110 | 2190 | return "fintrz%.d %f1,%0"; |
2191 | return "fintrz%.<FP:prec> %f1,%0"; | |
1d86aeab | 2192 | } |
3c904dda | 2193 | [(set_attr "type" "falu")]) |
c1dbe9ae | 2194 | |
2195 | ;; Convert a float whose value is an integer | |
2196 | ;; to an actual integer. Second stage of converting float to integer type. | |
58c23110 | 2197 | (define_expand "fix<mode>qi2" |
2198 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2199 | (fix:QI (match_operand:FP 1 "general_operand" "")))] | |
2200 | "TARGET_HARD_FLOAT" | |
2201 | "") | |
2202 | ||
2203 | (define_insn "fix<mode>qi2_68881" | |
c4af10f0 | 2204 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") |
58c23110 | 2205 | (fix:QI (match_operand:FP 1 "general_operand" "f")))] |
c1dbe9ae | 2206 | "TARGET_68881" |
3c904dda | 2207 | "fmove%.b %1,%0" |
2208 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2209 | |
58c23110 | 2210 | (define_insn "fix<mode>qi2_cf" |
2211 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U") | |
2212 | (fix:QI (match_operand:FP 1 "general_operand" "f")))] | |
2213 | "TARGET_COLDFIRE_FPU" | |
1d86aeab | 2214 | "fmove%.b %1,%0" |
2215 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2216 | |
58c23110 | 2217 | (define_expand "fix<mode>hi2" |
2218 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2219 | (fix:HI (match_operand:FP 1 "general_operand" "")))] | |
2220 | "TARGET_HARD_FLOAT" | |
2221 | "") | |
2222 | ||
2223 | (define_insn "fix<mode>hi2_68881" | |
c4af10f0 | 2224 | [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") |
58c23110 | 2225 | (fix:HI (match_operand:FP 1 "general_operand" "f")))] |
c1dbe9ae | 2226 | "TARGET_68881" |
3c904dda | 2227 | "fmove%.w %1,%0" |
2228 | [(set_attr "type" "fmove")]) | |
c1dbe9ae | 2229 | |
58c23110 | 2230 | (define_insn "fix<mode>hi2_cf" |
2231 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U") | |
2232 | (fix:HI (match_operand:FP 1 "general_operand" "f")))] | |
2233 | "TARGET_COLDFIRE_FPU" | |
1d86aeab | 2234 | "fmove%.w %1,%0" |
2235 | [(set_attr "type" "fmove")]) | |
58c23110 | 2236 | |
2237 | (define_expand "fix<mode>si2" | |
2238 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
2239 | (fix:SI (match_operand:FP 1 "general_operand" "")))] | |
2240 | "TARGET_HARD_FLOAT" | |
2241 | "") | |
2242 | ||
2243 | (define_insn "fix<mode>si2_68881" | |
c4af10f0 | 2244 | [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") |
58c23110 | 2245 | (fix:SI (match_operand:FP 1 "general_operand" "f")))] |
c1dbe9ae | 2246 | "TARGET_68881" |
3c904dda | 2247 | "fmove%.l %1,%0" |
2248 | [(set_attr "type" "fmove")]) | |
58c23110 | 2249 | |
2250 | (define_insn "fix<mode>si2_cf" | |
2251 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U") | |
2252 | (fix:SI (match_operand:FP 1 "general_operand" "f")))] | |
2253 | "TARGET_COLDFIRE_FPU" | |
1d86aeab | 2254 | "fmove%.l %1,%0" |
2255 | [(set_attr "type" "fmove")]) | |
58c23110 | 2256 | |
c1dbe9ae | 2257 | \f |
2258 | ;; add instructions | |
2259 | ||
697ae2f9 | 2260 | (define_insn "adddi_lshrdi_63" |
c4af10f0 | 2261 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") |
697ae2f9 | 2262 | (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm") |
2263 | (const_int 63)) | |
2264 | (match_dup 1))) | |
2265 | (clobber (match_scratch:SI 2 "=d"))] | |
2266 | "" | |
697ae2f9 | 2267 | { |
e6b2f841 | 2268 | operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
697ae2f9 | 2269 | if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0])) |
2270 | return | |
2de9355b | 2271 | "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0"; |
697ae2f9 | 2272 | if (GET_CODE (operands[1]) == REG) |
e6b2f841 | 2273 | operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
697ae2f9 | 2274 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC |
2275 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2276 | operands[4] = operands[1]; | |
2277 | else | |
eafc6604 | 2278 | operands[4] = adjust_address (operands[1], SImode, 4); |
697ae2f9 | 2279 | if (GET_CODE (operands[1]) == MEM |
2280 | && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2de9355b | 2281 | output_asm_insn ("move%.l %4,%3", operands); |
2282 | output_asm_insn ("move%.l %1,%0\;smi %2", operands); | |
960e6739 | 2283 | if (TARGET_68020 || TARGET_COLDFIRE) |
2de9355b | 2284 | output_asm_insn ("extb%.l %2", operands); |
697ae2f9 | 2285 | else |
2de9355b | 2286 | output_asm_insn ("ext%.w %2\;ext%.l %2", operands); |
697ae2f9 | 2287 | if (GET_CODE (operands[1]) != MEM |
2288 | || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC) | |
2de9355b | 2289 | output_asm_insn ("move%.l %4,%3", operands); |
2290 | return "sub%.l %2,%3\;subx%.l %2,%0"; | |
2291 | }) | |
697ae2f9 | 2292 | |
ef64b201 | 2293 | (define_insn "adddi_sexthishl32" |
c4af10f0 | 2294 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d") |
5e4c76b7 | 2295 | (plus:DI (ashift:DI (sign_extend:DI |
3f6dfb87 | 2296 | (match_operand:HI 1 "general_operand" "rm,rm,rm,rm")) |
5e4c76b7 | 2297 | (const_int 32)) |
3f6dfb87 | 2298 | (match_operand:DI 2 "general_operand" "0,0,0,0"))) |
2299 | (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] | |
960e6739 | 2300 | "!TARGET_COLDFIRE" |
5e4c76b7 | 2301 | { |
2302 | CC_STATUS_INIT; | |
ef64b201 | 2303 | if (ADDRESS_REG_P (operands[0])) |
2de9355b | 2304 | return "add%.w %1,%0"; |
3f6dfb87 | 2305 | else if (ADDRESS_REG_P (operands[3])) |
2de9355b | 2306 | return "move%.w %1,%3\;add%.l %3,%0"; |
ef64b201 | 2307 | else |
2de9355b | 2308 | return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0"; |
2309 | }) | |
5e4c76b7 | 2310 | |
b5489b01 | 2311 | (define_insn "*adddi_dilshr32" |
c4af10f0 | 2312 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o") |
b5489b01 | 2313 | (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d") |
2314 | (const_int 32)) | |
2315 | (match_operand:DI 2 "general_operand" "0,0")))] | |
2316 | "!TARGET_COLDFIRE" | |
5e4c76b7 | 2317 | { |
2318 | CC_STATUS_INIT; | |
2319 | if (GET_CODE (operands[0]) == REG) | |
e6b2f841 | 2320 | operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
5e4c76b7 | 2321 | else |
eafc6604 | 2322 | operands[2] = adjust_address (operands[0], SImode, 4); |
2de9355b | 2323 | return "add%.l %1,%2\;negx%.l %0\;neg%.l %0"; |
2324 | }) | |
5e4c76b7 | 2325 | |
b5489b01 | 2326 | (define_insn "*adddi_dilshr32_cf" |
2327 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2328 | (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro") | |
2329 | (const_int 32)) | |
2330 | (match_operand:DI 2 "register_operand" "0")))] | |
2331 | "TARGET_COLDFIRE" | |
2332 | { | |
2333 | CC_STATUS_INIT; | |
2334 | return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0"; | |
2335 | }) | |
2336 | ||
5e4c76b7 | 2337 | (define_insn "adddi_dishl32" |
c4af10f0 | 2338 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") |
d08c9ad7 | 2339 | ;; (plus:DI (match_operand:DI 2 "general_operand" "%0") |
2340 | ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro") | |
2341 | ;; (const_int 32))))] | |
00f41fc3 | 2342 | (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d") |
5e4c76b7 | 2343 | (const_int 32)) |
fb7ed77b | 2344 | (match_operand:DI 2 "general_operand" "0,0")))] |
5e4c76b7 | 2345 | "" |
5e4c76b7 | 2346 | { |
2347 | CC_STATUS_INIT; | |
2348 | if (GET_CODE (operands[1]) == REG) | |
e6b2f841 | 2349 | operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
5e4c76b7 | 2350 | else |
eafc6604 | 2351 | operands[1] = adjust_address (operands[1], SImode, 4); |
2de9355b | 2352 | return "add%.l %1,%0"; |
1d86aeab | 2353 | } |
3c904dda | 2354 | [(set_attr "type" "alu_l")]) |
5e4c76b7 | 2355 | |
5d3fef16 | 2356 | (define_insn "adddi3" |
b5489b01 | 2357 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d") |
2358 | (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0") | |
2359 | (match_operand:DI 2 "general_operand" "d,no>,d,a"))) | |
2360 | (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))] | |
5d3fef16 | 2361 | "" |
5d3fef16 | 2362 | { |
80925ff3 | 2363 | if (DATA_REG_P (operands[0])) |
2364 | { | |
2365 | if (DATA_REG_P (operands[2])) | |
2de9355b | 2366 | return "add%.l %R2,%R0\;addx%.l %2,%0"; |
80925ff3 | 2367 | else if (GET_CODE (operands[2]) == MEM |
2368 | && GET_CODE (XEXP (operands[2], 0)) == POST_INC) | |
2de9355b | 2369 | return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0"; |
80925ff3 | 2370 | else |
2371 | { | |
7014838c | 2372 | rtx high, low; |
05b6e83e | 2373 | rtx xoperands[2]; |
7014838c | 2374 | |
80925ff3 | 2375 | if (GET_CODE (operands[2]) == REG) |
dc5ebe55 | 2376 | { |
7014838c | 2377 | low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
2378 | high = operands[2]; | |
dc5ebe55 | 2379 | } |
7014838c | 2380 | else if (CONSTANT_P (operands[2])) |
2381 | split_double (operands[2], &high, &low); | |
2382 | else | |
dc5ebe55 | 2383 | { |
eafc6604 | 2384 | low = adjust_address (operands[2], SImode, 4); |
7014838c | 2385 | high = operands[2]; |
dc5ebe55 | 2386 | } |
7014838c | 2387 | |
2388 | operands[1] = low, operands[2] = high; | |
05b6e83e | 2389 | xoperands[0] = operands[3]; |
03a04b74 | 2390 | if (GET_CODE (operands[1]) == CONST_INT |
2391 | && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) | |
2392 | xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1); | |
2393 | else | |
2394 | xoperands[1] = operands[2]; | |
7014838c | 2395 | |
05b6e83e | 2396 | output_asm_insn (output_move_simode (xoperands), xoperands); |
2397 | if (GET_CODE (operands[1]) == CONST_INT) | |
2398 | { | |
2399 | if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) | |
2de9355b | 2400 | return "addq%.l %1,%R0\;addx%.l %3,%0"; |
05b6e83e | 2401 | else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) |
2402 | { | |
2403 | operands[1] = GEN_INT (-INTVAL (operands[1])); | |
2de9355b | 2404 | return "subq%.l %1,%R0\;subx%.l %3,%0"; |
05b6e83e | 2405 | } |
2406 | } | |
2de9355b | 2407 | return "add%.l %1,%R0\;addx%.l %3,%0"; |
80925ff3 | 2408 | } |
2409 | } | |
84653e0f | 2410 | else |
5e4c76b7 | 2411 | { |
84653e0f | 2412 | gcc_assert (GET_CODE (operands[0]) == MEM); |
5e4c76b7 | 2413 | CC_STATUS_INIT; |
80925ff3 | 2414 | if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) |
2415 | { | |
7014838c | 2416 | operands[1] = gen_rtx_MEM (SImode, |
29c05e22 | 2417 | plus_constant (Pmode, |
2418 | XEXP(operands[0], 0), -8)); | |
2de9355b | 2419 | return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1"; |
80925ff3 | 2420 | } |
2421 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2422 | { | |
2423 | operands[1] = XEXP(operands[0], 0); | |
2de9355b | 2424 | return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1"; |
80925ff3 | 2425 | } |
2426 | else | |
2427 | { | |
eafc6604 | 2428 | operands[1] = adjust_address (operands[0], SImode, 4); |
2de9355b | 2429 | return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0"; |
80925ff3 | 2430 | } |
5e4c76b7 | 2431 | } |
2de9355b | 2432 | }) |
5d3fef16 | 2433 | |
d08c9ad7 | 2434 | (define_insn "addsi_lshrsi_31" |
06817dd5 | 2435 | [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,dm,d<Q>") |
2436 | (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm,r<Q>,rm") | |
d08c9ad7 | 2437 | (const_int 31)) |
74a00d1a | 2438 | (match_dup 1)))] |
d08c9ad7 | 2439 | "" |
d08c9ad7 | 2440 | { |
2441 | operands[2] = operands[0]; | |
2442 | operands[3] = gen_label_rtx(); | |
2443 | if (GET_CODE (operands[0]) == MEM) | |
2444 | { | |
2445 | if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
e6b2f841 | 2446 | operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0)); |
d08c9ad7 | 2447 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) |
e6b2f841 | 2448 | operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0)); |
d08c9ad7 | 2449 | } |
2de9355b | 2450 | output_asm_insn ("move%.l %1,%0", operands); |
a1f3c748 | 2451 | output_asm_insn ("jpl %l3", operands); |
3acc77d9 | 2452 | output_asm_insn ("addq%.l #1,%2", operands); |
2de9355b | 2453 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
d08c9ad7 | 2454 | CODE_LABEL_NUMBER (operands[3])); |
2de9355b | 2455 | return ""; |
06817dd5 | 2456 | } |
2457 | [(set_attr "ok_for_coldfire" "no,yes,yes")]) | |
d08c9ad7 | 2458 | |
6dbf3211 | 2459 | (define_expand "addsi3" |
c4af10f0 | 2460 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
6dbf3211 | 2461 | (plus:SI (match_operand:SI 1 "general_operand" "") |
f0ecff58 | 2462 | (match_operand:SI 2 "general_src_operand" "")))] |
6dbf3211 | 2463 | "" |
2464 | "") | |
2465 | ||
c1dbe9ae | 2466 | ;; Note that the middle two alternatives are near-duplicates |
2467 | ;; in order to handle insns generated by reload. | |
2468 | ;; This is needed since they are not themselves reloaded, | |
2469 | ;; so commutativity won't apply to them. | |
6dbf3211 | 2470 | (define_insn "*addsi3_internal" |
c4af10f0 | 2471 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a") |
f0ecff58 | 2472 | (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0") |
2473 | (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))] | |
2474 | ||
2475 | ||
960e6739 | 2476 | "! TARGET_COLDFIRE" |
6dbf3211 | 2477 | "* return output_addsi3 (operands);") |
c1dbe9ae | 2478 | |
1d86aeab | 2479 | (define_insn_and_split "*addsi3_5200" |
869bde6b | 2480 | [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a, m,r, ?a, ?a,?a,?a") |
2481 | (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0, 0,0, a, a, r, a") | |
2482 | (match_operand:SI 2 "general_src_operand" " I, L, JCu,d,mrKi,Cj, r, a, JCu")))] | |
960e6739 | 2483 | "TARGET_COLDFIRE" |
1d86aeab | 2484 | { |
2485 | switch (which_alternative) | |
2486 | { | |
2487 | case 0: | |
2488 | return "addq%.l %2,%0"; | |
2489 | ||
2490 | case 1: | |
2491 | operands[2] = GEN_INT (- INTVAL (operands[2])); | |
2492 | return "subq%.l %2,%0"; | |
2493 | ||
1d86aeab | 2494 | case 3: |
94b82d11 | 2495 | case 4: |
1d86aeab | 2496 | return "add%.l %2,%0"; |
2497 | ||
94b82d11 | 2498 | case 5: |
1d86aeab | 2499 | /* move%.l %2,%0\n\tadd%.l %1,%0 */ |
2500 | return "#"; | |
2501 | ||
94b82d11 | 2502 | case 6: |
4ad53767 | 2503 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
1d86aeab | 2504 | |
94b82d11 | 2505 | case 7: |
4ad53767 | 2506 | return MOTOROLA ? "lea (%2,%1.l),%0" : "lea %2@(0,%1:l),%0"; |
1d86aeab | 2507 | |
94b82d11 | 2508 | case 2: |
2509 | case 8: | |
4ad53767 | 2510 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; |
1d86aeab | 2511 | |
2512 | default: | |
2513 | gcc_unreachable (); | |
2514 | return ""; | |
2515 | } | |
2516 | } | |
94b82d11 | 2517 | "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 5) && !operands_match_p (operands[0], operands[1])" |
1d86aeab | 2518 | [(set (match_dup 0) |
2519 | (match_dup 2)) | |
2520 | (set (match_dup 0) | |
2521 | (plus:SI (match_dup 0) | |
2522 | (match_dup 1)))] | |
2523 | "" | |
869bde6b | 2524 | [(set_attr "type" "aluq_l,aluq_l,lea, alu_l,alu_l,*,lea, lea, lea") |
2525 | (set_attr "opy" "2, 2, *, 2, 2, *,*, *, *") | |
2526 | (set_attr "opy_type" "*, *, mem5,*, *, *,mem6,mem6,mem5")]) | |
c1dbe9ae | 2527 | |
2528 | (define_insn "" | |
c4af10f0 | 2529 | [(set (match_operand:SI 0 "nonimmediate_operand" "=a") |
c1dbe9ae | 2530 | (plus:SI (match_operand:SI 1 "general_operand" "0") |
2531 | (sign_extend:SI | |
f0ecff58 | 2532 | (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] |
960e6739 | 2533 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2534 | "add%.w %2,%0") |
2535 | ||
2536 | (define_insn "addhi3" | |
c4af10f0 | 2537 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") |
c1dbe9ae | 2538 | (plus:HI (match_operand:HI 1 "general_operand" "%0,0") |
f0ecff58 | 2539 | (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] |
960e6739 | 2540 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2541 | { |
c1dbe9ae | 2542 | if (GET_CODE (operands[2]) == CONST_INT) |
2543 | { | |
bdf74c8a | 2544 | /* If the constant would be a negative number when interpreted as |
2545 | HImode, make it negative. This is usually, but not always, done | |
2546 | elsewhere in the compiler. First check for constants out of range, | |
2547 | which could confuse us. */ | |
2548 | ||
2549 | if (INTVAL (operands[2]) >= 32768) | |
e6b2f841 | 2550 | operands[2] = GEN_INT (INTVAL (operands[2]) - 65536); |
bdf74c8a | 2551 | |
c1dbe9ae | 2552 | if (INTVAL (operands[2]) > 0 |
2553 | && INTVAL (operands[2]) <= 8) | |
2de9355b | 2554 | return "addq%.w %2,%0"; |
c1dbe9ae | 2555 | if (INTVAL (operands[2]) < 0 |
2556 | && INTVAL (operands[2]) >= -8) | |
2557 | { | |
7014838c | 2558 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
2de9355b | 2559 | return "subq%.w %2,%0"; |
c1dbe9ae | 2560 | } |
975368ac | 2561 | /* On the CPU32 it is faster to use two addqw instructions to |
8b23f550 | 2562 | add a small integer (8 < N <= 16) to a register. |
0c0492c9 | 2563 | Likewise for subqw. */ |
bd40163f | 2564 | if (TUNE_CPU32 && REG_P (operands[0])) |
c1dbe9ae | 2565 | { |
8c287d02 | 2566 | if (INTVAL (operands[2]) > 8 |
2567 | && INTVAL (operands[2]) <= 16) | |
2568 | { | |
e6b2f841 | 2569 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3acc77d9 | 2570 | return "addq%.w #8,%0\;addq%.w %2,%0"; |
8c287d02 | 2571 | } |
2572 | if (INTVAL (operands[2]) < -8 | |
2573 | && INTVAL (operands[2]) >= -16) | |
2574 | { | |
7014838c | 2575 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3acc77d9 | 2576 | return "subq%.w #8,%0\;subq%.w %2,%0"; |
8c287d02 | 2577 | } |
c1dbe9ae | 2578 | } |
bd40163f | 2579 | if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) |
4ad53767 | 2580 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
975368ac | 2581 | } |
2de9355b | 2582 | return "add%.w %2,%0"; |
2583 | }) | |
c1dbe9ae | 2584 | |
a45d833a | 2585 | ;; These insns must use MATCH_DUP instead of the more expected |
2586 | ;; use of a matching constraint because the "output" here is also | |
2587 | ;; an input, so you can't use the matching constraint. That also means | |
2588 | ;; that you can't use the "%", so you need patterns with the matched | |
2589 | ;; operand in both positions. | |
2590 | ||
c1dbe9ae | 2591 | (define_insn "" |
c4af10f0 | 2592 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
c1dbe9ae | 2593 | (plus:HI (match_dup 0) |
f0ecff58 | 2594 | (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] |
960e6739 | 2595 | "!TARGET_COLDFIRE" |
bdf74c8a | 2596 | { |
bdf74c8a | 2597 | if (GET_CODE (operands[1]) == CONST_INT) |
2598 | { | |
2599 | /* If the constant would be a negative number when interpreted as | |
2600 | HImode, make it negative. This is usually, but not always, done | |
2601 | elsewhere in the compiler. First check for constants out of range, | |
2602 | which could confuse us. */ | |
2603 | ||
2604 | if (INTVAL (operands[1]) >= 32768) | |
e6b2f841 | 2605 | operands[1] = GEN_INT (INTVAL (operands[1]) - 65536); |
bdf74c8a | 2606 | |
2607 | if (INTVAL (operands[1]) > 0 | |
2608 | && INTVAL (operands[1]) <= 8) | |
2de9355b | 2609 | return "addq%.w %1,%0"; |
bdf74c8a | 2610 | if (INTVAL (operands[1]) < 0 |
2611 | && INTVAL (operands[1]) >= -8) | |
2612 | { | |
7014838c | 2613 | operands[1] = GEN_INT (- INTVAL (operands[1])); |
2de9355b | 2614 | return "subq%.w %1,%0"; |
bdf74c8a | 2615 | } |
975368ac | 2616 | /* On the CPU32 it is faster to use two addqw instructions to |
8b23f550 | 2617 | add a small integer (8 < N <= 16) to a register. |
0c0492c9 | 2618 | Likewise for subqw. */ |
bd40163f | 2619 | if (TUNE_CPU32 && REG_P (operands[0])) |
bdf74c8a | 2620 | { |
8c287d02 | 2621 | if (INTVAL (operands[1]) > 8 |
2622 | && INTVAL (operands[1]) <= 16) | |
2623 | { | |
e6b2f841 | 2624 | operands[1] = GEN_INT (INTVAL (operands[1]) - 8); |
3acc77d9 | 2625 | return "addq%.w #8,%0\;addq%.w %1,%0"; |
8c287d02 | 2626 | } |
2627 | if (INTVAL (operands[1]) < -8 | |
2628 | && INTVAL (operands[1]) >= -16) | |
2629 | { | |
7014838c | 2630 | operands[1] = GEN_INT (- INTVAL (operands[1]) - 8); |
3acc77d9 | 2631 | return "subq%.w #8,%0\;subq%.w %1,%0"; |
8c287d02 | 2632 | } |
bdf74c8a | 2633 | } |
bd40163f | 2634 | if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) |
4ad53767 | 2635 | return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0"; |
975368ac | 2636 | } |
2de9355b | 2637 | return "add%.w %1,%0"; |
2638 | }) | |
c1dbe9ae | 2639 | |
a45d833a | 2640 | (define_insn "" |
c4af10f0 | 2641 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
f0ecff58 | 2642 | (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn") |
a45d833a | 2643 | (match_dup 0)))] |
960e6739 | 2644 | "!TARGET_COLDFIRE" |
bdf74c8a | 2645 | { |
bdf74c8a | 2646 | if (GET_CODE (operands[1]) == CONST_INT) |
2647 | { | |
2648 | /* If the constant would be a negative number when interpreted as | |
2649 | HImode, make it negative. This is usually, but not always, done | |
2650 | elsewhere in the compiler. First check for constants out of range, | |
2651 | which could confuse us. */ | |
2652 | ||
2653 | if (INTVAL (operands[1]) >= 32768) | |
e6b2f841 | 2654 | operands[1] = GEN_INT (INTVAL (operands[1]) - 65536); |
bdf74c8a | 2655 | |
2656 | if (INTVAL (operands[1]) > 0 | |
2657 | && INTVAL (operands[1]) <= 8) | |
2de9355b | 2658 | return "addq%.w %1,%0"; |
bdf74c8a | 2659 | if (INTVAL (operands[1]) < 0 |
2660 | && INTVAL (operands[1]) >= -8) | |
2661 | { | |
7014838c | 2662 | operands[1] = GEN_INT (- INTVAL (operands[1])); |
2de9355b | 2663 | return "subq%.w %1,%0"; |
bdf74c8a | 2664 | } |
975368ac | 2665 | /* On the CPU32 it is faster to use two addqw instructions to |
8b23f550 | 2666 | add a small integer (8 < N <= 16) to a register. |
0c0492c9 | 2667 | Likewise for subqw. */ |
bd40163f | 2668 | if (TUNE_CPU32 && REG_P (operands[0])) |
bdf74c8a | 2669 | { |
8c287d02 | 2670 | if (INTVAL (operands[1]) > 8 |
2671 | && INTVAL (operands[1]) <= 16) | |
2672 | { | |
e6b2f841 | 2673 | operands[1] = GEN_INT (INTVAL (operands[1]) - 8); |
3acc77d9 | 2674 | return "addq%.w #8,%0\;addq%.w %1,%0"; |
8c287d02 | 2675 | } |
2676 | if (INTVAL (operands[1]) < -8 | |
2677 | && INTVAL (operands[1]) >= -16) | |
2678 | { | |
7014838c | 2679 | operands[1] = GEN_INT (- INTVAL (operands[1]) - 8); |
3acc77d9 | 2680 | return "subq%.w #8,%0\;subq%.w %1,%0"; |
8c287d02 | 2681 | } |
bdf74c8a | 2682 | } |
bd40163f | 2683 | if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) |
4ad53767 | 2684 | return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0"; |
975368ac | 2685 | } |
2de9355b | 2686 | return "add%.w %1,%0"; |
2687 | }) | |
a45d833a | 2688 | |
c1dbe9ae | 2689 | (define_insn "addqi3" |
c4af10f0 | 2690 | [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 2691 | (plus:QI (match_operand:QI 1 "general_operand" "%0,0") |
f0ecff58 | 2692 | (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] |
960e6739 | 2693 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2694 | { |
c1dbe9ae | 2695 | if (GET_CODE (operands[2]) == CONST_INT) |
2696 | { | |
bdf74c8a | 2697 | if (INTVAL (operands[2]) >= 128) |
e6b2f841 | 2698 | operands[2] = GEN_INT (INTVAL (operands[2]) - 256); |
bdf74c8a | 2699 | |
c1dbe9ae | 2700 | if (INTVAL (operands[2]) > 0 |
2701 | && INTVAL (operands[2]) <= 8) | |
2de9355b | 2702 | return "addq%.b %2,%0"; |
c1dbe9ae | 2703 | if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) |
2704 | { | |
7014838c | 2705 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
2de9355b | 2706 | return "subq%.b %2,%0"; |
c1dbe9ae | 2707 | } |
2708 | } | |
2de9355b | 2709 | return "add%.b %2,%0"; |
2710 | }) | |
c1dbe9ae | 2711 | |
2712 | (define_insn "" | |
c4af10f0 | 2713 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
c1dbe9ae | 2714 | (plus:QI (match_dup 0) |
f0ecff58 | 2715 | (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] |
960e6739 | 2716 | "!TARGET_COLDFIRE" |
bdf74c8a | 2717 | { |
bdf74c8a | 2718 | if (GET_CODE (operands[1]) == CONST_INT) |
2719 | { | |
2720 | if (INTVAL (operands[1]) >= 128) | |
e6b2f841 | 2721 | operands[1] = GEN_INT (INTVAL (operands[1]) - 256); |
bdf74c8a | 2722 | |
2723 | if (INTVAL (operands[1]) > 0 | |
2724 | && INTVAL (operands[1]) <= 8) | |
2de9355b | 2725 | return "addq%.b %1,%0"; |
bdf74c8a | 2726 | if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) |
2727 | { | |
7014838c | 2728 | operands[1] = GEN_INT (- INTVAL (operands[1])); |
2de9355b | 2729 | return "subq%.b %1,%0"; |
bdf74c8a | 2730 | } |
2731 | } | |
2de9355b | 2732 | return "add%.b %1,%0"; |
2733 | }) | |
c1dbe9ae | 2734 | |
a45d833a | 2735 | (define_insn "" |
c4af10f0 | 2736 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
f0ecff58 | 2737 | (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") |
a45d833a | 2738 | (match_dup 0)))] |
960e6739 | 2739 | "!TARGET_COLDFIRE" |
bdf74c8a | 2740 | { |
bdf74c8a | 2741 | if (GET_CODE (operands[1]) == CONST_INT) |
2742 | { | |
2743 | if (INTVAL (operands[1]) >= 128) | |
e6b2f841 | 2744 | operands[1] = GEN_INT (INTVAL (operands[1]) - 256); |
bdf74c8a | 2745 | |
2746 | if (INTVAL (operands[1]) > 0 | |
2747 | && INTVAL (operands[1]) <= 8) | |
2de9355b | 2748 | return "addq%.b %1,%0"; |
bdf74c8a | 2749 | if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) |
2750 | { | |
7014838c | 2751 | operands[1] = GEN_INT (- INTVAL (operands[1])); |
2de9355b | 2752 | return "subq%.b %1,%0"; |
bdf74c8a | 2753 | } |
2754 | } | |
2de9355b | 2755 | return "add%.b %1,%0"; |
2756 | }) | |
a45d833a | 2757 | |
58c23110 | 2758 | (define_expand "add<mode>3" |
2759 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
2760 | (plus:FP (match_operand:FP 1 "general_operand" "") | |
2761 | (match_operand:FP 2 "general_operand" "")))] | |
2762 | "TARGET_HARD_FLOAT" | |
c1dbe9ae | 2763 | "") |
2764 | ||
58c23110 | 2765 | (define_insn "add<mode>3_floatsi_68881" |
2766 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2767 | (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi")) | |
2768 | (match_operand:FP 1 "general_operand" "0")))] | |
c5c52bdc | 2769 | "TARGET_68881" |
3c904dda | 2770 | "f<FP:round>add%.l %2,%0" |
2771 | [(set_attr "type" "falu") | |
2772 | (set_attr "opy" "2")]) | |
c5c52bdc | 2773 | |
58c23110 | 2774 | (define_insn "add<mode>3_floathi_68881" |
2775 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2776 | (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn")) | |
2777 | (match_operand:FP 1 "general_operand" "0")))] | |
c5c52bdc | 2778 | "TARGET_68881" |
3c904dda | 2779 | "f<FP:round>add%.w %2,%0" |
2780 | [(set_attr "type" "falu") | |
2781 | (set_attr "opy" "2")]) | |
c5c52bdc | 2782 | |
58c23110 | 2783 | (define_insn "add<mode>3_floatqi_68881" |
2784 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2785 | (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn")) | |
2786 | (match_operand:FP 1 "general_operand" "0")))] | |
c5c52bdc | 2787 | "TARGET_68881" |
3c904dda | 2788 | "f<FP:round>add%.b %2,%0" |
2789 | [(set_attr "type" "falu") | |
2790 | (set_attr "opy" "2")]) | |
c5c52bdc | 2791 | |
58c23110 | 2792 | (define_insn "add<mode>3_68881" |
2793 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2794 | (plus:FP (match_operand:FP 1 "general_operand" "%0") | |
2795 | (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))] | |
c1dbe9ae | 2796 | "TARGET_68881" |
c1dbe9ae | 2797 | { |
58c23110 | 2798 | if (FP_REG_P (operands[2])) |
2799 | return "f<FP:round>add%.x %2,%0"; | |
2800 | return "f<FP:round>add%.<FP:prec> %f2,%0"; | |
3c904dda | 2801 | } |
2802 | [(set_attr "type" "falu") | |
2803 | (set_attr "opy" "2")]) | |
c1dbe9ae | 2804 | |
58c23110 | 2805 | (define_insn "add<mode>3_cf" |
2806 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2807 | (plus:FP (match_operand:FP 1 "general_operand" "%0") | |
2808 | (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))] | |
2809 | "TARGET_COLDFIRE_FPU" | |
c1dbe9ae | 2810 | { |
58c23110 | 2811 | if (FP_REG_P (operands[2])) |
6026414c | 2812 | return "f<FP:prec>add%.d %2,%0"; |
2813 | return "f<FP:prec>add%.<FP:prec> %2,%0"; | |
1d86aeab | 2814 | } |
3c904dda | 2815 | [(set_attr "type" "falu") |
2816 | (set_attr "opy" "2")]) | |
c1dbe9ae | 2817 | \f |
2818 | ;; subtract instructions | |
2819 | ||
ef64b201 | 2820 | (define_insn "subdi_sexthishl32" |
c4af10f0 | 2821 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d") |
3f6dfb87 | 2822 | (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0") |
2823 | (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm")) | |
5e4c76b7 | 2824 | (const_int 32)))) |
3f6dfb87 | 2825 | (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] |
960e6739 | 2826 | "!TARGET_COLDFIRE" |
5e4c76b7 | 2827 | { |
2828 | CC_STATUS_INIT; | |
ef64b201 | 2829 | if (ADDRESS_REG_P (operands[0])) |
2de9355b | 2830 | return "sub%.w %2,%0"; |
3f6dfb87 | 2831 | else if (ADDRESS_REG_P (operands[3])) |
2de9355b | 2832 | return "move%.w %2,%3\;sub%.l %3,%0"; |
ef64b201 | 2833 | else |
2de9355b | 2834 | return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0"; |
2835 | }) | |
5e4c76b7 | 2836 | |
2837 | (define_insn "subdi_dishl32" | |
c4af10f0 | 2838 | [(set (match_operand:DI 0 "nonimmediate_operand" "+ro") |
5e4c76b7 | 2839 | (minus:DI (match_dup 0) |
d08c9ad7 | 2840 | (ashift:DI (match_operand:DI 1 "general_operand" "ro") |
5e4c76b7 | 2841 | (const_int 32))))] |
2842 | "" | |
5e4c76b7 | 2843 | { |
2844 | CC_STATUS_INIT; | |
d08c9ad7 | 2845 | if (GET_CODE (operands[1]) == REG) |
e6b2f841 | 2846 | operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
d08c9ad7 | 2847 | else |
eafc6604 | 2848 | operands[1] = adjust_address (operands[1], SImode, 4); |
2de9355b | 2849 | return "sub%.l %1,%0"; |
1d86aeab | 2850 | } |
3c904dda | 2851 | [(set_attr "type" "alu_l")]) |
5e4c76b7 | 2852 | |
80925ff3 | 2853 | (define_insn "subdi3" |
b5489b01 | 2854 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d") |
2855 | (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0") | |
2856 | (match_operand:DI 2 "general_operand" "d,no>,d,a"))) | |
2857 | (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))] | |
5e4c76b7 | 2858 | "" |
5e4c76b7 | 2859 | { |
80925ff3 | 2860 | if (DATA_REG_P (operands[0])) |
d08c9ad7 | 2861 | { |
80925ff3 | 2862 | if (DATA_REG_P (operands[2])) |
2de9355b | 2863 | return "sub%.l %R2,%R0\;subx%.l %2,%0"; |
80925ff3 | 2864 | else if (GET_CODE (operands[2]) == MEM |
2865 | && GET_CODE (XEXP (operands[2], 0)) == POST_INC) | |
2866 | { | |
2de9355b | 2867 | return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0"; |
80925ff3 | 2868 | } |
2869 | else | |
2870 | { | |
7014838c | 2871 | rtx high, low; |
05b6e83e | 2872 | rtx xoperands[2]; |
7014838c | 2873 | |
80925ff3 | 2874 | if (GET_CODE (operands[2]) == REG) |
dc5ebe55 | 2875 | { |
7014838c | 2876 | low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
2877 | high = operands[2]; | |
dc5ebe55 | 2878 | } |
7014838c | 2879 | else if (CONSTANT_P (operands[2])) |
2880 | split_double (operands[2], &high, &low); | |
2881 | else | |
dc5ebe55 | 2882 | { |
eafc6604 | 2883 | low = adjust_address (operands[2], SImode, 4); |
7014838c | 2884 | high = operands[2]; |
dc5ebe55 | 2885 | } |
7014838c | 2886 | |
2887 | operands[1] = low, operands[2] = high; | |
05b6e83e | 2888 | xoperands[0] = operands[3]; |
03a04b74 | 2889 | if (GET_CODE (operands[1]) == CONST_INT |
2890 | && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) | |
2891 | xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1); | |
2892 | else | |
2893 | xoperands[1] = operands[2]; | |
7014838c | 2894 | |
05b6e83e | 2895 | output_asm_insn (output_move_simode (xoperands), xoperands); |
2896 | if (GET_CODE (operands[1]) == CONST_INT) | |
2897 | { | |
2898 | if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) | |
2de9355b | 2899 | return "subq%.l %1,%R0\;subx%.l %3,%0"; |
05b6e83e | 2900 | else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) |
2901 | { | |
2902 | operands[1] = GEN_INT (-INTVAL (operands[1])); | |
2de9355b | 2903 | return "addq%.l %1,%R0\;addx%.l %3,%0"; |
05b6e83e | 2904 | } |
2905 | } | |
2de9355b | 2906 | return "sub%.l %1,%R0\;subx%.l %3,%0"; |
80925ff3 | 2907 | } |
d08c9ad7 | 2908 | } |
84653e0f | 2909 | else |
5e4c76b7 | 2910 | { |
84653e0f | 2911 | gcc_assert (GET_CODE (operands[0]) == MEM); |
5e4c76b7 | 2912 | CC_STATUS_INIT; |
80925ff3 | 2913 | if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) |
2914 | { | |
e6b2f841 | 2915 | operands[1] |
29c05e22 | 2916 | = gen_rtx_MEM (SImode, plus_constant (Pmode, |
2917 | XEXP (operands[0], 0), -8)); | |
2de9355b | 2918 | return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1"; |
80925ff3 | 2919 | } |
2920 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2921 | { | |
2922 | operands[1] = XEXP(operands[0], 0); | |
2de9355b | 2923 | return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1"; |
80925ff3 | 2924 | } |
2925 | else | |
2926 | { | |
eafc6604 | 2927 | operands[1] = adjust_address (operands[0], SImode, 4); |
2de9355b | 2928 | return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0"; |
80925ff3 | 2929 | } |
5e4c76b7 | 2930 | } |
2de9355b | 2931 | }) |
5d3fef16 | 2932 | |
c1dbe9ae | 2933 | (define_insn "subsi3" |
1d86aeab | 2934 | [(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a") |
2935 | (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0") | |
2936 | (match_operand:SI 2 "general_src_operand" "I,dT,mSrT,mSrs")))] | |
c1dbe9ae | 2937 | "" |
1d86aeab | 2938 | "@ |
2939 | subq%.l %2, %0 | |
2940 | sub%.l %2,%0 | |
2941 | sub%.l %2,%0 | |
2942 | sub%.l %2,%0" | |
3c904dda | 2943 | [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l") |
1d86aeab | 2944 | (set_attr "opy" "2")]) |
c1dbe9ae | 2945 | |
2946 | (define_insn "" | |
c4af10f0 | 2947 | [(set (match_operand:SI 0 "nonimmediate_operand" "=a") |
c1dbe9ae | 2948 | (minus:SI (match_operand:SI 1 "general_operand" "0") |
2949 | (sign_extend:SI | |
f0ecff58 | 2950 | (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] |
960e6739 | 2951 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2952 | "sub%.w %2,%0") |
2953 | ||
2954 | (define_insn "subhi3" | |
c4af10f0 | 2955 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") |
c1dbe9ae | 2956 | (minus:HI (match_operand:HI 1 "general_operand" "0,0") |
f0ecff58 | 2957 | (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] |
960e6739 | 2958 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2959 | "sub%.w %2,%0") |
2960 | ||
2961 | (define_insn "" | |
c4af10f0 | 2962 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
c1dbe9ae | 2963 | (minus:HI (match_dup 0) |
f0ecff58 | 2964 | (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] |
960e6739 | 2965 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2966 | "sub%.w %1,%0") |
2967 | ||
2968 | (define_insn "subqi3" | |
c4af10f0 | 2969 | [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 2970 | (minus:QI (match_operand:QI 1 "general_operand" "0,0") |
f0ecff58 | 2971 | (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] |
960e6739 | 2972 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2973 | "sub%.b %2,%0") |
2974 | ||
2975 | (define_insn "" | |
c4af10f0 | 2976 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
c1dbe9ae | 2977 | (minus:QI (match_dup 0) |
f0ecff58 | 2978 | (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] |
960e6739 | 2979 | "!TARGET_COLDFIRE" |
c1dbe9ae | 2980 | "sub%.b %1,%0") |
2981 | ||
58c23110 | 2982 | (define_expand "sub<mode>3" |
2983 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
2984 | (minus:FP (match_operand:FP 1 "general_operand" "") | |
2985 | (match_operand:FP 2 "general_operand" "")))] | |
2986 | "TARGET_HARD_FLOAT" | |
c1dbe9ae | 2987 | "") |
2988 | ||
58c23110 | 2989 | (define_insn "sub<mode>3_floatsi_68881" |
2990 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
2991 | (minus:FP (match_operand:FP 1 "general_operand" "0") | |
2992 | (float:FP (match_operand:SI 2 "general_operand" "dmi"))))] | |
c5c52bdc | 2993 | "TARGET_68881" |
3c904dda | 2994 | "f<FP:round>sub%.l %2,%0" |
2995 | [(set_attr "type" "falu") | |
2996 | (set_attr "opy" "2")]) | |
c5c52bdc | 2997 | |
58c23110 | 2998 | (define_insn "sub<mode>3_floathi_68881" |
2999 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3000 | (minus:FP (match_operand:FP 1 "general_operand" "0") | |
3001 | (float:FP (match_operand:HI 2 "general_operand" "dmn"))))] | |
c5c52bdc | 3002 | "TARGET_68881" |
3c904dda | 3003 | "f<FP:round>sub%.w %2,%0" |
3004 | [(set_attr "type" "falu") | |
3005 | (set_attr "opy" "2")]) | |
c5c52bdc | 3006 | |
58c23110 | 3007 | (define_insn "sub<mode>3_floatqi_68881" |
3008 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3009 | (minus:FP (match_operand:FP 1 "general_operand" "0") | |
3010 | (float:FP (match_operand:QI 2 "general_operand" "dmn"))))] | |
c5c52bdc | 3011 | "TARGET_68881" |
3c904dda | 3012 | "f<FP:round>sub%.b %2,%0" |
3013 | [(set_attr "type" "falu") | |
3014 | (set_attr "opy" "2")]) | |
c5c52bdc | 3015 | |
58c23110 | 3016 | (define_insn "sub<mode>3_68881" |
3017 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3018 | (minus:FP (match_operand:FP 1 "general_operand" "0") | |
3019 | (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))] | |
c1dbe9ae | 3020 | "TARGET_68881" |
c1dbe9ae | 3021 | { |
58c23110 | 3022 | if (FP_REG_P (operands[2])) |
3023 | return "f<FP:round>sub%.x %2,%0"; | |
3024 | return "f<FP:round>sub%.<FP:prec> %f2,%0"; | |
3c904dda | 3025 | } |
3026 | [(set_attr "type" "falu") | |
3027 | (set_attr "opy" "2")]) | |
c1dbe9ae | 3028 | |
58c23110 | 3029 | (define_insn "sub<mode>3_cf" |
3030 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3031 | (minus:FP (match_operand:FP 1 "general_operand" "0") | |
3032 | (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))] | |
3033 | "TARGET_COLDFIRE_FPU" | |
c1dbe9ae | 3034 | { |
58c23110 | 3035 | if (FP_REG_P (operands[2])) |
6026414c | 3036 | return "f<FP:prec>sub%.d %2,%0"; |
3037 | return "f<FP:prec>sub%.<FP:prec> %2,%0"; | |
1d86aeab | 3038 | } |
3c904dda | 3039 | [(set_attr "type" "falu") |
3040 | (set_attr "opy" "2")]) | |
c1dbe9ae | 3041 | \f |
3042 | ;; multiply instructions | |
3043 | ||
3044 | (define_insn "mulhi3" | |
c4af10f0 | 3045 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3046 | (mult:HI (match_operand:HI 1 "general_operand" "%0") |
f0ecff58 | 3047 | (match_operand:HI 2 "general_src_operand" "dmSn")))] |
c1dbe9ae | 3048 | "" |
4ad53767 | 3049 | { |
3050 | return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; | |
3051 | } | |
3c904dda | 3052 | [(set_attr "type" "mul_w") |
1d86aeab | 3053 | (set_attr "opy" "2")]) |
c1dbe9ae | 3054 | |
3055 | (define_insn "mulhisi3" | |
c4af10f0 | 3056 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3057 | (mult:SI (sign_extend:SI |
3058 | (match_operand:HI 1 "nonimmediate_operand" "%0")) | |
3059 | (sign_extend:SI | |
f0ecff58 | 3060 | (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))] |
c1dbe9ae | 3061 | "" |
4ad53767 | 3062 | { |
3063 | return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; | |
3064 | } | |
3c904dda | 3065 | [(set_attr "type" "mul_w") |
1d86aeab | 3066 | (set_attr "opy" "2")]) |
c1dbe9ae | 3067 | |
1d86aeab | 3068 | (define_insn "*mulhisisi3_s" |
c4af10f0 | 3069 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3070 | (mult:SI (sign_extend:SI |
3071 | (match_operand:HI 1 "nonimmediate_operand" "%0")) | |
3072 | (match_operand:SI 2 "const_int_operand" "n")))] | |
21b49265 | 3073 | "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff" |
4ad53767 | 3074 | { |
3075 | return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; | |
3076 | } | |
3c904dda | 3077 | [(set_attr "type" "mul_w") |
1d86aeab | 3078 | (set_attr "opy" "2")]) |
c1dbe9ae | 3079 | |
a5667aaa | 3080 | (define_expand "mulsi3" |
c4af10f0 | 3081 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
a5667aaa | 3082 | (mult:SI (match_operand:SI 1 "general_operand" "") |
3083 | (match_operand:SI 2 "general_operand" "")))] | |
960e6739 | 3084 | "TARGET_68020 || TARGET_COLDFIRE" |
a5667aaa | 3085 | "") |
3086 | ||
1d86aeab | 3087 | (define_insn "*mulsi3_68020" |
c4af10f0 | 3088 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3089 | (mult:SI (match_operand:SI 1 "general_operand" "%0") |
f0ecff58 | 3090 | (match_operand:SI 2 "general_src_operand" "dmSTK")))] |
3091 | ||
a5667aaa | 3092 | "TARGET_68020" |
1d86aeab | 3093 | "muls%.l %2,%0" |
3c904dda | 3094 | [(set_attr "type" "mul_l") |
1d86aeab | 3095 | (set_attr "opy" "2")]) |
a5667aaa | 3096 | |
1d86aeab | 3097 | (define_insn "*mulsi3_cf" |
c4af10f0 | 3098 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
a5667aaa | 3099 | (mult:SI (match_operand:SI 1 "general_operand" "%0") |
4aab5c05 | 3100 | (match_operand:SI 2 "general_operand" "d<Q>")))] |
960e6739 | 3101 | "TARGET_COLDFIRE" |
1d86aeab | 3102 | "muls%.l %2,%0" |
3c904dda | 3103 | [(set_attr "type" "mul_l") |
1d86aeab | 3104 | (set_attr "opy" "2")]) |
c1dbe9ae | 3105 | |
3106 | (define_insn "umulhisi3" | |
c4af10f0 | 3107 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3108 | (mult:SI (zero_extend:SI |
3109 | (match_operand:HI 1 "nonimmediate_operand" "%0")) | |
3110 | (zero_extend:SI | |
f0ecff58 | 3111 | (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))] |
c1dbe9ae | 3112 | "" |
4ad53767 | 3113 | { |
3114 | return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0"; | |
3115 | } | |
3c904dda | 3116 | [(set_attr "type" "mul_w") |
1d86aeab | 3117 | (set_attr "opy" "2")]) |
c1dbe9ae | 3118 | |
1d86aeab | 3119 | (define_insn "*mulhisisi3_z" |
c4af10f0 | 3120 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3121 | (mult:SI (zero_extend:SI |
3122 | (match_operand:HI 1 "nonimmediate_operand" "%0")) | |
3123 | (match_operand:SI 2 "const_int_operand" "n")))] | |
fd0d78ff | 3124 | "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff" |
4ad53767 | 3125 | { |
3126 | return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0"; | |
3127 | } | |
3c904dda | 3128 | [(set_attr "type" "mul_w") |
1d86aeab | 3129 | (set_attr "opy" "2")]) |
c1dbe9ae | 3130 | |
3131 | ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the | |
3132 | ;; proper matching constraint. This is because the matching is between | |
3133 | ;; the high-numbered word of the DImode operand[0] and operand[1]. | |
3134 | (define_expand "umulsidi3" | |
3135 | [(parallel | |
701e46d0 | 3136 | [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4) |
fd0d78ff | 3137 | (mult:SI (match_operand:SI 1 "register_operand" "") |
aadef98c | 3138 | (match_operand:SI 2 "register_operand" ""))) |
c1dbe9ae | 3139 | (set (subreg:SI (match_dup 0) 0) |
fd0d78ff | 3140 | (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) |
3141 | (zero_extend:DI (match_dup 2))) | |
3142 | (const_int 32))))])] | |
bd40163f | 3143 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
c1dbe9ae | 3144 | "") |
3145 | ||
3146 | (define_insn "" | |
3147 | [(set (match_operand:SI 0 "register_operand" "=d") | |
fd0d78ff | 3148 | (mult:SI (match_operand:SI 1 "register_operand" "%0") |
3149 | (match_operand:SI 2 "nonimmediate_operand" "dm"))) | |
c1dbe9ae | 3150 | (set (match_operand:SI 3 "register_operand" "=d") |
fd0d78ff | 3151 | (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) |
3152 | (zero_extend:DI (match_dup 2))) | |
3153 | (const_int 32))))] | |
bd40163f | 3154 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
c1dbe9ae | 3155 | "mulu%.l %2,%3:%0") |
3156 | ||
579d2406 | 3157 | ; Match immediate case. For 2.4 only match things < 2^31. |
3158 | ; It's tricky with larger values in these patterns since we need to match | |
3159 | ; values between the two parallel multiplies, between a CONST_DOUBLE and | |
3160 | ; a CONST_INT. | |
28b4e224 | 3161 | (define_insn "" |
3162 | [(set (match_operand:SI 0 "register_operand" "=d") | |
fd0d78ff | 3163 | (mult:SI (match_operand:SI 1 "register_operand" "%0") |
579d2406 | 3164 | (match_operand:SI 2 "const_int_operand" "n"))) |
28b4e224 | 3165 | (set (match_operand:SI 3 "register_operand" "=d") |
fd0d78ff | 3166 | (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) |
3167 | (match_dup 2)) | |
3168 | (const_int 32))))] | |
bd40163f | 3169 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE |
579d2406 | 3170 | && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" |
28b4e224 | 3171 | "mulu%.l %2,%3:%0") |
3172 | ||
c1dbe9ae | 3173 | (define_expand "mulsidi3" |
3174 | [(parallel | |
701e46d0 | 3175 | [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4) |
fd0d78ff | 3176 | (mult:SI (match_operand:SI 1 "register_operand" "") |
aadef98c | 3177 | (match_operand:SI 2 "register_operand" ""))) |
c1dbe9ae | 3178 | (set (subreg:SI (match_dup 0) 0) |
374e01d1 | 3179 | (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) |
3180 | (sign_extend:DI (match_dup 2))) | |
3181 | (const_int 32))))])] | |
bd40163f | 3182 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
c1dbe9ae | 3183 | "") |
3184 | ||
3185 | (define_insn "" | |
3186 | [(set (match_operand:SI 0 "register_operand" "=d") | |
fd0d78ff | 3187 | (mult:SI (match_operand:SI 1 "register_operand" "%0") |
3188 | (match_operand:SI 2 "nonimmediate_operand" "dm"))) | |
c1dbe9ae | 3189 | (set (match_operand:SI 3 "register_operand" "=d") |
374e01d1 | 3190 | (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) |
3191 | (sign_extend:DI (match_dup 2))) | |
3192 | (const_int 32))))] | |
bd40163f | 3193 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
c1dbe9ae | 3194 | "muls%.l %2,%3:%0") |
3195 | ||
28b4e224 | 3196 | (define_insn "" |
3197 | [(set (match_operand:SI 0 "register_operand" "=d") | |
fd0d78ff | 3198 | (mult:SI (match_operand:SI 1 "register_operand" "%0") |
368ff7c0 | 3199 | (match_operand:SI 2 "const_int_operand" "n"))) |
28b4e224 | 3200 | (set (match_operand:SI 3 "register_operand" "=d") |
374e01d1 | 3201 | (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) |
3202 | (match_dup 2)) | |
3203 | (const_int 32))))] | |
bd40163f | 3204 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
28b4e224 | 3205 | "muls%.l %2,%3:%0") |
3206 | ||
1a4c1f7c | 3207 | (define_expand "umulsi3_highpart" |
3208 | [(parallel | |
3209 | [(set (match_operand:SI 0 "register_operand" "") | |
3210 | (truncate:SI | |
3211 | (lshiftrt:DI | |
3212 | (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) | |
3213 | (zero_extend:DI (match_operand:SI 2 "general_operand" ""))) | |
3214 | (const_int 32)))) | |
3215 | (clobber (match_dup 3))])] | |
bd40163f | 3216 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
1a4c1f7c | 3217 | { |
3218 | operands[3] = gen_reg_rtx (SImode); | |
368ff7c0 | 3219 | |
3220 | if (GET_CODE (operands[2]) == CONST_INT) | |
1a4c1f7c | 3221 | { |
368ff7c0 | 3222 | operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff, |
3223 | 0, DImode); | |
3224 | ||
f8fff87d | 3225 | /* We have to adjust the operand order for the matching constraints. */ |
1a4c1f7c | 3226 | emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3], |
3227 | operands[1], operands[2])); | |
3228 | DONE; | |
3229 | } | |
f5f2db69 | 3230 | }) |
1a4c1f7c | 3231 | |
3232 | (define_insn "" | |
345d5057 | 3233 | [(set (match_operand:SI 0 "register_operand" "=d") |
1a4c1f7c | 3234 | (truncate:SI |
3235 | (lshiftrt:DI | |
3236 | (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1")) | |
3237 | (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) | |
3238 | (const_int 32)))) | |
3239 | (clobber (match_operand:SI 1 "register_operand" "=d"))] | |
bd40163f | 3240 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
1a4c1f7c | 3241 | "mulu%.l %3,%0:%1") |
3242 | ||
3243 | (define_insn "const_umulsi3_highpart" | |
345d5057 | 3244 | [(set (match_operand:SI 0 "register_operand" "=d") |
1a4c1f7c | 3245 | (truncate:SI |
3246 | (lshiftrt:DI | |
3247 | (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1")) | |
368ff7c0 | 3248 | (match_operand:DI 3 "const_uint32_operand" "n")) |
1a4c1f7c | 3249 | (const_int 32)))) |
3250 | (clobber (match_operand:SI 1 "register_operand" "=d"))] | |
bd40163f | 3251 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
1a4c1f7c | 3252 | "mulu%.l %3,%0:%1") |
3253 | ||
3254 | (define_expand "smulsi3_highpart" | |
3255 | [(parallel | |
3256 | [(set (match_operand:SI 0 "register_operand" "") | |
3257 | (truncate:SI | |
3258 | (lshiftrt:DI | |
3259 | (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) | |
3260 | (sign_extend:DI (match_operand:SI 2 "general_operand" ""))) | |
3261 | (const_int 32)))) | |
3262 | (clobber (match_dup 3))])] | |
bd40163f | 3263 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
1a4c1f7c | 3264 | { |
3265 | operands[3] = gen_reg_rtx (SImode); | |
368ff7c0 | 3266 | if (GET_CODE (operands[2]) == CONST_INT) |
1a4c1f7c | 3267 | { |
f8fff87d | 3268 | /* We have to adjust the operand order for the matching constraints. */ |
1a4c1f7c | 3269 | emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3], |
3270 | operands[1], operands[2])); | |
3271 | DONE; | |
3272 | } | |
f5f2db69 | 3273 | }) |
1a4c1f7c | 3274 | |
3275 | (define_insn "" | |
345d5057 | 3276 | [(set (match_operand:SI 0 "register_operand" "=d") |
1a4c1f7c | 3277 | (truncate:SI |
3278 | (lshiftrt:DI | |
3279 | (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1")) | |
3280 | (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) | |
3281 | (const_int 32)))) | |
3282 | (clobber (match_operand:SI 1 "register_operand" "=d"))] | |
bd40163f | 3283 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
1a4c1f7c | 3284 | "muls%.l %3,%0:%1") |
3285 | ||
3286 | (define_insn "const_smulsi3_highpart" | |
345d5057 | 3287 | [(set (match_operand:SI 0 "register_operand" "=d") |
1a4c1f7c | 3288 | (truncate:SI |
3289 | (lshiftrt:DI | |
3290 | (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1")) | |
368ff7c0 | 3291 | (match_operand:DI 3 "const_sint32_operand" "n")) |
1a4c1f7c | 3292 | (const_int 32)))) |
3293 | (clobber (match_operand:SI 1 "register_operand" "=d"))] | |
bd40163f | 3294 | "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" |
1a4c1f7c | 3295 | "muls%.l %3,%0:%1") |
3296 | ||
58c23110 | 3297 | (define_expand "mul<mode>3" |
3298 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
3299 | (mult:FP (match_operand:FP 1 "general_operand" "") | |
3300 | (match_operand:FP 2 "general_operand" "")))] | |
3301 | "TARGET_HARD_FLOAT" | |
c1dbe9ae | 3302 | "") |
3303 | ||
58c23110 | 3304 | (define_insn "mul<mode>3_floatsi_68881" |
3305 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3306 | (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi")) | |
3307 | (match_operand:FP 1 "general_operand" "0")))] | |
c5c52bdc | 3308 | "TARGET_68881" |
58c23110 | 3309 | { |
6e6d2086 | 3310 | return TARGET_68040 |
58c23110 | 3311 | ? "f<FP:round>mul%.l %2,%0" |
3312 | : "f<FP:round_mul>mul%.l %2,%0"; | |
3c904dda | 3313 | } |
3314 | [(set_attr "type" "fmul") | |
3315 | (set_attr "opy" "2")]) | |
c5c52bdc | 3316 | |
58c23110 | 3317 | (define_insn "mul<mode>3_floathi_68881" |
3318 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3319 | (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn")) | |
3320 | (match_operand:FP 1 "general_operand" "0")))] | |
c5c52bdc | 3321 | "TARGET_68881" |
58c23110 | 3322 | { |
6e6d2086 | 3323 | return TARGET_68040 |
58c23110 | 3324 | ? "f<FP:round>mul%.w %2,%0" |
3325 | : "f<FP:round_mul>mul%.w %2,%0"; | |
3c904dda | 3326 | } |
3327 | [(set_attr "type" "fmul") | |
3328 | (set_attr "opy" "2")]) | |
c5c52bdc | 3329 | |
58c23110 | 3330 | (define_insn "mul<mode>3_floatqi_68881" |
3331 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3332 | (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn")) | |
3333 | (match_operand:FP 1 "general_operand" "0")))] | |
c5c52bdc | 3334 | "TARGET_68881" |
58c23110 | 3335 | { |
6e6d2086 | 3336 | return TARGET_68040 |
58c23110 | 3337 | ? "f<FP:round>mul%.b %2,%0" |
3338 | : "f<FP:round_mul>mul%.b %2,%0"; | |
3c904dda | 3339 | } |
3340 | [(set_attr "type" "fmul") | |
3341 | (set_attr "opy" "2")]) | |
c5c52bdc | 3342 | |
58c23110 | 3343 | (define_insn "muldf_68881" |
c4af10f0 | 3344 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f") |
c1dbe9ae | 3345 | (mult:DF (match_operand:DF 1 "general_operand" "%0") |
3346 | (match_operand:DF 2 "general_operand" "fmG")))] | |
3347 | "TARGET_68881" | |
c1dbe9ae | 3348 | { |
3349 | if (GET_CODE (operands[2]) == CONST_DOUBLE | |
f716b74b | 3350 | && floating_exact_log2 (operands[2]) && !TUNE_68040_60) |
c1dbe9ae | 3351 | { |
3352 | int i = floating_exact_log2 (operands[2]); | |
e6b2f841 | 3353 | operands[2] = GEN_INT (i); |
2de9355b | 3354 | return "fscale%.l %2,%0"; |
c1dbe9ae | 3355 | } |
3356 | if (REG_P (operands[2])) | |
2de9355b | 3357 | return "f%&mul%.x %2,%0"; |
3358 | return "f%&mul%.d %f2,%0"; | |
3359 | }) | |
c1dbe9ae | 3360 | |
58c23110 | 3361 | (define_insn "mulsf_68881" |
c4af10f0 | 3362 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f") |
c1dbe9ae | 3363 | (mult:SF (match_operand:SF 1 "general_operand" "%0") |
3364 | (match_operand:SF 2 "general_operand" "fdmF")))] | |
3365 | "TARGET_68881" | |
c1dbe9ae | 3366 | { |
58c23110 | 3367 | if (FP_REG_P (operands[2])) |
6e6d2086 | 3368 | return (TARGET_68040 |
2de9355b | 3369 | ? "fsmul%.x %2,%0" |
3370 | : "fsglmul%.x %2,%0"); | |
6e6d2086 | 3371 | return (TARGET_68040 |
2de9355b | 3372 | ? "fsmul%.s %f2,%0" |
3373 | : "fsglmul%.s %f2,%0"); | |
3374 | }) | |
c1dbe9ae | 3375 | |
58c23110 | 3376 | (define_insn "mulxf3_68881" |
3377 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f") | |
3378 | (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0") | |
3379 | (match_operand:XF 2 "nonimmediate_operand" "fm")))] | |
c5c52bdc | 3380 | "TARGET_68881" |
58c23110 | 3381 | { |
3382 | return "fmul%.x %f2,%0"; | |
3383 | }) | |
c5c52bdc | 3384 | |
58c23110 | 3385 | (define_insn "fmul<mode>3_cf" |
3386 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3387 | (mult:FP (match_operand:FP 1 "general_operand" "%0") | |
3388 | (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))] | |
3389 | "TARGET_COLDFIRE_FPU" | |
c1dbe9ae | 3390 | { |
58c23110 | 3391 | if (FP_REG_P (operands[2])) |
3392 | return "f<FP:prec>mul%.d %2,%0"; | |
3393 | return "f<FP:prec>mul%.<FP:prec> %2,%0"; | |
1d86aeab | 3394 | } |
3c904dda | 3395 | [(set_attr "type" "fmul") |
3396 | (set_attr "opy" "2")]) | |
58c23110 | 3397 | \f |
3398 | ;; divide instructions | |
c1dbe9ae | 3399 | |
58c23110 | 3400 | (define_expand "div<mode>3" |
3401 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
3402 | (div:FP (match_operand:FP 1 "general_operand" "") | |
3403 | (match_operand:FP 2 "general_operand" "")))] | |
3404 | "TARGET_HARD_FLOAT" | |
c1dbe9ae | 3405 | "") |
3406 | ||
58c23110 | 3407 | (define_insn "div<mode>3_floatsi_68881" |
3408 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3409 | (div:FP (match_operand:FP 1 "general_operand" "0") | |
3410 | (float:FP (match_operand:SI 2 "general_operand" "dmi"))))] | |
c5c52bdc | 3411 | "TARGET_68881" |
c5c52bdc | 3412 | { |
6e6d2086 | 3413 | return TARGET_68040 |
58c23110 | 3414 | ? "f<FP:round>div%.l %2,%0" |
3415 | : "f<FP:round_mul>div%.l %2,%0"; | |
2de9355b | 3416 | }) |
c5c52bdc | 3417 | |
58c23110 | 3418 | (define_insn "div<mode>3_floathi_68881" |
3419 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3420 | (div:FP (match_operand:FP 1 "general_operand" "0") | |
3421 | (float:FP (match_operand:HI 2 "general_operand" "dmn"))))] | |
c5c52bdc | 3422 | "TARGET_68881" |
c5c52bdc | 3423 | { |
6e6d2086 | 3424 | return TARGET_68040 |
58c23110 | 3425 | ? "f<FP:round>div%.w %2,%0" |
3426 | : "f<FP:round_mul>div%.w %2,%0"; | |
2de9355b | 3427 | }) |
c5c52bdc | 3428 | |
58c23110 | 3429 | (define_insn "div<mode>3_floatqi_68881" |
3430 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3431 | (div:FP (match_operand:FP 1 "general_operand" "0") | |
3432 | (float:FP (match_operand:QI 2 "general_operand" "dmn"))))] | |
c5c52bdc | 3433 | "TARGET_68881" |
c5c52bdc | 3434 | { |
6e6d2086 | 3435 | return TARGET_68040 |
58c23110 | 3436 | ? "f<FP:round>div%.b %2,%0" |
3437 | : "f<FP:round_mul>div%.b %2,%0"; | |
2de9355b | 3438 | }) |
c5c52bdc | 3439 | |
58c23110 | 3440 | (define_insn "div<mode>3_68881" |
3441 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3442 | (div:FP (match_operand:FP 1 "general_operand" "0") | |
3443 | (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))] | |
c1dbe9ae | 3444 | "TARGET_68881" |
c1dbe9ae | 3445 | { |
58c23110 | 3446 | if (FP_REG_P (operands[2])) |
6e6d2086 | 3447 | return (TARGET_68040 |
58c23110 | 3448 | ? "f<FP:round>div%.x %2,%0" |
3449 | : "f<FP:round_mul>div%.x %2,%0"); | |
6e6d2086 | 3450 | return (TARGET_68040 |
58c23110 | 3451 | ? "f<FP:round>div%.<FP:prec> %f2,%0" |
3452 | : "f<FP:round_mul>div%.<FP:prec> %f2,%0"); | |
3453 | }) | |
3454 | ||
3455 | (define_insn "div<mode>3_cf" | |
3456 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
3457 | (div:FP (match_operand:FP 1 "general_operand" "0") | |
3458 | (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))] | |
3459 | "TARGET_COLDFIRE_FPU" | |
3460 | { | |
3461 | if (FP_REG_P (operands[2])) | |
3462 | return "f<FP:prec>div%.d %2,%0"; | |
3463 | return "f<FP:prec>div%.<FP:prec> %2,%0"; | |
1d86aeab | 3464 | } |
3c904dda | 3465 | [(set_attr "type" "fdiv") |
3466 | (set_attr "opy" "2")]) | |
c1dbe9ae | 3467 | \f |
3468 | ;; Remainder instructions. | |
3469 | ||
960e6739 | 3470 | (define_expand "divmodsi4" |
3471 | [(parallel | |
3472 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
3473 | (div:SI (match_operand:SI 1 "general_operand" "") | |
3474 | (match_operand:SI 2 "general_src_operand" ""))) | |
3475 | (set (match_operand:SI 3 "nonimmediate_operand" "") | |
3476 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
3477 | "TARGET_68020 || TARGET_CF_HWDIV" | |
3478 | "") | |
3479 | ||
3480 | (define_insn "" | |
3481 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
3482 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
3483 | (match_operand:SI 2 "general_src_operand" "d<Q>U"))) | |
3484 | (set (match_operand:SI 3 "nonimmediate_operand" "=&d") | |
3485 | (mod:SI (match_dup 1) (match_dup 2)))] | |
3486 | "TARGET_CF_HWDIV" | |
960e6739 | 3487 | { |
3488 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
2de9355b | 3489 | return "divs%.l %2,%0"; |
960e6739 | 3490 | else if (find_reg_note (insn, REG_UNUSED, operands[0])) |
2de9355b | 3491 | return "rems%.l %2,%3:%0"; |
960e6739 | 3492 | else |
2de9355b | 3493 | return "rems%.l %2,%3:%0\;divs%.l %2,%0"; |
3c904dda | 3494 | } |
3495 | [(set_attr "type" "div_l") | |
3496 | (set_attr "opy" "2")]) | |
960e6739 | 3497 | |
3498 | (define_insn "" | |
c4af10f0 | 3499 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3500 | (div:SI (match_operand:SI 1 "general_operand" "0") |
f0ecff58 | 3501 | (match_operand:SI 2 "general_src_operand" "dmSTK"))) |
c4af10f0 | 3502 | (set (match_operand:SI 3 "nonimmediate_operand" "=d") |
c1dbe9ae | 3503 | (mod:SI (match_dup 1) (match_dup 2)))] |
960e6739 | 3504 | "TARGET_68020" |
c1dbe9ae | 3505 | { |
3506 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
2de9355b | 3507 | return "divs%.l %2,%0"; |
c1dbe9ae | 3508 | else |
2de9355b | 3509 | return "divsl%.l %2,%3:%0"; |
3510 | }) | |
c1dbe9ae | 3511 | |
960e6739 | 3512 | (define_expand "udivmodsi4" |
3513 | [(parallel | |
3514 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
3515 | (udiv:SI (match_operand:SI 1 "general_operand" "0") | |
3516 | (match_operand:SI 2 "general_src_operand" "dmSTK"))) | |
3517 | (set (match_operand:SI 3 "nonimmediate_operand" "=d") | |
3518 | (umod:SI (match_dup 1) (match_dup 2)))])] | |
3519 | "TARGET_68020 || TARGET_CF_HWDIV" | |
3520 | "") | |
3521 | ||
3522 | (define_insn "" | |
3523 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
3524 | (udiv:SI (match_operand:SI 1 "general_operand" "0") | |
3525 | (match_operand:SI 2 "general_src_operand" "d<Q>U"))) | |
3526 | (set (match_operand:SI 3 "nonimmediate_operand" "=&d") | |
3527 | (umod:SI (match_dup 1) (match_dup 2)))] | |
3528 | "TARGET_CF_HWDIV" | |
960e6739 | 3529 | { |
3530 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
2de9355b | 3531 | return "divu%.l %2,%0"; |
960e6739 | 3532 | else if (find_reg_note (insn, REG_UNUSED, operands[0])) |
2de9355b | 3533 | return "remu%.l %2,%3:%0"; |
960e6739 | 3534 | else |
2de9355b | 3535 | return "remu%.l %2,%3:%0\;divu%.l %2,%0"; |
3c904dda | 3536 | } |
3537 | [(set_attr "type" "div_l") | |
3538 | (set_attr "opy" "2")]) | |
960e6739 | 3539 | |
3540 | (define_insn "" | |
c4af10f0 | 3541 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
c1dbe9ae | 3542 | (udiv:SI (match_operand:SI 1 "general_operand" "0") |
f0ecff58 | 3543 | (match_operand:SI 2 "general_src_operand" "dmSTK"))) |
c4af10f0 | 3544 | (set (match_operand:SI 3 "nonimmediate_operand" "=d") |
c1dbe9ae | 3545 | (umod:SI (match_dup 1) (match_dup 2)))] |
960e6739 | 3546 | "TARGET_68020 && !TARGET_COLDFIRE" |
c1dbe9ae | 3547 | { |
3548 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
2de9355b | 3549 | return "divu%.l %2,%0"; |
c1dbe9ae | 3550 | else |
2de9355b | 3551 | return "divul%.l %2,%3:%0"; |
3552 | }) | |
d9b5fe6f | 3553 | |
3554 | (define_insn "divmodhi4" | |
c4af10f0 | 3555 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d") |
d9b5fe6f | 3556 | (div:HI (match_operand:HI 1 "general_operand" "0") |
f0ecff58 | 3557 | (match_operand:HI 2 "general_src_operand" "dmSKT"))) |
c4af10f0 | 3558 | (set (match_operand:HI 3 "nonimmediate_operand" "=d") |
d9b5fe6f | 3559 | (mod:HI (match_dup 1) (match_dup 2)))] |
960e6739 | 3560 | "!TARGET_COLDFIRE || TARGET_CF_HWDIV" |
d9b5fe6f | 3561 | { |
4ad53767 | 3562 | output_asm_insn (MOTOROLA ? |
3563 | "ext%.l %0\;divs%.w %2,%0" : | |
3564 | "extl %0\;divs %2,%0", | |
3565 | operands); | |
d9b5fe6f | 3566 | if (!find_reg_note(insn, REG_UNUSED, operands[3])) |
3567 | { | |
3568 | CC_STATUS_INIT; | |
2de9355b | 3569 | return "move%.l %0,%3\;swap %3"; |
d9b5fe6f | 3570 | } |
3571 | else | |
2de9355b | 3572 | return ""; |
3573 | }) | |
d9b5fe6f | 3574 | |
3575 | (define_insn "udivmodhi4" | |
c4af10f0 | 3576 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d") |
d9b5fe6f | 3577 | (udiv:HI (match_operand:HI 1 "general_operand" "0") |
f0ecff58 | 3578 | (match_operand:HI 2 "general_src_operand" "dmSKT"))) |
c4af10f0 | 3579 | (set (match_operand:HI 3 "nonimmediate_operand" "=d") |
d9b5fe6f | 3580 | (umod:HI (match_dup 1) (match_dup 2)))] |
960e6739 | 3581 | "!TARGET_COLDFIRE || TARGET_CF_HWDIV" |
d9b5fe6f | 3582 | { |
da8fbdfe | 3583 | if (ISA_HAS_MVS_MVZ) |
4ad53767 | 3584 | output_asm_insn (MOTOROLA ? |
3585 | "mvz%.w %0,%0\;divu%.w %2,%0" : | |
3586 | "mvz%.w %0,%0\;divu %2,%0", | |
3587 | operands); | |
0c4bc85a | 3588 | else |
4ad53767 | 3589 | output_asm_insn (MOTOROLA ? |
3590 | "and%.l #0xFFFF,%0\;divu%.w %2,%0" : | |
3591 | "and%.l #0xFFFF,%0\;divu %2,%0", | |
3592 | operands); | |
0c4bc85a | 3593 | |
d9b5fe6f | 3594 | if (!find_reg_note(insn, REG_UNUSED, operands[3])) |
3595 | { | |
3596 | CC_STATUS_INIT; | |
2de9355b | 3597 | return "move%.l %0,%3\;swap %3"; |
d9b5fe6f | 3598 | } |
3599 | else | |
2de9355b | 3600 | return ""; |
3601 | }) | |
c1dbe9ae | 3602 | \f |
3603 | ;; logical-and instructions | |
3604 | ||
3605 | ;; Prevent AND from being made with sp. This doesn't exist in the machine | |
3606 | ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we | |
bdf74c8a | 3607 | ;; can't allocate pseudos into it. |
83f6afc2 | 3608 | |
3609 | (define_expand "andsi3" | |
f0ecff58 | 3610 | [(set (match_operand:SI 0 "not_sp_operand" "") |
3611 | (and:SI (match_operand:SI 1 "general_operand" "") | |
3612 | (match_operand:SI 2 "general_src_operand" "")))] | |
c1dbe9ae | 3613 | "" |
83f6afc2 | 3614 | "") |
3615 | ||
e2eeb731 | 3616 | ;; produced by split operations after reload finished |
3617 | (define_insn "*andsi3_split" | |
3618 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3619 | (and:SI (match_operand:SI 1 "register_operand" "0") | |
3620 | (match_operand:SI 2 "const_int_operand" "i")))] | |
3621 | "reload_completed && !TARGET_COLDFIRE" | |
3622 | { | |
3623 | return output_andsi3 (operands); | |
3624 | }) | |
3625 | ||
83f6afc2 | 3626 | (define_insn "andsi3_internal" |
3627 | [(set (match_operand:SI 0 "not_sp_operand" "=m,d") | |
3628 | (and:SI (match_operand:SI 1 "general_operand" "%0,0") | |
f0ecff58 | 3629 | (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))] |
960e6739 | 3630 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3631 | { |
dc5ebe55 | 3632 | return output_andsi3 (operands); |
2de9355b | 3633 | }) |
c1dbe9ae | 3634 | |
83f6afc2 | 3635 | (define_insn "andsi3_5200" |
3636 | [(set (match_operand:SI 0 "not_sp_operand" "=m,d") | |
3637 | (and:SI (match_operand:SI 1 "general_operand" "%0,0") | |
f0ecff58 | 3638 | (match_operand:SI 2 "general_src_operand" "d,dmsK")))] |
960e6739 | 3639 | "TARGET_COLDFIRE" |
0c4bc85a | 3640 | { |
da8fbdfe | 3641 | if (ISA_HAS_MVS_MVZ |
42af5438 | 3642 | && DATA_REG_P (operands[0]) |
0c4bc85a | 3643 | && GET_CODE (operands[2]) == CONST_INT) |
3644 | { | |
3645 | if (INTVAL (operands[2]) == 0x000000ff) | |
f5f2db69 | 3646 | return "mvz%.b %0,%0"; |
0c4bc85a | 3647 | else if (INTVAL (operands[2]) == 0x0000ffff) |
f5f2db69 | 3648 | return "mvz%.w %0,%0"; |
0c4bc85a | 3649 | } |
3650 | return output_andsi3 (operands); | |
3651 | }) | |
83f6afc2 | 3652 | |
c1dbe9ae | 3653 | (define_insn "andhi3" |
c4af10f0 | 3654 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 3655 | (and:HI (match_operand:HI 1 "general_operand" "%0,0") |
f0ecff58 | 3656 | (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3657 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3658 | "and%.w %2,%0") |
3659 | ||
a45d833a | 3660 | (define_insn "" |
c4af10f0 | 3661 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
a45d833a | 3662 | (and:HI (match_dup 0) |
f0ecff58 | 3663 | (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3664 | "!TARGET_COLDFIRE" |
a45d833a | 3665 | "and%.w %1,%0") |
3666 | ||
3667 | (define_insn "" | |
c4af10f0 | 3668 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
f0ecff58 | 3669 | (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") |
a45d833a | 3670 | (match_dup 0)))] |
960e6739 | 3671 | "!TARGET_COLDFIRE" |
a45d833a | 3672 | "and%.w %1,%0") |
3673 | ||
c1dbe9ae | 3674 | (define_insn "andqi3" |
c4af10f0 | 3675 | [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 3676 | (and:QI (match_operand:QI 1 "general_operand" "%0,0") |
f0ecff58 | 3677 | (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3678 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3679 | "and%.b %2,%0") |
3680 | ||
a45d833a | 3681 | (define_insn "" |
c4af10f0 | 3682 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
a45d833a | 3683 | (and:QI (match_dup 0) |
f0ecff58 | 3684 | (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3685 | "!TARGET_COLDFIRE" |
a45d833a | 3686 | "and%.b %1,%0") |
3687 | ||
3688 | (define_insn "" | |
c4af10f0 | 3689 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
f0ecff58 | 3690 | (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") |
a45d833a | 3691 | (match_dup 0)))] |
960e6739 | 3692 | "!TARGET_COLDFIRE" |
a45d833a | 3693 | "and%.b %1,%0") |
c1dbe9ae | 3694 | \f |
3695 | ;; inclusive-or instructions | |
3696 | ||
43b24f37 | 3697 | (define_insn "iordi_zext" |
c4af10f0 | 3698 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") |
43b24f37 | 3699 | (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn")) |
3700 | (match_operand:DI 2 "general_operand" "0,0")))] | |
960e6739 | 3701 | "!TARGET_COLDFIRE" |
43b24f37 | 3702 | { |
3703 | int byte_mode; | |
3704 | ||
3705 | CC_STATUS_INIT; | |
3706 | if (GET_CODE (operands[0]) == REG) | |
7014838c | 3707 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
43b24f37 | 3708 | else |
eafc6604 | 3709 | operands[0] = adjust_address (operands[0], SImode, 4); |
43b24f37 | 3710 | if (GET_MODE (operands[1]) == SImode) |
2de9355b | 3711 | return "or%.l %1,%0"; |
43b24f37 | 3712 | byte_mode = (GET_MODE (operands[1]) == QImode); |
3713 | if (GET_CODE (operands[0]) == MEM) | |
eafc6604 | 3714 | operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode, |
3715 | byte_mode ? 3 : 2); | |
43b24f37 | 3716 | if (byte_mode) |
2de9355b | 3717 | return "or%.b %1,%0"; |
43b24f37 | 3718 | else |
2de9355b | 3719 | return "or%.w %1,%0"; |
3720 | }) | |
43b24f37 | 3721 | |
83f6afc2 | 3722 | (define_expand "iorsi3" |
c4af10f0 | 3723 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
83f6afc2 | 3724 | (ior:SI (match_operand:SI 1 "general_operand" "") |
f0ecff58 | 3725 | (match_operand:SI 2 "general_src_operand" "")))] |
83f6afc2 | 3726 | "" |
3727 | "") | |
3728 | ||
3729 | (define_insn "iorsi3_internal" | |
c4af10f0 | 3730 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 3731 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") |
f0ecff58 | 3732 | (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))] |
960e6739 | 3733 | "! TARGET_COLDFIRE" |
c1dbe9ae | 3734 | { |
dc5ebe55 | 3735 | return output_iorsi3 (operands); |
2de9355b | 3736 | }) |
c1dbe9ae | 3737 | |
83f6afc2 | 3738 | (define_insn "iorsi3_5200" |
c4af10f0 | 3739 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") |
83f6afc2 | 3740 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") |
f0ecff58 | 3741 | (match_operand:SI 2 "general_src_operand" "d,dmsK")))] |
960e6739 | 3742 | "TARGET_COLDFIRE" |
0c4bc85a | 3743 | { |
3744 | return output_iorsi3 (operands); | |
3745 | }) | |
83f6afc2 | 3746 | |
c1dbe9ae | 3747 | (define_insn "iorhi3" |
c4af10f0 | 3748 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 3749 | (ior:HI (match_operand:HI 1 "general_operand" "%0,0") |
f0ecff58 | 3750 | (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3751 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3752 | "or%.w %2,%0") |
3753 | ||
a45d833a | 3754 | (define_insn "" |
c4af10f0 | 3755 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
a45d833a | 3756 | (ior:HI (match_dup 0) |
f0ecff58 | 3757 | (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3758 | "!TARGET_COLDFIRE" |
a45d833a | 3759 | "or%.w %1,%0") |
3760 | ||
3761 | (define_insn "" | |
c4af10f0 | 3762 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) |
f0ecff58 | 3763 | (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") |
a45d833a | 3764 | (match_dup 0)))] |
960e6739 | 3765 | "!TARGET_COLDFIRE" |
a45d833a | 3766 | "or%.w %1,%0") |
3767 | ||
c1dbe9ae | 3768 | (define_insn "iorqi3" |
c4af10f0 | 3769 | [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") |
c1dbe9ae | 3770 | (ior:QI (match_operand:QI 1 "general_operand" "%0,0") |
f0ecff58 | 3771 | (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3772 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3773 | "or%.b %2,%0") |
a45d833a | 3774 | |
3775 | (define_insn "" | |
c4af10f0 | 3776 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
a45d833a | 3777 | (ior:QI (match_dup 0) |
f0ecff58 | 3778 | (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] |
960e6739 | 3779 | "!TARGET_COLDFIRE" |
a45d833a | 3780 | "or%.b %1,%0") |
3781 | ||
3782 | (define_insn "" | |
c4af10f0 | 3783 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) |
f0ecff58 | 3784 | (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") |
a45d833a | 3785 | (match_dup 0)))] |
960e6739 | 3786 | "!TARGET_COLDFIRE" |
a45d833a | 3787 | "or%.b %1,%0") |
a9829424 | 3788 | |
0412aa61 | 3789 | ;; On all 68k models, this makes faster code in a special case. |
3790 | ;; See also ashlsi_16, ashrsi_16 and lshrsi_16. | |
3791 | ||
3792 | (define_insn "iorsi_zexthi_ashl16" | |
c4af10f0 | 3793 | [(set (match_operand:SI 0 "nonimmediate_operand" "=&d") |
43b24f37 | 3794 | (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn")) |
3795 | (ashift:SI (match_operand:SI 2 "general_operand" "or") | |
0412aa61 | 3796 | (const_int 16))))] |
43b24f37 | 3797 | "" |
0412aa61 | 3798 | { |
3799 | CC_STATUS_INIT; | |
3800 | if (GET_CODE (operands[2]) != REG) | |
eafc6604 | 3801 | operands[2] = adjust_address (operands[2], HImode, 2); |
43b24f37 | 3802 | if (GET_CODE (operands[2]) != REG |
3803 | || REGNO (operands[2]) != REGNO (operands[0])) | |
2de9355b | 3804 | output_asm_insn ("move%.w %2,%0", operands); |
3805 | return "swap %0\;mov%.w %1,%0"; | |
3806 | }) | |
0412aa61 | 3807 | |
43b24f37 | 3808 | (define_insn "iorsi_zext" |
c4af10f0 | 3809 | [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d") |
a9829424 | 3810 | (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn")) |
3811 | (match_operand:SI 2 "general_operand" "0,0")))] | |
960e6739 | 3812 | "!TARGET_COLDFIRE" |
a9829424 | 3813 | { |
3814 | int byte_mode; | |
3815 | ||
3816 | CC_STATUS_INIT; | |
43b24f37 | 3817 | byte_mode = (GET_MODE (operands[1]) == QImode); |
a9829424 | 3818 | if (GET_CODE (operands[0]) == MEM) |
eafc6604 | 3819 | operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode, |
3820 | byte_mode ? 3 : 2); | |
a9829424 | 3821 | if (byte_mode) |
2de9355b | 3822 | return "or%.b %1,%0"; |
a9829424 | 3823 | else |
2de9355b | 3824 | return "or%.w %1,%0"; |
3825 | }) | |
c1dbe9ae | 3826 | \f |
3827 | ;; xor instructions | |
3828 | ||
83f6afc2 | 3829 | (define_expand "xorsi3" |
c4af10f0 | 3830 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
83f6afc2 | 3831 | (xor:SI (match_operand:SI 1 "general_operand" "") |
3832 | (match_operand:SI 2 "general_operand" "")))] | |
3833 | "" | |
3834 | "") | |
3835 | ||
3836 | (define_insn "xorsi3_internal" | |
8dc239d3 | 3837 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,o,m") |
3838 | (xor:SI (match_operand:SI 1 "general_operand" "%0, 0,0") | |
3839 | (match_operand:SI 2 "general_operand" "di,dK,dKT")))] | |
f0ecff58 | 3840 | |
960e6739 | 3841 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3842 | { |
dc5ebe55 | 3843 | return output_xorsi3 (operands); |
2de9355b | 3844 | }) |
c1dbe9ae | 3845 | |
83f6afc2 | 3846 | (define_insn "xorsi3_5200" |
c4af10f0 | 3847 | [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d") |
96dc54f0 | 3848 | (xor:SI (match_operand:SI 1 "general_operand" "%0,0") |
3849 | (match_operand:SI 2 "general_operand" "d,Ks")))] | |
960e6739 | 3850 | "TARGET_COLDFIRE" |
0c4bc85a | 3851 | { |
3852 | return output_xorsi3 (operands); | |
3853 | }) | |
83f6afc2 | 3854 | |
c1dbe9ae | 3855 | (define_insn "xorhi3" |
c4af10f0 | 3856 | [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 3857 | (xor:HI (match_operand:HI 1 "general_operand" "%0") |
3858 | (match_operand:HI 2 "general_operand" "dn")))] | |
960e6739 | 3859 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3860 | "eor%.w %2,%0") |
3861 | ||
a45d833a | 3862 | (define_insn "" |
c4af10f0 | 3863 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 3864 | (xor:HI (match_dup 0) |
3865 | (match_operand:HI 1 "general_operand" "dn")))] | |
960e6739 | 3866 | "!TARGET_COLDFIRE" |
a45d833a | 3867 | "eor%.w %1,%0") |
3868 | ||
a45d833a | 3869 | (define_insn "" |
c4af10f0 | 3870 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 3871 | (xor:HI (match_operand:HI 1 "general_operand" "dn") |
3872 | (match_dup 0)))] | |
960e6739 | 3873 | "!TARGET_COLDFIRE" |
a45d833a | 3874 | "eor%.w %1,%0") |
3875 | ||
c1dbe9ae | 3876 | (define_insn "xorqi3" |
c4af10f0 | 3877 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 3878 | (xor:QI (match_operand:QI 1 "general_operand" "%0") |
3879 | (match_operand:QI 2 "general_operand" "dn")))] | |
960e6739 | 3880 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3881 | "eor%.b %2,%0") |
a45d833a | 3882 | |
3883 | (define_insn "" | |
c4af10f0 | 3884 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 3885 | (xor:QI (match_dup 0) |
3886 | (match_operand:QI 1 "general_operand" "dn")))] | |
960e6739 | 3887 | "!TARGET_COLDFIRE" |
a45d833a | 3888 | "eor%.b %1,%0") |
3889 | ||
3890 | (define_insn "" | |
c4af10f0 | 3891 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 3892 | (xor:QI (match_operand:QI 1 "general_operand" "dn") |
3893 | (match_dup 0)))] | |
960e6739 | 3894 | "!TARGET_COLDFIRE" |
a45d833a | 3895 | "eor%.b %1,%0") |
c1dbe9ae | 3896 | \f |
3897 | ;; negation instructions | |
3898 | ||
a8005235 | 3899 | (define_expand "negdi2" |
c4af10f0 | 3900 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
a8005235 | 3901 | (neg:DI (match_operand:DI 1 "general_operand" "")))] |
3902 | "" | |
a8005235 | 3903 | { |
960e6739 | 3904 | if (TARGET_COLDFIRE) |
a8005235 | 3905 | emit_insn (gen_negdi2_5200 (operands[0], operands[1])); |
3906 | else | |
3907 | emit_insn (gen_negdi2_internal (operands[0], operands[1])); | |
3908 | DONE; | |
f5f2db69 | 3909 | }) |
a8005235 | 3910 | |
3911 | (define_insn "negdi2_internal" | |
c4af10f0 | 3912 | [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a") |
3f6dfb87 | 3913 | (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))] |
960e6739 | 3914 | "!TARGET_COLDFIRE" |
5e4c76b7 | 3915 | { |
3f6dfb87 | 3916 | if (which_alternative == 0) |
2de9355b | 3917 | return "neg%.l %0\;negx%.l %0"; |
5e4c76b7 | 3918 | if (GET_CODE (operands[0]) == REG) |
e6b2f841 | 3919 | operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
5e4c76b7 | 3920 | else |
eafc6604 | 3921 | operands[1] = adjust_address (operands[0], SImode, 4); |
7b0353a0 | 3922 | if (ADDRESS_REG_P (operands[0])) |
2de9355b | 3923 | return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0"; |
7b0353a0 | 3924 | else |
2de9355b | 3925 | return "neg%.l %1\;negx%.l %0"; |
3926 | }) | |
5e4c76b7 | 3927 | |
a8005235 | 3928 | (define_insn "negdi2_5200" |
c4af10f0 | 3929 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") |
a7781f4f | 3930 | (neg:DI (match_operand:DI 1 "general_operand" "0")))] |
960e6739 | 3931 | "TARGET_COLDFIRE" |
a8005235 | 3932 | { |
e6b2f841 | 3933 | operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 3934 | return "neg%.l %1\;negx%.l %0"; |
3935 | }) | |
a8005235 | 3936 | |
a7781f4f | 3937 | (define_expand "negsi2" |
c4af10f0 | 3938 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
a7781f4f | 3939 | (neg:SI (match_operand:SI 1 "general_operand" "")))] |
3940 | "" | |
a7781f4f | 3941 | { |
960e6739 | 3942 | if (TARGET_COLDFIRE) |
a7781f4f | 3943 | emit_insn (gen_negsi2_5200 (operands[0], operands[1])); |
3944 | else | |
3945 | emit_insn (gen_negsi2_internal (operands[0], operands[1])); | |
3946 | DONE; | |
f5f2db69 | 3947 | }) |
a7781f4f | 3948 | |
3949 | (define_insn "negsi2_internal" | |
c4af10f0 | 3950 | [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 3951 | (neg:SI (match_operand:SI 1 "general_operand" "0")))] |
960e6739 | 3952 | "!TARGET_COLDFIRE" |
1d86aeab | 3953 | "neg%.l %0" |
3954 | [(set_attr "type" "neg_l")]) | |
a7781f4f | 3955 | |
3956 | (define_insn "negsi2_5200" | |
c4af10f0 | 3957 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
a7781f4f | 3958 | (neg:SI (match_operand:SI 1 "general_operand" "0")))] |
960e6739 | 3959 | "TARGET_COLDFIRE" |
1d86aeab | 3960 | "neg%.l %0" |
3961 | [(set_attr "type" "neg_l")]) | |
c1dbe9ae | 3962 | |
3963 | (define_insn "neghi2" | |
c4af10f0 | 3964 | [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 3965 | (neg:HI (match_operand:HI 1 "general_operand" "0")))] |
960e6739 | 3966 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3967 | "neg%.w %0") |
3968 | ||
a45d833a | 3969 | (define_insn "" |
c4af10f0 | 3970 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 3971 | (neg:HI (match_dup 0)))] |
960e6739 | 3972 | "!TARGET_COLDFIRE" |
a45d833a | 3973 | "neg%.w %0") |
3974 | ||
c1dbe9ae | 3975 | (define_insn "negqi2" |
c4af10f0 | 3976 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 3977 | (neg:QI (match_operand:QI 1 "general_operand" "0")))] |
960e6739 | 3978 | "!TARGET_COLDFIRE" |
c1dbe9ae | 3979 | "neg%.b %0") |
3980 | ||
a45d833a | 3981 | (define_insn "" |
c4af10f0 | 3982 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 3983 | (neg:QI (match_dup 0)))] |
960e6739 | 3984 | "!TARGET_COLDFIRE" |
a45d833a | 3985 | "neg%.b %0") |
3986 | ||
69740164 | 3987 | ;; If using software floating point, just flip the sign bit. |
3988 | ||
c1dbe9ae | 3989 | (define_expand "negsf2" |
c4af10f0 | 3990 | [(set (match_operand:SF 0 "nonimmediate_operand" "") |
c1dbe9ae | 3991 | (neg:SF (match_operand:SF 1 "general_operand" "")))] |
69740164 | 3992 | "" |
69740164 | 3993 | { |
58c23110 | 3994 | if (!TARGET_HARD_FLOAT) |
69740164 | 3995 | { |
3996 | rtx result; | |
3997 | rtx target; | |
3998 | ||
3999 | target = operand_subword_force (operands[0], 0, SFmode); | |
4000 | result = expand_binop (SImode, xor_optab, | |
4001 | operand_subword_force (operands[1], 0, SFmode), | |
7f2a4bd2 | 4002 | GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN); |
84653e0f | 4003 | gcc_assert (result); |
69740164 | 4004 | |
4005 | if (result != target) | |
4006 | emit_move_insn (result, target); | |
4007 | ||
4008 | /* Make a place for REG_EQUAL. */ | |
4009 | emit_move_insn (operands[0], operands[0]); | |
4010 | DONE; | |
4011 | } | |
f5f2db69 | 4012 | }) |
c1dbe9ae | 4013 | |
c1dbe9ae | 4014 | (define_expand "negdf2" |
c4af10f0 | 4015 | [(set (match_operand:DF 0 "nonimmediate_operand" "") |
c1dbe9ae | 4016 | (neg:DF (match_operand:DF 1 "general_operand" "")))] |
69740164 | 4017 | "" |
69740164 | 4018 | { |
58c23110 | 4019 | if (!TARGET_HARD_FLOAT) |
69740164 | 4020 | { |
4021 | rtx result; | |
4022 | rtx target; | |
4023 | rtx insns; | |
4024 | ||
4025 | start_sequence (); | |
4026 | target = operand_subword (operands[0], 0, 1, DFmode); | |
4027 | result = expand_binop (SImode, xor_optab, | |
4028 | operand_subword_force (operands[1], 0, DFmode), | |
7f2a4bd2 | 4029 | GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN); |
84653e0f | 4030 | gcc_assert (result); |
69740164 | 4031 | |
4032 | if (result != target) | |
4033 | emit_move_insn (result, target); | |
3f6dfb87 | 4034 | |
69740164 | 4035 | emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), |
4036 | operand_subword_force (operands[1], 1, DFmode)); | |
4037 | ||
4038 | insns = get_insns (); | |
4039 | end_sequence (); | |
4040 | ||
e29831db | 4041 | emit_insn (insns); |
69740164 | 4042 | DONE; |
4043 | } | |
f5f2db69 | 4044 | }) |
c1dbe9ae | 4045 | |
58c23110 | 4046 | (define_expand "negxf2" |
4047 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
4048 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))] | |
4049 | "" | |
4050 | { | |
4051 | if (!TARGET_68881) | |
4052 | { | |
4053 | rtx result; | |
4054 | rtx target; | |
4055 | rtx insns; | |
4056 | ||
4057 | start_sequence (); | |
4058 | target = operand_subword (operands[0], 0, 1, XFmode); | |
4059 | result = expand_binop (SImode, xor_optab, | |
4060 | operand_subword_force (operands[1], 0, XFmode), | |
7f2a4bd2 | 4061 | GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN); |
58c23110 | 4062 | gcc_assert (result); |
4063 | ||
4064 | if (result != target) | |
4065 | emit_move_insn (result, target); | |
4066 | ||
4067 | emit_move_insn (operand_subword (operands[0], 1, 1, XFmode), | |
4068 | operand_subword_force (operands[1], 1, XFmode)); | |
4069 | emit_move_insn (operand_subword (operands[0], 2, 1, XFmode), | |
4070 | operand_subword_force (operands[1], 2, XFmode)); | |
4071 | ||
4072 | insns = get_insns (); | |
4073 | end_sequence (); | |
4074 | ||
e29831db | 4075 | emit_insn (insns); |
58c23110 | 4076 | DONE; |
4077 | } | |
4078 | }) | |
4079 | ||
4080 | (define_insn "neg<mode>2_68881" | |
4081 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") | |
4082 | (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))] | |
c1dbe9ae | 4083 | "TARGET_68881" |
c1dbe9ae | 4084 | { |
4085 | if (DATA_REG_P (operands[0])) | |
4086 | { | |
e6b2f841 | 4087 | operands[1] = GEN_INT (31); |
2de9355b | 4088 | return "bchg %1,%0"; |
c1dbe9ae | 4089 | } |
58c23110 | 4090 | if (FP_REG_P (operands[1])) |
4091 | return "f<FP:round>neg%.x %1,%0"; | |
4092 | return "f<FP:round>neg%.<FP:prec> %f1,%0"; | |
4093 | }) | |
4094 | ||
4095 | (define_insn "neg<mode>2_cf" | |
4096 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") | |
4097 | (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))] | |
4098 | "TARGET_COLDFIRE_FPU" | |
4099 | { | |
4100 | if (DATA_REG_P (operands[0])) | |
4101 | { | |
4102 | operands[1] = GEN_INT (31); | |
4103 | return "bchg %1,%0"; | |
4104 | } | |
4105 | if (FP_REG_P (operands[1])) | |
4106 | return "f<FP:prec>neg%.d %1,%0"; | |
4107 | return "f<FP:prec>neg%.<FP:prec> %1,%0"; | |
2de9355b | 4108 | }) |
c1dbe9ae | 4109 | \f |
ce5b71b5 | 4110 | ;; Sqrt instruction for the 68881 |
4111 | ||
58c23110 | 4112 | (define_expand "sqrt<mode>2" |
4113 | [(set (match_operand:FP 0 "nonimmediate_operand" "") | |
4114 | (sqrt:FP (match_operand:FP 1 "general_operand" "")))] | |
4115 | "TARGET_HARD_FLOAT" | |
4116 | "") | |
4117 | ||
4118 | (define_insn "sqrt<mode>2_68881" | |
4119 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
4120 | (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))] | |
71e1d078 | 4121 | "TARGET_68881" |
71e1d078 | 4122 | { |
4123 | if (FP_REG_P (operands[1])) | |
58c23110 | 4124 | return "f<FP:round>sqrt%.x %1,%0"; |
4125 | return "f<FP:round>sqrt%.<FP:prec> %1,%0"; | |
1d86aeab | 4126 | } |
4127 | [(set_attr "type" "fsqrt")]) | |
71e1d078 | 4128 | |
58c23110 | 4129 | (define_insn "sqrt<mode>2_cf" |
4130 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
4131 | (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))] | |
4132 | "TARGET_COLDFIRE_FPU" | |
ce5b71b5 | 4133 | { |
4134 | if (FP_REG_P (operands[1])) | |
58c23110 | 4135 | return "f<FP:prec>sqrt%.d %1,%0"; |
4136 | return "f<FP:prec>sqrt%.<FP:prec> %1,%0"; | |
3c904dda | 4137 | } |
4138 | [(set_attr "type" "fsqrt")]) | |
c1dbe9ae | 4139 | ;; Absolute value instructions |
69740164 | 4140 | ;; If using software floating point, just zero the sign bit. |
c1dbe9ae | 4141 | |
4142 | (define_expand "abssf2" | |
c4af10f0 | 4143 | [(set (match_operand:SF 0 "nonimmediate_operand" "") |
c1dbe9ae | 4144 | (abs:SF (match_operand:SF 1 "general_operand" "")))] |
69740164 | 4145 | "" |
69740164 | 4146 | { |
58c23110 | 4147 | if (!TARGET_HARD_FLOAT) |
69740164 | 4148 | { |
4149 | rtx result; | |
4150 | rtx target; | |
4151 | ||
4152 | target = operand_subword_force (operands[0], 0, SFmode); | |
4153 | result = expand_binop (SImode, and_optab, | |
4154 | operand_subword_force (operands[1], 0, SFmode), | |
7014838c | 4155 | GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); |
84653e0f | 4156 | gcc_assert (result); |
69740164 | 4157 | |
4158 | if (result != target) | |
4159 | emit_move_insn (result, target); | |
4160 | ||
4161 | /* Make a place for REG_EQUAL. */ | |
4162 | emit_move_insn (operands[0], operands[0]); | |
4163 | DONE; | |
4164 | } | |
f5f2db69 | 4165 | }) |
c1dbe9ae | 4166 | |
c1dbe9ae | 4167 | (define_expand "absdf2" |
c4af10f0 | 4168 | [(set (match_operand:DF 0 "nonimmediate_operand" "") |
c1dbe9ae | 4169 | (abs:DF (match_operand:DF 1 "general_operand" "")))] |
69740164 | 4170 | "" |
69740164 | 4171 | { |
58c23110 | 4172 | if (!TARGET_HARD_FLOAT) |
69740164 | 4173 | { |
4174 | rtx result; | |
4175 | rtx target; | |
4176 | rtx insns; | |
4177 | ||
4178 | start_sequence (); | |
4179 | target = operand_subword (operands[0], 0, 1, DFmode); | |
4180 | result = expand_binop (SImode, and_optab, | |
4181 | operand_subword_force (operands[1], 0, DFmode), | |
7014838c | 4182 | GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); |
84653e0f | 4183 | gcc_assert (result); |
69740164 | 4184 | |
4185 | if (result != target) | |
4186 | emit_move_insn (result, target); | |
3f6dfb87 | 4187 | |
69740164 | 4188 | emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), |
4189 | operand_subword_force (operands[1], 1, DFmode)); | |
4190 | ||
4191 | insns = get_insns (); | |
4192 | end_sequence (); | |
4193 | ||
e29831db | 4194 | emit_insn (insns); |
69740164 | 4195 | DONE; |
4196 | } | |
f5f2db69 | 4197 | }) |
c1dbe9ae | 4198 | |
58c23110 | 4199 | (define_expand "absxf2" |
4200 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
4201 | (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))] | |
4202 | "" | |
4203 | { | |
4204 | if (!TARGET_68881) | |
4205 | { | |
4206 | rtx result; | |
4207 | rtx target; | |
4208 | rtx insns; | |
4209 | ||
4210 | start_sequence (); | |
4211 | target = operand_subword (operands[0], 0, 1, XFmode); | |
4212 | result = expand_binop (SImode, and_optab, | |
4213 | operand_subword_force (operands[1], 0, XFmode), | |
4214 | GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); | |
4215 | gcc_assert (result); | |
4216 | ||
4217 | if (result != target) | |
4218 | emit_move_insn (result, target); | |
4219 | ||
4220 | emit_move_insn (operand_subword (operands[0], 1, 1, XFmode), | |
4221 | operand_subword_force (operands[1], 1, XFmode)); | |
4222 | emit_move_insn (operand_subword (operands[0], 2, 1, XFmode), | |
4223 | operand_subword_force (operands[1], 2, XFmode)); | |
4224 | ||
4225 | insns = get_insns (); | |
4226 | end_sequence (); | |
4227 | ||
e29831db | 4228 | emit_insn (insns); |
58c23110 | 4229 | DONE; |
4230 | } | |
4231 | }) | |
4232 | ||
4233 | (define_insn "abs<mode>2_68881" | |
4234 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") | |
4235 | (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))] | |
4236 | "TARGET_68881" | |
4237 | { | |
4238 | if (DATA_REG_P (operands[0])) | |
4239 | { | |
4240 | operands[1] = GEN_INT (31); | |
4241 | return "bclr %1,%0"; | |
4242 | } | |
4243 | if (FP_REG_P (operands[1])) | |
4244 | return "f<FP:round>abs%.x %1,%0"; | |
4245 | return "f<FP:round>abs%.<FP:prec> %f1,%0"; | |
4246 | }) | |
4247 | ||
4248 | (define_insn "abs<mode>2_cf" | |
4249 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") | |
4250 | (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))] | |
4251 | "TARGET_COLDFIRE_FPU" | |
c1dbe9ae | 4252 | { |
58c23110 | 4253 | if (DATA_REG_P (operands[0])) |
4254 | { | |
4255 | operands[1] = GEN_INT (31); | |
4256 | return "bclr %1,%0"; | |
4257 | } | |
4258 | if (FP_REG_P (operands[1])) | |
4259 | return "f<FP:prec>abs%.d %1,%0"; | |
4260 | return "f<FP:prec>abs%.<FP:prec> %1,%0"; | |
3c904dda | 4261 | } |
4262 | [(set_attr "type" "bitrw,fneg")]) | |
c1dbe9ae | 4263 | \f |
afc78fc6 | 4264 | ;; bit indexing instructions |
4265 | ||
eddf6a68 | 4266 | (define_expand "clzsi2" |
4267 | [(set (match_operand:SI 0 "register_operand" "") | |
4268 | (clz:SI (match_operand:SI 1 "general_operand" "")))] | |
4269 | "ISA_HAS_FF1 || (TARGET_68020 && TARGET_BITFIELD)" | |
4270 | { | |
4271 | if (ISA_HAS_FF1) | |
4272 | operands[1] = force_reg (SImode, operands[1]); | |
4273 | }) | |
4274 | ||
4275 | (define_insn "*clzsi2_68k" | |
4276 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4277 | (clz:SI (match_operand:SI 1 "general_operand" "do")))] | |
4278 | "TARGET_68020 && TARGET_BITFIELD" | |
4279 | { | |
4280 | CC_STATUS_INIT; | |
4281 | return "bfffo %1{#0:#0},%0"; | |
4282 | }) | |
4283 | ||
afc78fc6 | 4284 | ;; ColdFire ff1 instruction implements clz. |
eddf6a68 | 4285 | (define_insn "*clzsi2_cf" |
afc78fc6 | 4286 | [(set (match_operand:SI 0 "register_operand" "=d") |
4287 | (clz:SI (match_operand:SI 1 "register_operand" "0")))] | |
da8fbdfe | 4288 | "ISA_HAS_FF1" |
eddf6a68 | 4289 | { |
4290 | CC_STATUS_INIT; | |
4291 | return "ff1 %0"; | |
4292 | } | |
3c904dda | 4293 | [(set_attr "type" "ext")]) |
afc78fc6 | 4294 | \f |
c1dbe9ae | 4295 | ;; one complement instructions |
4296 | ||
a7781f4f | 4297 | (define_expand "one_cmplsi2" |
c4af10f0 | 4298 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
a7781f4f | 4299 | (not:SI (match_operand:SI 1 "general_operand" "")))] |
4300 | "" | |
a7781f4f | 4301 | { |
960e6739 | 4302 | if (TARGET_COLDFIRE) |
a7781f4f | 4303 | emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1])); |
4304 | else | |
4305 | emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1])); | |
4306 | DONE; | |
f5f2db69 | 4307 | }) |
a7781f4f | 4308 | |
4309 | (define_insn "one_cmplsi2_internal" | |
c4af10f0 | 4310 | [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 4311 | (not:SI (match_operand:SI 1 "general_operand" "0")))] |
960e6739 | 4312 | "!TARGET_COLDFIRE" |
a7781f4f | 4313 | "not%.l %0") |
4314 | ||
4315 | (define_insn "one_cmplsi2_5200" | |
c4af10f0 | 4316 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
a7781f4f | 4317 | (not:SI (match_operand:SI 1 "general_operand" "0")))] |
960e6739 | 4318 | "TARGET_COLDFIRE" |
1d86aeab | 4319 | "not%.l %0" |
3c904dda | 4320 | [(set_attr "type" "neg_l")]) |
c1dbe9ae | 4321 | |
4322 | (define_insn "one_cmplhi2" | |
c4af10f0 | 4323 | [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 4324 | (not:HI (match_operand:HI 1 "general_operand" "0")))] |
960e6739 | 4325 | "!TARGET_COLDFIRE" |
c1dbe9ae | 4326 | "not%.w %0") |
4327 | ||
a45d833a | 4328 | (define_insn "" |
c4af10f0 | 4329 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 4330 | (not:HI (match_dup 0)))] |
960e6739 | 4331 | "!TARGET_COLDFIRE" |
a45d833a | 4332 | "not%.w %0") |
4333 | ||
c1dbe9ae | 4334 | (define_insn "one_cmplqi2" |
c4af10f0 | 4335 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") |
c1dbe9ae | 4336 | (not:QI (match_operand:QI 1 "general_operand" "0")))] |
960e6739 | 4337 | "!TARGET_COLDFIRE" |
c1dbe9ae | 4338 | "not%.b %0") |
a45d833a | 4339 | |
4340 | (define_insn "" | |
c4af10f0 | 4341 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) |
a45d833a | 4342 | (not:QI (match_dup 0)))] |
960e6739 | 4343 | "!TARGET_COLDFIRE" |
a45d833a | 4344 | "not%.b %0") |
c1dbe9ae | 4345 | \f |
4346 | ;; arithmetic shift instructions | |
4347 | ;; We don't need the shift memory by 1 bit instruction | |
6ad9a408 | 4348 | (define_insn_and_split "ashldi_extsi" |
c4af10f0 | 4349 | [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") |
d08c9ad7 | 4350 | (ashift:DI |
4351 | (match_operator:DI 2 "extend_operator" | |
4352 | [(match_operand:SI 1 "general_operand" "rm")]) | |
4353 | (const_int 32)))] | |
4354 | "" | |
6ad9a408 | 4355 | "#" |
4356 | "&& reload_completed" | |
4357 | [(set (match_dup 3) (match_dup 1)) | |
4358 | (set (match_dup 2) (const_int 0))] | |
4359 | "split_di(operands, 1, operands + 2, operands + 3);") | |
d08c9ad7 | 4360 | |
5e4c76b7 | 4361 | (define_insn "ashldi_sexthi" |
c4af10f0 | 4362 | [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d") |
3f6dfb87 | 4363 | (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm")) |
4364 | (const_int 32))) | |
4365 | (clobber (match_scratch:SI 2 "=a,X"))] | |
5e4c76b7 | 4366 | "" |
5e4c76b7 | 4367 | { |
4368 | CC_STATUS_INIT; | |
3f6dfb87 | 4369 | if (GET_CODE (operands[0]) == MEM) |
4370 | { | |
4371 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2de9355b | 4372 | return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0"; |
3f6dfb87 | 4373 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) |
2de9355b | 4374 | return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0"; |
3f6dfb87 | 4375 | else |
4376 | { | |
eafc6604 | 4377 | operands[3] = adjust_address (operands[0], SImode, 4); |
2de9355b | 4378 | return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3"; |
3f6dfb87 | 4379 | } |
4380 | } | |
4381 | else if (DATA_REG_P (operands[0])) | |
2de9355b | 4382 | return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0"; |
5e4c76b7 | 4383 | else |
2de9355b | 4384 | return "move%.w %1,%0\;sub%.l %R0,%R0"; |
4385 | }) | |
5e4c76b7 | 4386 | |
8ec9650e | 4387 | (define_insn "*ashldi3_const1" |
4388 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4389 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
4390 | (const_int 1)))] | |
4391 | "!TARGET_COLDFIRE" | |
4392 | "add%.l %R0,%R0\;addx%.l %0,%0") | |
4393 | ||
4394 | (define_split | |
4395 | [(set (match_operand:DI 0 "register_operand" "") | |
4396 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4397 | (const_int 2)))] | |
4398 | "reload_completed && !TARGET_COLDFIRE" | |
4399 | [(set (match_dup 0) | |
4400 | (ashift:DI (match_dup 1) (const_int 1))) | |
4401 | (set (match_dup 0) | |
4402 | (ashift:DI (match_dup 0) (const_int 1)))] | |
4403 | "") | |
4404 | ||
4405 | (define_split | |
4406 | [(set (match_operand:DI 0 "register_operand" "") | |
4407 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4408 | (const_int 3)))] | |
4409 | "reload_completed && !TARGET_COLDFIRE" | |
4410 | [(set (match_dup 0) | |
4411 | (ashift:DI (match_dup 1) (const_int 2))) | |
4412 | (set (match_dup 0) | |
4413 | (ashift:DI (match_dup 0) (const_int 1)))] | |
4414 | "") | |
4415 | ||
4416 | (define_split | |
4417 | [(set (match_operand:DI 0 "register_operand" "") | |
4418 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4419 | (const_int 8)))] | |
4420 | "reload_completed && !TARGET_COLDFIRE" | |
4421 | [(set (match_dup 2) | |
4422 | (rotate:SI (match_dup 2) (const_int 8))) | |
4423 | (set (match_dup 3) | |
4424 | (rotate:SI (match_dup 3) (const_int 8))) | |
4425 | (set (strict_low_part (subreg:QI (match_dup 0) 3)) | |
4426 | (subreg:QI (match_dup 0) 7)) | |
4427 | (set (strict_low_part (subreg:QI (match_dup 0) 7)) | |
4428 | (const_int 0))] | |
4429 | { | |
4430 | operands[2] = gen_highpart (SImode, operands[0]); | |
4431 | operands[3] = gen_lowpart (SImode, operands[0]); | |
4432 | }) | |
4433 | ||
4434 | (define_split | |
4435 | [(set (match_operand:DI 0 "register_operand" "") | |
4436 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4437 | (const_int 16)))] | |
4438 | "reload_completed && !TARGET_COLDFIRE" | |
4439 | [(set (match_dup 2) | |
4440 | (rotate:SI (match_dup 2) (const_int 16))) | |
4441 | (set (match_dup 3) | |
4442 | (rotate:SI (match_dup 3) (const_int 16))) | |
4443 | (set (strict_low_part (subreg:HI (match_dup 0) 2)) | |
4444 | (subreg:HI (match_dup 0) 6)) | |
4445 | (set (strict_low_part (subreg:HI (match_dup 0) 6)) | |
4446 | (const_int 0))] | |
4447 | { | |
4448 | operands[2] = gen_highpart (SImode, operands[0]); | |
4449 | operands[3] = gen_lowpart (SImode, operands[0]); | |
4450 | }) | |
4451 | ||
4452 | (define_split | |
4453 | [(set (match_operand:DI 0 "pre_dec_operand" "") | |
4454 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4455 | (const_int 32)))] | |
4456 | "reload_completed" | |
4457 | [(set (match_dup 0) (const_int 0)) | |
4458 | (set (match_dup 0) (match_dup 1))] | |
4459 | { | |
4460 | operands[0] = adjust_address(operands[0], SImode, 0); | |
4461 | operands[1] = gen_lowpart(SImode, operands[1]); | |
4462 | }) | |
4463 | ||
4464 | (define_split | |
4465 | [(set (match_operand:DI 0 "post_inc_operand" "") | |
4466 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4467 | (const_int 32)))] | |
4468 | "reload_completed" | |
4469 | [(set (match_dup 0) (match_dup 1)) | |
4470 | (set (match_dup 0) (const_int 0))] | |
4471 | { | |
4472 | operands[0] = adjust_address(operands[0], SImode, 0); | |
4473 | operands[1] = gen_lowpart(SImode, operands[1]); | |
4474 | }) | |
4475 | ||
4476 | (define_insn_and_split "*ashldi3_const32" | |
4477 | [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>") | |
4478 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro") | |
4479 | (const_int 32)))] | |
5e4c76b7 | 4480 | "" |
8ec9650e | 4481 | "#" |
4482 | "&& reload_completed" | |
4483 | [(set (match_dup 4) (match_dup 3)) | |
4484 | (set (match_dup 2) (const_int 0))] | |
4485 | "split_di(operands, 2, operands + 2, operands + 4);") | |
4486 | ||
4487 | (define_split | |
4488 | [(set (match_operand:DI 0 "register_operand" "") | |
4489 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4490 | (match_operand 2 "const_int_operand" "")))] | |
4491 | "reload_completed && !TARGET_COLDFIRE | |
4492 | && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40" | |
4493 | [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2))) | |
4494 | (set (match_dup 3) (match_dup 4)) | |
4495 | (set (match_dup 4) (const_int 0))] | |
4496 | { | |
4497 | operands[2] = GEN_INT (INTVAL (operands[2]) - 32); | |
4498 | operands[3] = gen_highpart (SImode, operands[0]); | |
4499 | operands[4] = gen_lowpart (SImode, operands[0]); | |
4500 | }) | |
4501 | ||
4502 | (define_split | |
4503 | [(set (match_operand:DI 0 "register_operand" "") | |
4504 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4505 | (const_int 48)))] | |
4506 | "reload_completed && !TARGET_COLDFIRE" | |
4507 | [(set (match_dup 2) (match_dup 3)) | |
4508 | (set (match_dup 2) | |
4509 | (rotate:SI (match_dup 2) (const_int 16))) | |
4510 | (set (match_dup 3) (const_int 0)) | |
4511 | (set (strict_low_part (subreg:HI (match_dup 0) 2)) | |
4512 | (const_int 0))] | |
5e4c76b7 | 4513 | { |
8ec9650e | 4514 | operands[2] = gen_highpart (SImode, operands[0]); |
4515 | operands[3] = gen_lowpart (SImode, operands[0]); | |
2de9355b | 4516 | }) |
5e4c76b7 | 4517 | |
8ec9650e | 4518 | (define_split |
4519 | [(set (match_operand:DI 0 "register_operand" "") | |
4520 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4521 | (match_operand 2 "const_int_operand" "")))] | |
4522 | "reload_completed && !TARGET_COLDFIRE | |
4523 | && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63" | |
4524 | [(set (match_dup 3) (match_dup 2)) | |
4525 | (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3))) | |
4526 | (set (match_dup 3) (match_dup 4)) | |
4527 | (set (match_dup 4) (const_int 0))] | |
4528 | { | |
4529 | operands[2] = GEN_INT (INTVAL (operands[2]) - 32); | |
4530 | operands[3] = gen_highpart (SImode, operands[0]); | |
4531 | operands[4] = gen_lowpart (SImode, operands[0]); | |
4532 | }) | |
4533 | ||
4534 | (define_insn "*ashldi3" | |
4535 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4536 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
4537 | (match_operand 2 "const_int_operand" "n")))] | |
4538 | "!TARGET_COLDFIRE | |
4f5b397b | 4539 | && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) |
4540 | || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 | |
8ec9650e | 4541 | || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" |
4542 | "#") | |
5e4c76b7 | 4543 | |
4544 | (define_expand "ashldi3" | |
8ec9650e | 4545 | [(set (match_operand:DI 0 "register_operand" "") |
4546 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
4547 | (match_operand 2 "const_int_operand" "")))] | |
960e6739 | 4548 | "!TARGET_COLDFIRE" |
5e4c76b7 | 4549 | { |
4f5b397b | 4550 | /* ??? This is a named pattern like this is not allowed to FAIL based |
4551 | on its operands. */ | |
5e4c76b7 | 4552 | if (GET_CODE (operands[2]) != CONST_INT |
4f5b397b | 4553 | || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) |
4554 | && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 | |
4555 | && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) | |
5e4c76b7 | 4556 | FAIL; |
8ec9650e | 4557 | }) |
5e4c76b7 | 4558 | |
4282b62a | 4559 | ;; On most 68k models, this makes faster code in a special case. |
bdf74c8a | 4560 | |
4282b62a | 4561 | (define_insn "ashlsi_16" |
bdf74c8a | 4562 | [(set (match_operand:SI 0 "register_operand" "=d") |
4563 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
68048623 | 4564 | (const_int 16)))] |
bd40163f | 4565 | "!TUNE_68060" |
bdf74c8a | 4566 | { |
4567 | CC_STATUS_INIT; | |
2de9355b | 4568 | return "swap %0\;clr%.w %0"; |
4569 | }) | |
bdf74c8a | 4570 | |
3f6dfb87 | 4571 | ;; ashift patterns : use lsl instead of asl, because lsl always clears the |
4572 | ;; overflow bit, so we must not set CC_NO_OVERFLOW. | |
4573 | ||
c1dbe9ae | 4574 | ;; On the 68000, this makes faster code in a special case. |
4575 | ||
4282b62a | 4576 | (define_insn "ashlsi_17_24" |
c1dbe9ae | 4577 | [(set (match_operand:SI 0 "register_operand" "=d") |
4578 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
68048623 | 4579 | (match_operand:SI 2 "const_int_operand" "n")))] |
bd40163f | 4580 | "TUNE_68000_10 |
4581 | && INTVAL (operands[2]) > 16 | |
4582 | && INTVAL (operands[2]) <= 24" | |
c1dbe9ae | 4583 | { |
4584 | CC_STATUS_INIT; | |
4585 | ||
e6b2f841 | 4586 | operands[2] = GEN_INT (INTVAL (operands[2]) - 16); |
2de9355b | 4587 | return "lsl%.w %2,%0\;swap %0\;clr%.w %0"; |
4588 | }) | |
c1dbe9ae | 4589 | |
4590 | (define_insn "ashlsi3" | |
4591 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4592 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
4593 | (match_operand:SI 2 "general_operand" "dI")))] | |
4594 | "" | |
c1dbe9ae | 4595 | { |
4596 | if (operands[2] == const1_rtx) | |
3f6dfb87 | 4597 | { |
4598 | cc_status.flags = CC_NO_OVERFLOW; | |
2de9355b | 4599 | return "add%.l %0,%0"; |
3f6dfb87 | 4600 | } |
2de9355b | 4601 | return "lsl%.l %2,%0"; |
4602 | }) | |
c1dbe9ae | 4603 | |
4604 | (define_insn "ashlhi3" | |
4605 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4606 | (ashift:HI (match_operand:HI 1 "register_operand" "0") | |
4607 | (match_operand:HI 2 "general_operand" "dI")))] | |
960e6739 | 4608 | "!TARGET_COLDFIRE" |
3f6dfb87 | 4609 | "lsl%.w %2,%0") |
c1dbe9ae | 4610 | |
a45d833a | 4611 | (define_insn "" |
4612 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) | |
4613 | (ashift:HI (match_dup 0) | |
4614 | (match_operand:HI 1 "general_operand" "dI")))] | |
960e6739 | 4615 | "!TARGET_COLDFIRE" |
3f6dfb87 | 4616 | "lsl%.w %1,%0") |
a45d833a | 4617 | |
c1dbe9ae | 4618 | (define_insn "ashlqi3" |
4619 | [(set (match_operand:QI 0 "register_operand" "=d") | |
4620 | (ashift:QI (match_operand:QI 1 "register_operand" "0") | |
4621 | (match_operand:QI 2 "general_operand" "dI")))] | |
960e6739 | 4622 | "!TARGET_COLDFIRE" |
3f6dfb87 | 4623 | "lsl%.b %2,%0") |
c1dbe9ae | 4624 | |
a45d833a | 4625 | (define_insn "" |
4626 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) | |
4627 | (ashift:QI (match_dup 0) | |
4628 | (match_operand:QI 1 "general_operand" "dI")))] | |
960e6739 | 4629 | "!TARGET_COLDFIRE" |
3f6dfb87 | 4630 | "lsl%.b %1,%0") |
a45d833a | 4631 | |
42b462d7 | 4632 | ;; On most 68k models, this makes faster code in a special case. |
bdf74c8a | 4633 | |
0412aa61 | 4634 | (define_insn "ashrsi_16" |
bdf74c8a | 4635 | [(set (match_operand:SI 0 "register_operand" "=d") |
4636 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
68048623 | 4637 | (const_int 16)))] |
bd40163f | 4638 | "!TUNE_68060" |
bdf74c8a | 4639 | "swap %0\;ext%.l %0") |
4640 | ||
c1dbe9ae | 4641 | ;; On the 68000, this makes faster code in a special case. |
4642 | ||
4643 | (define_insn "" | |
4644 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4645 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
68048623 | 4646 | (match_operand:SI 2 "const_int_operand" "n")))] |
bd40163f | 4647 | "TUNE_68000_10 |
4648 | && INTVAL (operands[2]) > 16 | |
4649 | && INTVAL (operands[2]) <= 24" | |
c1dbe9ae | 4650 | { |
e6b2f841 | 4651 | operands[2] = GEN_INT (INTVAL (operands[2]) - 16); |
2de9355b | 4652 | return "swap %0\;asr%.w %2,%0\;ext%.l %0"; |
4653 | }) | |
c1dbe9ae | 4654 | |
d08c9ad7 | 4655 | (define_insn "subreghi1ashrdi_const32" |
c4af10f0 | 4656 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
d08c9ad7 | 4657 | (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") |
00f41fc3 | 4658 | (const_int 32)) 6))] |
d08c9ad7 | 4659 | "" |
d08c9ad7 | 4660 | { |
4661 | if (GET_CODE (operands[1]) != REG) | |
eafc6604 | 4662 | operands[1] = adjust_address (operands[1], HImode, 2); |
2de9355b | 4663 | return "move%.w %1,%0"; |
1d86aeab | 4664 | } |
3c904dda | 4665 | [(set_attr "type" "move")]) |
d08c9ad7 | 4666 | |
4667 | (define_insn "subregsi1ashrdi_const32" | |
c4af10f0 | 4668 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
5e4c76b7 | 4669 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") |
701e46d0 | 4670 | (const_int 32)) 4))] |
5e4c76b7 | 4671 | "" |
5e4c76b7 | 4672 | { |
2de9355b | 4673 | return "move%.l %1,%0"; |
1d86aeab | 4674 | } |
4675 | [(set_attr "type" "move_l")]) | |
5e4c76b7 | 4676 | |
8ec9650e | 4677 | (define_insn "*ashrdi3_const1" |
4678 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4679 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4680 | (const_int 1)))] | |
4681 | "!TARGET_COLDFIRE" | |
4682 | { | |
4683 | operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
4684 | return "asr%.l #1,%0\;roxr%.l #1,%1"; | |
4685 | }) | |
4686 | ||
4687 | (define_split | |
4688 | [(set (match_operand:DI 0 "register_operand" "") | |
4689 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4690 | (const_int 2)))] | |
4691 | "reload_completed && !TARGET_COLDFIRE" | |
4692 | [(set (match_dup 0) | |
4693 | (ashiftrt:DI (match_dup 1) (const_int 1))) | |
4694 | (set (match_dup 0) | |
4695 | (ashiftrt:DI (match_dup 0) (const_int 1)))] | |
4696 | "") | |
4697 | ||
4698 | (define_split | |
4699 | [(set (match_operand:DI 0 "register_operand" "") | |
4700 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4701 | (const_int 3)))] | |
4702 | "reload_completed && !TARGET_COLDFIRE" | |
4703 | [(set (match_dup 0) | |
4704 | (ashiftrt:DI (match_dup 1) (const_int 2))) | |
4705 | (set (match_dup 0) | |
4706 | (ashiftrt:DI (match_dup 0) (const_int 1)))] | |
4707 | "") | |
4708 | ||
4709 | (define_split | |
4710 | [(set (match_operand:DI 0 "register_operand" "") | |
4711 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4712 | (const_int 8)))] | |
4713 | "reload_completed && !TARGET_COLDFIRE" | |
4714 | [(set (strict_low_part (subreg:QI (match_dup 0) 7)) | |
4715 | (subreg:QI (match_dup 0) 3)) | |
4716 | (set (match_dup 2) | |
4717 | (ashiftrt:SI (match_dup 2) (const_int 8))) | |
4718 | (set (match_dup 3) | |
4719 | (rotatert:SI (match_dup 3) (const_int 8)))] | |
4720 | { | |
4721 | operands[2] = gen_highpart (SImode, operands[0]); | |
4722 | operands[3] = gen_lowpart (SImode, operands[0]); | |
4723 | }) | |
4724 | ||
4725 | (define_split | |
4726 | [(set (match_operand:DI 0 "register_operand" "") | |
4727 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4728 | (const_int 16)))] | |
4729 | "reload_completed && !TARGET_COLDFIRE" | |
4730 | [(set (strict_low_part (subreg:HI (match_dup 0) 6)) | |
4731 | (subreg:HI (match_dup 0) 2)) | |
4732 | (set (match_dup 2) | |
4733 | (rotate:SI (match_dup 2) (const_int 16))) | |
4734 | (set (match_dup 3) | |
4735 | (rotate:SI (match_dup 3) (const_int 16))) | |
4736 | (set (match_dup 2) | |
4737 | (sign_extend:SI (subreg:HI (match_dup 2) 2)))] | |
4738 | { | |
4739 | operands[2] = gen_highpart (SImode, operands[0]); | |
4740 | operands[3] = gen_lowpart (SImode, operands[0]); | |
4741 | }) | |
4742 | ||
4743 | (define_insn "*ashrdi_const32" | |
4744 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4745 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro") | |
4746 | (const_int 32)))] | |
4747 | "" | |
4748 | { | |
4749 | CC_STATUS_INIT; | |
4750 | if (TARGET_68020) | |
4751 | return "move%.l %1,%R0\;smi %0\;extb%.l %0"; | |
4752 | else | |
4753 | return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0"; | |
4754 | }) | |
4755 | ||
4756 | (define_insn "*ashrdi_const32_mem" | |
4757 | [(set (match_operand:DI 0 "memory_operand" "=o,<") | |
4758 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro") | |
5e4c76b7 | 4759 | (const_int 32))) |
8ec9650e | 4760 | (clobber (match_scratch:SI 2 "=d,d"))] |
5e4c76b7 | 4761 | "" |
5e4c76b7 | 4762 | { |
4763 | CC_STATUS_INIT; | |
8ec9650e | 4764 | operands[3] = adjust_address (operands[0], SImode, |
4765 | which_alternative == 0 ? 4 : 0); | |
4766 | operands[0] = adjust_address (operands[0], SImode, 0); | |
4767 | if (TARGET_68020 || TARGET_COLDFIRE) | |
4768 | return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0"; | |
5e4c76b7 | 4769 | else |
8ec9650e | 4770 | return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0"; |
2de9355b | 4771 | }) |
5e4c76b7 | 4772 | |
8ec9650e | 4773 | (define_split |
4774 | [(set (match_operand:DI 0 "register_operand" "") | |
4775 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4776 | (const_int 63)))] | |
4777 | "reload_completed && !TARGET_COLDFIRE" | |
4778 | [(set (match_dup 3) | |
4779 | (ashiftrt:SI (match_dup 3) (const_int 31))) | |
4780 | (set (match_dup 2) | |
4781 | (match_dup 3))] | |
4782 | "split_di(operands, 1, operands + 2, operands + 3);") | |
4783 | ||
d08c9ad7 | 4784 | ;; The predicate below must be general_operand, because ashrdi3 allows that |
5e4c76b7 | 4785 | (define_insn "ashrdi_const" |
8ec9650e | 4786 | [(set (match_operand:DI 0 "register_operand" "=d") |
4787 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4788 | (match_operand 2 "const_int_operand" "n")))] | |
4789 | "!TARGET_COLDFIRE | |
c58f67a9 | 4790 | && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) |
4f5b397b | 4791 | || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 |
4792 | || INTVAL (operands[2]) == 31 | |
8ec9650e | 4793 | || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" |
5e4c76b7 | 4794 | { |
e6b2f841 | 4795 | operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
5e4c76b7 | 4796 | CC_STATUS_INIT; |
8ec9650e | 4797 | if (INTVAL (operands[2]) == 48) |
2de9355b | 4798 | return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0"; |
8ec9650e | 4799 | if (INTVAL (operands[2]) == 31) |
2de9355b | 4800 | return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0"; |
8ec9650e | 4801 | if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63) |
c58f67a9 | 4802 | { |
cc51d498 | 4803 | operands[2] = GEN_INT (INTVAL (operands[2]) - 32); |
2de9355b | 4804 | output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" : |
4805 | "moveq %2,%1\;asr%.l %1,%0", operands); | |
4806 | output_asm_insn ("mov%.l %0,%1\;smi %0", operands); | |
4807 | return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" : | |
4808 | TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0"; | |
c58f67a9 | 4809 | } |
8ec9650e | 4810 | return "#"; |
2de9355b | 4811 | }) |
5e4c76b7 | 4812 | |
4813 | (define_expand "ashrdi3" | |
8ec9650e | 4814 | [(set (match_operand:DI 0 "register_operand" "") |
4815 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4816 | (match_operand 2 "const_int_operand" "")))] | |
960e6739 | 4817 | "!TARGET_COLDFIRE" |
5e4c76b7 | 4818 | { |
4f5b397b | 4819 | /* ??? This is a named pattern like this is not allowed to FAIL based |
4820 | on its operands. */ | |
5e4c76b7 | 4821 | if (GET_CODE (operands[2]) != CONST_INT |
4f5b397b | 4822 | || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) |
4823 | && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 | |
4824 | && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63))) | |
5e4c76b7 | 4825 | FAIL; |
8ec9650e | 4826 | }) |
5e4c76b7 | 4827 | |
12a7ac93 | 4828 | ;; On all 68k models, this makes faster code in a special case. |
4829 | ||
4830 | (define_insn "ashrsi_31" | |
4831 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4832 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
4833 | (const_int 31)))] | |
4834 | "" | |
12a7ac93 | 4835 | { |
2de9355b | 4836 | return "add%.l %0,%0\;subx%.l %0,%0"; |
4837 | }) | |
12a7ac93 | 4838 | |
c1dbe9ae | 4839 | (define_insn "ashrsi3" |
4840 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4841 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
4842 | (match_operand:SI 2 "general_operand" "dI")))] | |
4843 | "" | |
1d86aeab | 4844 | "asr%.l %2,%0" |
3c904dda | 4845 | [(set_attr "type" "shift") |
1d86aeab | 4846 | (set_attr "opy" "2")]) |
c1dbe9ae | 4847 | |
4848 | (define_insn "ashrhi3" | |
4849 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4850 | (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") | |
4851 | (match_operand:HI 2 "general_operand" "dI")))] | |
960e6739 | 4852 | "!TARGET_COLDFIRE" |
c1dbe9ae | 4853 | "asr%.w %2,%0") |
4854 | ||
a45d833a | 4855 | (define_insn "" |
4856 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) | |
4857 | (ashiftrt:HI (match_dup 0) | |
4858 | (match_operand:HI 1 "general_operand" "dI")))] | |
960e6739 | 4859 | "!TARGET_COLDFIRE" |
a45d833a | 4860 | "asr%.w %1,%0") |
4861 | ||
c1dbe9ae | 4862 | (define_insn "ashrqi3" |
4863 | [(set (match_operand:QI 0 "register_operand" "=d") | |
4864 | (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") | |
4865 | (match_operand:QI 2 "general_operand" "dI")))] | |
960e6739 | 4866 | "!TARGET_COLDFIRE" |
c1dbe9ae | 4867 | "asr%.b %2,%0") |
a45d833a | 4868 | |
4869 | (define_insn "" | |
4870 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) | |
4871 | (ashiftrt:QI (match_dup 0) | |
4872 | (match_operand:QI 1 "general_operand" "dI")))] | |
960e6739 | 4873 | "!TARGET_COLDFIRE" |
a45d833a | 4874 | "asr%.b %1,%0") |
c1dbe9ae | 4875 | \f |
4876 | ;; logical shift instructions | |
4877 | ||
a1c7fb9b | 4878 | ;; commented out because of reload problems in 950612-1.c |
4879 | ;;(define_insn "" | |
4880 | ;; [(set (cc0) | |
4881 | ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") | |
701e46d0 | 4882 | ;; (const_int 32)) 4)) |
c4af10f0 | 4883 | ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm") |
a1c7fb9b | 4884 | ;; (subreg:SI (lshiftrt:DI (match_dup 0) |
701e46d0 | 4885 | ;; (const_int 32)) 4))] |
a1c7fb9b | 4886 | ;; "" |
a1c7fb9b | 4887 | ;;{ |
2de9355b | 4888 | ;; return "move%.l %0,%1"; |
4889 | ;;}) | |
a1c7fb9b | 4890 | ;; |
4891 | ;;(define_insn "" | |
4892 | ;; [(set (cc0) | |
4893 | ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") | |
4894 | ;; (const_int 32)) 0)) | |
c4af10f0 | 4895 | ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do") |
a1c7fb9b | 4896 | ;; (lshiftrt:DI (match_dup 0) |
4897 | ;; (const_int 32)))] | |
4898 | ;; "" | |
a1c7fb9b | 4899 | ;;{ |
4900 | ;; if (GET_CODE (operands[1]) == REG) | |
e6b2f841 | 4901 | ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
a1c7fb9b | 4902 | ;; else |
eafc6604 | 4903 | ;; operands[2] = adjust_address (operands[1], SImode, 4); |
2de9355b | 4904 | ;; return "move%.l %0,%2\;clr%.l %1"; |
4905 | ;;}) | |
d08c9ad7 | 4906 | |
5e4c76b7 | 4907 | (define_insn "subreg1lshrdi_const32" |
c4af10f0 | 4908 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
5e4c76b7 | 4909 | (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro") |
701e46d0 | 4910 | (const_int 32)) 4))] |
5e4c76b7 | 4911 | "" |
1d86aeab | 4912 | "move%.l %1,%0" |
4913 | [(set_attr "type" "move_l")]) | |
5e4c76b7 | 4914 | |
8ec9650e | 4915 | (define_insn "*lshrdi3_const1" |
4916 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4917 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4918 | (const_int 1)))] | |
4919 | "!TARGET_COLDFIRE" | |
4920 | "lsr%.l #1,%0\;roxr%.l #1,%R0") | |
4921 | ||
4922 | (define_split | |
4923 | [(set (match_operand:DI 0 "register_operand" "") | |
4924 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4925 | (const_int 2)))] | |
4926 | "reload_completed && !TARGET_COLDFIRE" | |
4927 | [(set (match_dup 0) | |
4928 | (lshiftrt:DI (match_dup 1) (const_int 1))) | |
4929 | (set (match_dup 0) | |
4930 | (lshiftrt:DI (match_dup 0) (const_int 1)))] | |
4931 | "") | |
4932 | ||
4933 | (define_split | |
4934 | [(set (match_operand:DI 0 "register_operand" "") | |
4935 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4936 | (const_int 3)))] | |
4937 | "reload_completed && !TARGET_COLDFIRE" | |
4938 | [(set (match_dup 0) | |
4939 | (lshiftrt:DI (match_dup 1) (const_int 2))) | |
4940 | (set (match_dup 0) | |
4941 | (lshiftrt:DI (match_dup 0) (const_int 1)))] | |
4942 | "") | |
4943 | ||
4944 | (define_split | |
4945 | [(set (match_operand:DI 0 "register_operand" "") | |
4946 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4947 | (const_int 8)))] | |
4948 | "reload_completed && !TARGET_COLDFIRE" | |
4949 | [(set (strict_low_part (subreg:QI (match_dup 0) 7)) | |
4950 | (subreg:QI (match_dup 0) 3)) | |
4951 | (set (match_dup 2) | |
4952 | (lshiftrt:SI (match_dup 2) (const_int 8))) | |
4953 | (set (match_dup 3) | |
4954 | (rotatert:SI (match_dup 3) (const_int 8)))] | |
4955 | { | |
4956 | operands[2] = gen_highpart (SImode, operands[0]); | |
4957 | operands[3] = gen_lowpart (SImode, operands[0]); | |
4958 | }) | |
4959 | ||
4960 | (define_split | |
4961 | [(set (match_operand:DI 0 "register_operand" "") | |
4962 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
4963 | (const_int 16)))] | |
4964 | "reload_completed && !TARGET_COLDFIRE" | |
4965 | [(set (strict_low_part (subreg:HI (match_dup 0) 6)) | |
4966 | (subreg:HI (match_dup 0) 2)) | |
4967 | (set (strict_low_part (subreg:HI (match_dup 0) 2)) | |
4968 | (const_int 0)) | |
4969 | (set (match_dup 3) | |
4970 | (rotate:SI (match_dup 3) (const_int 16))) | |
4971 | (set (match_dup 2) | |
4972 | (rotate:SI (match_dup 2) (const_int 16)))] | |
4973 | { | |
4974 | operands[2] = gen_highpart (SImode, operands[0]); | |
4975 | operands[3] = gen_lowpart (SImode, operands[0]); | |
4976 | }) | |
4977 | ||
4978 | (define_split | |
4979 | [(set (match_operand:DI 0 "pre_dec_operand" "") | |
4980 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4981 | (const_int 32)))] | |
4982 | "reload_completed" | |
4983 | [(set (match_dup 0) (match_dup 1)) | |
4984 | (set (match_dup 0) (const_int 0))] | |
4985 | { | |
4986 | operands[0] = adjust_address(operands[0], SImode, 0); | |
4987 | operands[1] = gen_highpart(SImode, operands[1]); | |
4988 | }) | |
4989 | ||
4990 | (define_split | |
4991 | [(set (match_operand:DI 0 "post_inc_operand" "") | |
4992 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4993 | (const_int 32)))] | |
4994 | "reload_completed" | |
4995 | [(set (match_dup 0) (const_int 0)) | |
4996 | (set (match_dup 0) (match_dup 1))] | |
4997 | { | |
4998 | operands[0] = adjust_address(operands[0], SImode, 0); | |
4999 | operands[1] = gen_highpart(SImode, operands[1]); | |
5000 | }) | |
5001 | ||
5002 | (define_split | |
5003 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5004 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5005 | (const_int 32)))] | |
5006 | "reload_completed" | |
5007 | [(set (match_dup 2) (match_dup 5)) | |
5008 | (set (match_dup 4) (const_int 0))] | |
5009 | "split_di(operands, 2, operands + 2, operands + 4);") | |
5010 | ||
5011 | (define_insn "*lshrdi_const32" | |
5012 | [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>") | |
5013 | (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro") | |
5e4c76b7 | 5014 | (const_int 32)))] |
5015 | "" | |
8ec9650e | 5016 | "#") |
5017 | ||
5018 | (define_split | |
5019 | [(set (match_operand:DI 0 "register_operand" "") | |
5020 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5021 | (match_operand 2 "const_int_operand" "")))] | |
5022 | "reload_completed && !TARGET_COLDFIRE | |
5023 | && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40" | |
5024 | [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2))) | |
5025 | (set (match_dup 4) (match_dup 3)) | |
5026 | (set (match_dup 3) (const_int 0))] | |
5e4c76b7 | 5027 | { |
8ec9650e | 5028 | operands[2] = GEN_INT (INTVAL (operands[2]) - 32); |
5029 | operands[3] = gen_highpart (SImode, operands[0]); | |
5030 | operands[4] = gen_lowpart (SImode, operands[0]); | |
2de9355b | 5031 | }) |
5e4c76b7 | 5032 | |
8ec9650e | 5033 | (define_split |
5034 | [(set (match_operand:DI 0 "register_operand" "") | |
5035 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5036 | (const_int 48)))] | |
5037 | "reload_completed" | |
5038 | [(set (match_dup 3) (match_dup 2)) | |
5039 | (set (strict_low_part (subreg:HI (match_dup 0) 6)) | |
5040 | (const_int 0)) | |
5041 | (set (match_dup 2) (const_int 0)) | |
5042 | (set (match_dup 3) | |
5043 | (rotate:SI (match_dup 3) (const_int 16)))] | |
5044 | { | |
5045 | operands[2] = gen_highpart (SImode, operands[0]); | |
5046 | operands[3] = gen_lowpart (SImode, operands[0]); | |
5047 | }) | |
5048 | ||
5049 | (define_split | |
5050 | [(set (match_operand:DI 0 "register_operand" "") | |
5051 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5052 | (match_operand 2 "const_int_operand" "")))] | |
5053 | "reload_completed && !TARGET_COLDFIRE | |
5054 | && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62" | |
5055 | [(set (match_dup 4) (match_dup 2)) | |
5056 | (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4))) | |
5057 | (set (match_dup 4) (match_dup 3)) | |
5058 | (set (match_dup 3) (const_int 0))] | |
5059 | { | |
5060 | operands[2] = GEN_INT (INTVAL (operands[2]) - 32); | |
5061 | operands[3] = gen_highpart (SImode, operands[0]); | |
5062 | operands[4] = gen_lowpart (SImode, operands[0]); | |
5063 | }) | |
5064 | ||
5065 | (define_insn "*lshrdi_const63" | |
5066 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5067 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
5068 | (const_int 63)))] | |
5069 | "" | |
5070 | "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1") | |
5071 | ||
5072 | (define_insn "*lshrdi3_const" | |
5073 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5074 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
5e4c76b7 | 5075 | (match_operand 2 "const_int_operand" "n")))] |
960e6739 | 5076 | "(!TARGET_COLDFIRE |
8ec9650e | 5077 | && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3) |
4f5b397b | 5078 | || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 |
5079 | || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" | |
8ec9650e | 5080 | "#") |
5e4c76b7 | 5081 | |
5082 | (define_expand "lshrdi3" | |
8ec9650e | 5083 | [(set (match_operand:DI 0 "register_operand" "") |
5084 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
d08c9ad7 | 5085 | (match_operand 2 "const_int_operand" "")))] |
960e6739 | 5086 | "!TARGET_COLDFIRE" |
5e4c76b7 | 5087 | { |
4f5b397b | 5088 | /* ??? This is a named pattern like this is not allowed to FAIL based |
5089 | on its operands. */ | |
5e4c76b7 | 5090 | if (GET_CODE (operands[2]) != CONST_INT |
4f5b397b | 5091 | || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) |
5092 | && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 | |
5093 | && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) | |
5e4c76b7 | 5094 | FAIL; |
2de9355b | 5095 | }) |
68048623 | 5096 | |
bdf74c8a | 5097 | ;; On all 68k models, this makes faster code in a special case. |
5098 | ||
5e4c76b7 | 5099 | (define_insn "lshrsi_31" |
5100 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5101 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
5102 | (const_int 31)))] | |
5103 | "" | |
5e4c76b7 | 5104 | { |
2de9355b | 5105 | return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0"; |
5106 | }) | |
5e4c76b7 | 5107 | |
4282b62a | 5108 | ;; On most 68k models, this makes faster code in a special case. |
5e4c76b7 | 5109 | |
5110 | (define_insn "lshrsi_16" | |
bdf74c8a | 5111 | [(set (match_operand:SI 0 "register_operand" "=d") |
5112 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
68048623 | 5113 | (const_int 16)))] |
bd40163f | 5114 | "!TUNE_68060" |
bdf74c8a | 5115 | { |
5116 | CC_STATUS_INIT; | |
2de9355b | 5117 | return "clr%.w %0\;swap %0"; |
5118 | }) | |
bdf74c8a | 5119 | |
c1dbe9ae | 5120 | ;; On the 68000, this makes faster code in a special case. |
5121 | ||
5e4c76b7 | 5122 | (define_insn "lshrsi_17_24" |
c1dbe9ae | 5123 | [(set (match_operand:SI 0 "register_operand" "=d") |
5124 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
68048623 | 5125 | (match_operand:SI 2 "const_int_operand" "n")))] |
bd40163f | 5126 | "TUNE_68000_10 |
5127 | && INTVAL (operands[2]) > 16 | |
5128 | && INTVAL (operands[2]) <= 24" | |
c1dbe9ae | 5129 | { |
c1dbe9ae | 5130 | /* I think lsr%.w sets the CC properly. */ |
e6b2f841 | 5131 | operands[2] = GEN_INT (INTVAL (operands[2]) - 16); |
2de9355b | 5132 | return "clr%.w %0\;swap %0\;lsr%.w %2,%0"; |
5133 | }) | |
c1dbe9ae | 5134 | |
5135 | (define_insn "lshrsi3" | |
5136 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5137 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
5138 | (match_operand:SI 2 "general_operand" "dI")))] | |
5139 | "" | |
1d86aeab | 5140 | "lsr%.l %2,%0" |
3c904dda | 5141 | [(set_attr "type" "shift") |
1d86aeab | 5142 | (set_attr "opy" "2")]) |
c1dbe9ae | 5143 | |
5144 | (define_insn "lshrhi3" | |
5145 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5146 | (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") | |
5147 | (match_operand:HI 2 "general_operand" "dI")))] | |
960e6739 | 5148 | "!TARGET_COLDFIRE" |
c1dbe9ae | 5149 | "lsr%.w %2,%0") |
5150 | ||
a45d833a | 5151 | (define_insn "" |
5152 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) | |
5153 | (lshiftrt:HI (match_dup 0) | |
5154 | (match_operand:HI 1 "general_operand" "dI")))] | |
960e6739 | 5155 | "!TARGET_COLDFIRE" |
a45d833a | 5156 | "lsr%.w %1,%0") |
5157 | ||
c1dbe9ae | 5158 | (define_insn "lshrqi3" |
5159 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5160 | (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") | |
5161 | (match_operand:QI 2 "general_operand" "dI")))] | |
960e6739 | 5162 | "!TARGET_COLDFIRE" |
c1dbe9ae | 5163 | "lsr%.b %2,%0") |
a45d833a | 5164 | |
5165 | (define_insn "" | |
5166 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) | |
5167 | (lshiftrt:QI (match_dup 0) | |
5168 | (match_operand:QI 1 "general_operand" "dI")))] | |
960e6739 | 5169 | "!TARGET_COLDFIRE" |
a45d833a | 5170 | "lsr%.b %1,%0") |
c1dbe9ae | 5171 | \f |
5172 | ;; rotate instructions | |
5173 | ||
41f22863 | 5174 | (define_insn "rotlsi_16" |
5175 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5176 | (rotate:SI (match_operand:SI 1 "register_operand" "0") | |
5177 | (const_int 16)))] | |
5178 | "" | |
5179 | "swap %0" | |
5180 | [(set_attr "type" "shift")]) | |
5181 | ||
c1dbe9ae | 5182 | (define_insn "rotlsi3" |
5183 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5184 | (rotate:SI (match_operand:SI 1 "register_operand" "0") | |
c68c8763 | 5185 | (match_operand:SI 2 "general_operand" "dINO")))] |
960e6739 | 5186 | "!TARGET_COLDFIRE" |
c68c8763 | 5187 | { |
5188 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16) | |
2de9355b | 5189 | return "swap %0"; |
c68c8763 | 5190 | else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16) |
5191 | { | |
e6b2f841 | 5192 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); |
2de9355b | 5193 | return "ror%.l %2,%0"; |
c68c8763 | 5194 | } |
5195 | else | |
2de9355b | 5196 | return "rol%.l %2,%0"; |
5197 | }) | |
c1dbe9ae | 5198 | |
5199 | (define_insn "rotlhi3" | |
5200 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5201 | (rotate:HI (match_operand:HI 1 "register_operand" "0") | |
c68c8763 | 5202 | (match_operand:HI 2 "general_operand" "dIP")))] |
960e6739 | 5203 | "!TARGET_COLDFIRE" |
c68c8763 | 5204 | { |
5205 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) | |
5206 | { | |
e6b2f841 | 5207 | operands[2] = GEN_INT (16 - INTVAL (operands[2])); |
2de9355b | 5208 | return "ror%.w %2,%0"; |
c68c8763 | 5209 | } |
5210 | else | |
2de9355b | 5211 | return "rol%.w %2,%0"; |
5212 | }) | |
a45d833a | 5213 | |
e2be515a | 5214 | (define_insn "*rotlhi3_lowpart" |
a45d833a | 5215 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) |
5216 | (rotate:HI (match_dup 0) | |
c68c8763 | 5217 | (match_operand:HI 1 "general_operand" "dIP")))] |
960e6739 | 5218 | "!TARGET_COLDFIRE" |
c68c8763 | 5219 | { |
e2be515a | 5220 | if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 8) |
c68c8763 | 5221 | { |
e2be515a | 5222 | operands[1] = GEN_INT (16 - INTVAL (operands[1])); |
5223 | return "ror%.w %1,%0"; | |
c68c8763 | 5224 | } |
5225 | else | |
e2be515a | 5226 | return "rol%.w %1,%0"; |
2de9355b | 5227 | }) |
a45d833a | 5228 | |
c1dbe9ae | 5229 | (define_insn "rotlqi3" |
5230 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5231 | (rotate:QI (match_operand:QI 1 "register_operand" "0") | |
5232 | (match_operand:QI 2 "general_operand" "dI")))] | |
960e6739 | 5233 | "!TARGET_COLDFIRE" |
c68c8763 | 5234 | { |
5235 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) | |
5236 | { | |
e6b2f841 | 5237 | operands[2] = GEN_INT (8 - INTVAL (operands[2])); |
2de9355b | 5238 | return "ror%.b %2,%0"; |
c68c8763 | 5239 | } |
5240 | else | |
2de9355b | 5241 | return "rol%.b %2,%0"; |
5242 | }) | |
c1dbe9ae | 5243 | |
e2be515a | 5244 | (define_insn "*rotlqi3_lowpart" |
a45d833a | 5245 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) |
5246 | (rotate:QI (match_dup 0) | |
5247 | (match_operand:QI 1 "general_operand" "dI")))] | |
960e6739 | 5248 | "!TARGET_COLDFIRE" |
c68c8763 | 5249 | { |
e2be515a | 5250 | if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 4) |
c68c8763 | 5251 | { |
e2be515a | 5252 | operands[1] = GEN_INT (8 - INTVAL (operands[1])); |
5253 | return "ror%.b %1,%0"; | |
c68c8763 | 5254 | } |
5255 | else | |
e2be515a | 5256 | return "rol%.b %1,%0"; |
2de9355b | 5257 | }) |
a45d833a | 5258 | |
c1dbe9ae | 5259 | (define_insn "rotrsi3" |
5260 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5261 | (rotatert:SI (match_operand:SI 1 "register_operand" "0") | |
5262 | (match_operand:SI 2 "general_operand" "dI")))] | |
960e6739 | 5263 | "!TARGET_COLDFIRE" |
c1dbe9ae | 5264 | "ror%.l %2,%0") |
5265 | ||
5266 | (define_insn "rotrhi3" | |
5267 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5268 | (rotatert:HI (match_operand:HI 1 "register_operand" "0") | |
5269 | (match_operand:HI 2 "general_operand" "dI")))] | |
960e6739 | 5270 | "!TARGET_COLDFIRE" |
c1dbe9ae | 5271 | "ror%.w %2,%0") |
5272 | ||
886bfde4 | 5273 | (define_insn "rotrhi_lowpart" |
a45d833a | 5274 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) |
5275 | (rotatert:HI (match_dup 0) | |
5276 | (match_operand:HI 1 "general_operand" "dI")))] | |
960e6739 | 5277 | "!TARGET_COLDFIRE" |
a45d833a | 5278 | "ror%.w %1,%0") |
5279 | ||
c1dbe9ae | 5280 | (define_insn "rotrqi3" |
5281 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5282 | (rotatert:QI (match_operand:QI 1 "register_operand" "0") | |
5283 | (match_operand:QI 2 "general_operand" "dI")))] | |
960e6739 | 5284 | "!TARGET_COLDFIRE" |
c1dbe9ae | 5285 | "ror%.b %2,%0") |
a45d833a | 5286 | |
5287 | (define_insn "" | |
5288 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) | |
5289 | (rotatert:QI (match_dup 0) | |
5290 | (match_operand:QI 1 "general_operand" "dI")))] | |
960e6739 | 5291 | "!TARGET_COLDFIRE" |
a45d833a | 5292 | "ror%.b %1,%0") |
886bfde4 | 5293 | |
5294 | (define_expand "bswapsi2" | |
5295 | [(set (match_operand:SI 0 "register_operand") | |
5296 | (bswap:SI (match_operand:SI 1 "register_operand")))] | |
5297 | "!TARGET_COLDFIRE" | |
5298 | { | |
5299 | rtx x = operands[0]; | |
5300 | emit_move_insn (x, operands[1]); | |
5301 | emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8))); | |
5302 | emit_insn (gen_rotlsi3 (x, x, GEN_INT (16))); | |
5303 | emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8))); | |
5304 | DONE; | |
5305 | }) | |
c1dbe9ae | 5306 | \f |
57a52c8d | 5307 | |
5308 | ;; Bit set/clear in memory byte. | |
5309 | ||
5310 | ;; set bit, bit number is int | |
5311 | (define_insn "bsetmemqi" | |
5312 | [(set (match_operand:QI 0 "memory_operand" "+m") | |
5313 | (ior:QI (subreg:QI (ashift:SI (const_int 1) | |
00f41fc3 | 5314 | (match_operand:SI 1 "general_operand" "d")) 3) |
57a52c8d | 5315 | (match_dup 0)))] |
5316 | "" | |
57a52c8d | 5317 | { |
5318 | CC_STATUS_INIT; | |
2de9355b | 5319 | return "bset %1,%0"; |
1d86aeab | 5320 | } |
3c904dda | 5321 | [(set_attr "type" "bitrw")]) |
57a52c8d | 5322 | |
5323 | ;; set bit, bit number is (sign/zero)_extended from HImode/QImode | |
1d86aeab | 5324 | (define_insn "*bsetmemqi_ext" |
57a52c8d | 5325 | [(set (match_operand:QI 0 "memory_operand" "+m") |
5326 | (ior:QI (subreg:QI (ashift:SI (const_int 1) | |
5327 | (match_operator:SI 2 "extend_operator" | |
00f41fc3 | 5328 | [(match_operand 1 "general_operand" "d")])) 3) |
57a52c8d | 5329 | (match_dup 0)))] |
5330 | "" | |
57a52c8d | 5331 | { |
5332 | CC_STATUS_INIT; | |
2de9355b | 5333 | return "bset %1,%0"; |
1d86aeab | 5334 | } |
3c904dda | 5335 | [(set_attr "type" "bitrw")]) |
57a52c8d | 5336 | |
5337 | ;; clear bit, bit number is int | |
5338 | (define_insn "bclrmemqi" | |
5339 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") | |
5340 | (const_int 1) | |
5341 | (minus:SI (const_int 7) | |
5342 | (match_operand:SI 1 "general_operand" "d"))) | |
5343 | (const_int 0))] | |
5344 | "" | |
57a52c8d | 5345 | { |
5346 | CC_STATUS_INIT; | |
2de9355b | 5347 | return "bclr %1,%0"; |
1d86aeab | 5348 | } |
3c904dda | 5349 | [(set_attr "type" "bitrw")]) |
57a52c8d | 5350 | |
5351 | ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode | |
1d86aeab | 5352 | (define_insn "*bclrmemqi_ext" |
57a52c8d | 5353 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") |
5354 | (const_int 1) | |
5355 | (minus:SI (const_int 7) | |
5356 | (match_operator:SI 2 "extend_operator" | |
5357 | [(match_operand 1 "general_operand" "d")]))) | |
5358 | (const_int 0))] | |
5359 | "" | |
57a52c8d | 5360 | { |
5361 | CC_STATUS_INIT; | |
2de9355b | 5362 | return "bclr %1,%0"; |
1d86aeab | 5363 | } |
3c904dda | 5364 | [(set_attr "type" "bitrw")]) |
57a52c8d | 5365 | |
c1dbe9ae | 5366 | ;; Special cases of bit-field insns which we should |
5367 | ;; recognize in preference to the general case. | |
5368 | ;; These handle aligned 8-bit and 16-bit fields, | |
5369 | ;; which can usually be done with move instructions. | |
5370 | ||
5371 | ; | |
5372 | ; Special case for 32-bit field in memory. This only occurs when 32-bit | |
5373 | ; alignment of structure members is specified. | |
5374 | ; | |
5375 | ; The move is allowed to be odd byte aligned, because that's still faster | |
b14b4511 | 5376 | ; than an odd byte aligned bit-field instruction. |
c1dbe9ae | 5377 | ; |
facacc46 | 5378 | (define_insn "*insv_32_mem" |
532c99f2 | 5379 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") |
68048623 | 5380 | (const_int 32) |
dd193d7c | 5381 | (match_operand:SI 1 "const_int_operand" "n")) |
5382 | (match_operand:SI 2 "general_src_operand" "rmSi"))] | |
c1dbe9ae | 5383 | "TARGET_68020 && TARGET_BITFIELD |
dd193d7c | 5384 | && (INTVAL (operands[1]) % 8) == 0 |
4e27ffd0 | 5385 | && ! mode_dependent_address_p (XEXP (operands[0], 0), |
5386 | MEM_ADDR_SPACE (operands[0]))" | |
c1dbe9ae | 5387 | { |
5388 | operands[0] | |
eafc6604 | 5389 | = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8); |
c1dbe9ae | 5390 | |
2de9355b | 5391 | return "move%.l %2,%0"; |
5392 | }) | |
c1dbe9ae | 5393 | |
facacc46 | 5394 | (define_insn "*insv_8_16_reg" |
5395 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") | |
68048623 | 5396 | (match_operand:SI 1 "const_int_operand" "n") |
5397 | (match_operand:SI 2 "const_int_operand" "n")) | |
5398 | (match_operand:SI 3 "register_operand" "d"))] | |
c1dbe9ae | 5399 | "TARGET_68020 && TARGET_BITFIELD |
c1dbe9ae | 5400 | && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) |
facacc46 | 5401 | && INTVAL (operands[2]) % INTVAL (operands[1]) == 0" |
c1dbe9ae | 5402 | { |
facacc46 | 5403 | if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) |
5404 | return "bfins %3,%0{%b2:%b1}"; | |
eafc6604 | 5405 | |
c1dbe9ae | 5406 | if (INTVAL (operands[1]) == 8) |
2de9355b | 5407 | return "move%.b %3,%0"; |
5408 | return "move%.w %3,%0"; | |
5409 | }) | |
c1dbe9ae | 5410 | |
5411 | ||
5412 | ; | |
5413 | ; Special case for 32-bit field in memory. This only occurs when 32-bit | |
5414 | ; alignment of structure members is specified. | |
5415 | ; | |
5416 | ; The move is allowed to be odd byte aligned, because that's still faster | |
b14b4511 | 5417 | ; than an odd byte aligned bit-field instruction. |
c1dbe9ae | 5418 | ; |
facacc46 | 5419 | (define_insn "*extzv_32_mem" |
c4af10f0 | 5420 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
f0ecff58 | 5421 | (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS") |
68048623 | 5422 | (const_int 32) |
dd193d7c | 5423 | (match_operand:SI 2 "const_int_operand" "n")))] |
c1dbe9ae | 5424 | "TARGET_68020 && TARGET_BITFIELD |
dd193d7c | 5425 | && (INTVAL (operands[2]) % 8) == 0 |
4e27ffd0 | 5426 | && ! mode_dependent_address_p (XEXP (operands[1], 0), |
5427 | MEM_ADDR_SPACE (operands[1]))" | |
c1dbe9ae | 5428 | { |
5429 | operands[1] | |
eafc6604 | 5430 | = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8); |
c1dbe9ae | 5431 | |
2de9355b | 5432 | return "move%.l %1,%0"; |
5433 | }) | |
c1dbe9ae | 5434 | |
facacc46 | 5435 | (define_insn "*extzv_8_16_reg" |
c4af10f0 | 5436 | [(set (match_operand:SI 0 "nonimmediate_operand" "=&d") |
facacc46 | 5437 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
68048623 | 5438 | (match_operand:SI 2 "const_int_operand" "n") |
5439 | (match_operand:SI 3 "const_int_operand" "n")))] | |
c1dbe9ae | 5440 | "TARGET_68020 && TARGET_BITFIELD |
ed51cc0c | 5441 | && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) |
facacc46 | 5442 | && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" |
c1dbe9ae | 5443 | { |
5444 | cc_status.flags |= CC_NOT_NEGATIVE; | |
facacc46 | 5445 | if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) |
5446 | return "bfextu %1{%b3:%b2},%0"; | |
c1dbe9ae | 5447 | |
2de9355b | 5448 | output_asm_insn ("clr%.l %0", operands); |
c1dbe9ae | 5449 | if (INTVAL (operands[2]) == 8) |
2de9355b | 5450 | return "move%.b %1,%0"; |
5451 | return "move%.w %1,%0"; | |
5452 | }) | |
c1dbe9ae | 5453 | |
5454 | ; | |
5455 | ; Special case for 32-bit field in memory. This only occurs when 32-bit | |
5456 | ; alignment of structure members is specified. | |
5457 | ; | |
5458 | ; The move is allowed to be odd byte aligned, because that's still faster | |
b14b4511 | 5459 | ; than an odd byte aligned bit-field instruction. |
c1dbe9ae | 5460 | ; |
facacc46 | 5461 | (define_insn "*extv_32_mem" |
c4af10f0 | 5462 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
f0ecff58 | 5463 | (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS") |
68048623 | 5464 | (const_int 32) |
dd193d7c | 5465 | (match_operand:SI 2 "const_int_operand" "n")))] |
c1dbe9ae | 5466 | "TARGET_68020 && TARGET_BITFIELD |
dd193d7c | 5467 | && (INTVAL (operands[2]) % 8) == 0 |
4e27ffd0 | 5468 | && ! mode_dependent_address_p (XEXP (operands[1], 0), |
5469 | MEM_ADDR_SPACE (operands[1]))" | |
c1dbe9ae | 5470 | { |
5471 | operands[1] | |
eafc6604 | 5472 | = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8); |
c1dbe9ae | 5473 | |
2de9355b | 5474 | return "move%.l %1,%0"; |
5475 | }) | |
c1dbe9ae | 5476 | |
facacc46 | 5477 | (define_insn "*extv_8_16_reg" |
c4af10f0 | 5478 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
facacc46 | 5479 | (sign_extract:SI (match_operand:SI 1 "register_operand" "d") |
68048623 | 5480 | (match_operand:SI 2 "const_int_operand" "n") |
5481 | (match_operand:SI 3 "const_int_operand" "n")))] | |
c1dbe9ae | 5482 | "TARGET_68020 && TARGET_BITFIELD |
ed51cc0c | 5483 | && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) |
facacc46 | 5484 | && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" |
c1dbe9ae | 5485 | { |
facacc46 | 5486 | if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) |
5487 | return "bfexts %1{%b3:%b2},%0"; | |
c1dbe9ae | 5488 | |
5489 | if (INTVAL (operands[2]) == 8) | |
2de9355b | 5490 | return "move%.b %1,%0\;extb%.l %0"; |
5491 | return "move%.w %1,%0\;ext%.l %0"; | |
5492 | }) | |
c1dbe9ae | 5493 | \f |
b14b4511 | 5494 | ;; Bit-field instructions, general cases. |
c1dbe9ae | 5495 | ;; "o,d" constraint causes a nonoffsettable memref to match the "o" |
5496 | ;; so that its address is reloaded. | |
5497 | ||
532c99f2 | 5498 | (define_expand "extv" |
894a8d28 | 5499 | [(set (match_operand:SI 0 "register_operand" "") |
532c99f2 | 5500 | (sign_extract:SI (match_operand:SI 1 "general_operand" "") |
894a8d28 | 5501 | (match_operand:SI 2 "const_int_operand" "") |
5502 | (match_operand:SI 3 "const_int_operand" "")))] | |
532c99f2 | 5503 | "TARGET_68020 && TARGET_BITFIELD" |
5504 | "") | |
5505 | ||
facacc46 | 5506 | (define_insn "*extv_bfexts_mem" |
894a8d28 | 5507 | [(set (match_operand:SI 0 "register_operand" "=d") |
532c99f2 | 5508 | (sign_extract:SI (match_operand:QI 1 "memory_operand" "o") |
894a8d28 | 5509 | (match_operand:SI 2 "nonmemory_operand" "dn") |
5510 | (match_operand:SI 3 "nonmemory_operand" "dn")))] | |
c1dbe9ae | 5511 | "TARGET_68020 && TARGET_BITFIELD" |
4ad53767 | 5512 | "bfexts %1{%b3:%b2},%0") |
c1dbe9ae | 5513 | |
532c99f2 | 5514 | (define_expand "extzv" |
894a8d28 | 5515 | [(set (match_operand:SI 0 "register_operand" "") |
532c99f2 | 5516 | (zero_extract:SI (match_operand:SI 1 "general_operand" "") |
894a8d28 | 5517 | (match_operand:SI 2 "const_int_operand" "") |
5518 | (match_operand:SI 3 "const_int_operand" "")))] | |
532c99f2 | 5519 | "TARGET_68020 && TARGET_BITFIELD" |
5520 | "") | |
5521 | ||
facacc46 | 5522 | (define_insn "*extzv_bfextu_mem" |
894a8d28 | 5523 | [(set (match_operand:SI 0 "register_operand" "=d") |
5524 | (zero_extract:SI (match_operand:QI 1 "memory_operand" "o") | |
5525 | (match_operand:SI 2 "nonmemory_operand" "dn") | |
5526 | (match_operand:SI 3 "nonmemory_operand" "dn")))] | |
c1dbe9ae | 5527 | "TARGET_68020 && TARGET_BITFIELD" |
c1dbe9ae | 5528 | { |
355b9680 | 5529 | if (GET_CODE (operands[2]) == CONST_INT) |
5530 | { | |
5531 | if (INTVAL (operands[2]) != 32) | |
5532 | cc_status.flags |= CC_NOT_NEGATIVE; | |
5533 | } | |
5534 | else | |
5535 | { | |
5536 | CC_STATUS_INIT; | |
5537 | } | |
4ad53767 | 5538 | return "bfextu %1{%b3:%b2},%0"; |
2de9355b | 5539 | }) |
c1dbe9ae | 5540 | |
facacc46 | 5541 | (define_insn "*insv_bfchg_mem" |
532c99f2 | 5542 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") |
894a8d28 | 5543 | (match_operand:SI 1 "nonmemory_operand" "dn") |
5544 | (match_operand:SI 2 "nonmemory_operand" "dn")) | |
c1dbe9ae | 5545 | (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) |
532c99f2 | 5546 | (match_operand 3 "const_int_operand" "n")))] |
c1dbe9ae | 5547 | "TARGET_68020 && TARGET_BITFIELD |
c1dbe9ae | 5548 | && (INTVAL (operands[3]) == -1 |
5549 | || (GET_CODE (operands[1]) == CONST_INT | |
5550 | && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" | |
c1dbe9ae | 5551 | { |
5552 | CC_STATUS_INIT; | |
4ad53767 | 5553 | return "bfchg %0{%b2:%b1}"; |
2de9355b | 5554 | }) |
c1dbe9ae | 5555 | |
facacc46 | 5556 | (define_insn "*insv_bfclr_mem" |
532c99f2 | 5557 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") |
894a8d28 | 5558 | (match_operand:SI 1 "nonmemory_operand" "dn") |
5559 | (match_operand:SI 2 "nonmemory_operand" "dn")) | |
c1dbe9ae | 5560 | (const_int 0))] |
5561 | "TARGET_68020 && TARGET_BITFIELD" | |
c1dbe9ae | 5562 | { |
5563 | CC_STATUS_INIT; | |
4ad53767 | 5564 | return "bfclr %0{%b2:%b1}"; |
2de9355b | 5565 | }) |
c1dbe9ae | 5566 | |
facacc46 | 5567 | (define_insn "*insv_bfset_mem" |
532c99f2 | 5568 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") |
f9854e90 | 5569 | (match_operand:SI 1 "general_operand" "dn") |
5570 | (match_operand:SI 2 "general_operand" "dn")) | |
c1dbe9ae | 5571 | (const_int -1))] |
5572 | "TARGET_68020 && TARGET_BITFIELD" | |
c1dbe9ae | 5573 | { |
5574 | CC_STATUS_INIT; | |
4ad53767 | 5575 | return "bfset %0{%b2:%b1}"; |
2de9355b | 5576 | }) |
c1dbe9ae | 5577 | |
532c99f2 | 5578 | (define_expand "insv" |
c4af10f0 | 5579 | [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "") |
894a8d28 | 5580 | (match_operand:SI 1 "const_int_operand" "") |
5581 | (match_operand:SI 2 "const_int_operand" "")) | |
8dc239d3 | 5582 | (match_operand:SI 3 "reg_or_pow2_m1_operand" ""))] |
532c99f2 | 5583 | "TARGET_68020 && TARGET_BITFIELD" |
8dc239d3 | 5584 | " |
5585 | { | |
5586 | /* Special case initializing a field to all ones. */ | |
5587 | if (GET_CODE (operands[3]) == CONST_INT) | |
5588 | { | |
5589 | if (exact_log2 (INTVAL (operands[3]) + 1) != INTVAL (operands[1])) | |
5590 | operands[3] = force_reg (SImode, operands[3]); | |
5591 | else | |
5592 | operands[3] = constm1_rtx; | |
5593 | ||
5594 | } | |
5595 | }") | |
532c99f2 | 5596 | |
facacc46 | 5597 | (define_insn "*insv_bfins_mem" |
532c99f2 | 5598 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") |
894a8d28 | 5599 | (match_operand:SI 1 "nonmemory_operand" "dn") |
5600 | (match_operand:SI 2 "nonmemory_operand" "dn")) | |
532c99f2 | 5601 | (match_operand:SI 3 "register_operand" "d"))] |
c1dbe9ae | 5602 | "TARGET_68020 && TARGET_BITFIELD" |
4ad53767 | 5603 | "bfins %3,%0{%b2:%b1}") |
c1dbe9ae | 5604 | |
b14b4511 | 5605 | ;; Now recognize bit-field insns that operate on registers |
c1dbe9ae | 5606 | ;; (or at least were intended to do so). |
5607 | ||
facacc46 | 5608 | (define_insn "*extv_bfexts_reg" |
c4af10f0 | 5609 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
532c99f2 | 5610 | (sign_extract:SI (match_operand:SI 1 "register_operand" "d") |
894a8d28 | 5611 | (match_operand:SI 2 "const_int_operand" "n") |
5612 | (match_operand:SI 3 "const_int_operand" "n")))] | |
c1dbe9ae | 5613 | "TARGET_68020 && TARGET_BITFIELD" |
4ad53767 | 5614 | "bfexts %1{%b3:%b2},%0") |
c1dbe9ae | 5615 | |
facacc46 | 5616 | (define_insn "*extv_bfextu_reg" |
c4af10f0 | 5617 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
532c99f2 | 5618 | (zero_extract:SI (match_operand:SI 1 "register_operand" "d") |
894a8d28 | 5619 | (match_operand:SI 2 "const_int_operand" "n") |
5620 | (match_operand:SI 3 "const_int_operand" "n")))] | |
c1dbe9ae | 5621 | "TARGET_68020 && TARGET_BITFIELD" |
c1dbe9ae | 5622 | { |
355b9680 | 5623 | if (GET_CODE (operands[2]) == CONST_INT) |
5624 | { | |
5625 | if (INTVAL (operands[2]) != 32) | |
5626 | cc_status.flags |= CC_NOT_NEGATIVE; | |
5627 | } | |
5628 | else | |
5629 | { | |
5630 | CC_STATUS_INIT; | |
5631 | } | |
4ad53767 | 5632 | return "bfextu %1{%b3:%b2},%0"; |
2de9355b | 5633 | }) |
c1dbe9ae | 5634 | |
facacc46 | 5635 | (define_insn "*insv_bfclr_reg" |
532c99f2 | 5636 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") |
894a8d28 | 5637 | (match_operand:SI 1 "const_int_operand" "n") |
5638 | (match_operand:SI 2 "const_int_operand" "n")) | |
c1dbe9ae | 5639 | (const_int 0))] |
5640 | "TARGET_68020 && TARGET_BITFIELD" | |
c1dbe9ae | 5641 | { |
5642 | CC_STATUS_INIT; | |
4ad53767 | 5643 | return "bfclr %0{%b2:%b1}"; |
2de9355b | 5644 | }) |
c1dbe9ae | 5645 | |
facacc46 | 5646 | (define_insn "*insv_bfset_reg" |
532c99f2 | 5647 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") |
894a8d28 | 5648 | (match_operand:SI 1 "const_int_operand" "n") |
5649 | (match_operand:SI 2 "const_int_operand" "n")) | |
c1dbe9ae | 5650 | (const_int -1))] |
5651 | "TARGET_68020 && TARGET_BITFIELD" | |
c1dbe9ae | 5652 | { |
5653 | CC_STATUS_INIT; | |
4ad53767 | 5654 | return "bfset %0{%b2:%b1}"; |
2de9355b | 5655 | }) |
c1dbe9ae | 5656 | |
facacc46 | 5657 | (define_insn "*insv_bfins_reg" |
532c99f2 | 5658 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") |
894a8d28 | 5659 | (match_operand:SI 1 "const_int_operand" "n") |
5660 | (match_operand:SI 2 "const_int_operand" "n")) | |
68048623 | 5661 | (match_operand:SI 3 "register_operand" "d"))] |
c1dbe9ae | 5662 | "TARGET_68020 && TARGET_BITFIELD" |
c1dbe9ae | 5663 | { |
5664 | #if 0 | |
5665 | /* These special cases are now recognized by a specific pattern. */ | |
5666 | if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT | |
5667 | && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) | |
2de9355b | 5668 | return "move%.w %3,%0"; |
c1dbe9ae | 5669 | if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT |
5670 | && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) | |
2de9355b | 5671 | return "move%.b %3,%0"; |
c1dbe9ae | 5672 | #endif |
4ad53767 | 5673 | return "bfins %3,%0{%b2:%b1}"; |
2de9355b | 5674 | }) |
c1dbe9ae | 5675 | \f |
5676 | ;; Special patterns for optimizing bit-field instructions. | |
5677 | ||
facacc46 | 5678 | (define_insn "*tst_bftst_mem" |
c1dbe9ae | 5679 | [(set (cc0) |
74f4459c | 5680 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") |
5681 | (match_operand:SI 1 "const_int_operand" "n") | |
5682 | (match_operand:SI 2 "general_operand" "dn")) | |
5683 | (const_int 0)))] | |
68048623 | 5684 | "TARGET_68020 && TARGET_BITFIELD" |
c1dbe9ae | 5685 | { |
5686 | if (operands[1] == const1_rtx | |
5687 | && GET_CODE (operands[2]) == CONST_INT) | |
3f6dfb87 | 5688 | { |
c1dbe9ae | 5689 | int width = GET_CODE (operands[0]) == REG ? 31 : 7; |
5690 | return output_btst (operands, | |
e6b2f841 | 5691 | GEN_INT (width - INTVAL (operands[2])), |
7014838c | 5692 | operands[0], insn, 1000); |
c1dbe9ae | 5693 | /* Pass 1000 as SIGNPOS argument so that btst will |
5694 | not think we are testing the sign bit for an `and' | |
5695 | and assume that nonzero implies a negative result. */ | |
5696 | } | |
5697 | if (INTVAL (operands[1]) != 32) | |
5698 | cc_status.flags = CC_NOT_NEGATIVE; | |
4ad53767 | 5699 | return "bftst %0{%b2:%b1}"; |
2de9355b | 5700 | }) |
c1dbe9ae | 5701 | |
3f6dfb87 | 5702 | |
c1dbe9ae | 5703 | ;;; now handle the register cases |
facacc46 | 5704 | (define_insn "*tst_bftst_reg" |
c1dbe9ae | 5705 | [(set (cc0) |
74f4459c | 5706 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
5707 | (match_operand:SI 1 "const_int_operand" "n") | |
5708 | (match_operand:SI 2 "general_operand" "dn")) | |
5709 | (const_int 0)))] | |
68048623 | 5710 | "TARGET_68020 && TARGET_BITFIELD" |
c1dbe9ae | 5711 | { |
5712 | if (operands[1] == const1_rtx | |
5713 | && GET_CODE (operands[2]) == CONST_INT) | |
3f6dfb87 | 5714 | { |
c1dbe9ae | 5715 | int width = GET_CODE (operands[0]) == REG ? 31 : 7; |
7014838c | 5716 | return output_btst (operands, GEN_INT (width - INTVAL (operands[2])), |
5717 | operands[0], insn, 1000); | |
c1dbe9ae | 5718 | /* Pass 1000 as SIGNPOS argument so that btst will |
5719 | not think we are testing the sign bit for an `and' | |
5720 | and assume that nonzero implies a negative result. */ | |
5721 | } | |
5722 | if (INTVAL (operands[1]) != 32) | |
5723 | cc_status.flags = CC_NOT_NEGATIVE; | |
4ad53767 | 5724 | return "bftst %0{%b2:%b1}"; |
2de9355b | 5725 | }) |
c1dbe9ae | 5726 | \f |
d08c9ad7 | 5727 | (define_insn "scc0_di" |
c4af10f0 | 5728 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") |
74f4459c | 5729 | (match_operator 1 "ordered_comparison_operator" |
d08c9ad7 | 5730 | [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] |
960e6739 | 5731 | "! TARGET_COLDFIRE" |
0e5f101c | 5732 | { |
5733 | return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); | |
2de9355b | 5734 | }) |
0e5f101c | 5735 | |
5736 | (define_insn "scc0_di_5200" | |
c4af10f0 | 5737 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d") |
74f4459c | 5738 | (match_operator 1 "ordered_comparison_operator" |
0e5f101c | 5739 | [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] |
960e6739 | 5740 | "TARGET_COLDFIRE" |
d08c9ad7 | 5741 | { |
5742 | return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); | |
2de9355b | 5743 | }) |
d08c9ad7 | 5744 | |
5745 | (define_insn "scc_di" | |
c4af10f0 | 5746 | [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm") |
74f4459c | 5747 | (match_operator 1 "ordered_comparison_operator" |
d08c9ad7 | 5748 | [(match_operand:DI 2 "general_operand" "ro,r") |
5749 | (match_operand:DI 3 "general_operand" "r,ro")]))] | |
960e6739 | 5750 | "! TARGET_COLDFIRE" |
0e5f101c | 5751 | { |
5752 | return output_scc_di (operands[1], operands[2], operands[3], operands[0]); | |
2de9355b | 5753 | }) |
0e5f101c | 5754 | |
5755 | (define_insn "scc_di_5200" | |
c4af10f0 | 5756 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d") |
74f4459c | 5757 | (match_operator 1 "ordered_comparison_operator" |
0e5f101c | 5758 | [(match_operand:DI 2 "general_operand" "ro,r") |
5759 | (match_operand:DI 3 "general_operand" "r,ro")]))] | |
960e6739 | 5760 | "TARGET_COLDFIRE" |
d08c9ad7 | 5761 | { |
5762 | return output_scc_di (operands[1], operands[2], operands[3], operands[0]); | |
2de9355b | 5763 | }) |
d08c9ad7 | 5764 | |
be2828ce | 5765 | ;; Note that operand 0 of an SCC insn is supported in the hardware as |
5766 | ;; memory, but we cannot allow it to be in memory in case the address | |
5767 | ;; needs to be reloaded. | |
5768 | ||
83843a0b | 5769 | (define_insn "" |
be2828ce | 5770 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5771 | (eq:QI (cc0) (const_int 0)))] |
be2828ce | 5772 | "" |
2de9355b | 5773 | { |
c1dbe9ae | 5774 | cc_status = cc_prev_status; |
2de9355b | 5775 | OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0"); |
5776 | }) | |
c1dbe9ae | 5777 | |
83843a0b | 5778 | (define_insn "" |
be2828ce | 5779 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5780 | (ne:QI (cc0) (const_int 0)))] |
be2828ce | 5781 | "" |
2de9355b | 5782 | { |
c1dbe9ae | 5783 | cc_status = cc_prev_status; |
2de9355b | 5784 | OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0"); |
5785 | }) | |
c1dbe9ae | 5786 | |
83843a0b | 5787 | (define_insn "" |
be2828ce | 5788 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5789 | (gt:QI (cc0) (const_int 0)))] |
be2828ce | 5790 | "" |
2de9355b | 5791 | { |
0e5f101c | 5792 | cc_status = cc_prev_status; |
2de9355b | 5793 | OUTPUT_JUMP ("sgt %0", "fsgt %0", 0); |
5794 | }) | |
0e5f101c | 5795 | |
0e5f101c | 5796 | (define_insn "" |
be2828ce | 5797 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5798 | (gtu:QI (cc0) (const_int 0)))] |
be2828ce | 5799 | "" |
2de9355b | 5800 | { |
5801 | cc_status = cc_prev_status; | |
5802 | return "shi %0"; | |
5803 | }) | |
c1dbe9ae | 5804 | |
83843a0b | 5805 | (define_insn "" |
be2828ce | 5806 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5807 | (lt:QI (cc0) (const_int 0)))] |
be2828ce | 5808 | "" |
2de9355b | 5809 | { |
be2828ce | 5810 | cc_status = cc_prev_status; |
2de9355b | 5811 | OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0"); |
5812 | }) | |
0e5f101c | 5813 | |
0e5f101c | 5814 | (define_insn "" |
be2828ce | 5815 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5816 | (ltu:QI (cc0) (const_int 0)))] |
be2828ce | 5817 | "" |
2de9355b | 5818 | { |
be2828ce | 5819 | cc_status = cc_prev_status; |
2de9355b | 5820 | return "scs %0"; |
5821 | }) | |
c1dbe9ae | 5822 | |
83843a0b | 5823 | (define_insn "" |
be2828ce | 5824 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5825 | (ge:QI (cc0) (const_int 0)))] |
be2828ce | 5826 | "" |
2de9355b | 5827 | { |
be2828ce | 5828 | cc_status = cc_prev_status; |
2de9355b | 5829 | OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0"); |
5830 | }) | |
0e5f101c | 5831 | |
1d86aeab | 5832 | (define_insn "*scc" |
be2828ce | 5833 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5834 | (geu:QI (cc0) (const_int 0)))] |
be2828ce | 5835 | "" |
2de9355b | 5836 | { |
be2828ce | 5837 | cc_status = cc_prev_status; |
2de9355b | 5838 | return "scc %0"; |
1d86aeab | 5839 | } |
5840 | [(set_attr "type" "scc")]) | |
c1dbe9ae | 5841 | |
83843a0b | 5842 | (define_insn "" |
be2828ce | 5843 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5844 | (le:QI (cc0) (const_int 0)))] |
be2828ce | 5845 | "" |
2de9355b | 5846 | { |
0e5f101c | 5847 | cc_status = cc_prev_status; |
2de9355b | 5848 | OUTPUT_JUMP ("sle %0", "fsle %0", 0); |
5849 | }) | |
0e5f101c | 5850 | |
1d86aeab | 5851 | (define_insn "*sls" |
be2828ce | 5852 | [(set (match_operand:QI 0 "register_operand" "=d") |
0e5f101c | 5853 | (leu:QI (cc0) (const_int 0)))] |
be2828ce | 5854 | "" |
2de9355b | 5855 | { |
be2828ce | 5856 | cc_status = cc_prev_status; |
2de9355b | 5857 | return "sls %0"; |
1d86aeab | 5858 | } |
5859 | [(set_attr "type" "scc")]) | |
e3323f4d | 5860 | |
e3323f4d | 5861 | (define_insn "*sordered_1" |
5862 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5863 | (ordered:QI (cc0) (const_int 0)))] | |
bd40163f | 5864 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5865 | { |
5866 | cc_status = cc_prev_status; | |
5867 | return "fsor %0"; | |
5868 | }) | |
5869 | ||
e3323f4d | 5870 | (define_insn "*sunordered_1" |
5871 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5872 | (unordered:QI (cc0) (const_int 0)))] | |
bd40163f | 5873 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5874 | { |
5875 | cc_status = cc_prev_status; | |
5876 | return "fsun %0"; | |
5877 | }) | |
5878 | ||
e3323f4d | 5879 | (define_insn "*suneq_1" |
5880 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5881 | (uneq:QI (cc0) (const_int 0)))] | |
bd40163f | 5882 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5883 | { |
5884 | cc_status = cc_prev_status; | |
5885 | return "fsueq %0"; | |
5886 | }) | |
5887 | ||
e3323f4d | 5888 | (define_insn "*sunge_1" |
5889 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5890 | (unge:QI (cc0) (const_int 0)))] | |
bd40163f | 5891 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5892 | { |
5893 | cc_status = cc_prev_status; | |
5894 | return "fsuge %0"; | |
5895 | }) | |
5896 | ||
e3323f4d | 5897 | (define_insn "*sungt_1" |
5898 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5899 | (ungt:QI (cc0) (const_int 0)))] | |
bd40163f | 5900 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5901 | { |
5902 | cc_status = cc_prev_status; | |
5903 | return "fsugt %0"; | |
5904 | }) | |
5905 | ||
e3323f4d | 5906 | (define_insn "*sunle_1" |
5907 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5908 | (unle:QI (cc0) (const_int 0)))] | |
bd40163f | 5909 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5910 | { |
5911 | cc_status = cc_prev_status; | |
5912 | return "fsule %0"; | |
5913 | }) | |
5914 | ||
e3323f4d | 5915 | (define_insn "*sunlt_1" |
5916 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5917 | (unlt:QI (cc0) (const_int 0)))] | |
bd40163f | 5918 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5919 | { |
5920 | cc_status = cc_prev_status; | |
5921 | return "fsult %0"; | |
5922 | }) | |
5923 | ||
e3323f4d | 5924 | (define_insn "*sltgt_1" |
5925 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5926 | (ltgt:QI (cc0) (const_int 0)))] | |
bd40163f | 5927 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5928 | { |
5929 | cc_status = cc_prev_status; | |
5930 | return "fsogl %0"; | |
5931 | }) | |
5932 | ||
5933 | (define_insn "*fsogt_1" | |
5934 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5935 | (not:QI (unle:QI (cc0) (const_int 0))))] | |
bd40163f | 5936 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5937 | { |
5938 | cc_status = cc_prev_status; | |
5939 | return "fsogt %0"; | |
5940 | }) | |
5941 | ||
5942 | (define_insn "*fsoge_1" | |
5943 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5944 | (not:QI (unlt:QI (cc0) (const_int 0))))] | |
bd40163f | 5945 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5946 | { |
5947 | cc_status = cc_prev_status; | |
5948 | return "fsoge %0"; | |
5949 | }) | |
5950 | ||
5951 | (define_insn "*fsolt_1" | |
5952 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5953 | (not:QI (unge:QI (cc0) (const_int 0))))] | |
bd40163f | 5954 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5955 | { |
5956 | cc_status = cc_prev_status; | |
5957 | return "fsolt %0"; | |
5958 | }) | |
5959 | ||
5960 | (define_insn "*fsole_1" | |
5961 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5962 | (not:QI (ungt:QI (cc0) (const_int 0))))] | |
bd40163f | 5963 | "TARGET_68881 && !TUNE_68060" |
e3323f4d | 5964 | { |
5965 | cc_status = cc_prev_status; | |
5966 | return "fsole %0"; | |
5967 | }) | |
c1dbe9ae | 5968 | \f |
5969 | ;; Basic conditional jump instructions. | |
5970 | ||
d08c9ad7 | 5971 | (define_insn "beq0_di" |
5972 | [(set (pc) | |
47a6c561 | 5973 | (if_then_else (eq (match_operand:DI 0 "general_operand" "d*a,o,<>") |
d08c9ad7 | 5974 | (const_int 0)) |
47a6c561 | 5975 | (label_ref (match_operand 1 "" ",,")) |
d08c9ad7 | 5976 | (pc))) |
47a6c561 | 5977 | (clobber (match_scratch:SI 2 "=d,&d,d"))] |
d08c9ad7 | 5978 | "" |
d08c9ad7 | 5979 | { |
3f6dfb87 | 5980 | CC_STATUS_INIT; |
47a6c561 | 5981 | if (which_alternative == 2) |
a1f3c748 | 5982 | return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1"; |
3f6dfb87 | 5983 | if ((cc_prev_status.value1 |
5984 | && rtx_equal_p (cc_prev_status.value1, operands[0])) | |
5985 | || (cc_prev_status.value2 | |
5986 | && rtx_equal_p (cc_prev_status.value2, operands[0]))) | |
5987 | { | |
5988 | cc_status = cc_prev_status; | |
a1f3c748 | 5989 | return "jeq %l1"; |
3f6dfb87 | 5990 | } |
d08c9ad7 | 5991 | if (GET_CODE (operands[0]) == REG) |
e6b2f841 | 5992 | operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
d08c9ad7 | 5993 | else |
eafc6604 | 5994 | operands[3] = adjust_address (operands[0], SImode, 4); |
d08c9ad7 | 5995 | if (! ADDRESS_REG_P (operands[0])) |
0dbd1c74 | 5996 | { |
31a5f8a0 | 5997 | if (reg_overlap_mentioned_p (operands[2], operands[0])) |
5998 | { | |
5999 | if (reg_overlap_mentioned_p (operands[2], operands[3])) | |
a1f3c748 | 6000 | return "or%.l %0,%2\;jeq %l1"; |
31a5f8a0 | 6001 | else |
a1f3c748 | 6002 | return "or%.l %3,%2\;jeq %l1"; |
31a5f8a0 | 6003 | } |
a1f3c748 | 6004 | return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1"; |
0dbd1c74 | 6005 | } |
d08c9ad7 | 6006 | operands[4] = gen_label_rtx(); |
960e6739 | 6007 | if (TARGET_68020 || TARGET_COLDFIRE) |
a1f3c748 | 6008 | output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands); |
a421ea47 | 6009 | else |
a1f3c748 | 6010 | output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands); |
2de9355b | 6011 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
d08c9ad7 | 6012 | CODE_LABEL_NUMBER (operands[4])); |
2de9355b | 6013 | return ""; |
6014 | }) | |
d08c9ad7 | 6015 | |
6016 | (define_insn "bne0_di" | |
6017 | [(set (pc) | |
47a6c561 | 6018 | (if_then_else (ne (match_operand:DI 0 "general_operand" "d,o,*a") |
d08c9ad7 | 6019 | (const_int 0)) |
47a6c561 | 6020 | (label_ref (match_operand 1 "" ",,")) |
d08c9ad7 | 6021 | (pc))) |
47a6c561 | 6022 | (clobber (match_scratch:SI 2 "=d,&d,X"))] |
d08c9ad7 | 6023 | "" |
d08c9ad7 | 6024 | { |
3f6dfb87 | 6025 | if ((cc_prev_status.value1 |
6026 | && rtx_equal_p (cc_prev_status.value1, operands[0])) | |
6027 | || (cc_prev_status.value2 | |
6028 | && rtx_equal_p (cc_prev_status.value2, operands[0]))) | |
6029 | { | |
6030 | cc_status = cc_prev_status; | |
a1f3c748 | 6031 | return "jne %l1"; |
3f6dfb87 | 6032 | } |
6033 | CC_STATUS_INIT; | |
d08c9ad7 | 6034 | if (GET_CODE (operands[0]) == REG) |
e6b2f841 | 6035 | operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
d08c9ad7 | 6036 | else |
eafc6604 | 6037 | operands[3] = adjust_address (operands[0], SImode, 4); |
a421ea47 | 6038 | if (!ADDRESS_REG_P (operands[0])) |
0dbd1c74 | 6039 | { |
31a5f8a0 | 6040 | if (reg_overlap_mentioned_p (operands[2], operands[0])) |
6041 | { | |
6042 | if (reg_overlap_mentioned_p (operands[2], operands[3])) | |
a1f3c748 | 6043 | return "or%.l %0,%2\;jne %l1"; |
31a5f8a0 | 6044 | else |
a1f3c748 | 6045 | return "or%.l %3,%2\;jne %l1"; |
31a5f8a0 | 6046 | } |
a1f3c748 | 6047 | return "move%.l %0,%2\;or%.l %3,%2\;jne %l1"; |
0dbd1c74 | 6048 | } |
960e6739 | 6049 | if (TARGET_68020 || TARGET_COLDFIRE) |
a1f3c748 | 6050 | return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1"; |
d08c9ad7 | 6051 | else |
a1f3c748 | 6052 | return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1"; |
2de9355b | 6053 | }) |
d08c9ad7 | 6054 | |
6055 | (define_insn "bge0_di" | |
6056 | [(set (pc) | |
6057 | (if_then_else (ge (match_operand:DI 0 "general_operand" "ro") | |
6058 | (const_int 0)) | |
6059 | (label_ref (match_operand 1 "" "")) | |
6060 | (pc)))] | |
6061 | "" | |
d08c9ad7 | 6062 | { |
3f6dfb87 | 6063 | if ((cc_prev_status.value1 |
6064 | && rtx_equal_p (cc_prev_status.value1, operands[0])) | |
6065 | || (cc_prev_status.value2 | |
6066 | && rtx_equal_p (cc_prev_status.value2, operands[0]))) | |
6067 | { | |
6068 | cc_status = cc_prev_status; | |
a1f3c748 | 6069 | return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1"; |
3f6dfb87 | 6070 | } |
6071 | CC_STATUS_INIT; | |
960e6739 | 6072 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) |
2de9355b | 6073 | output_asm_insn("tst%.l %0", operands); |
a421ea47 | 6074 | else |
0dbd1c74 | 6075 | { |
6076 | /* On an address reg, cmpw may replace cmpl. */ | |
3acc77d9 | 6077 | output_asm_insn("cmp%.w #0,%0", operands); |
0dbd1c74 | 6078 | } |
a1f3c748 | 6079 | return "jpl %l1"; |
2de9355b | 6080 | }) |
d08c9ad7 | 6081 | |
6082 | (define_insn "blt0_di" | |
6083 | [(set (pc) | |
6084 | (if_then_else (lt (match_operand:DI 0 "general_operand" "ro") | |
6085 | (const_int 0)) | |
6086 | (label_ref (match_operand 1 "" "")) | |
6087 | (pc)))] | |
6088 | "" | |
d08c9ad7 | 6089 | { |
3f6dfb87 | 6090 | if ((cc_prev_status.value1 |
6091 | && rtx_equal_p (cc_prev_status.value1, operands[0])) | |
6092 | || (cc_prev_status.value2 | |
6093 | && rtx_equal_p (cc_prev_status.value2, operands[0]))) | |
6094 | { | |
6095 | cc_status = cc_prev_status; | |
a1f3c748 | 6096 | return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1"; |
3f6dfb87 | 6097 | } |
6098 | CC_STATUS_INIT; | |
960e6739 | 6099 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) |
2de9355b | 6100 | output_asm_insn("tst%.l %0", operands); |
a421ea47 | 6101 | else |
0dbd1c74 | 6102 | { |
6103 | /* On an address reg, cmpw may replace cmpl. */ | |
3acc77d9 | 6104 | output_asm_insn("cmp%.w #0,%0", operands); |
0dbd1c74 | 6105 | } |
a1f3c748 | 6106 | return "jmi %l1"; |
2de9355b | 6107 | }) |
d08c9ad7 | 6108 | |
c1dbe9ae | 6109 | (define_insn "beq" |
6110 | [(set (pc) | |
6111 | (if_then_else (eq (cc0) | |
6112 | (const_int 0)) | |
6113 | (label_ref (match_operand 0 "" "")) | |
6114 | (pc)))] | |
6115 | "" | |
c1dbe9ae | 6116 | { |
4f747969 | 6117 | OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); |
1d86aeab | 6118 | } |
f4831ba5 | 6119 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6120 | |
6121 | (define_insn "bne" | |
6122 | [(set (pc) | |
6123 | (if_then_else (ne (cc0) | |
6124 | (const_int 0)) | |
6125 | (label_ref (match_operand 0 "" "")) | |
6126 | (pc)))] | |
6127 | "" | |
c1dbe9ae | 6128 | { |
4f747969 | 6129 | OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); |
1d86aeab | 6130 | } |
f4831ba5 | 6131 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6132 | |
6133 | (define_insn "bgt" | |
6134 | [(set (pc) | |
6135 | (if_then_else (gt (cc0) | |
6136 | (const_int 0)) | |
6137 | (label_ref (match_operand 0 "" "")) | |
6138 | (pc)))] | |
6139 | "" | |
2de9355b | 6140 | { |
bf7cf42a | 6141 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6142 | { | |
6143 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6144 | return 0; | |
6145 | } | |
6146 | ||
4f747969 | 6147 | OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0); |
1d86aeab | 6148 | } |
f4831ba5 | 6149 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6150 | |
6151 | (define_insn "bgtu" | |
6152 | [(set (pc) | |
6153 | (if_then_else (gtu (cc0) | |
6154 | (const_int 0)) | |
6155 | (label_ref (match_operand 0 "" "")) | |
6156 | (pc)))] | |
6157 | "" | |
bf7cf42a | 6158 | { |
6159 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6160 | { | |
6161 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6162 | return 0; | |
6163 | } | |
6164 | ||
6165 | return "jhi %l0"; | |
6166 | } | |
1d86aeab | 6167 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6168 | |
6169 | (define_insn "blt" | |
6170 | [(set (pc) | |
6171 | (if_then_else (lt (cc0) | |
6172 | (const_int 0)) | |
6173 | (label_ref (match_operand 0 "" "")) | |
6174 | (pc)))] | |
6175 | "" | |
2de9355b | 6176 | { |
bf7cf42a | 6177 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6178 | { | |
6179 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6180 | return 0; | |
6181 | } | |
6182 | ||
4f747969 | 6183 | OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0"); |
1d86aeab | 6184 | } |
f4831ba5 | 6185 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6186 | |
6187 | (define_insn "bltu" | |
6188 | [(set (pc) | |
6189 | (if_then_else (ltu (cc0) | |
6190 | (const_int 0)) | |
6191 | (label_ref (match_operand 0 "" "")) | |
6192 | (pc)))] | |
6193 | "" | |
bf7cf42a | 6194 | { |
6195 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6196 | { | |
6197 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6198 | return 0; | |
6199 | } | |
6200 | ||
6201 | return "jcs %l0"; | |
6202 | } | |
1d86aeab | 6203 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6204 | |
6205 | (define_insn "bge" | |
6206 | [(set (pc) | |
6207 | (if_then_else (ge (cc0) | |
6208 | (const_int 0)) | |
6209 | (label_ref (match_operand 0 "" "")) | |
6210 | (pc)))] | |
6211 | "" | |
2de9355b | 6212 | { |
bf7cf42a | 6213 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6214 | { | |
6215 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6216 | return 0; | |
6217 | } | |
6218 | ||
4f747969 | 6219 | OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0"); |
2de9355b | 6220 | }) |
c1dbe9ae | 6221 | |
6222 | (define_insn "bgeu" | |
6223 | [(set (pc) | |
6224 | (if_then_else (geu (cc0) | |
6225 | (const_int 0)) | |
6226 | (label_ref (match_operand 0 "" "")) | |
6227 | (pc)))] | |
6228 | "" | |
bf7cf42a | 6229 | { |
6230 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6231 | { | |
6232 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6233 | return 0; | |
6234 | } | |
6235 | ||
6236 | return "jcc %l0"; | |
6237 | } | |
1d86aeab | 6238 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6239 | |
6240 | (define_insn "ble" | |
6241 | [(set (pc) | |
6242 | (if_then_else (le (cc0) | |
6243 | (const_int 0)) | |
6244 | (label_ref (match_operand 0 "" "")) | |
6245 | (pc)))] | |
6246 | "" | |
2de9355b | 6247 | { |
bf7cf42a | 6248 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6249 | { | |
6250 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6251 | return 0; | |
6252 | } | |
6253 | ||
4f747969 | 6254 | OUTPUT_JUMP ("jle %l0", "fjle %l0", 0); |
1d86aeab | 6255 | } |
6256 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6257 | |
6258 | (define_insn "bleu" | |
6259 | [(set (pc) | |
6260 | (if_then_else (leu (cc0) | |
6261 | (const_int 0)) | |
6262 | (label_ref (match_operand 0 "" "")) | |
6263 | (pc)))] | |
6264 | "" | |
bf7cf42a | 6265 | { |
6266 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6267 | { | |
6268 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6269 | return 0; | |
6270 | } | |
6271 | ||
6272 | return "jls %l0"; | |
6273 | } | |
1d86aeab | 6274 | [(set_attr "type" "bcc")]) |
e3323f4d | 6275 | |
6276 | (define_insn "bordered" | |
6277 | [(set (pc) | |
6278 | (if_then_else (ordered (cc0) (const_int 0)) | |
6279 | (label_ref (match_operand 0 "" "")) | |
6280 | (pc)))] | |
a77fcdb5 | 6281 | "TARGET_HARD_FLOAT" |
e3323f4d | 6282 | { |
84653e0f | 6283 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6284 | return "fjor %l0"; |
3c904dda | 6285 | } |
6286 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6287 | |
6288 | (define_insn "bunordered" | |
6289 | [(set (pc) | |
6290 | (if_then_else (unordered (cc0) (const_int 0)) | |
6291 | (label_ref (match_operand 0 "" "")) | |
6292 | (pc)))] | |
a77fcdb5 | 6293 | "TARGET_HARD_FLOAT" |
e3323f4d | 6294 | { |
84653e0f | 6295 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6296 | return "fjun %l0"; |
3c904dda | 6297 | } |
6298 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6299 | |
6300 | (define_insn "buneq" | |
6301 | [(set (pc) | |
6302 | (if_then_else (uneq (cc0) (const_int 0)) | |
6303 | (label_ref (match_operand 0 "" "")) | |
6304 | (pc)))] | |
a77fcdb5 | 6305 | "TARGET_HARD_FLOAT" |
e3323f4d | 6306 | { |
84653e0f | 6307 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6308 | return "fjueq %l0"; |
3c904dda | 6309 | } |
6310 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6311 | |
6312 | (define_insn "bunge" | |
6313 | [(set (pc) | |
6314 | (if_then_else (unge (cc0) (const_int 0)) | |
6315 | (label_ref (match_operand 0 "" "")) | |
6316 | (pc)))] | |
a77fcdb5 | 6317 | "TARGET_HARD_FLOAT" |
e3323f4d | 6318 | { |
84653e0f | 6319 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6320 | return "fjuge %l0"; |
3c904dda | 6321 | } |
6322 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6323 | |
6324 | (define_insn "bungt" | |
6325 | [(set (pc) | |
6326 | (if_then_else (ungt (cc0) (const_int 0)) | |
6327 | (label_ref (match_operand 0 "" "")) | |
6328 | (pc)))] | |
a77fcdb5 | 6329 | "TARGET_HARD_FLOAT" |
e3323f4d | 6330 | { |
84653e0f | 6331 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6332 | return "fjugt %l0"; |
3c904dda | 6333 | } |
6334 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6335 | |
6336 | (define_insn "bunle" | |
6337 | [(set (pc) | |
6338 | (if_then_else (unle (cc0) (const_int 0)) | |
6339 | (label_ref (match_operand 0 "" "")) | |
6340 | (pc)))] | |
a77fcdb5 | 6341 | "TARGET_HARD_FLOAT" |
e3323f4d | 6342 | { |
84653e0f | 6343 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6344 | return "fjule %l0"; |
3c904dda | 6345 | } |
6346 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6347 | |
6348 | (define_insn "bunlt" | |
6349 | [(set (pc) | |
6350 | (if_then_else (unlt (cc0) (const_int 0)) | |
6351 | (label_ref (match_operand 0 "" "")) | |
6352 | (pc)))] | |
a77fcdb5 | 6353 | "TARGET_HARD_FLOAT" |
e3323f4d | 6354 | { |
84653e0f | 6355 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6356 | return "fjult %l0"; |
3c904dda | 6357 | } |
6358 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6359 | |
6360 | (define_insn "bltgt" | |
6361 | [(set (pc) | |
6362 | (if_then_else (ltgt (cc0) (const_int 0)) | |
6363 | (label_ref (match_operand 0 "" "")) | |
6364 | (pc)))] | |
a77fcdb5 | 6365 | "TARGET_HARD_FLOAT" |
e3323f4d | 6366 | { |
84653e0f | 6367 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6368 | return "fjogl %l0"; |
3c904dda | 6369 | } |
6370 | [(set_attr "type" "fbcc")]) | |
c1dbe9ae | 6371 | \f |
6372 | ;; Negated conditional jump instructions. | |
6373 | ||
4f747969 | 6374 | (define_insn "*beq_rev" |
c1dbe9ae | 6375 | [(set (pc) |
6376 | (if_then_else (eq (cc0) | |
6377 | (const_int 0)) | |
6378 | (pc) | |
6379 | (label_ref (match_operand 0 "" ""))))] | |
6380 | "" | |
c1dbe9ae | 6381 | { |
4f747969 | 6382 | OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); |
1d86aeab | 6383 | } |
6384 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6385 | |
4f747969 | 6386 | (define_insn "*bne_rev" |
c1dbe9ae | 6387 | [(set (pc) |
6388 | (if_then_else (ne (cc0) | |
6389 | (const_int 0)) | |
6390 | (pc) | |
6391 | (label_ref (match_operand 0 "" ""))))] | |
6392 | "" | |
c1dbe9ae | 6393 | { |
4f747969 | 6394 | OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); |
1d86aeab | 6395 | } |
6396 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6397 | |
4f747969 | 6398 | (define_insn "*bgt_rev" |
c1dbe9ae | 6399 | [(set (pc) |
6400 | (if_then_else (gt (cc0) | |
6401 | (const_int 0)) | |
6402 | (pc) | |
6403 | (label_ref (match_operand 0 "" ""))))] | |
6404 | "" | |
2de9355b | 6405 | { |
bf7cf42a | 6406 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6407 | { | |
6408 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6409 | return 0; | |
6410 | } | |
6411 | ||
4f747969 | 6412 | OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0); |
1d86aeab | 6413 | } |
6414 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6415 | |
a1f3c748 | 6416 | (define_insn "*bgtu_rev" |
c1dbe9ae | 6417 | [(set (pc) |
6418 | (if_then_else (gtu (cc0) | |
6419 | (const_int 0)) | |
6420 | (pc) | |
6421 | (label_ref (match_operand 0 "" ""))))] | |
6422 | "" | |
bf7cf42a | 6423 | { |
6424 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6425 | { | |
6426 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6427 | return 0; | |
6428 | } | |
6429 | ||
6430 | return "jls %l0"; | |
6431 | } | |
1d86aeab | 6432 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6433 | |
4f747969 | 6434 | (define_insn "*blt_rev" |
c1dbe9ae | 6435 | [(set (pc) |
6436 | (if_then_else (lt (cc0) | |
6437 | (const_int 0)) | |
6438 | (pc) | |
6439 | (label_ref (match_operand 0 "" ""))))] | |
6440 | "" | |
2de9355b | 6441 | { |
bf7cf42a | 6442 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6443 | { | |
6444 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6445 | return 0; | |
6446 | } | |
6447 | ||
4f747969 | 6448 | OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0"); |
1d86aeab | 6449 | } |
6450 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6451 | |
a1f3c748 | 6452 | (define_insn "*bltu_rev" |
c1dbe9ae | 6453 | [(set (pc) |
6454 | (if_then_else (ltu (cc0) | |
6455 | (const_int 0)) | |
6456 | (pc) | |
6457 | (label_ref (match_operand 0 "" ""))))] | |
6458 | "" | |
bf7cf42a | 6459 | { |
6460 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6461 | { | |
6462 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6463 | return 0; | |
6464 | } | |
6465 | ||
6466 | return "jcc %l0"; | |
6467 | } | |
1d86aeab | 6468 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6469 | |
4f747969 | 6470 | (define_insn "*bge_rev" |
c1dbe9ae | 6471 | [(set (pc) |
6472 | (if_then_else (ge (cc0) | |
6473 | (const_int 0)) | |
6474 | (pc) | |
6475 | (label_ref (match_operand 0 "" ""))))] | |
6476 | "" | |
2de9355b | 6477 | { |
bf7cf42a | 6478 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6479 | { | |
6480 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6481 | return 0; | |
6482 | } | |
6483 | ||
4f747969 | 6484 | OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0"); |
1d86aeab | 6485 | } |
6486 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6487 | |
a1f3c748 | 6488 | (define_insn "*bgeu_rev" |
c1dbe9ae | 6489 | [(set (pc) |
6490 | (if_then_else (geu (cc0) | |
6491 | (const_int 0)) | |
6492 | (pc) | |
6493 | (label_ref (match_operand 0 "" ""))))] | |
6494 | "" | |
bf7cf42a | 6495 | { |
6496 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6497 | { | |
6498 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6499 | return 0; | |
6500 | } | |
6501 | ||
6502 | return "jcs %l0"; | |
6503 | } | |
1d86aeab | 6504 | [(set_attr "type" "bcc")]) |
c1dbe9ae | 6505 | |
4f747969 | 6506 | (define_insn "*ble_rev" |
c1dbe9ae | 6507 | [(set (pc) |
6508 | (if_then_else (le (cc0) | |
6509 | (const_int 0)) | |
6510 | (pc) | |
6511 | (label_ref (match_operand 0 "" ""))))] | |
6512 | "" | |
2de9355b | 6513 | { |
bf7cf42a | 6514 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) |
6515 | { | |
6516 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6517 | return 0; | |
6518 | } | |
6519 | ||
4f747969 | 6520 | OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0); |
1d86aeab | 6521 | } |
6522 | [(set_attr "type" "bcc")]) | |
c1dbe9ae | 6523 | |
a1f3c748 | 6524 | (define_insn "*bleu_rev" |
c1dbe9ae | 6525 | [(set (pc) |
6526 | (if_then_else (leu (cc0) | |
6527 | (const_int 0)) | |
6528 | (pc) | |
6529 | (label_ref (match_operand 0 "" ""))))] | |
6530 | "" | |
bf7cf42a | 6531 | { |
6532 | if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) | |
6533 | { | |
6534 | cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; | |
6535 | return 0; | |
6536 | } | |
6537 | ||
6538 | return "jhi %l0"; | |
6539 | } | |
1d86aeab | 6540 | [(set_attr "type" "bcc")]) |
e3323f4d | 6541 | |
6542 | (define_insn "*bordered_rev" | |
6543 | [(set (pc) | |
6544 | (if_then_else (ordered (cc0) (const_int 0)) | |
6545 | (pc) | |
6546 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6547 | "TARGET_HARD_FLOAT" |
e3323f4d | 6548 | { |
84653e0f | 6549 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6550 | return "fjun %l0"; |
3c904dda | 6551 | } |
6552 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6553 | |
6554 | (define_insn "*bunordered_rev" | |
6555 | [(set (pc) | |
6556 | (if_then_else (unordered (cc0) (const_int 0)) | |
6557 | (pc) | |
6558 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6559 | "TARGET_HARD_FLOAT" |
e3323f4d | 6560 | { |
84653e0f | 6561 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6562 | return "fjor %l0"; |
3c904dda | 6563 | } |
6564 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6565 | |
6566 | (define_insn "*buneq_rev" | |
6567 | [(set (pc) | |
6568 | (if_then_else (uneq (cc0) (const_int 0)) | |
6569 | (pc) | |
6570 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6571 | "TARGET_HARD_FLOAT" |
e3323f4d | 6572 | { |
84653e0f | 6573 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6574 | return "fjogl %l0"; |
3c904dda | 6575 | } |
6576 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6577 | |
6578 | (define_insn "*bunge_rev" | |
6579 | [(set (pc) | |
6580 | (if_then_else (unge (cc0) (const_int 0)) | |
6581 | (pc) | |
6582 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6583 | "TARGET_HARD_FLOAT" |
e3323f4d | 6584 | { |
84653e0f | 6585 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6586 | return "fjolt %l0"; |
3c904dda | 6587 | } |
6588 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6589 | |
71a703eb | 6590 | (define_insn "*bungt_rev" |
6591 | [(set (pc) | |
6592 | (if_then_else (ungt (cc0) (const_int 0)) | |
6593 | (pc) | |
6594 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6595 | "TARGET_HARD_FLOAT" |
71a703eb | 6596 | { |
6597 | gcc_assert (cc_prev_status.flags & CC_IN_68881); | |
4f747969 | 6598 | return "fjole %l0"; |
3c904dda | 6599 | } |
6600 | [(set_attr "type" "fbcc")]) | |
71a703eb | 6601 | |
e3323f4d | 6602 | (define_insn "*bunle_rev" |
6603 | [(set (pc) | |
6604 | (if_then_else (unle (cc0) (const_int 0)) | |
6605 | (pc) | |
6606 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6607 | "TARGET_HARD_FLOAT" |
e3323f4d | 6608 | { |
84653e0f | 6609 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6610 | return "fjogt %l0"; |
3c904dda | 6611 | } |
6612 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6613 | |
6614 | (define_insn "*bunlt_rev" | |
6615 | [(set (pc) | |
6616 | (if_then_else (unlt (cc0) (const_int 0)) | |
6617 | (pc) | |
6618 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6619 | "TARGET_HARD_FLOAT" |
e3323f4d | 6620 | { |
84653e0f | 6621 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6622 | return "fjoge %l0"; |
3c904dda | 6623 | } |
6624 | [(set_attr "type" "fbcc")]) | |
e3323f4d | 6625 | |
6626 | (define_insn "*bltgt_rev" | |
6627 | [(set (pc) | |
6628 | (if_then_else (ltgt (cc0) (const_int 0)) | |
6629 | (pc) | |
6630 | (label_ref (match_operand 0 "" ""))))] | |
a77fcdb5 | 6631 | "TARGET_HARD_FLOAT" |
e3323f4d | 6632 | { |
84653e0f | 6633 | gcc_assert (cc_prev_status.flags & CC_IN_68881); |
4f747969 | 6634 | return "fjueq %l0"; |
3c904dda | 6635 | } |
6636 | [(set_attr "type" "fbcc")]) | |
c1dbe9ae | 6637 | \f |
6638 | ;; Unconditional and other jump instructions | |
6639 | (define_insn "jump" | |
6640 | [(set (pc) | |
6641 | (label_ref (match_operand 0 "" "")))] | |
6642 | "" | |
a1f3c748 | 6643 | "jra %l0" |
1d86aeab | 6644 | [(set_attr "type" "bra")]) |
c1dbe9ae | 6645 | |
c1dbe9ae | 6646 | (define_expand "tablejump" |
6647 | [(parallel [(set (pc) (match_operand 0 "" "")) | |
6648 | (use (label_ref (match_operand 1 "" "")))])] | |
6649 | "" | |
c1dbe9ae | 6650 | { |
bcab8a3c | 6651 | #if CASE_VECTOR_PC_RELATIVE |
e6b2f841 | 6652 | operands[0] = gen_rtx_PLUS (SImode, pc_rtx, |
6653 | gen_rtx_SIGN_EXTEND (SImode, operands[0])); | |
c1dbe9ae | 6654 | #endif |
f5f2db69 | 6655 | }) |
c1dbe9ae | 6656 | |
6657 | ;; Jump to variable address from dispatch table of absolute addresses. | |
1d86aeab | 6658 | (define_insn "*tablejump_internal" |
c1dbe9ae | 6659 | [(set (pc) (match_operand:SI 0 "register_operand" "a")) |
6660 | (use (label_ref (match_operand 1 "" "")))] | |
6661 | "" | |
4ad53767 | 6662 | { |
6663 | return MOTOROLA ? "jmp (%0)" : "jmp %0@"; | |
6664 | } | |
3c904dda | 6665 | [(set_attr "type" "jmp")]) |
c1dbe9ae | 6666 | |
6667 | ;; Jump to variable address from dispatch table of relative addresses. | |
6668 | (define_insn "" | |
6669 | [(set (pc) | |
8a7375fb | 6670 | (plus:SI (pc) |
6671 | (sign_extend:SI (match_operand:HI 0 "register_operand" "r")))) | |
c1dbe9ae | 6672 | (use (label_ref (match_operand 1 "" "")))] |
6673 | "" | |
2de9355b | 6674 | { |
c1dbe9ae | 6675 | #ifdef ASM_RETURN_CASE_JUMP |
2de9355b | 6676 | ASM_RETURN_CASE_JUMP; |
c1dbe9ae | 6677 | #else |
960e6739 | 6678 | if (TARGET_COLDFIRE) |
33bfcc44 | 6679 | { |
251538ce | 6680 | if (ADDRESS_REG_P (operands[0])) |
4ad53767 | 6681 | return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)"; |
6682 | else if (MOTOROLA) | |
6683 | return "ext%.l %0\;jmp (2,pc,%0.l)"; | |
251538ce | 6684 | else |
4ad53767 | 6685 | return "extl %0\;jmp pc@(2,%0:l)"; |
33bfcc44 | 6686 | } |
6687 | else | |
4ad53767 | 6688 | return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)"; |
c1dbe9ae | 6689 | #endif |
2de9355b | 6690 | }) |
c1dbe9ae | 6691 | |
6692 | ;; Decrement-and-branch insns. | |
a1f3c748 | 6693 | (define_insn "*dbne_hi" |
c1dbe9ae | 6694 | [(set (pc) |
6695 | (if_then_else | |
c4af10f0 | 6696 | (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g") |
c1dbe9ae | 6697 | (const_int 0)) |
6698 | (label_ref (match_operand 1 "" "")) | |
6699 | (pc))) | |
6700 | (set (match_dup 0) | |
6701 | (plus:HI (match_dup 0) | |
6702 | (const_int -1)))] | |
960e6739 | 6703 | "!TARGET_COLDFIRE" |
c1dbe9ae | 6704 | { |
6705 | CC_STATUS_INIT; | |
6706 | if (DATA_REG_P (operands[0])) | |
2de9355b | 6707 | return "dbra %0,%l1"; |
c1dbe9ae | 6708 | if (GET_CODE (operands[0]) == MEM) |
a1f3c748 | 6709 | return "subq%.w #1,%0\;jcc %l1"; |
6710 | return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1"; | |
2de9355b | 6711 | }) |
c1dbe9ae | 6712 | |
a1f3c748 | 6713 | (define_insn "*dbne_si" |
c1dbe9ae | 6714 | [(set (pc) |
6715 | (if_then_else | |
c4af10f0 | 6716 | (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g") |
c1dbe9ae | 6717 | (const_int 0)) |
6718 | (label_ref (match_operand 1 "" "")) | |
6719 | (pc))) | |
6720 | (set (match_dup 0) | |
6721 | (plus:SI (match_dup 0) | |
6722 | (const_int -1)))] | |
960e6739 | 6723 | "!TARGET_COLDFIRE" |
c1dbe9ae | 6724 | { |
6725 | CC_STATUS_INIT; | |
3acc77d9 | 6726 | if (DATA_REG_P (operands[0])) |
a1f3c748 | 6727 | return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1"; |
3acc77d9 | 6728 | if (GET_CODE (operands[0]) == MEM) |
a1f3c748 | 6729 | return "subq%.l #1,%0\;jcc %l1"; |
6730 | return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1"; | |
2de9355b | 6731 | }) |
c1dbe9ae | 6732 | |
bdf74c8a | 6733 | ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce. |
6734 | ||
a1f3c748 | 6735 | (define_insn "*dbge_hi" |
bdf74c8a | 6736 | [(set (pc) |
6737 | (if_then_else | |
c4af10f0 | 6738 | (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am") |
bdf74c8a | 6739 | (const_int -1)) |
6740 | (const_int 0)) | |
6741 | (label_ref (match_operand 1 "" "")) | |
6742 | (pc))) | |
6743 | (set (match_dup 0) | |
6744 | (plus:HI (match_dup 0) | |
6745 | (const_int -1)))] | |
960e6739 | 6746 | "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" |
bdf74c8a | 6747 | { |
6748 | CC_STATUS_INIT; | |
3acc77d9 | 6749 | if (DATA_REG_P (operands[0])) |
6750 | return "dbra %0,%l1"; | |
6751 | if (GET_CODE (operands[0]) == MEM) | |
a1f3c748 | 6752 | return "subq%.w #1,%0\;jcc %l1"; |
6753 | return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1"; | |
2de9355b | 6754 | }) |
c1dbe9ae | 6755 | |
e193ff3d | 6756 | (define_expand "decrement_and_branch_until_zero" |
6757 | [(parallel [(set (pc) | |
6758 | (if_then_else | |
c4af10f0 | 6759 | (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "") |
e193ff3d | 6760 | (const_int -1)) |
6761 | (const_int 0)) | |
6762 | (label_ref (match_operand 1 "" "")) | |
6763 | (pc))) | |
6764 | (set (match_dup 0) | |
6765 | (plus:SI (match_dup 0) | |
6766 | (const_int -1)))])] | |
6767 | "" | |
6768 | "") | |
6769 | ||
a1f3c748 | 6770 | (define_insn "*dbge_si" |
c1dbe9ae | 6771 | [(set (pc) |
6772 | (if_then_else | |
c4af10f0 | 6773 | (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am") |
bdf74c8a | 6774 | (const_int -1)) |
c1dbe9ae | 6775 | (const_int 0)) |
6776 | (label_ref (match_operand 1 "" "")) | |
6777 | (pc))) | |
6778 | (set (match_dup 0) | |
6779 | (plus:SI (match_dup 0) | |
6780 | (const_int -1)))] | |
960e6739 | 6781 | "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" |
c1dbe9ae | 6782 | { |
6783 | CC_STATUS_INIT; | |
3acc77d9 | 6784 | if (DATA_REG_P (operands[0])) |
a1f3c748 | 6785 | return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1"; |
3acc77d9 | 6786 | if (GET_CODE (operands[0]) == MEM) |
a1f3c748 | 6787 | return "subq%.l #1,%0\;jcc %l1"; |
6788 | return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1"; | |
2de9355b | 6789 | }) |
c1dbe9ae | 6790 | |
33fb08b8 | 6791 | (define_expand "sibcall" |
6792 | [(call (match_operand:QI 0 "memory_operand" "") | |
6793 | (match_operand:SI 1 "general_operand" ""))] | |
6794 | "" | |
6795 | { | |
6796 | operands[0] = m68k_legitimize_sibcall_address (operands[0]); | |
6797 | }) | |
6798 | ||
6799 | (define_insn "*sibcall" | |
6800 | [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "")) | |
6801 | (match_operand:SI 1 "general_operand" ""))] | |
6802 | "SIBLING_CALL_P (insn)" | |
6803 | { | |
6804 | return output_sibcall (operands[0]); | |
6805 | }) | |
6806 | ||
6807 | (define_expand "sibcall_value" | |
6808 | [(set (match_operand 0 "" "") | |
6809 | (call (match_operand:QI 1 "memory_operand" "") | |
6810 | (match_operand:SI 2 "general_operand" "")))] | |
6811 | "" | |
6812 | { | |
6813 | operands[1] = m68k_legitimize_sibcall_address (operands[1]); | |
6814 | }) | |
6815 | ||
6816 | (define_insn "*sibcall_value" | |
6817 | [(set (match_operand 0 "" "=rf,rf") | |
6818 | (call (mem:QI (match_operand:SI 1 "sibcall_operand" "")) | |
6819 | (match_operand:SI 2 "general_operand" "")))] | |
6820 | "SIBLING_CALL_P (insn)" | |
6821 | { | |
6822 | operands[0] = operands[1]; | |
6823 | return output_sibcall (operands[0]); | |
6824 | }) | |
6825 | ||
c1dbe9ae | 6826 | ;; Call subroutine with no return value. |
6827 | (define_expand "call" | |
6828 | [(call (match_operand:QI 0 "memory_operand" "") | |
6829 | (match_operand:SI 1 "general_operand" ""))] | |
6830 | ;; Operand 1 not really used on the m68000. | |
c1dbe9ae | 6831 | "" |
c1dbe9ae | 6832 | { |
dd7218bb | 6833 | operands[0] = m68k_legitimize_call_address (operands[0]); |
f5f2db69 | 6834 | }) |
c1dbe9ae | 6835 | |
dd7218bb | 6836 | (define_insn "*call" |
6837 | [(call (mem:QI (match_operand:SI 0 "call_operand" "a,W")) | |
6838 | (match_operand:SI 1 "general_operand" "g,g"))] | |
c1dbe9ae | 6839 | ;; Operand 1 not really used on the m68000. |
33fb08b8 | 6840 | "!SIBLING_CALL_P (insn)" |
2de9355b | 6841 | { |
dd7218bb | 6842 | return output_call (operands[0]); |
3c904dda | 6843 | } |
6844 | [(set_attr "type" "jsr")]) | |
c1dbe9ae | 6845 | |
6846 | ;; Call subroutine, returning value in operand 0 | |
6847 | ;; (which must be a hard register). | |
c1dbe9ae | 6848 | (define_expand "call_value" |
6849 | [(set (match_operand 0 "" "") | |
6850 | (call (match_operand:QI 1 "memory_operand" "") | |
dd7218bb | 6851 | (match_operand:SI 2 "general_operand" "")))] |
c1dbe9ae | 6852 | ;; Operand 2 not really used on the m68000. |
6853 | "" | |
c1dbe9ae | 6854 | { |
dd7218bb | 6855 | operands[1] = m68k_legitimize_call_address (operands[1]); |
f5f2db69 | 6856 | }) |
c1dbe9ae | 6857 | |
1d86aeab | 6858 | (define_insn "*non_symbolic_call_value" |
dd7218bb | 6859 | [(set (match_operand 0 "" "=rf,rf") |
1d86aeab | 6860 | (call (mem:QI (match_operand:SI 1 "non_symbolic_call_operand" "a,W")) |
dd7218bb | 6861 | (match_operand:SI 2 "general_operand" "g,g")))] |
c1dbe9ae | 6862 | ;; Operand 2 not really used on the m68000. |
33fb08b8 | 6863 | "!SIBLING_CALL_P (insn)" |
1d86aeab | 6864 | "jsr %a1" |
6865 | [(set_attr "type" "jsr") | |
1d86aeab | 6866 | (set_attr "opx" "1")]) |
6867 | ||
6868 | (define_insn "*symbolic_call_value_jsr" | |
6869 | [(set (match_operand 0 "" "=rf,rf") | |
6870 | (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W")) | |
6871 | (match_operand:SI 2 "general_operand" "g,g")))] | |
6872 | ;; Operand 2 not really used on the m68000. | |
6873 | "!SIBLING_CALL_P (insn) && m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_JSR" | |
2de9355b | 6874 | { |
dd7218bb | 6875 | operands[0] = operands[1]; |
1d86aeab | 6876 | return m68k_symbolic_call; |
6877 | } | |
6878 | [(set_attr "type" "jsr") | |
1d86aeab | 6879 | (set_attr "opx" "1")]) |
6880 | ||
6881 | (define_insn "*symbolic_call_value_bsr" | |
6882 | [(set (match_operand 0 "" "=rf,rf") | |
6883 | (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W")) | |
6884 | (match_operand:SI 2 "general_operand" "g,g")))] | |
6885 | ;; Operand 2 not really used on the m68000. | |
6886 | "!SIBLING_CALL_P (insn) | |
6887 | && (m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_C | |
6888 | || m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_P)" | |
6889 | { | |
6890 | operands[0] = operands[1]; | |
6891 | return m68k_symbolic_call; | |
6892 | } | |
6893 | [(set_attr "type" "bsr") | |
1d86aeab | 6894 | (set_attr "opx" "1")]) |
c1dbe9ae | 6895 | |
7283a35a | 6896 | ;; Call subroutine returning any type. |
6897 | ||
6898 | (define_expand "untyped_call" | |
6899 | [(parallel [(call (match_operand 0 "" "") | |
6900 | (const_int 0)) | |
6901 | (match_operand 1 "" "") | |
6902 | (match_operand 2 "" "")])] | |
6903 | "NEEDS_UNTYPED_CALL" | |
7283a35a | 6904 | { |
6905 | int i; | |
6906 | ||
7f265a08 | 6907 | emit_call_insn (gen_call (operands[0], const0_rtx)); |
7283a35a | 6908 | |
6909 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6910 | { | |
6911 | rtx set = XVECEXP (operands[2], 0, i); | |
6912 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6913 | } | |
6914 | ||
6915 | /* The optimizer does not know that the call sets the function value | |
6916 | registers we stored in the result block. We avoid problems by | |
6917 | claiming that all hard registers are used and clobbered at this | |
6918 | point. */ | |
6919 | emit_insn (gen_blockage ()); | |
6920 | ||
6921 | DONE; | |
f5f2db69 | 6922 | }) |
7283a35a | 6923 | |
6924 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6925 | ;; all of memory. This blocks insns from being moved across this point. | |
6926 | ||
6927 | (define_insn "blockage" | |
104e421a | 6928 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
7283a35a | 6929 | "" |
6930 | "") | |
6931 | ||
c1dbe9ae | 6932 | (define_insn "nop" |
6933 | [(const_int 0)] | |
6934 | "" | |
1d86aeab | 6935 | "nop" |
6936 | [(set_attr "type" "nop")]) | |
c1dbe9ae | 6937 | |
9c47decb | 6938 | (define_expand "prologue" |
6939 | [(const_int 0)] | |
6940 | "" | |
6941 | { | |
6942 | m68k_expand_prologue (); | |
6943 | DONE; | |
6944 | }) | |
6945 | ||
6946 | (define_expand "epilogue" | |
6947 | [(return)] | |
6948 | "" | |
6949 | { | |
33fb08b8 | 6950 | m68k_expand_epilogue (false); |
6951 | DONE; | |
6952 | }) | |
6953 | ||
6954 | (define_expand "sibcall_epilogue" | |
6955 | [(return)] | |
6956 | "" | |
6957 | { | |
6958 | m68k_expand_epilogue (true); | |
9c47decb | 6959 | DONE; |
6960 | }) | |
6961 | ||
bdf74c8a | 6962 | ;; Used for frameless functions which save no regs and allocate no locals. |
9c47decb | 6963 | (define_expand "return" |
c1dbe9ae | 6964 | [(return)] |
b38bcc54 | 6965 | "m68k_use_return_insn ()" |
9c47decb | 6966 | "") |
6967 | ||
6968 | (define_insn "*return" | |
6969 | [(return)] | |
6970 | "" | |
c1dbe9ae | 6971 | { |
f9a44575 | 6972 | switch (m68k_get_function_kind (current_function_decl)) |
9c47decb | 6973 | { |
f9a44575 | 6974 | case m68k_fk_interrupt_handler: |
6975 | return "rte"; | |
6976 | ||
6977 | case m68k_fk_interrupt_thread: | |
6978 | return "sleep"; | |
6979 | ||
6980 | default: | |
abe32cce | 6981 | if (crtl->args.pops_args) |
f9a44575 | 6982 | { |
abe32cce | 6983 | operands[0] = GEN_INT (crtl->args.pops_args); |
f9a44575 | 6984 | return "rtd %0"; |
6985 | } | |
6986 | else | |
6987 | return "rts"; | |
9c47decb | 6988 | } |
1d86aeab | 6989 | } |
6990 | [(set_attr "type" "rts")]) | |
9c47decb | 6991 | |
6992 | (define_insn "*m68k_store_multiple" | |
6993 | [(match_parallel 0 "" [(match_operand 1 "")])] | |
6994 | "m68k_movem_pattern_p (operands[0], NULL, 0, true)" | |
6995 | { | |
6996 | return m68k_output_movem (operands, operands[0], 0, true); | |
6997 | }) | |
6998 | ||
6999 | (define_insn "*m68k_store_multiple_automod" | |
7000 | [(match_parallel 0 "" | |
7001 | [(set (match_operand:SI 1 "register_operand" "=a") | |
7002 | (plus:SI (match_operand:SI 2 "register_operand" "1") | |
7003 | (match_operand:SI 3 "const_int_operand")))])] | |
7004 | "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)" | |
7005 | { | |
7006 | return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true); | |
7007 | }) | |
7008 | ||
7009 | (define_insn "*m68k_load_multiple" | |
7010 | [(match_parallel 0 "" [(match_operand 1 "")])] | |
7011 | "m68k_movem_pattern_p (operands[0], NULL, 0, false)" | |
7012 | { | |
7013 | return m68k_output_movem (operands, operands[0], 0, false); | |
7014 | }) | |
7015 | ||
7016 | (define_insn "*m68k_load_multiple_automod" | |
7017 | [(match_parallel 0 "" | |
7018 | [(set (match_operand:SI 1 "register_operand" "=a") | |
7019 | (plus:SI (match_operand:SI 2 "register_operand" "1") | |
7020 | (match_operand:SI 3 "const_int_operand")))])] | |
7021 | "m68k_movem_pattern_p (operands[0], operands[1], | |
7022 | INTVAL (operands[3]), false)" | |
7023 | { | |
7024 | return m68k_output_movem (operands, operands[0], | |
7025 | INTVAL (operands[3]), false); | |
7026 | }) | |
7027 | ||
7028 | (define_expand "link" | |
7029 | [(parallel | |
7030 | [(set (match_operand:SI 0 "register_operand") | |
7031 | (plus:SI (reg:SI SP_REG) (const_int -4))) | |
7032 | (set (match_dup 2) | |
7033 | (match_dup 0)) | |
7034 | (set (reg:SI SP_REG) | |
7035 | (plus:SI (reg:SI SP_REG) | |
7036 | (match_operand:SI 1 "const_int_operand")))])] | |
7037 | "TARGET_68020 || INTVAL (operands[1]) >= -0x8004" | |
7038 | { | |
29c05e22 | 7039 | operands[2] = gen_frame_mem (SImode, |
7040 | plus_constant (Pmode, stack_pointer_rtx, -4)); | |
9c47decb | 7041 | }) |
7042 | ||
7043 | (define_insn "*link" | |
7044 | [(set (match_operand:SI 0 "register_operand" "+r") | |
7045 | (plus:SI (reg:SI SP_REG) (const_int -4))) | |
7046 | (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) | |
7047 | (match_dup 0)) | |
7048 | (set (reg:SI SP_REG) | |
7049 | (plus:SI (reg:SI SP_REG) | |
7050 | (match_operand:SI 1 "const_int_operand")))] | |
7051 | "TARGET_68020 || INTVAL (operands[1]) >= -0x8004" | |
7052 | { | |
7053 | operands[1] = GEN_INT (INTVAL (operands[1]) + 4); | |
4ad53767 | 7054 | if (!MOTOROLA) |
7055 | return "link %0,%1"; | |
7056 | else if (INTVAL (operands[1]) >= -0x8000) | |
7057 | return "link.w %0,%1"; | |
9c47decb | 7058 | else |
4ad53767 | 7059 | return "link.l %0,%1"; |
3c904dda | 7060 | } |
7061 | [(set_attr "type" "link")]) | |
9c47decb | 7062 | |
7063 | (define_expand "unlink" | |
7064 | [(parallel | |
7065 | [(set (match_operand:SI 0 "register_operand") | |
7066 | (match_dup 1)) | |
7067 | (set (reg:SI SP_REG) | |
7068 | (plus:SI (match_dup 0) | |
7069 | (const_int 4)))])] | |
7070 | "" | |
7071 | { | |
7072 | operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0])); | |
7073 | }) | |
7074 | ||
7075 | (define_insn "*unlink" | |
7076 | [(set (match_operand:SI 0 "register_operand" "+r") | |
7077 | (mem:SI (match_dup 0))) | |
7078 | (set (reg:SI SP_REG) | |
7079 | (plus:SI (match_dup 0) | |
7080 | (const_int 4)))] | |
7081 | "" | |
1d86aeab | 7082 | "unlk %0" |
7083 | [(set_attr "type" "unlk")]) | |
9c47decb | 7084 | |
7085 | (define_insn "load_got" | |
7086 | [(set (match_operand:SI 0 "register_operand" "=a") | |
7087 | (unspec:SI [(const_int 0)] UNSPEC_GOT))] | |
7088 | "" | |
7089 | { | |
7090 | if (TARGET_ID_SHARED_LIBRARY) | |
7091 | { | |
7092 | operands[1] = gen_rtx_REG (Pmode, PIC_REG); | |
4ad53767 | 7093 | return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0"; |
9c47decb | 7094 | } |
7095 | else if (MOTOROLA) | |
7096 | { | |
7097 | if (TARGET_COLDFIRE) | |
7098 | /* Load the full 32-bit PC-relative offset of | |
7099 | _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to | |
7100 | calculate the absolute value. The offset and "lea" | |
7101 | operation word together occupy 6 bytes. */ | |
7102 | return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t" | |
7103 | "lea (-6, %%pc, %0), %0"); | |
7104 | else | |
7105 | return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0"; | |
7106 | } | |
7107 | else | |
7108 | return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t" | |
7109 | "lea %%pc@(0,%0:l),%0"); | |
2de9355b | 7110 | }) |
c1dbe9ae | 7111 | |
7112 | (define_insn "indirect_jump" | |
9be9825b | 7113 | [(set (pc) (match_operand:SI 0 "address_operand" "p"))] |
c1dbe9ae | 7114 | "" |
1d86aeab | 7115 | "jmp %a0" |
7116 | [(set_attr "type" "jmp")]) | |
c1dbe9ae | 7117 | \f |
7118 | ;; This should not be used unless the add/sub insns can't be. | |
7119 | ||
4bea814f | 7120 | (define_insn "*lea" |
c4af10f0 | 7121 | [(set (match_operand:SI 0 "nonimmediate_operand" "=a") |
c1dbe9ae | 7122 | (match_operand:QI 1 "address_operand" "p"))] |
7123 | "" | |
4bea814f | 7124 | "lea %a1,%0") |
c1dbe9ae | 7125 | \f |
7126 | ;; This is the first machine-dependent peephole optimization. | |
7127 | ;; It is useful when a floating value is returned from a function call | |
7128 | ;; and then is moved into an FP register. | |
7129 | ;; But it is mainly intended to test the support for these optimizations. | |
7130 | ||
e64adf14 | 7131 | (define_peephole2 |
f5f2db69 | 7132 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) |
e64adf14 | 7133 | (set (match_operand:DF 0 "register_operand" "") |
7134 | (match_operand:DF 1 "register_operand" ""))] | |
7135 | "FP_REG_P (operands[0]) && !FP_REG_P (operands[1])" | |
7136 | [(set (mem:SI (reg:SI SP_REG)) (match_dup 1)) | |
7137 | (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 2)) | |
7138 | (set (match_dup 0) (mem:DF (post_inc:SI (reg:SI SP_REG))))] | |
7139 | "split_di(operands + 1, 1, operands + 1, operands + 2);") | |
c1dbe9ae | 7140 | |
7141 | ;; Optimize a stack-adjust followed by a push of an argument. | |
7142 | ;; This is said to happen frequently with -msoft-float | |
7143 | ;; when there are consecutive library calls. | |
7144 | ||
e64adf14 | 7145 | (define_peephole2 |
7146 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) | |
7147 | (set (match_operand:SF 0 "push_operand" "") | |
7148 | (match_operand:SF 1 "general_operand" ""))] | |
7149 | "!reg_mentioned_p (stack_pointer_rtx, operands[0])" | |
7150 | [(set (match_dup 0) (match_dup 1))] | |
7151 | "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);") | |
7152 | ||
7153 | (define_peephole2 | |
f5f2db69 | 7154 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) |
e64adf14 | 7155 | (match_operand:SI 0 "const_int_operand" ""))) |
7156 | (set (match_operand:SF 1 "push_operand" "") | |
7157 | (match_operand:SF 2 "general_operand" ""))] | |
7158 | "INTVAL (operands[0]) > 4 | |
7159 | && !reg_mentioned_p (stack_pointer_rtx, operands[2])" | |
7160 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0))) | |
7161 | (set (match_dup 1) (match_dup 2))] | |
c1dbe9ae | 7162 | { |
e64adf14 | 7163 | operands[0] = GEN_INT (INTVAL (operands[0]) - 4); |
7164 | operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx); | |
2de9355b | 7165 | }) |
c1dbe9ae | 7166 | |
7167 | ;; Speed up stack adjust followed by a fullword fixedpoint push. | |
e64adf14 | 7168 | ;; Constant operands need special care, as replacing a "pea X.w" with |
7169 | ;; "move.l #X,(%sp)" is often not a win. | |
c1dbe9ae | 7170 | |
e64adf14 | 7171 | ;; Already done by the previous csa pass, left as reference. |
7172 | (define_peephole2 | |
7173 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) | |
7174 | (set (match_operand:SI 0 "push_operand" "") | |
7175 | (match_operand:SI 1 "general_operand" ""))] | |
7176 | "!reg_mentioned_p (stack_pointer_rtx, operands[1])" | |
7177 | [(set (match_dup 0) (match_dup 1))] | |
7178 | "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);") | |
7179 | ||
7180 | ;; Try to use moveq, after stack push has been changed into a simple move. | |
7181 | (define_peephole2 | |
7182 | [(match_scratch:SI 2 "d") | |
7183 | (set (match_operand:SI 0 "memory_operand" "") | |
7184 | (match_operand:SI 1 "const_int_operand" ""))] | |
7185 | "GET_CODE (XEXP (operands[0], 0)) != PRE_DEC | |
7186 | && INTVAL (operands[1]) != 0 | |
7187 | && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f) | |
7188 | && !valid_mov3q_const (INTVAL (operands[1]))" | |
7189 | [(set (match_dup 2) (match_dup 1)) | |
7190 | (set (match_dup 0) (match_dup 2))]) | |
7191 | ||
7192 | ;; This sequence adds an instruction, but is two bytes shorter. | |
7193 | (define_peephole2 | |
7194 | [(match_scratch:SI 2 "d") | |
7195 | (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 12))) | |
7196 | (set (match_operand:SI 0 "push_operand" "") | |
7197 | (match_operand:SI 1 "const_int_operand" ""))] | |
7198 | "INTVAL (operands[1]) != 0 | |
7199 | && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f) | |
7200 | && !valid_mov3q_const (INTVAL (operands[1]))" | |
7201 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8))) | |
7202 | (set (match_dup 2) (match_dup 1)) | |
7203 | (set (match_dup 0) (match_dup 2))] | |
7204 | "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);") | |
7205 | ||
7206 | ;; Changing pea X.w into a move.l is no real win here. | |
7207 | (define_peephole2 | |
f5f2db69 | 7208 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) |
e64adf14 | 7209 | (match_operand:SI 0 "const_int_operand" ""))) |
7210 | (set (match_operand:SI 1 "push_operand" "") | |
7211 | (match_operand:SI 2 "general_operand" ""))] | |
7212 | "INTVAL (operands[0]) > 4 | |
7213 | && !reg_mentioned_p (stack_pointer_rtx, operands[2]) | |
7214 | && !(CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0 | |
7215 | && IN_RANGE (INTVAL (operands[2]), -0x8000, 0x7fff) | |
7216 | && !valid_mov3q_const (INTVAL (operands[2])))" | |
7217 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0))) | |
7218 | (set (match_dup 1) (match_dup 2))] | |
7219 | { | |
7220 | operands[0] = GEN_INT (INTVAL (operands[0]) - 4); | |
7221 | operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx); | |
7222 | }) | |
7223 | ||
7224 | ;; Speed up pushing a single byte/two bytes but leaving four bytes of space | |
7225 | ;; (which differs slightly between m680x0 and ColdFire). | |
7226 | ||
7227 | (define_peephole2 | |
7228 | [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) | |
7229 | (set (match_operand:QI 0 "memory_operand" "") | |
7230 | (match_operand:QI 1 "register_operand" ""))] | |
7231 | "!reg_mentioned_p (stack_pointer_rtx, operands[1]) | |
7232 | && GET_CODE (XEXP (operands[0], 0)) == PLUS | |
7233 | && rtx_equal_p (XEXP (XEXP (operands[0], 0), 0), stack_pointer_rtx) | |
7234 | && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)) | |
7235 | && INTVAL (XEXP (XEXP (operands[0], 0), 1)) == 3" | |
7236 | [(set (match_dup 0) (match_dup 1))] | |
7237 | { | |
7238 | rtx addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); | |
7239 | operands[0] = adjust_automodify_address (operands[0], SImode, addr, -3); | |
7240 | operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0); | |
7241 | }) | |
7242 | ||
7243 | (define_peephole2 | |
7244 | [(set (match_operand:QI 0 "push_operand" "") | |
7245 | (match_operand:QI 1 "register_operand" "")) | |
7246 | (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -3)))] | |
7247 | "!reg_mentioned_p (stack_pointer_rtx, operands[1])" | |
7248 | [(set (match_dup 0) (match_dup 1))] | |
7249 | { | |
7250 | operands[0] = adjust_automodify_address (operands[0], SImode, | |
7251 | XEXP (operands[0], 0), -3); | |
7252 | operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0); | |
7253 | }) | |
7254 | ||
7255 | (define_peephole2 | |
7256 | [(set (match_operand:HI 0 "push_operand" "") | |
7257 | (match_operand:HI 1 "register_operand" "")) | |
7258 | (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))] | |
7259 | "!reg_mentioned_p (stack_pointer_rtx, operands[1])" | |
7260 | [(set (match_dup 0) (match_dup 1))] | |
7261 | { | |
7262 | operands[0] = adjust_automodify_address (operands[0], SImode, | |
7263 | XEXP (operands[0], 0), -2); | |
7264 | operands[1] = simplify_gen_subreg (SImode, operands[1], HImode, 0); | |
7265 | }) | |
7266 | ||
7267 | ;; Optimize a series of strict_low_part assignments | |
7268 | ||
7269 | (define_peephole2 | |
7270 | [(set (match_operand:SI 0 "register_operand" "") | |
7271 | (const_int 0)) | |
7272 | (set (strict_low_part (match_operand:HI 1 "register_operand" "")) | |
7273 | (match_operand:HI 2 "general_operand" ""))] | |
7274 | "REGNO (operands[0]) == REGNO (operands[1]) | |
7275 | && strict_low_part_peephole_ok (HImode, insn, operands[0])" | |
7276 | [(set (strict_low_part (match_dup 1)) (match_dup 2))] | |
7277 | "") | |
bdf74c8a | 7278 | |
e64adf14 | 7279 | (define_peephole2 |
7280 | [(set (match_operand:SI 0 "register_operand" "") | |
74d64a26 | 7281 | (const_int 0)) |
e64adf14 | 7282 | (set (strict_low_part (match_operand:QI 1 "register_operand" "")) |
7283 | (match_operand:QI 2 "general_operand" ""))] | |
7284 | "REGNO (operands[0]) == REGNO (operands[1]) | |
7285 | && strict_low_part_peephole_ok (QImode, insn, operands[0])" | |
7286 | [(set (strict_low_part (match_dup 1)) (match_dup 2))] | |
7287 | "") | |
74d64a26 | 7288 | |
bdf74c8a | 7289 | ;; dbCC peepholes |
7290 | ;; | |
7291 | ;; Turns | |
7292 | ;; loop: | |
7293 | ;; [ ... ] | |
7294 | ;; jCC label ; abnormal loop termination | |
7295 | ;; dbra dN, loop ; normal loop termination | |
7296 | ;; | |
7297 | ;; Into | |
7298 | ;; loop: | |
7299 | ;; [ ... ] | |
7300 | ;; dbCC dN, loop | |
7301 | ;; jCC label | |
7302 | ;; | |
7303 | ;; Which moves the jCC condition outside the inner loop for free. | |
d66298a9 | 7304 | ;; |
1ee5bf27 | 7305 | |
7306 | (define_peephole | |
7307 | [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" | |
7308 | [(cc0) (const_int 0)]) | |
7309 | (label_ref (match_operand 2 "" "")) | |
7310 | (pc))) | |
7311 | (parallel | |
7312 | [(set (pc) | |
7313 | (if_then_else | |
7314 | (ne (match_operand:HI 0 "register_operand" "") | |
7315 | (const_int 0)) | |
7316 | (label_ref (match_operand 1 "" "")) | |
7317 | (pc))) | |
7318 | (set (match_dup 0) | |
7319 | (plus:HI (match_dup 0) | |
7320 | (const_int -1)))])] | |
960e6739 | 7321 | "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" |
1ee5bf27 | 7322 | { |
7323 | CC_STATUS_INIT; | |
7324 | output_dbcc_and_branch (operands); | |
2de9355b | 7325 | return ""; |
7326 | }) | |
1ee5bf27 | 7327 | |
7328 | (define_peephole | |
7329 | [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" | |
7330 | [(cc0) (const_int 0)]) | |
7331 | (label_ref (match_operand 2 "" "")) | |
7332 | (pc))) | |
7333 | (parallel | |
7334 | [(set (pc) | |
7335 | (if_then_else | |
7336 | (ne (match_operand:SI 0 "register_operand" "") | |
7337 | (const_int 0)) | |
7338 | (label_ref (match_operand 1 "" "")) | |
7339 | (pc))) | |
7340 | (set (match_dup 0) | |
7341 | (plus:SI (match_dup 0) | |
7342 | (const_int -1)))])] | |
960e6739 | 7343 | "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" |
1ee5bf27 | 7344 | { |
7345 | CC_STATUS_INIT; | |
7346 | output_dbcc_and_branch (operands); | |
2de9355b | 7347 | return ""; |
7348 | }) | |
1ee5bf27 | 7349 | |
bdf74c8a | 7350 | (define_peephole |
7351 | [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" | |
7352 | [(cc0) (const_int 0)]) | |
7353 | (label_ref (match_operand 2 "" "")) | |
7354 | (pc))) | |
7355 | (parallel | |
7356 | [(set (pc) | |
7357 | (if_then_else | |
1ee5bf27 | 7358 | (ge (plus:HI (match_operand:HI 0 "register_operand" "") |
bdf74c8a | 7359 | (const_int -1)) |
7360 | (const_int 0)) | |
7361 | (label_ref (match_operand 1 "" "")) | |
7362 | (pc))) | |
7363 | (set (match_dup 0) | |
7364 | (plus:HI (match_dup 0) | |
7365 | (const_int -1)))])] | |
960e6739 | 7366 | "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" |
bdf74c8a | 7367 | { |
7368 | CC_STATUS_INIT; | |
7369 | output_dbcc_and_branch (operands); | |
2de9355b | 7370 | return ""; |
7371 | }) | |
bdf74c8a | 7372 | |
7373 | (define_peephole | |
7374 | [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" | |
7375 | [(cc0) (const_int 0)]) | |
7376 | (label_ref (match_operand 2 "" "")) | |
7377 | (pc))) | |
7378 | (parallel | |
7379 | [(set (pc) | |
7380 | (if_then_else | |
1ee5bf27 | 7381 | (ge (plus:SI (match_operand:SI 0 "register_operand" "") |
bdf74c8a | 7382 | (const_int -1)) |
7383 | (const_int 0)) | |
7384 | (label_ref (match_operand 1 "" "")) | |
7385 | (pc))) | |
7386 | (set (match_dup 0) | |
7387 | (plus:SI (match_dup 0) | |
7388 | (const_int -1)))])] | |
960e6739 | 7389 | "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" |
bdf74c8a | 7390 | { |
7391 | CC_STATUS_INIT; | |
7392 | output_dbcc_and_branch (operands); | |
2de9355b | 7393 | return ""; |
7394 | }) | |
bdf74c8a | 7395 | |
c1dbe9ae | 7396 | \f |
03189682 | 7397 | (define_insn "extendsfxf2" |
c4af10f0 | 7398 | [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f") |
be2828ce | 7399 | (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))] |
03189682 | 7400 | "TARGET_68881" |
03189682 | 7401 | { |
7402 | if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) | |
7403 | { | |
7404 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
7405 | { | |
7406 | /* Extending float to double in an fp-reg is a no-op. | |
7407 | NOTICE_UPDATE_CC has already assumed that the | |
7408 | cc will be set. So cancel what it did. */ | |
7409 | cc_status = cc_prev_status; | |
2de9355b | 7410 | return ""; |
03189682 | 7411 | } |
2de9355b | 7412 | return "f%$move%.x %1,%0"; |
03189682 | 7413 | } |
7414 | if (FP_REG_P (operands[0])) | |
be2828ce | 7415 | { |
7416 | if (FP_REG_P (operands[1])) | |
2de9355b | 7417 | return "f%$move%.x %1,%0"; |
be2828ce | 7418 | else if (ADDRESS_REG_P (operands[1])) |
2de9355b | 7419 | return "move%.l %1,%-\;f%$move%.s %+,%0"; |
be2828ce | 7420 | else if (GET_CODE (operands[1]) == CONST_DOUBLE) |
7421 | return output_move_const_single (operands); | |
2de9355b | 7422 | return "f%$move%.s %f1,%0"; |
be2828ce | 7423 | } |
2de9355b | 7424 | return "fmove%.x %f1,%0"; |
7425 | }) | |
03189682 | 7426 | |
7427 | ||
7428 | (define_insn "extenddfxf2" | |
c4af10f0 | 7429 | [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f") |
03189682 | 7430 | (float_extend:XF |
be2828ce | 7431 | (match_operand:DF 1 "general_operand" "f,rmE")))] |
03189682 | 7432 | "TARGET_68881" |
03189682 | 7433 | { |
7434 | if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) | |
7435 | { | |
7436 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
7437 | { | |
7438 | /* Extending float to double in an fp-reg is a no-op. | |
7439 | NOTICE_UPDATE_CC has already assumed that the | |
7440 | cc will be set. So cancel what it did. */ | |
7441 | cc_status = cc_prev_status; | |
2de9355b | 7442 | return ""; |
03189682 | 7443 | } |
2de9355b | 7444 | return "fmove%.x %1,%0"; |
03189682 | 7445 | } |
7446 | if (FP_REG_P (operands[0])) | |
be2828ce | 7447 | { |
7448 | if (REG_P (operands[1])) | |
7449 | { | |
7450 | rtx xoperands[2]; | |
7014838c | 7451 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2de9355b | 7452 | output_asm_insn ("move%.l %1,%-", xoperands); |
7453 | output_asm_insn ("move%.l %1,%-", operands); | |
7454 | return "f%&move%.d %+,%0"; | |
be2828ce | 7455 | } |
7456 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
7457 | return output_move_const_double (operands); | |
2de9355b | 7458 | return "f%&move%.d %f1,%0"; |
be2828ce | 7459 | } |
2de9355b | 7460 | return "fmove%.x %f1,%0"; |
7461 | }) | |
03189682 | 7462 | |
7463 | (define_insn "truncxfdf2" | |
c4af10f0 | 7464 | [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r") |
03189682 | 7465 | (float_truncate:DF |
7466 | (match_operand:XF 1 "general_operand" "f,f")))] | |
7467 | "TARGET_68881" | |
03189682 | 7468 | { |
7469 | if (REG_P (operands[0])) | |
7470 | { | |
2de9355b | 7471 | output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); |
e6b2f841 | 7472 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2de9355b | 7473 | return "move%.l %+,%0"; |
03189682 | 7474 | } |
2de9355b | 7475 | return "fmove%.d %f1,%0"; |
7476 | }) | |
3f6dfb87 | 7477 | |
f1ee72f7 | 7478 | (define_insn "truncxfsf2" |
7479 | [(set (match_operand:SF 0 "nonimmediate_operand" "=dm") | |
7480 | (float_truncate:SF | |
7481 | (match_operand:XF 1 "general_operand" "f")))] | |
7482 | "TARGET_68881" | |
7483 | "fmove%.s %f1,%0") | |
7484 | ||
58c23110 | 7485 | (define_insn "sin<mode>2" |
7486 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
7487 | (unspec:FP | |
7488 | [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))] | |
7f3be425 | 7489 | "TARGET_68881 && flag_unsafe_math_optimizations" |
71e1d078 | 7490 | { |
7491 | if (FP_REG_P (operands[1])) | |
2de9355b | 7492 | return "fsin%.x %1,%0"; |
71e1d078 | 7493 | else |
58c23110 | 7494 | return "fsin%.<FP:prec> %1,%0"; |
2de9355b | 7495 | }) |
71e1d078 | 7496 | |
58c23110 | 7497 | (define_insn "cos<mode>2" |
7498 | [(set (match_operand:FP 0 "nonimmediate_operand" "=f") | |
7499 | (unspec:FP | |
7500 | [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))] | |
7f3be425 | 7501 | "TARGET_68881 && flag_unsafe_math_optimizations" |
71e1d078 | 7502 | { |
7503 | if (FP_REG_P (operands[1])) | |
2de9355b | 7504 | return "fcos%.x %1,%0"; |
71e1d078 | 7505 | else |
58c23110 | 7506 | return "fcos%.<FP:prec> %1,%0"; |
2de9355b | 7507 | }) |
71e1d078 | 7508 | |
1d86aeab | 7509 | ;; Unconditional traps are assumed to have (const_int 1) for the condition. |
8f8ac140 | 7510 | (define_insn "trap" |
1d86aeab | 7511 | [(trap_if (const_int 1) (const_int 7))] |
8f8ac140 | 7512 | "" |
1d86aeab | 7513 | "trap #7" |
7514 | [(set_attr "type" "trap")]) | |
8f8ac140 | 7515 | |
74f4459c | 7516 | (define_expand "ctrapdi4" |
7517 | [(trap_if (match_operator 0 "ordered_comparison_operator" | |
e680c1ac | 7518 | [(cc0) (const_int 0)]) |
74f4459c | 7519 | (match_operand:SI 3 "const1_operand" ""))] |
e680c1ac | 7520 | "TARGET_68020" |
7521 | { | |
74f4459c | 7522 | if (operands[2] == const0_rtx) |
7523 | emit_insn (gen_tstdi (operands[1])); | |
7524 | else | |
7525 | emit_insn (gen_cmpdi (operands[1], operands[2])); | |
7526 | operands[1] = cc0_rtx; | |
7527 | operands[2] = const0_rtx; | |
e680c1ac | 7528 | }) |
7529 | ||
74f4459c | 7530 | (define_expand "ctrapsi4" |
7531 | [(set (cc0) | |
7532 | (compare (match_operand:SI 1 "nonimmediate_operand" "") | |
7533 | (match_operand:SI 2 "general_operand" ""))) | |
7534 | (trap_if (match_operator 0 "ordered_comparison_operator" | |
7535 | [(cc0) (const_int 0)]) | |
7536 | (match_operand:SI 3 "const1_operand" ""))] | |
7537 | "TARGET_68020" | |
7538 | "") | |
7539 | ||
7540 | (define_expand "ctraphi4" | |
7541 | [(set (cc0) | |
7542 | (compare (match_operand:HI 1 "nonimmediate_src_operand" "") | |
7543 | (match_operand:HI 2 "general_src_operand" ""))) | |
7544 | (trap_if (match_operator 0 "ordered_comparison_operator" | |
7545 | [(cc0) (const_int 0)]) | |
7546 | (match_operand:SI 3 "const1_operand" ""))] | |
7547 | "TARGET_68020" | |
7548 | "") | |
7549 | ||
7550 | (define_expand "ctrapqi4" | |
7551 | [(set (cc0) | |
7552 | (compare (match_operand:QI 1 "nonimmediate_src_operand" "") | |
7553 | (match_operand:QI 2 "general_src_operand" ""))) | |
7554 | (trap_if (match_operator 0 "ordered_comparison_operator" | |
7555 | [(cc0) (const_int 0)]) | |
7556 | (match_operand:SI 3 "const1_operand" ""))] | |
7557 | "TARGET_68020" | |
7558 | "") | |
7559 | ||
e680c1ac | 7560 | (define_insn "*conditional_trap" |
74f4459c | 7561 | [(trap_if (match_operator 0 "ordered_comparison_operator" |
8f8ac140 | 7562 | [(cc0) (const_int 0)]) |
74f4459c | 7563 | (match_operand:SI 1 "const1_operand" "I"))] |
8f8ac140 | 7564 | "TARGET_68020 && ! flags_in_68881 ()" |
8f8ac140 | 7565 | { |
7566 | switch (GET_CODE (operands[0])) | |
7567 | { | |
2de9355b | 7568 | case EQ: return "trapeq"; |
7569 | case NE: return "trapne"; | |
7570 | case GT: return "trapgt"; | |
7571 | case GTU: return "traphi"; | |
7572 | case LT: return "traplt"; | |
7573 | case LTU: return "trapcs"; | |
7574 | case GE: return "trapge"; | |
7575 | case GEU: return "trapcc"; | |
7576 | case LE: return "traple"; | |
7577 | case LEU: return "trapls"; | |
84653e0f | 7578 | default: gcc_unreachable (); |
8f8ac140 | 7579 | } |
2de9355b | 7580 | }) |
1d86aeab | 7581 | |
3c904dda | 7582 | ;; These are to prevent the scheduler from moving stores to the frame |
7583 | ;; before the stack adjustment. | |
7584 | (define_insn "stack_tie" | |
7585 | [(set (mem:BLK (scratch)) | |
7586 | (unspec:BLK [(match_operand:SI 0 "register_operand" "r") | |
7587 | (match_operand:SI 1 "register_operand" "r")] | |
7588 | UNSPEC_TIE))] | |
7589 | "" | |
7590 | "" | |
7591 | [(set_attr "type" "ignore")]) | |
7592 | ||
1d86aeab | 7593 | ;; Instruction that subscribes one word in ColdFire instruction buffer. |
7594 | ;; This instruction is used within scheduler only and should not appear | |
7595 | ;; in the instruction stream. | |
7596 | (define_insn "ib" | |
7597 | [(unspec [(const_int 0)] UNSPEC_IB)] | |
7598 | "" | |
7599 | "#" | |
7600 | [(set_attr "type" "ib")]) | |
15b9ea10 | 7601 | |
7602 | (include "cf.md") | |
ee2d89e9 | 7603 | (include "sync.md") |
fe09f7a2 | 7604 | |
7605 | ;; Convert | |
7606 | ;; | |
7607 | ;; move.l 4(%a0),%a0 | |
7608 | ;; clr.b (%a0,%a1.l) | |
7609 | ;; | |
7610 | ;; into | |
7611 | ;; | |
7612 | ;; add.l 4(%a0),%a1 | |
7613 | ;; clr.b (%a1) | |
7614 | ;; | |
7615 | ;; The latter is smaller. It is faster on all models except m68060. | |
7616 | ||
7617 | (define_peephole2 | |
7618 | [(set (match_operand:SI 0 "register_operand" "") | |
7619 | (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") | |
7620 | (match_operand:SI 2 "const_int_operand" "")))) | |
7621 | (set (mem:QI (plus:SI (match_operand:SI 3 "register_operand" "") | |
7622 | (match_operand:SI 4 "register_operand" ""))) | |
7623 | (const_int 0))] | |
7624 | "(optimize_size || !TUNE_68060) | |
7625 | && (operands[0] == operands[3] || operands[0] == operands[4]) | |
7626 | && ADDRESS_REG_P (operands[1]) | |
7627 | && ADDRESS_REG_P ((operands[0] == operands[3]) ? operands[4] : operands[3]) | |
7628 | && peep2_reg_dead_p (2, operands[3]) | |
7629 | && peep2_reg_dead_p (2, operands[4])" | |
7630 | [(set (match_dup 5) | |
7631 | (plus:SI (match_dup 5) | |
7632 | (mem:SI (plus:SI (match_dup 1) | |
7633 | (match_dup 2))))) | |
7634 | (set (mem:QI (match_dup 5)) | |
7635 | (const_int 0))] | |
7636 | "operands[5] = (operands[0] == operands[3]) ? operands[4] : operands[3];") |