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7b45b59b | 1 | ;; GCC machine description for m68k synchronization instructions. |
aeee4812 | 2 | ;; Copyright (C) 2011-2023 Free Software Foundation, Inc. |
7b45b59b RH |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | ||
21 | (define_expand "atomic_compare_and_swap<mode>" | |
22 | [(match_operand:QI 0 "register_operand" "") ;; bool success output | |
23 | (match_operand:I 1 "register_operand" "") ;; oldval output | |
24 | (match_operand:I 2 "memory_operand" "") ;; memory | |
25 | (match_operand:I 3 "register_operand" "") ;; expected input | |
26 | (match_operand:I 4 "register_operand" "") ;; newval input | |
27 | (match_operand:SI 5 "const_int_operand" "") ;; is_weak | |
28 | (match_operand:SI 6 "const_int_operand" "") ;; success model | |
29 | (match_operand:SI 7 "const_int_operand" "")] ;; failure model | |
6a2b269b | 30 | "TARGET_CAS" |
7b45b59b RH |
31 | { |
32 | emit_insn (gen_atomic_compare_and_swap<mode>_1 | |
33 | (operands[0], operands[1], operands[2], | |
34 | operands[3], operands[4])); | |
35 | emit_insn (gen_negqi2 (operands[0], operands[0])); | |
36 | DONE; | |
37 | }) | |
38 | ||
39 | (define_insn "atomic_compare_and_swap<mode>_1" | |
40 | [(set (match_operand:I 1 "register_operand" "=d") | |
41 | (unspec_volatile:I | |
42 | [(match_operand:I 2 "memory_operand" "+m") | |
b339cf22 | 43 | (match_operand:I 3 "register_operand" "1") |
7b45b59b RH |
44 | (match_operand:I 4 "register_operand" "d")] |
45 | UNSPECV_CAS_1)) | |
46 | (set (match_dup 2) | |
47 | (unspec_volatile:I | |
48 | [(match_dup 2) (match_dup 3) (match_dup 4)] | |
49 | UNSPECV_CAS_2)) | |
50 | (set (match_operand:QI 0 "register_operand" "=d") | |
51 | (unspec_volatile:QI | |
52 | [(match_dup 2) (match_dup 3) (match_dup 4)] | |
53 | UNSPECV_CAS_2))] | |
6a2b269b | 54 | "TARGET_CAS" |
7b45b59b RH |
55 | ;; Elide the seq if operands[0] is dead. |
56 | "cas<sz> %1,%4,%2\;seq %0") | |
57 | ||
4c1fd084 RH |
58 | (define_expand "atomic_test_and_set" |
59 | [(match_operand:QI 0 "register_operand" "") ;; bool success output | |
60 | (match_operand:QI 1 "memory_operand" "") ;; memory | |
61 | (match_operand:SI 2 "const_int_operand" "")] ;; model | |
22a89c86 | 62 | "ISA_HAS_TAS" |
7b45b59b | 63 | { |
b7313c30 RH |
64 | rtx t = gen_reg_rtx (QImode); |
65 | emit_insn (gen_atomic_test_and_set_1 (t, operands[1])); | |
66 | t = expand_simple_unop (QImode, NEG, t, operands[0], 0); | |
67 | if (t != operands[0]) | |
68 | emit_move_insn (operands[0], t); | |
7b45b59b RH |
69 | DONE; |
70 | }) | |
71 | ||
4c1fd084 | 72 | (define_insn "atomic_test_and_set_1" |
7b45b59b RH |
73 | [(set (match_operand:QI 0 "register_operand" "=d") |
74 | (unspec_volatile:QI | |
75 | [(match_operand:QI 1 "memory_operand" "+m")] | |
76 | UNSPECV_TAS_1)) | |
77 | (set (match_dup 1) | |
78 | (unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))] | |
22a89c86 | 79 | "ISA_HAS_TAS" |
7b45b59b | 80 | "tas %1\;sne %0") |