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Commit | Line | Data |
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8f90be4c | 1 | /* Output routines for Motorola MCore processor |
09a2b93a KH |
2 | Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004 |
3 | Free Software Foundation, Inc. | |
8f90be4c | 4 | |
08903e08 | 5 | This file is part of GCC. |
8f90be4c | 6 | |
08903e08 SB |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 2, or (at your | |
10 | option) any later version. | |
8f90be4c | 11 | |
08903e08 SB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
8f90be4c | 16 | |
08903e08 SB |
17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
8f90be4c | 21 | |
bc27e96c | 22 | #include "config.h" |
4bd048ef | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
4816b8e4 NC |
26 | #include "rtl.h" |
27 | #include "tree.h" | |
28 | #include "tm_p.h" | |
8f90be4c | 29 | #include "assert.h" |
8f90be4c | 30 | #include "mcore.h" |
8f90be4c NC |
31 | #include "regs.h" |
32 | #include "hard-reg-set.h" | |
33 | #include "real.h" | |
34 | #include "insn-config.h" | |
35 | #include "conditions.h" | |
8f90be4c NC |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
39 | #include "obstack.h" | |
40 | #include "expr.h" | |
41 | #include "reload.h" | |
42 | #include "recog.h" | |
43 | #include "function.h" | |
44 | #include "ggc.h" | |
45 | #include "toplev.h" | |
672a6f42 NB |
46 | #include "target.h" |
47 | #include "target-def.h" | |
8f90be4c | 48 | |
8f90be4c NC |
49 | /* Maximum size we are allowed to grow the stack in a single operation. |
50 | If we want more, we must do it in increments of at most this size. | |
51 | If this value is 0, we don't check at all. */ | |
52 | const char * mcore_stack_increment_string = 0; | |
53 | int mcore_stack_increment = STACK_UNITS_MAXSTEP; | |
54 | ||
55 | /* For dumping information about frame sizes. */ | |
56 | char * mcore_current_function_name = 0; | |
57 | long mcore_current_compilation_timestamp = 0; | |
58 | ||
59 | /* Global variables for machine-dependent things. */ | |
60 | ||
61 | /* Saved operands from the last compare to use when we generate an scc | |
62 | or bcc insn. */ | |
63 | rtx arch_compare_op0; | |
64 | rtx arch_compare_op1; | |
65 | ||
66 | /* Provides the class number of the smallest class containing | |
67 | reg number. */ | |
0139adca | 68 | const int regno_reg_class[FIRST_PSEUDO_REGISTER] = |
8f90be4c NC |
69 | { |
70 | GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS, | |
71 | LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS, | |
72 | LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS, | |
73 | LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS, | |
74 | GENERAL_REGS, C_REGS, NO_REGS, NO_REGS, | |
75 | }; | |
76 | ||
77 | /* Provide reg_class from a letter such as appears in the machine | |
78 | description. */ | |
0b5826ac | 79 | const enum reg_class reg_class_from_letter[] = |
8f90be4c NC |
80 | { |
81 | /* a */ LRW_REGS, /* b */ ONLYR1_REGS, /* c */ C_REGS, /* d */ NO_REGS, | |
82 | /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS, | |
83 | /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ NO_REGS, | |
84 | /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS, | |
85 | /* q */ NO_REGS, /* r */ GENERAL_REGS, /* s */ NO_REGS, /* t */ NO_REGS, | |
86 | /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ ALL_REGS, | |
87 | /* y */ NO_REGS, /* z */ NO_REGS | |
88 | }; | |
89 | ||
f27cd94d NC |
90 | struct mcore_frame |
91 | { | |
08903e08 SB |
92 | int arg_size; /* Stdarg spills (bytes). */ |
93 | int reg_size; /* Non-volatile reg saves (bytes). */ | |
94 | int reg_mask; /* Non-volatile reg saves. */ | |
95 | int local_size; /* Locals. */ | |
96 | int outbound_size; /* Arg overflow on calls out. */ | |
f27cd94d NC |
97 | int pad_outbound; |
98 | int pad_local; | |
99 | int pad_reg; | |
100 | /* Describe the steps we'll use to grow it. */ | |
08903e08 | 101 | #define MAX_STACK_GROWS 4 /* Gives us some spare space. */ |
f27cd94d NC |
102 | int growth[MAX_STACK_GROWS]; |
103 | int arg_offset; | |
104 | int reg_offset; | |
105 | int reg_growth; | |
106 | int local_growth; | |
107 | }; | |
108 | ||
109 | typedef enum | |
110 | { | |
111 | COND_NO, | |
112 | COND_MOV_INSN, | |
113 | COND_CLR_INSN, | |
114 | COND_INC_INSN, | |
115 | COND_DEC_INSN, | |
116 | COND_BRANCH_INSN | |
117 | } | |
118 | cond_type; | |
119 | ||
08903e08 SB |
120 | static void output_stack_adjust (int, int); |
121 | static int calc_live_regs (int *); | |
122 | static int const_ok_for_mcore (int); | |
123 | static int try_constant_tricks (long, int *, int *); | |
124 | static const char * output_inline_const (enum machine_mode, rtx *); | |
125 | static void block_move_sequence (rtx, rtx, rtx, rtx, int, int, int); | |
126 | static void layout_mcore_frame (struct mcore_frame *); | |
09a2b93a | 127 | static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int); |
08903e08 SB |
128 | static cond_type is_cond_candidate (rtx); |
129 | static rtx emit_new_cond_insn (rtx, int); | |
130 | static rtx conditionalize_block (rtx); | |
131 | static void conditionalize_optimization (void); | |
132 | static void mcore_reorg (void); | |
133 | static rtx handle_structs_in_regs (enum machine_mode, tree, int); | |
134 | static void mcore_mark_dllexport (tree); | |
135 | static void mcore_mark_dllimport (tree); | |
136 | static int mcore_dllexport_p (tree); | |
137 | static int mcore_dllimport_p (tree); | |
91d231cb | 138 | const struct attribute_spec mcore_attribute_table[]; |
08903e08 | 139 | static tree mcore_handle_naked_attribute (tree *, tree, tree, int, bool *); |
ede75ee8 | 140 | #ifdef OBJECT_FORMAT_ELF |
08903e08 SB |
141 | static void mcore_asm_named_section (const char *, |
142 | unsigned int); | |
ede75ee8 | 143 | #endif |
08903e08 SB |
144 | static void mcore_unique_section (tree, int); |
145 | static void mcore_encode_section_info (tree, rtx, int); | |
146 | static const char *mcore_strip_name_encoding (const char *); | |
147 | static int mcore_const_costs (rtx, RTX_CODE); | |
148 | static int mcore_and_cost (rtx); | |
149 | static int mcore_ior_cost (rtx); | |
150 | static bool mcore_rtx_costs (rtx, int, int, int *); | |
09a2b93a KH |
151 | static void mcore_external_libcall (rtx); |
152 | static bool mcore_return_in_memory (tree, tree); | |
153 | ||
672a6f42 NB |
154 | \f |
155 | /* Initialize the GCC target structure. */ | |
09a2b93a KH |
156 | #undef TARGET_ASM_EXTERNAL_LIBCALL |
157 | #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall | |
158 | ||
b2ca3702 | 159 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
08903e08 SB |
160 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
161 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes | |
672a6f42 NB |
162 | #endif |
163 | ||
301d03af | 164 | #ifdef OBJECT_FORMAT_ELF |
08903e08 | 165 | #undef TARGET_ASM_UNALIGNED_HI_OP |
301d03af | 166 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" |
08903e08 | 167 | #undef TARGET_ASM_UNALIGNED_SI_OP |
301d03af RS |
168 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" |
169 | #endif | |
170 | ||
08903e08 SB |
171 | #undef TARGET_ATTRIBUTE_TABLE |
172 | #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table | |
173 | #undef TARGET_ASM_UNIQUE_SECTION | |
174 | #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section | |
ab5c8549 JJ |
175 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION |
176 | #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section | |
08903e08 SB |
177 | #undef TARGET_ENCODE_SECTION_INFO |
178 | #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info | |
179 | #undef TARGET_STRIP_NAME_ENCODING | |
180 | #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding | |
181 | #undef TARGET_RTX_COSTS | |
182 | #define TARGET_RTX_COSTS mcore_rtx_costs | |
183 | #undef TARGET_ADDRESS_COST | |
184 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
185 | #undef TARGET_MACHINE_DEPENDENT_REORG | |
186 | #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg | |
18dbd950 | 187 | |
09a2b93a KH |
188 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
189 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
190 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
191 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
192 | #undef TARGET_PROMOTE_PROTOTYPES | |
193 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
194 | ||
09a2b93a KH |
195 | #undef TARGET_RETURN_IN_MEMORY |
196 | #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory | |
fe984136 RH |
197 | #undef TARGET_MUST_PASS_IN_STACK |
198 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
199 | #undef TARGET_PASS_BY_REFERENCE |
200 | #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack | |
09a2b93a KH |
201 | |
202 | #undef TARGET_SETUP_INCOMING_VARARGS | |
203 | #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs | |
204 | ||
f6897b10 | 205 | struct gcc_target targetm = TARGET_INITIALIZER; |
f27cd94d | 206 | \f |
8f90be4c NC |
207 | /* Adjust the stack and return the number of bytes taken to do it. */ |
208 | static void | |
08903e08 | 209 | output_stack_adjust (int direction, int size) |
8f90be4c | 210 | { |
4816b8e4 | 211 | /* If extending stack a lot, we do it incrementally. */ |
8f90be4c NC |
212 | if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0) |
213 | { | |
f1c25d3b | 214 | rtx tmp = gen_rtx_REG (SImode, 1); |
8f90be4c | 215 | rtx memref; |
08903e08 | 216 | |
8f90be4c NC |
217 | emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment))); |
218 | do | |
219 | { | |
220 | emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp)); | |
f1c25d3b | 221 | memref = gen_rtx_MEM (SImode, stack_pointer_rtx); |
8f90be4c NC |
222 | MEM_VOLATILE_P (memref) = 1; |
223 | emit_insn (gen_movsi (memref, stack_pointer_rtx)); | |
224 | size -= mcore_stack_increment; | |
225 | } | |
226 | while (size > mcore_stack_increment); | |
227 | ||
4816b8e4 NC |
228 | /* SIZE is now the residual for the last adjustment, |
229 | which doesn't require a probe. */ | |
8f90be4c NC |
230 | } |
231 | ||
232 | if (size) | |
233 | { | |
234 | rtx insn; | |
235 | rtx val = GEN_INT (size); | |
236 | ||
237 | if (size > 32) | |
238 | { | |
f1c25d3b | 239 | rtx nval = gen_rtx_REG (SImode, 1); |
8f90be4c NC |
240 | emit_insn (gen_movsi (nval, val)); |
241 | val = nval; | |
242 | } | |
243 | ||
244 | if (direction > 0) | |
245 | insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val); | |
246 | else | |
247 | insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val); | |
248 | ||
249 | emit_insn (insn); | |
250 | } | |
251 | } | |
252 | ||
4816b8e4 NC |
253 | /* Work out the registers which need to be saved, |
254 | both as a mask and a count. */ | |
255 | ||
8f90be4c | 256 | static int |
08903e08 | 257 | calc_live_regs (int * count) |
8f90be4c NC |
258 | { |
259 | int reg; | |
260 | int live_regs_mask = 0; | |
261 | ||
262 | * count = 0; | |
263 | ||
264 | for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++) | |
265 | { | |
266 | if (regs_ever_live[reg] && !call_used_regs[reg]) | |
267 | { | |
268 | (*count)++; | |
269 | live_regs_mask |= (1 << reg); | |
270 | } | |
271 | } | |
272 | ||
273 | return live_regs_mask; | |
274 | } | |
275 | ||
276 | /* Print the operand address in x to the stream. */ | |
4816b8e4 | 277 | |
8f90be4c | 278 | void |
08903e08 | 279 | mcore_print_operand_address (FILE * stream, rtx x) |
8f90be4c NC |
280 | { |
281 | switch (GET_CODE (x)) | |
282 | { | |
283 | case REG: | |
284 | fprintf (stream, "(%s)", reg_names[REGNO (x)]); | |
285 | break; | |
286 | ||
287 | case PLUS: | |
288 | { | |
289 | rtx base = XEXP (x, 0); | |
290 | rtx index = XEXP (x, 1); | |
291 | ||
292 | if (GET_CODE (base) != REG) | |
293 | { | |
294 | /* Ensure that BASE is a register (one of them must be). */ | |
295 | rtx temp = base; | |
296 | base = index; | |
297 | index = temp; | |
298 | } | |
299 | ||
300 | switch (GET_CODE (index)) | |
301 | { | |
302 | case CONST_INT: | |
fd7b8952 KG |
303 | fprintf (stream, "(%s," HOST_WIDE_INT_PRINT_DEC ")", |
304 | reg_names[REGNO(base)], INTVAL (index)); | |
8f90be4c NC |
305 | break; |
306 | ||
307 | default: | |
308 | debug_rtx (x); | |
309 | ||
310 | abort (); | |
311 | } | |
312 | } | |
313 | ||
314 | break; | |
315 | ||
316 | default: | |
317 | output_addr_const (stream, x); | |
318 | break; | |
319 | } | |
320 | } | |
321 | ||
322 | /* Print operand x (an rtx) in assembler syntax to file stream | |
323 | according to modifier code. | |
324 | ||
325 | 'R' print the next register or memory location along, ie the lsw in | |
326 | a double word value | |
327 | 'O' print a constant without the # | |
328 | 'M' print a constant as its negative | |
329 | 'P' print log2 of a power of two | |
330 | 'Q' print log2 of an inverse of a power of two | |
331 | 'U' print register for ldm/stm instruction | |
4816b8e4 NC |
332 | 'X' print byte number for xtrbN instruction. */ |
333 | ||
8f90be4c | 334 | void |
08903e08 | 335 | mcore_print_operand (FILE * stream, rtx x, int code) |
8f90be4c NC |
336 | { |
337 | switch (code) | |
338 | { | |
339 | case 'N': | |
340 | if (INTVAL(x) == -1) | |
341 | fprintf (asm_out_file, "32"); | |
342 | else | |
343 | fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1)); | |
344 | break; | |
345 | case 'P': | |
346 | fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x))); | |
347 | break; | |
348 | case 'Q': | |
349 | fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x))); | |
350 | break; | |
351 | case 'O': | |
fd7b8952 | 352 | fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); |
8f90be4c NC |
353 | break; |
354 | case 'M': | |
fd7b8952 | 355 | fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, - INTVAL (x)); |
8f90be4c NC |
356 | break; |
357 | case 'R': | |
358 | /* Next location along in memory or register. */ | |
359 | switch (GET_CODE (x)) | |
360 | { | |
361 | case REG: | |
362 | fputs (reg_names[REGNO (x) + 1], (stream)); | |
363 | break; | |
364 | case MEM: | |
b72f00af RK |
365 | mcore_print_operand_address |
366 | (stream, XEXP (adjust_address (x, SImode, 4), 0)); | |
8f90be4c NC |
367 | break; |
368 | default: | |
369 | abort (); | |
370 | } | |
371 | break; | |
372 | case 'U': | |
373 | fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)], | |
374 | reg_names[REGNO (x) + 3]); | |
375 | break; | |
376 | case 'x': | |
fd7b8952 | 377 | fprintf (asm_out_file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
8f90be4c NC |
378 | break; |
379 | case 'X': | |
fd7b8952 | 380 | fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, 3 - INTVAL (x) / 8); |
8f90be4c NC |
381 | break; |
382 | ||
383 | default: | |
384 | switch (GET_CODE (x)) | |
385 | { | |
386 | case REG: | |
387 | fputs (reg_names[REGNO (x)], (stream)); | |
388 | break; | |
389 | case MEM: | |
390 | output_address (XEXP (x, 0)); | |
391 | break; | |
392 | default: | |
393 | output_addr_const (stream, x); | |
394 | break; | |
395 | } | |
396 | break; | |
397 | } | |
398 | } | |
399 | ||
400 | /* What does a constant cost ? */ | |
4816b8e4 | 401 | |
3c50106f | 402 | static int |
08903e08 | 403 | mcore_const_costs (rtx exp, enum rtx_code code) |
8f90be4c | 404 | { |
8f90be4c NC |
405 | int val = INTVAL (exp); |
406 | ||
407 | /* Easy constants. */ | |
408 | if ( CONST_OK_FOR_I (val) | |
409 | || CONST_OK_FOR_M (val) | |
410 | || CONST_OK_FOR_N (val) | |
411 | || (code == PLUS && CONST_OK_FOR_L (val))) | |
412 | return 1; | |
413 | else if (code == AND | |
414 | && ( CONST_OK_FOR_M (~val) | |
415 | || CONST_OK_FOR_N (~val))) | |
416 | return 2; | |
417 | else if (code == PLUS | |
418 | && ( CONST_OK_FOR_I (-val) | |
419 | || CONST_OK_FOR_M (-val) | |
420 | || CONST_OK_FOR_N (-val))) | |
421 | return 2; | |
422 | ||
423 | return 5; | |
424 | } | |
425 | ||
426 | /* What does an and instruction cost - we do this b/c immediates may | |
427 | have been relaxed. We want to ensure that cse will cse relaxed immeds | |
4816b8e4 NC |
428 | out. Otherwise we'll get bad code (multiple reloads of the same const). */ |
429 | ||
3c50106f | 430 | static int |
08903e08 | 431 | mcore_and_cost (rtx x) |
8f90be4c NC |
432 | { |
433 | int val; | |
434 | ||
435 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
436 | return 2; | |
437 | ||
438 | val = INTVAL (XEXP (x, 1)); | |
439 | ||
4816b8e4 | 440 | /* Do it directly. */ |
8f90be4c NC |
441 | if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val)) |
442 | return 2; | |
443 | /* Takes one instruction to load. */ | |
444 | else if (const_ok_for_mcore (val)) | |
445 | return 3; | |
446 | /* Takes two instructions to load. */ | |
447 | else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val)) | |
448 | return 4; | |
449 | ||
4816b8e4 | 450 | /* Takes a lrw to load. */ |
8f90be4c NC |
451 | return 5; |
452 | } | |
453 | ||
4816b8e4 NC |
454 | /* What does an or cost - see and_cost(). */ |
455 | ||
3c50106f | 456 | static int |
08903e08 | 457 | mcore_ior_cost (rtx x) |
8f90be4c NC |
458 | { |
459 | int val; | |
460 | ||
461 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
462 | return 2; | |
463 | ||
464 | val = INTVAL (XEXP (x, 1)); | |
465 | ||
4816b8e4 | 466 | /* Do it directly with bclri. */ |
8f90be4c NC |
467 | if (CONST_OK_FOR_M (val)) |
468 | return 2; | |
4816b8e4 | 469 | /* Takes one instruction to load. */ |
8f90be4c NC |
470 | else if (const_ok_for_mcore (val)) |
471 | return 3; | |
4816b8e4 | 472 | /* Takes two instructions to load. */ |
8f90be4c NC |
473 | else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val)) |
474 | return 4; | |
475 | ||
4816b8e4 | 476 | /* Takes a lrw to load. */ |
8f90be4c NC |
477 | return 5; |
478 | } | |
479 | ||
3c50106f | 480 | static bool |
08903e08 | 481 | mcore_rtx_costs (rtx x, int code, int outer_code, int * total) |
3c50106f RH |
482 | { |
483 | switch (code) | |
484 | { | |
485 | case CONST_INT: | |
486 | *total = mcore_const_costs (x, outer_code); | |
487 | return true; | |
488 | case CONST: | |
489 | case LABEL_REF: | |
490 | case SYMBOL_REF: | |
491 | *total = 5; | |
492 | return true; | |
493 | case CONST_DOUBLE: | |
494 | *total = 10; | |
495 | return true; | |
496 | ||
497 | case AND: | |
498 | *total = COSTS_N_INSNS (mcore_and_cost (x)); | |
499 | return true; | |
500 | ||
501 | case IOR: | |
502 | *total = COSTS_N_INSNS (mcore_ior_cost (x)); | |
503 | return true; | |
504 | ||
505 | case DIV: | |
506 | case UDIV: | |
507 | case MOD: | |
508 | case UMOD: | |
509 | case FLOAT: | |
510 | case FIX: | |
511 | *total = COSTS_N_INSNS (100); | |
512 | return true; | |
513 | ||
514 | default: | |
515 | return false; | |
516 | } | |
517 | } | |
518 | ||
8f90be4c NC |
519 | /* Check to see if a comparison against a constant can be made more efficient |
520 | by incrementing/decrementing the constant to get one that is more efficient | |
521 | to load. */ | |
4816b8e4 | 522 | |
8f90be4c | 523 | int |
08903e08 | 524 | mcore_modify_comparison (enum rtx_code code) |
8f90be4c | 525 | { |
08903e08 | 526 | rtx op1 = arch_compare_op1; |
8f90be4c NC |
527 | |
528 | if (GET_CODE (op1) == CONST_INT) | |
529 | { | |
530 | int val = INTVAL (op1); | |
531 | ||
532 | switch (code) | |
533 | { | |
534 | case LE: | |
535 | if (CONST_OK_FOR_J (val + 1)) | |
536 | { | |
537 | arch_compare_op1 = GEN_INT (val + 1); | |
538 | return 1; | |
539 | } | |
540 | break; | |
541 | ||
542 | default: | |
543 | break; | |
544 | } | |
545 | } | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
550 | /* Prepare the operands for a comparison. */ | |
4816b8e4 | 551 | |
8f90be4c | 552 | rtx |
08903e08 | 553 | mcore_gen_compare_reg (enum rtx_code code) |
8f90be4c NC |
554 | { |
555 | rtx op0 = arch_compare_op0; | |
556 | rtx op1 = arch_compare_op1; | |
f1c25d3b | 557 | rtx cc_reg = gen_rtx_REG (CCmode, CC_REG); |
8f90be4c NC |
558 | |
559 | if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT) | |
560 | op1 = force_reg (SImode, op1); | |
561 | ||
562 | /* cmpnei: 0-31 (K immediate) | |
4816b8e4 | 563 | cmplti: 1-32 (J immediate, 0 using btsti x,31). */ |
8f90be4c NC |
564 | switch (code) |
565 | { | |
4816b8e4 | 566 | case EQ: /* Use inverted condition, cmpne. */ |
8f90be4c | 567 | code = NE; |
08903e08 | 568 | /* Drop through. */ |
4816b8e4 NC |
569 | |
570 | case NE: /* Use normal condition, cmpne. */ | |
8f90be4c NC |
571 | if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1))) |
572 | op1 = force_reg (SImode, op1); | |
573 | break; | |
574 | ||
4816b8e4 | 575 | case LE: /* Use inverted condition, reversed cmplt. */ |
8f90be4c | 576 | code = GT; |
08903e08 | 577 | /* Drop through. */ |
4816b8e4 NC |
578 | |
579 | case GT: /* Use normal condition, reversed cmplt. */ | |
8f90be4c NC |
580 | if (GET_CODE (op1) == CONST_INT) |
581 | op1 = force_reg (SImode, op1); | |
582 | break; | |
583 | ||
4816b8e4 | 584 | case GE: /* Use inverted condition, cmplt. */ |
8f90be4c | 585 | code = LT; |
08903e08 | 586 | /* Drop through. */ |
4816b8e4 NC |
587 | |
588 | case LT: /* Use normal condition, cmplt. */ | |
8f90be4c | 589 | if (GET_CODE (op1) == CONST_INT && |
08903e08 | 590 | /* covered by btsti x,31. */ |
8f90be4c NC |
591 | INTVAL (op1) != 0 && |
592 | ! CONST_OK_FOR_J (INTVAL (op1))) | |
593 | op1 = force_reg (SImode, op1); | |
594 | break; | |
595 | ||
4816b8e4 | 596 | case GTU: /* Use inverted condition, cmple. */ |
8f90be4c NC |
597 | if (GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0) |
598 | { | |
599 | /* Unsigned > 0 is the same as != 0, but we need | |
600 | to invert the condition, so we want to set | |
601 | code = EQ. This cannot be done however, as the | |
602 | mcore does not support such a test. Instead we | |
603 | cope with this case in the "bgtu" pattern itself | |
604 | so we should never reach this point. */ | |
605 | /* code = EQ; */ | |
606 | abort (); | |
607 | break; | |
608 | } | |
609 | code = LEU; | |
08903e08 | 610 | /* Drop through. */ |
4816b8e4 | 611 | |
14bc6742 | 612 | case LEU: /* Use normal condition, reversed cmphs. */ |
8f90be4c NC |
613 | if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) |
614 | op1 = force_reg (SImode, op1); | |
615 | break; | |
616 | ||
4816b8e4 | 617 | case LTU: /* Use inverted condition, cmphs. */ |
8f90be4c | 618 | code = GEU; |
08903e08 | 619 | /* Drop through. */ |
4816b8e4 NC |
620 | |
621 | case GEU: /* Use normal condition, cmphs. */ | |
8f90be4c NC |
622 | if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) |
623 | op1 = force_reg (SImode, op1); | |
624 | break; | |
625 | ||
626 | default: | |
627 | break; | |
628 | } | |
629 | ||
1c563bed | 630 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_fmt_ee (code, CCmode, op0, op1))); |
8f90be4c NC |
631 | |
632 | return cc_reg; | |
633 | } | |
634 | ||
8f90be4c | 635 | int |
08903e08 | 636 | mcore_symbolic_address_p (rtx x) |
8f90be4c NC |
637 | { |
638 | switch (GET_CODE (x)) | |
639 | { | |
640 | case SYMBOL_REF: | |
641 | case LABEL_REF: | |
642 | return 1; | |
643 | case CONST: | |
644 | x = XEXP (x, 0); | |
645 | return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF | |
646 | || GET_CODE (XEXP (x, 0)) == LABEL_REF) | |
647 | && GET_CODE (XEXP (x, 1)) == CONST_INT); | |
648 | default: | |
649 | return 0; | |
650 | } | |
651 | } | |
652 | ||
653 | int | |
08903e08 | 654 | mcore_call_address_operand (rtx x, enum machine_mode mode) |
8f90be4c NC |
655 | { |
656 | return register_operand (x, mode) || CONSTANT_P (x); | |
657 | } | |
658 | ||
659 | /* Functions to output assembly code for a function call. */ | |
f27cd94d | 660 | |
8f90be4c | 661 | char * |
08903e08 | 662 | mcore_output_call (rtx operands[], int index) |
8f90be4c NC |
663 | { |
664 | static char buffer[20]; | |
665 | rtx addr = operands [index]; | |
666 | ||
667 | if (REG_P (addr)) | |
668 | { | |
669 | if (TARGET_CG_DATA) | |
670 | { | |
671 | if (mcore_current_function_name == 0) | |
672 | abort (); | |
673 | ||
674 | ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, | |
675 | "unknown", 1); | |
676 | } | |
677 | ||
678 | sprintf (buffer, "jsr\t%%%d", index); | |
679 | } | |
680 | else | |
681 | { | |
682 | if (TARGET_CG_DATA) | |
683 | { | |
684 | if (mcore_current_function_name == 0) | |
685 | abort (); | |
686 | ||
687 | if (GET_CODE (addr) != SYMBOL_REF) | |
688 | abort (); | |
689 | ||
690 | ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, XSTR (addr, 0), 0); | |
691 | } | |
692 | ||
693 | sprintf (buffer, "jbsr\t%%%d", index); | |
694 | } | |
695 | ||
696 | return buffer; | |
697 | } | |
698 | ||
699 | /* Can we load a constant with a single instruction ? */ | |
4816b8e4 | 700 | |
8f90be4c | 701 | static int |
08903e08 | 702 | const_ok_for_mcore (int value) |
8f90be4c NC |
703 | { |
704 | if (value >= 0 && value <= 127) | |
705 | return 1; | |
706 | ||
707 | /* Try exact power of two. */ | |
708 | if ((value & (value - 1)) == 0) | |
709 | return 1; | |
710 | ||
14bc6742 | 711 | /* Try exact power of two - 1. */ |
8f90be4c NC |
712 | if ((value & (value + 1)) == 0) |
713 | return 1; | |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
718 | /* Can we load a constant inline with up to 2 instructions ? */ | |
4816b8e4 | 719 | |
8f90be4c | 720 | int |
08903e08 | 721 | mcore_const_ok_for_inline (long value) |
8f90be4c NC |
722 | { |
723 | int x, y; | |
724 | ||
725 | return try_constant_tricks (value, & x, & y) > 0; | |
726 | } | |
727 | ||
728 | /* Are we loading the constant using a not ? */ | |
4816b8e4 | 729 | |
8f90be4c | 730 | int |
08903e08 | 731 | mcore_const_trick_uses_not (long value) |
8f90be4c NC |
732 | { |
733 | int x, y; | |
734 | ||
735 | return try_constant_tricks (value, & x, & y) == 2; | |
736 | } | |
737 | ||
738 | /* Try tricks to load a constant inline and return the trick number if | |
739 | success (0 is non-inlinable). | |
4816b8e4 NC |
740 | |
741 | 0: not inlinable | |
742 | 1: single instruction (do the usual thing) | |
743 | 2: single insn followed by a 'not' | |
744 | 3: single insn followed by a subi | |
745 | 4: single insn followed by an addi | |
746 | 5: single insn followed by rsubi | |
747 | 6: single insn followed by bseti | |
748 | 7: single insn followed by bclri | |
749 | 8: single insn followed by rotli | |
750 | 9: single insn followed by lsli | |
751 | 10: single insn followed by ixh | |
752 | 11: single insn followed by ixw. */ | |
8f90be4c NC |
753 | |
754 | static int | |
08903e08 | 755 | try_constant_tricks (long value, int * x, int * y) |
8f90be4c NC |
756 | { |
757 | int i; | |
758 | unsigned bit, shf, rot; | |
759 | ||
760 | if (const_ok_for_mcore (value)) | |
4816b8e4 | 761 | return 1; /* Do the usual thing. */ |
8f90be4c NC |
762 | |
763 | if (TARGET_HARDLIT) | |
764 | { | |
765 | if (const_ok_for_mcore (~value)) | |
766 | { | |
767 | *x = ~value; | |
768 | return 2; | |
769 | } | |
770 | ||
771 | for (i = 1; i <= 32; i++) | |
772 | { | |
773 | if (const_ok_for_mcore (value - i)) | |
774 | { | |
775 | *x = value - i; | |
776 | *y = i; | |
777 | ||
778 | return 3; | |
779 | } | |
780 | ||
781 | if (const_ok_for_mcore (value + i)) | |
782 | { | |
783 | *x = value + i; | |
784 | *y = i; | |
785 | ||
786 | return 4; | |
787 | } | |
788 | } | |
789 | ||
11f9ed1a | 790 | bit = 0x80000000L; |
8f90be4c NC |
791 | |
792 | for (i = 0; i <= 31; i++) | |
793 | { | |
794 | if (const_ok_for_mcore (i - value)) | |
795 | { | |
796 | *x = i - value; | |
797 | *y = i; | |
798 | ||
799 | return 5; | |
800 | } | |
801 | ||
802 | if (const_ok_for_mcore (value & ~bit)) | |
803 | { | |
804 | *y = bit; | |
805 | *x = value & ~bit; | |
806 | ||
807 | return 6; | |
808 | } | |
809 | ||
810 | if (const_ok_for_mcore (value | bit)) | |
811 | { | |
812 | *y = ~bit; | |
813 | *x = value | bit; | |
814 | ||
815 | return 7; | |
816 | } | |
817 | ||
818 | bit >>= 1; | |
819 | } | |
820 | ||
821 | shf = value; | |
822 | rot = value; | |
823 | ||
824 | for (i = 1; i < 31; i++) | |
825 | { | |
826 | int c; | |
827 | ||
828 | /* MCore has rotate left. */ | |
829 | c = rot << 31; | |
830 | rot >>= 1; | |
831 | rot &= 0x7FFFFFFF; | |
832 | rot |= c; /* Simulate rotate. */ | |
833 | ||
834 | if (const_ok_for_mcore (rot)) | |
835 | { | |
836 | *y = i; | |
837 | *x = rot; | |
838 | ||
839 | return 8; | |
840 | } | |
841 | ||
842 | if (shf & 1) | |
4816b8e4 | 843 | shf = 0; /* Can't use logical shift, low order bit is one. */ |
8f90be4c NC |
844 | |
845 | shf >>= 1; | |
846 | ||
847 | if (shf != 0 && const_ok_for_mcore (shf)) | |
848 | { | |
849 | *y = i; | |
850 | *x = shf; | |
851 | ||
852 | return 9; | |
853 | } | |
854 | } | |
855 | ||
856 | if ((value % 3) == 0 && const_ok_for_mcore (value / 3)) | |
857 | { | |
858 | *x = value / 3; | |
859 | ||
860 | return 10; | |
861 | } | |
862 | ||
863 | if ((value % 5) == 0 && const_ok_for_mcore (value / 5)) | |
864 | { | |
865 | *x = value / 5; | |
866 | ||
867 | return 11; | |
868 | } | |
869 | } | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
8f90be4c NC |
874 | /* Check whether reg is dead at first. This is done by searching ahead |
875 | for either the next use (i.e., reg is live), a death note, or a set of | |
876 | reg. Don't just use dead_or_set_p() since reload does not always mark | |
877 | deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We | |
4816b8e4 NC |
878 | can ignore subregs by extracting the actual register. BRC */ |
879 | ||
8f90be4c | 880 | int |
08903e08 | 881 | mcore_is_dead (rtx first, rtx reg) |
8f90be4c NC |
882 | { |
883 | rtx insn; | |
884 | ||
885 | /* For mcore, subregs can't live independently of their parent regs. */ | |
886 | if (GET_CODE (reg) == SUBREG) | |
887 | reg = SUBREG_REG (reg); | |
888 | ||
889 | /* Dies immediately. */ | |
890 | if (dead_or_set_p (first, reg)) | |
891 | return 1; | |
892 | ||
893 | /* Look for conclusive evidence of live/death, otherwise we have | |
894 | to assume that it is live. */ | |
895 | for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn)) | |
896 | { | |
897 | if (GET_CODE (insn) == JUMP_INSN) | |
898 | return 0; /* We lose track, assume it is alive. */ | |
899 | ||
900 | else if (GET_CODE(insn) == CALL_INSN) | |
901 | { | |
902 | /* Call's might use it for target or register parms. */ | |
903 | if (reg_referenced_p (reg, PATTERN (insn)) | |
904 | || find_reg_fusage (insn, USE, reg)) | |
905 | return 0; | |
906 | else if (dead_or_set_p (insn, reg)) | |
907 | return 1; | |
908 | } | |
909 | else if (GET_CODE (insn) == INSN) | |
910 | { | |
911 | if (reg_referenced_p (reg, PATTERN (insn))) | |
912 | return 0; | |
913 | else if (dead_or_set_p (insn, reg)) | |
914 | return 1; | |
915 | } | |
916 | } | |
917 | ||
1e5f1716 | 918 | /* No conclusive evidence either way, we cannot take the chance |
8f90be4c NC |
919 | that control flow hid the use from us -- "I'm not dead yet". */ |
920 | return 0; | |
921 | } | |
922 | ||
8f90be4c | 923 | /* Count the number of ones in mask. */ |
4816b8e4 | 924 | |
8f90be4c | 925 | int |
08903e08 | 926 | mcore_num_ones (int mask) |
8f90be4c | 927 | { |
4816b8e4 | 928 | /* A trick to count set bits recently posted on comp.compilers. */ |
8f90be4c NC |
929 | mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555); |
930 | mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333); | |
931 | mask = ((mask >> 4) + mask) & 0x0f0f0f0f; | |
932 | mask = ((mask >> 8) + mask); | |
933 | ||
934 | return (mask + (mask >> 16)) & 0xff; | |
935 | } | |
936 | ||
4816b8e4 NC |
937 | /* Count the number of zeros in mask. */ |
938 | ||
8f90be4c | 939 | int |
08903e08 | 940 | mcore_num_zeros (int mask) |
8f90be4c NC |
941 | { |
942 | return 32 - mcore_num_ones (mask); | |
943 | } | |
944 | ||
945 | /* Determine byte being masked. */ | |
4816b8e4 | 946 | |
8f90be4c | 947 | int |
08903e08 | 948 | mcore_byte_offset (unsigned int mask) |
8f90be4c | 949 | { |
11f9ed1a | 950 | if (mask == 0x00ffffffL) |
8f90be4c | 951 | return 0; |
11f9ed1a | 952 | else if (mask == 0xff00ffffL) |
8f90be4c | 953 | return 1; |
11f9ed1a | 954 | else if (mask == 0xffff00ffL) |
8f90be4c | 955 | return 2; |
11f9ed1a | 956 | else if (mask == 0xffffff00L) |
8f90be4c NC |
957 | return 3; |
958 | ||
959 | return -1; | |
960 | } | |
961 | ||
962 | /* Determine halfword being masked. */ | |
4816b8e4 | 963 | |
8f90be4c | 964 | int |
08903e08 | 965 | mcore_halfword_offset (unsigned int mask) |
8f90be4c NC |
966 | { |
967 | if (mask == 0x0000ffffL) | |
968 | return 0; | |
11f9ed1a | 969 | else if (mask == 0xffff0000L) |
8f90be4c NC |
970 | return 1; |
971 | ||
972 | return -1; | |
973 | } | |
974 | ||
975 | /* Output a series of bseti's corresponding to mask. */ | |
4816b8e4 | 976 | |
f27cd94d | 977 | const char * |
08903e08 | 978 | mcore_output_bseti (rtx dst, int mask) |
8f90be4c NC |
979 | { |
980 | rtx out_operands[2]; | |
981 | int bit; | |
982 | ||
983 | out_operands[0] = dst; | |
984 | ||
985 | for (bit = 0; bit < 32; bit++) | |
986 | { | |
987 | if ((mask & 0x1) == 0x1) | |
988 | { | |
989 | out_operands[1] = GEN_INT (bit); | |
990 | ||
991 | output_asm_insn ("bseti\t%0,%1", out_operands); | |
992 | } | |
993 | mask >>= 1; | |
994 | } | |
995 | ||
996 | return ""; | |
997 | } | |
998 | ||
999 | /* Output a series of bclri's corresponding to mask. */ | |
4816b8e4 | 1000 | |
f27cd94d | 1001 | const char * |
08903e08 | 1002 | mcore_output_bclri (rtx dst, int mask) |
8f90be4c NC |
1003 | { |
1004 | rtx out_operands[2]; | |
1005 | int bit; | |
1006 | ||
1007 | out_operands[0] = dst; | |
1008 | ||
1009 | for (bit = 0; bit < 32; bit++) | |
1010 | { | |
1011 | if ((mask & 0x1) == 0x0) | |
1012 | { | |
1013 | out_operands[1] = GEN_INT (bit); | |
1014 | ||
1015 | output_asm_insn ("bclri\t%0,%1", out_operands); | |
1016 | } | |
1017 | ||
1018 | mask >>= 1; | |
1019 | } | |
1020 | ||
1021 | return ""; | |
1022 | } | |
1023 | ||
1024 | /* Output a conditional move of two constants that are +/- 1 within each | |
1025 | other. See the "movtK" patterns in mcore.md. I'm not sure this is | |
1026 | really worth the effort. */ | |
4816b8e4 | 1027 | |
f27cd94d | 1028 | const char * |
08903e08 | 1029 | mcore_output_cmov (rtx operands[], int cmp_t, const char * test) |
8f90be4c NC |
1030 | { |
1031 | int load_value; | |
1032 | int adjust_value; | |
1033 | rtx out_operands[4]; | |
1034 | ||
1035 | out_operands[0] = operands[0]; | |
1036 | ||
4816b8e4 | 1037 | /* Check to see which constant is loadable. */ |
8f90be4c NC |
1038 | if (const_ok_for_mcore (INTVAL (operands[1]))) |
1039 | { | |
1040 | out_operands[1] = operands[1]; | |
1041 | out_operands[2] = operands[2]; | |
1042 | } | |
1043 | else if (const_ok_for_mcore (INTVAL (operands[2]))) | |
1044 | { | |
1045 | out_operands[1] = operands[2]; | |
1046 | out_operands[2] = operands[1]; | |
1047 | ||
4816b8e4 | 1048 | /* Complement test since constants are swapped. */ |
8f90be4c NC |
1049 | cmp_t = (cmp_t == 0); |
1050 | } | |
1051 | load_value = INTVAL (out_operands[1]); | |
1052 | adjust_value = INTVAL (out_operands[2]); | |
1053 | ||
4816b8e4 | 1054 | /* First output the test if folded into the pattern. */ |
8f90be4c NC |
1055 | |
1056 | if (test) | |
1057 | output_asm_insn (test, operands); | |
1058 | ||
4816b8e4 | 1059 | /* Load the constant - for now, only support constants that can be |
8f90be4c NC |
1060 | generated with a single instruction. maybe add general inlinable |
1061 | constants later (this will increase the # of patterns since the | |
4816b8e4 | 1062 | instruction sequence has a different length attribute). */ |
8f90be4c NC |
1063 | if (load_value >= 0 && load_value <= 127) |
1064 | output_asm_insn ("movi\t%0,%1", out_operands); | |
1065 | else if ((load_value & (load_value - 1)) == 0) | |
1066 | output_asm_insn ("bgeni\t%0,%P1", out_operands); | |
1067 | else if ((load_value & (load_value + 1)) == 0) | |
1068 | output_asm_insn ("bmaski\t%0,%N1", out_operands); | |
1069 | ||
4816b8e4 | 1070 | /* Output the constant adjustment. */ |
8f90be4c NC |
1071 | if (load_value > adjust_value) |
1072 | { | |
1073 | if (cmp_t) | |
1074 | output_asm_insn ("decf\t%0", out_operands); | |
1075 | else | |
1076 | output_asm_insn ("dect\t%0", out_operands); | |
1077 | } | |
1078 | else | |
1079 | { | |
1080 | if (cmp_t) | |
1081 | output_asm_insn ("incf\t%0", out_operands); | |
1082 | else | |
1083 | output_asm_insn ("inct\t%0", out_operands); | |
1084 | } | |
1085 | ||
1086 | return ""; | |
1087 | } | |
1088 | ||
1089 | /* Outputs the peephole for moving a constant that gets not'ed followed | |
4816b8e4 NC |
1090 | by an and (i.e. combine the not and the and into andn). BRC */ |
1091 | ||
f27cd94d | 1092 | const char * |
08903e08 | 1093 | mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[]) |
8f90be4c NC |
1094 | { |
1095 | int x, y; | |
1096 | rtx out_operands[3]; | |
f27cd94d | 1097 | const char * load_op; |
8f90be4c NC |
1098 | char buf[256]; |
1099 | ||
1100 | if (try_constant_tricks (INTVAL (operands[1]), &x, &y) != 2) | |
1101 | abort (); | |
1102 | ||
1103 | out_operands[0] = operands[0]; | |
1104 | out_operands[1] = GEN_INT(x); | |
1105 | out_operands[2] = operands[2]; | |
1106 | ||
1107 | if (x >= 0 && x <= 127) | |
1108 | load_op = "movi\t%0,%1"; | |
4816b8e4 NC |
1109 | |
1110 | /* Try exact power of two. */ | |
8f90be4c NC |
1111 | else if ((x & (x - 1)) == 0) |
1112 | load_op = "bgeni\t%0,%P1"; | |
4816b8e4 NC |
1113 | |
1114 | /* Try exact power of two - 1. */ | |
8f90be4c NC |
1115 | else if ((x & (x + 1)) == 0) |
1116 | load_op = "bmaski\t%0,%N1"; | |
4816b8e4 | 1117 | |
8f90be4c NC |
1118 | else |
1119 | load_op = "BADMOVI\t%0,%1"; | |
1120 | ||
1121 | sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op); | |
1122 | output_asm_insn (buf, out_operands); | |
1123 | ||
1124 | return ""; | |
1125 | } | |
1126 | ||
1127 | /* Output an inline constant. */ | |
4816b8e4 | 1128 | |
f27cd94d | 1129 | static const char * |
08903e08 | 1130 | output_inline_const (enum machine_mode mode, rtx operands[]) |
8f90be4c NC |
1131 | { |
1132 | int x = 0, y = 0; | |
1133 | int trick_no; | |
1134 | rtx out_operands[3]; | |
1135 | char buf[256]; | |
1136 | char load_op[256]; | |
f27cd94d | 1137 | const char *dst_fmt; |
8f90be4c NC |
1138 | int value; |
1139 | ||
1140 | value = INTVAL (operands[1]); | |
1141 | ||
1142 | if ((trick_no = try_constant_tricks (value, &x, &y)) == 0) | |
1143 | { | |
1144 | /* lrw's are handled separately: Large inlinable constants | |
1145 | never get turned into lrw's. Our caller uses try_constant_tricks | |
1146 | to back off to an lrw rather than calling this routine. */ | |
1147 | abort (); | |
1148 | } | |
1149 | ||
1150 | if (trick_no == 1) | |
1151 | x = value; | |
1152 | ||
4816b8e4 | 1153 | /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */ |
8f90be4c NC |
1154 | out_operands[0] = operands[0]; |
1155 | out_operands[1] = GEN_INT (x); | |
1156 | ||
1157 | if (trick_no > 2) | |
1158 | out_operands[2] = GEN_INT (y); | |
1159 | ||
4816b8e4 | 1160 | /* Select dst format based on mode. */ |
8f90be4c NC |
1161 | if (mode == DImode && (! TARGET_LITTLE_END)) |
1162 | dst_fmt = "%R0"; | |
1163 | else | |
1164 | dst_fmt = "%0"; | |
1165 | ||
1166 | if (x >= 0 && x <= 127) | |
1167 | sprintf (load_op, "movi\t%s,%%1", dst_fmt); | |
4816b8e4 | 1168 | |
8f90be4c NC |
1169 | /* Try exact power of two. */ |
1170 | else if ((x & (x - 1)) == 0) | |
1171 | sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt); | |
4816b8e4 NC |
1172 | |
1173 | /* Try exact power of two - 1. */ | |
8f90be4c NC |
1174 | else if ((x & (x + 1)) == 0) |
1175 | sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt); | |
4816b8e4 | 1176 | |
8f90be4c NC |
1177 | else |
1178 | sprintf (load_op, "BADMOVI\t%s,%%1", dst_fmt); | |
1179 | ||
1180 | switch (trick_no) | |
1181 | { | |
1182 | case 1: | |
1183 | strcpy (buf, load_op); | |
1184 | break; | |
1185 | case 2: /* not */ | |
1186 | sprintf (buf, "%s\n\tnot\t%s\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1187 | break; | |
1188 | case 3: /* add */ | |
1189 | sprintf (buf, "%s\n\taddi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1190 | break; | |
1191 | case 4: /* sub */ | |
1192 | sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1193 | break; | |
1194 | case 5: /* rsub */ | |
4816b8e4 | 1195 | /* Never happens unless -mrsubi, see try_constant_tricks(). */ |
8f90be4c NC |
1196 | sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); |
1197 | break; | |
1198 | case 6: /* bset */ | |
1199 | sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1200 | break; | |
1201 | case 7: /* bclr */ | |
1202 | sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1203 | break; | |
1204 | case 8: /* rotl */ | |
1205 | sprintf (buf, "%s\n\trotli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1206 | break; | |
1207 | case 9: /* lsl */ | |
1208 | sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value); | |
1209 | break; | |
1210 | case 10: /* ixh */ | |
1211 | sprintf (buf, "%s\n\tixh\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value); | |
1212 | break; | |
1213 | case 11: /* ixw */ | |
1214 | sprintf (buf, "%s\n\tixw\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value); | |
1215 | break; | |
1216 | default: | |
1217 | return ""; | |
1218 | } | |
1219 | ||
1220 | output_asm_insn (buf, out_operands); | |
1221 | ||
1222 | return ""; | |
1223 | } | |
1224 | ||
1225 | /* Output a move of a word or less value. */ | |
4816b8e4 | 1226 | |
f27cd94d | 1227 | const char * |
08903e08 SB |
1228 | mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[], |
1229 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
8f90be4c NC |
1230 | { |
1231 | rtx dst = operands[0]; | |
1232 | rtx src = operands[1]; | |
1233 | ||
1234 | if (GET_CODE (dst) == REG) | |
1235 | { | |
1236 | if (GET_CODE (src) == REG) | |
1237 | { | |
1238 | if (REGNO (src) == CC_REG) /* r-c */ | |
1239 | return "mvc\t%0"; | |
1240 | else | |
1241 | return "mov\t%0,%1"; /* r-r*/ | |
1242 | } | |
1243 | else if (GET_CODE (src) == MEM) | |
1244 | { | |
1245 | if (GET_CODE (XEXP (src, 0)) == LABEL_REF) | |
1246 | return "lrw\t%0,[%1]"; /* a-R */ | |
1247 | else | |
f0f4da32 RS |
1248 | switch (GET_MODE (src)) /* r-m */ |
1249 | { | |
1250 | case SImode: | |
1251 | return "ldw\t%0,%1"; | |
1252 | case HImode: | |
1253 | return "ld.h\t%0,%1"; | |
1254 | case QImode: | |
1255 | return "ld.b\t%0,%1"; | |
1256 | default: | |
1257 | abort (); | |
1258 | } | |
8f90be4c NC |
1259 | } |
1260 | else if (GET_CODE (src) == CONST_INT) | |
1261 | { | |
1262 | int x, y; | |
1263 | ||
1264 | if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */ | |
1265 | return "movi\t%0,%1"; | |
1266 | else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */ | |
1267 | return "bgeni\t%0,%P1\t// %1 %x1"; | |
1268 | else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */ | |
1269 | return "bmaski\t%0,%N1\t// %1 %x1"; | |
1270 | else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */ | |
1271 | return output_inline_const (SImode, operands); /* 1-2 insns */ | |
1272 | else | |
4816b8e4 | 1273 | return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */ |
8f90be4c NC |
1274 | } |
1275 | else | |
4816b8e4 | 1276 | return "lrw\t%0, %1"; /* Into the literal pool. */ |
8f90be4c NC |
1277 | } |
1278 | else if (GET_CODE (dst) == MEM) /* m-r */ | |
f0f4da32 RS |
1279 | switch (GET_MODE (dst)) |
1280 | { | |
1281 | case SImode: | |
1282 | return "stw\t%1,%0"; | |
1283 | case HImode: | |
1284 | return "st.h\t%1,%0"; | |
1285 | case QImode: | |
1286 | return "st.b\t%1,%0"; | |
1287 | default: | |
1288 | abort (); | |
1289 | } | |
8f90be4c NC |
1290 | |
1291 | abort (); | |
1292 | } | |
1293 | ||
8f90be4c NC |
1294 | /* Return a sequence of instructions to perform DI or DF move. |
1295 | Since the MCORE cannot move a DI or DF in one instruction, we have | |
1296 | to take care when we see overlapping source and dest registers. */ | |
4816b8e4 | 1297 | |
f27cd94d | 1298 | const char * |
08903e08 | 1299 | mcore_output_movedouble (rtx operands[], enum machine_mode mode ATTRIBUTE_UNUSED) |
8f90be4c NC |
1300 | { |
1301 | rtx dst = operands[0]; | |
1302 | rtx src = operands[1]; | |
1303 | ||
1304 | if (GET_CODE (dst) == REG) | |
1305 | { | |
1306 | if (GET_CODE (src) == REG) | |
1307 | { | |
1308 | int dstreg = REGNO (dst); | |
1309 | int srcreg = REGNO (src); | |
4816b8e4 | 1310 | |
8f90be4c NC |
1311 | /* Ensure the second source not overwritten. */ |
1312 | if (srcreg + 1 == dstreg) | |
1313 | return "mov %R0,%R1\n\tmov %0,%1"; | |
1314 | else | |
1315 | return "mov %0,%1\n\tmov %R0,%R1"; | |
1316 | } | |
1317 | else if (GET_CODE (src) == MEM) | |
1318 | { | |
1319 | rtx memexp = memexp = XEXP (src, 0); | |
1320 | int dstreg = REGNO (dst); | |
1321 | int basereg = -1; | |
1322 | ||
1323 | if (GET_CODE (memexp) == LABEL_REF) | |
1324 | return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]"; | |
1325 | else if (GET_CODE (memexp) == REG) | |
1326 | basereg = REGNO (memexp); | |
1327 | else if (GET_CODE (memexp) == PLUS) | |
1328 | { | |
1329 | if (GET_CODE (XEXP (memexp, 0)) == REG) | |
1330 | basereg = REGNO (XEXP (memexp, 0)); | |
1331 | else if (GET_CODE (XEXP (memexp, 1)) == REG) | |
1332 | basereg = REGNO (XEXP (memexp, 1)); | |
1333 | else | |
1334 | abort (); | |
1335 | } | |
1336 | else | |
1337 | abort (); | |
1338 | ||
4816b8e4 | 1339 | /* ??? length attribute is wrong here. */ |
8f90be4c NC |
1340 | if (dstreg == basereg) |
1341 | { | |
4816b8e4 | 1342 | /* Just load them in reverse order. */ |
8f90be4c | 1343 | return "ldw\t%R0,%R1\n\tldw\t%0,%1"; |
4816b8e4 | 1344 | |
8f90be4c | 1345 | /* XXX: alternative: move basereg to basereg+1 |
4816b8e4 | 1346 | and then fall through. */ |
8f90be4c NC |
1347 | } |
1348 | else | |
1349 | return "ldw\t%0,%1\n\tldw\t%R0,%R1"; | |
1350 | } | |
1351 | else if (GET_CODE (src) == CONST_INT) | |
1352 | { | |
1353 | if (TARGET_LITTLE_END) | |
1354 | { | |
1355 | if (CONST_OK_FOR_I (INTVAL (src))) | |
1356 | output_asm_insn ("movi %0,%1", operands); | |
1357 | else if (CONST_OK_FOR_M (INTVAL (src))) | |
1358 | output_asm_insn ("bgeni %0,%P1", operands); | |
1359 | else if (INTVAL (src) == -1) | |
1360 | output_asm_insn ("bmaski %0,32", operands); | |
1361 | else if (CONST_OK_FOR_N (INTVAL (src))) | |
1362 | output_asm_insn ("bmaski %0,%N1", operands); | |
1363 | else | |
1364 | abort (); | |
1365 | ||
1366 | if (INTVAL (src) < 0) | |
1367 | return "bmaski %R0,32"; | |
1368 | else | |
1369 | return "movi %R0,0"; | |
1370 | } | |
1371 | else | |
1372 | { | |
1373 | if (CONST_OK_FOR_I (INTVAL (src))) | |
1374 | output_asm_insn ("movi %R0,%1", operands); | |
1375 | else if (CONST_OK_FOR_M (INTVAL (src))) | |
1376 | output_asm_insn ("bgeni %R0,%P1", operands); | |
1377 | else if (INTVAL (src) == -1) | |
1378 | output_asm_insn ("bmaski %R0,32", operands); | |
1379 | else if (CONST_OK_FOR_N (INTVAL (src))) | |
1380 | output_asm_insn ("bmaski %R0,%N1", operands); | |
1381 | else | |
1382 | abort (); | |
1383 | ||
1384 | if (INTVAL (src) < 0) | |
1385 | return "bmaski %0,32"; | |
1386 | else | |
1387 | return "movi %0,0"; | |
1388 | } | |
1389 | } | |
1390 | else | |
1391 | abort (); | |
1392 | } | |
1393 | else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG) | |
1394 | return "stw\t%1,%0\n\tstw\t%R1,%R0"; | |
1395 | else | |
1396 | abort (); | |
1397 | } | |
1398 | ||
1399 | /* Predicates used by the templates. */ | |
1400 | ||
88cad84b | 1401 | /* Nonzero if OP can be source of a simple move operation. */ |
4816b8e4 | 1402 | |
8f90be4c | 1403 | int |
08903e08 | 1404 | mcore_general_movsrc_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1405 | { |
1406 | /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */ | |
1407 | if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1408 | return 1; | |
1409 | ||
1410 | return general_operand (op, mode); | |
1411 | } | |
1412 | ||
14bc6742 | 1413 | /* Nonzero if OP can be destination of a simple move operation. */ |
4816b8e4 | 1414 | |
8f90be4c | 1415 | int |
08903e08 | 1416 | mcore_general_movdst_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1417 | { |
1418 | if (GET_CODE (op) == REG && REGNO (op) == CC_REG) | |
1419 | return 0; | |
1420 | ||
1421 | return general_operand (op, mode); | |
1422 | } | |
1423 | ||
1424 | /* Nonzero if OP is a normal arithmetic register. */ | |
4816b8e4 | 1425 | |
8f90be4c | 1426 | int |
08903e08 | 1427 | mcore_arith_reg_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1428 | { |
1429 | if (! register_operand (op, mode)) | |
1430 | return 0; | |
1431 | ||
1432 | if (GET_CODE (op) == SUBREG) | |
1433 | op = SUBREG_REG (op); | |
1434 | ||
1435 | if (GET_CODE (op) == REG) | |
1436 | return REGNO (op) != CC_REG; | |
1437 | ||
1438 | return 1; | |
1439 | } | |
1440 | ||
88cad84b | 1441 | /* Nonzero if OP should be recognized during reload for an ixh/ixw |
8f90be4c | 1442 | operand. See the ixh/ixw patterns. */ |
4816b8e4 | 1443 | |
8f90be4c | 1444 | int |
08903e08 | 1445 | mcore_reload_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1446 | { |
1447 | if (mcore_arith_reg_operand (op, mode)) | |
1448 | return 1; | |
1449 | ||
1450 | if (! reload_in_progress) | |
1451 | return 0; | |
1452 | ||
1453 | return GET_CODE (op) == MEM; | |
1454 | } | |
1455 | ||
1456 | /* Nonzero if OP is a valid source operand for an arithmetic insn. */ | |
4816b8e4 | 1457 | |
8f90be4c | 1458 | int |
08903e08 | 1459 | mcore_arith_J_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1460 | { |
1461 | if (register_operand (op, mode)) | |
1462 | return 1; | |
1463 | ||
1464 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op))) | |
1465 | return 1; | |
1466 | ||
1467 | return 0; | |
1468 | } | |
1469 | ||
1470 | /* Nonzero if OP is a valid source operand for an arithmetic insn. */ | |
4816b8e4 | 1471 | |
8f90be4c | 1472 | int |
08903e08 | 1473 | mcore_arith_K_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1474 | { |
1475 | if (register_operand (op, mode)) | |
1476 | return 1; | |
1477 | ||
1478 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))) | |
1479 | return 1; | |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | /* Nonzero if OP is a valid source operand for a shift or rotate insn. */ | |
4816b8e4 | 1485 | |
8f90be4c | 1486 | int |
08903e08 | 1487 | mcore_arith_K_operand_not_0 (rtx op, enum machine_mode mode) |
8f90be4c NC |
1488 | { |
1489 | if (register_operand (op, mode)) | |
1490 | return 1; | |
1491 | ||
1492 | if ( GET_CODE (op) == CONST_INT | |
1493 | && CONST_OK_FOR_K (INTVAL (op)) | |
1494 | && INTVAL (op) != 0) | |
1495 | return 1; | |
1496 | ||
1497 | return 0; | |
1498 | } | |
1499 | ||
1500 | int | |
08903e08 | 1501 | mcore_arith_K_S_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1502 | { |
1503 | if (register_operand (op, mode)) | |
1504 | return 1; | |
1505 | ||
1506 | if (GET_CODE (op) == CONST_INT) | |
1507 | { | |
1508 | if (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_M (~INTVAL (op))) | |
1509 | return 1; | |
1510 | } | |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | int | |
08903e08 | 1516 | mcore_arith_S_operand (rtx op) |
8f90be4c NC |
1517 | { |
1518 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op))) | |
1519 | return 1; | |
1520 | ||
1521 | return 0; | |
1522 | } | |
1523 | ||
1524 | int | |
08903e08 | 1525 | mcore_arith_M_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1526 | { |
1527 | if (register_operand (op, mode)) | |
1528 | return 1; | |
1529 | ||
1530 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op))) | |
1531 | return 1; | |
1532 | ||
1533 | return 0; | |
1534 | } | |
1535 | ||
4816b8e4 NC |
1536 | /* Nonzero if OP is a valid source operand for loading. */ |
1537 | ||
8f90be4c | 1538 | int |
08903e08 | 1539 | mcore_arith_imm_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1540 | { |
1541 | if (register_operand (op, mode)) | |
1542 | return 1; | |
1543 | ||
1544 | if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op))) | |
1545 | return 1; | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | int | |
08903e08 | 1551 | mcore_arith_any_imm_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1552 | { |
1553 | if (register_operand (op, mode)) | |
1554 | return 1; | |
1555 | ||
1556 | if (GET_CODE (op) == CONST_INT) | |
1557 | return 1; | |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | ||
4816b8e4 NC |
1562 | /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */ |
1563 | ||
8f90be4c | 1564 | int |
08903e08 | 1565 | mcore_arith_O_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1566 | { |
1567 | if (register_operand (op, mode)) | |
1568 | return 1; | |
1569 | ||
1570 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op))) | |
1571 | return 1; | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | /* Nonzero if OP is a valid source operand for a btsti. */ | |
4816b8e4 | 1577 | |
8f90be4c | 1578 | int |
08903e08 | 1579 | mcore_literal_K_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8f90be4c NC |
1580 | { |
1581 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))) | |
1582 | return 1; | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | /* Nonzero if OP is a valid source operand for an add/sub insn. */ | |
4816b8e4 | 1588 | |
8f90be4c | 1589 | int |
08903e08 | 1590 | mcore_addsub_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1591 | { |
1592 | if (register_operand (op, mode)) | |
1593 | return 1; | |
1594 | ||
1595 | if (GET_CODE (op) == CONST_INT) | |
1596 | { | |
1597 | return 1; | |
1598 | ||
1599 | /* The following is removed because it precludes large constants from being | |
1600 | returned as valid source operands for and add/sub insn. While large | |
1601 | constants may not directly be used in an add/sub, they may if first loaded | |
1602 | into a register. Thus, this predicate should indicate that they are valid, | |
1603 | and the constraint in mcore.md should control whether an additional load to | |
4816b8e4 | 1604 | register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */ |
8f90be4c NC |
1605 | /* |
1606 | if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op))) | |
1607 | return 1; | |
1608 | */ | |
1609 | } | |
1610 | ||
1611 | return 0; | |
1612 | } | |
1613 | ||
1614 | /* Nonzero if OP is a valid source operand for a compare operation. */ | |
4816b8e4 | 1615 | |
8f90be4c | 1616 | int |
08903e08 | 1617 | mcore_compare_operand (rtx op, enum machine_mode mode) |
8f90be4c NC |
1618 | { |
1619 | if (register_operand (op, mode)) | |
1620 | return 1; | |
1621 | ||
1622 | if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0) | |
1623 | return 1; | |
1624 | ||
1625 | return 0; | |
1626 | } | |
1627 | ||
4816b8e4 NC |
1628 | /* Expand insert bit field. BRC */ |
1629 | ||
8f90be4c | 1630 | int |
08903e08 | 1631 | mcore_expand_insv (rtx operands[]) |
8f90be4c NC |
1632 | { |
1633 | int width = INTVAL (operands[1]); | |
1634 | int posn = INTVAL (operands[2]); | |
1635 | int mask; | |
1636 | rtx mreg, sreg, ereg; | |
1637 | ||
1638 | /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191) | |
1639 | for width==1 must be removed. Look around line 368. This is something | |
4816b8e4 | 1640 | we really want the md part to do. */ |
8f90be4c NC |
1641 | if (width == 1 && GET_CODE (operands[3]) == CONST_INT) |
1642 | { | |
4816b8e4 NC |
1643 | /* Do directly with bseti or bclri. */ |
1644 | /* RBE: 2/97 consider only low bit of constant. */ | |
8f90be4c NC |
1645 | if ((INTVAL(operands[3])&1) == 0) |
1646 | { | |
1647 | mask = ~(1 << posn); | |
f1c25d3b KH |
1648 | emit_insn (gen_rtx_SET (SImode, operands[0], |
1649 | gen_rtx_AND (SImode, operands[0], GEN_INT (mask)))); | |
8f90be4c NC |
1650 | } |
1651 | else | |
1652 | { | |
1653 | mask = 1 << posn; | |
f1c25d3b KH |
1654 | emit_insn (gen_rtx_SET (SImode, operands[0], |
1655 | gen_rtx_IOR (SImode, operands[0], GEN_INT (mask)))); | |
8f90be4c NC |
1656 | } |
1657 | ||
1658 | return 1; | |
1659 | } | |
1660 | ||
43a88a8c | 1661 | /* Look at some bit-field placements that we aren't interested |
4816b8e4 | 1662 | in handling ourselves, unless specifically directed to do so. */ |
8f90be4c NC |
1663 | if (! TARGET_W_FIELD) |
1664 | return 0; /* Generally, give up about now. */ | |
1665 | ||
1666 | if (width == 8 && posn % 8 == 0) | |
1667 | /* Byte sized and aligned; let caller break it up. */ | |
1668 | return 0; | |
1669 | ||
1670 | if (width == 16 && posn % 16 == 0) | |
1671 | /* Short sized and aligned; let caller break it up. */ | |
1672 | return 0; | |
1673 | ||
1674 | /* The general case - we can do this a little bit better than what the | |
1675 | machine independent part tries. This will get rid of all the subregs | |
1676 | that mess up constant folding in combine when working with relaxed | |
4816b8e4 | 1677 | immediates. */ |
8f90be4c NC |
1678 | |
1679 | /* If setting the entire field, do it directly. */ | |
1680 | if (GET_CODE (operands[3]) == CONST_INT && | |
1681 | INTVAL (operands[3]) == ((1 << width) - 1)) | |
1682 | { | |
1683 | mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn)); | |
f1c25d3b KH |
1684 | emit_insn (gen_rtx_SET (SImode, operands[0], |
1685 | gen_rtx_IOR (SImode, operands[0], mreg))); | |
8f90be4c NC |
1686 | return 1; |
1687 | } | |
1688 | ||
1689 | /* Generate the clear mask. */ | |
1690 | mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn))); | |
1691 | ||
1692 | /* Clear the field, to overlay it later with the source. */ | |
f1c25d3b KH |
1693 | emit_insn (gen_rtx_SET (SImode, operands[0], |
1694 | gen_rtx_AND (SImode, operands[0], mreg))); | |
8f90be4c NC |
1695 | |
1696 | /* If the source is constant 0, we've nothing to add back. */ | |
1697 | if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0) | |
1698 | return 1; | |
1699 | ||
1700 | /* XXX: Should we worry about more games with constant values? | |
1701 | We've covered the high profile: set/clear single-bit and many-bit | |
1702 | fields. How often do we see "arbitrary bit pattern" constants? */ | |
1703 | sreg = copy_to_mode_reg (SImode, operands[3]); | |
1704 | ||
1705 | /* Extract src as same width as dst (needed for signed values). We | |
1706 | always have to do this since we widen everything to SImode. | |
1707 | We don't have to mask if we're shifting this up against the | |
1708 | MSB of the register (e.g., the shift will push out any hi-order | |
4816b8e4 | 1709 | bits. */ |
f27cd94d | 1710 | if (width + posn != (int) GET_MODE_SIZE (SImode)) |
8f90be4c NC |
1711 | { |
1712 | ereg = force_reg (SImode, GEN_INT ((1 << width) - 1)); | |
f1c25d3b KH |
1713 | emit_insn (gen_rtx_SET (SImode, sreg, |
1714 | gen_rtx_AND (SImode, sreg, ereg))); | |
8f90be4c NC |
1715 | } |
1716 | ||
4816b8e4 | 1717 | /* Insert source value in dest. */ |
8f90be4c | 1718 | if (posn != 0) |
f1c25d3b KH |
1719 | emit_insn (gen_rtx_SET (SImode, sreg, |
1720 | gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn)))); | |
8f90be4c | 1721 | |
f1c25d3b KH |
1722 | emit_insn (gen_rtx_SET (SImode, operands[0], |
1723 | gen_rtx_IOR (SImode, operands[0], sreg))); | |
8f90be4c NC |
1724 | |
1725 | return 1; | |
1726 | } | |
1727 | ||
1728 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
1729 | PARALLEL and the first section will be tested. */ | |
08903e08 | 1730 | |
8f90be4c | 1731 | int |
08903e08 | 1732 | mcore_load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8f90be4c NC |
1733 | { |
1734 | int count = XVECLEN (op, 0); | |
1735 | int dest_regno; | |
1736 | rtx src_addr; | |
1737 | int i; | |
1738 | ||
1739 | /* Perform a quick check so we don't blow up below. */ | |
1740 | if (count <= 1 | |
1741 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1742 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
1743 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
1744 | return 0; | |
1745 | ||
1746 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1747 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1748 | ||
1749 | for (i = 1; i < count; i++) | |
1750 | { | |
1751 | rtx elt = XVECEXP (op, 0, i); | |
1752 | ||
1753 | if (GET_CODE (elt) != SET | |
1754 | || GET_CODE (SET_DEST (elt)) != REG | |
1755 | || GET_MODE (SET_DEST (elt)) != SImode | |
f27cd94d NC |
1756 | || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i) |
1757 | || GET_CODE (SET_SRC (elt)) != MEM | |
1758 | || GET_MODE (SET_SRC (elt)) != SImode | |
8f90be4c NC |
1759 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS |
1760 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
1761 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
1762 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
1763 | return 0; | |
1764 | } | |
1765 | ||
1766 | return 1; | |
1767 | } | |
1768 | ||
1769 | /* Similar, but tests for store multiple. */ | |
4816b8e4 | 1770 | |
8f90be4c | 1771 | int |
08903e08 | 1772 | mcore_store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8f90be4c NC |
1773 | { |
1774 | int count = XVECLEN (op, 0); | |
1775 | int src_regno; | |
1776 | rtx dest_addr; | |
1777 | int i; | |
1778 | ||
1779 | /* Perform a quick check so we don't blow up below. */ | |
1780 | if (count <= 1 | |
1781 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1782 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
1783 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
1784 | return 0; | |
1785 | ||
1786 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1787 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1788 | ||
1789 | for (i = 1; i < count; i++) | |
1790 | { | |
1791 | rtx elt = XVECEXP (op, 0, i); | |
1792 | ||
1793 | if (GET_CODE (elt) != SET | |
1794 | || GET_CODE (SET_SRC (elt)) != REG | |
1795 | || GET_MODE (SET_SRC (elt)) != SImode | |
f27cd94d | 1796 | || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i) |
8f90be4c NC |
1797 | || GET_CODE (SET_DEST (elt)) != MEM |
1798 | || GET_MODE (SET_DEST (elt)) != SImode | |
1799 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
1800 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
1801 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
1802 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
1803 | return 0; | |
1804 | } | |
1805 | ||
1806 | return 1; | |
1807 | } | |
1808 | \f | |
1809 | /* ??? Block move stuff stolen from m88k. This code has not been | |
1810 | verified for correctness. */ | |
1811 | ||
1812 | /* Emit code to perform a block move. Choose the best method. | |
1813 | ||
1814 | OPERANDS[0] is the destination. | |
1815 | OPERANDS[1] is the source. | |
1816 | OPERANDS[2] is the size. | |
1817 | OPERANDS[3] is the alignment safe to use. */ | |
1818 | ||
1819 | /* Emit code to perform a block move with an offset sequence of ldw/st | |
1820 | instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are | |
1821 | known constants. DEST and SRC are registers. OFFSET is the known | |
1822 | starting point for the output pattern. */ | |
1823 | ||
8b60264b | 1824 | static const enum machine_mode mode_from_align[] = |
8f90be4c NC |
1825 | { |
1826 | VOIDmode, QImode, HImode, VOIDmode, SImode, | |
1827 | VOIDmode, VOIDmode, VOIDmode, DImode | |
1828 | }; | |
1829 | ||
1830 | static void | |
08903e08 SB |
1831 | block_move_sequence (rtx dest, rtx dst_mem, rtx src, rtx src_mem, |
1832 | int size, int align, int offset) | |
8f90be4c NC |
1833 | { |
1834 | rtx temp[2]; | |
1835 | enum machine_mode mode[2]; | |
1836 | int amount[2]; | |
1837 | int active[2]; | |
1838 | int phase = 0; | |
1839 | int next; | |
1840 | int offset_ld = offset; | |
1841 | int offset_st = offset; | |
1842 | ||
1843 | active[0] = active[1] = FALSE; | |
1844 | ||
1845 | /* Establish parameters for the first load and for the second load if | |
1846 | it is known to be the same mode as the first. */ | |
1847 | amount[0] = amount[1] = align; | |
1848 | ||
1849 | mode[0] = mode_from_align[align]; | |
1850 | ||
1851 | temp[0] = gen_reg_rtx (mode[0]); | |
1852 | ||
1853 | if (size >= 2 * align) | |
1854 | { | |
1855 | mode[1] = mode[0]; | |
1856 | temp[1] = gen_reg_rtx (mode[1]); | |
1857 | } | |
1858 | ||
1859 | do | |
1860 | { | |
1861 | rtx srcp, dstp; | |
1862 | ||
1863 | next = phase; | |
1864 | phase = !phase; | |
1865 | ||
1866 | if (size > 0) | |
1867 | { | |
1868 | /* Change modes as the sequence tails off. */ | |
1869 | if (size < amount[next]) | |
1870 | { | |
1871 | amount[next] = (size >= 4 ? 4 : (size >= 2 ? 2 : 1)); | |
1872 | mode[next] = mode_from_align[amount[next]]; | |
1873 | temp[next] = gen_reg_rtx (mode[next]); | |
1874 | } | |
1875 | ||
1876 | size -= amount[next]; | |
f1c25d3b | 1877 | srcp = gen_rtx_MEM ( |
8f90be4c NC |
1878 | #if 0 |
1879 | MEM_IN_STRUCT_P (src_mem) ? mode[next] : BLKmode, | |
1880 | #else | |
1881 | mode[next], | |
1882 | #endif | |
67245ad3 | 1883 | gen_rtx_PLUS (Pmode, src, GEN_INT (offset_ld))); |
8f90be4c | 1884 | |
389fdba0 | 1885 | MEM_READONLY_P (srcp) = MEM_READONLY_P (src_mem); |
8f90be4c NC |
1886 | MEM_VOLATILE_P (srcp) = MEM_VOLATILE_P (src_mem); |
1887 | MEM_IN_STRUCT_P (srcp) = 1; | |
f1c25d3b | 1888 | emit_insn (gen_rtx_SET (VOIDmode, temp[next], srcp)); |
8f90be4c NC |
1889 | offset_ld += amount[next]; |
1890 | active[next] = TRUE; | |
1891 | } | |
1892 | ||
1893 | if (active[phase]) | |
1894 | { | |
1895 | active[phase] = FALSE; | |
1896 | ||
f1c25d3b | 1897 | dstp = gen_rtx_MEM ( |
8f90be4c NC |
1898 | #if 0 |
1899 | MEM_IN_STRUCT_P (dst_mem) ? mode[phase] : BLKmode, | |
1900 | #else | |
1901 | mode[phase], | |
1902 | #endif | |
67245ad3 | 1903 | gen_rtx_PLUS (Pmode, dest, GEN_INT (offset_st))); |
8f90be4c | 1904 | |
389fdba0 | 1905 | MEM_READONLY_P (dstp) = MEM_READONLY_P (dst_mem); |
8f90be4c NC |
1906 | MEM_VOLATILE_P (dstp) = MEM_VOLATILE_P (dst_mem); |
1907 | MEM_IN_STRUCT_P (dstp) = 1; | |
f1c25d3b | 1908 | emit_insn (gen_rtx_SET (VOIDmode, dstp, temp[phase])); |
8f90be4c NC |
1909 | offset_st += amount[phase]; |
1910 | } | |
1911 | } | |
1912 | while (active[next]); | |
1913 | } | |
1914 | ||
1915 | void | |
08903e08 | 1916 | mcore_expand_block_move (rtx dst_mem, rtx src_mem, rtx * operands) |
8f90be4c NC |
1917 | { |
1918 | int align = INTVAL (operands[3]); | |
1919 | int bytes; | |
1920 | ||
1921 | if (GET_CODE (operands[2]) == CONST_INT) | |
1922 | { | |
1923 | bytes = INTVAL (operands[2]); | |
1924 | ||
1925 | if (bytes <= 0) | |
1926 | return; | |
1927 | if (align > 4) | |
1928 | align = 4; | |
1929 | ||
1930 | /* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before | |
4816b8e4 | 1931 | we give up and go to memcpy. */ |
8f90be4c NC |
1932 | if ((align == 4 && (bytes <= 4*4 |
1933 | || ((bytes & 01) == 0 && bytes <= 8*4) | |
1934 | || ((bytes & 03) == 0 && bytes <= 16*4))) | |
1935 | || (align == 2 && bytes <= 4*2) | |
1936 | || (align == 1 && bytes <= 4*1)) | |
1937 | { | |
1938 | block_move_sequence (operands[0], dst_mem, operands[1], src_mem, | |
1939 | bytes, align, 0); | |
1940 | return; | |
1941 | } | |
1942 | } | |
1943 | ||
1944 | /* If we get here, just use the library routine. */ | |
f1c25d3b | 1945 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0, VOIDmode, 3, |
8f90be4c NC |
1946 | operands[0], Pmode, operands[1], Pmode, operands[2], |
1947 | SImode); | |
1948 | } | |
1949 | \f | |
1950 | ||
1951 | /* Code to generate prologue and epilogue sequences. */ | |
1952 | static int number_of_regs_before_varargs; | |
4816b8e4 | 1953 | |
bd5bd7ac | 1954 | /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is |
8f90be4c NC |
1955 | for a varargs function. */ |
1956 | static int current_function_anonymous_args; | |
1957 | ||
8f90be4c NC |
1958 | #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT) |
1959 | #define STORE_REACH (64) /* Maximum displace of word store + 4. */ | |
4816b8e4 | 1960 | #define ADDI_REACH (32) /* Maximum addi operand. */ |
8f90be4c | 1961 | |
8f90be4c | 1962 | static void |
08903e08 | 1963 | layout_mcore_frame (struct mcore_frame * infp) |
8f90be4c NC |
1964 | { |
1965 | int n; | |
1966 | unsigned int i; | |
1967 | int nbytes; | |
1968 | int regarg; | |
1969 | int localregarg; | |
1970 | int localreg; | |
1971 | int outbounds; | |
1972 | unsigned int growths; | |
1973 | int step; | |
1974 | ||
1975 | /* Might have to spill bytes to re-assemble a big argument that | |
4816b8e4 | 1976 | was passed partially in registers and partially on the stack. */ |
8f90be4c NC |
1977 | nbytes = current_function_pretend_args_size; |
1978 | ||
1979 | /* Determine how much space for spilled anonymous args (e.g., stdarg). */ | |
1980 | if (current_function_anonymous_args) | |
1981 | nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD; | |
1982 | ||
1983 | infp->arg_size = nbytes; | |
1984 | ||
1985 | /* How much space to save non-volatile registers we stomp. */ | |
1986 | infp->reg_mask = calc_live_regs (& n); | |
1987 | infp->reg_size = n * 4; | |
1988 | ||
14bc6742 | 1989 | /* And the rest of it... locals and space for overflowed outbounds. */ |
8f90be4c NC |
1990 | infp->local_size = get_frame_size (); |
1991 | infp->outbound_size = current_function_outgoing_args_size; | |
1992 | ||
1993 | /* Make sure we have a whole number of words for the locals. */ | |
1994 | if (infp->local_size % STACK_BYTES) | |
1995 | infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1); | |
1996 | ||
1997 | /* Only thing we know we have to pad is the outbound space, since | |
1998 | we've aligned our locals assuming that base of locals is aligned. */ | |
1999 | infp->pad_local = 0; | |
2000 | infp->pad_reg = 0; | |
2001 | infp->pad_outbound = 0; | |
2002 | if (infp->outbound_size % STACK_BYTES) | |
2003 | infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES); | |
2004 | ||
2005 | /* Now we see how we want to stage the prologue so that it does | |
2006 | the most appropriate stack growth and register saves to either: | |
2007 | (1) run fast, | |
2008 | (2) reduce instruction space, or | |
2009 | (3) reduce stack space. */ | |
b6a1cbae | 2010 | for (i = 0; i < ARRAY_SIZE (infp->growth); i++) |
8f90be4c NC |
2011 | infp->growth[i] = 0; |
2012 | ||
2013 | regarg = infp->reg_size + infp->arg_size; | |
2014 | localregarg = infp->local_size + regarg; | |
2015 | localreg = infp->local_size + infp->reg_size; | |
2016 | outbounds = infp->outbound_size + infp->pad_outbound; | |
2017 | growths = 0; | |
2018 | ||
2019 | /* XXX: Consider one where we consider localregarg + outbound too! */ | |
2020 | ||
2021 | /* Frame of <= 32 bytes and using stm would get <= 2 registers. | |
2022 | use stw's with offsets and buy the frame in one shot. */ | |
2023 | if (localregarg <= ADDI_REACH | |
2024 | && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000)) | |
2025 | { | |
2026 | /* Make sure we'll be aligned. */ | |
2027 | if (localregarg % STACK_BYTES) | |
2028 | infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES); | |
2029 | ||
2030 | step = localregarg + infp->pad_reg; | |
2031 | infp->reg_offset = infp->local_size; | |
2032 | ||
2033 | if (outbounds + step <= ADDI_REACH && !frame_pointer_needed) | |
2034 | { | |
2035 | step += outbounds; | |
2036 | infp->reg_offset += outbounds; | |
2037 | outbounds = 0; | |
2038 | } | |
2039 | ||
2040 | infp->arg_offset = step - 4; | |
2041 | infp->growth[growths++] = step; | |
2042 | infp->reg_growth = growths; | |
2043 | infp->local_growth = growths; | |
2044 | ||
4816b8e4 | 2045 | /* If we haven't already folded it in. */ |
8f90be4c NC |
2046 | if (outbounds) |
2047 | infp->growth[growths++] = outbounds; | |
2048 | ||
2049 | goto finish; | |
2050 | } | |
2051 | ||
2052 | /* Frame can't be done with a single subi, but can be done with 2 | |
2053 | insns. If the 'stm' is getting <= 2 registers, we use stw's and | |
2054 | shift some of the stack purchase into the first subi, so both are | |
2055 | single instructions. */ | |
2056 | if (localregarg <= STORE_REACH | |
2057 | && (infp->local_size > ADDI_REACH) | |
2058 | && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000)) | |
2059 | { | |
2060 | int all; | |
2061 | ||
2062 | /* Make sure we'll be aligned; use either pad_reg or pad_local. */ | |
2063 | if (localregarg % STACK_BYTES) | |
2064 | infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES); | |
2065 | ||
2066 | all = localregarg + infp->pad_reg + infp->pad_local; | |
2067 | step = ADDI_REACH; /* As much up front as we can. */ | |
2068 | if (step > all) | |
2069 | step = all; | |
2070 | ||
2071 | /* XXX: Consider whether step will still be aligned; we believe so. */ | |
2072 | infp->arg_offset = step - 4; | |
2073 | infp->growth[growths++] = step; | |
2074 | infp->reg_growth = growths; | |
2075 | infp->reg_offset = step - infp->pad_reg - infp->reg_size; | |
2076 | all -= step; | |
2077 | ||
4816b8e4 | 2078 | /* Can we fold in any space required for outbounds? */ |
8f90be4c NC |
2079 | if (outbounds + all <= ADDI_REACH && !frame_pointer_needed) |
2080 | { | |
2081 | all += outbounds; | |
2082 | outbounds = 0; | |
2083 | } | |
2084 | ||
4816b8e4 | 2085 | /* Get the rest of the locals in place. */ |
8f90be4c NC |
2086 | step = all; |
2087 | infp->growth[growths++] = step; | |
2088 | infp->local_growth = growths; | |
2089 | all -= step; | |
2090 | ||
2091 | assert (all == 0); | |
2092 | ||
4816b8e4 | 2093 | /* Finish off if we need to do so. */ |
8f90be4c NC |
2094 | if (outbounds) |
2095 | infp->growth[growths++] = outbounds; | |
2096 | ||
2097 | goto finish; | |
2098 | } | |
2099 | ||
2100 | /* Registers + args is nicely aligned, so we'll buy that in one shot. | |
2101 | Then we buy the rest of the frame in 1 or 2 steps depending on | |
2102 | whether we need a frame pointer. */ | |
2103 | if ((regarg % STACK_BYTES) == 0) | |
2104 | { | |
2105 | infp->growth[growths++] = regarg; | |
2106 | infp->reg_growth = growths; | |
2107 | infp->arg_offset = regarg - 4; | |
2108 | infp->reg_offset = 0; | |
2109 | ||
2110 | if (infp->local_size % STACK_BYTES) | |
2111 | infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES); | |
2112 | ||
2113 | step = infp->local_size + infp->pad_local; | |
2114 | ||
2115 | if (!frame_pointer_needed) | |
2116 | { | |
2117 | step += outbounds; | |
2118 | outbounds = 0; | |
2119 | } | |
2120 | ||
2121 | infp->growth[growths++] = step; | |
2122 | infp->local_growth = growths; | |
2123 | ||
4816b8e4 | 2124 | /* If there's any left to be done. */ |
8f90be4c NC |
2125 | if (outbounds) |
2126 | infp->growth[growths++] = outbounds; | |
2127 | ||
2128 | goto finish; | |
2129 | } | |
2130 | ||
2131 | /* XXX: optimizations that we'll want to play with.... | |
4816b8e4 NC |
2132 | -- regarg is not aligned, but it's a small number of registers; |
2133 | use some of localsize so that regarg is aligned and then | |
2134 | save the registers. */ | |
8f90be4c NC |
2135 | |
2136 | /* Simple encoding; plods down the stack buying the pieces as it goes. | |
4816b8e4 NC |
2137 | -- does not optimize space consumption. |
2138 | -- does not attempt to optimize instruction counts. | |
2139 | -- but it is safe for all alignments. */ | |
8f90be4c NC |
2140 | if (regarg % STACK_BYTES != 0) |
2141 | infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES); | |
2142 | ||
2143 | infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg; | |
2144 | infp->reg_growth = growths; | |
2145 | infp->arg_offset = infp->growth[0] - 4; | |
2146 | infp->reg_offset = 0; | |
2147 | ||
2148 | if (frame_pointer_needed) | |
2149 | { | |
2150 | if (infp->local_size % STACK_BYTES != 0) | |
2151 | infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES); | |
2152 | ||
2153 | infp->growth[growths++] = infp->local_size + infp->pad_local; | |
2154 | infp->local_growth = growths; | |
2155 | ||
2156 | infp->growth[growths++] = outbounds; | |
2157 | } | |
2158 | else | |
2159 | { | |
2160 | if ((infp->local_size + outbounds) % STACK_BYTES != 0) | |
2161 | infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES); | |
2162 | ||
2163 | infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds; | |
2164 | infp->local_growth = growths; | |
2165 | } | |
2166 | ||
f27cd94d | 2167 | /* Anything else that we've forgotten?, plus a few consistency checks. */ |
8f90be4c NC |
2168 | finish: |
2169 | assert (infp->reg_offset >= 0); | |
2170 | assert (growths <= MAX_STACK_GROWS); | |
2171 | ||
2172 | for (i = 0; i < growths; i++) | |
2173 | { | |
2174 | if (infp->growth[i] % STACK_BYTES) | |
2175 | { | |
2176 | fprintf (stderr,"stack growth of %d is not %d aligned\n", | |
2177 | infp->growth[i], STACK_BYTES); | |
2178 | abort (); | |
2179 | } | |
2180 | } | |
2181 | } | |
2182 | ||
2183 | /* Define the offset between two registers, one to be eliminated, and | |
2184 | the other its replacement, at the start of a routine. */ | |
4816b8e4 | 2185 | |
8f90be4c | 2186 | int |
08903e08 | 2187 | mcore_initial_elimination_offset (int from, int to) |
8f90be4c NC |
2188 | { |
2189 | int above_frame; | |
2190 | int below_frame; | |
2191 | struct mcore_frame fi; | |
2192 | ||
2193 | layout_mcore_frame (& fi); | |
2194 | ||
2195 | /* fp to ap */ | |
2196 | above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg; | |
2197 | /* sp to fp */ | |
2198 | below_frame = fi.outbound_size + fi.pad_outbound; | |
2199 | ||
2200 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
2201 | return above_frame; | |
2202 | ||
2203 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
2204 | return above_frame + below_frame; | |
2205 | ||
2206 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
2207 | return below_frame; | |
2208 | ||
2209 | abort (); | |
2210 | ||
2211 | return 0; | |
2212 | } | |
2213 | ||
4816b8e4 NC |
2214 | /* Keep track of some information about varargs for the prolog. */ |
2215 | ||
09a2b93a KH |
2216 | static void |
2217 | mcore_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_far, | |
08903e08 | 2218 | enum machine_mode mode, tree type, |
09a2b93a KH |
2219 | int * ptr_pretend_size ATTRIBUTE_UNUSED, |
2220 | int second_time ATTRIBUTE_UNUSED) | |
8f90be4c NC |
2221 | { |
2222 | current_function_anonymous_args = 1; | |
2223 | ||
2224 | /* We need to know how many argument registers are used before | |
2225 | the varargs start, so that we can push the remaining argument | |
2226 | registers during the prologue. */ | |
09a2b93a | 2227 | number_of_regs_before_varargs = *args_so_far + mcore_num_arg_regs (mode, type); |
8f90be4c | 2228 | |
dab66575 | 2229 | /* There is a bug somewhere in the arg handling code. |
8f90be4c NC |
2230 | Until I can find it this workaround always pushes the |
2231 | last named argument onto the stack. */ | |
09a2b93a | 2232 | number_of_regs_before_varargs = *args_so_far; |
8f90be4c NC |
2233 | |
2234 | /* The last named argument may be split between argument registers | |
2235 | and the stack. Allow for this here. */ | |
2236 | if (number_of_regs_before_varargs > NPARM_REGS) | |
2237 | number_of_regs_before_varargs = NPARM_REGS; | |
2238 | } | |
2239 | ||
2240 | void | |
08903e08 | 2241 | mcore_expand_prolog (void) |
8f90be4c NC |
2242 | { |
2243 | struct mcore_frame fi; | |
2244 | int space_allocated = 0; | |
2245 | int growth = 0; | |
2246 | ||
2247 | /* Find out what we're doing. */ | |
2248 | layout_mcore_frame (&fi); | |
2249 | ||
2250 | space_allocated = fi.arg_size + fi.reg_size + fi.local_size + | |
2251 | fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg; | |
2252 | ||
2253 | if (TARGET_CG_DATA) | |
2254 | { | |
2255 | /* Emit a symbol for this routine's frame size. */ | |
2256 | rtx x; | |
8f90be4c NC |
2257 | |
2258 | x = DECL_RTL (current_function_decl); | |
2259 | ||
2260 | if (GET_CODE (x) != MEM) | |
2261 | abort (); | |
2262 | ||
2263 | x = XEXP (x, 0); | |
2264 | ||
2265 | if (GET_CODE (x) != SYMBOL_REF) | |
2266 | abort (); | |
2267 | ||
2268 | if (mcore_current_function_name) | |
2269 | free (mcore_current_function_name); | |
2270 | ||
1dcd444b | 2271 | mcore_current_function_name = xstrdup (XSTR (x, 0)); |
8f90be4c NC |
2272 | |
2273 | ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated); | |
2274 | ||
2275 | if (current_function_calls_alloca) | |
2276 | ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1); | |
2277 | ||
2278 | /* 970425: RBE: | |
2279 | We're looking at how the 8byte alignment affects stack layout | |
2280 | and where we had to pad things. This emits information we can | |
2281 | extract which tells us about frame sizes and the like. */ | |
2282 | fprintf (asm_out_file, | |
2283 | "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n", | |
2284 | mcore_current_function_name, | |
2285 | fi.arg_size, fi.reg_size, fi.reg_mask, | |
2286 | fi.local_size, fi.outbound_size, | |
2287 | frame_pointer_needed); | |
2288 | } | |
2289 | ||
2290 | if (mcore_naked_function_p ()) | |
2291 | return; | |
2292 | ||
2293 | /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */ | |
08903e08 | 2294 | output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ |
8f90be4c NC |
2295 | |
2296 | /* If we have a parameter passed partially in regs and partially in memory, | |
2297 | the registers will have been stored to memory already in function.c. So | |
2298 | we only need to do something here for varargs functions. */ | |
2299 | if (fi.arg_size != 0 && current_function_pretend_args_size == 0) | |
2300 | { | |
2301 | int offset; | |
2302 | int rn = FIRST_PARM_REG + NPARM_REGS - 1; | |
2303 | int remaining = fi.arg_size; | |
2304 | ||
2305 | for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4) | |
2306 | { | |
2307 | emit_insn (gen_movsi | |
f1c25d3b | 2308 | (gen_rtx_MEM (SImode, |
8f90be4c | 2309 | plus_constant (stack_pointer_rtx, offset)), |
f1c25d3b | 2310 | gen_rtx_REG (SImode, rn))); |
8f90be4c NC |
2311 | } |
2312 | } | |
2313 | ||
4816b8e4 | 2314 | /* Do we need another stack adjustment before we do the register saves? */ |
8f90be4c | 2315 | if (growth < fi.reg_growth) |
08903e08 | 2316 | output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ |
8f90be4c NC |
2317 | |
2318 | if (fi.reg_size != 0) | |
2319 | { | |
2320 | int i; | |
2321 | int offs = fi.reg_offset; | |
2322 | ||
2323 | for (i = 15; i >= 0; i--) | |
2324 | { | |
2325 | if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000)) | |
2326 | { | |
2327 | int first_reg = 15; | |
2328 | ||
2329 | while (fi.reg_mask & (1 << first_reg)) | |
2330 | first_reg--; | |
2331 | first_reg++; | |
2332 | ||
f1c25d3b KH |
2333 | emit_insn (gen_store_multiple (gen_rtx_MEM (SImode, stack_pointer_rtx), |
2334 | gen_rtx_REG (SImode, first_reg), | |
8f90be4c NC |
2335 | GEN_INT (16 - first_reg))); |
2336 | ||
2337 | i -= (15 - first_reg); | |
2338 | offs += (16 - first_reg) * 4; | |
2339 | } | |
2340 | else if (fi.reg_mask & (1 << i)) | |
2341 | { | |
2342 | emit_insn (gen_movsi | |
f1c25d3b | 2343 | (gen_rtx_MEM (SImode, |
8f90be4c | 2344 | plus_constant (stack_pointer_rtx, offs)), |
f1c25d3b | 2345 | gen_rtx_REG (SImode, i))); |
8f90be4c NC |
2346 | offs += 4; |
2347 | } | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | /* Figure the locals + outbounds. */ | |
2352 | if (frame_pointer_needed) | |
2353 | { | |
2354 | /* If we haven't already purchased to 'fp'. */ | |
2355 | if (growth < fi.local_growth) | |
08903e08 | 2356 | output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ |
8f90be4c NC |
2357 | |
2358 | emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); | |
2359 | ||
4816b8e4 | 2360 | /* ... and then go any remaining distance for outbounds, etc. */ |
8f90be4c NC |
2361 | if (fi.growth[growth]) |
2362 | output_stack_adjust (-1, fi.growth[growth++]); | |
2363 | } | |
2364 | else | |
2365 | { | |
2366 | if (growth < fi.local_growth) | |
08903e08 | 2367 | output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ |
8f90be4c NC |
2368 | if (fi.growth[growth]) |
2369 | output_stack_adjust (-1, fi.growth[growth++]); | |
2370 | } | |
2371 | } | |
2372 | ||
2373 | void | |
08903e08 | 2374 | mcore_expand_epilog (void) |
8f90be4c NC |
2375 | { |
2376 | struct mcore_frame fi; | |
2377 | int i; | |
2378 | int offs; | |
2379 | int growth = MAX_STACK_GROWS - 1 ; | |
2380 | ||
f27cd94d | 2381 | |
8f90be4c NC |
2382 | /* Find out what we're doing. */ |
2383 | layout_mcore_frame(&fi); | |
2384 | ||
2385 | if (mcore_naked_function_p ()) | |
2386 | return; | |
f27cd94d | 2387 | |
8f90be4c NC |
2388 | /* If we had a frame pointer, restore the sp from that. */ |
2389 | if (frame_pointer_needed) | |
2390 | { | |
2391 | emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); | |
2392 | growth = fi.local_growth - 1; | |
2393 | } | |
2394 | else | |
2395 | { | |
2396 | /* XXX: while loop should accumulate and do a single sell. */ | |
2397 | while (growth >= fi.local_growth) | |
2398 | { | |
2399 | if (fi.growth[growth] != 0) | |
2400 | output_stack_adjust (1, fi.growth[growth]); | |
2401 | growth--; | |
2402 | } | |
2403 | } | |
2404 | ||
2405 | /* Make sure we've shrunk stack back to the point where the registers | |
2406 | were laid down. This is typically 0/1 iterations. Then pull the | |
4816b8e4 | 2407 | register save information back off the stack. */ |
8f90be4c NC |
2408 | while (growth >= fi.reg_growth) |
2409 | output_stack_adjust ( 1, fi.growth[growth--]); | |
2410 | ||
2411 | offs = fi.reg_offset; | |
2412 | ||
2413 | for (i = 15; i >= 0; i--) | |
2414 | { | |
2415 | if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000)) | |
2416 | { | |
2417 | int first_reg; | |
2418 | ||
2419 | /* Find the starting register. */ | |
2420 | first_reg = 15; | |
2421 | ||
2422 | while (fi.reg_mask & (1 << first_reg)) | |
2423 | first_reg--; | |
2424 | ||
2425 | first_reg++; | |
2426 | ||
f1c25d3b KH |
2427 | emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg), |
2428 | gen_rtx_MEM (SImode, stack_pointer_rtx), | |
8f90be4c NC |
2429 | GEN_INT (16 - first_reg))); |
2430 | ||
2431 | i -= (15 - first_reg); | |
2432 | offs += (16 - first_reg) * 4; | |
2433 | } | |
2434 | else if (fi.reg_mask & (1 << i)) | |
2435 | { | |
2436 | emit_insn (gen_movsi | |
f1c25d3b KH |
2437 | (gen_rtx_REG (SImode, i), |
2438 | gen_rtx_MEM (SImode, | |
8f90be4c NC |
2439 | plus_constant (stack_pointer_rtx, offs)))); |
2440 | offs += 4; | |
2441 | } | |
2442 | } | |
2443 | ||
2444 | /* Give back anything else. */ | |
dab66575 | 2445 | /* XXX: Should accumulate total and then give it back. */ |
8f90be4c NC |
2446 | while (growth >= 0) |
2447 | output_stack_adjust ( 1, fi.growth[growth--]); | |
2448 | } | |
2449 | \f | |
2450 | /* This code is borrowed from the SH port. */ | |
2451 | ||
2452 | /* The MCORE cannot load a large constant into a register, constants have to | |
2453 | come from a pc relative load. The reference of a pc relative load | |
2454 | instruction must be less than 1k infront of the instruction. This | |
2455 | means that we often have to dump a constant inside a function, and | |
2456 | generate code to branch around it. | |
2457 | ||
2458 | It is important to minimize this, since the branches will slow things | |
2459 | down and make things bigger. | |
2460 | ||
2461 | Worst case code looks like: | |
2462 | ||
2463 | lrw L1,r0 | |
2464 | br L2 | |
2465 | align | |
2466 | L1: .long value | |
2467 | L2: | |
2468 | .. | |
2469 | ||
2470 | lrw L3,r0 | |
2471 | br L4 | |
2472 | align | |
2473 | L3: .long value | |
2474 | L4: | |
2475 | .. | |
2476 | ||
2477 | We fix this by performing a scan before scheduling, which notices which | |
2478 | instructions need to have their operands fetched from the constant table | |
2479 | and builds the table. | |
2480 | ||
2481 | The algorithm is: | |
2482 | ||
2483 | scan, find an instruction which needs a pcrel move. Look forward, find the | |
2484 | last barrier which is within MAX_COUNT bytes of the requirement. | |
2485 | If there isn't one, make one. Process all the instructions between | |
2486 | the find and the barrier. | |
2487 | ||
2488 | In the above example, we can tell that L3 is within 1k of L1, so | |
2489 | the first move can be shrunk from the 2 insn+constant sequence into | |
2490 | just 1 insn, and the constant moved to L3 to make: | |
2491 | ||
2492 | lrw L1,r0 | |
2493 | .. | |
2494 | lrw L3,r0 | |
2495 | bra L4 | |
2496 | align | |
2497 | L3:.long value | |
2498 | L4:.long value | |
2499 | ||
2500 | Then the second move becomes the target for the shortening process. */ | |
2501 | ||
2502 | typedef struct | |
2503 | { | |
2504 | rtx value; /* Value in table. */ | |
2505 | rtx label; /* Label of value. */ | |
2506 | } pool_node; | |
2507 | ||
2508 | /* The maximum number of constants that can fit into one pool, since | |
2509 | the pc relative range is 0...1020 bytes and constants are at least 4 | |
2a43945f | 2510 | bytes long. We subtract 4 from the range to allow for the case where |
8f90be4c NC |
2511 | we need to add a branch/align before the constant pool. */ |
2512 | ||
2513 | #define MAX_COUNT 1016 | |
2514 | #define MAX_POOL_SIZE (MAX_COUNT/4) | |
2515 | static pool_node pool_vector[MAX_POOL_SIZE]; | |
2516 | static int pool_size; | |
2517 | ||
2518 | /* Dump out any constants accumulated in the final pass. These | |
2519 | will only be labels. */ | |
4816b8e4 | 2520 | |
f27cd94d | 2521 | const char * |
08903e08 | 2522 | mcore_output_jump_label_table (void) |
8f90be4c NC |
2523 | { |
2524 | int i; | |
2525 | ||
2526 | if (pool_size) | |
2527 | { | |
2528 | fprintf (asm_out_file, "\t.align 2\n"); | |
2529 | ||
2530 | for (i = 0; i < pool_size; i++) | |
2531 | { | |
2532 | pool_node * p = pool_vector + i; | |
2533 | ||
4977bab6 | 2534 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label)); |
8f90be4c NC |
2535 | |
2536 | output_asm_insn (".long %0", &p->value); | |
2537 | } | |
2538 | ||
2539 | pool_size = 0; | |
2540 | } | |
2541 | ||
2542 | return ""; | |
2543 | } | |
2544 | ||
8f90be4c | 2545 | /* Check whether insn is a candidate for a conditional. */ |
4816b8e4 | 2546 | |
8f90be4c | 2547 | static cond_type |
08903e08 | 2548 | is_cond_candidate (rtx insn) |
8f90be4c NC |
2549 | { |
2550 | /* The only things we conditionalize are those that can be directly | |
2551 | changed into a conditional. Only bother with SImode items. If | |
2552 | we wanted to be a little more aggressive, we could also do other | |
4816b8e4 | 2553 | modes such as DImode with reg-reg move or load 0. */ |
8f90be4c NC |
2554 | if (GET_CODE (insn) == INSN) |
2555 | { | |
2556 | rtx pat = PATTERN (insn); | |
2557 | rtx src, dst; | |
2558 | ||
2559 | if (GET_CODE (pat) != SET) | |
2560 | return COND_NO; | |
2561 | ||
2562 | dst = XEXP (pat, 0); | |
2563 | ||
2564 | if ((GET_CODE (dst) != REG && | |
2565 | GET_CODE (dst) != SUBREG) || | |
2566 | GET_MODE (dst) != SImode) | |
2567 | return COND_NO; | |
2568 | ||
2569 | src = XEXP (pat, 1); | |
2570 | ||
2571 | if ((GET_CODE (src) == REG || | |
2572 | (GET_CODE (src) == SUBREG && | |
2573 | GET_CODE (SUBREG_REG (src)) == REG)) && | |
2574 | GET_MODE (src) == SImode) | |
2575 | return COND_MOV_INSN; | |
2576 | else if (GET_CODE (src) == CONST_INT && | |
2577 | INTVAL (src) == 0) | |
2578 | return COND_CLR_INSN; | |
2579 | else if (GET_CODE (src) == PLUS && | |
2580 | (GET_CODE (XEXP (src, 0)) == REG || | |
2581 | (GET_CODE (XEXP (src, 0)) == SUBREG && | |
2582 | GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) && | |
2583 | GET_MODE (XEXP (src, 0)) == SImode && | |
2584 | GET_CODE (XEXP (src, 1)) == CONST_INT && | |
2585 | INTVAL (XEXP (src, 1)) == 1) | |
2586 | return COND_INC_INSN; | |
2587 | else if (((GET_CODE (src) == MINUS && | |
2588 | GET_CODE (XEXP (src, 1)) == CONST_INT && | |
2589 | INTVAL( XEXP (src, 1)) == 1) || | |
2590 | (GET_CODE (src) == PLUS && | |
2591 | GET_CODE (XEXP (src, 1)) == CONST_INT && | |
2592 | INTVAL (XEXP (src, 1)) == -1)) && | |
2593 | (GET_CODE (XEXP (src, 0)) == REG || | |
2594 | (GET_CODE (XEXP (src, 0)) == SUBREG && | |
2595 | GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) && | |
2596 | GET_MODE (XEXP (src, 0)) == SImode) | |
2597 | return COND_DEC_INSN; | |
2598 | ||
14bc6742 | 2599 | /* Some insns that we don't bother with: |
8f90be4c NC |
2600 | (set (rx:DI) (ry:DI)) |
2601 | (set (rx:DI) (const_int 0)) | |
2602 | */ | |
2603 | ||
2604 | } | |
2605 | else if (GET_CODE (insn) == JUMP_INSN && | |
2606 | GET_CODE (PATTERN (insn)) == SET && | |
2607 | GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF) | |
2608 | return COND_BRANCH_INSN; | |
2609 | ||
2610 | return COND_NO; | |
2611 | } | |
2612 | ||
2613 | /* Emit a conditional version of insn and replace the old insn with the | |
2614 | new one. Return the new insn if emitted. */ | |
4816b8e4 | 2615 | |
8f90be4c | 2616 | static rtx |
08903e08 | 2617 | emit_new_cond_insn (rtx insn, int cond) |
8f90be4c NC |
2618 | { |
2619 | rtx c_insn = 0; | |
2620 | rtx pat, dst, src; | |
2621 | cond_type num; | |
2622 | ||
2623 | if ((num = is_cond_candidate (insn)) == COND_NO) | |
2624 | return NULL; | |
2625 | ||
2626 | pat = PATTERN (insn); | |
2627 | ||
2628 | if (GET_CODE (insn) == INSN) | |
2629 | { | |
2630 | dst = SET_DEST (pat); | |
2631 | src = SET_SRC (pat); | |
2632 | } | |
2633 | else | |
cd4c46f3 KG |
2634 | { |
2635 | dst = JUMP_LABEL (insn); | |
2636 | src = NULL_RTX; | |
2637 | } | |
8f90be4c NC |
2638 | |
2639 | switch (num) | |
2640 | { | |
2641 | case COND_MOV_INSN: | |
2642 | case COND_CLR_INSN: | |
2643 | if (cond) | |
2644 | c_insn = gen_movt0 (dst, src, dst); | |
2645 | else | |
2646 | c_insn = gen_movt0 (dst, dst, src); | |
2647 | break; | |
2648 | ||
2649 | case COND_INC_INSN: | |
2650 | if (cond) | |
2651 | c_insn = gen_incscc (dst, dst); | |
2652 | else | |
2653 | c_insn = gen_incscc_false (dst, dst); | |
2654 | break; | |
2655 | ||
2656 | case COND_DEC_INSN: | |
2657 | if (cond) | |
2658 | c_insn = gen_decscc (dst, dst); | |
2659 | else | |
2660 | c_insn = gen_decscc_false (dst, dst); | |
2661 | break; | |
2662 | ||
2663 | case COND_BRANCH_INSN: | |
2664 | if (cond) | |
2665 | c_insn = gen_branch_true (dst); | |
2666 | else | |
2667 | c_insn = gen_branch_false (dst); | |
2668 | break; | |
2669 | ||
2670 | default: | |
2671 | return NULL; | |
2672 | } | |
2673 | ||
2674 | /* Only copy the notes if they exist. */ | |
2675 | if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7) | |
2676 | { | |
2677 | /* We really don't need to bother with the notes and links at this | |
2678 | point, but go ahead and save the notes. This will help is_dead() | |
2679 | when applying peepholes (links don't matter since they are not | |
2680 | used any more beyond this point for the mcore). */ | |
2681 | REG_NOTES (c_insn) = REG_NOTES (insn); | |
2682 | } | |
2683 | ||
2684 | if (num == COND_BRANCH_INSN) | |
2685 | { | |
2686 | /* For jumps, we need to be a little bit careful and emit the new jump | |
2687 | before the old one and to update the use count for the target label. | |
2688 | This way, the barrier following the old (uncond) jump will get | |
2689 | deleted, but the label won't. */ | |
2690 | c_insn = emit_jump_insn_before (c_insn, insn); | |
2691 | ||
2692 | ++ LABEL_NUSES (dst); | |
2693 | ||
2694 | JUMP_LABEL (c_insn) = dst; | |
2695 | } | |
2696 | else | |
2697 | c_insn = emit_insn_after (c_insn, insn); | |
2698 | ||
2699 | delete_insn (insn); | |
2700 | ||
2701 | return c_insn; | |
2702 | } | |
2703 | ||
2704 | /* Attempt to change a basic block into a series of conditional insns. This | |
2705 | works by taking the branch at the end of the 1st block and scanning for the | |
2706 | end of the 2nd block. If all instructions in the 2nd block have cond. | |
2707 | versions and the label at the start of block 3 is the same as the target | |
2708 | from the branch at block 1, then conditionalize all insn in block 2 using | |
2709 | the inverse condition of the branch at block 1. (Note I'm bending the | |
2710 | definition of basic block here.) | |
2711 | ||
2712 | e.g., change: | |
2713 | ||
2714 | bt L2 <-- end of block 1 (delete) | |
2715 | mov r7,r8 | |
2716 | addu r7,1 | |
2717 | br L3 <-- end of block 2 | |
2718 | ||
2719 | L2: ... <-- start of block 3 (NUSES==1) | |
2720 | L3: ... | |
2721 | ||
2722 | to: | |
2723 | ||
2724 | movf r7,r8 | |
2725 | incf r7 | |
2726 | bf L3 | |
2727 | ||
2728 | L3: ... | |
2729 | ||
2730 | we can delete the L2 label if NUSES==1 and re-apply the optimization | |
2731 | starting at the last instruction of block 2. This may allow an entire | |
4816b8e4 | 2732 | if-then-else statement to be conditionalized. BRC */ |
8f90be4c | 2733 | static rtx |
08903e08 | 2734 | conditionalize_block (rtx first) |
8f90be4c NC |
2735 | { |
2736 | rtx insn; | |
2737 | rtx br_pat; | |
2738 | rtx end_blk_1_br = 0; | |
2739 | rtx end_blk_2_insn = 0; | |
2740 | rtx start_blk_3_lab = 0; | |
2741 | int cond; | |
2742 | int br_lab_num; | |
2743 | int blk_size = 0; | |
2744 | ||
2745 | ||
2746 | /* Check that the first insn is a candidate conditional jump. This is | |
2747 | the one that we'll eliminate. If not, advance to the next insn to | |
2748 | try. */ | |
2749 | if (GET_CODE (first) != JUMP_INSN || | |
2750 | GET_CODE (PATTERN (first)) != SET || | |
2751 | GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE) | |
2752 | return NEXT_INSN (first); | |
2753 | ||
2754 | /* Extract some information we need. */ | |
2755 | end_blk_1_br = first; | |
2756 | br_pat = PATTERN (end_blk_1_br); | |
2757 | ||
2758 | /* Complement the condition since we use the reverse cond. for the insns. */ | |
2759 | cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ); | |
2760 | ||
2761 | /* Determine what kind of branch we have. */ | |
2762 | if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF) | |
2763 | { | |
2764 | /* A normal branch, so extract label out of first arm. */ | |
2765 | br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0)); | |
2766 | } | |
2767 | else | |
2768 | { | |
2769 | /* An inverse branch, so extract the label out of the 2nd arm | |
2770 | and complement the condition. */ | |
2771 | cond = (cond == 0); | |
2772 | br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0)); | |
2773 | } | |
2774 | ||
2775 | /* Scan forward for the start of block 2: it must start with a | |
2776 | label and that label must be the same as the branch target | |
2777 | label from block 1. We don't care about whether block 2 actually | |
2778 | ends with a branch or a label (an uncond. branch is | |
2779 | conditionalizable). */ | |
2780 | for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn)) | |
2781 | { | |
2782 | enum rtx_code code; | |
2783 | ||
2784 | code = GET_CODE (insn); | |
2785 | ||
14bc6742 | 2786 | /* Look for the label at the start of block 3. */ |
8f90be4c NC |
2787 | if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num) |
2788 | break; | |
2789 | ||
2790 | /* Skip barriers, notes, and conditionalizable insns. If the | |
2791 | insn is not conditionalizable or makes this optimization fail, | |
2792 | just return the next insn so we can start over from that point. */ | |
2793 | if (code != BARRIER && code != NOTE && !is_cond_candidate (insn)) | |
2794 | return NEXT_INSN (insn); | |
2795 | ||
2796 | /* Remember the last real insn before the label (ie end of block 2). */ | |
2797 | if (code == JUMP_INSN || code == INSN) | |
2798 | { | |
2799 | blk_size ++; | |
2800 | end_blk_2_insn = insn; | |
2801 | } | |
2802 | } | |
2803 | ||
2804 | if (!insn) | |
2805 | return insn; | |
2806 | ||
2807 | /* It is possible for this optimization to slow performance if the blocks | |
2808 | are long. This really depends upon whether the branch is likely taken | |
2809 | or not. If the branch is taken, we slow performance in many cases. But, | |
2810 | if the branch is not taken, we always help performance (for a single | |
2811 | block, but for a double block (i.e. when the optimization is re-applied) | |
2812 | this is not true since the 'right thing' depends on the overall length of | |
2813 | the collapsed block). As a compromise, don't apply this optimization on | |
2814 | blocks larger than size 2 (unlikely for the mcore) when speed is important. | |
2815 | the best threshold depends on the latencies of the instructions (i.e., | |
2816 | the branch penalty). */ | |
2817 | if (optimize > 1 && blk_size > 2) | |
2818 | return insn; | |
2819 | ||
2820 | /* At this point, we've found the start of block 3 and we know that | |
2821 | it is the destination of the branch from block 1. Also, all | |
2822 | instructions in the block 2 are conditionalizable. So, apply the | |
2823 | conditionalization and delete the branch. */ | |
2824 | start_blk_3_lab = insn; | |
2825 | ||
2826 | for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab; | |
2827 | insn = NEXT_INSN (insn)) | |
2828 | { | |
2829 | rtx newinsn; | |
2830 | ||
2831 | if (INSN_DELETED_P (insn)) | |
2832 | continue; | |
2833 | ||
14bc6742 | 2834 | /* Try to form a conditional variant of the instruction and emit it. */ |
8f90be4c NC |
2835 | if ((newinsn = emit_new_cond_insn (insn, cond))) |
2836 | { | |
2837 | if (end_blk_2_insn == insn) | |
2838 | end_blk_2_insn = newinsn; | |
2839 | ||
2840 | insn = newinsn; | |
2841 | } | |
2842 | } | |
2843 | ||
2844 | /* Note whether we will delete the label starting blk 3 when the jump | |
2845 | gets deleted. If so, we want to re-apply this optimization at the | |
2846 | last real instruction right before the label. */ | |
2847 | if (LABEL_NUSES (start_blk_3_lab) == 1) | |
2848 | { | |
2849 | start_blk_3_lab = 0; | |
2850 | } | |
2851 | ||
2852 | /* ??? we probably should redistribute the death notes for this insn, esp. | |
2853 | the death of cc, but it doesn't really matter this late in the game. | |
2854 | The peepholes all use is_dead() which will find the correct death | |
2855 | regardless of whether there is a note. */ | |
2856 | delete_insn (end_blk_1_br); | |
2857 | ||
2858 | if (! start_blk_3_lab) | |
2859 | return end_blk_2_insn; | |
2860 | ||
4816b8e4 | 2861 | /* Return the insn right after the label at the start of block 3. */ |
8f90be4c NC |
2862 | return NEXT_INSN (start_blk_3_lab); |
2863 | } | |
2864 | ||
2865 | /* Apply the conditionalization of blocks optimization. This is the | |
2866 | outer loop that traverses through the insns scanning for a branch | |
2867 | that signifies an opportunity to apply the optimization. Note that | |
2868 | this optimization is applied late. If we could apply it earlier, | |
2869 | say before cse 2, it may expose more optimization opportunities. | |
2870 | but, the pay back probably isn't really worth the effort (we'd have | |
2871 | to update all reg/flow/notes/links/etc to make it work - and stick it | |
4816b8e4 NC |
2872 | in before cse 2). */ |
2873 | ||
8f90be4c | 2874 | static void |
08903e08 | 2875 | conditionalize_optimization (void) |
8f90be4c NC |
2876 | { |
2877 | rtx insn; | |
2878 | ||
18dbd950 | 2879 | for (insn = get_insns (); insn; insn = conditionalize_block (insn)) |
8f90be4c NC |
2880 | continue; |
2881 | } | |
2882 | ||
2883 | static int saved_warn_return_type = -1; | |
2884 | static int saved_warn_return_type_count = 0; | |
2885 | ||
18dbd950 | 2886 | /* This is to handle loads from the constant pool. */ |
4816b8e4 | 2887 | |
18dbd950 | 2888 | static void |
08903e08 | 2889 | mcore_reorg (void) |
8f90be4c NC |
2890 | { |
2891 | /* Reset this variable. */ | |
2892 | current_function_anonymous_args = 0; | |
2893 | ||
4816b8e4 | 2894 | /* Restore the warn_return_type if it has been altered. */ |
8f90be4c NC |
2895 | if (saved_warn_return_type != -1) |
2896 | { | |
2897 | /* Only restore the value if we have reached another function. | |
2898 | The test of warn_return_type occurs in final_function () in | |
2899 | c-decl.c a long time after the code for the function is generated, | |
2900 | so we need a counter to tell us when we have finished parsing that | |
2901 | function and can restore the flag. */ | |
2902 | if (--saved_warn_return_type_count == 0) | |
2903 | { | |
2904 | warn_return_type = saved_warn_return_type; | |
2905 | saved_warn_return_type = -1; | |
2906 | } | |
2907 | } | |
2908 | ||
2909 | if (optimize == 0) | |
2910 | return; | |
2911 | ||
2912 | /* Conditionalize blocks where we can. */ | |
18dbd950 | 2913 | conditionalize_optimization (); |
8f90be4c NC |
2914 | |
2915 | /* Literal pool generation is now pushed off until the assembler. */ | |
2916 | } | |
2917 | ||
2918 | \f | |
f0f4da32 | 2919 | /* Return true if X is something that can be moved directly into r15. */ |
8f90be4c | 2920 | |
f0f4da32 | 2921 | bool |
08903e08 | 2922 | mcore_r15_operand_p (rtx x) |
f0f4da32 RS |
2923 | { |
2924 | switch (GET_CODE (x)) | |
2925 | { | |
2926 | case CONST_INT: | |
2927 | return mcore_const_ok_for_inline (INTVAL (x)); | |
8f90be4c | 2928 | |
f0f4da32 RS |
2929 | case REG: |
2930 | case SUBREG: | |
2931 | case MEM: | |
2932 | return 1; | |
2933 | ||
2934 | default: | |
2935 | return 0; | |
2936 | } | |
2937 | } | |
2938 | ||
2939 | /* Implement SECONDARY_RELOAD_CLASS. If CLASS contains r15, and we can't | |
2940 | directly move X into it, use r1-r14 as a temporary. */ | |
08903e08 | 2941 | |
f0f4da32 | 2942 | enum reg_class |
08903e08 SB |
2943 | mcore_secondary_reload_class (enum reg_class class, |
2944 | enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
f0f4da32 RS |
2945 | { |
2946 | if (TEST_HARD_REG_BIT (reg_class_contents[class], 15) | |
2947 | && !mcore_r15_operand_p (x)) | |
2948 | return LRW_REGS; | |
2949 | return NO_REGS; | |
2950 | } | |
8f90be4c | 2951 | |
f0f4da32 RS |
2952 | /* Return the reg_class to use when reloading the rtx X into the class |
2953 | CLASS. If X is too complex to move directly into r15, prefer to | |
2954 | use LRW_REGS instead. */ | |
08903e08 | 2955 | |
8f90be4c | 2956 | enum reg_class |
08903e08 | 2957 | mcore_reload_class (rtx x, enum reg_class class) |
8f90be4c | 2958 | { |
f0f4da32 RS |
2959 | if (reg_class_subset_p (LRW_REGS, class) && !mcore_r15_operand_p (x)) |
2960 | return LRW_REGS; | |
8f90be4c | 2961 | |
f0f4da32 | 2962 | return class; |
8f90be4c NC |
2963 | } |
2964 | ||
2965 | /* Tell me if a pair of reg/subreg rtx's actually refer to the same | |
2966 | register. Note that the current version doesn't worry about whether | |
2967 | they are the same mode or note (e.g., a QImode in r2 matches an HImode | |
2968 | in r2 matches an SImode in r2. Might think in the future about whether | |
2969 | we want to be able to say something about modes. */ | |
08903e08 | 2970 | |
8f90be4c | 2971 | int |
08903e08 | 2972 | mcore_is_same_reg (rtx x, rtx y) |
8f90be4c | 2973 | { |
14bc6742 | 2974 | /* Strip any and all of the subreg wrappers. */ |
8f90be4c NC |
2975 | while (GET_CODE (x) == SUBREG) |
2976 | x = SUBREG_REG (x); | |
2977 | ||
2978 | while (GET_CODE (y) == SUBREG) | |
2979 | y = SUBREG_REG (y); | |
2980 | ||
2981 | if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y)) | |
2982 | return 1; | |
2983 | ||
2984 | return 0; | |
2985 | } | |
2986 | ||
8f90be4c | 2987 | void |
08903e08 | 2988 | mcore_override_options (void) |
8f90be4c NC |
2989 | { |
2990 | if (mcore_stack_increment_string) | |
2991 | { | |
2992 | mcore_stack_increment = atoi (mcore_stack_increment_string); | |
2993 | ||
2994 | if (mcore_stack_increment < 0 | |
2995 | || (mcore_stack_increment == 0 | |
2996 | && (mcore_stack_increment_string[0] != '0' | |
2997 | || mcore_stack_increment_string[1] != 0))) | |
c725bd79 | 2998 | error ("invalid option `-mstack-increment=%s'", |
8f90be4c NC |
2999 | mcore_stack_increment_string); |
3000 | } | |
3001 | ||
3002 | /* Only the m340 supports little endian code. */ | |
3003 | if (TARGET_LITTLE_END && ! TARGET_M340) | |
3004 | target_flags |= M340_BIT; | |
8f90be4c NC |
3005 | } |
3006 | \f | |
8f90be4c NC |
3007 | /* Compute the number of word sized registers needed to |
3008 | hold a function argument of mode MODE and type TYPE. */ | |
08903e08 | 3009 | |
8f90be4c | 3010 | int |
08903e08 | 3011 | mcore_num_arg_regs (enum machine_mode mode, tree type) |
8f90be4c NC |
3012 | { |
3013 | int size; | |
3014 | ||
fe984136 | 3015 | if (targetm.calls.must_pass_in_stack (mode, type)) |
8f90be4c NC |
3016 | return 0; |
3017 | ||
3018 | if (type && mode == BLKmode) | |
3019 | size = int_size_in_bytes (type); | |
3020 | else | |
3021 | size = GET_MODE_SIZE (mode); | |
3022 | ||
3023 | return ROUND_ADVANCE (size); | |
3024 | } | |
3025 | ||
3026 | static rtx | |
08903e08 | 3027 | handle_structs_in_regs (enum machine_mode mode, tree type, int reg) |
8f90be4c NC |
3028 | { |
3029 | int size; | |
3030 | ||
3031 | /* The MCore ABI defines that a structure whoes size is not a whole multiple | |
3032 | of bytes is passed packed into registers (or spilled onto the stack if | |
3033 | not enough registers are available) with the last few bytes of the | |
3034 | structure being packed, left-justified, into the last register/stack slot. | |
3035 | GCC handles this correctly if the last word is in a stack slot, but we | |
3036 | have to generate a special, PARALLEL RTX if the last word is in an | |
3037 | argument register. */ | |
3038 | if (type | |
3039 | && TYPE_MODE (type) == BLKmode | |
3040 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
3041 | && (size = int_size_in_bytes (type)) > UNITS_PER_WORD | |
3042 | && (size % UNITS_PER_WORD != 0) | |
3043 | && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS))) | |
3044 | { | |
3045 | rtx arg_regs [NPARM_REGS]; | |
3046 | int nregs; | |
3047 | rtx result; | |
3048 | rtvec rtvec; | |
3049 | ||
3050 | for (nregs = 0; size > 0; size -= UNITS_PER_WORD) | |
3051 | { | |
3052 | arg_regs [nregs] = | |
3053 | gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++), | |
3054 | GEN_INT (nregs * UNITS_PER_WORD)); | |
3055 | nregs ++; | |
3056 | } | |
3057 | ||
3058 | /* We assume here that NPARM_REGS == 6. The assert checks this. */ | |
b6a1cbae | 3059 | assert (ARRAY_SIZE (arg_regs) == 6); |
8f90be4c NC |
3060 | rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2], |
3061 | arg_regs[3], arg_regs[4], arg_regs[5]); | |
3062 | ||
3063 | result = gen_rtx_PARALLEL (mode, rtvec); | |
3064 | return result; | |
3065 | } | |
3066 | ||
3067 | return gen_rtx_REG (mode, reg); | |
3068 | } | |
3069 | ||
3070 | rtx | |
08903e08 | 3071 | mcore_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) |
8f90be4c NC |
3072 | { |
3073 | enum machine_mode mode; | |
3074 | int unsigned_p; | |
3075 | ||
3076 | mode = TYPE_MODE (valtype); | |
3077 | ||
3078 | PROMOTE_MODE (mode, unsigned_p, NULL); | |
3079 | ||
3080 | return handle_structs_in_regs (mode, valtype, FIRST_RET_REG); | |
3081 | } | |
3082 | ||
3083 | /* Define where to put the arguments to a function. | |
3084 | Value is zero to push the argument on the stack, | |
3085 | or a hard register in which to store the argument. | |
3086 | ||
3087 | MODE is the argument's machine mode. | |
3088 | TYPE is the data type of the argument (as a tree). | |
3089 | This is null for libcalls where that information may | |
3090 | not be available. | |
3091 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3092 | the preceding args and about the function being called. | |
3093 | NAMED is nonzero if this argument is a named parameter | |
3094 | (otherwise it is an extra parameter matching an ellipsis). | |
3095 | ||
3096 | On MCore the first args are normally in registers | |
3097 | and the rest are pushed. Any arg that starts within the first | |
3098 | NPARM_REGS words is at least partially passed in a register unless | |
3099 | its data type forbids. */ | |
08903e08 | 3100 | |
8f90be4c | 3101 | rtx |
08903e08 SB |
3102 | mcore_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, |
3103 | tree type, int named) | |
8f90be4c NC |
3104 | { |
3105 | int arg_reg; | |
3106 | ||
3107 | if (! named) | |
3108 | return 0; | |
3109 | ||
fe984136 | 3110 | if (targetm.calls.must_pass_in_stack (mode, type)) |
8f90be4c NC |
3111 | return 0; |
3112 | ||
3113 | arg_reg = ROUND_REG (cum, mode); | |
3114 | ||
3115 | if (arg_reg < NPARM_REGS) | |
3116 | return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg); | |
3117 | ||
3118 | return 0; | |
3119 | } | |
3120 | ||
3121 | /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. | |
3122 | Returns the number of argument registers required to hold *part* of | |
3123 | a parameter of machine mode MODE and type TYPE (which may be NULL if | |
dab66575 | 3124 | the type is not known). If the argument fits entirely in the argument |
8f90be4c NC |
3125 | registers, or entirely on the stack, then 0 is returned. CUM is the |
3126 | number of argument registers already used by earlier parameters to | |
3127 | the function. */ | |
08903e08 | 3128 | |
8f90be4c | 3129 | int |
08903e08 SB |
3130 | mcore_function_arg_partial_nregs (CUMULATIVE_ARGS cum, enum machine_mode mode, |
3131 | tree type, int named) | |
8f90be4c NC |
3132 | { |
3133 | int reg = ROUND_REG (cum, mode); | |
3134 | ||
3135 | if (named == 0) | |
3136 | return 0; | |
3137 | ||
fe984136 | 3138 | if (targetm.calls.must_pass_in_stack (mode, type)) |
8f90be4c NC |
3139 | return 0; |
3140 | ||
3141 | /* REG is not the *hardware* register number of the register that holds | |
3142 | the argument, it is the *argument* register number. So for example, | |
3143 | the first argument to a function goes in argument register 0, which | |
3144 | translates (for the MCore) into hardware register 2. The second | |
3145 | argument goes into argument register 1, which translates into hardware | |
3146 | register 3, and so on. NPARM_REGS is the number of argument registers | |
3147 | supported by the target, not the maximum hardware register number of | |
3148 | the target. */ | |
3149 | if (reg >= NPARM_REGS) | |
3150 | return 0; | |
3151 | ||
3152 | /* If the argument fits entirely in registers, return 0. */ | |
3153 | if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS) | |
3154 | return 0; | |
3155 | ||
3156 | /* The argument overflows the number of available argument registers. | |
3157 | Compute how many argument registers have not yet been assigned to | |
3158 | hold an argument. */ | |
3159 | reg = NPARM_REGS - reg; | |
3160 | ||
3161 | /* Return partially in registers and partially on the stack. */ | |
3162 | return reg; | |
3163 | } | |
3164 | \f | |
a0ab749a | 3165 | /* Return nonzero if SYMBOL is marked as being dllexport'd. */ |
08903e08 | 3166 | |
8f90be4c | 3167 | int |
08903e08 | 3168 | mcore_dllexport_name_p (const char * symbol) |
8f90be4c NC |
3169 | { |
3170 | return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.'; | |
3171 | } | |
3172 | ||
a0ab749a | 3173 | /* Return nonzero if SYMBOL is marked as being dllimport'd. */ |
08903e08 | 3174 | |
8f90be4c | 3175 | int |
08903e08 | 3176 | mcore_dllimport_name_p (const char * symbol) |
8f90be4c NC |
3177 | { |
3178 | return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.'; | |
3179 | } | |
3180 | ||
3181 | /* Mark a DECL as being dllexport'd. */ | |
08903e08 | 3182 | |
8f90be4c | 3183 | static void |
08903e08 | 3184 | mcore_mark_dllexport (tree decl) |
8f90be4c | 3185 | { |
cbd3488b | 3186 | const char * oldname; |
8f90be4c NC |
3187 | char * newname; |
3188 | rtx rtlname; | |
3189 | tree idp; | |
3190 | ||
3191 | rtlname = XEXP (DECL_RTL (decl), 0); | |
3192 | ||
3193 | if (GET_CODE (rtlname) == SYMBOL_REF) | |
3194 | oldname = XSTR (rtlname, 0); | |
3195 | else if ( GET_CODE (rtlname) == MEM | |
3196 | && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF) | |
3197 | oldname = XSTR (XEXP (rtlname, 0), 0); | |
3198 | else | |
3199 | abort (); | |
3200 | ||
3201 | if (mcore_dllexport_name_p (oldname)) | |
3202 | return; /* Already done. */ | |
3203 | ||
3204 | newname = alloca (strlen (oldname) + 4); | |
3205 | sprintf (newname, "@e.%s", oldname); | |
3206 | ||
3207 | /* We pass newname through get_identifier to ensure it has a unique | |
3208 | address. RTL processing can sometimes peek inside the symbol ref | |
3209 | and compare the string's addresses to see if two symbols are | |
3210 | identical. */ | |
3211 | /* ??? At least I think that's why we do this. */ | |
3212 | idp = get_identifier (newname); | |
3213 | ||
3214 | XEXP (DECL_RTL (decl), 0) = | |
f1c25d3b | 3215 | gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp)); |
8f90be4c NC |
3216 | } |
3217 | ||
3218 | /* Mark a DECL as being dllimport'd. */ | |
08903e08 | 3219 | |
8f90be4c | 3220 | static void |
08903e08 | 3221 | mcore_mark_dllimport (tree decl) |
8f90be4c | 3222 | { |
cbd3488b | 3223 | const char * oldname; |
8f90be4c NC |
3224 | char * newname; |
3225 | tree idp; | |
3226 | rtx rtlname; | |
3227 | rtx newrtl; | |
3228 | ||
3229 | rtlname = XEXP (DECL_RTL (decl), 0); | |
3230 | ||
3231 | if (GET_CODE (rtlname) == SYMBOL_REF) | |
3232 | oldname = XSTR (rtlname, 0); | |
3233 | else if ( GET_CODE (rtlname) == MEM | |
3234 | && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF) | |
3235 | oldname = XSTR (XEXP (rtlname, 0), 0); | |
3236 | else | |
3237 | abort (); | |
3238 | ||
3239 | if (mcore_dllexport_name_p (oldname)) | |
3240 | abort (); /* This shouldn't happen. */ | |
3241 | else if (mcore_dllimport_name_p (oldname)) | |
3242 | return; /* Already done. */ | |
3243 | ||
3244 | /* ??? One can well ask why we're making these checks here, | |
3245 | and that would be a good question. */ | |
3246 | ||
3247 | /* Imported variables can't be initialized. */ | |
3248 | if (TREE_CODE (decl) == VAR_DECL | |
3249 | && !DECL_VIRTUAL_P (decl) | |
3250 | && DECL_INITIAL (decl)) | |
3251 | { | |
ddd2d57e | 3252 | error ("%Jinitialized variable '%D' is marked dllimport", decl, decl); |
8f90be4c NC |
3253 | return; |
3254 | } | |
3255 | ||
3256 | /* `extern' needn't be specified with dllimport. | |
3257 | Specify `extern' now and hope for the best. Sigh. */ | |
3258 | if (TREE_CODE (decl) == VAR_DECL | |
3259 | /* ??? Is this test for vtables needed? */ | |
3260 | && !DECL_VIRTUAL_P (decl)) | |
3261 | { | |
3262 | DECL_EXTERNAL (decl) = 1; | |
3263 | TREE_PUBLIC (decl) = 1; | |
3264 | } | |
3265 | ||
3266 | newname = alloca (strlen (oldname) + 11); | |
3267 | sprintf (newname, "@i.__imp_%s", oldname); | |
3268 | ||
3269 | /* We pass newname through get_identifier to ensure it has a unique | |
3270 | address. RTL processing can sometimes peek inside the symbol ref | |
3271 | and compare the string's addresses to see if two symbols are | |
3272 | identical. */ | |
3273 | /* ??? At least I think that's why we do this. */ | |
3274 | idp = get_identifier (newname); | |
3275 | ||
f1c25d3b KH |
3276 | newrtl = gen_rtx_MEM (Pmode, |
3277 | gen_rtx_SYMBOL_REF (Pmode, | |
8f90be4c NC |
3278 | IDENTIFIER_POINTER (idp))); |
3279 | XEXP (DECL_RTL (decl), 0) = newrtl; | |
3280 | } | |
3281 | ||
3282 | static int | |
08903e08 | 3283 | mcore_dllexport_p (tree decl) |
8f90be4c NC |
3284 | { |
3285 | if ( TREE_CODE (decl) != VAR_DECL | |
3286 | && TREE_CODE (decl) != FUNCTION_DECL) | |
3287 | return 0; | |
3288 | ||
91d231cb | 3289 | return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0; |
8f90be4c NC |
3290 | } |
3291 | ||
3292 | static int | |
08903e08 | 3293 | mcore_dllimport_p (tree decl) |
8f90be4c NC |
3294 | { |
3295 | if ( TREE_CODE (decl) != VAR_DECL | |
3296 | && TREE_CODE (decl) != FUNCTION_DECL) | |
3297 | return 0; | |
3298 | ||
91d231cb | 3299 | return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0; |
8f90be4c NC |
3300 | } |
3301 | ||
fb49053f | 3302 | /* We must mark dll symbols specially. Definitions of dllexport'd objects |
14bc6742 | 3303 | install some info in the .drective (PE) or .exports (ELF) sections. */ |
fb49053f RH |
3304 | |
3305 | static void | |
08903e08 | 3306 | mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIBUTE_UNUSED) |
8f90be4c | 3307 | { |
8f90be4c NC |
3308 | /* Mark the decl so we can tell from the rtl whether the object is |
3309 | dllexport'd or dllimport'd. */ | |
3310 | if (mcore_dllexport_p (decl)) | |
3311 | mcore_mark_dllexport (decl); | |
3312 | else if (mcore_dllimport_p (decl)) | |
3313 | mcore_mark_dllimport (decl); | |
3314 | ||
3315 | /* It might be that DECL has already been marked as dllimport, but | |
3316 | a subsequent definition nullified that. The attribute is gone | |
3317 | but DECL_RTL still has @i.__imp_foo. We need to remove that. */ | |
3318 | else if ((TREE_CODE (decl) == FUNCTION_DECL | |
3319 | || TREE_CODE (decl) == VAR_DECL) | |
3320 | && DECL_RTL (decl) != NULL_RTX | |
3321 | && GET_CODE (DECL_RTL (decl)) == MEM | |
3322 | && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM | |
3323 | && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF | |
3324 | && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0))) | |
3325 | { | |
3cce094d | 3326 | const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0); |
8f90be4c | 3327 | tree idp = get_identifier (oldname + 9); |
f1c25d3b | 3328 | rtx newrtl = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp)); |
8f90be4c NC |
3329 | |
3330 | XEXP (DECL_RTL (decl), 0) = newrtl; | |
3331 | ||
3332 | /* We previously set TREE_PUBLIC and DECL_EXTERNAL. | |
3333 | ??? We leave these alone for now. */ | |
3334 | } | |
3335 | } | |
3336 | ||
772c5265 RH |
3337 | /* Undo the effects of the above. */ |
3338 | ||
3339 | static const char * | |
08903e08 | 3340 | mcore_strip_name_encoding (const char * str) |
772c5265 RH |
3341 | { |
3342 | return str + (str[0] == '@' ? 3 : 0); | |
3343 | } | |
3344 | ||
8f90be4c NC |
3345 | /* MCore specific attribute support. |
3346 | dllexport - for exporting a function/variable that will live in a dll | |
3347 | dllimport - for importing a function/variable from a dll | |
3348 | naked - do not create a function prologue/epilogue. */ | |
8f90be4c | 3349 | |
91d231cb JM |
3350 | const struct attribute_spec mcore_attribute_table[] = |
3351 | { | |
3352 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
3353 | { "dllexport", 0, 0, true, false, false, NULL }, | |
3354 | { "dllimport", 0, 0, true, false, false, NULL }, | |
3355 | { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute }, | |
3356 | { NULL, 0, 0, false, false, false, NULL } | |
3357 | }; | |
8f90be4c | 3358 | |
91d231cb JM |
3359 | /* Handle a "naked" attribute; arguments as in |
3360 | struct attribute_spec.handler. */ | |
08903e08 | 3361 | |
91d231cb | 3362 | static tree |
08903e08 SB |
3363 | mcore_handle_naked_attribute (tree * node, tree name, tree args ATTRIBUTE_UNUSED, |
3364 | int flags ATTRIBUTE_UNUSED, bool * no_add_attrs) | |
91d231cb JM |
3365 | { |
3366 | if (TREE_CODE (*node) == FUNCTION_DECL) | |
8f90be4c NC |
3367 | { |
3368 | /* PR14310 - don't complain about lack of return statement | |
3369 | in naked functions. The solution here is a gross hack | |
3370 | but this is the only way to solve the problem without | |
3371 | adding a new feature to GCC. I did try submitting a patch | |
3372 | that would add such a new feature, but it was (rightfully) | |
3373 | rejected on the grounds that it was creeping featurism, | |
3374 | so hence this code. */ | |
3375 | if (warn_return_type) | |
3376 | { | |
3377 | saved_warn_return_type = warn_return_type; | |
3378 | warn_return_type = 0; | |
3379 | saved_warn_return_type_count = 2; | |
3380 | } | |
3381 | else if (saved_warn_return_type_count) | |
3382 | saved_warn_return_type_count = 2; | |
91d231cb JM |
3383 | } |
3384 | else | |
3385 | { | |
3386 | warning ("`%s' attribute only applies to functions", | |
3387 | IDENTIFIER_POINTER (name)); | |
3388 | *no_add_attrs = true; | |
8f90be4c NC |
3389 | } |
3390 | ||
91d231cb | 3391 | return NULL_TREE; |
8f90be4c NC |
3392 | } |
3393 | ||
ae46c4e0 RH |
3394 | /* ??? It looks like this is PE specific? Oh well, this is what the |
3395 | old code did as well. */ | |
8f90be4c | 3396 | |
ae46c4e0 | 3397 | static void |
08903e08 | 3398 | mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
8f90be4c NC |
3399 | { |
3400 | int len; | |
0139adca | 3401 | const char * name; |
8f90be4c | 3402 | char * string; |
f27cd94d | 3403 | const char * prefix; |
8f90be4c NC |
3404 | |
3405 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
3406 | ||
3407 | /* Strip off any encoding in name. */ | |
772c5265 | 3408 | name = (* targetm.strip_name_encoding) (name); |
8f90be4c NC |
3409 | |
3410 | /* The object is put in, for example, section .text$foo. | |
3411 | The linker will then ultimately place them in .text | |
3412 | (everything from the $ on is stripped). */ | |
3413 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
3414 | prefix = ".text$"; | |
f710504c | 3415 | /* For compatibility with EPOC, we ignore the fact that the |
8f90be4c | 3416 | section might have relocs against it. */ |
4e4d733e | 3417 | else if (decl_readonly_section (decl, 0)) |
8f90be4c NC |
3418 | prefix = ".rdata$"; |
3419 | else | |
3420 | prefix = ".data$"; | |
3421 | ||
3422 | len = strlen (name) + strlen (prefix); | |
3423 | string = alloca (len + 1); | |
3424 | ||
3425 | sprintf (string, "%s%s", prefix, name); | |
3426 | ||
3427 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
3428 | } | |
3429 | ||
3430 | int | |
08903e08 | 3431 | mcore_naked_function_p (void) |
8f90be4c | 3432 | { |
91d231cb | 3433 | return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; |
8f90be4c | 3434 | } |
7c262518 | 3435 | |
ede75ee8 | 3436 | #ifdef OBJECT_FORMAT_ELF |
7c262518 | 3437 | static void |
08903e08 | 3438 | mcore_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED) |
7c262518 RH |
3439 | { |
3440 | fprintf (asm_out_file, "\t.section %s\n", name); | |
3441 | } | |
ede75ee8 | 3442 | #endif /* OBJECT_FORMAT_ELF */ |
09a2b93a | 3443 | |
dc7efe6e KH |
3444 | /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */ |
3445 | ||
09a2b93a KH |
3446 | static void |
3447 | mcore_external_libcall (rtx fun) | |
3448 | { | |
3449 | fprintf (asm_out_file, "\t.import\t"); | |
3450 | assemble_name (asm_out_file, XSTR (fun, 0)); | |
3451 | fprintf (asm_out_file, "\n"); | |
3452 | } | |
3453 | ||
dc7efe6e KH |
3454 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
3455 | ||
09a2b93a KH |
3456 | static bool |
3457 | mcore_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
3458 | { | |
78bc94a2 KH |
3459 | HOST_WIDE_INT size = int_size_in_bytes (type); |
3460 | return (size == -1 || size > 2 * UNITS_PER_WORD); | |
09a2b93a | 3461 | } |