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8f90be4c NC |
1 | /* Definitions of target machine for GNU compiler, |
2 | for Motorola M*CORE Processor. | |
31488c64 NC |
3 | Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003 |
4 | Free Software Foundation, Inc. | |
8f90be4c | 5 | |
31488c64 | 6 | This file is part of GCC. |
8f90be4c | 7 | |
31488c64 NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
8f90be4c | 12 | |
31488c64 NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
8f90be4c | 17 | |
31488c64 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
8f90be4c | 22 | |
88657302 RH |
23 | #ifndef GCC_MCORE_H |
24 | #define GCC_MCORE_H | |
8f90be4c NC |
25 | |
26 | /* RBE: need to move these elsewhere. */ | |
27 | #undef LIKE_PPC_ABI | |
28 | #define MCORE_STRUCT_ARGS | |
29 | /* RBE: end of "move elsewhere". */ | |
30 | ||
8f90be4c NC |
31 | /* Run-time Target Specification. */ |
32 | #define TARGET_MCORE | |
33 | ||
672a6f42 NB |
34 | /* Get tree.c to declare a target-specific specialization of |
35 | merge_decl_attributes. */ | |
36 | #define TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
8f90be4c NC |
37 | |
38 | /* Support the __declspec keyword by turning them into attributes. | |
39 | We currently only support: dllexport and dllimport. | |
40 | Note that the current way we do this may result in a collision with | |
41 | predefined attributes later on. This can be solved by using one attribute, | |
42 | say __declspec__, and passing args to it. The problem with that approach | |
43 | is that args are not accumulated: each new appearance would clobber any | |
f7248b51 NB |
44 | existing args. */ |
45 | #define TARGET_CPU_CPP_BUILTINS() \ | |
46 | do \ | |
47 | { \ | |
48 | builtin_define ("__mcore__"); \ | |
49 | builtin_define ("__MCORE__"); \ | |
50 | builtin_define ("__declspec(x)=__attribute__((x))"); \ | |
51 | if (TARGET_LITTLE_END) \ | |
52 | builtin_define ("__MCORELE__"); \ | |
53 | else \ | |
54 | builtin_define ("__MCOREBE__"); \ | |
55 | if (TARGET_M340) \ | |
56 | builtin_define ("__M340__"); \ | |
57 | else \ | |
58 | builtin_define ("__M210__"); \ | |
59 | } \ | |
60 | while (0) | |
8f90be4c | 61 | |
d6a7951f | 62 | /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC |
8f90be4c | 63 | %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */ |
31488c64 NC |
64 | #undef CPP_SPEC |
65 | #define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}" | |
8f90be4c NC |
66 | |
67 | /* We don't have a -lg library, so don't put it in the list. */ | |
68 | #undef LIB_SPEC | |
69 | #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" | |
70 | ||
71 | #undef ASM_SPEC | |
72 | #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}" | |
73 | ||
74 | #undef LINK_SPEC | |
75 | #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X" | |
76 | ||
77 | /* Can only count on 16 bits of availability; change to long would affect | |
78 | many architecture specific files (other architectures...). */ | |
79 | extern int target_flags; | |
80 | ||
81 | #define HARDLIT_BIT (1 << 0) /* Build in-line literals using 2 insns */ | |
82 | #define ALIGN8_BIT (1 << 1) /* Max alignment goes to 8 instead of 4 */ | |
83 | #define DIV_BIT (1 << 2) /* Generate divide instructions */ | |
84 | #define RELAX_IMM_BIT (1 << 3) /* Arbitrary immediates in and, or, tst */ | |
85 | #define W_FIELD_BIT (1 << 4) /* Generate bit insv/extv using SImode */ | |
86 | #define OVERALIGN_FUNC_BIT (1 << 5) /* Align functions to 4 byte boundary */ | |
87 | #define CGDATA_BIT (1 << 6) /* Generate callgraph data */ | |
88 | #define SLOW_BYTES_BIT (1 << 7) /* Slow byte access */ | |
89 | #define LITTLE_END_BIT (1 << 8) /* Generate little endian code */ | |
90 | #define M340_BIT (1 << 9) /* Generate code for the m340 */ | |
91 | ||
92 | #define TARGET_DEFAULT \ | |
93 | (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT) | |
94 | ||
95 | #ifndef MULTILIB_DEFAULTS | |
96 | #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" } | |
97 | #endif | |
98 | ||
99 | #define TARGET_HARDLIT (target_flags & HARDLIT_BIT) | |
100 | /* The ability to have 4 byte alignment is being suppressed for now. | |
101 | If this ability is reenabled, you must enable the definition below | |
102 | *and* edit t-mcore to enable multilibs for 4 byte alignment code. */ | |
103 | #if 0 | |
104 | #define TARGET_8ALIGN (target_flags & ALIGN8_BIT) | |
105 | #else | |
106 | #define TARGET_8ALIGN 1 | |
107 | #endif | |
108 | #define TARGET_DIV (target_flags & DIV_BIT) | |
109 | #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT) | |
110 | #define TARGET_W_FIELD (target_flags & W_FIELD_BIT) | |
111 | #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT) | |
112 | #define TARGET_CG_DATA (target_flags & CGDATA_BIT) | |
113 | #define TARGET_CG_DATA (target_flags & CGDATA_BIT) | |
114 | #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT) | |
115 | #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT) | |
116 | #define TARGET_M340 (target_flags & M340_BIT) | |
117 | ||
118 | ||
047142d3 PT |
119 | #define TARGET_SWITCHES \ |
120 | { {"hardlit", HARDLIT_BIT, \ | |
121 | N_("Inline constants if it can be done in 2 insns or less") }, \ | |
122 | {"no-hardlit", - HARDLIT_BIT, \ | |
c725bd79 | 123 | N_("Inline constants if it only takes 1 instruction") }, \ |
047142d3 PT |
124 | {"4align", - ALIGN8_BIT, \ |
125 | N_("Set maximum alignment to 4") }, \ | |
126 | {"8align", ALIGN8_BIT, \ | |
127 | N_("Set maximum alignment to 8") }, \ | |
128 | {"div", DIV_BIT, \ | |
129 | "" }, \ | |
130 | {"no-div", - DIV_BIT, \ | |
131 | N_("Do not use the divide instruction") }, \ | |
132 | {"relax-immediates", RELAX_IMM_BIT, \ | |
133 | "" }, \ | |
134 | {"no-relax-immediates", - RELAX_IMM_BIT, \ | |
8e854b76 | 135 | N_("Do not arbitrary sized immediates in bit operations") }, \ |
047142d3 | 136 | {"wide-bitfields", W_FIELD_BIT, \ |
b0287a90 | 137 | N_("Always treat bit-field as int-sized") }, \ |
047142d3 PT |
138 | {"no-wide-bitfields", - W_FIELD_BIT, \ |
139 | "" }, \ | |
140 | {"4byte-functions", OVERALIGN_FUNC_BIT, \ | |
141 | N_("Force functions to be aligned to a 4 byte boundary") }, \ | |
142 | {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \ | |
143 | N_("Force functions to be aligned to a 2 byte boundary") }, \ | |
144 | {"callgraph-data", CGDATA_BIT, \ | |
145 | N_("Emit call graph information") }, \ | |
146 | {"no-callgraph-data", - CGDATA_BIT, \ | |
147 | "" }, \ | |
148 | {"slow-bytes", SLOW_BYTES_BIT, \ | |
149 | N_("Prefer word accesses over byte accesses") }, \ | |
150 | {"no-slow-bytes", - SLOW_BYTES_BIT, \ | |
151 | "" }, \ | |
152 | { "no-lsim", 0, "" }, \ | |
153 | {"little-endian", LITTLE_END_BIT, \ | |
154 | N_("Generate little endian code") }, \ | |
155 | {"big-endian", - LITTLE_END_BIT, \ | |
156 | "" }, \ | |
157 | {"210", - M340_BIT, \ | |
158 | "" }, \ | |
159 | {"340", M340_BIT, \ | |
160 | N_("Generate code for the M*Core M340") }, \ | |
161 | {"", TARGET_DEFAULT, \ | |
162 | "" } \ | |
8f90be4c NC |
163 | } |
164 | ||
165 | extern char * mcore_current_function_name; | |
166 | ||
167 | /* Target specific options (as opposed to the switches above). */ | |
168 | extern const char * mcore_stack_increment_string; | |
169 | ||
047142d3 PT |
170 | #define TARGET_OPTIONS \ |
171 | { \ | |
172 | {"stack-increment=", & mcore_stack_increment_string, \ | |
c409ea0d | 173 | N_("Maximum amount for a single stack increment operation"), 0} \ |
8f90be4c NC |
174 | } |
175 | ||
56ae9405 NC |
176 | /* The MCore ABI says that bitfields are unsigned by default. */ |
177 | #define CC1_SPEC "-funsigned-bitfields" | |
8f90be4c NC |
178 | |
179 | /* What options are we going to default to specific settings when | |
180 | -O* happens; the user can subsequently override these settings. | |
181 | ||
182 | Omitting the frame pointer is a very good idea on the MCore. | |
183 | Scheduling isn't worth anything on the current MCore implementation. */ | |
184 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ | |
185 | { \ | |
186 | if (LEVEL) \ | |
187 | { \ | |
188 | flag_no_function_cse = 1; \ | |
189 | flag_omit_frame_pointer = 1; \ | |
190 | \ | |
191 | if (LEVEL >= 2) \ | |
192 | { \ | |
193 | flag_caller_saves = 0; \ | |
194 | flag_schedule_insns = 0; \ | |
195 | flag_schedule_insns_after_reload = 0; \ | |
196 | } \ | |
197 | } \ | |
198 | if (SIZE) \ | |
199 | { \ | |
200 | target_flags &= ~ HARDLIT_BIT; \ | |
201 | } \ | |
202 | } | |
203 | ||
204 | /* What options are we going to force to specific settings, | |
205 | regardless of what the user thought he wanted. | |
31488c64 | 206 | We also use this for some post-processing of options. */ |
8f90be4c NC |
207 | #define OVERRIDE_OPTIONS mcore_override_options () |
208 | ||
209 | /* Target machine storage Layout. */ | |
210 | ||
8f90be4c NC |
211 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
212 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
213 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
214 | { \ | |
215 | (MODE) = SImode; \ | |
216 | (UNSIGNEDP) = 1; \ | |
217 | } | |
218 | ||
219 | #define PROMOTE_FUNCTION_ARGS | |
220 | ||
221 | #define PROMOTE_FUNCTION_RETURN | |
222 | ||
223 | /* Define this if most significant bit is lowest numbered | |
224 | in instructions that operate on numbered bit-fields. */ | |
225 | #define BITS_BIG_ENDIAN 0 | |
226 | ||
227 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
228 | #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END) | |
229 | ||
230 | /* Define this if most significant word of a multiword number is the lowest | |
231 | numbered. */ | |
232 | #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END) | |
233 | ||
234 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
235 | #ifdef __MCORELE__ | |
236 | #undef LIBGCC2_WORDS_BIG_ENDIAN | |
237 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
238 | #endif | |
239 | ||
8f90be4c NC |
240 | #define MAX_BITS_PER_WORD 32 |
241 | ||
242 | /* Width of a word, in units (bytes). */ | |
243 | #define UNITS_PER_WORD 4 | |
244 | ||
8f90be4c NC |
245 | /* A C expression for the size in bits of the type `long long' on the |
246 | target machine. If you don't define this, the default is two | |
247 | words. */ | |
248 | #define LONG_LONG_TYPE_SIZE 64 | |
249 | ||
8f90be4c NC |
250 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
251 | #define PARM_BOUNDARY 32 | |
252 | ||
dab66575 | 253 | /* Doubles must be aligned to an 8 byte boundary. */ |
8f90be4c NC |
254 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
255 | ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \ | |
256 | ? BIGGEST_ALIGNMENT : PARM_BOUNDARY) | |
257 | ||
258 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
259 | #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) | |
260 | ||
261 | /* Largest increment in UNITS we allow the stack to grow in a single operation. */ | |
262 | extern int mcore_stack_increment; | |
263 | #define STACK_UNITS_MAXSTEP 4096 | |
264 | ||
265 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
266 | #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16) | |
267 | ||
268 | /* Alignment of field after `int : 0' in a structure. */ | |
269 | #define EMPTY_FIELD_BOUNDARY 32 | |
270 | ||
271 | /* No data type wants to be aligned rounder than this. */ | |
272 | #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32) | |
273 | ||
274 | /* The best alignment to use in cases where we have a choice. */ | |
275 | #define FASTEST_ALIGNMENT 32 | |
276 | ||
277 | /* Every structures size must be a multiple of 8 bits. */ | |
278 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
279 | ||
43a88a8c | 280 | /* Look at the fundamental type that is used for a bit-field and use |
8f90be4c NC |
281 | that to impose alignment on the enclosing structure. |
282 | struct s {int a:8}; should have same alignment as "int", not "char". */ | |
283 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
284 | ||
285 | /* Largest integer machine mode for structures. If undefined, the default | |
286 | is GET_MODE_SIZE(DImode). */ | |
287 | #define MAX_FIXED_MODE_SIZE 32 | |
288 | ||
289 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
290 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
291 | ((TREE_CODE (EXP) == STRING_CST \ | |
292 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
293 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
294 | ||
295 | /* Make arrays of chars word-aligned for the same reasons. */ | |
296 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
297 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
298 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
299 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
300 | ||
301 | /* Set this nonzero if move instructions will actually fail to work | |
302 | when given unaligned data. */ | |
303 | #define STRICT_ALIGNMENT 1 | |
304 | ||
305 | /* Standard register usage. */ | |
306 | ||
307 | /* Register allocation for our first guess | |
308 | ||
309 | r0 stack pointer | |
310 | r1 scratch, target reg for xtrb? | |
311 | r2-r7 arguments. | |
312 | r8-r14 call saved | |
313 | r15 link register | |
314 | ap arg pointer (doesn't really exist, always eliminated) | |
315 | c c bit | |
316 | fp frame pointer (doesn't really exist, always eliminated) | |
317 | x19 two control registers */ | |
318 | ||
319 | /* Number of actual hardware registers. | |
320 | The hardware registers are assigned numbers for the compiler | |
321 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
322 | All registers that the compiler knows about must be given numbers, | |
323 | even those that are not normally considered general registers. | |
324 | ||
325 | MCore has 16 integer registers and 2 control registers + the arg | |
326 | pointer. */ | |
327 | ||
328 | #define FIRST_PSEUDO_REGISTER 20 | |
329 | ||
330 | #define R1_REG 1 /* where literals are forced */ | |
331 | #define LK_REG 15 /* overloaded on general register */ | |
332 | #define AP_REG 16 /* fake arg pointer register */ | |
333 | /* RBE: mcore.md depends on CC_REG being set to 17 */ | |
f5143c46 | 334 | #define CC_REG 17 /* can't name it C_REG */ |
8f90be4c NC |
335 | #define FP_REG 18 /* fake frame pointer register */ |
336 | ||
337 | /* Specify the registers used for certain standard purposes. | |
338 | The values of these macros are register numbers. */ | |
339 | ||
340 | ||
341 | #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */ | |
342 | #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */ | |
343 | #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */ | |
344 | ||
345 | /* The assembler's names for the registers. RFP need not always be used as | |
346 | the Real framepointer; it can also be used as a normal general register. | |
347 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
348 | the argument-and-return-context pointer. */ | |
349 | #define REGISTER_NAMES \ | |
350 | { \ | |
351 | "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
352 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
353 | "apvirtual", "c", "fpvirtual", "x19" \ | |
354 | } | |
355 | ||
356 | /* 1 for registers that have pervasive standard uses | |
357 | and are not available for the register allocator. */ | |
358 | #define FIXED_REGISTERS \ | |
359 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
360 | { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
361 | ||
362 | /* 1 for registers not available across function calls. | |
363 | These must include the FIXED_REGISTERS and also any | |
364 | registers that can be used without being saved. | |
365 | The latter must include the registers where values are returned | |
366 | and the register where structure-value addresses are passed. | |
367 | Aside from that, you can include as many other registers as you like. */ | |
368 | ||
369 | /* RBE: r15 {link register} not available across calls, | |
31488c64 | 370 | But we don't mark it that way here... */ |
8f90be4c NC |
371 | #define CALL_USED_REGISTERS \ |
372 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
373 | { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
374 | ||
375 | /* The order in which register should be allocated. */ | |
376 | #define REG_ALLOC_ORDER \ | |
377 | /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \ | |
378 | { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19} | |
379 | ||
380 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
381 | to hold something of mode MODE. | |
382 | This is ordinarily the length in words of a value of mode MODE | |
383 | but can be less for certain modes in special long registers. | |
384 | ||
385 | On the MCore regs are UNITS_PER_WORD bits wide; */ | |
386 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
387 | (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
388 | ||
389 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
390 | We may keep double values in even registers. */ | |
391 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
392 | ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18)) | |
393 | ||
394 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
395 | when one has mode MODE1 and one has mode MODE2. | |
396 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
397 | for any hard reg, then this must be 0 for correct output. */ | |
398 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
399 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
400 | ||
401 | /* Value should be nonzero if functions must have frame pointers. | |
402 | Zero means the frame pointer need not be set up (and parms may be accessed | |
403 | via the stack pointer) in functions that seem suitable. */ | |
404 | #define FRAME_POINTER_REQUIRED 0 | |
405 | ||
406 | /* Definitions for register eliminations. | |
407 | ||
408 | We have two registers that can be eliminated on the MCore. First, the | |
409 | frame pointer register can often be eliminated in favor of the stack | |
410 | pointer register. Secondly, the argument pointer register can always be | |
411 | eliminated; it is replaced with either the stack or frame pointer. */ | |
412 | ||
413 | /* Base register for access to arguments of the function. */ | |
414 | #define ARG_POINTER_REGNUM 16 | |
415 | ||
416 | /* Register in which the static-chain is passed to a function. */ | |
417 | #define STATIC_CHAIN_REGNUM 1 | |
418 | ||
419 | /* This is an array of structures. Each structure initializes one pair | |
420 | of eliminable registers. The "from" register number is given first, | |
421 | followed by "to". Eliminations of the same "from" register are listed | |
422 | in order of preference. */ | |
423 | #define ELIMINABLE_REGS \ | |
424 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
425 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
426 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
427 | ||
428 | /* Given FROM and TO register numbers, say whether this elimination | |
429 | is allowed. */ | |
430 | #define CAN_ELIMINATE(FROM, TO) \ | |
431 | (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) | |
432 | ||
433 | /* Define the offset between two registers, one to be eliminated, and the other | |
434 | its replacement, at the start of a routine. */ | |
435 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
436 | OFFSET = mcore_initial_elimination_offset (FROM, TO) | |
437 | ||
438 | /* Place that structure value return address is placed. */ | |
439 | #define STRUCT_VALUE 0 | |
440 | ||
441 | /* Define the classes of registers for register constraints in the | |
442 | machine description. Also define ranges of constants. | |
443 | ||
444 | One of the classes must always be named ALL_REGS and include all hard regs. | |
445 | If there is more than one class, another class must be named NO_REGS | |
446 | and contain no registers. | |
447 | ||
448 | The name GENERAL_REGS must be the name of a class (or an alias for | |
449 | another name such as ALL_REGS). This is the class of registers | |
450 | that is allowed by "g" or "r" in a register constraint. | |
451 | Also, registers outside this class are allocated only when | |
452 | instructions express preferences for them. | |
453 | ||
454 | The classes must be numbered in nondecreasing order; that is, | |
455 | a larger-numbered class must never be contained completely | |
456 | in a smaller-numbered class. | |
457 | ||
458 | For any two classes, it is very desirable that there be another | |
459 | class that represents their union. */ | |
460 | ||
461 | /* The MCore has only general registers. There are | |
462 | also some special purpose registers: the T bit register, the | |
463 | procedure Link and the Count Registers */ | |
464 | enum reg_class | |
465 | { | |
466 | NO_REGS, | |
467 | ONLYR1_REGS, | |
468 | LRW_REGS, | |
469 | GENERAL_REGS, | |
470 | C_REGS, | |
471 | ALL_REGS, | |
472 | LIM_REG_CLASSES | |
473 | }; | |
474 | ||
475 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
476 | ||
477 | /* Give names of register classes as strings for dump file. */ | |
478 | #define REG_CLASS_NAMES \ | |
479 | { \ | |
480 | "NO_REGS", \ | |
481 | "ONLYR1_REGS", \ | |
482 | "LRW_REGS", \ | |
483 | "GENERAL_REGS", \ | |
484 | "C_REGS", \ | |
485 | "ALL_REGS", \ | |
486 | } | |
487 | ||
488 | /* Define which registers fit in which classes. | |
489 | This is an initializer for a vector of HARD_REG_SET | |
490 | of length N_REG_CLASSES. */ | |
491 | ||
492 | /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */ | |
493 | #define REG_CLASS_CONTENTS \ | |
494 | { \ | |
495 | {0x000000}, /* NO_REGS */ \ | |
496 | {0x000002}, /* ONLYR1_REGS */ \ | |
497 | {0x007FFE}, /* LRW_REGS */ \ | |
498 | {0x01FFFF}, /* GENERAL_REGS */ \ | |
499 | {0x020000}, /* C_REGS */ \ | |
500 | {0x0FFFFF} /* ALL_REGS */ \ | |
501 | } | |
502 | ||
503 | /* The same information, inverted: | |
504 | Return the class number of the smallest class containing | |
505 | reg number REGNO. This could be a conditional expression | |
506 | or could index an array. */ | |
507 | ||
0139adca | 508 | extern const int regno_reg_class[FIRST_PSEUDO_REGISTER]; |
8f90be4c NC |
509 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO] |
510 | ||
511 | /* When defined, the compiler allows registers explicitly used in the | |
512 | rtl to be used as spill registers but prevents the compiler from | |
513 | extending the lifetime of these registers. */ | |
514 | #define SMALL_REGISTER_CLASSES 1 | |
515 | ||
516 | /* The class value for index registers, and the one for base regs. */ | |
517 | #define INDEX_REG_CLASS NO_REGS | |
518 | #define BASE_REG_CLASS GENERAL_REGS | |
519 | ||
520 | /* Get reg_class from a letter such as appears in the machine | |
521 | description. */ | |
0b5826ac | 522 | extern const enum reg_class reg_class_from_letter[]; |
8f90be4c NC |
523 | |
524 | #define REG_CLASS_FROM_LETTER(C) \ | |
31488c64 | 525 | (ISLOWER (C) ? reg_class_from_letter[(C) - 'a'] : NO_REGS) |
8f90be4c NC |
526 | |
527 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
528 | can be used to stand for particular ranges of immediate operands. | |
529 | This macro defines what the ranges are. | |
530 | C is the letter, and VALUE is a constant value. | |
531 | Return 1 if VALUE is in the range specified by C. | |
532 | I: loadable by movi (0..127) | |
533 | J: arithmetic operand 1..32 | |
534 | K: shift operand 0..31 | |
535 | L: negative arithmetic operand -1..-32 | |
536 | M: powers of two, constants loadable by bgeni | |
537 | N: powers of two minus 1, constants loadable by bmaski, including -1 | |
538 | O: allowed by cmov with two constants +/- 1 of each other | |
539 | P: values we will generate 'inline' -- without an 'lrw' | |
540 | ||
541 | Others defined for use after reload | |
542 | Q: constant 1 | |
543 | R: a label | |
544 | S: 0/1/2 cleared bits out of 32 [for bclri's] | |
545 | T: 2 set bits out of 32 [for bseti's] | |
546 | U: constant 0 | |
547 | xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri | |
548 | xxxT: 2 cleared bits out of 32. for pairs of bclris. */ | |
549 | #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f) | |
550 | #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32) | |
551 | #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32) | |
552 | #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31) | |
553 | #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0) | |
554 | #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0) | |
555 | #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \ | |
556 | CONST_OK_FOR_M(VALUE) || \ | |
557 | CONST_OK_FOR_N(VALUE) || \ | |
558 | CONST_OK_FOR_M((int)(VALUE) - 1) || \ | |
559 | CONST_OK_FOR_N((int)(VALUE) + 1)) | |
560 | ||
561 | #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE)) | |
562 | ||
563 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
564 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
565 | : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ | |
566 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
567 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
568 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
569 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
570 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ | |
571 | : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ | |
572 | : 0) | |
573 | ||
574 | /* Similar, but for floating constants, and defining letters G and H. | |
575 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
576 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
577 | ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \ | |
578 | && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \ | |
579 | : 0) | |
580 | ||
581 | /* Letters in the range `Q' through `U' in a register constraint string | |
582 | may be defined in a machine-dependent fashion to stand for arbitrary | |
583 | operand types. */ | |
584 | #define EXTRA_CONSTRAINT(OP, C) \ | |
585 | ((C) == 'R' ? (GET_CODE (OP) == MEM \ | |
586 | && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \ | |
587 | : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \ | |
588 | && mcore_num_zeros (INTVAL (OP)) <= 2) \ | |
589 | : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \ | |
590 | && mcore_num_ones (INTVAL (OP)) == 2) \ | |
591 | : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \ | |
592 | && INTVAL(OP) == 1) \ | |
593 | : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \ | |
594 | && INTVAL(OP) == 0) \ | |
595 | : 0) | |
596 | ||
597 | /* Given an rtx X being reloaded into a reg required to be | |
598 | in class CLASS, return the class of reg to actually use. | |
599 | In general this is just CLASS; but on some machines | |
600 | in some cases it is preferable to use a more restrictive class. */ | |
601 | #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS) | |
602 | ||
603 | /* Return the register class of a scratch register needed to copy IN into | |
604 | or out of a register in CLASS in MODE. If it can be done directly, | |
605 | NO_REGS is returned. */ | |
606 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS | |
607 | ||
608 | /* Return the maximum number of consecutive registers | |
609 | needed to represent mode MODE in a register of class CLASS. | |
610 | ||
611 | On MCore this is the size of MODE in words. */ | |
612 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
613 | (ROUND_ADVANCE (GET_MODE_SIZE (MODE))) | |
614 | ||
615 | /* Stack layout; function entry, exit and calling. */ | |
616 | ||
617 | /* Define the number of register that can hold parameters. | |
618 | These two macros are used only in other macro definitions below. */ | |
619 | #define NPARM_REGS 6 | |
620 | #define FIRST_PARM_REG 2 | |
621 | #define FIRST_RET_REG 2 | |
622 | ||
623 | /* Define this if pushing a word on the stack | |
624 | makes the stack pointer a smaller address. */ | |
625 | #define STACK_GROWS_DOWNWARD | |
626 | ||
627 | /* Define this if the nominal address of the stack frame | |
628 | is at the high-address end of the local variables; | |
629 | that is, each additional local variable allocated | |
630 | goes at a more negative offset in the frame. */ | |
631 | /* We don't define this, because the MCore does not support | |
632 | addresses with negative offsets. */ | |
633 | /* #define FRAME_GROWS_DOWNWARD */ | |
634 | ||
635 | /* Offset within stack frame to start allocating local variables at. | |
636 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
637 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
638 | of the first local allocated. */ | |
639 | #define STARTING_FRAME_OFFSET 0 | |
640 | ||
641 | /* If defined, the maximum amount of space required for outgoing arguments | |
642 | will be computed and placed into the variable | |
643 | `current_function_outgoing_args_size'. No space will be pushed | |
644 | onto the stack for each call; instead, the function prologue should | |
645 | increase the stack frame size by this amount. */ | |
f73ad30e | 646 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8f90be4c NC |
647 | |
648 | /* Offset of first parameter from the argument pointer register value. */ | |
649 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
650 | ||
651 | /* Value is the number of byte of arguments automatically | |
652 | popped when returning from a subroutine call. | |
653 | FUNTYPE is the data type of the function (as a tree), | |
654 | or for a library call it is an identifier node for the subroutine name. | |
655 | SIZE is the number of bytes of arguments passed on the stack. | |
656 | ||
657 | On the MCore, the callee does not pop any of its arguments that were passed | |
658 | on the stack. */ | |
659 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
660 | ||
661 | /* Define how to find the value returned by a function. | |
662 | VALTYPE is the data type of the value (as a tree). | |
663 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
664 | otherwise, FUNC is 0. */ | |
665 | #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC) | |
666 | ||
667 | /* Don't default to pcc-struct-return, because gcc is the only compiler, and | |
668 | we want to retain compatibility with older gcc versions. */ | |
669 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
670 | ||
671 | /* how we are going to return big values */ | |
672 | /* | |
673 | * #define RETURN_IN_MEMORY(TYPE) \ | |
674 | * (TYPE_MODE (TYPE) == BLKmode \ | |
675 | * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \ | |
676 | * && !(TYPE_MODE (TYPE) == SImode \ | |
677 | * || (TYPE_MODE (TYPE) == BLKmode \ | |
678 | * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \ | |
679 | * && int_size_in_bytes (TYPE) == UNITS_PER_WORD)))) | |
680 | */ | |
681 | ||
682 | ||
683 | /* How many registers to use for struct return. */ | |
684 | #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD) | |
685 | ||
686 | /* Define how to find the value returned by a library function | |
687 | assuming the value has mode MODE. */ | |
688 | #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG) | |
689 | ||
690 | /* 1 if N is a possible register number for a function value. | |
691 | On the MCore, only r4 can return results. */ | |
692 | #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) | |
693 | ||
694 | #define MUST_PASS_IN_STACK(MODE,TYPE) \ | |
695 | mcore_must_pass_on_stack (MODE, TYPE) | |
696 | ||
697 | /* 1 if N is a possible register number for function argument passing. */ | |
698 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
699 | ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) | |
700 | ||
701 | /* Define a data type for recording info about an argument list | |
702 | during the scan of that argument list. This data type should | |
703 | hold all necessary information about the function itself | |
704 | and about the args processed so far, enough to enable macros | |
705 | such as FUNCTION_ARG to determine where the next arg should go. | |
706 | ||
707 | On MCore, this is a single integer, which is a number of words | |
708 | of arguments scanned so far (including the invisible argument, | |
709 | if any, which holds the structure-value-address). | |
710 | Thus NARGREGS or more means all following args should go on the stack. */ | |
711 | #define CUMULATIVE_ARGS int | |
712 | ||
713 | #define ROUND_ADVANCE(SIZE) \ | |
714 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
715 | ||
716 | /* Round a register number up to a proper boundary for an arg of mode | |
717 | MODE. | |
718 | ||
719 | We round to an even reg for things larger than a word. */ | |
720 | #define ROUND_REG(X, MODE) \ | |
721 | ((TARGET_8ALIGN \ | |
722 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
723 | ? ((X) + ((X) & 1)) : (X)) | |
724 | ||
725 | ||
726 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
727 | for a call to a function whose data type is FNTYPE. | |
728 | For a library call, FNTYPE is 0. | |
729 | ||
730 | On MCore, the offset always starts at 0: the first parm reg is always | |
731 | the same reg. */ | |
732 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ | |
733 | ((CUM) = 0) | |
734 | ||
735 | /* Update the data in CUM to advance over an argument | |
736 | of mode MODE and data type TYPE. | |
737 | (TYPE is null for libcalls where that information may not be | |
738 | available.) */ | |
739 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
740 | ((CUM) = (ROUND_REG ((CUM), (MODE)) \ | |
741 | + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \ | |
742 | ||
743 | /* Define where to put the arguments to a function. */ | |
744 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
745 | mcore_function_arg (CUM, MODE, TYPE, NAMED) | |
746 | ||
747 | /* A C expression that indicates when an argument must be passed by | |
748 | reference. If nonzero for an argument, a copy of that argument is | |
749 | made in memory and a pointer to the argument is passed instead of | |
750 | the argument itself. The pointer is passed in whatever way is | |
751 | appropriate for passing a pointer to that type. */ | |
752 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
753 | MUST_PASS_IN_STACK (MODE, TYPE) | |
754 | ||
755 | /* For an arg passed partly in registers and partly in memory, | |
756 | this is the number of registers used. | |
757 | For args passed entirely in registers or entirely in memory, zero. | |
758 | Any arg that starts in the first NPARM_REGS regs but won't entirely | |
759 | fit in them needs partial registers on the MCore. */ | |
760 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
761 | mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED) | |
762 | ||
763 | /* Perform any needed actions needed for a function that is receiving a | |
764 | variable number of arguments. */ | |
765 | #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ | |
766 | mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS) | |
767 | ||
768 | /* Call the function profiler with a given profile label. */ | |
769 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ | |
770 | { \ | |
771 | fprintf (STREAM, " trap 1\n"); \ | |
772 | fprintf (STREAM, " .align 2\n"); \ | |
773 | fprintf (STREAM, " .long LP%d\n", (LABELNO)); \ | |
774 | } | |
775 | ||
776 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
777 | the stack pointer does not matter. The value is tested only in | |
778 | functions that have frame pointers. | |
779 | No definition is equivalent to always zero. */ | |
780 | #define EXIT_IGNORE_STACK 0 | |
781 | ||
782 | /* Output assembler code for a block containing the constant parts | |
783 | of a trampoline, leaving space for the variable parts. | |
784 | ||
dab66575 | 785 | On the MCore, the trampoline looks like: |
8f90be4c NC |
786 | lrw r1, function |
787 | lrw r13, area | |
788 | jmp r13 | |
789 | or r0, r0 | |
790 | .literals */ | |
791 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
792 | { \ | |
793 | fprintf ((FILE), " .short 0x7102\n"); \ | |
794 | fprintf ((FILE), " .short 0x7d02\n"); \ | |
795 | fprintf ((FILE), " .short 0x00cd\n"); \ | |
796 | fprintf ((FILE), " .short 0x1e00\n"); \ | |
797 | fprintf ((FILE), " .long 0\n"); \ | |
798 | fprintf ((FILE), " .long 0\n"); \ | |
799 | } | |
800 | ||
801 | /* Length in units of the trampoline for entering a nested function. */ | |
802 | #define TRAMPOLINE_SIZE 12 | |
803 | ||
006946e4 JM |
804 | /* Alignment required for a trampoline in bits. */ |
805 | #define TRAMPOLINE_ALIGNMENT 32 | |
8f90be4c NC |
806 | |
807 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
808 | FNADDR is an RTX for the address of the function's pure code. | |
809 | CXT is an RTX for the static chain value for the function. */ | |
810 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
811 | { \ | |
812 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ | |
813 | (CXT)); \ | |
814 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ | |
815 | (FNADDR)); \ | |
816 | } | |
817 | ||
818 | /* Macros to check register numbers against specific register classes. */ | |
819 | ||
820 | /* These assume that REGNO is a hard or pseudo reg number. | |
821 | They give nonzero only if REGNO is a hard reg of the suitable class | |
822 | or a pseudo reg currently allocated to a suitable hard reg. | |
823 | Since they use reg_renumber, they are safe only once reg_renumber | |
824 | has been allocated, which happens in local-alloc.c. */ | |
825 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
826 | ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG) | |
827 | ||
828 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
829 | ||
830 | /* Maximum number of registers that can appear in a valid memory | |
831 | address. */ | |
832 | #define MAX_REGS_PER_ADDRESS 1 | |
833 | ||
834 | /* Recognize any constant value that is a valid address. */ | |
835 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) | |
836 | ||
837 | /* Nonzero if the constant value X is a legitimate general operand. | |
838 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
839 | ||
840 | On the MCore, allow anything but a double. */ | |
841 | #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE) | |
842 | ||
843 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) | |
844 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
845 | and check its validity for a certain class. | |
846 | We have two alternate definitions for each of them. | |
847 | The usual definition accepts all pseudo regs; the other rejects | |
848 | them unless they have been allocated suitable hard regs. | |
849 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
850 | #ifndef REG_OK_STRICT | |
851 | ||
852 | /* Nonzero if X is a hard reg that can be used as a base reg | |
853 | or if it is a pseudo reg. */ | |
854 | #define REG_OK_FOR_BASE_P(X) \ | |
855 | (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
856 | ||
857 | /* Nonzero if X is a hard reg that can be used as an index | |
858 | or if it is a pseudo reg. */ | |
859 | #define REG_OK_FOR_INDEX_P(X) 0 | |
860 | ||
861 | #else | |
862 | ||
863 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
864 | #define REG_OK_FOR_BASE_P(X) \ | |
865 | REGNO_OK_FOR_BASE_P (REGNO (X)) | |
866 | ||
867 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
868 | #define REG_OK_FOR_INDEX_P(X) 0 | |
869 | ||
870 | #endif | |
871 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
872 | that is a valid memory address for an instruction. | |
873 | The MODE argument is the machine mode for the MEM expression | |
874 | that wants to use this address. | |
875 | ||
876 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
877 | #define BASE_REGISTER_RTX_P(X) \ | |
878 | (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) | |
879 | ||
880 | #define INDEX_REGISTER_RTX_P(X) \ | |
881 | (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) | |
882 | ||
883 | ||
884 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
885 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
886 | the above macros so we are in luck. | |
887 | ||
888 | Allow REG | |
889 | REG+disp | |
890 | ||
891 | A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60, | |
892 | and for DI is 0..56 because we use two SI loads, etc. */ | |
893 | #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \ | |
894 | do \ | |
895 | { \ | |
896 | if (GET_CODE (OP) == CONST_INT) \ | |
897 | { \ | |
898 | if (GET_MODE_SIZE (MODE) >= 4 \ | |
899 | && (((unsigned)INTVAL (OP)) % 4) == 0 \ | |
900 | && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \ | |
901 | goto LABEL; \ | |
902 | if (GET_MODE_SIZE (MODE) == 2 \ | |
903 | && (((unsigned)INTVAL (OP)) % 2) == 0 \ | |
904 | && ((unsigned)INTVAL (OP)) <= 30) \ | |
905 | goto LABEL; \ | |
906 | if (GET_MODE_SIZE (MODE) == 1 \ | |
907 | && ((unsigned)INTVAL (OP)) <= 15) \ | |
908 | goto LABEL; \ | |
909 | } \ | |
910 | } \ | |
911 | while (0) | |
912 | ||
913 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
914 | { \ | |
915 | if (BASE_REGISTER_RTX_P (X)) \ | |
916 | goto LABEL; \ | |
917 | else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \ | |
918 | { \ | |
919 | rtx xop0 = XEXP (X,0); \ | |
920 | rtx xop1 = XEXP (X,1); \ | |
921 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
922 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
923 | if (BASE_REGISTER_RTX_P (xop1)) \ | |
924 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
925 | } \ | |
926 | } | |
927 | ||
928 | /* Go to LABEL if ADDR (a legitimate address expression) | |
929 | has an effect that depends on the machine mode it is used for. */ | |
930 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
931 | { \ | |
932 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ | |
933 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
934 | goto LABEL; \ | |
935 | } | |
936 | ||
937 | /* Specify the machine mode that this machine uses | |
938 | for the index in the tablejump instruction. */ | |
939 | #define CASE_VECTOR_MODE SImode | |
940 | ||
941 | /* Define this if the tablejump instruction expects the table | |
942 | to contain offsets from the address of the table. | |
943 | Do not define this if the table should contain absolute addresses. */ | |
944 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
945 | ||
8f90be4c NC |
946 | /* 'char' is signed by default. */ |
947 | #define DEFAULT_SIGNED_CHAR 0 | |
948 | ||
949 | /* The type of size_t unsigned int. */ | |
950 | #define SIZE_TYPE "unsigned int" | |
951 | ||
952 | /* Don't cse the address of the function being compiled. */ | |
953 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
954 | ||
955 | /* Max number of bytes we can move from memory to memory | |
956 | in one reasonably fast instruction. */ | |
957 | #define MOVE_MAX 4 | |
958 | ||
959 | /* Define if operations between registers always perform the operation | |
960 | on the full register even if a narrower mode is specified. */ | |
961 | #define WORD_REGISTER_OPERATIONS | |
962 | ||
963 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
964 | will either zero-extend or sign-extend. The value of this macro should | |
965 | be the code that says which one of the two operations is implicitly | |
966 | done, NIL if none. */ | |
967 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
968 | ||
969 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
970 | #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES | |
971 | ||
8f90be4c NC |
972 | /* Immediate shift counts are truncated by the output routines (or was it |
973 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
974 | that the native compiler puts too large (> 32) immediate shift counts | |
975 | into a register and shifts by the register, letting the ARM decide what | |
976 | to do instead of doing that itself. */ | |
977 | #define SHIFT_COUNT_TRUNCATED 1 | |
978 | ||
979 | /* All integers have the same format so truncation is easy. */ | |
980 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
981 | ||
982 | /* Define this if addresses of constant functions | |
983 | shouldn't be put through pseudo regs where they can be cse'd. | |
984 | Desirable on machines where ordinary constants are expensive | |
985 | but a CALL with constant address is cheap. */ | |
986 | /* why is this defined??? -- dac */ | |
987 | #define NO_FUNCTION_CSE 1 | |
988 | ||
989 | /* Chars and shorts should be passed as ints. */ | |
990 | #define PROMOTE_PROTOTYPES 1 | |
991 | ||
992 | /* The machine modes of pointers and functions. */ | |
993 | #define Pmode SImode | |
994 | #define FUNCTION_MODE Pmode | |
995 | ||
8f90be4c NC |
996 | /* Compute extra cost of moving data between one register class |
997 | and another. All register moves are cheap. */ | |
cf011243 | 998 | #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2 |
8f90be4c NC |
999 | |
1000 | #define WORD_REGISTER_OPERATIONS | |
1001 | ||
8f90be4c NC |
1002 | /* Implicit library calls should use memcpy, not bcopy, etc. */ |
1003 | #define TARGET_MEM_FUNCTIONS | |
1004 | ||
1005 | /* Assembler output control. */ | |
1006 | #define ASM_COMMENT_START "\t//" | |
1007 | ||
1008 | #define ASM_APP_ON "// inline asm begin\n" | |
1009 | #define ASM_APP_OFF "// inline asm end\n" | |
1010 | ||
1011 | #define FILE_ASM_OP "\t.file\n" | |
1012 | ||
1013 | /* Switch to the text or data segment. */ | |
1014 | #define TEXT_SECTION_ASM_OP "\t.text" | |
1015 | #define DATA_SECTION_ASM_OP "\t.data" | |
1016 | ||
1017 | #undef EXTRA_SECTIONS | |
2cc07db4 | 1018 | #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS |
8f90be4c NC |
1019 | |
1020 | #undef EXTRA_SECTION_FUNCTIONS | |
1021 | #define EXTRA_SECTION_FUNCTIONS \ | |
8f90be4c NC |
1022 | SUBTARGET_EXTRA_SECTION_FUNCTIONS \ |
1023 | SWITCH_SECTION_FUNCTION | |
1024 | ||
8f90be4c NC |
1025 | /* Switch to SECTION (an `enum in_section'). |
1026 | ||
1027 | ??? This facility should be provided by GCC proper. | |
1028 | The problem is that we want to temporarily switch sections in | |
1029 | ASM_DECLARE_OBJECT_NAME and then switch back to the original section | |
1030 | afterwards. */ | |
1031 | #define SWITCH_SECTION_FUNCTION \ | |
55710451 KG |
1032 | static void switch_to_section PARAMS ((enum in_section, tree)); \ |
1033 | static void \ | |
8f90be4c NC |
1034 | switch_to_section (section, decl) \ |
1035 | enum in_section section; \ | |
1036 | tree decl; \ | |
1037 | { \ | |
1038 | switch (section) \ | |
1039 | { \ | |
1040 | case in_text: text_section (); break; \ | |
1041 | case in_data: data_section (); break; \ | |
1042 | case in_named: named_section (decl, NULL, 0); break; \ | |
8f90be4c NC |
1043 | SUBTARGET_SWITCH_SECTIONS \ |
1044 | default: abort (); break; \ | |
1045 | } \ | |
1046 | } | |
1047 | ||
7c262518 | 1048 | /* Switch into a generic section. */ |
1943c2c1 | 1049 | #undef TARGET_ASM_NAMED_SECTION |
7c262518 | 1050 | #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section |
8f90be4c NC |
1051 | |
1052 | /* This is how to output an insn to push a register on the stack. | |
1053 | It need not be very fast code. */ | |
1054 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1055 | fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \ | |
1056 | reg_names[STACK_POINTER_REGNUM], \ | |
1057 | (STACK_BOUNDARY / BITS_PER_UNIT), \ | |
1058 | reg_names[REGNO], \ | |
1059 | reg_names[STACK_POINTER_REGNUM]) | |
1060 | ||
1061 | /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ | |
1062 | #define REG_PUSH_LENGTH 2 | |
1063 | ||
1064 | /* This is how to output an insn to pop a register from the stack. */ | |
1065 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1066 | fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \ | |
1067 | reg_names[REGNO], \ | |
1068 | reg_names[STACK_POINTER_REGNUM], \ | |
1069 | reg_names[STACK_POINTER_REGNUM], \ | |
1070 | (STACK_BOUNDARY / BITS_PER_UNIT)) | |
1071 | ||
1072 | ||
8f90be4c NC |
1073 | /* Output a reference to a label. */ |
1074 | #undef ASM_OUTPUT_LABELREF | |
1075 | #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
772c5265 RH |
1076 | fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ |
1077 | (* targetm.strip_name_encoding) (NAME)) | |
8f90be4c NC |
1078 | |
1079 | /* This is how to output an assembler line | |
1080 | that says to advance the location counter | |
1081 | to a multiple of 2**LOG bytes. */ | |
1082 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1083 | if ((LOG) != 0) \ | |
1084 | fprintf (FILE, "\t.align\t%d\n", LOG) | |
1085 | ||
1086 | #ifndef ASM_DECLARE_RESULT | |
1087 | #define ASM_DECLARE_RESULT(FILE, RESULT) | |
1088 | #endif | |
1089 | ||
8f90be4c NC |
1090 | #define MULTIPLE_SYMBOL_SPACES 1 |
1091 | ||
1092 | #define SUPPORTS_ONE_ONLY 1 | |
1093 | ||
1094 | /* A pair of macros to output things for the callgraph data. | |
1095 | VALUE means (to the tools that reads this info later): | |
1096 | 0 a call from src to dst | |
1097 | 1 the call is special (e.g. dst is "unknown" or "alloca") | |
1098 | 2 the call is special (e.g., the src is a table instead of routine) | |
1099 | ||
1100 | Frame sizes are augmented with timestamps to help later tools | |
1101 | differentiate between static entities with same names in different | |
1102 | files. */ | |
1103 | extern long mcore_current_compilation_timestamp; | |
1104 | #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \ | |
1105 | do \ | |
1106 | { \ | |
1107 | if (mcore_current_compilation_timestamp == 0) \ | |
1108 | mcore_current_compilation_timestamp = time (0); \ | |
1109 | fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \ | |
1110 | (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \ | |
1111 | } \ | |
1112 | while (0) | |
1113 | ||
1114 | #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \ | |
1115 | do \ | |
1116 | { \ | |
1117 | fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \ | |
1118 | (SRCNAME), (DSTNAME), (VALUE)); \ | |
1119 | } \ | |
1120 | while (0) | |
1121 | ||
506a61b1 KG |
1122 | /* Globalizing directive for a label. */ |
1123 | #define GLOBAL_ASM_OP "\t.export\t" | |
8f90be4c | 1124 | |
31488c64 | 1125 | /* The prefix to add to user-visible assembler symbols. */ |
8f90be4c NC |
1126 | #undef USER_LABEL_PREFIX |
1127 | #define USER_LABEL_PREFIX "" | |
1128 | ||
1129 | /* Make an internal label into a string. */ | |
1130 | #undef ASM_GENERATE_INTERNAL_LABEL | |
1131 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ | |
1132 | sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM) | |
1133 | ||
31488c64 | 1134 | /* Jump tables must be 32 bit aligned. */ |
8f90be4c NC |
1135 | #undef ASM_OUTPUT_CASE_LABEL |
1136 | #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ | |
1137 | fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM); | |
1138 | ||
1139 | /* Output a relative address. Not needed since jump tables are absolute | |
1140 | but we must define it anyway. */ | |
1141 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ | |
1142 | fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) | |
1143 | ||
1144 | /* Output an element of a dispatch table. */ | |
1145 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
1146 | fprintf (STREAM, "\t.long\t.L%d\n", VALUE) | |
1147 | ||
1148 | /* Output various types of constants. */ | |
1149 | ||
8f90be4c NC |
1150 | /* This is how to output an assembler line |
1151 | that says to advance the location counter by SIZE bytes. */ | |
1152 | #undef ASM_OUTPUT_SKIP | |
1153 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 1154 | fprintf (FILE, "\t.fill %d, 1\n", (int)(SIZE)) |
8f90be4c NC |
1155 | |
1156 | /* This says how to output an assembler line | |
1157 | to define a global common symbol, with alignment information. */ | |
1158 | /* XXX - for now we ignore the alignment. */ | |
1159 | #undef ASM_OUTPUT_ALIGNED_COMMON | |
1160 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
1161 | do \ | |
1162 | { \ | |
1163 | if (mcore_dllexport_name_p (NAME)) \ | |
1164 | MCORE_EXPORT_NAME (FILE, NAME) \ | |
1165 | if (! mcore_dllimport_name_p (NAME)) \ | |
1166 | { \ | |
1167 | fputs ("\t.comm\t", FILE); \ | |
1168 | assemble_name (FILE, NAME); \ | |
74eda121 | 1169 | fprintf (FILE, ",%lu\n", (unsigned long)(SIZE)); \ |
8f90be4c NC |
1170 | } \ |
1171 | } \ | |
1172 | while (0) | |
1173 | ||
1174 | /* This says how to output an assembler line | |
1175 | to define an external symbol. */ | |
1176 | #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ | |
1177 | do \ | |
1178 | { \ | |
1179 | fputs ("\t.import\t", (FILE)); \ | |
1180 | assemble_name ((FILE), (NAME)); \ | |
1181 | fputs ("\n", (FILE)); \ | |
1182 | } \ | |
1183 | while (0) | |
1184 | ||
1185 | #undef ASM_OUTPUT_EXTERNAL | |
1186 | /* RBE: we undefined this and let gas do it's "undefined is imported" | |
1187 | games. This is because when we use this, we get a marked | |
1188 | reference through the call to assemble_name and this forces C++ | |
1189 | inlined member functions (or any inlined function) to be instantiated | |
dab66575 | 1190 | regardless of whether any call sites remain. |
8f90be4c NC |
1191 | This makes this aspect of the compiler non-ABI compliant. */ |
1192 | ||
1193 | /* Similar, but for libcall. FUN is an rtx. */ | |
1194 | #undef ASM_OUTPUT_EXTERNAL_LIBCALL | |
1195 | #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ | |
1196 | do \ | |
1197 | { \ | |
1198 | fprintf (FILE, "\t.import\t"); \ | |
1199 | assemble_name (FILE, XSTR (FUN, 0)); \ | |
1200 | fprintf (FILE, "\n"); \ | |
1201 | } \ | |
1202 | while (0) | |
1203 | ||
1204 | ||
1205 | /* This says how to output an assembler line | |
1206 | to define a local common symbol... */ | |
1207 | #undef ASM_OUTPUT_LOCAL | |
1208 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1209 | (fputs ("\t.lcomm\t", FILE), \ | |
1210 | assemble_name (FILE, NAME), \ | |
58e15542 | 1211 | fprintf (FILE, ",%d\n", (int)SIZE)) |
8f90be4c NC |
1212 | |
1213 | /* ... and how to define a local common symbol whose alignment | |
1214 | we wish to specify. ALIGN comes in as bits, we have to turn | |
1215 | it into bytes. */ | |
1216 | #undef ASM_OUTPUT_ALIGNED_LOCAL | |
1217 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ | |
1218 | do \ | |
1219 | { \ | |
1220 | fputs ("\t.bss\t", (FILE)); \ | |
1221 | assemble_name ((FILE), (NAME)); \ | |
58e15542 | 1222 | fprintf ((FILE), ",%d,%d\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ |
8f90be4c NC |
1223 | } \ |
1224 | while (0) | |
1225 | ||
8f90be4c NC |
1226 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1227 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1228 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1229 | #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE) | |
1230 | ||
1231 | /* Print a memory address as an operand to reference that memory location. */ | |
1232 | #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X) | |
1233 | ||
1234 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
1235 | ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!') | |
1236 | ||
8f90be4c NC |
1237 | #define PREDICATE_CODES \ |
1238 | { "mcore_arith_reg_operand", { REG, SUBREG }}, \ | |
1239 | { "mcore_general_movsrc_operand", { MEM, CONST_INT, REG, SUBREG }},\ | |
1240 | { "mcore_general_movdst_operand", { MEM, CONST_INT, REG, SUBREG }},\ | |
1241 | { "mcore_reload_operand", { MEM, REG, SUBREG }}, \ | |
1242 | { "mcore_arith_J_operand", { CONST_INT, REG, SUBREG }}, \ | |
1243 | { "mcore_arith_K_operand", { CONST_INT, REG, SUBREG }}, \ | |
1244 | { "mcore_arith_K_operand_not_0", { CONST_INT, REG, SUBREG }}, \ | |
1245 | { "mcore_arith_M_operand", { CONST_INT, REG, SUBREG }}, \ | |
1246 | { "mcore_arith_K_S_operand", { CONST_INT, REG, SUBREG }}, \ | |
1247 | { "mcore_arith_O_operand", { CONST_INT, REG, SUBREG }}, \ | |
1248 | { "mcore_arith_imm_operand", { CONST_INT, REG, SUBREG }}, \ | |
1249 | { "mcore_arith_any_imm_operand", { CONST_INT, REG, SUBREG }}, \ | |
1250 | { "mcore_literal_K_operand", { CONST_INT }}, \ | |
1251 | { "mcore_addsub_operand", { CONST_INT, REG, SUBREG }}, \ | |
1252 | { "mcore_compare_operand", { CONST_INT, REG, SUBREG }}, \ | |
1253 | { "mcore_load_multiple_operation", { PARALLEL }}, \ | |
1254 | { "mcore_store_multiple_operation", { PARALLEL }}, \ | |
1255 | { "mcore_call_address_operand", { REG, SUBREG, CONST_INT }}, \ | |
1256 | ||
88657302 | 1257 | #endif /* ! GCC_MCORE_H */ |