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8f90be4c NC |
1 | /* Definitions of target machine for GNU compiler, |
2 | for Motorola M*CORE Processor. | |
fe9565ed | 3 | Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
31488c64 | 4 | Free Software Foundation, Inc. |
8f90be4c | 5 | |
31488c64 | 6 | This file is part of GCC. |
8f90be4c | 7 | |
31488c64 NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
8f90be4c | 12 | |
31488c64 NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
8f90be4c | 17 | |
31488c64 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
39d14dda KC |
20 | Free Software Foundation, 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
8f90be4c | 22 | |
88657302 RH |
23 | #ifndef GCC_MCORE_H |
24 | #define GCC_MCORE_H | |
8f90be4c NC |
25 | |
26 | /* RBE: need to move these elsewhere. */ | |
27 | #undef LIKE_PPC_ABI | |
28 | #define MCORE_STRUCT_ARGS | |
29 | /* RBE: end of "move elsewhere". */ | |
30 | ||
8f90be4c NC |
31 | /* Run-time Target Specification. */ |
32 | #define TARGET_MCORE | |
33 | ||
672a6f42 NB |
34 | /* Get tree.c to declare a target-specific specialization of |
35 | merge_decl_attributes. */ | |
b2ca3702 | 36 | #define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1 |
8f90be4c | 37 | |
f7248b51 NB |
38 | #define TARGET_CPU_CPP_BUILTINS() \ |
39 | do \ | |
40 | { \ | |
41 | builtin_define ("__mcore__"); \ | |
42 | builtin_define ("__MCORE__"); \ | |
f7248b51 NB |
43 | if (TARGET_LITTLE_END) \ |
44 | builtin_define ("__MCORELE__"); \ | |
45 | else \ | |
46 | builtin_define ("__MCOREBE__"); \ | |
47 | if (TARGET_M340) \ | |
48 | builtin_define ("__M340__"); \ | |
49 | else \ | |
50 | builtin_define ("__M210__"); \ | |
51 | } \ | |
52 | while (0) | |
8f90be4c | 53 | |
d6a7951f | 54 | /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC |
08903e08 | 55 | %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}. */ |
31488c64 NC |
56 | #undef CPP_SPEC |
57 | #define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}" | |
8f90be4c NC |
58 | |
59 | /* We don't have a -lg library, so don't put it in the list. */ | |
60 | #undef LIB_SPEC | |
61 | #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" | |
62 | ||
63 | #undef ASM_SPEC | |
64 | #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}" | |
65 | ||
66 | #undef LINK_SPEC | |
67 | #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X" | |
68 | ||
78fb8038 RS |
69 | #define TARGET_DEFAULT \ |
70 | (MASK_HARDLIT \ | |
71 | | MASK_8ALIGN \ | |
72 | | MASK_DIV \ | |
73 | | MASK_RELAX_IMM \ | |
74 | | MASK_M340 \ | |
75 | | MASK_LITTLE_END) | |
8f90be4c NC |
76 | |
77 | #ifndef MULTILIB_DEFAULTS | |
78 | #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" } | |
79 | #endif | |
80 | ||
8f90be4c | 81 | /* The ability to have 4 byte alignment is being suppressed for now. |
78fb8038 | 82 | If this ability is reenabled, you must disable the definition below |
8f90be4c | 83 | *and* edit t-mcore to enable multilibs for 4 byte alignment code. */ |
78fb8038 RS |
84 | #undef TARGET_8ALIGN |
85 | #define TARGET_8ALIGN 1 | |
8f90be4c NC |
86 | |
87 | extern char * mcore_current_function_name; | |
88 | ||
56ae9405 NC |
89 | /* The MCore ABI says that bitfields are unsigned by default. */ |
90 | #define CC1_SPEC "-funsigned-bitfields" | |
8f90be4c NC |
91 | |
92 | /* What options are we going to default to specific settings when | |
93 | -O* happens; the user can subsequently override these settings. | |
94 | ||
95 | Omitting the frame pointer is a very good idea on the MCore. | |
96 | Scheduling isn't worth anything on the current MCore implementation. */ | |
97 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ | |
98 | { \ | |
99 | if (LEVEL) \ | |
100 | { \ | |
101 | flag_no_function_cse = 1; \ | |
102 | flag_omit_frame_pointer = 1; \ | |
103 | \ | |
104 | if (LEVEL >= 2) \ | |
105 | { \ | |
106 | flag_caller_saves = 0; \ | |
107 | flag_schedule_insns = 0; \ | |
108 | flag_schedule_insns_after_reload = 0; \ | |
109 | } \ | |
110 | } \ | |
111 | if (SIZE) \ | |
112 | { \ | |
78fb8038 | 113 | target_flags &= ~MASK_HARDLIT; \ |
8f90be4c NC |
114 | } \ |
115 | } | |
116 | ||
117 | /* What options are we going to force to specific settings, | |
118 | regardless of what the user thought he wanted. | |
31488c64 | 119 | We also use this for some post-processing of options. */ |
8f90be4c NC |
120 | #define OVERRIDE_OPTIONS mcore_override_options () |
121 | ||
122 | /* Target machine storage Layout. */ | |
123 | ||
8f90be4c NC |
124 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
125 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
126 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
127 | { \ | |
128 | (MODE) = SImode; \ | |
129 | (UNSIGNEDP) = 1; \ | |
130 | } | |
131 | ||
8f90be4c NC |
132 | /* Define this if most significant bit is lowest numbered |
133 | in instructions that operate on numbered bit-fields. */ | |
134 | #define BITS_BIG_ENDIAN 0 | |
135 | ||
136 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
137 | #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END) | |
138 | ||
139 | /* Define this if most significant word of a multiword number is the lowest | |
140 | numbered. */ | |
141 | #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END) | |
142 | ||
143 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
144 | #ifdef __MCORELE__ | |
145 | #undef LIBGCC2_WORDS_BIG_ENDIAN | |
146 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
147 | #endif | |
148 | ||
8f90be4c NC |
149 | #define MAX_BITS_PER_WORD 32 |
150 | ||
151 | /* Width of a word, in units (bytes). */ | |
152 | #define UNITS_PER_WORD 4 | |
153 | ||
8f90be4c NC |
154 | /* A C expression for the size in bits of the type `long long' on the |
155 | target machine. If you don't define this, the default is two | |
156 | words. */ | |
157 | #define LONG_LONG_TYPE_SIZE 64 | |
158 | ||
8f90be4c NC |
159 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
160 | #define PARM_BOUNDARY 32 | |
161 | ||
dab66575 | 162 | /* Doubles must be aligned to an 8 byte boundary. */ |
8f90be4c NC |
163 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
164 | ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \ | |
165 | ? BIGGEST_ALIGNMENT : PARM_BOUNDARY) | |
166 | ||
167 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
168 | #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) | |
169 | ||
170 | /* Largest increment in UNITS we allow the stack to grow in a single operation. */ | |
171 | extern int mcore_stack_increment; | |
172 | #define STACK_UNITS_MAXSTEP 4096 | |
173 | ||
174 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
175 | #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16) | |
176 | ||
177 | /* Alignment of field after `int : 0' in a structure. */ | |
178 | #define EMPTY_FIELD_BOUNDARY 32 | |
179 | ||
180 | /* No data type wants to be aligned rounder than this. */ | |
181 | #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32) | |
182 | ||
183 | /* The best alignment to use in cases where we have a choice. */ | |
184 | #define FASTEST_ALIGNMENT 32 | |
185 | ||
186 | /* Every structures size must be a multiple of 8 bits. */ | |
187 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
188 | ||
43a88a8c | 189 | /* Look at the fundamental type that is used for a bit-field and use |
8f90be4c NC |
190 | that to impose alignment on the enclosing structure. |
191 | struct s {int a:8}; should have same alignment as "int", not "char". */ | |
192 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
193 | ||
194 | /* Largest integer machine mode for structures. If undefined, the default | |
195 | is GET_MODE_SIZE(DImode). */ | |
196 | #define MAX_FIXED_MODE_SIZE 32 | |
197 | ||
198 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
199 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
200 | ((TREE_CODE (EXP) == STRING_CST \ | |
201 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
202 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
203 | ||
204 | /* Make arrays of chars word-aligned for the same reasons. */ | |
205 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
206 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
207 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
208 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
209 | ||
210 | /* Set this nonzero if move instructions will actually fail to work | |
211 | when given unaligned data. */ | |
212 | #define STRICT_ALIGNMENT 1 | |
213 | ||
214 | /* Standard register usage. */ | |
215 | ||
216 | /* Register allocation for our first guess | |
217 | ||
218 | r0 stack pointer | |
219 | r1 scratch, target reg for xtrb? | |
220 | r2-r7 arguments. | |
221 | r8-r14 call saved | |
222 | r15 link register | |
223 | ap arg pointer (doesn't really exist, always eliminated) | |
224 | c c bit | |
225 | fp frame pointer (doesn't really exist, always eliminated) | |
08903e08 | 226 | x19 two control registers. */ |
8f90be4c NC |
227 | |
228 | /* Number of actual hardware registers. | |
229 | The hardware registers are assigned numbers for the compiler | |
230 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
231 | All registers that the compiler knows about must be given numbers, | |
232 | even those that are not normally considered general registers. | |
233 | ||
234 | MCore has 16 integer registers and 2 control registers + the arg | |
235 | pointer. */ | |
236 | ||
237 | #define FIRST_PSEUDO_REGISTER 20 | |
238 | ||
08903e08 SB |
239 | #define R1_REG 1 /* Where literals are forced. */ |
240 | #define LK_REG 15 /* Overloaded on general register. */ | |
241 | #define AP_REG 16 /* Fake arg pointer register. */ | |
242 | /* RBE: mcore.md depends on CC_REG being set to 17. */ | |
243 | #define CC_REG 17 /* Can't name it C_REG. */ | |
244 | #define FP_REG 18 /* Fake frame pointer register. */ | |
8f90be4c NC |
245 | |
246 | /* Specify the registers used for certain standard purposes. | |
247 | The values of these macros are register numbers. */ | |
248 | ||
249 | ||
250 | #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */ | |
251 | #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */ | |
252 | #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */ | |
253 | ||
254 | /* The assembler's names for the registers. RFP need not always be used as | |
255 | the Real framepointer; it can also be used as a normal general register. | |
256 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
257 | the argument-and-return-context pointer. */ | |
258 | #define REGISTER_NAMES \ | |
259 | { \ | |
260 | "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
261 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
262 | "apvirtual", "c", "fpvirtual", "x19" \ | |
263 | } | |
264 | ||
265 | /* 1 for registers that have pervasive standard uses | |
266 | and are not available for the register allocator. */ | |
267 | #define FIXED_REGISTERS \ | |
268 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
269 | { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
270 | ||
271 | /* 1 for registers not available across function calls. | |
272 | These must include the FIXED_REGISTERS and also any | |
273 | registers that can be used without being saved. | |
274 | The latter must include the registers where values are returned | |
275 | and the register where structure-value addresses are passed. | |
276 | Aside from that, you can include as many other registers as you like. */ | |
277 | ||
278 | /* RBE: r15 {link register} not available across calls, | |
14bc6742 | 279 | But we don't mark it that way here.... */ |
8f90be4c NC |
280 | #define CALL_USED_REGISTERS \ |
281 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
282 | { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
283 | ||
284 | /* The order in which register should be allocated. */ | |
285 | #define REG_ALLOC_ORDER \ | |
286 | /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \ | |
287 | { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19} | |
288 | ||
289 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
290 | to hold something of mode MODE. | |
291 | This is ordinarily the length in words of a value of mode MODE | |
292 | but can be less for certain modes in special long registers. | |
293 | ||
294 | On the MCore regs are UNITS_PER_WORD bits wide; */ | |
295 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
296 | (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
297 | ||
298 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
299 | We may keep double values in even registers. */ | |
300 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
301 | ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18)) | |
302 | ||
303 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
304 | when one has mode MODE1 and one has mode MODE2. | |
305 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
306 | for any hard reg, then this must be 0 for correct output. */ | |
307 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
308 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
309 | ||
310 | /* Value should be nonzero if functions must have frame pointers. | |
311 | Zero means the frame pointer need not be set up (and parms may be accessed | |
312 | via the stack pointer) in functions that seem suitable. */ | |
313 | #define FRAME_POINTER_REQUIRED 0 | |
314 | ||
315 | /* Definitions for register eliminations. | |
316 | ||
317 | We have two registers that can be eliminated on the MCore. First, the | |
318 | frame pointer register can often be eliminated in favor of the stack | |
319 | pointer register. Secondly, the argument pointer register can always be | |
320 | eliminated; it is replaced with either the stack or frame pointer. */ | |
321 | ||
322 | /* Base register for access to arguments of the function. */ | |
323 | #define ARG_POINTER_REGNUM 16 | |
324 | ||
325 | /* Register in which the static-chain is passed to a function. */ | |
326 | #define STATIC_CHAIN_REGNUM 1 | |
327 | ||
328 | /* This is an array of structures. Each structure initializes one pair | |
329 | of eliminable registers. The "from" register number is given first, | |
330 | followed by "to". Eliminations of the same "from" register are listed | |
331 | in order of preference. */ | |
332 | #define ELIMINABLE_REGS \ | |
333 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
334 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
335 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
336 | ||
337 | /* Given FROM and TO register numbers, say whether this elimination | |
338 | is allowed. */ | |
339 | #define CAN_ELIMINATE(FROM, TO) \ | |
340 | (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) | |
341 | ||
342 | /* Define the offset between two registers, one to be eliminated, and the other | |
343 | its replacement, at the start of a routine. */ | |
344 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
345 | OFFSET = mcore_initial_elimination_offset (FROM, TO) | |
346 | ||
8f90be4c NC |
347 | /* Define the classes of registers for register constraints in the |
348 | machine description. Also define ranges of constants. | |
349 | ||
350 | One of the classes must always be named ALL_REGS and include all hard regs. | |
351 | If there is more than one class, another class must be named NO_REGS | |
352 | and contain no registers. | |
353 | ||
354 | The name GENERAL_REGS must be the name of a class (or an alias for | |
355 | another name such as ALL_REGS). This is the class of registers | |
356 | that is allowed by "g" or "r" in a register constraint. | |
357 | Also, registers outside this class are allocated only when | |
358 | instructions express preferences for them. | |
359 | ||
360 | The classes must be numbered in nondecreasing order; that is, | |
361 | a larger-numbered class must never be contained completely | |
362 | in a smaller-numbered class. | |
363 | ||
364 | For any two classes, it is very desirable that there be another | |
365 | class that represents their union. */ | |
366 | ||
367 | /* The MCore has only general registers. There are | |
368 | also some special purpose registers: the T bit register, the | |
08903e08 | 369 | procedure Link and the Count Registers. */ |
8f90be4c NC |
370 | enum reg_class |
371 | { | |
372 | NO_REGS, | |
373 | ONLYR1_REGS, | |
374 | LRW_REGS, | |
375 | GENERAL_REGS, | |
376 | C_REGS, | |
377 | ALL_REGS, | |
378 | LIM_REG_CLASSES | |
379 | }; | |
380 | ||
381 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
382 | ||
14bc6742 | 383 | /* Give names of register classes as strings for dump file. */ |
8f90be4c NC |
384 | #define REG_CLASS_NAMES \ |
385 | { \ | |
386 | "NO_REGS", \ | |
387 | "ONLYR1_REGS", \ | |
388 | "LRW_REGS", \ | |
389 | "GENERAL_REGS", \ | |
390 | "C_REGS", \ | |
391 | "ALL_REGS", \ | |
392 | } | |
393 | ||
394 | /* Define which registers fit in which classes. | |
395 | This is an initializer for a vector of HARD_REG_SET | |
396 | of length N_REG_CLASSES. */ | |
397 | ||
398 | /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */ | |
399 | #define REG_CLASS_CONTENTS \ | |
400 | { \ | |
401 | {0x000000}, /* NO_REGS */ \ | |
402 | {0x000002}, /* ONLYR1_REGS */ \ | |
403 | {0x007FFE}, /* LRW_REGS */ \ | |
404 | {0x01FFFF}, /* GENERAL_REGS */ \ | |
405 | {0x020000}, /* C_REGS */ \ | |
406 | {0x0FFFFF} /* ALL_REGS */ \ | |
407 | } | |
408 | ||
409 | /* The same information, inverted: | |
410 | Return the class number of the smallest class containing | |
411 | reg number REGNO. This could be a conditional expression | |
412 | or could index an array. */ | |
413 | ||
0139adca | 414 | extern const int regno_reg_class[FIRST_PSEUDO_REGISTER]; |
8f90be4c NC |
415 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO] |
416 | ||
417 | /* When defined, the compiler allows registers explicitly used in the | |
418 | rtl to be used as spill registers but prevents the compiler from | |
419 | extending the lifetime of these registers. */ | |
420 | #define SMALL_REGISTER_CLASSES 1 | |
421 | ||
422 | /* The class value for index registers, and the one for base regs. */ | |
423 | #define INDEX_REG_CLASS NO_REGS | |
424 | #define BASE_REG_CLASS GENERAL_REGS | |
425 | ||
426 | /* Get reg_class from a letter such as appears in the machine | |
427 | description. */ | |
0b5826ac | 428 | extern const enum reg_class reg_class_from_letter[]; |
8f90be4c NC |
429 | |
430 | #define REG_CLASS_FROM_LETTER(C) \ | |
31488c64 | 431 | (ISLOWER (C) ? reg_class_from_letter[(C) - 'a'] : NO_REGS) |
8f90be4c NC |
432 | |
433 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
434 | can be used to stand for particular ranges of immediate operands. | |
435 | This macro defines what the ranges are. | |
436 | C is the letter, and VALUE is a constant value. | |
437 | Return 1 if VALUE is in the range specified by C. | |
438 | I: loadable by movi (0..127) | |
439 | J: arithmetic operand 1..32 | |
440 | K: shift operand 0..31 | |
441 | L: negative arithmetic operand -1..-32 | |
442 | M: powers of two, constants loadable by bgeni | |
443 | N: powers of two minus 1, constants loadable by bmaski, including -1 | |
444 | O: allowed by cmov with two constants +/- 1 of each other | |
445 | P: values we will generate 'inline' -- without an 'lrw' | |
446 | ||
447 | Others defined for use after reload | |
448 | Q: constant 1 | |
449 | R: a label | |
450 | S: 0/1/2 cleared bits out of 32 [for bclri's] | |
451 | T: 2 set bits out of 32 [for bseti's] | |
452 | U: constant 0 | |
453 | xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri | |
454 | xxxT: 2 cleared bits out of 32. for pairs of bclris. */ | |
455 | #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f) | |
456 | #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32) | |
457 | #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32) | |
458 | #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31) | |
459 | #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0) | |
460 | #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0) | |
461 | #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \ | |
462 | CONST_OK_FOR_M(VALUE) || \ | |
463 | CONST_OK_FOR_N(VALUE) || \ | |
464 | CONST_OK_FOR_M((int)(VALUE) - 1) || \ | |
465 | CONST_OK_FOR_N((int)(VALUE) + 1)) | |
466 | ||
467 | #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE)) | |
468 | ||
469 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
470 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
471 | : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ | |
472 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
473 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
474 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
475 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
476 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ | |
477 | : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ | |
478 | : 0) | |
479 | ||
480 | /* Similar, but for floating constants, and defining letters G and H. | |
481 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
482 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
483 | ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \ | |
484 | && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \ | |
485 | : 0) | |
486 | ||
487 | /* Letters in the range `Q' through `U' in a register constraint string | |
488 | may be defined in a machine-dependent fashion to stand for arbitrary | |
489 | operand types. */ | |
490 | #define EXTRA_CONSTRAINT(OP, C) \ | |
491 | ((C) == 'R' ? (GET_CODE (OP) == MEM \ | |
492 | && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \ | |
493 | : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \ | |
494 | && mcore_num_zeros (INTVAL (OP)) <= 2) \ | |
495 | : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \ | |
496 | && mcore_num_ones (INTVAL (OP)) == 2) \ | |
497 | : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \ | |
498 | && INTVAL(OP) == 1) \ | |
499 | : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \ | |
500 | && INTVAL(OP) == 0) \ | |
501 | : 0) | |
502 | ||
503 | /* Given an rtx X being reloaded into a reg required to be | |
504 | in class CLASS, return the class of reg to actually use. | |
505 | In general this is just CLASS; but on some machines | |
506 | in some cases it is preferable to use a more restrictive class. */ | |
507 | #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS) | |
508 | ||
509 | /* Return the register class of a scratch register needed to copy IN into | |
510 | or out of a register in CLASS in MODE. If it can be done directly, | |
511 | NO_REGS is returned. */ | |
f0f4da32 RS |
512 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ |
513 | mcore_secondary_reload_class (CLASS, MODE, X) | |
8f90be4c NC |
514 | |
515 | /* Return the maximum number of consecutive registers | |
516 | needed to represent mode MODE in a register of class CLASS. | |
517 | ||
518 | On MCore this is the size of MODE in words. */ | |
519 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
520 | (ROUND_ADVANCE (GET_MODE_SIZE (MODE))) | |
521 | ||
522 | /* Stack layout; function entry, exit and calling. */ | |
523 | ||
524 | /* Define the number of register that can hold parameters. | |
525 | These two macros are used only in other macro definitions below. */ | |
526 | #define NPARM_REGS 6 | |
527 | #define FIRST_PARM_REG 2 | |
528 | #define FIRST_RET_REG 2 | |
529 | ||
530 | /* Define this if pushing a word on the stack | |
531 | makes the stack pointer a smaller address. */ | |
532 | #define STACK_GROWS_DOWNWARD | |
533 | ||
8f90be4c NC |
534 | /* Offset within stack frame to start allocating local variables at. |
535 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
536 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
537 | of the first local allocated. */ | |
538 | #define STARTING_FRAME_OFFSET 0 | |
539 | ||
540 | /* If defined, the maximum amount of space required for outgoing arguments | |
541 | will be computed and placed into the variable | |
542 | `current_function_outgoing_args_size'. No space will be pushed | |
543 | onto the stack for each call; instead, the function prologue should | |
544 | increase the stack frame size by this amount. */ | |
f73ad30e | 545 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8f90be4c NC |
546 | |
547 | /* Offset of first parameter from the argument pointer register value. */ | |
548 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
549 | ||
550 | /* Value is the number of byte of arguments automatically | |
551 | popped when returning from a subroutine call. | |
552 | FUNTYPE is the data type of the function (as a tree), | |
553 | or for a library call it is an identifier node for the subroutine name. | |
554 | SIZE is the number of bytes of arguments passed on the stack. | |
555 | ||
556 | On the MCore, the callee does not pop any of its arguments that were passed | |
557 | on the stack. */ | |
558 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
559 | ||
560 | /* Define how to find the value returned by a function. | |
561 | VALTYPE is the data type of the value (as a tree). | |
562 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
563 | otherwise, FUNC is 0. */ | |
564 | #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC) | |
565 | ||
566 | /* Don't default to pcc-struct-return, because gcc is the only compiler, and | |
567 | we want to retain compatibility with older gcc versions. */ | |
568 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
569 | ||
8f90be4c NC |
570 | /* Define how to find the value returned by a library function |
571 | assuming the value has mode MODE. */ | |
f1c25d3b | 572 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG) |
8f90be4c NC |
573 | |
574 | /* 1 if N is a possible register number for a function value. | |
575 | On the MCore, only r4 can return results. */ | |
576 | #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) | |
577 | ||
8f90be4c NC |
578 | /* 1 if N is a possible register number for function argument passing. */ |
579 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
580 | ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) | |
581 | ||
582 | /* Define a data type for recording info about an argument list | |
583 | during the scan of that argument list. This data type should | |
584 | hold all necessary information about the function itself | |
585 | and about the args processed so far, enough to enable macros | |
586 | such as FUNCTION_ARG to determine where the next arg should go. | |
587 | ||
588 | On MCore, this is a single integer, which is a number of words | |
589 | of arguments scanned so far (including the invisible argument, | |
590 | if any, which holds the structure-value-address). | |
591 | Thus NARGREGS or more means all following args should go on the stack. */ | |
592 | #define CUMULATIVE_ARGS int | |
593 | ||
594 | #define ROUND_ADVANCE(SIZE) \ | |
595 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
596 | ||
597 | /* Round a register number up to a proper boundary for an arg of mode | |
598 | MODE. | |
599 | ||
600 | We round to an even reg for things larger than a word. */ | |
601 | #define ROUND_REG(X, MODE) \ | |
602 | ((TARGET_8ALIGN \ | |
603 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
604 | ? ((X) + ((X) & 1)) : (X)) | |
605 | ||
606 | ||
607 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
608 | for a call to a function whose data type is FNTYPE. | |
609 | For a library call, FNTYPE is 0. | |
610 | ||
611 | On MCore, the offset always starts at 0: the first parm reg is always | |
612 | the same reg. */ | |
0f6937fe | 613 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
8f90be4c NC |
614 | ((CUM) = 0) |
615 | ||
616 | /* Update the data in CUM to advance over an argument | |
617 | of mode MODE and data type TYPE. | |
618 | (TYPE is null for libcalls where that information may not be | |
619 | available.) */ | |
620 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
621 | ((CUM) = (ROUND_REG ((CUM), (MODE)) \ | |
622 | + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \ | |
623 | ||
624 | /* Define where to put the arguments to a function. */ | |
625 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
626 | mcore_function_arg (CUM, MODE, TYPE, NAMED) | |
8f90be4c | 627 | |
8f90be4c NC |
628 | /* Call the function profiler with a given profile label. */ |
629 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ | |
630 | { \ | |
631 | fprintf (STREAM, " trap 1\n"); \ | |
632 | fprintf (STREAM, " .align 2\n"); \ | |
633 | fprintf (STREAM, " .long LP%d\n", (LABELNO)); \ | |
634 | } | |
635 | ||
636 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
637 | the stack pointer does not matter. The value is tested only in | |
638 | functions that have frame pointers. | |
639 | No definition is equivalent to always zero. */ | |
640 | #define EXIT_IGNORE_STACK 0 | |
641 | ||
642 | /* Output assembler code for a block containing the constant parts | |
643 | of a trampoline, leaving space for the variable parts. | |
644 | ||
dab66575 | 645 | On the MCore, the trampoline looks like: |
8f90be4c NC |
646 | lrw r1, function |
647 | lrw r13, area | |
648 | jmp r13 | |
649 | or r0, r0 | |
650 | .literals */ | |
651 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
652 | { \ | |
653 | fprintf ((FILE), " .short 0x7102\n"); \ | |
654 | fprintf ((FILE), " .short 0x7d02\n"); \ | |
655 | fprintf ((FILE), " .short 0x00cd\n"); \ | |
656 | fprintf ((FILE), " .short 0x1e00\n"); \ | |
657 | fprintf ((FILE), " .long 0\n"); \ | |
658 | fprintf ((FILE), " .long 0\n"); \ | |
659 | } | |
660 | ||
661 | /* Length in units of the trampoline for entering a nested function. */ | |
662 | #define TRAMPOLINE_SIZE 12 | |
663 | ||
006946e4 JM |
664 | /* Alignment required for a trampoline in bits. */ |
665 | #define TRAMPOLINE_ALIGNMENT 32 | |
8f90be4c NC |
666 | |
667 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
668 | FNADDR is an RTX for the address of the function's pure code. | |
669 | CXT is an RTX for the static chain value for the function. */ | |
670 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
671 | { \ | |
f1c25d3b | 672 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \ |
8f90be4c | 673 | (CXT)); \ |
f1c25d3b | 674 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \ |
8f90be4c NC |
675 | (FNADDR)); \ |
676 | } | |
677 | ||
678 | /* Macros to check register numbers against specific register classes. */ | |
679 | ||
680 | /* These assume that REGNO is a hard or pseudo reg number. | |
681 | They give nonzero only if REGNO is a hard reg of the suitable class | |
682 | or a pseudo reg currently allocated to a suitable hard reg. | |
683 | Since they use reg_renumber, they are safe only once reg_renumber | |
684 | has been allocated, which happens in local-alloc.c. */ | |
685 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
686 | ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG) | |
687 | ||
688 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
689 | ||
690 | /* Maximum number of registers that can appear in a valid memory | |
691 | address. */ | |
692 | #define MAX_REGS_PER_ADDRESS 1 | |
693 | ||
694 | /* Recognize any constant value that is a valid address. */ | |
695 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) | |
696 | ||
697 | /* Nonzero if the constant value X is a legitimate general operand. | |
698 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
699 | ||
700 | On the MCore, allow anything but a double. */ | |
701 | #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE) | |
702 | ||
8f90be4c NC |
703 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
704 | and check its validity for a certain class. | |
705 | We have two alternate definitions for each of them. | |
706 | The usual definition accepts all pseudo regs; the other rejects | |
707 | them unless they have been allocated suitable hard regs. | |
708 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
709 | #ifndef REG_OK_STRICT | |
710 | ||
711 | /* Nonzero if X is a hard reg that can be used as a base reg | |
712 | or if it is a pseudo reg. */ | |
713 | #define REG_OK_FOR_BASE_P(X) \ | |
714 | (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
715 | ||
716 | /* Nonzero if X is a hard reg that can be used as an index | |
717 | or if it is a pseudo reg. */ | |
718 | #define REG_OK_FOR_INDEX_P(X) 0 | |
719 | ||
720 | #else | |
721 | ||
722 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
723 | #define REG_OK_FOR_BASE_P(X) \ | |
724 | REGNO_OK_FOR_BASE_P (REGNO (X)) | |
725 | ||
726 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
727 | #define REG_OK_FOR_INDEX_P(X) 0 | |
728 | ||
729 | #endif | |
730 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
731 | that is a valid memory address for an instruction. | |
732 | The MODE argument is the machine mode for the MEM expression | |
733 | that wants to use this address. | |
734 | ||
735 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
736 | #define BASE_REGISTER_RTX_P(X) \ | |
737 | (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) | |
738 | ||
739 | #define INDEX_REGISTER_RTX_P(X) \ | |
740 | (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) | |
741 | ||
742 | ||
743 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
744 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
745 | the above macros so we are in luck. | |
746 | ||
747 | Allow REG | |
748 | REG+disp | |
749 | ||
750 | A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60, | |
751 | and for DI is 0..56 because we use two SI loads, etc. */ | |
752 | #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \ | |
753 | do \ | |
754 | { \ | |
755 | if (GET_CODE (OP) == CONST_INT) \ | |
756 | { \ | |
757 | if (GET_MODE_SIZE (MODE) >= 4 \ | |
758 | && (((unsigned)INTVAL (OP)) % 4) == 0 \ | |
759 | && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \ | |
760 | goto LABEL; \ | |
761 | if (GET_MODE_SIZE (MODE) == 2 \ | |
762 | && (((unsigned)INTVAL (OP)) % 2) == 0 \ | |
763 | && ((unsigned)INTVAL (OP)) <= 30) \ | |
764 | goto LABEL; \ | |
765 | if (GET_MODE_SIZE (MODE) == 1 \ | |
766 | && ((unsigned)INTVAL (OP)) <= 15) \ | |
767 | goto LABEL; \ | |
768 | } \ | |
769 | } \ | |
770 | while (0) | |
771 | ||
772 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
773 | { \ | |
774 | if (BASE_REGISTER_RTX_P (X)) \ | |
775 | goto LABEL; \ | |
776 | else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \ | |
777 | { \ | |
778 | rtx xop0 = XEXP (X,0); \ | |
779 | rtx xop1 = XEXP (X,1); \ | |
780 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
781 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
782 | if (BASE_REGISTER_RTX_P (xop1)) \ | |
783 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
784 | } \ | |
785 | } | |
786 | ||
787 | /* Go to LABEL if ADDR (a legitimate address expression) | |
788 | has an effect that depends on the machine mode it is used for. */ | |
789 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
790 | { \ | |
791 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ | |
792 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
793 | goto LABEL; \ | |
794 | } | |
795 | ||
796 | /* Specify the machine mode that this machine uses | |
797 | for the index in the tablejump instruction. */ | |
798 | #define CASE_VECTOR_MODE SImode | |
799 | ||
8f90be4c NC |
800 | /* 'char' is signed by default. */ |
801 | #define DEFAULT_SIGNED_CHAR 0 | |
802 | ||
803 | /* The type of size_t unsigned int. */ | |
804 | #define SIZE_TYPE "unsigned int" | |
805 | ||
8f90be4c NC |
806 | /* Max number of bytes we can move from memory to memory |
807 | in one reasonably fast instruction. */ | |
808 | #define MOVE_MAX 4 | |
809 | ||
810 | /* Define if operations between registers always perform the operation | |
811 | on the full register even if a narrower mode is specified. */ | |
812 | #define WORD_REGISTER_OPERATIONS | |
813 | ||
814 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
815 | will either zero-extend or sign-extend. The value of this macro should | |
816 | be the code that says which one of the two operations is implicitly | |
f822d252 | 817 | done, UNKNOWN if none. */ |
8f90be4c NC |
818 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
819 | ||
820 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
821 | #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES | |
822 | ||
8f90be4c NC |
823 | /* Immediate shift counts are truncated by the output routines (or was it |
824 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
825 | that the native compiler puts too large (> 32) immediate shift counts | |
826 | into a register and shifts by the register, letting the ARM decide what | |
827 | to do instead of doing that itself. */ | |
828 | #define SHIFT_COUNT_TRUNCATED 1 | |
829 | ||
830 | /* All integers have the same format so truncation is easy. */ | |
831 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
832 | ||
833 | /* Define this if addresses of constant functions | |
834 | shouldn't be put through pseudo regs where they can be cse'd. | |
835 | Desirable on machines where ordinary constants are expensive | |
836 | but a CALL with constant address is cheap. */ | |
14bc6742 | 837 | /* Why is this defined??? -- dac */ |
8f90be4c NC |
838 | #define NO_FUNCTION_CSE 1 |
839 | ||
8f90be4c NC |
840 | /* The machine modes of pointers and functions. */ |
841 | #define Pmode SImode | |
842 | #define FUNCTION_MODE Pmode | |
843 | ||
8f90be4c NC |
844 | /* Compute extra cost of moving data between one register class |
845 | and another. All register moves are cheap. */ | |
cf011243 | 846 | #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2 |
8f90be4c NC |
847 | |
848 | #define WORD_REGISTER_OPERATIONS | |
849 | ||
8f90be4c NC |
850 | /* Assembler output control. */ |
851 | #define ASM_COMMENT_START "\t//" | |
852 | ||
853 | #define ASM_APP_ON "// inline asm begin\n" | |
854 | #define ASM_APP_OFF "// inline asm end\n" | |
855 | ||
856 | #define FILE_ASM_OP "\t.file\n" | |
857 | ||
858 | /* Switch to the text or data segment. */ | |
859 | #define TEXT_SECTION_ASM_OP "\t.text" | |
860 | #define DATA_SECTION_ASM_OP "\t.data" | |
861 | ||
862 | #undef EXTRA_SECTIONS | |
2cc07db4 | 863 | #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS |
8f90be4c NC |
864 | |
865 | #undef EXTRA_SECTION_FUNCTIONS | |
866 | #define EXTRA_SECTION_FUNCTIONS \ | |
8f90be4c NC |
867 | SUBTARGET_EXTRA_SECTION_FUNCTIONS \ |
868 | SWITCH_SECTION_FUNCTION | |
869 | ||
8f90be4c NC |
870 | /* Switch to SECTION (an `enum in_section'). |
871 | ||
872 | ??? This facility should be provided by GCC proper. | |
873 | The problem is that we want to temporarily switch sections in | |
874 | ASM_DECLARE_OBJECT_NAME and then switch back to the original section | |
875 | afterwards. */ | |
876 | #define SWITCH_SECTION_FUNCTION \ | |
08903e08 | 877 | static void switch_to_section (enum in_section, tree); \ |
55710451 | 878 | static void \ |
08903e08 | 879 | switch_to_section (enum in_section section, tree decl) \ |
8f90be4c NC |
880 | { \ |
881 | switch (section) \ | |
882 | { \ | |
883 | case in_text: text_section (); break; \ | |
9fb32434 | 884 | case in_unlikely_executed_text: unlikely_text_section (); break; \ |
8f90be4c NC |
885 | case in_data: data_section (); break; \ |
886 | case in_named: named_section (decl, NULL, 0); break; \ | |
8f90be4c | 887 | SUBTARGET_SWITCH_SECTIONS \ |
6e1f65b5 | 888 | default: gcc_unreachable (); \ |
8f90be4c NC |
889 | } \ |
890 | } | |
891 | ||
7c262518 | 892 | /* Switch into a generic section. */ |
1943c2c1 | 893 | #undef TARGET_ASM_NAMED_SECTION |
7c262518 | 894 | #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section |
8f90be4c NC |
895 | |
896 | /* This is how to output an insn to push a register on the stack. | |
897 | It need not be very fast code. */ | |
898 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
899 | fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \ | |
900 | reg_names[STACK_POINTER_REGNUM], \ | |
901 | (STACK_BOUNDARY / BITS_PER_UNIT), \ | |
902 | reg_names[REGNO], \ | |
903 | reg_names[STACK_POINTER_REGNUM]) | |
904 | ||
905 | /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ | |
906 | #define REG_PUSH_LENGTH 2 | |
907 | ||
908 | /* This is how to output an insn to pop a register from the stack. */ | |
909 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
910 | fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \ | |
911 | reg_names[REGNO], \ | |
912 | reg_names[STACK_POINTER_REGNUM], \ | |
913 | reg_names[STACK_POINTER_REGNUM], \ | |
914 | (STACK_BOUNDARY / BITS_PER_UNIT)) | |
915 | ||
916 | ||
8f90be4c NC |
917 | /* Output a reference to a label. */ |
918 | #undef ASM_OUTPUT_LABELREF | |
919 | #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
772c5265 RH |
920 | fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ |
921 | (* targetm.strip_name_encoding) (NAME)) | |
8f90be4c NC |
922 | |
923 | /* This is how to output an assembler line | |
924 | that says to advance the location counter | |
925 | to a multiple of 2**LOG bytes. */ | |
926 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
927 | if ((LOG) != 0) \ | |
928 | fprintf (FILE, "\t.align\t%d\n", LOG) | |
929 | ||
930 | #ifndef ASM_DECLARE_RESULT | |
931 | #define ASM_DECLARE_RESULT(FILE, RESULT) | |
932 | #endif | |
933 | ||
8f90be4c NC |
934 | #define MULTIPLE_SYMBOL_SPACES 1 |
935 | ||
936 | #define SUPPORTS_ONE_ONLY 1 | |
937 | ||
938 | /* A pair of macros to output things for the callgraph data. | |
939 | VALUE means (to the tools that reads this info later): | |
940 | 0 a call from src to dst | |
941 | 1 the call is special (e.g. dst is "unknown" or "alloca") | |
942 | 2 the call is special (e.g., the src is a table instead of routine) | |
943 | ||
944 | Frame sizes are augmented with timestamps to help later tools | |
945 | differentiate between static entities with same names in different | |
946 | files. */ | |
947 | extern long mcore_current_compilation_timestamp; | |
948 | #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \ | |
949 | do \ | |
950 | { \ | |
951 | if (mcore_current_compilation_timestamp == 0) \ | |
952 | mcore_current_compilation_timestamp = time (0); \ | |
953 | fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \ | |
954 | (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \ | |
955 | } \ | |
956 | while (0) | |
957 | ||
958 | #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \ | |
959 | do \ | |
960 | { \ | |
961 | fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \ | |
962 | (SRCNAME), (DSTNAME), (VALUE)); \ | |
963 | } \ | |
964 | while (0) | |
965 | ||
506a61b1 KG |
966 | /* Globalizing directive for a label. */ |
967 | #define GLOBAL_ASM_OP "\t.export\t" | |
8f90be4c | 968 | |
31488c64 | 969 | /* The prefix to add to user-visible assembler symbols. */ |
8f90be4c NC |
970 | #undef USER_LABEL_PREFIX |
971 | #define USER_LABEL_PREFIX "" | |
972 | ||
973 | /* Make an internal label into a string. */ | |
974 | #undef ASM_GENERATE_INTERNAL_LABEL | |
975 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ | |
976 | sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM) | |
977 | ||
31488c64 | 978 | /* Jump tables must be 32 bit aligned. */ |
8f90be4c NC |
979 | #undef ASM_OUTPUT_CASE_LABEL |
980 | #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ | |
981 | fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM); | |
982 | ||
983 | /* Output a relative address. Not needed since jump tables are absolute | |
984 | but we must define it anyway. */ | |
985 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ | |
986 | fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) | |
987 | ||
988 | /* Output an element of a dispatch table. */ | |
989 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
990 | fprintf (STREAM, "\t.long\t.L%d\n", VALUE) | |
991 | ||
992 | /* Output various types of constants. */ | |
993 | ||
8f90be4c NC |
994 | /* This is how to output an assembler line |
995 | that says to advance the location counter by SIZE bytes. */ | |
996 | #undef ASM_OUTPUT_SKIP | |
997 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 998 | fprintf (FILE, "\t.fill %d, 1\n", (int)(SIZE)) |
8f90be4c NC |
999 | |
1000 | /* This says how to output an assembler line | |
1001 | to define a global common symbol, with alignment information. */ | |
1002 | /* XXX - for now we ignore the alignment. */ | |
1003 | #undef ASM_OUTPUT_ALIGNED_COMMON | |
1004 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
1005 | do \ | |
1006 | { \ | |
1007 | if (mcore_dllexport_name_p (NAME)) \ | |
1008 | MCORE_EXPORT_NAME (FILE, NAME) \ | |
1009 | if (! mcore_dllimport_name_p (NAME)) \ | |
1010 | { \ | |
1011 | fputs ("\t.comm\t", FILE); \ | |
1012 | assemble_name (FILE, NAME); \ | |
74eda121 | 1013 | fprintf (FILE, ",%lu\n", (unsigned long)(SIZE)); \ |
8f90be4c NC |
1014 | } \ |
1015 | } \ | |
1016 | while (0) | |
1017 | ||
8f90be4c | 1018 | /* This says how to output an assembler line |
14bc6742 | 1019 | to define a local common symbol.... */ |
8f90be4c NC |
1020 | #undef ASM_OUTPUT_LOCAL |
1021 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1022 | (fputs ("\t.lcomm\t", FILE), \ | |
1023 | assemble_name (FILE, NAME), \ | |
58e15542 | 1024 | fprintf (FILE, ",%d\n", (int)SIZE)) |
8f90be4c NC |
1025 | |
1026 | /* ... and how to define a local common symbol whose alignment | |
1027 | we wish to specify. ALIGN comes in as bits, we have to turn | |
1028 | it into bytes. */ | |
1029 | #undef ASM_OUTPUT_ALIGNED_LOCAL | |
1030 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ | |
1031 | do \ | |
1032 | { \ | |
1033 | fputs ("\t.bss\t", (FILE)); \ | |
1034 | assemble_name ((FILE), (NAME)); \ | |
58e15542 | 1035 | fprintf ((FILE), ",%d,%d\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ |
8f90be4c NC |
1036 | } \ |
1037 | while (0) | |
1038 | ||
8f90be4c NC |
1039 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1040 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1041 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1042 | #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE) | |
1043 | ||
1044 | /* Print a memory address as an operand to reference that memory location. */ | |
1045 | #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X) | |
1046 | ||
1047 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
1048 | ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!') | |
1049 | ||
88657302 | 1050 | #endif /* ! GCC_MCORE_H */ |