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8f90be4c NC |
1 | /* Definitions of target machine for GNU compiler, |
2 | for Motorola M*CORE Processor. | |
16c484c7 | 3 | Copyright (C) 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
8f90be4c NC |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
9f2f9eb6 JM |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
8f90be4c | 21 | |
88657302 RH |
22 | #ifndef GCC_MCORE_H |
23 | #define GCC_MCORE_H | |
8f90be4c NC |
24 | |
25 | /* RBE: need to move these elsewhere. */ | |
26 | #undef LIKE_PPC_ABI | |
27 | #define MCORE_STRUCT_ARGS | |
28 | /* RBE: end of "move elsewhere". */ | |
29 | ||
30 | #include "hwint.h" | |
31 | ||
32 | #ifndef HAVE_MACHINE_MODES | |
33 | #include "machmode.h" | |
34 | #endif | |
35 | ||
36 | /* Run-time Target Specification. */ | |
37 | #define TARGET_MCORE | |
38 | ||
672a6f42 NB |
39 | /* Get tree.c to declare a target-specific specialization of |
40 | merge_decl_attributes. */ | |
41 | #define TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
8f90be4c NC |
42 | |
43 | /* Support the __declspec keyword by turning them into attributes. | |
44 | We currently only support: dllexport and dllimport. | |
45 | Note that the current way we do this may result in a collision with | |
46 | predefined attributes later on. This can be solved by using one attribute, | |
47 | say __declspec__, and passing args to it. The problem with that approach | |
48 | is that args are not accumulated: each new appearance would clobber any | |
49 | existing args. XXX- FIXME the definition below relies upon string | |
50 | concatenation, which is non-portable. */ | |
51 | #define CPP_PREDEFINES \ | |
52 | "-D__mcore__ -D__MCORE__=1 -D__declspec(x)=__attribute__((x))" SUBTARGET_CPP_PREDEFINES | |
53 | ||
54 | /* If -m4align is ever re-enabled then uncomment this line as well: | |
55 | #define CPP_SPEC "%{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}" */ | |
56 | ||
57 | #undef CPP_SPEC | |
58 | #define CPP_SPEC " \ | |
59 | %{mbig-endian: \ | |
60 | %{mlittle-endian:%echoose either big or little endian, not both} \ | |
61 | -D__MCOREBE__} \ | |
62 | %{m210: \ | |
63 | %{m340:%echoose either m340 or m210 not both} \ | |
64 | %{mlittle-endian:%ethe m210 does not have little endian support} \ | |
65 | -D__M210__} \ | |
66 | %{!mbig-endian: -D__MCORELE__} \ | |
67 | %{!m210: -D__M340__} \ | |
68 | " | |
d6a7951f | 69 | /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC |
8f90be4c NC |
70 | %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */ |
71 | ||
72 | /* We don't have a -lg library, so don't put it in the list. */ | |
73 | #undef LIB_SPEC | |
74 | #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" | |
75 | ||
76 | #undef ASM_SPEC | |
77 | #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}" | |
78 | ||
79 | #undef LINK_SPEC | |
80 | #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X" | |
81 | ||
82 | /* Can only count on 16 bits of availability; change to long would affect | |
83 | many architecture specific files (other architectures...). */ | |
84 | extern int target_flags; | |
85 | ||
86 | #define HARDLIT_BIT (1 << 0) /* Build in-line literals using 2 insns */ | |
87 | #define ALIGN8_BIT (1 << 1) /* Max alignment goes to 8 instead of 4 */ | |
88 | #define DIV_BIT (1 << 2) /* Generate divide instructions */ | |
89 | #define RELAX_IMM_BIT (1 << 3) /* Arbitrary immediates in and, or, tst */ | |
90 | #define W_FIELD_BIT (1 << 4) /* Generate bit insv/extv using SImode */ | |
91 | #define OVERALIGN_FUNC_BIT (1 << 5) /* Align functions to 4 byte boundary */ | |
92 | #define CGDATA_BIT (1 << 6) /* Generate callgraph data */ | |
93 | #define SLOW_BYTES_BIT (1 << 7) /* Slow byte access */ | |
94 | #define LITTLE_END_BIT (1 << 8) /* Generate little endian code */ | |
95 | #define M340_BIT (1 << 9) /* Generate code for the m340 */ | |
96 | ||
97 | #define TARGET_DEFAULT \ | |
98 | (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT) | |
99 | ||
100 | #ifndef MULTILIB_DEFAULTS | |
101 | #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" } | |
102 | #endif | |
103 | ||
104 | #define TARGET_HARDLIT (target_flags & HARDLIT_BIT) | |
105 | /* The ability to have 4 byte alignment is being suppressed for now. | |
106 | If this ability is reenabled, you must enable the definition below | |
107 | *and* edit t-mcore to enable multilibs for 4 byte alignment code. */ | |
108 | #if 0 | |
109 | #define TARGET_8ALIGN (target_flags & ALIGN8_BIT) | |
110 | #else | |
111 | #define TARGET_8ALIGN 1 | |
112 | #endif | |
113 | #define TARGET_DIV (target_flags & DIV_BIT) | |
114 | #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT) | |
115 | #define TARGET_W_FIELD (target_flags & W_FIELD_BIT) | |
116 | #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT) | |
117 | #define TARGET_CG_DATA (target_flags & CGDATA_BIT) | |
118 | #define TARGET_CG_DATA (target_flags & CGDATA_BIT) | |
119 | #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT) | |
120 | #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT) | |
121 | #define TARGET_M340 (target_flags & M340_BIT) | |
122 | ||
123 | ||
047142d3 PT |
124 | #define TARGET_SWITCHES \ |
125 | { {"hardlit", HARDLIT_BIT, \ | |
126 | N_("Inline constants if it can be done in 2 insns or less") }, \ | |
127 | {"no-hardlit", - HARDLIT_BIT, \ | |
c725bd79 | 128 | N_("Inline constants if it only takes 1 instruction") }, \ |
047142d3 PT |
129 | {"4align", - ALIGN8_BIT, \ |
130 | N_("Set maximum alignment to 4") }, \ | |
131 | {"8align", ALIGN8_BIT, \ | |
132 | N_("Set maximum alignment to 8") }, \ | |
133 | {"div", DIV_BIT, \ | |
134 | "" }, \ | |
135 | {"no-div", - DIV_BIT, \ | |
136 | N_("Do not use the divide instruction") }, \ | |
137 | {"relax-immediates", RELAX_IMM_BIT, \ | |
138 | "" }, \ | |
139 | {"no-relax-immediates", - RELAX_IMM_BIT, \ | |
140 | N_("Do not arbitary sized immediates in bit operations") }, \ | |
141 | {"wide-bitfields", W_FIELD_BIT, \ | |
b0287a90 | 142 | N_("Always treat bit-field as int-sized") }, \ |
047142d3 PT |
143 | {"no-wide-bitfields", - W_FIELD_BIT, \ |
144 | "" }, \ | |
145 | {"4byte-functions", OVERALIGN_FUNC_BIT, \ | |
146 | N_("Force functions to be aligned to a 4 byte boundary") }, \ | |
147 | {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \ | |
148 | N_("Force functions to be aligned to a 2 byte boundary") }, \ | |
149 | {"callgraph-data", CGDATA_BIT, \ | |
150 | N_("Emit call graph information") }, \ | |
151 | {"no-callgraph-data", - CGDATA_BIT, \ | |
152 | "" }, \ | |
153 | {"slow-bytes", SLOW_BYTES_BIT, \ | |
154 | N_("Prefer word accesses over byte accesses") }, \ | |
155 | {"no-slow-bytes", - SLOW_BYTES_BIT, \ | |
156 | "" }, \ | |
157 | { "no-lsim", 0, "" }, \ | |
158 | {"little-endian", LITTLE_END_BIT, \ | |
159 | N_("Generate little endian code") }, \ | |
160 | {"big-endian", - LITTLE_END_BIT, \ | |
161 | "" }, \ | |
162 | {"210", - M340_BIT, \ | |
163 | "" }, \ | |
164 | {"340", M340_BIT, \ | |
165 | N_("Generate code for the M*Core M340") }, \ | |
166 | {"", TARGET_DEFAULT, \ | |
167 | "" } \ | |
8f90be4c NC |
168 | } |
169 | ||
170 | extern char * mcore_current_function_name; | |
171 | ||
172 | /* Target specific options (as opposed to the switches above). */ | |
173 | extern const char * mcore_stack_increment_string; | |
174 | ||
047142d3 PT |
175 | #define TARGET_OPTIONS \ |
176 | { \ | |
177 | {"stack-increment=", & mcore_stack_increment_string, \ | |
178 | N_("Maximum amount for a single stack increment operation")} \ | |
8f90be4c NC |
179 | } |
180 | ||
56ae9405 NC |
181 | #ifndef CC1_SPEC |
182 | /* The MCore ABI says that bitfields are unsigned by default. */ | |
183 | #define CC1_SPEC "-funsigned-bitfields" | |
184 | #endif | |
8f90be4c NC |
185 | |
186 | /* What options are we going to default to specific settings when | |
187 | -O* happens; the user can subsequently override these settings. | |
188 | ||
189 | Omitting the frame pointer is a very good idea on the MCore. | |
190 | Scheduling isn't worth anything on the current MCore implementation. */ | |
191 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ | |
192 | { \ | |
193 | if (LEVEL) \ | |
194 | { \ | |
195 | flag_no_function_cse = 1; \ | |
196 | flag_omit_frame_pointer = 1; \ | |
197 | \ | |
198 | if (LEVEL >= 2) \ | |
199 | { \ | |
200 | flag_caller_saves = 0; \ | |
201 | flag_schedule_insns = 0; \ | |
202 | flag_schedule_insns_after_reload = 0; \ | |
203 | } \ | |
204 | } \ | |
205 | if (SIZE) \ | |
206 | { \ | |
207 | target_flags &= ~ HARDLIT_BIT; \ | |
208 | } \ | |
209 | } | |
210 | ||
211 | /* What options are we going to force to specific settings, | |
212 | regardless of what the user thought he wanted. | |
213 | We also use this for some post-processing of options. */ | |
214 | #define OVERRIDE_OPTIONS mcore_override_options () | |
215 | ||
216 | /* Target machine storage Layout. */ | |
217 | ||
8f90be4c NC |
218 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
219 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
220 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
221 | { \ | |
222 | (MODE) = SImode; \ | |
223 | (UNSIGNEDP) = 1; \ | |
224 | } | |
225 | ||
226 | #define PROMOTE_FUNCTION_ARGS | |
227 | ||
228 | #define PROMOTE_FUNCTION_RETURN | |
229 | ||
230 | /* Define this if most significant bit is lowest numbered | |
231 | in instructions that operate on numbered bit-fields. */ | |
232 | #define BITS_BIG_ENDIAN 0 | |
233 | ||
234 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
235 | #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END) | |
236 | ||
237 | /* Define this if most significant word of a multiword number is the lowest | |
238 | numbered. */ | |
239 | #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END) | |
240 | ||
241 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
242 | #ifdef __MCORELE__ | |
243 | #undef LIBGCC2_WORDS_BIG_ENDIAN | |
244 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
245 | #endif | |
246 | ||
8f90be4c NC |
247 | #define MAX_BITS_PER_WORD 32 |
248 | ||
249 | /* Width of a word, in units (bytes). */ | |
250 | #define UNITS_PER_WORD 4 | |
251 | ||
8f90be4c NC |
252 | /* A C expression for the size in bits of the type `long long' on the |
253 | target machine. If you don't define this, the default is two | |
254 | words. */ | |
255 | #define LONG_LONG_TYPE_SIZE 64 | |
256 | ||
8f90be4c NC |
257 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
258 | #define PARM_BOUNDARY 32 | |
259 | ||
260 | /* Doubles must be alogned to an 8 byte boundary. */ | |
261 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
262 | ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \ | |
263 | ? BIGGEST_ALIGNMENT : PARM_BOUNDARY) | |
264 | ||
265 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
266 | #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) | |
267 | ||
268 | /* Largest increment in UNITS we allow the stack to grow in a single operation. */ | |
269 | extern int mcore_stack_increment; | |
270 | #define STACK_UNITS_MAXSTEP 4096 | |
271 | ||
272 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
273 | #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16) | |
274 | ||
275 | /* Alignment of field after `int : 0' in a structure. */ | |
276 | #define EMPTY_FIELD_BOUNDARY 32 | |
277 | ||
278 | /* No data type wants to be aligned rounder than this. */ | |
279 | #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32) | |
280 | ||
281 | /* The best alignment to use in cases where we have a choice. */ | |
282 | #define FASTEST_ALIGNMENT 32 | |
283 | ||
284 | /* Every structures size must be a multiple of 8 bits. */ | |
285 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
286 | ||
287 | /* Look at the fundamental type that is used for a bitfield and use | |
288 | that to impose alignment on the enclosing structure. | |
289 | struct s {int a:8}; should have same alignment as "int", not "char". */ | |
290 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
291 | ||
292 | /* Largest integer machine mode for structures. If undefined, the default | |
293 | is GET_MODE_SIZE(DImode). */ | |
294 | #define MAX_FIXED_MODE_SIZE 32 | |
295 | ||
296 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
297 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
298 | ((TREE_CODE (EXP) == STRING_CST \ | |
299 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
300 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
301 | ||
302 | /* Make arrays of chars word-aligned for the same reasons. */ | |
303 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
304 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
305 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
306 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
307 | ||
308 | /* Set this nonzero if move instructions will actually fail to work | |
309 | when given unaligned data. */ | |
310 | #define STRICT_ALIGNMENT 1 | |
311 | ||
312 | /* Standard register usage. */ | |
313 | ||
314 | /* Register allocation for our first guess | |
315 | ||
316 | r0 stack pointer | |
317 | r1 scratch, target reg for xtrb? | |
318 | r2-r7 arguments. | |
319 | r8-r14 call saved | |
320 | r15 link register | |
321 | ap arg pointer (doesn't really exist, always eliminated) | |
322 | c c bit | |
323 | fp frame pointer (doesn't really exist, always eliminated) | |
324 | x19 two control registers */ | |
325 | ||
326 | /* Number of actual hardware registers. | |
327 | The hardware registers are assigned numbers for the compiler | |
328 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
329 | All registers that the compiler knows about must be given numbers, | |
330 | even those that are not normally considered general registers. | |
331 | ||
332 | MCore has 16 integer registers and 2 control registers + the arg | |
333 | pointer. */ | |
334 | ||
335 | #define FIRST_PSEUDO_REGISTER 20 | |
336 | ||
337 | #define R1_REG 1 /* where literals are forced */ | |
338 | #define LK_REG 15 /* overloaded on general register */ | |
339 | #define AP_REG 16 /* fake arg pointer register */ | |
340 | /* RBE: mcore.md depends on CC_REG being set to 17 */ | |
f5143c46 | 341 | #define CC_REG 17 /* can't name it C_REG */ |
8f90be4c NC |
342 | #define FP_REG 18 /* fake frame pointer register */ |
343 | ||
344 | /* Specify the registers used for certain standard purposes. | |
345 | The values of these macros are register numbers. */ | |
346 | ||
347 | ||
348 | #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */ | |
349 | #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */ | |
350 | #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */ | |
351 | ||
352 | /* The assembler's names for the registers. RFP need not always be used as | |
353 | the Real framepointer; it can also be used as a normal general register. | |
354 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
355 | the argument-and-return-context pointer. */ | |
356 | #define REGISTER_NAMES \ | |
357 | { \ | |
358 | "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
359 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
360 | "apvirtual", "c", "fpvirtual", "x19" \ | |
361 | } | |
362 | ||
363 | /* 1 for registers that have pervasive standard uses | |
364 | and are not available for the register allocator. */ | |
365 | #define FIXED_REGISTERS \ | |
366 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
367 | { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
368 | ||
369 | /* 1 for registers not available across function calls. | |
370 | These must include the FIXED_REGISTERS and also any | |
371 | registers that can be used without being saved. | |
372 | The latter must include the registers where values are returned | |
373 | and the register where structure-value addresses are passed. | |
374 | Aside from that, you can include as many other registers as you like. */ | |
375 | ||
376 | /* RBE: r15 {link register} not available across calls, | |
377 | * But we don't mark it that way here... */ | |
378 | #define CALL_USED_REGISTERS \ | |
379 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
380 | { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
381 | ||
382 | /* The order in which register should be allocated. */ | |
383 | #define REG_ALLOC_ORDER \ | |
384 | /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \ | |
385 | { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19} | |
386 | ||
387 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
388 | to hold something of mode MODE. | |
389 | This is ordinarily the length in words of a value of mode MODE | |
390 | but can be less for certain modes in special long registers. | |
391 | ||
392 | On the MCore regs are UNITS_PER_WORD bits wide; */ | |
393 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
394 | (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
395 | ||
396 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
397 | We may keep double values in even registers. */ | |
398 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
399 | ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18)) | |
400 | ||
401 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
402 | when one has mode MODE1 and one has mode MODE2. | |
403 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
404 | for any hard reg, then this must be 0 for correct output. */ | |
405 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
406 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
407 | ||
408 | /* Value should be nonzero if functions must have frame pointers. | |
409 | Zero means the frame pointer need not be set up (and parms may be accessed | |
410 | via the stack pointer) in functions that seem suitable. */ | |
411 | #define FRAME_POINTER_REQUIRED 0 | |
412 | ||
413 | /* Definitions for register eliminations. | |
414 | ||
415 | We have two registers that can be eliminated on the MCore. First, the | |
416 | frame pointer register can often be eliminated in favor of the stack | |
417 | pointer register. Secondly, the argument pointer register can always be | |
418 | eliminated; it is replaced with either the stack or frame pointer. */ | |
419 | ||
420 | /* Base register for access to arguments of the function. */ | |
421 | #define ARG_POINTER_REGNUM 16 | |
422 | ||
423 | /* Register in which the static-chain is passed to a function. */ | |
424 | #define STATIC_CHAIN_REGNUM 1 | |
425 | ||
426 | /* This is an array of structures. Each structure initializes one pair | |
427 | of eliminable registers. The "from" register number is given first, | |
428 | followed by "to". Eliminations of the same "from" register are listed | |
429 | in order of preference. */ | |
430 | #define ELIMINABLE_REGS \ | |
431 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
432 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
433 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
434 | ||
435 | /* Given FROM and TO register numbers, say whether this elimination | |
436 | is allowed. */ | |
437 | #define CAN_ELIMINATE(FROM, TO) \ | |
438 | (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) | |
439 | ||
440 | /* Define the offset between two registers, one to be eliminated, and the other | |
441 | its replacement, at the start of a routine. */ | |
442 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
443 | OFFSET = mcore_initial_elimination_offset (FROM, TO) | |
444 | ||
445 | /* Place that structure value return address is placed. */ | |
446 | #define STRUCT_VALUE 0 | |
447 | ||
448 | /* Define the classes of registers for register constraints in the | |
449 | machine description. Also define ranges of constants. | |
450 | ||
451 | One of the classes must always be named ALL_REGS and include all hard regs. | |
452 | If there is more than one class, another class must be named NO_REGS | |
453 | and contain no registers. | |
454 | ||
455 | The name GENERAL_REGS must be the name of a class (or an alias for | |
456 | another name such as ALL_REGS). This is the class of registers | |
457 | that is allowed by "g" or "r" in a register constraint. | |
458 | Also, registers outside this class are allocated only when | |
459 | instructions express preferences for them. | |
460 | ||
461 | The classes must be numbered in nondecreasing order; that is, | |
462 | a larger-numbered class must never be contained completely | |
463 | in a smaller-numbered class. | |
464 | ||
465 | For any two classes, it is very desirable that there be another | |
466 | class that represents their union. */ | |
467 | ||
468 | /* The MCore has only general registers. There are | |
469 | also some special purpose registers: the T bit register, the | |
470 | procedure Link and the Count Registers */ | |
471 | enum reg_class | |
472 | { | |
473 | NO_REGS, | |
474 | ONLYR1_REGS, | |
475 | LRW_REGS, | |
476 | GENERAL_REGS, | |
477 | C_REGS, | |
478 | ALL_REGS, | |
479 | LIM_REG_CLASSES | |
480 | }; | |
481 | ||
482 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
483 | ||
484 | /* Give names of register classes as strings for dump file. */ | |
485 | #define REG_CLASS_NAMES \ | |
486 | { \ | |
487 | "NO_REGS", \ | |
488 | "ONLYR1_REGS", \ | |
489 | "LRW_REGS", \ | |
490 | "GENERAL_REGS", \ | |
491 | "C_REGS", \ | |
492 | "ALL_REGS", \ | |
493 | } | |
494 | ||
495 | /* Define which registers fit in which classes. | |
496 | This is an initializer for a vector of HARD_REG_SET | |
497 | of length N_REG_CLASSES. */ | |
498 | ||
499 | /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */ | |
500 | #define REG_CLASS_CONTENTS \ | |
501 | { \ | |
502 | {0x000000}, /* NO_REGS */ \ | |
503 | {0x000002}, /* ONLYR1_REGS */ \ | |
504 | {0x007FFE}, /* LRW_REGS */ \ | |
505 | {0x01FFFF}, /* GENERAL_REGS */ \ | |
506 | {0x020000}, /* C_REGS */ \ | |
507 | {0x0FFFFF} /* ALL_REGS */ \ | |
508 | } | |
509 | ||
510 | /* The same information, inverted: | |
511 | Return the class number of the smallest class containing | |
512 | reg number REGNO. This could be a conditional expression | |
513 | or could index an array. */ | |
514 | ||
0139adca | 515 | extern const int regno_reg_class[FIRST_PSEUDO_REGISTER]; |
8f90be4c NC |
516 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO] |
517 | ||
518 | /* When defined, the compiler allows registers explicitly used in the | |
519 | rtl to be used as spill registers but prevents the compiler from | |
520 | extending the lifetime of these registers. */ | |
521 | #define SMALL_REGISTER_CLASSES 1 | |
522 | ||
523 | /* The class value for index registers, and the one for base regs. */ | |
524 | #define INDEX_REG_CLASS NO_REGS | |
525 | #define BASE_REG_CLASS GENERAL_REGS | |
526 | ||
527 | /* Get reg_class from a letter such as appears in the machine | |
528 | description. */ | |
0b5826ac | 529 | extern const enum reg_class reg_class_from_letter[]; |
8f90be4c NC |
530 | |
531 | #define REG_CLASS_FROM_LETTER(C) \ | |
0df6c2c7 | 532 | ( ISLOWER (C) ? reg_class_from_letter[(C) - 'a'] : NO_REGS ) |
8f90be4c NC |
533 | |
534 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
535 | can be used to stand for particular ranges of immediate operands. | |
536 | This macro defines what the ranges are. | |
537 | C is the letter, and VALUE is a constant value. | |
538 | Return 1 if VALUE is in the range specified by C. | |
539 | I: loadable by movi (0..127) | |
540 | J: arithmetic operand 1..32 | |
541 | K: shift operand 0..31 | |
542 | L: negative arithmetic operand -1..-32 | |
543 | M: powers of two, constants loadable by bgeni | |
544 | N: powers of two minus 1, constants loadable by bmaski, including -1 | |
545 | O: allowed by cmov with two constants +/- 1 of each other | |
546 | P: values we will generate 'inline' -- without an 'lrw' | |
547 | ||
548 | Others defined for use after reload | |
549 | Q: constant 1 | |
550 | R: a label | |
551 | S: 0/1/2 cleared bits out of 32 [for bclri's] | |
552 | T: 2 set bits out of 32 [for bseti's] | |
553 | U: constant 0 | |
554 | xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri | |
555 | xxxT: 2 cleared bits out of 32. for pairs of bclris. */ | |
556 | #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f) | |
557 | #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32) | |
558 | #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32) | |
559 | #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31) | |
560 | #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0) | |
561 | #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0) | |
562 | #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \ | |
563 | CONST_OK_FOR_M(VALUE) || \ | |
564 | CONST_OK_FOR_N(VALUE) || \ | |
565 | CONST_OK_FOR_M((int)(VALUE) - 1) || \ | |
566 | CONST_OK_FOR_N((int)(VALUE) + 1)) | |
567 | ||
568 | #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE)) | |
569 | ||
570 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
571 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
572 | : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ | |
573 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
574 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
575 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
576 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
577 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ | |
578 | : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ | |
579 | : 0) | |
580 | ||
581 | /* Similar, but for floating constants, and defining letters G and H. | |
582 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
583 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
584 | ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \ | |
585 | && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \ | |
586 | : 0) | |
587 | ||
588 | /* Letters in the range `Q' through `U' in a register constraint string | |
589 | may be defined in a machine-dependent fashion to stand for arbitrary | |
590 | operand types. */ | |
591 | #define EXTRA_CONSTRAINT(OP, C) \ | |
592 | ((C) == 'R' ? (GET_CODE (OP) == MEM \ | |
593 | && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \ | |
594 | : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \ | |
595 | && mcore_num_zeros (INTVAL (OP)) <= 2) \ | |
596 | : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \ | |
597 | && mcore_num_ones (INTVAL (OP)) == 2) \ | |
598 | : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \ | |
599 | && INTVAL(OP) == 1) \ | |
600 | : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \ | |
601 | && INTVAL(OP) == 0) \ | |
602 | : 0) | |
603 | ||
604 | /* Given an rtx X being reloaded into a reg required to be | |
605 | in class CLASS, return the class of reg to actually use. | |
606 | In general this is just CLASS; but on some machines | |
607 | in some cases it is preferable to use a more restrictive class. */ | |
608 | #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS) | |
609 | ||
610 | /* Return the register class of a scratch register needed to copy IN into | |
611 | or out of a register in CLASS in MODE. If it can be done directly, | |
612 | NO_REGS is returned. */ | |
613 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS | |
614 | ||
615 | /* Return the maximum number of consecutive registers | |
616 | needed to represent mode MODE in a register of class CLASS. | |
617 | ||
618 | On MCore this is the size of MODE in words. */ | |
619 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
620 | (ROUND_ADVANCE (GET_MODE_SIZE (MODE))) | |
621 | ||
622 | /* Stack layout; function entry, exit and calling. */ | |
623 | ||
624 | /* Define the number of register that can hold parameters. | |
625 | These two macros are used only in other macro definitions below. */ | |
626 | #define NPARM_REGS 6 | |
627 | #define FIRST_PARM_REG 2 | |
628 | #define FIRST_RET_REG 2 | |
629 | ||
630 | /* Define this if pushing a word on the stack | |
631 | makes the stack pointer a smaller address. */ | |
632 | #define STACK_GROWS_DOWNWARD | |
633 | ||
634 | /* Define this if the nominal address of the stack frame | |
635 | is at the high-address end of the local variables; | |
636 | that is, each additional local variable allocated | |
637 | goes at a more negative offset in the frame. */ | |
638 | /* We don't define this, because the MCore does not support | |
639 | addresses with negative offsets. */ | |
640 | /* #define FRAME_GROWS_DOWNWARD */ | |
641 | ||
642 | /* Offset within stack frame to start allocating local variables at. | |
643 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
644 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
645 | of the first local allocated. */ | |
646 | #define STARTING_FRAME_OFFSET 0 | |
647 | ||
648 | /* If defined, the maximum amount of space required for outgoing arguments | |
649 | will be computed and placed into the variable | |
650 | `current_function_outgoing_args_size'. No space will be pushed | |
651 | onto the stack for each call; instead, the function prologue should | |
652 | increase the stack frame size by this amount. */ | |
f73ad30e | 653 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8f90be4c NC |
654 | |
655 | /* Offset of first parameter from the argument pointer register value. */ | |
656 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
657 | ||
658 | /* Value is the number of byte of arguments automatically | |
659 | popped when returning from a subroutine call. | |
660 | FUNTYPE is the data type of the function (as a tree), | |
661 | or for a library call it is an identifier node for the subroutine name. | |
662 | SIZE is the number of bytes of arguments passed on the stack. | |
663 | ||
664 | On the MCore, the callee does not pop any of its arguments that were passed | |
665 | on the stack. */ | |
666 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
667 | ||
668 | /* Define how to find the value returned by a function. | |
669 | VALTYPE is the data type of the value (as a tree). | |
670 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
671 | otherwise, FUNC is 0. */ | |
672 | #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC) | |
673 | ||
674 | /* Don't default to pcc-struct-return, because gcc is the only compiler, and | |
675 | we want to retain compatibility with older gcc versions. */ | |
676 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
677 | ||
678 | /* how we are going to return big values */ | |
679 | /* | |
680 | * #define RETURN_IN_MEMORY(TYPE) \ | |
681 | * (TYPE_MODE (TYPE) == BLKmode \ | |
682 | * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \ | |
683 | * && !(TYPE_MODE (TYPE) == SImode \ | |
684 | * || (TYPE_MODE (TYPE) == BLKmode \ | |
685 | * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \ | |
686 | * && int_size_in_bytes (TYPE) == UNITS_PER_WORD)))) | |
687 | */ | |
688 | ||
689 | ||
690 | /* How many registers to use for struct return. */ | |
691 | #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD) | |
692 | ||
693 | /* Define how to find the value returned by a library function | |
694 | assuming the value has mode MODE. */ | |
695 | #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG) | |
696 | ||
697 | /* 1 if N is a possible register number for a function value. | |
698 | On the MCore, only r4 can return results. */ | |
699 | #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) | |
700 | ||
701 | #define MUST_PASS_IN_STACK(MODE,TYPE) \ | |
702 | mcore_must_pass_on_stack (MODE, TYPE) | |
703 | ||
704 | /* 1 if N is a possible register number for function argument passing. */ | |
705 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
706 | ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) | |
707 | ||
708 | /* Define a data type for recording info about an argument list | |
709 | during the scan of that argument list. This data type should | |
710 | hold all necessary information about the function itself | |
711 | and about the args processed so far, enough to enable macros | |
712 | such as FUNCTION_ARG to determine where the next arg should go. | |
713 | ||
714 | On MCore, this is a single integer, which is a number of words | |
715 | of arguments scanned so far (including the invisible argument, | |
716 | if any, which holds the structure-value-address). | |
717 | Thus NARGREGS or more means all following args should go on the stack. */ | |
718 | #define CUMULATIVE_ARGS int | |
719 | ||
720 | #define ROUND_ADVANCE(SIZE) \ | |
721 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
722 | ||
723 | /* Round a register number up to a proper boundary for an arg of mode | |
724 | MODE. | |
725 | ||
726 | We round to an even reg for things larger than a word. */ | |
727 | #define ROUND_REG(X, MODE) \ | |
728 | ((TARGET_8ALIGN \ | |
729 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
730 | ? ((X) + ((X) & 1)) : (X)) | |
731 | ||
732 | ||
733 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
734 | for a call to a function whose data type is FNTYPE. | |
735 | For a library call, FNTYPE is 0. | |
736 | ||
737 | On MCore, the offset always starts at 0: the first parm reg is always | |
738 | the same reg. */ | |
739 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ | |
740 | ((CUM) = 0) | |
741 | ||
742 | /* Update the data in CUM to advance over an argument | |
743 | of mode MODE and data type TYPE. | |
744 | (TYPE is null for libcalls where that information may not be | |
745 | available.) */ | |
746 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
747 | ((CUM) = (ROUND_REG ((CUM), (MODE)) \ | |
748 | + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \ | |
749 | ||
750 | /* Define where to put the arguments to a function. */ | |
751 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
752 | mcore_function_arg (CUM, MODE, TYPE, NAMED) | |
753 | ||
754 | /* A C expression that indicates when an argument must be passed by | |
755 | reference. If nonzero for an argument, a copy of that argument is | |
756 | made in memory and a pointer to the argument is passed instead of | |
757 | the argument itself. The pointer is passed in whatever way is | |
758 | appropriate for passing a pointer to that type. */ | |
759 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
760 | MUST_PASS_IN_STACK (MODE, TYPE) | |
761 | ||
762 | /* For an arg passed partly in registers and partly in memory, | |
763 | this is the number of registers used. | |
764 | For args passed entirely in registers or entirely in memory, zero. | |
765 | Any arg that starts in the first NPARM_REGS regs but won't entirely | |
766 | fit in them needs partial registers on the MCore. */ | |
767 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
768 | mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED) | |
769 | ||
770 | /* Perform any needed actions needed for a function that is receiving a | |
771 | variable number of arguments. */ | |
772 | #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ | |
773 | mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS) | |
774 | ||
775 | /* Call the function profiler with a given profile label. */ | |
776 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ | |
777 | { \ | |
778 | fprintf (STREAM, " trap 1\n"); \ | |
779 | fprintf (STREAM, " .align 2\n"); \ | |
780 | fprintf (STREAM, " .long LP%d\n", (LABELNO)); \ | |
781 | } | |
782 | ||
783 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
784 | the stack pointer does not matter. The value is tested only in | |
785 | functions that have frame pointers. | |
786 | No definition is equivalent to always zero. */ | |
787 | #define EXIT_IGNORE_STACK 0 | |
788 | ||
789 | /* Output assembler code for a block containing the constant parts | |
790 | of a trampoline, leaving space for the variable parts. | |
791 | ||
792 | On the MCore, the trapoline looks like: | |
793 | lrw r1, function | |
794 | lrw r13, area | |
795 | jmp r13 | |
796 | or r0, r0 | |
797 | .literals */ | |
798 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
799 | { \ | |
800 | fprintf ((FILE), " .short 0x7102\n"); \ | |
801 | fprintf ((FILE), " .short 0x7d02\n"); \ | |
802 | fprintf ((FILE), " .short 0x00cd\n"); \ | |
803 | fprintf ((FILE), " .short 0x1e00\n"); \ | |
804 | fprintf ((FILE), " .long 0\n"); \ | |
805 | fprintf ((FILE), " .long 0\n"); \ | |
806 | } | |
807 | ||
808 | /* Length in units of the trampoline for entering a nested function. */ | |
809 | #define TRAMPOLINE_SIZE 12 | |
810 | ||
006946e4 JM |
811 | /* Alignment required for a trampoline in bits. */ |
812 | #define TRAMPOLINE_ALIGNMENT 32 | |
8f90be4c NC |
813 | |
814 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
815 | FNADDR is an RTX for the address of the function's pure code. | |
816 | CXT is an RTX for the static chain value for the function. */ | |
817 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
818 | { \ | |
819 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ | |
820 | (CXT)); \ | |
821 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ | |
822 | (FNADDR)); \ | |
823 | } | |
824 | ||
825 | /* Macros to check register numbers against specific register classes. */ | |
826 | ||
827 | /* These assume that REGNO is a hard or pseudo reg number. | |
828 | They give nonzero only if REGNO is a hard reg of the suitable class | |
829 | or a pseudo reg currently allocated to a suitable hard reg. | |
830 | Since they use reg_renumber, they are safe only once reg_renumber | |
831 | has been allocated, which happens in local-alloc.c. */ | |
832 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
833 | ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG) | |
834 | ||
835 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
836 | ||
837 | /* Maximum number of registers that can appear in a valid memory | |
838 | address. */ | |
839 | #define MAX_REGS_PER_ADDRESS 1 | |
840 | ||
841 | /* Recognize any constant value that is a valid address. */ | |
842 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) | |
843 | ||
844 | /* Nonzero if the constant value X is a legitimate general operand. | |
845 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
846 | ||
847 | On the MCore, allow anything but a double. */ | |
848 | #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE) | |
849 | ||
850 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) | |
851 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
852 | and check its validity for a certain class. | |
853 | We have two alternate definitions for each of them. | |
854 | The usual definition accepts all pseudo regs; the other rejects | |
855 | them unless they have been allocated suitable hard regs. | |
856 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
857 | #ifndef REG_OK_STRICT | |
858 | ||
859 | /* Nonzero if X is a hard reg that can be used as a base reg | |
860 | or if it is a pseudo reg. */ | |
861 | #define REG_OK_FOR_BASE_P(X) \ | |
862 | (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
863 | ||
864 | /* Nonzero if X is a hard reg that can be used as an index | |
865 | or if it is a pseudo reg. */ | |
866 | #define REG_OK_FOR_INDEX_P(X) 0 | |
867 | ||
868 | #else | |
869 | ||
870 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
871 | #define REG_OK_FOR_BASE_P(X) \ | |
872 | REGNO_OK_FOR_BASE_P (REGNO (X)) | |
873 | ||
874 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
875 | #define REG_OK_FOR_INDEX_P(X) 0 | |
876 | ||
877 | #endif | |
878 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
879 | that is a valid memory address for an instruction. | |
880 | The MODE argument is the machine mode for the MEM expression | |
881 | that wants to use this address. | |
882 | ||
883 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
884 | #define BASE_REGISTER_RTX_P(X) \ | |
885 | (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) | |
886 | ||
887 | #define INDEX_REGISTER_RTX_P(X) \ | |
888 | (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) | |
889 | ||
890 | ||
891 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
892 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
893 | the above macros so we are in luck. | |
894 | ||
895 | Allow REG | |
896 | REG+disp | |
897 | ||
898 | A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60, | |
899 | and for DI is 0..56 because we use two SI loads, etc. */ | |
900 | #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \ | |
901 | do \ | |
902 | { \ | |
903 | if (GET_CODE (OP) == CONST_INT) \ | |
904 | { \ | |
905 | if (GET_MODE_SIZE (MODE) >= 4 \ | |
906 | && (((unsigned)INTVAL (OP)) % 4) == 0 \ | |
907 | && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \ | |
908 | goto LABEL; \ | |
909 | if (GET_MODE_SIZE (MODE) == 2 \ | |
910 | && (((unsigned)INTVAL (OP)) % 2) == 0 \ | |
911 | && ((unsigned)INTVAL (OP)) <= 30) \ | |
912 | goto LABEL; \ | |
913 | if (GET_MODE_SIZE (MODE) == 1 \ | |
914 | && ((unsigned)INTVAL (OP)) <= 15) \ | |
915 | goto LABEL; \ | |
916 | } \ | |
917 | } \ | |
918 | while (0) | |
919 | ||
920 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
921 | { \ | |
922 | if (BASE_REGISTER_RTX_P (X)) \ | |
923 | goto LABEL; \ | |
924 | else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \ | |
925 | { \ | |
926 | rtx xop0 = XEXP (X,0); \ | |
927 | rtx xop1 = XEXP (X,1); \ | |
928 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
929 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
930 | if (BASE_REGISTER_RTX_P (xop1)) \ | |
931 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
932 | } \ | |
933 | } | |
934 | ||
935 | /* Go to LABEL if ADDR (a legitimate address expression) | |
936 | has an effect that depends on the machine mode it is used for. */ | |
937 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
938 | { \ | |
939 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ | |
940 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
941 | goto LABEL; \ | |
942 | } | |
943 | ||
944 | /* Specify the machine mode that this machine uses | |
945 | for the index in the tablejump instruction. */ | |
946 | #define CASE_VECTOR_MODE SImode | |
947 | ||
948 | /* Define this if the tablejump instruction expects the table | |
949 | to contain offsets from the address of the table. | |
950 | Do not define this if the table should contain absolute addresses. */ | |
951 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
952 | ||
8f90be4c NC |
953 | /* 'char' is signed by default. */ |
954 | #define DEFAULT_SIGNED_CHAR 0 | |
955 | ||
956 | /* The type of size_t unsigned int. */ | |
957 | #define SIZE_TYPE "unsigned int" | |
958 | ||
959 | /* Don't cse the address of the function being compiled. */ | |
960 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
961 | ||
962 | /* Max number of bytes we can move from memory to memory | |
963 | in one reasonably fast instruction. */ | |
964 | #define MOVE_MAX 4 | |
965 | ||
966 | /* Define if operations between registers always perform the operation | |
967 | on the full register even if a narrower mode is specified. */ | |
968 | #define WORD_REGISTER_OPERATIONS | |
969 | ||
970 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
971 | will either zero-extend or sign-extend. The value of this macro should | |
972 | be the code that says which one of the two operations is implicitly | |
973 | done, NIL if none. */ | |
974 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
975 | ||
976 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
977 | #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES | |
978 | ||
979 | /* We assume that the store-condition-codes instructions store 0 for false | |
980 | and some other value for true. This is the value stored for true. */ | |
981 | #define STORE_FLAG_VALUE 1 | |
982 | ||
983 | /* Immediate shift counts are truncated by the output routines (or was it | |
984 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
985 | that the native compiler puts too large (> 32) immediate shift counts | |
986 | into a register and shifts by the register, letting the ARM decide what | |
987 | to do instead of doing that itself. */ | |
988 | #define SHIFT_COUNT_TRUNCATED 1 | |
989 | ||
990 | /* All integers have the same format so truncation is easy. */ | |
991 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
992 | ||
993 | /* Define this if addresses of constant functions | |
994 | shouldn't be put through pseudo regs where they can be cse'd. | |
995 | Desirable on machines where ordinary constants are expensive | |
996 | but a CALL with constant address is cheap. */ | |
997 | /* why is this defined??? -- dac */ | |
998 | #define NO_FUNCTION_CSE 1 | |
999 | ||
1000 | /* Chars and shorts should be passed as ints. */ | |
1001 | #define PROMOTE_PROTOTYPES 1 | |
1002 | ||
1003 | /* The machine modes of pointers and functions. */ | |
1004 | #define Pmode SImode | |
1005 | #define FUNCTION_MODE Pmode | |
1006 | ||
1007 | /* The relative costs of various types of constants. Note that cse.c defines | |
1008 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
1009 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ | |
1010 | case CONST_INT: \ | |
1011 | return mcore_const_costs (RTX, OUTER_CODE); \ | |
1012 | case CONST: \ | |
1013 | case LABEL_REF: \ | |
1014 | case SYMBOL_REF: \ | |
1015 | return 5; \ | |
1016 | case CONST_DOUBLE: \ | |
1017 | return 10; | |
1018 | ||
1019 | /* provide the cost for an address calculation. | |
1020 | All addressing modes cost the same on the MCore. */ | |
1021 | #define ADDRESS_COST(RTX) 1 | |
1022 | ||
1023 | /* Provide the cost of an rtl expression. */ | |
1024 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
1025 | case AND: \ | |
1026 | return COSTS_N_INSNS (mcore_and_cost (X)); \ | |
1027 | case IOR: \ | |
1028 | return COSTS_N_INSNS (mcore_ior_cost (X)); \ | |
1029 | case DIV: \ | |
1030 | case UDIV: \ | |
1031 | case MOD: \ | |
1032 | case UMOD: \ | |
1033 | return COSTS_N_INSNS (100); \ | |
1034 | case FLOAT: \ | |
1035 | case FIX: \ | |
1036 | return 100; | |
1037 | ||
1038 | /* Compute extra cost of moving data between one register class | |
1039 | and another. All register moves are cheap. */ | |
cf011243 | 1040 | #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2 |
8f90be4c NC |
1041 | |
1042 | #define WORD_REGISTER_OPERATIONS | |
1043 | ||
8f90be4c NC |
1044 | /* Implicit library calls should use memcpy, not bcopy, etc. */ |
1045 | #define TARGET_MEM_FUNCTIONS | |
1046 | ||
1047 | /* Assembler output control. */ | |
1048 | #define ASM_COMMENT_START "\t//" | |
1049 | ||
1050 | #define ASM_APP_ON "// inline asm begin\n" | |
1051 | #define ASM_APP_OFF "// inline asm end\n" | |
1052 | ||
1053 | #define FILE_ASM_OP "\t.file\n" | |
1054 | ||
1055 | /* Switch to the text or data segment. */ | |
1056 | #define TEXT_SECTION_ASM_OP "\t.text" | |
1057 | #define DATA_SECTION_ASM_OP "\t.data" | |
1058 | ||
1059 | #undef EXTRA_SECTIONS | |
2cc07db4 | 1060 | #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS |
8f90be4c NC |
1061 | |
1062 | #undef EXTRA_SECTION_FUNCTIONS | |
1063 | #define EXTRA_SECTION_FUNCTIONS \ | |
8f90be4c NC |
1064 | SUBTARGET_EXTRA_SECTION_FUNCTIONS \ |
1065 | SWITCH_SECTION_FUNCTION | |
1066 | ||
8f90be4c NC |
1067 | /* Switch to SECTION (an `enum in_section'). |
1068 | ||
1069 | ??? This facility should be provided by GCC proper. | |
1070 | The problem is that we want to temporarily switch sections in | |
1071 | ASM_DECLARE_OBJECT_NAME and then switch back to the original section | |
1072 | afterwards. */ | |
1073 | #define SWITCH_SECTION_FUNCTION \ | |
55710451 KG |
1074 | static void switch_to_section PARAMS ((enum in_section, tree)); \ |
1075 | static void \ | |
8f90be4c NC |
1076 | switch_to_section (section, decl) \ |
1077 | enum in_section section; \ | |
1078 | tree decl; \ | |
1079 | { \ | |
1080 | switch (section) \ | |
1081 | { \ | |
1082 | case in_text: text_section (); break; \ | |
1083 | case in_data: data_section (); break; \ | |
1084 | case in_named: named_section (decl, NULL, 0); break; \ | |
8f90be4c NC |
1085 | SUBTARGET_SWITCH_SECTIONS \ |
1086 | default: abort (); break; \ | |
1087 | } \ | |
1088 | } | |
1089 | ||
7c262518 | 1090 | /* Switch into a generic section. */ |
1943c2c1 | 1091 | #undef TARGET_ASM_NAMED_SECTION |
7c262518 | 1092 | #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section |
8f90be4c NC |
1093 | |
1094 | /* This is how to output an insn to push a register on the stack. | |
1095 | It need not be very fast code. */ | |
1096 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1097 | fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \ | |
1098 | reg_names[STACK_POINTER_REGNUM], \ | |
1099 | (STACK_BOUNDARY / BITS_PER_UNIT), \ | |
1100 | reg_names[REGNO], \ | |
1101 | reg_names[STACK_POINTER_REGNUM]) | |
1102 | ||
1103 | /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ | |
1104 | #define REG_PUSH_LENGTH 2 | |
1105 | ||
1106 | /* This is how to output an insn to pop a register from the stack. */ | |
1107 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1108 | fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \ | |
1109 | reg_names[REGNO], \ | |
1110 | reg_names[STACK_POINTER_REGNUM], \ | |
1111 | reg_names[STACK_POINTER_REGNUM], \ | |
1112 | (STACK_BOUNDARY / BITS_PER_UNIT)) | |
1113 | ||
1114 | ||
8f90be4c NC |
1115 | /* Output a label definition. */ |
1116 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1117 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1118 | ||
1119 | /* Output a reference to a label. */ | |
1120 | #undef ASM_OUTPUT_LABELREF | |
1121 | #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
1122 | fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, MCORE_STRIP_NAME_ENCODING (NAME)) | |
1123 | ||
1124 | ||
1125 | /* This is how to output an assembler line | |
1126 | that says to advance the location counter | |
1127 | to a multiple of 2**LOG bytes. */ | |
1128 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1129 | if ((LOG) != 0) \ | |
1130 | fprintf (FILE, "\t.align\t%d\n", LOG) | |
1131 | ||
1132 | #ifndef ASM_DECLARE_RESULT | |
1133 | #define ASM_DECLARE_RESULT(FILE, RESULT) | |
1134 | #endif | |
1135 | ||
1136 | /* Strip export encoding from a function name. */ | |
1137 | #define MCORE_STRIP_NAME_ENCODING(SYM_NAME) \ | |
1138 | ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0)) | |
1139 | ||
fb49053f RH |
1140 | /* Strip any text from SYM_NAME added by targetm.encode_section_info |
1141 | and store the result in VAR. */ | |
8f90be4c NC |
1142 | #undef STRIP_NAME_ENCODING |
1143 | #define STRIP_NAME_ENCODING(VAR, SYM_NAME) \ | |
1144 | (VAR) = MCORE_STRIP_NAME_ENCODING (SYM_NAME) | |
1145 | ||
8f90be4c NC |
1146 | #define MULTIPLE_SYMBOL_SPACES 1 |
1147 | ||
1148 | #define SUPPORTS_ONE_ONLY 1 | |
1149 | ||
1150 | /* A pair of macros to output things for the callgraph data. | |
1151 | VALUE means (to the tools that reads this info later): | |
1152 | 0 a call from src to dst | |
1153 | 1 the call is special (e.g. dst is "unknown" or "alloca") | |
1154 | 2 the call is special (e.g., the src is a table instead of routine) | |
1155 | ||
1156 | Frame sizes are augmented with timestamps to help later tools | |
1157 | differentiate between static entities with same names in different | |
1158 | files. */ | |
1159 | extern long mcore_current_compilation_timestamp; | |
1160 | #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \ | |
1161 | do \ | |
1162 | { \ | |
1163 | if (mcore_current_compilation_timestamp == 0) \ | |
1164 | mcore_current_compilation_timestamp = time (0); \ | |
1165 | fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \ | |
1166 | (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \ | |
1167 | } \ | |
1168 | while (0) | |
1169 | ||
1170 | #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \ | |
1171 | do \ | |
1172 | { \ | |
1173 | fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \ | |
1174 | (SRCNAME), (DSTNAME), (VALUE)); \ | |
1175 | } \ | |
1176 | while (0) | |
1177 | ||
1178 | /* Output a globalising directive for a label. */ | |
1179 | #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ | |
1180 | (fprintf (STREAM, "\t.export\t"), \ | |
1181 | assemble_name (STREAM, NAME), \ | |
1182 | fputc ('\n',STREAM)) \ | |
1183 | ||
1184 | /* The prefix to add to user-visible assembler symbols. */ | |
1185 | #undef USER_LABEL_PREFIX | |
1186 | #define USER_LABEL_PREFIX "" | |
1187 | ||
1188 | /* Make an internal label into a string. */ | |
1189 | #undef ASM_GENERATE_INTERNAL_LABEL | |
1190 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ | |
1191 | sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM) | |
1192 | ||
1193 | /* Output an internal label definition. */ | |
1194 | #undef ASM_OUTPUT_INTERNAL_LABEL | |
1195 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
1196 | fprintf (FILE, ".%s%d:\n", PREFIX, NUM) | |
1197 | ||
1198 | /* Construct a private name. */ | |
1199 | #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ | |
1200 | ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ | |
1201 | sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) | |
1202 | ||
1203 | /* Jump tables must be 32 bit aligned. */ | |
1204 | #undef ASM_OUTPUT_CASE_LABEL | |
1205 | #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ | |
1206 | fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM); | |
1207 | ||
1208 | /* Output a relative address. Not needed since jump tables are absolute | |
1209 | but we must define it anyway. */ | |
1210 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ | |
1211 | fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) | |
1212 | ||
1213 | /* Output an element of a dispatch table. */ | |
1214 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
1215 | fprintf (STREAM, "\t.long\t.L%d\n", VALUE) | |
1216 | ||
1217 | /* Output various types of constants. */ | |
1218 | ||
8f90be4c NC |
1219 | /* This is how to output an assembler line |
1220 | that says to advance the location counter by SIZE bytes. */ | |
1221 | #undef ASM_OUTPUT_SKIP | |
1222 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1223 | fprintf (FILE, "\t.fill %d, 1\n", (SIZE)) | |
1224 | ||
1225 | /* This says how to output an assembler line | |
1226 | to define a global common symbol, with alignment information. */ | |
1227 | /* XXX - for now we ignore the alignment. */ | |
1228 | #undef ASM_OUTPUT_ALIGNED_COMMON | |
1229 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
1230 | do \ | |
1231 | { \ | |
1232 | if (mcore_dllexport_name_p (NAME)) \ | |
1233 | MCORE_EXPORT_NAME (FILE, NAME) \ | |
1234 | if (! mcore_dllimport_name_p (NAME)) \ | |
1235 | { \ | |
1236 | fputs ("\t.comm\t", FILE); \ | |
1237 | assemble_name (FILE, NAME); \ | |
1238 | fprintf (FILE, ",%d\n", SIZE); \ | |
1239 | } \ | |
1240 | } \ | |
1241 | while (0) | |
1242 | ||
1243 | /* This says how to output an assembler line | |
1244 | to define an external symbol. */ | |
1245 | #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ | |
1246 | do \ | |
1247 | { \ | |
1248 | fputs ("\t.import\t", (FILE)); \ | |
1249 | assemble_name ((FILE), (NAME)); \ | |
1250 | fputs ("\n", (FILE)); \ | |
1251 | } \ | |
1252 | while (0) | |
1253 | ||
1254 | #undef ASM_OUTPUT_EXTERNAL | |
1255 | /* RBE: we undefined this and let gas do it's "undefined is imported" | |
1256 | games. This is because when we use this, we get a marked | |
1257 | reference through the call to assemble_name and this forces C++ | |
1258 | inlined member functions (or any inlined function) to be instantiated | |
1259 | regardless of whether any callsites remain. | |
1260 | This makes this aspect of the compiler non-ABI compliant. */ | |
1261 | ||
1262 | /* Similar, but for libcall. FUN is an rtx. */ | |
1263 | #undef ASM_OUTPUT_EXTERNAL_LIBCALL | |
1264 | #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ | |
1265 | do \ | |
1266 | { \ | |
1267 | fprintf (FILE, "\t.import\t"); \ | |
1268 | assemble_name (FILE, XSTR (FUN, 0)); \ | |
1269 | fprintf (FILE, "\n"); \ | |
1270 | } \ | |
1271 | while (0) | |
1272 | ||
1273 | ||
1274 | /* This says how to output an assembler line | |
1275 | to define a local common symbol... */ | |
1276 | #undef ASM_OUTPUT_LOCAL | |
1277 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1278 | (fputs ("\t.lcomm\t", FILE), \ | |
1279 | assemble_name (FILE, NAME), \ | |
1280 | fprintf (FILE, ",%d\n", SIZE)) | |
1281 | ||
1282 | /* ... and how to define a local common symbol whose alignment | |
1283 | we wish to specify. ALIGN comes in as bits, we have to turn | |
1284 | it into bytes. */ | |
1285 | #undef ASM_OUTPUT_ALIGNED_LOCAL | |
1286 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ | |
1287 | do \ | |
1288 | { \ | |
1289 | fputs ("\t.bss\t", (FILE)); \ | |
1290 | assemble_name ((FILE), (NAME)); \ | |
1291 | fprintf ((FILE), ",%d,%d\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \ | |
1292 | } \ | |
1293 | while (0) | |
1294 | ||
8f90be4c NC |
1295 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1296 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1297 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1298 | #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE) | |
1299 | ||
1300 | /* Print a memory address as an operand to reference that memory location. */ | |
1301 | #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X) | |
1302 | ||
1303 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
1304 | ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!') | |
1305 | ||
1306 | /* This is to handle loads from the constant pool. */ | |
1307 | #define MACHINE_DEPENDENT_REORG(X) mcore_dependent_reorg (X) | |
1308 | ||
8f90be4c NC |
1309 | #define PREDICATE_CODES \ |
1310 | { "mcore_arith_reg_operand", { REG, SUBREG }}, \ | |
1311 | { "mcore_general_movsrc_operand", { MEM, CONST_INT, REG, SUBREG }},\ | |
1312 | { "mcore_general_movdst_operand", { MEM, CONST_INT, REG, SUBREG }},\ | |
1313 | { "mcore_reload_operand", { MEM, REG, SUBREG }}, \ | |
1314 | { "mcore_arith_J_operand", { CONST_INT, REG, SUBREG }}, \ | |
1315 | { "mcore_arith_K_operand", { CONST_INT, REG, SUBREG }}, \ | |
1316 | { "mcore_arith_K_operand_not_0", { CONST_INT, REG, SUBREG }}, \ | |
1317 | { "mcore_arith_M_operand", { CONST_INT, REG, SUBREG }}, \ | |
1318 | { "mcore_arith_K_S_operand", { CONST_INT, REG, SUBREG }}, \ | |
1319 | { "mcore_arith_O_operand", { CONST_INT, REG, SUBREG }}, \ | |
1320 | { "mcore_arith_imm_operand", { CONST_INT, REG, SUBREG }}, \ | |
1321 | { "mcore_arith_any_imm_operand", { CONST_INT, REG, SUBREG }}, \ | |
1322 | { "mcore_literal_K_operand", { CONST_INT }}, \ | |
1323 | { "mcore_addsub_operand", { CONST_INT, REG, SUBREG }}, \ | |
1324 | { "mcore_compare_operand", { CONST_INT, REG, SUBREG }}, \ | |
1325 | { "mcore_load_multiple_operation", { PARALLEL }}, \ | |
1326 | { "mcore_store_multiple_operation", { PARALLEL }}, \ | |
1327 | { "mcore_call_address_operand", { REG, SUBREG, CONST_INT }}, \ | |
1328 | ||
88657302 | 1329 | #endif /* ! GCC_MCORE_H */ |