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8f90be4c NC |
1 | /* Definitions of target machine for GNU compiler, |
2 | for Motorola M*CORE Processor. | |
cbe34bb5 | 3 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
8f90be4c | 4 | |
31488c64 | 5 | This file is part of GCC. |
8f90be4c | 6 | |
31488c64 NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
31488c64 | 10 | option) any later version. |
8f90be4c | 11 | |
31488c64 NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
8f90be4c | 16 | |
31488c64 | 17 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
8f90be4c | 20 | |
88657302 RH |
21 | #ifndef GCC_MCORE_H |
22 | #define GCC_MCORE_H | |
8f90be4c NC |
23 | |
24 | /* RBE: need to move these elsewhere. */ | |
25 | #undef LIKE_PPC_ABI | |
26 | #define MCORE_STRUCT_ARGS | |
27 | /* RBE: end of "move elsewhere". */ | |
28 | ||
8f90be4c NC |
29 | /* Run-time Target Specification. */ |
30 | #define TARGET_MCORE | |
31 | ||
672a6f42 NB |
32 | /* Get tree.c to declare a target-specific specialization of |
33 | merge_decl_attributes. */ | |
b2ca3702 | 34 | #define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1 |
8f90be4c | 35 | |
f7248b51 NB |
36 | #define TARGET_CPU_CPP_BUILTINS() \ |
37 | do \ | |
38 | { \ | |
39 | builtin_define ("__mcore__"); \ | |
40 | builtin_define ("__MCORE__"); \ | |
f7248b51 NB |
41 | if (TARGET_LITTLE_END) \ |
42 | builtin_define ("__MCORELE__"); \ | |
43 | else \ | |
44 | builtin_define ("__MCOREBE__"); \ | |
45 | if (TARGET_M340) \ | |
46 | builtin_define ("__M340__"); \ | |
47 | else \ | |
48 | builtin_define ("__M210__"); \ | |
49 | } \ | |
50 | while (0) | |
8f90be4c | 51 | |
31488c64 NC |
52 | #undef CPP_SPEC |
53 | #define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}" | |
8f90be4c NC |
54 | |
55 | /* We don't have a -lg library, so don't put it in the list. */ | |
56 | #undef LIB_SPEC | |
57 | #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" | |
58 | ||
59 | #undef ASM_SPEC | |
60 | #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}" | |
61 | ||
62 | #undef LINK_SPEC | |
63 | #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X" | |
64 | ||
78fb8038 RS |
65 | #define TARGET_DEFAULT \ |
66 | (MASK_HARDLIT \ | |
78fb8038 RS |
67 | | MASK_DIV \ |
68 | | MASK_RELAX_IMM \ | |
69 | | MASK_M340 \ | |
70 | | MASK_LITTLE_END) | |
8f90be4c NC |
71 | |
72 | #ifndef MULTILIB_DEFAULTS | |
73 | #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" } | |
74 | #endif | |
75 | ||
8f90be4c | 76 | /* The ability to have 4 byte alignment is being suppressed for now. |
78fb8038 | 77 | If this ability is reenabled, you must disable the definition below |
8f90be4c | 78 | *and* edit t-mcore to enable multilibs for 4 byte alignment code. */ |
78fb8038 RS |
79 | #undef TARGET_8ALIGN |
80 | #define TARGET_8ALIGN 1 | |
8f90be4c NC |
81 | |
82 | extern char * mcore_current_function_name; | |
83 | ||
56ae9405 NC |
84 | /* The MCore ABI says that bitfields are unsigned by default. */ |
85 | #define CC1_SPEC "-funsigned-bitfields" | |
8f90be4c | 86 | |
8f90be4c NC |
87 | /* Target machine storage Layout. */ |
88 | ||
8f90be4c NC |
89 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
90 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
91 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
92 | { \ | |
93 | (MODE) = SImode; \ | |
94 | (UNSIGNEDP) = 1; \ | |
95 | } | |
96 | ||
8f90be4c NC |
97 | /* Define this if most significant bit is lowest numbered |
98 | in instructions that operate on numbered bit-fields. */ | |
99 | #define BITS_BIG_ENDIAN 0 | |
100 | ||
101 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
102 | #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END) | |
103 | ||
104 | /* Define this if most significant word of a multiword number is the lowest | |
105 | numbered. */ | |
106 | #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END) | |
107 | ||
8f90be4c NC |
108 | #define MAX_BITS_PER_WORD 32 |
109 | ||
110 | /* Width of a word, in units (bytes). */ | |
111 | #define UNITS_PER_WORD 4 | |
112 | ||
8f90be4c NC |
113 | /* A C expression for the size in bits of the type `long long' on the |
114 | target machine. If you don't define this, the default is two | |
115 | words. */ | |
116 | #define LONG_LONG_TYPE_SIZE 64 | |
117 | ||
8f90be4c NC |
118 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
119 | #define PARM_BOUNDARY 32 | |
120 | ||
8f90be4c NC |
121 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
122 | #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32) | |
123 | ||
124 | /* Largest increment in UNITS we allow the stack to grow in a single operation. */ | |
8f90be4c NC |
125 | #define STACK_UNITS_MAXSTEP 4096 |
126 | ||
127 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
128 | #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16) | |
129 | ||
130 | /* Alignment of field after `int : 0' in a structure. */ | |
131 | #define EMPTY_FIELD_BOUNDARY 32 | |
132 | ||
133 | /* No data type wants to be aligned rounder than this. */ | |
134 | #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32) | |
135 | ||
136 | /* The best alignment to use in cases where we have a choice. */ | |
137 | #define FASTEST_ALIGNMENT 32 | |
138 | ||
139 | /* Every structures size must be a multiple of 8 bits. */ | |
140 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
141 | ||
43a88a8c | 142 | /* Look at the fundamental type that is used for a bit-field and use |
8f90be4c NC |
143 | that to impose alignment on the enclosing structure. |
144 | struct s {int a:8}; should have same alignment as "int", not "char". */ | |
145 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
146 | ||
147 | /* Largest integer machine mode for structures. If undefined, the default | |
148 | is GET_MODE_SIZE(DImode). */ | |
149 | #define MAX_FIXED_MODE_SIZE 32 | |
150 | ||
151 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
152 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
153 | ((TREE_CODE (EXP) == STRING_CST \ | |
154 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
155 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
156 | ||
157 | /* Make arrays of chars word-aligned for the same reasons. */ | |
158 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
159 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
160 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
161 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
162 | ||
163 | /* Set this nonzero if move instructions will actually fail to work | |
164 | when given unaligned data. */ | |
165 | #define STRICT_ALIGNMENT 1 | |
166 | ||
167 | /* Standard register usage. */ | |
168 | ||
169 | /* Register allocation for our first guess | |
170 | ||
171 | r0 stack pointer | |
172 | r1 scratch, target reg for xtrb? | |
173 | r2-r7 arguments. | |
174 | r8-r14 call saved | |
175 | r15 link register | |
176 | ap arg pointer (doesn't really exist, always eliminated) | |
177 | c c bit | |
178 | fp frame pointer (doesn't really exist, always eliminated) | |
08903e08 | 179 | x19 two control registers. */ |
8f90be4c NC |
180 | |
181 | /* Number of actual hardware registers. | |
182 | The hardware registers are assigned numbers for the compiler | |
183 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
184 | All registers that the compiler knows about must be given numbers, | |
185 | even those that are not normally considered general registers. | |
186 | ||
187 | MCore has 16 integer registers and 2 control registers + the arg | |
188 | pointer. */ | |
189 | ||
190 | #define FIRST_PSEUDO_REGISTER 20 | |
191 | ||
08903e08 SB |
192 | #define R1_REG 1 /* Where literals are forced. */ |
193 | #define LK_REG 15 /* Overloaded on general register. */ | |
194 | #define AP_REG 16 /* Fake arg pointer register. */ | |
195 | /* RBE: mcore.md depends on CC_REG being set to 17. */ | |
196 | #define CC_REG 17 /* Can't name it C_REG. */ | |
197 | #define FP_REG 18 /* Fake frame pointer register. */ | |
8f90be4c NC |
198 | |
199 | /* Specify the registers used for certain standard purposes. | |
200 | The values of these macros are register numbers. */ | |
201 | ||
202 | ||
203 | #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */ | |
204 | #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */ | |
205 | #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */ | |
206 | ||
207 | /* The assembler's names for the registers. RFP need not always be used as | |
208 | the Real framepointer; it can also be used as a normal general register. | |
209 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
210 | the argument-and-return-context pointer. */ | |
211 | #define REGISTER_NAMES \ | |
212 | { \ | |
213 | "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
214 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
215 | "apvirtual", "c", "fpvirtual", "x19" \ | |
216 | } | |
217 | ||
218 | /* 1 for registers that have pervasive standard uses | |
219 | and are not available for the register allocator. */ | |
220 | #define FIXED_REGISTERS \ | |
221 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
222 | { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
223 | ||
224 | /* 1 for registers not available across function calls. | |
225 | These must include the FIXED_REGISTERS and also any | |
226 | registers that can be used without being saved. | |
227 | The latter must include the registers where values are returned | |
228 | and the register where structure-value addresses are passed. | |
229 | Aside from that, you can include as many other registers as you like. */ | |
230 | ||
231 | /* RBE: r15 {link register} not available across calls, | |
14bc6742 | 232 | But we don't mark it that way here.... */ |
8f90be4c NC |
233 | #define CALL_USED_REGISTERS \ |
234 | /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \ | |
235 | { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1} | |
236 | ||
237 | /* The order in which register should be allocated. */ | |
238 | #define REG_ALLOC_ORDER \ | |
239 | /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \ | |
240 | { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19} | |
241 | ||
242 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
243 | to hold something of mode MODE. | |
244 | This is ordinarily the length in words of a value of mode MODE | |
245 | but can be less for certain modes in special long registers. | |
246 | ||
247 | On the MCore regs are UNITS_PER_WORD bits wide; */ | |
248 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
249 | (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
250 | ||
8f90be4c NC |
251 | /* Value is 1 if it is a good idea to tie two pseudo registers |
252 | when one has mode MODE1 and one has mode MODE2. | |
f939c3e6 RS |
253 | If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1 |
254 | and MODE2, for any hard reg, then this must be 0 for correct output. */ | |
8f90be4c NC |
255 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
256 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
257 | ||
8f90be4c NC |
258 | /* Definitions for register eliminations. |
259 | ||
260 | We have two registers that can be eliminated on the MCore. First, the | |
261 | frame pointer register can often be eliminated in favor of the stack | |
262 | pointer register. Secondly, the argument pointer register can always be | |
263 | eliminated; it is replaced with either the stack or frame pointer. */ | |
264 | ||
265 | /* Base register for access to arguments of the function. */ | |
266 | #define ARG_POINTER_REGNUM 16 | |
267 | ||
268 | /* Register in which the static-chain is passed to a function. */ | |
269 | #define STATIC_CHAIN_REGNUM 1 | |
270 | ||
271 | /* This is an array of structures. Each structure initializes one pair | |
272 | of eliminable registers. The "from" register number is given first, | |
273 | followed by "to". Eliminations of the same "from" register are listed | |
274 | in order of preference. */ | |
275 | #define ELIMINABLE_REGS \ | |
276 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
277 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
278 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
279 | ||
8f90be4c NC |
280 | /* Define the offset between two registers, one to be eliminated, and the other |
281 | its replacement, at the start of a routine. */ | |
282 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
283 | OFFSET = mcore_initial_elimination_offset (FROM, TO) | |
284 | ||
8f90be4c NC |
285 | /* Define the classes of registers for register constraints in the |
286 | machine description. Also define ranges of constants. | |
287 | ||
288 | One of the classes must always be named ALL_REGS and include all hard regs. | |
289 | If there is more than one class, another class must be named NO_REGS | |
290 | and contain no registers. | |
291 | ||
292 | The name GENERAL_REGS must be the name of a class (or an alias for | |
293 | another name such as ALL_REGS). This is the class of registers | |
294 | that is allowed by "g" or "r" in a register constraint. | |
295 | Also, registers outside this class are allocated only when | |
296 | instructions express preferences for them. | |
297 | ||
298 | The classes must be numbered in nondecreasing order; that is, | |
299 | a larger-numbered class must never be contained completely | |
300 | in a smaller-numbered class. | |
301 | ||
302 | For any two classes, it is very desirable that there be another | |
303 | class that represents their union. */ | |
304 | ||
305 | /* The MCore has only general registers. There are | |
306 | also some special purpose registers: the T bit register, the | |
08903e08 | 307 | procedure Link and the Count Registers. */ |
8f90be4c NC |
308 | enum reg_class |
309 | { | |
310 | NO_REGS, | |
311 | ONLYR1_REGS, | |
312 | LRW_REGS, | |
313 | GENERAL_REGS, | |
314 | C_REGS, | |
315 | ALL_REGS, | |
316 | LIM_REG_CLASSES | |
317 | }; | |
318 | ||
319 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
320 | ||
d43b42f9 | 321 | |
14bc6742 | 322 | /* Give names of register classes as strings for dump file. */ |
8f90be4c NC |
323 | #define REG_CLASS_NAMES \ |
324 | { \ | |
325 | "NO_REGS", \ | |
326 | "ONLYR1_REGS", \ | |
327 | "LRW_REGS", \ | |
328 | "GENERAL_REGS", \ | |
329 | "C_REGS", \ | |
330 | "ALL_REGS", \ | |
331 | } | |
332 | ||
333 | /* Define which registers fit in which classes. | |
334 | This is an initializer for a vector of HARD_REG_SET | |
335 | of length N_REG_CLASSES. */ | |
336 | ||
337 | /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */ | |
338 | #define REG_CLASS_CONTENTS \ | |
339 | { \ | |
340 | {0x000000}, /* NO_REGS */ \ | |
341 | {0x000002}, /* ONLYR1_REGS */ \ | |
342 | {0x007FFE}, /* LRW_REGS */ \ | |
343 | {0x01FFFF}, /* GENERAL_REGS */ \ | |
344 | {0x020000}, /* C_REGS */ \ | |
345 | {0x0FFFFF} /* ALL_REGS */ \ | |
346 | } | |
347 | ||
348 | /* The same information, inverted: | |
349 | Return the class number of the smallest class containing | |
350 | reg number REGNO. This could be a conditional expression | |
351 | or could index an array. */ | |
352 | ||
5a82ecd9 | 353 | extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; |
e1ea7451 | 354 | #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER ? regno_reg_class[REGNO] : NO_REGS) |
8f90be4c | 355 | |
42db504c SB |
356 | /* When this hook returns true for MODE, the compiler allows |
357 | registers explicitly used in the rtl to be used as spill registers | |
358 | but prevents the compiler from extending the lifetime of these | |
359 | registers. */ | |
360 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
8f90be4c NC |
361 | |
362 | /* The class value for index registers, and the one for base regs. */ | |
363 | #define INDEX_REG_CLASS NO_REGS | |
364 | #define BASE_REG_CLASS GENERAL_REGS | |
365 | ||
944f4bb3 NF |
366 | /* Convenience wrappers around insn_const_int_ok_for_constraint. */ |
367 | #define CONST_OK_FOR_I(VALUE) \ | |
368 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_I) | |
369 | #define CONST_OK_FOR_J(VALUE) \ | |
370 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_J) | |
371 | #define CONST_OK_FOR_L(VALUE) \ | |
372 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_L) | |
373 | #define CONST_OK_FOR_K(VALUE) \ | |
374 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_K) | |
375 | #define CONST_OK_FOR_M(VALUE) \ | |
376 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_M) | |
377 | #define CONST_OK_FOR_N(VALUE) \ | |
378 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_N) | |
379 | #define CONST_OK_FOR_O(VALUE) \ | |
380 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_O) | |
381 | #define CONST_OK_FOR_P(VALUE) \ | |
382 | insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_P) | |
8f90be4c NC |
383 | |
384 | /* Given an rtx X being reloaded into a reg required to be | |
385 | in class CLASS, return the class of reg to actually use. | |
386 | In general this is just CLASS; but on some machines | |
387 | in some cases it is preferable to use a more restrictive class. */ | |
388 | #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS) | |
389 | ||
390 | /* Return the register class of a scratch register needed to copy IN into | |
391 | or out of a register in CLASS in MODE. If it can be done directly, | |
392 | NO_REGS is returned. */ | |
f0f4da32 RS |
393 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ |
394 | mcore_secondary_reload_class (CLASS, MODE, X) | |
8f90be4c NC |
395 | |
396 | /* Return the maximum number of consecutive registers | |
397 | needed to represent mode MODE in a register of class CLASS. | |
398 | ||
399 | On MCore this is the size of MODE in words. */ | |
400 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
401 | (ROUND_ADVANCE (GET_MODE_SIZE (MODE))) | |
402 | ||
403 | /* Stack layout; function entry, exit and calling. */ | |
404 | ||
405 | /* Define the number of register that can hold parameters. | |
406 | These two macros are used only in other macro definitions below. */ | |
407 | #define NPARM_REGS 6 | |
408 | #define FIRST_PARM_REG 2 | |
409 | #define FIRST_RET_REG 2 | |
410 | ||
411 | /* Define this if pushing a word on the stack | |
412 | makes the stack pointer a smaller address. */ | |
62f9f30b | 413 | #define STACK_GROWS_DOWNWARD 1 |
8f90be4c | 414 | |
8f90be4c NC |
415 | /* Offset within stack frame to start allocating local variables at. |
416 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
417 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
418 | of the first local allocated. */ | |
419 | #define STARTING_FRAME_OFFSET 0 | |
420 | ||
421 | /* If defined, the maximum amount of space required for outgoing arguments | |
422 | will be computed and placed into the variable | |
38173d38 | 423 | `crtl->outgoing_args_size'. No space will be pushed |
8f90be4c NC |
424 | onto the stack for each call; instead, the function prologue should |
425 | increase the stack frame size by this amount. */ | |
f73ad30e | 426 | #define ACCUMULATE_OUTGOING_ARGS 1 |
8f90be4c NC |
427 | |
428 | /* Offset of first parameter from the argument pointer register value. */ | |
429 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
430 | ||
8f90be4c NC |
431 | /* Define how to find the value returned by a function. |
432 | VALTYPE is the data type of the value (as a tree). | |
433 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
434 | otherwise, FUNC is 0. */ | |
435 | #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC) | |
436 | ||
437 | /* Don't default to pcc-struct-return, because gcc is the only compiler, and | |
438 | we want to retain compatibility with older gcc versions. */ | |
439 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
440 | ||
8f90be4c NC |
441 | /* Define how to find the value returned by a library function |
442 | assuming the value has mode MODE. */ | |
f1c25d3b | 443 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG) |
8f90be4c NC |
444 | |
445 | /* 1 if N is a possible register number for a function value. | |
446 | On the MCore, only r4 can return results. */ | |
447 | #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) | |
448 | ||
8f90be4c NC |
449 | /* 1 if N is a possible register number for function argument passing. */ |
450 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
451 | ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) | |
452 | ||
453 | /* Define a data type for recording info about an argument list | |
454 | during the scan of that argument list. This data type should | |
455 | hold all necessary information about the function itself | |
456 | and about the args processed so far, enough to enable macros | |
457 | such as FUNCTION_ARG to determine where the next arg should go. | |
458 | ||
459 | On MCore, this is a single integer, which is a number of words | |
460 | of arguments scanned so far (including the invisible argument, | |
461 | if any, which holds the structure-value-address). | |
462 | Thus NARGREGS or more means all following args should go on the stack. */ | |
463 | #define CUMULATIVE_ARGS int | |
464 | ||
465 | #define ROUND_ADVANCE(SIZE) \ | |
466 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
467 | ||
468 | /* Round a register number up to a proper boundary for an arg of mode | |
469 | MODE. | |
470 | ||
471 | We round to an even reg for things larger than a word. */ | |
472 | #define ROUND_REG(X, MODE) \ | |
473 | ((TARGET_8ALIGN \ | |
474 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
475 | ? ((X) + ((X) & 1)) : (X)) | |
476 | ||
477 | ||
478 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
479 | for a call to a function whose data type is FNTYPE. | |
480 | For a library call, FNTYPE is 0. | |
481 | ||
482 | On MCore, the offset always starts at 0: the first parm reg is always | |
483 | the same reg. */ | |
0f6937fe | 484 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
8f90be4c NC |
485 | ((CUM) = 0) |
486 | ||
8f90be4c NC |
487 | /* Call the function profiler with a given profile label. */ |
488 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ | |
489 | { \ | |
490 | fprintf (STREAM, " trap 1\n"); \ | |
491 | fprintf (STREAM, " .align 2\n"); \ | |
492 | fprintf (STREAM, " .long LP%d\n", (LABELNO)); \ | |
493 | } | |
494 | ||
495 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
496 | the stack pointer does not matter. The value is tested only in | |
497 | functions that have frame pointers. | |
498 | No definition is equivalent to always zero. */ | |
499 | #define EXIT_IGNORE_STACK 0 | |
500 | ||
8f90be4c NC |
501 | /* Length in units of the trampoline for entering a nested function. */ |
502 | #define TRAMPOLINE_SIZE 12 | |
503 | ||
006946e4 JM |
504 | /* Alignment required for a trampoline in bits. */ |
505 | #define TRAMPOLINE_ALIGNMENT 32 | |
8f90be4c | 506 | |
8f90be4c NC |
507 | /* Macros to check register numbers against specific register classes. */ |
508 | ||
509 | /* These assume that REGNO is a hard or pseudo reg number. | |
510 | They give nonzero only if REGNO is a hard reg of the suitable class | |
511 | or a pseudo reg currently allocated to a suitable hard reg. | |
512 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
513 | has been allocated, which happens in reginfo.c during register |
514 | allocation. */ | |
8f90be4c NC |
515 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
516 | ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG) | |
517 | ||
518 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
519 | ||
520 | /* Maximum number of registers that can appear in a valid memory | |
521 | address. */ | |
522 | #define MAX_REGS_PER_ADDRESS 1 | |
523 | ||
524 | /* Recognize any constant value that is a valid address. */ | |
525 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) | |
526 | ||
8f90be4c NC |
527 | /* Specify the machine mode that this machine uses |
528 | for the index in the tablejump instruction. */ | |
529 | #define CASE_VECTOR_MODE SImode | |
530 | ||
8f90be4c NC |
531 | /* 'char' is signed by default. */ |
532 | #define DEFAULT_SIGNED_CHAR 0 | |
533 | ||
ed38428f | 534 | #undef SIZE_TYPE |
8f90be4c NC |
535 | #define SIZE_TYPE "unsigned int" |
536 | ||
ed38428f JM |
537 | #undef PTRDIFF_TYPE |
538 | #define PTRDIFF_TYPE "int" | |
539 | ||
540 | #undef WCHAR_TYPE | |
541 | #define WCHAR_TYPE "long int" | |
542 | ||
543 | #undef WCHAR_TYPE_SIZE | |
544 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
545 | ||
8f90be4c NC |
546 | /* Max number of bytes we can move from memory to memory |
547 | in one reasonably fast instruction. */ | |
548 | #define MOVE_MAX 4 | |
549 | ||
550 | /* Define if operations between registers always perform the operation | |
551 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 552 | #define WORD_REGISTER_OPERATIONS 1 |
8f90be4c NC |
553 | |
554 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
555 | will either zero-extend or sign-extend. The value of this macro should | |
556 | be the code that says which one of the two operations is implicitly | |
f822d252 | 557 | done, UNKNOWN if none. */ |
8f90be4c NC |
558 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
559 | ||
560 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
561 | #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES | |
562 | ||
90e0c734 JW |
563 | /* Shift counts are truncated to 6-bits (0 to 63) instead of the expected |
564 | 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this | |
565 | target. */ | |
566 | #define SHIFT_COUNT_TRUNCATED 0 | |
8f90be4c NC |
567 | |
568 | /* All integers have the same format so truncation is easy. */ | |
569 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
570 | ||
571 | /* Define this if addresses of constant functions | |
572 | shouldn't be put through pseudo regs where they can be cse'd. | |
573 | Desirable on machines where ordinary constants are expensive | |
574 | but a CALL with constant address is cheap. */ | |
14bc6742 | 575 | /* Why is this defined??? -- dac */ |
8f90be4c NC |
576 | #define NO_FUNCTION_CSE 1 |
577 | ||
8f90be4c NC |
578 | /* The machine modes of pointers and functions. */ |
579 | #define Pmode SImode | |
580 | #define FUNCTION_MODE Pmode | |
581 | ||
8f90be4c NC |
582 | /* Compute extra cost of moving data between one register class |
583 | and another. All register moves are cheap. */ | |
cf011243 | 584 | #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2 |
8f90be4c | 585 | |
9e11bfef | 586 | #define WORD_REGISTER_OPERATIONS 1 |
8f90be4c | 587 | |
8f90be4c NC |
588 | /* Assembler output control. */ |
589 | #define ASM_COMMENT_START "\t//" | |
590 | ||
591 | #define ASM_APP_ON "// inline asm begin\n" | |
592 | #define ASM_APP_OFF "// inline asm end\n" | |
593 | ||
594 | #define FILE_ASM_OP "\t.file\n" | |
595 | ||
596 | /* Switch to the text or data segment. */ | |
597 | #define TEXT_SECTION_ASM_OP "\t.text" | |
598 | #define DATA_SECTION_ASM_OP "\t.data" | |
599 | ||
7c262518 | 600 | /* Switch into a generic section. */ |
6e3a343d | 601 | #undef TARGET_ASM_NAMED_SECTION |
7c262518 | 602 | #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section |
8f90be4c | 603 | |
fd02e833 NF |
604 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LK_REG) |
605 | ||
8f90be4c NC |
606 | /* This is how to output an insn to push a register on the stack. |
607 | It need not be very fast code. */ | |
608 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
609 | fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \ | |
610 | reg_names[STACK_POINTER_REGNUM], \ | |
611 | (STACK_BOUNDARY / BITS_PER_UNIT), \ | |
612 | reg_names[REGNO], \ | |
613 | reg_names[STACK_POINTER_REGNUM]) | |
614 | ||
615 | /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ | |
616 | #define REG_PUSH_LENGTH 2 | |
617 | ||
618 | /* This is how to output an insn to pop a register from the stack. */ | |
619 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
620 | fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \ | |
621 | reg_names[REGNO], \ | |
622 | reg_names[STACK_POINTER_REGNUM], \ | |
623 | reg_names[STACK_POINTER_REGNUM], \ | |
624 | (STACK_BOUNDARY / BITS_PER_UNIT)) | |
625 | ||
626 | ||
8f90be4c NC |
627 | /* Output a reference to a label. */ |
628 | #undef ASM_OUTPUT_LABELREF | |
629 | #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
772c5265 RH |
630 | fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ |
631 | (* targetm.strip_name_encoding) (NAME)) | |
8f90be4c NC |
632 | |
633 | /* This is how to output an assembler line | |
634 | that says to advance the location counter | |
635 | to a multiple of 2**LOG bytes. */ | |
636 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
637 | if ((LOG) != 0) \ | |
638 | fprintf (FILE, "\t.align\t%d\n", LOG) | |
639 | ||
640 | #ifndef ASM_DECLARE_RESULT | |
641 | #define ASM_DECLARE_RESULT(FILE, RESULT) | |
642 | #endif | |
643 | ||
8f90be4c NC |
644 | #define MULTIPLE_SYMBOL_SPACES 1 |
645 | ||
646 | #define SUPPORTS_ONE_ONLY 1 | |
647 | ||
648 | /* A pair of macros to output things for the callgraph data. | |
649 | VALUE means (to the tools that reads this info later): | |
650 | 0 a call from src to dst | |
651 | 1 the call is special (e.g. dst is "unknown" or "alloca") | |
652 | 2 the call is special (e.g., the src is a table instead of routine) | |
653 | ||
654 | Frame sizes are augmented with timestamps to help later tools | |
655 | differentiate between static entities with same names in different | |
656 | files. */ | |
657 | extern long mcore_current_compilation_timestamp; | |
658 | #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \ | |
659 | do \ | |
660 | { \ | |
661 | if (mcore_current_compilation_timestamp == 0) \ | |
662 | mcore_current_compilation_timestamp = time (0); \ | |
663 | fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \ | |
664 | (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \ | |
665 | } \ | |
666 | while (0) | |
667 | ||
668 | #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \ | |
669 | do \ | |
670 | { \ | |
671 | fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \ | |
672 | (SRCNAME), (DSTNAME), (VALUE)); \ | |
673 | } \ | |
674 | while (0) | |
675 | ||
506a61b1 KG |
676 | /* Globalizing directive for a label. */ |
677 | #define GLOBAL_ASM_OP "\t.export\t" | |
8f90be4c | 678 | |
31488c64 | 679 | /* The prefix to add to user-visible assembler symbols. */ |
8f90be4c NC |
680 | #undef USER_LABEL_PREFIX |
681 | #define USER_LABEL_PREFIX "" | |
682 | ||
683 | /* Make an internal label into a string. */ | |
684 | #undef ASM_GENERATE_INTERNAL_LABEL | |
685 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ | |
686 | sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM) | |
687 | ||
31488c64 | 688 | /* Jump tables must be 32 bit aligned. */ |
8f90be4c NC |
689 | #undef ASM_OUTPUT_CASE_LABEL |
690 | #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ | |
691 | fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM); | |
692 | ||
693 | /* Output a relative address. Not needed since jump tables are absolute | |
694 | but we must define it anyway. */ | |
695 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ | |
696 | fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) | |
697 | ||
698 | /* Output an element of a dispatch table. */ | |
699 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
700 | fprintf (STREAM, "\t.long\t.L%d\n", VALUE) | |
701 | ||
702 | /* Output various types of constants. */ | |
703 | ||
8f90be4c NC |
704 | /* This is how to output an assembler line |
705 | that says to advance the location counter by SIZE bytes. */ | |
706 | #undef ASM_OUTPUT_SKIP | |
707 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 708 | fprintf (FILE, "\t.fill %d, 1\n", (int)(SIZE)) |
8f90be4c NC |
709 | |
710 | /* This says how to output an assembler line | |
711 | to define a global common symbol, with alignment information. */ | |
712 | /* XXX - for now we ignore the alignment. */ | |
713 | #undef ASM_OUTPUT_ALIGNED_COMMON | |
714 | #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
715 | do \ | |
716 | { \ | |
717 | if (mcore_dllexport_name_p (NAME)) \ | |
718 | MCORE_EXPORT_NAME (FILE, NAME) \ | |
719 | if (! mcore_dllimport_name_p (NAME)) \ | |
720 | { \ | |
721 | fputs ("\t.comm\t", FILE); \ | |
722 | assemble_name (FILE, NAME); \ | |
74eda121 | 723 | fprintf (FILE, ",%lu\n", (unsigned long)(SIZE)); \ |
8f90be4c NC |
724 | } \ |
725 | } \ | |
726 | while (0) | |
727 | ||
8f90be4c | 728 | /* This says how to output an assembler line |
14bc6742 | 729 | to define a local common symbol.... */ |
8f90be4c NC |
730 | #undef ASM_OUTPUT_LOCAL |
731 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
732 | (fputs ("\t.lcomm\t", FILE), \ | |
733 | assemble_name (FILE, NAME), \ | |
58e15542 | 734 | fprintf (FILE, ",%d\n", (int)SIZE)) |
8f90be4c NC |
735 | |
736 | /* ... and how to define a local common symbol whose alignment | |
737 | we wish to specify. ALIGN comes in as bits, we have to turn | |
738 | it into bytes. */ | |
739 | #undef ASM_OUTPUT_ALIGNED_LOCAL | |
740 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ | |
741 | do \ | |
742 | { \ | |
743 | fputs ("\t.bss\t", (FILE)); \ | |
744 | assemble_name ((FILE), (NAME)); \ | |
58e15542 | 745 | fprintf ((FILE), ",%d,%d\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ |
8f90be4c NC |
746 | } \ |
747 | while (0) | |
748 | ||
88657302 | 749 | #endif /* ! GCC_MCORE_H */ |