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target.def (legitimate_constant_p): New hook.
[thirdparty/gcc.git] / gcc / config / mep / mep.h
CommitLineData
7acf4da6 1/* Definitions for Toshiba Media Processor
eb1eb914 2 Copyright (C) 2001, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
7acf4da6
DD		 3 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21\f
22
23#undef CPP_SPEC
24#define CPP_SPEC "\
25-D__MEP__ -D__MeP__ \
26-D__section(_x)=__attribute__((section(_x))) \
27-D__align(_x)=__attribute__((aligned(_x))) \
28-D__io(_x)=__attribute__((io(_x))) \
29-D__cb(_x)=__attribute__((cb(_x))) \
30-D__based=__attribute__((based)) \
31-D__tiny=__attribute__((tiny)) \
32-D__near=__attribute__((near)) \
33-D__far=__attribute__((far)) \
34-D__vliw=__attribute__((vliw)) \
35-D__interrupt=__attribute__((interrupt)) \
36-D__disinterrupt=__attribute__((disinterrupt)) \
7acf4da6
DD		 37%{!meb:%{!mel:-D__BIG_ENDIAN__}} \
38%{meb:-U__LITTLE_ENDIAN__ -D__BIG_ENDIAN__} \
39%{mel:-U__BIG_ENDIAN__ -D__LITTLE_ENDIAN__} \
40%{mconfig=*:-D__MEP_CONFIG_%*} \
41%{mivc2:-D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64} \
42"
43
44#undef CC1_SPEC
45#define CC1_SPEC "%{!mlibrary:%(config_cc_spec)} \
1700c2e7
DD		 46%{!.cc:%{O2:%{!funroll*:--param max-completely-peeled-insns=6 \
47 --param max-unrolled-insns=6 -funroll-loops}}}"
7acf4da6
DD		 48
49#undef CC1PLUS_SPEC
50#define CC1PLUS_SPEC "%{!mlibrary:%(config_cc_spec)}"
51
52#undef ASM_SPEC
53#define ASM_SPEC "%{mconfig=*} %{meb:-EB} %{mel:-EL} \
54%{mno-satur} %{msatur} %{mno-clip} %{mclip} %{mno-minmax} %{mminmax} \
55%{mno-absdiff} %{mabsdiff} %{mno-leadz} %{mleadz} %{mno-bitops} %{mbitops} \
56%{mno-div} %{mdiv} %{mno-mult} %{mmult} %{mno-average} %{maverage} \
57%{mcop32} %{mno-debug} %{mdebug} %{mlibrary}"
58
59/* The MeP config tool will edit this spec. */
60#undef STARTFILE_SPEC
61#define STARTFILE_SPEC "%{msdram:%{msim:simsdram-crt0.o%s}} \
62%{mno-sdram:%{msim:sim-crt0.o%s}} \
63%{msdram:%{!msim*:sdram-crt0.o%s}} \
64%{mno-sdram:%{!msim*:crt0.o%s}} \
65%(config_start_spec) \
66%{msimnovec:simnovec-crt0.o%s} \
67crtbegin.o%s"
68
69#undef LIB_SPEC
70#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) %(config_link_spec)"
71
72#undef LINK_SPEC
73#define LINK_SPEC "%{meb:-EB} %{mel:-EL}"
74
75#undef ENDFILE_SPEC
76#define ENDFILE_SPEC "crtend.o%s %{msim*:sim-crtn.o%s}%{!msim*:crtn.o%s}"
77
78/* The MeP config tool will edit this spec. */
79#define CONFIG_CC_SPEC "\
80%{mconfig=default: -mbitops -mleadz -mabsdiff -maverage -mminmax -mclip -msatur -mvl64 -mvliw -mcop64 -D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64 -mivc2}\
81"
82/* end-config-cc-spec */
83
84/* The MeP config tool will edit this spec. */
85#define CONFIG_LINK_SPEC "\
86%{mconfig=default: %{!T*:-Tdefault.ld}}\
87"
88/* end-config-link-spec */
89
90/* The MeP config tool will edit this spec. */
91#define CONFIG_START_SPEC "\
92%{!msdram:%{!mno-sdram:%{!msim*:crt0.o%s}}} \
93%{!msdram:%{!mno-sdram:%{msim:sim-crt0.o%s}}} \
94"
95/* end-config-start-spec */
96
97#define EXTRA_SPECS \
98 { "config_cc_spec", CONFIG_CC_SPEC }, \
99 { "config_link_spec", CONFIG_LINK_SPEC }, \
100 { "config_start_spec", CONFIG_START_SPEC },
101\f
102
103#define TARGET_CPU_CPP_BUILTINS() \
104 do \
105 { \
106 builtin_define_std ("mep"); \
107 builtin_assert ("machine=mep"); \
108 } \
109 while (0)
110
7acf4da6
DD		 111/* Controlled by MeP-Integrator. */
112#define TARGET_H1 0
113
114#define MEP_ALL_OPTS (MASK_OPT_AVERAGE \
115 | MASK_OPT_MULT \
116 | MASK_OPT_DIV \
117 | MASK_OPT_BITOPS \
118 | MASK_OPT_LEADZ \
119 | MASK_OPT_ABSDIFF \
120 | MASK_OPT_MINMAX \
121 | MASK_OPT_CLIP \
122 | MASK_OPT_SATUR )
123
124#define TARGET_DEFAULT (MASK_IO_VOLATILE | MASK_OPT_REPEAT | MEP_ALL_OPTS | MASK_LITTLE_ENDIAN)
125
126#define TARGET_IO_NO_VOLATILE (! (target_flags & MASK_IO_VOLATILE))
127#define TARGET_OPT_NOREPEAT (! (target_flags & MASK_OPT_REPEAT))
128#define TARGET_32BIT_CR_REGS (! (target_flags & MASK_64BIT_CR_REGS))
129#define TARGET_BIG_ENDIAN (! (target_flags & MASK_LITTLE_ENDIAN))
130
131#define TARGET_COPRO_MULT 0
132
7acf4da6
DD		 133/* The MeP config tool will replace this as appropriate. */
134#define DEFAULT_ENDIAN_SPEC "%{!meb: -mel}"
135
136/* The MeP config tool will replace this with an -mconfig= switch. */
137#define LIBRARY_CONFIG_SPEC "-mconfig=default"
138
139/* Don't add an endian option when building the libraries. */
140#define DRIVER_SELF_SPECS \
141 "%{!mlibrary:" DEFAULT_ENDIAN_SPEC "}", \
2be55a25
JM		 142 "%{mlibrary: " LIBRARY_CONFIG_SPEC " %{!mel:-meb}}", \
143 "%{mall-opts:-maverage -mmult -mdiv -mbitops -mleadz \
144 -mabsdiff -mminmax -mclip -msatur -mdebug} %<mall-opts", \
145 "%{mno-opts:-mno-average -mno-mult -mno-div -mno-bitops -mno-leadz \
146 -mno-absdiff -mno-minmax -mno-clip -mno-satur -mno-debug} %<mno-opts", \
147 "%{mfar:-ml -mtf -mc=far} %<mfar", \
148 "%{mconfig=default:-mmult -mdiv -D__MEP_CONFIG_ISA=1}"
7acf4da6
DD		 149
150/* The MeP config tool will add COPROC_SELECTION_TABLE here. */
151/* start-coproc-selection-table */
152#define COPROC_SELECTION_TABLE \
153{"default", ISA_EXT1}
154/* end-coproc-selection-table */
7acf4da6
DD		 155\f
156
157#define BITS_BIG_ENDIAN 0
158#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1)
159#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1)
160
7acf4da6
DD		 161#define UNITS_PER_WORD 4
162
163#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
164 do \
165 { \
166 if (GET_MODE_CLASS (MODE) == MODE_INT \
167 && GET_MODE_SIZE (MODE) < 4) \
168 (MODE) = SImode; \
169 } \
170 while (0)
171
172#define PARM_BOUNDARY 32
173#define STACK_BOUNDARY 32
174#define PREFERRED_STACK_BOUNDARY 64
175#define FUNCTION_BOUNDARY 16
176#define BIGGEST_ALIGNMENT 64
177
178#define DATA_ALIGNMENT(TYPE, ALIGN) \
179 (TREE_CODE (TYPE) == ARRAY_TYPE \
180 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
181 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
182
183#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
184 (TREE_CODE (EXP) == STRING_CST \
185 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
186
187#define STRICT_ALIGNMENT 1
188
189#define PCC_BITFIELD_TYPE_MATTERS 1
190
191#define DEFAULT_VTABLE_THUNKS 1
192
193\f
194#define INT_TYPE_SIZE 32
195#define SHORT_TYPE_SIZE 16
196#define LONG_TYPE_SIZE 32
197#define LONG_LONG_TYPE_SIZE 64
198#define CHAR_TYPE_SIZE 8
199#define FLOAT_TYPE_SIZE 32
200#define DOUBLE_TYPE_SIZE 64
201#define LONG_DOUBLE_TYPE_SIZE 64
202#define DEFAULT_SIGNED_CHAR 1
e195f6e0
JM		 203
204#undef SIZE_TYPE
205#define SIZE_TYPE "unsigned int"
206
207#undef PTRDIFF_TYPE
208#define PTRDIFF_TYPE "int"
209
210#undef WCHAR_TYPE
211#define WCHAR_TYPE "long int"
212
213#undef WCHAR_TYPE_SIZE
214#define WCHAR_TYPE_SIZE BITS_PER_WORD
7acf4da6
DD		 215\f
216/* Register numbers:
217 0..15 core registers
218 16..47 control registers
219 48..79 coprocessor registers
220 80..111 coprocessor control registers
221 112 virtual arg pointer register */
222
223#define FIRST_PSEUDO_REGISTER (LAST_SHADOW_REGISTER + 1)
224
225 /* R12 is optionally FP. R13 is TP, R14 is GP, R15 is SP. */
226 /* hi and lo can be used as general registers. Others have
227 immutable bits. */
228/* A "1" here means the register is generally not available to gcc,
229 and is assumed to remain unchanged or unused throughout. */
230#define FIXED_REGISTERS { \
231 /* core registers */ \
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
233 /* control registers */ \
234 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
235 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
236 /* coprocessor registers */ \
237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
239 /* coprocessor control registers */ \
240 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
241 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
242 /* virtual arg pointer */ \
243 1, FIXED_SHADOW_REGISTERS \
244 }
245
246/* This is a call-clobbered reg not used for args or return value,
247 that we use as a temp for saving control registers in the prolog
248 and restoring them in the epilog. */
249#define REGSAVE_CONTROL_TEMP 11
250
251/* A "1" here means a register may be changed by a function without
252 needing to preserve its previous value. */
253#define CALL_USED_REGISTERS { \
254 /* core registers */ \
255 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, \
256 /* control registers */ \
257 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
258 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
259 /* coprocessor registers */ \
260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
261 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
262 /* coprocessor control registers */ \
263 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
264 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
265 /* virtual arg pointer */ \
266 1, CALL_USED_SHADOW_REGISTERS \
267 }
268
7acf4da6
DD		 269#define REG_ALLOC_ORDER { \
270 /* core registers */ \
271 3, 2, 1, 0, 9, 10, 11, 12, 4, 5, 6, 7, 8, 13, 14, 15, \
272 /* control registers */ \
273 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
274 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
275 /* coprocessor registers */ \
276 /* Prefer to use the non-loadable registers when looking for a \
277 member of CR_REGS (as opposed to LOADABLE_CR_REGS). */ \
278 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 48, 49, 50, 51, 52, 58, \
279 59, 60, 61, 62, 63, 53, 54, 55, 56, 57, 74, 75, 76, 77, 78, 79, \
280 /* coprocessor control registers */ \
281 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
282 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, \
283 /* virtual arg pointer */ \
284 112, SHADOW_REG_ALLOC_ORDER \
285 }
286
287/* We must somehow disable register remapping for interrupt functions. */
288extern char mep_leaf_registers[];
289#define LEAF_REGISTERS mep_leaf_registers
290#define LEAF_REG_REMAP(REG) (REG)
291
292\f
293#define FIRST_GR_REGNO 0
294#define FIRST_CONTROL_REGNO (FIRST_GR_REGNO + 16)
295#define FIRST_CR_REGNO (FIRST_CONTROL_REGNO + 32)
296#define FIRST_CCR_REGNO (FIRST_CR_REGNO + 32)
297
298#define GR_REGNO_P(REGNO) \
299 ((unsigned) ((REGNO) - FIRST_GR_REGNO) < 16)
300
301#define CONTROL_REGNO_P(REGNO) \
302 ((unsigned) ((REGNO) - FIRST_CONTROL_REGNO) < 32)
303
304#define LOADABLE_CR_REGNO_P(REGNO) \
305 ((unsigned) ((REGNO) - FIRST_CR_REGNO) < 16)
306
307#define CR_REGNO_P(REGNO) \
308 ((unsigned) ((REGNO) - FIRST_CR_REGNO) < 32)
309
310#define CCR_REGNO_P(REGNO) \
311 ((unsigned) ((REGNO) - FIRST_CCR_REGNO) < 32)
312
313#define ANY_CONTROL_REGNO_P(REGNO) \
314 (CONTROL_REGNO_P (REGNO) || CCR_REGNO_P (REGNO))
315
316#define HARD_REGNO_NREGS(REGNO, MODE) \
317 ((CR_REGNO_P (REGNO) && TARGET_64BIT_CR_REGS) \
318 ? (GET_MODE_SIZE (MODE) + 8 - 1) / 8 \
319 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4)
320
321#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
322
323#define MODES_TIEABLE_P(MODE1, MODE2) 1
324
325#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
326 mep_cannot_change_mode_class (FROM, TO, CLASS)
327\f
328enum reg_class
329{
330 NO_REGS,
331 SP_REGS,
332 TP_REGS,
333 GP_REGS,
334 R0_REGS,
335 RPC_REGS,
336 HI_REGS,
337 LO_REGS,
338 HILO_REGS,
339 TPREL_REGS,
340 GENERAL_NOT_R0_REGS,
341 GENERAL_REGS,
342 CONTROL_REGS,
343 CONTROL_OR_GENERAL_REGS,
344 USER0_REGS,
345 USER1_REGS,
346 USER2_REGS,
347 USER3_REGS,
348 LOADABLE_CR_REGS,
349 CR_REGS,
350 CCR_REGS,
351 ALL_REGS,
352 LIM_REG_CLASSES
353};
354
355#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
356
357#define REG_CLASS_NAMES { \
358 "NO_REGS", \
359 "SP_REGS", \
360 "TP_REGS", \
361 "GP_REGS", \
362 "R0_REGS", \
363 "RPC_REGS", \
364 "HI_REGS", \
365 "LO_REGS", \
366 "HILO_REGS", \
367 "TPREL_REGS", \
368 "GENERAL_NOT_R0_REGS", \
369 "GENERAL_REGS", \
370 "CONTROL_REGS", \
371 "CONTROL_OR_GENERAL_REGS", \
372 "USER0_REGS", \
373 "USER1_REGS", \
374 "USER2_REGS", \
375 "USER3_REGS", \
376 "LOADABLE_CR_REGS", \
377 "CR_REGS", \
378 "CCR_REGS", \
379 "ALL_REGS" }
380
381#define REG_CLASS_CONTENTS { \
382 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
383 { 0x00008000, 0x00000000, 0x00000000, 0x00000000 }, /* SP_REGS */ \
384 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* TP_REGS */ \
385 { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* GP_REGS */ \
386 { 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* R0_REGS */ \
387 { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* RPC_REGS */ \
388 { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
389 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
390 { 0x01800000, 0x00000000, 0x00000000, 0x00000000 }, /* HILO_REGS */ \
391 { 0x000000ff, 0x00000000, 0x00000000, 0x00000000 }, /* TPREL_REGS */ \
392 { 0x0000fffe, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_NOT_R0_REGS */ \
393 { 0x0000ffff, 0x00000000, 0x00000000, 0x00010000 }, /* GENERAL_REGS */ \
394 { 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_REGS */ \
395 { 0xffffffff, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_OR_GENERAL_REGS */ \
396 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER0_REGS */ \
397 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER1_REGS */ \
398 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER2_REGS */ \
399 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER3_REGS */ \
400 { 0x00000000, 0xffff0000, 0x00000000, 0x00000000 }, /* LOADABLE_CR_REGS */ \
401 { 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* CR_REGS */ \
402 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* CCR_REGS */ \
403 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0001ffff }, /* ALL_REGS */ \
404 }
405
77b0efff 406#define REGNO_REG_CLASS(REGNO) (enum reg_class) mep_regno_reg_class (REGNO)
7acf4da6 407
7acf4da6
DD		 408#define BASE_REG_CLASS GENERAL_REGS
409#define INDEX_REG_CLASS GENERAL_REGS
410
411#if 0
412#define REG_CLASS_FROM_CONSTRAINT(CHAR, STRING) \
413 mep_reg_class_from_constraint (CHAR, STRING)
414#endif
415
416#define REGNO_OK_FOR_BASE_P(NUM) (GR_REGNO_P (NUM) \
417 || (NUM) == ARG_POINTER_REGNUM \
418 || (NUM) >= FIRST_PSEUDO_REGISTER)
419
420#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
421
422#define PREFERRED_RELOAD_CLASS(X, CLASS) mep_preferred_reload_class (X, CLASS)
423
424#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
425 mep_secondary_input_reload_class (CLASS, MODE, X)
426#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
427 mep_secondary_output_reload_class (CLASS, MODE, X)
428#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
429 mep_secondary_memory_needed (CLASS1, CLASS2, MODE)
430
431#define CLASS_MAX_NREGS(CLASS, MODE) \
432 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
433
434#if 0
435#define CONST_OK_FOR_LETTER_P(VALUE, C) mep_const_ok_for_letter_p (VALUE, C)
436
437#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
438
439#define CONSTRAINT_LEN(C, STR) \
440 ((C) == 'e' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
441#define EXTRA_CONSTRAINT(VALUE, C) mep_extra_constraint (VALUE, C)
442#endif
443
444#define WANT_GCC_DECLARATIONS
445#include "mep-intrin.h"
446#undef WANT_GCC_DECLARATIONS
447
448extern int mep_intrinsic_insn[];
449extern unsigned int mep_selected_isa;
450
451/* True if intrinsic X is available. X is a mep_* value declared
452 in mep-intrin.h. */
453#define MEP_INTRINSIC_AVAILABLE_P(X) (mep_intrinsic_insn[X] >= 0)
454
455/* Used to define CGEN_ENABLE_INTRINSIC_P in mep-intrin.h. */
456#define CGEN_CURRENT_ISAS mep_selected_isa
457#define CGEN_CURRENT_GROUP \
458 (mep_vliw_function_p (cfun->decl) ? GROUP_VLIW : GROUP_NORMAL)
459
460\f
461
462#define STACK_GROWS_DOWNWARD 1
463#define FRAME_GROWS_DOWNWARD 1
464#define STARTING_FRAME_OFFSET 0
465#define FIRST_PARM_OFFSET(FUNDECL) 0
466#define INCOMING_FRAME_SP_OFFSET 0
467
468#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) mep_return_addr_rtx (COUNT)
469#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LP_REGNO)
470#define DWARF_FRAME_RETURN_COLUMN LP_REGNO
471
472#define STACK_POINTER_REGNUM 15
473#define FRAME_POINTER_REGNUM 8
474#define ARG_POINTER_REGNUM 112
475#define RETURN_ADDRESS_POINTER_REGNUM 17
476#define STATIC_CHAIN_REGNUM 0
477
478\f
479
7acf4da6
DD		 480#define ELIMINABLE_REGS \
481{ \
482 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
483 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
484 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
485}
486
7acf4da6
DD		 487#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
488 (OFFSET) = mep_elimination_offset (FROM, TO)
489
490#define ACCUMULATE_OUTGOING_ARGS 1
491
7acf4da6
DD		 492\f
493
7acf4da6
DD		 494#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) 1
495
496typedef struct
497{
498 int nregs;
499 int vliw;
500} CUMULATIVE_ARGS;
501
502#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
503 mep_init_cumulative_args (& (CUM), FNTYPE, LIBNAME, FNDECL)
504
b9263ae5
DD		 505#define FUNCTION_ARG_REGNO_P(REGNO) \
506 (((REGNO) >= 1 && (REGNO) <= 4) \
453503d6
DD		 507 || ((REGNO) >= FIRST_CR_REGNO + 1 \
508 && (REGNO) <= FIRST_CR_REGNO + 4 \
509 && TARGET_COP))
7acf4da6
DD		 510
511#define RETURN_VALUE_REGNUM 0
512
513#define FUNCTION_VALUE(VALTYPE, FUNC) mep_function_value (VALTYPE, FUNC)
514#define LIBCALL_VALUE(MODE) mep_libcall_value (MODE)
515
516#define FUNCTION_VALUE_REGNO_P(REGNO) \
517 ((REGNO) == RETURN_VALUE_REGNUM)
518
519#define DEFAULT_PCC_STRUCT_RETURN 0
520
521#define STRUCT_VALUE 0
522
523#define FUNCTION_OK_FOR_SIBCALL(DECL) mep_function_ok_for_sibcall(DECL)
524\f
525/* Prologue and epilogues are all handled via RTL. */
526
527#define EXIT_IGNORE_STACK 1
528
529#define EPILOGUE_USES(REGNO) mep_epilogue_uses (REGNO)
530
531/* Profiling is supported. */
532
533#define FUNCTION_PROFILER(FILE, LABELNO) mep_function_profiler (FILE);
534#undef TARGET_HAS_F_SETLKW
535#define NO_PROFILE_COUNTERS 1
536\f
537/* Trampolines are built at run-time. The cache is invalidated at
538 run-time also. */
539
540#define TRAMPOLINE_SIZE 20
7acf4da6
DD		 541\f
542
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DD		 543#define MAX_REGS_PER_ADDRESS 1
544
545#ifdef REG_OK_STRICT
546#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
547 if (mep_legitimate_address ((MODE), (X), 1)) goto LABEL
548#else
549#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
550 if (mep_legitimate_address ((MODE), (X), 0)) goto LABEL
551#endif
552
553#ifdef REG_OK_STRICT
554#define REG_OK_FOR_BASE_P(X) GR_REGNO_P (REGNO (X))
555#else
556#define REG_OK_FOR_BASE_P(X) (GR_REGNO_P (REGNO (X)) \
557 || REGNO (X) == ARG_POINTER_REGNUM \
558 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
559#endif
560
561#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
562
563#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
564 if (mep_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE), (IND_LEVELS))) \
565 goto WIN
566
567#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
568
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DD		 569#define SELECT_CC_MODE(OP, X, Y) CCmode
570\f
571
572/* Moves between control regs need a scratch. */
573#define REGISTER_MOVE_COST(MODE, FROM, TO) mep_register_move_cost (MODE, FROM, TO)
574
575#define SLOW_BYTE_ACCESS 1
576
577/* Define this macro if it is as good or better to call a constant function
578 address than to call an address kept in a register. */
579#define NO_FUNCTION_CSE
580
581\f
582#define TEXT_SECTION_ASM_OP "\t.text\n\t.core"
583#define DATA_SECTION_ASM_OP "\t.data"
584#define BSS_SECTION_ASM_OP ".bss"
585
820ca276
DD		 586#define USE_SELECT_SECTION_FOR_FUNCTIONS 1
587
d839f1eb
DD		 588#define JUMP_TABLES_IN_TEXT_SECTION 1
589
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DD		 590#define TARGET_ASM_FILE_END mep_file_cleanups
591
592#define ASM_APP_ON "#APP\n"
593#define ASM_APP_OFF "#NO_APP\n"
594
595#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
596 do \
597 { \
598 long l[2]; \
599 \
600 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
601 fprintf (FILE, "\t.long\t0x%lx,0x%lx\n", l[0], l[1]); \
602 } \
603 while (0)
604
605#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
606 do \
607 { \
608 long l; \
609 \
610 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
611 fprintf ((FILE), "\t.long\t0x%lx\n", l); \
612 } \
613 while (0)
614
615#define ASM_OUTPUT_CHAR(FILE, VALUE) \
616 do \
617 { \
618 fprintf (FILE, "\t.byte\t"); \
619 output_addr_const (FILE, (VALUE)); \
620 fprintf (FILE, "\n"); \
621 } \
622 while (0)
623
624#define ASM_OUTPUT_SHORT(FILE, VALUE) \
625 do \
626 { \
627 fprintf (FILE, "\t.hword\t"); \
628 output_addr_const (FILE, (VALUE)); \
629 fprintf (FILE, "\n"); \
630 } \
631 while (0)
632
633#define ASM_OUTPUT_INT(FILE, VALUE) \
634 do \
635 { \
636 fprintf (FILE, "\t.word\t"); \
637 output_addr_const (FILE, (VALUE)); \
638 fprintf (FILE, "\n"); \
639 } \
640 while (0)
641
642#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
643 fprintf (STREAM, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
644
645/* Most of these are here to support based/tiny/far/io attributes. */
646
647#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
648 mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
649
650#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
651 mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
652
653#define ASM_OUTPUT_LABEL(STREAM, NAME) \
654 do \
655 { \
656 assemble_name (STREAM, NAME); \
657 fputs (":\n", STREAM); \
658 } \
659 while (0)
660
661/* Globalizing directive for a label. */
662#define GLOBAL_ASM_OP "\t.globl "
663
664#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
665 asm_fprintf ((STREAM), "%U%s", mep_strip_name_encoding (NAME))
666
667#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
668 do \
669 { \
670 (OUTVAR) = (char *) alloca (strlen ((NAME)) + 12); \
671 sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER)); \
672 } \
673 while (0)
674\f
675
676#define REGISTER_NAMES \
677{ \
678 /* Core registers. */ \
679 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
680 "$8", "$9", "$10", "$11", "$12", "$tp", "$gp", "$sp", \
681 /* Control registers. */ \
682 "$pc", "$lp", "$sar", "3", "$rpb", "$rpe", "$rpc", "$hi", \
683 "$lo", "9", "10", "11", "$mb0", "$me0", "$mb1", "$me1", \
684 "$psw", "$id", "$tmp", "$epc", "$exc", "$cfg", "22", "$npc", \
685 "$dbg", "$depc", "$opt", "$rcfg", "$ccfg", "29", "30", "31", \
686 /* Coprocessor registers. */ \
687 "$c0", "$c1", "$c2", "$c3", "$c4", "$c5", "$c6", "$c7", \
688 "$c8", "$c9", "$c10", "$c11", "$c12", "$c13", "$c14", "$c15", \
689 "$c16", "$c17", "$c18", "$c19", "$c20", "$c21", "$c22", "$c23", \
690 "$c24", "$c25", "$c26", "$c27", "$c28", "$c29", "$c30", "$c31", \
691 /* Coprocessor control registers. */ \
692 "$ccr0", "$ccr1", "$ccr2", "$ccr3", "$ccr4", "$ccr5", "$ccr6", \
693 "$ccr7", "$ccr8", "$ccr9", "$ccr10", "$ccr11", "$ccr12", "$ccr13", \
694 "$ccr14", "$ccr15", "$ccr16", "$ccr17", "$ccr18", "$ccr19", "$ccr20", \
695 "$ccr21", "$ccr22", "$ccr23", "$ccr24", "$ccr25", "$ccr26", "$ccr27", \
696 "$ccr28", "$ccr29", "$ccr30", "$ccr31", \
697 /* Virtual arg pointer. */ \
698 "$argp", SHADOW_REGISTER_NAMES \
699}
700
701/* We duplicate some of the above because we twiddle the above
702 according to *how* the registers are used. Likewise, we include
703 the standard names for coprocessor control registers so that
704 coprocessor options can rename them in the default table. Note
705 that these are compared to stripped names (see REGISTER_PREFIX
706 below). */
707#define ADDITIONAL_REGISTER_NAMES \
708{ \
709 { "8", 8 }, { "fp", 8 }, \
710 { "13", 13 }, { "tp", 13 }, \
711 { "14", 14 }, { "gp", 14 }, \
712 { "15", 15 }, { "sp", 15 }, \
713 { "ccr0", FIRST_CCR_REGNO + 0 }, \
714 { "ccr1", FIRST_CCR_REGNO + 1 }, \
715 { "ccr2", FIRST_CCR_REGNO + 2 }, \
716 { "ccr3", FIRST_CCR_REGNO + 3 }, \
717 { "ccr4", FIRST_CCR_REGNO + 4 }, \
718 { "ccr5", FIRST_CCR_REGNO + 5 }, \
719 { "ccr6", FIRST_CCR_REGNO + 6 }, \
720 { "ccr7", FIRST_CCR_REGNO + 7 }, \
721 { "ccr8", FIRST_CCR_REGNO + 8 }, \
722 { "ccr9", FIRST_CCR_REGNO + 9 }, \
723 { "ccr10", FIRST_CCR_REGNO + 10 }, \
724 { "ccr11", FIRST_CCR_REGNO + 11 }, \
725 { "ccr12", FIRST_CCR_REGNO + 12 }, \
726 { "ccr13", FIRST_CCR_REGNO + 13 }, \
727 { "ccr14", FIRST_CCR_REGNO + 14 }, \
728 { "ccr15", FIRST_CCR_REGNO + 15 }, \
729 { "ccr16", FIRST_CCR_REGNO + 16 }, \
730 { "ccr17", FIRST_CCR_REGNO + 17 }, \
731 { "ccr18", FIRST_CCR_REGNO + 18 }, \
732 { "ccr19", FIRST_CCR_REGNO + 19 }, \
733 { "ccr20", FIRST_CCR_REGNO + 20 }, \
734 { "ccr21", FIRST_CCR_REGNO + 21 }, \
735 { "ccr22", FIRST_CCR_REGNO + 22 }, \
736 { "ccr23", FIRST_CCR_REGNO + 23 }, \
737 { "ccr24", FIRST_CCR_REGNO + 24 }, \
738 { "ccr25", FIRST_CCR_REGNO + 25 }, \
739 { "ccr26", FIRST_CCR_REGNO + 26 }, \
740 { "ccr27", FIRST_CCR_REGNO + 27 }, \
741 { "ccr28", FIRST_CCR_REGNO + 28 }, \
742 { "ccr29", FIRST_CCR_REGNO + 29 }, \
743 { "ccr30", FIRST_CCR_REGNO + 30 }, \
744 { "ccr31", FIRST_CCR_REGNO + 31 } \
745}
746
747/* We watch for pipeline hazards with these */
748#define ASM_OUTPUT_OPCODE(STREAM, PTR) mep_asm_output_opcode (STREAM, PTR)
749#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) mep_final_prescan_insn (INSN, OPVEC, NOPERANDS)
750
751#define PRINT_OPERAND(STREAM, X, CODE) mep_print_operand (STREAM, X, CODE)
752
753#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '!' || (CODE) == '<')
754
755#define PRINT_OPERAND_ADDRESS(STREAM, X) mep_print_operand_address (STREAM, X)
756
757#define REGISTER_PREFIX "$"
758#define LOCAL_LABEL_PREFIX "."
759#define USER_LABEL_PREFIX ""
760#define IMMEDIATE_PREFIX ""
761
762\f
763
764#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
765 fprintf (STREAM, "\t.word .L%d\n", VALUE)
766
767\f
768
769#undef PREFERRED_DEBUGGING_TYPE
770#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
771#define DWARF2_DEBUGGING_INFO 1
772#define DWARF2_UNWIND_INFO 1
773
774#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 10 : INVALID_REGNUM)
775
776#define EH_RETURN_STACKADJ_RTX mep_return_stackadj_rtx ()
777#define EH_RETURN_HANDLER_RTX mep_return_handler_rtx ()
778
779#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
780
781\f
782
783#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
784 fprintf ((STREAM), "\t.p2align %d\n", (POWER))
785
786\f
787
788#define CASE_VECTOR_MODE SImode
789
790#define WORD_REGISTER_OPERATIONS
791#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
792
793#define SHORT_IMMEDIATES_SIGN_EXTEND
794
795#define MOVE_MAX 4
796
797#define SHIFT_COUNT_TRUNCATED 1
798
799#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
800
801#define STORE_FLAG_VALUE 1
802
803#define Pmode SImode
804
805#define FUNCTION_MODE SImode
806
807#define REGISTER_TARGET_PRAGMAS() mep_register_pragmas ()
808
7acf4da6
DD		 809/* If defined, a C expression to determine the base term of address X.
810 This macro is used in only one place: `find_base_term' in alias.c.
811
812 It is always safe for this macro to not be defined. It exists so
813 that alias analysis can understand machine-dependent addresses.
814
815 The typical use of this macro is to handle addresses containing
816 a label_ref or symbol_ref within an UNSPEC. */
817#define FIND_BASE_TERM(X) mep_find_base_term (X)
Mirror of https://gcc.gnu.org/git/gcc.git