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80920132 1/* Definitions of target machine for GNU compiler for Xilinx MicroBlaze.
23a5b65a 2 Copyright (C) 2009-2014 Free Software Foundation, Inc.
80920132
ME		 3
4 Contributed by Michael Eager <eager@eagercon.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22/* Standard GCC variables that we reference. */
23
24/* MicroBlaze external variables defined in microblaze.c. */
25
26/* Which pipeline to schedule for. */
27enum pipeline_type
28{
29 MICROBLAZE_PIPE_3 = 0,
30 MICROBLAZE_PIPE_5 = 1
31};
32
33#define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
34
35/* print_operand punctuation chars */
36extern char microblaze_print_operand_punct[];
37
38/* # bytes of data/sdata cutoff */
39extern int microblaze_section_threshold;
40
41/* Map register # to debug register # */
42extern int microblaze_dbx_regno[];
43
44extern int microblaze_no_unsafe_delay;
c77f83d5 45extern int microblaze_has_clz;
80920132
ME		 46extern enum pipeline_type microblaze_pipe;
47
48#define OBJECT_FORMAT_ELF
49
76ef61fb
EI		 50#if TARGET_BIG_ENDIAN_DEFAULT
51#define TARGET_ENDIAN_DEFAULT 0
52#define TARGET_ENDIAN_OPTION "mbig-endian"
53#else
54#define TARGET_ENDIAN_DEFAULT MASK_LITTLE_ENDIAN
55#define TARGET_ENDIAN_OPTION "mlittle-endian"
56#endif
57
80920132 58/* Default target_flags if no switches are specified */
76ef61fb
EI		 59#define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT \
60 | TARGET_ENDIAN_DEFAULT)
80920132 61
c77f83d5
EI		 62/* Do we have CLZ? */
63#define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
64
debd11d9
EI		 65/* The default is to support PIC. */
66#define TARGET_SUPPORTS_PIC 1
67
8cc9a5a5
EI		 68/* The default is to not need GOT for TLS. */
69#define TLS_NEEDS_GOT 0
70
80920132
ME		 71/* What is the default setting for -mcpu= . We set it to v4.00.a even though
72 we are actually ahead. This is safest version that has generate code
73 compatible for the original ISA */
74#define MICROBLAZE_DEFAULT_CPU "v4.00.a"
75
76/* Macros to decide whether certain features are available or not,
77 depending on the instruction set architecture level. */
78
80920132
ME		 79#define DRIVER_SELF_SPECS \
80 "%{mxl-soft-mul:%<mno-xl-soft-mul}", \
81 "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \
82 "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \
83 "%{mxl-soft-div:%<mno-xl-soft-div}", \
cb8a1637 84 "%{mxl-reorder:%<mno-xl-reorder}", \
80920132
ME		 85 "%{msoft-float:%<mhard-float}"
86
87/* Tell collect what flags to pass to nm. */
88#ifndef NM_FLAGS
89#define NM_FLAGS "-Bn"
90#endif
91
92/* Names to predefine in the preprocessor for this target machine. */
93#define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile)
94
95/* Assembler specs. */
96
78a14252 97#define TARGET_ASM_SPEC ""
80920132
ME		 98
99#define ASM_SPEC "\
76ef61fb
EI		 100%(target_asm_spec) \
101%{mbig-endian:-EB} \
102%{mlittle-endian:-EL}"
80920132
ME		 103
104/* Extra switches sometimes passed to the linker. */
105/* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */
106
107#define LINK_SPEC "%{shared:-shared} -N -relax \
76ef61fb
EI		 108 %{mbig-endian:-EB --oformat=elf32-microblaze} \
109 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
80920132
ME		 110 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
111 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
112 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
c6c34cb4 113 %{!T*: -dT xilinx.ld%s}"
80920132
ME		 114
115/* Specs for the compiler proper */
116
117#ifndef CC1_SPEC
118#define CC1_SPEC " \
34830bfd 119%{G*} \
80920132
ME		 120%(subtarget_cc1_spec) \
121%{mxl-multiply-high:-mcpu=v6.00.a} \
122"
123#endif
124
125#define EXTRA_SPECS \
126 { "target_asm_spec", TARGET_ASM_SPEC }, \
127 SUBTARGET_EXTRA_SPECS
128
80920132
ME		 129/* Local compiler-generated symbols must have a prefix that the assembler
130 understands. */
131
132#ifndef LOCAL_LABEL_PREFIX
133#define LOCAL_LABEL_PREFIX "$"
134#endif
135
136/* fixed registers. */
137#define MB_ABI_BASE_REGNUM 0
138#define MB_ABI_STACK_POINTER_REGNUM 1
139#define MB_ABI_GPRO_REGNUM 2
140#define MB_ABI_GPRW_REGNUM 13
141#define MB_ABI_INTR_RETURN_ADDR_REGNUM 14
142#define MB_ABI_SUB_RETURN_ADDR_REGNUM 15
143#define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16
144#define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17
145#define MB_ABI_ASM_TEMP_REGNUM 18
146/* This is our temp register. */
147#define MB_ABI_FRAME_POINTER_REGNUM 19
148#define MB_ABI_PIC_ADDR_REGNUM 20
149#define MB_ABI_PIC_FUNC_REGNUM 21
150/* Volatile registers. */
151#define MB_ABI_INT_RETURN_VAL_REGNUM 3
152#define MB_ABI_INT_RETURN_VAL2_REGNUM 4
153#define MB_ABI_FIRST_ARG_REGNUM 5
154#define MB_ABI_LAST_ARG_REGNUM 10
155#define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \
156 - MB_ABI_FIRST_ARG_REGNUM + 1)
157#define MB_ABI_STATIC_CHAIN_REGNUM 3
158#define MB_ABI_TEMP1_REGNUM 11
159#define MB_ABI_TEMP2_REGNUM 12
160#define MB_ABI_MSR_SAVE_REG 11
161/* Volatile register used to save MSR in interrupt handlers. */
162
163
164/* Debug stuff. */
165
166/* How to renumber registers for dbx and gdb. */
167#define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)]
168
169/* Generate DWARF exception handling info. */
170#define DWARF2_UNWIND_INFO 1
171
172/* Don't generate .loc operations. */
173#define DWARF2_ASM_LINE_DEBUG_INFO 0
174
175/* The DWARF 2 CFA column which tracks the return address. */
176#define DWARF_FRAME_RETURN_COLUMN \
177 (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
178
179/* Initial state of return address on entry to func = R15.
180 Actually, the RA is at R15+8, but gcc doesn't know how
181 to generate this.
182 NOTE: GDB has a workaround and expects this incorrect value.
183 If this is fixed, a corresponding fix to GDB is needed. */
184#define INCOMING_RETURN_ADDR_RTX \
185 gen_rtx_REG (VOIDmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
186
187/* Use DWARF 2 debugging information by default. */
188#define DWARF2_DEBUGGING_INFO
189#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
190
191/* Target machine storage layout */
192
193#define BITS_BIG_ENDIAN 0
76ef61fb
EI		 194#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
195#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
80920132
ME		 196#define BITS_PER_WORD 32
197#define UNITS_PER_WORD 4
198#define MIN_UNITS_PER_WORD 4
199#define INT_TYPE_SIZE 32
200#define SHORT_TYPE_SIZE 16
201#define LONG_TYPE_SIZE 32
202#define LONG_LONG_TYPE_SIZE 64
203#define FLOAT_TYPE_SIZE 32
204#define DOUBLE_TYPE_SIZE 64
205#define LONG_DOUBLE_TYPE_SIZE 64
206#define POINTER_SIZE 32
207#define PARM_BOUNDARY 32
208#define FUNCTION_BOUNDARY 32
209#define EMPTY_FIELD_BOUNDARY 32
210#define STRUCTURE_SIZE_BOUNDARY 8
211#define BIGGEST_ALIGNMENT 32
212#define STRICT_ALIGNMENT 1
213#define PCC_BITFIELD_TYPE_MATTERS 1
214
215#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
216 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
217 && (ALIGN) < BITS_PER_WORD \
218 ? BITS_PER_WORD \
219 : (ALIGN))
220
221#define DATA_ALIGNMENT(TYPE, ALIGN) \
222 ((((ALIGN) < BITS_PER_WORD) \
223 && (TREE_CODE (TYPE) == ARRAY_TYPE \
224 || TREE_CODE (TYPE) == UNION_TYPE \
225 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
226
227#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
228 (((TREE_CODE (TYPE) == ARRAY_TYPE \
229 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
230 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
231
232#define WORD_REGISTER_OPERATIONS
233
234#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
235
236#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
237 if (GET_MODE_CLASS (MODE) == MODE_INT \
238 && GET_MODE_SIZE (MODE) < 4) \
239 (MODE) = SImode;
240
241/* Standard register usage. */
242
243/* On the MicroBlaze, we have 32 integer registers */
244
245#define FIRST_PSEUDO_REGISTER 36
246
247#define FIXED_REGISTERS \
248{ \
249 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
250 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
251 1, 1, 1, 1 \
252}
253
254#define CALL_USED_REGISTERS \
255{ \
256 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
257 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
258 1, 1, 1, 1 \
259}
260
261#define GP_REG_FIRST 0
262#define GP_REG_LAST 31
263#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
264#define GP_DBX_FIRST 0
265
266#define ST_REG 32
267#define AP_REG_NUM 33
268#define RAP_REG_NUM 34
269#define FRP_REG_NUM 35
270
271#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
272#define ST_REG_P(REGNO) ((REGNO) == ST_REG)
273
274#define HARD_REGNO_NREGS(REGNO, MODE) \
275 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
276
277/* Value is 1 if hard register REGNO can hold a value of machine-mode
278 MODE. In 32 bit mode, require that DImode and DFmode be in even
279 registers. For DImode, this makes some of the insns easier to
280 write, since you don't have to worry about a DImode value in
281 registers 3 & 4, producing a result in 4 & 5.
282
283 To make the code simpler HARD_REGNO_MODE_OK now just references an
284 array built in override_options. Because machmodes.h is not yet
285 included before this file is processed, the MODE bound can't be
286 expressed here. */
287extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
288#define HARD_REGNO_MODE_OK(REGNO, MODE) \
289 microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)]
290
291#define MODES_TIEABLE_P(MODE1, MODE2) \
292 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
293 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
294 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
295 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
296
297#define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM)
298
299#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL)
300
301/* Base register for access to local variables of the function. We
302 pretend that the frame pointer is
303 MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it
304 to HARD_FRAME_POINTER_REGNUM. We can get away with this because
305 rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed
306 register(return address for interrupt), and will not be used for
307 anything else. */
308
309#define FRAME_POINTER_REGNUM FRP_REG_NUM
310#define HARD_FRAME_POINTER_REGNUM \
311 (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM)
312#define ARG_POINTER_REGNUM AP_REG_NUM
313#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
314#define STATIC_CHAIN_REGNUM \
315 (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM)
316
317/* registers used in prologue/epilogue code when the stack frame
318 is larger than 32K bytes. These registers must come from the
319 scratch register set, and not used for passing and returning
320 arguments and any other information used in the calling sequence
321 (such as pic). */
322
323#define MICROBLAZE_TEMP1_REGNUM \
324 (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM)
325
326#define MICROBLAZE_TEMP2_REGNUM \
327 (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM)
328
329#define NO_FUNCTION_CSE 1
330
8cc9a5a5 331#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM)
80920132
ME		 332
333enum reg_class
334{
335 NO_REGS, /* no registers in set. */
336 GR_REGS, /* integer registers. */
337 ST_REGS, /* status register. */
338 ALL_REGS, /* all registers. */
339 LIM_REG_CLASSES /* max value + 1. */
340};
341
342#define N_REG_CLASSES (int) LIM_REG_CLASSES
343
344#define GENERAL_REGS GR_REGS
345
346#define REG_CLASS_NAMES \
347{ \
348 "NO_REGS", \
349 "GR_REGS", \
350 "ST_REGS", \
351 "ALL_REGS" \
352}
353
354#define REG_CLASS_CONTENTS \
355{ \
356 { 0x00000000, 0x00000000 }, /* no registers. */ \
357 { 0xffffffff, 0x00000000 }, /* integer registers. */ \
358 { 0x00000000, 0x00000001 }, /* status registers. */ \
359 { 0xffffffff, 0x0000000f } /* all registers. */ \
360}
361
362extern enum reg_class microblaze_regno_to_class[];
363
364#define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ]
365
366#define BASE_REG_CLASS GR_REGS
367
368#define INDEX_REG_CLASS GR_REGS
369
370#define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS)
371
372/* REGISTER AND CONSTANT CLASSES */
373
374#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
556618c1
JR		 375#define LARGE_INT(X) \
376 (INTVAL (X) > 0 && UINTVAL (X) >= 0x80000000 && UINTVAL (X) <= 0xffffffff)
80920132
ME		 377#define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT)
378/* Test for a valid operand for a call instruction.
379 Don't allow the arg pointer register or virtual regs
380 since they may change into reg + const, which the patterns
381 can't handle yet. */
382#define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
383 || (GET_CODE (X) == REG && X != arg_pointer_rtx\
384 && ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
385 && REGNO (X) <= LAST_VIRTUAL_REGISTER)))
386
387/* True if VALUE is a signed 16-bit number. */
388#define SMALL_OPERAND(VALUE) \
389 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
390
391/* Constant which cannot be loaded in one instruction. */
392#define LARGE_OPERAND(VALUE) \
393 ((((VALUE) & ~0x0000ffff) != 0) \
394 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
395 && (((VALUE) & 0x0000ffff) != 0 \
396 || (((VALUE) & ~2147483647) != 0 \
397 && ((VALUE) & ~2147483647) != ~2147483647)))
398
399#define PREFERRED_RELOAD_CLASS(X,CLASS) \
400 ((CLASS) != ALL_REGS \
401 ? (CLASS) \
402 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
403 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
404 ? (GR_REGS) \
405 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
406 || GET_MODE (X) == VOIDmode) \
407 ? (GR_REGS) : (CLASS))))
408
409#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
410 (GET_MODE_CLASS (MODE) == MODE_INT)
411
80920132
ME		 412/* Stack layout; function entry, exit and calling. */
413
414#define STACK_GROWS_DOWNWARD
415
416/* Changed the starting frame offset to including the new link stuff */
417#define STARTING_FRAME_OFFSET \
418 (crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL))
419
420/* The return address for the current frame is in r31 if this is a leaf
421 function. Otherwise, it is on the stack. It is at a variable offset
422 from sp/fp/ap, so we define a fake hard register rap which is a
423 poiner to the return address on the stack. This always gets eliminated
424 during reload to be either the frame pointer or the stack pointer plus
425 an offset. */
426
427#define RETURN_ADDR_RTX(count, frame) \
428 microblaze_return_addr(count,frame)
429
430extern struct microblaze_frame_info current_frame_info;
431
432#define ELIMINABLE_REGS \
433{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
434 { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
435 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
436 { RETURN_ADDRESS_POINTER_REGNUM, \
437 GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
438 { RETURN_ADDRESS_POINTER_REGNUM, \
439 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \
440 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
441 { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}}
442
443#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
444 (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO))
445
446#define ACCUMULATE_OUTGOING_ARGS 1
447
448#define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
449
450#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
451
452#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
453
454#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
455
456#define STACK_BOUNDARY 32
457
458#define NUM_OF_ARGS 6
459
460#define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
461
462#define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM)
463#define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM)
464
465#define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
466
467#define LIBCALL_VALUE(MODE) \
468 gen_rtx_REG ( \
469 ((GET_MODE_CLASS (MODE) != MODE_INT \
470 || GET_MODE_SIZE (MODE) >= 4) \
471 ? (MODE) \
472 : SImode), GP_RETURN)
473
474/* 1 if N is a possible register number for a function value.
475 On the MicroBlaze, R2 R3 are the only register thus used.
476 Currently, R2 are only implemented here (C has no complex type) */
477
478#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
479
480#define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
481
482typedef struct microblaze_args
483{
484 int gp_reg_found; /* whether a gp register was found yet */
485 int arg_number; /* argument number */
486 int arg_words; /* # total words the arguments take */
487 int fp_arg_words; /* # words for FP args */
488 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
489 int fp_code; /* Mode of FP arguments */
490 int num_adjusts; /* number of adjustments made */
491 /* Adjustments made to args pass in regs. */
492 /* ??? The size is doubled to work around a bug in the code that sets the
493 adjustments in function_arg. */
984514ac 494 rtx adjust[MAX_ARGS_IN_REGISTERS * 2];
80920132
ME		 495} CUMULATIVE_ARGS;
496
497#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
498 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
499
80920132
ME		 500#define NO_PROFILE_COUNTERS 1
501
502#define FUNCTION_PROFILER(FILE, LABELNO) { \
503 { \
504 fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
505 } \
506 }
507
508#define EXIT_IGNORE_STACK 1
509
8ec77be0
EI		 510/* 4 insns + 2 words of data. */
511#define TRAMPOLINE_SIZE (6 * 4)
80920132
ME		 512
513#define TRAMPOLINE_ALIGNMENT 32
514
515#define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
516
517#define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
518
519#ifndef REG_OK_STRICT
520#define REG_STRICT_FLAG 0
521#else
522#define REG_STRICT_FLAG 1
523#endif
524
525#define REG_OK_FOR_BASE_P(X) \
526 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
527
528#define REG_OK_FOR_INDEX_P(X) \
529 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
530
531#define MAX_REGS_PER_ADDRESS 2
532
533
534/* Identify valid constant addresses. Exclude if PIC addr which
535 needs scratch register. */
536#define CONSTANT_ADDRESS_P(X) \
537 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
538 || GET_CODE (X) == CONST_INT \
539 || (GET_CODE (X) == CONST \
540 && ! (flag_pic && pic_address_needs_scratch (X))))
541
542/* Define this, so that when PIC, reload won't try to reload invalid
543 addresses which require two reload registers. */
91c4e421 544#define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X)
80920132 545
80920132
ME		 546#define CASE_VECTOR_MODE (SImode)
547
548#ifndef DEFAULT_SIGNED_CHAR
549#define DEFAULT_SIGNED_CHAR 1
550#endif
551
552#define MOVE_MAX 4
553#define MAX_MOVE_MAX 8
554
555#define SLOW_BYTE_ACCESS 1
556
557/* sCOND operations return 1. */
558#define STORE_FLAG_VALUE 1
559
560#define SHIFT_COUNT_TRUNCATED 1
561
562/* This results in inefficient code for 64 bit to 32 conversions.
563 Something needs to be done about this. Perhaps not use any 32 bit
564 instructions? Perhaps use PROMOTE_MODE? */
565#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
566
567#define Pmode SImode
568
569#define FUNCTION_MODE SImode
570
073a8998 571/* Mode should always be SImode */
80920132
ME		 572#define REGISTER_MOVE_COST(MODE, FROM, TO) \
573 ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
574 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
575 : 12)
576
577#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
578 (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
579
580#define BRANCH_COST(speed_p, predictable_p) 2
581
582/* Control the assembler format that we output. */
583#define ASM_APP_ON " #APP\n"
584#define ASM_APP_OFF " #NO_APP\n"
585
586#define REGISTER_NAMES { \
587 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
588 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
589 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
590 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
591 "rmsr", "$ap", "$rap", "$frp" }
592
593#define ADDITIONAL_REGISTER_NAMES \
594{ \
595 { "r0", 0 + GP_REG_FIRST }, \
596 { "r1", 1 + GP_REG_FIRST }, \
597 { "r2", 2 + GP_REG_FIRST }, \
598 { "r3", 3 + GP_REG_FIRST }, \
599 { "r4", 4 + GP_REG_FIRST }, \
600 { "r5", 5 + GP_REG_FIRST }, \
601 { "r6", 6 + GP_REG_FIRST }, \
602 { "r7", 7 + GP_REG_FIRST }, \
603 { "r8", 8 + GP_REG_FIRST }, \
604 { "r9", 9 + GP_REG_FIRST }, \
605 { "r10", 10 + GP_REG_FIRST }, \
606 { "r11", 11 + GP_REG_FIRST }, \
607 { "r12", 12 + GP_REG_FIRST }, \
608 { "r13", 13 + GP_REG_FIRST }, \
609 { "r14", 14 + GP_REG_FIRST }, \
610 { "r15", 15 + GP_REG_FIRST }, \
611 { "r16", 16 + GP_REG_FIRST }, \
612 { "r17", 17 + GP_REG_FIRST }, \
613 { "r18", 18 + GP_REG_FIRST }, \
614 { "r19", 19 + GP_REG_FIRST }, \
615 { "r20", 20 + GP_REG_FIRST }, \
616 { "r21", 21 + GP_REG_FIRST }, \
617 { "r22", 22 + GP_REG_FIRST }, \
618 { "r23", 23 + GP_REG_FIRST }, \
619 { "r24", 24 + GP_REG_FIRST }, \
620 { "r25", 25 + GP_REG_FIRST }, \
621 { "r26", 26 + GP_REG_FIRST }, \
622 { "r27", 27 + GP_REG_FIRST }, \
623 { "r28", 28 + GP_REG_FIRST }, \
624 { "r29", 29 + GP_REG_FIRST }, \
625 { "r30", 30 + GP_REG_FIRST }, \
626 { "r31", 31 + GP_REG_FIRST }, \
627 { "rmsr", ST_REG} \
628}
629
630#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
631
632#define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE]
633
634#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
635
636/* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL
637
638 Unfortunately, we still need to set the section explicitly. Somehow,
639 our binutils assign .comm and .lcomm variables to the "current" section
640 in the assembly file, rather than where they implicitly belong. We need to
641 remove this explicit setting in GCC when binutils can understand sections
642 better. */
643#undef ASM_OUTPUT_ALIGNED_COMMON
644#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
645do { \
556618c1
JR		 646 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
647 && (int) (SIZE) <= microblaze_section_threshold \
648 && TARGET_XLGPOPT) \
80920132
ME		 649 { \
650 switch_to_section (sbss_section); \
651 } \
652 else \
653 { \
654 switch_to_section (bss_section); \
655 } \
656 fprintf (FILE, "%s", COMMON_ASM_OP); \
657 assemble_name ((FILE), (NAME)); \
658 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
659 (SIZE), (ALIGN) / BITS_PER_UNIT); \
660 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
661} while (0)
662
663#undef ASM_OUTPUT_ALIGNED_LOCAL
664#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
665do { \
556618c1
JR		 666 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
667 && (int) (SIZE) <= microblaze_section_threshold \
668 && TARGET_XLGPOPT) \
80920132
ME		 669 { \
670 switch_to_section (sbss_section); \
671 } \
672 else \
673 { \
674 switch_to_section (bss_section); \
675 } \
676 fprintf (FILE, "%s", LCOMMON_ASM_OP); \
677 assemble_name ((FILE), (NAME)); \
678 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
679 (SIZE), (ALIGN) / BITS_PER_UNIT); \
680 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
681} while (0)
682
683#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
684do { \
685 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
686} while (0)
687
688#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
689{ \
690}
691
692#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
693 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
694
695#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
696 fprintf (STREAM, "\t%s\t%sL%d\n", \
697 ".gpword", \
698 LOCAL_LABEL_PREFIX, VALUE)
699
700#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
701do { \
702 if (flag_pic == 2) \
703 fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \
704 ".gpword", \
705 LOCAL_LABEL_PREFIX, VALUE); \
706 else \
707 fprintf (STREAM, "\t%s\t%sL%d\n", \
708 ".gpword", \
709 LOCAL_LABEL_PREFIX, VALUE); \
710} while (0)
711
712#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
713 fprintf (STREAM, "\t.align\t%d\n", (LOG))
714
715#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
716 fprintf (STREAM, "\t.space\t%lu\n", (SIZE))
717
718#define ASCII_DATA_ASM_OP "\t.ascii\t"
719#define STRING_ASM_OP "\t.asciz\t"
720
a8781821
SB		 721#undef TARGET_ASM_OUTPUT_IDENT
722#define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
80920132
ME		 723
724/* Default to -G 8 */
725#ifndef MICROBLAZE_DEFAULT_GVALUE
726#define MICROBLAZE_DEFAULT_GVALUE 8
727#endif
728
729/* Given a decl node or constant node, choose the section to output it in
730 and select that section. */
731
732/* Store in OUTPUT a string (made with alloca) containing
733 an assembler-name for a local static variable named NAME.
734 LABELNO is an integer which is different for each call. */
735#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
736( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
556618c1 737 sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long)(LABELNO)))
80920132
ME		 738
739/* How to start an assembler comment.
740 The leading space is important (the microblaze assembler requires it). */
741#ifndef ASM_COMMENT_START
742#define ASM_COMMENT_START " #"
743#endif
744
745#define BSS_VAR 1
746#define SBSS_VAR 2
747#define DATA_VAR 4
748#define SDATA_VAR 5
749#define RODATA_VAR 6
750#define SDATA2_VAR 7
751
752/* These definitions are used in with the shift_type flag in the rtl. */
753#define SHIFT_CONST 1
754#define SHIFT_REG 2
755#define USE_ADDK 3
756
757/* Handle interrupt attribute. */
758extern int interrupt_handler;
ee61ea38 759extern int fast_interrupt;
80920132
ME		 760extern int save_volatiles;
761
762#define INTERRUPT_HANDLER_NAME "_interrupt_handler"
ee61ea38 763#define FAST_INTERRUPT_NAME "_fast_interrupt"
80920132 764
80920132
ME		 765/* The following #defines are used in the headers files. Always retain these. */
766
767/* Added for declaring size at the end of the function. */
768#undef ASM_DECLARE_FUNCTION_SIZE
769#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
770 do { \
771 if (!flag_inhibit_size_directive) \
772 { \
773 char label[256]; \
774 static int labelno; \
775 labelno++; \
776 ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
777 (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \
778 fprintf (FILE, "%s", SIZE_ASM_OP); \
779 assemble_name (FILE, (FNAME)); \
780 fprintf (FILE, ","); \
781 assemble_name (FILE, label); \
782 fprintf (FILE, "-"); \
783 assemble_name (FILE, (FNAME)); \
784 putc ('\n', FILE); \
785 } \
786 } while (0)
787
788#define GLOBAL_ASM_OP "\t.globl\t"
789#define TYPE_ASM_OP "\t.type\t"
790#define SIZE_ASM_OP "\t.size\t"
791#define COMMON_ASM_OP "\t.comm\t"
792#define LCOMMON_ASM_OP "\t.lcomm\t"
793
794#define MAX_OFILE_ALIGNMENT (32768*8)
795
796#define TYPE_OPERAND_FMT "@%s"
797
798/* Write the extra assembler code needed to declare an object properly. */
799#undef ASM_DECLARE_OBJECT_NAME
800#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \
801 do { \
802 fprintf (FILE, "%s", TYPE_ASM_OP); \
803 assemble_name (FILE, NAME); \
804 putc (',', FILE); \
805 fprintf (FILE, TYPE_OPERAND_FMT, "object"); \
806 putc ('\n', FILE); \
807 size_directive_output = 0; \
808 if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
809 { \
810 size_directive_output = 1; \
811 fprintf (FILE, "%s", SIZE_ASM_OP); \
812 assemble_name (FILE, NAME); \
556618c1
JR		 813 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
814 int_size_in_bytes (TREE_TYPE (DECL))); \
80920132
ME		 815 } \
816 microblaze_declare_object (FILE, NAME, "", ":\n", 0); \
817 } while (0)
818
819#undef ASM_FINISH_DECLARE_OBJECT
820#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
821do { \
556618c1 822 const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
80920132
ME		 823 if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
824 && ! AT_END && TOP_LEVEL \
825 && DECL_INITIAL (DECL) == error_mark_node \
826 && !size_directive_output) \
827 { \
828 size_directive_output = 1; \
829 fprintf (FILE, "%s", SIZE_ASM_OP); \
830 assemble_name (FILE, name); \
556618c1
JR		 831 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
832 int_size_in_bytes (TREE_TYPE (DECL))); \
80920132
ME		 833 } \
834 } while (0)
835
836#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
837 do { fputc ( '\t', FILE); \
838 assemble_name (FILE, LABEL1); \
839 fputs ( " = ", FILE); \
840 assemble_name (FILE, LABEL2); \
841 fputc ( '\n', FILE); \
842 } while (0)
843
844#define ASM_WEAKEN_LABEL(FILE,NAME) \
845 do { fputs ("\t.weakext\t", FILE); \
846 assemble_name (FILE, NAME); \
847 fputc ('\n', FILE); \
848 } while (0)
849
850#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
851#undef UNIQUE_SECTION_P
852#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
853
854#undef TARGET_ASM_NAMED_SECTION
855#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
856
857/* Define the strings to put out for each section in the object file.
858
859 Note: For ctors/dtors, we want to give these sections the SHF_WRITE
860 attribute to allow shared libraries to patch/resolve addresses into
861 these locations. On Microblaze, there is no concept of shared libraries
862 yet, so this is for future use. */
863#define TEXT_SECTION_ASM_OP "\t.text"
864#define DATA_SECTION_ASM_OP "\t.data"
865#define READONLY_DATA_SECTION_ASM_OP \
866 "\t.rodata"
867#define BSS_SECTION_ASM_OP "\t.bss"
868#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
869#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
870#define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\""
871#define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\""
872
873#define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */
874#define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */
875#define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */
876#define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */
877
80920132
ME		 878/* We do this to save a few 10s of code space that would be taken up
879 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
880 definition in crtstuff.c. */
881#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
882 asm ( SECTION_OP "\n" \
883 "\tbrlid r15, " #FUNC "\n\t nop\n" \
884 TEXT_SECTION_ASM_OP);
885
886/* We need to group -lm as well, since some Newlib math functions
887 reference __errno! */
888#undef LIB_SPEC
889#define LIB_SPEC \
890"%{!nostdlib: \
891%{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \
892%{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} "
893
d33d9e47
AI		 894/* microblaze-unknown-elf target has no support of C99 runtime */
895#undef TARGET_LIBC_HAS_FUNCTION
896#define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
897
80920132
ME		 898#undef ENDFILE_SPEC
899#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
900
901#define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
902#define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
903#define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s"
904#define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s"
905#define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \
906%{mno-clearbss: sim-crtinit.o%s}} \
907%{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}"
908
909#define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC
910
911#undef SUBTARGET_EXTRA_SPECS
912#define SUBTARGET_EXTRA_SPECS \
913 { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \
914 { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \
915 { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \
916 { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \
917 { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \
918 { "startfile_default", STARTFILE_DEFAULT_SPEC },
919
920#undef STARTFILE_SPEC
921#define STARTFILE_SPEC "\
922%{Zxl-mode-executable : %(startfile_executable) ; \
923 mxl-mode-executable : %(startfile_executable) ; \
924 Zxl-mode-xmdstub : %(startfile_xmdstub) ; \
925 mxl-mode-xmdstub : %(startfile_xmdstub) ; \
926 Zxl-mode-bootstrap : %(startfile_bootstrap) ; \
927 mxl-mode-bootstrap : %(startfile_bootstrap) ; \
928 Zxl-mode-novectors : %(startfile_novectors) ; \
929 mxl-mode-novectors : %(startfile_novectors) ; \
930 Zxl-mode-xilkernel : %(startfile_xilkernel) ; \
931 mxl-mode-xilkernel : %(startfile_xilkernel) ; \
932 : %(startfile_default) \
933} \
934%(startfile_crtinit)"
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