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880986c1 | 1 | ;; DFA-based pipeline descriptions for MIPS Technologies 24K core. |
99917bc3 | 2 | ;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com) |
880986c1 DU |
3 | ;; and David Ung (davidu@mips.com) |
4 | ;; | |
bdd77024 RS |
5 | ;; The 24kf2_1 is a single-issue processor with a half-clocked fpu. |
6 | ;; The 24kf1_1 is 24k with 1:1 clocked fpu. | |
880986c1 DU |
7 | ;; |
8 | ;; References: | |
9 | ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04." | |
10 | ;; | |
99dee823 | 11 | ;; Copyright (C) 2005-2021 Free Software Foundation, Inc. |
880986c1 DU |
12 | ;; |
13 | ;; This file is part of GCC. | |
14 | ;; | |
15 | ;; GCC is free software; you can redistribute it and/or modify it | |
16 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 17 | ;; by the Free Software Foundation; either version 3, or (at your |
880986c1 DU |
18 | ;; option) any later version. |
19 | ||
20 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
21 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
22 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
23 | ;; License for more details. | |
24 | ||
25 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
26 | ;; along with GCC; see the file COPYING3. If not see |
27 | ;; <http://www.gnu.org/licenses/>. | |
880986c1 DU |
28 | |
29 | (define_automaton "r24k_cpu, r24k_mdu, r24k_fpu") | |
30 | ||
31 | ;; Integer execution unit. | |
32 | (define_cpu_unit "r24k_iss" "r24k_cpu") | |
33 | (define_cpu_unit "r24k_ixu_arith" "r24k_cpu") | |
34 | (define_cpu_unit "r24k_mul3a" "r24k_mdu") | |
35 | (define_cpu_unit "r24k_mul3b" "r24k_mdu") | |
36 | (define_cpu_unit "r24k_mul3c" "r24k_mdu") | |
37 | ||
38 | ;; -------------------------------------------------------------- | |
39 | ;; Producers | |
40 | ;; -------------------------------------------------------------- | |
41 | ||
42 | ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs | |
99917bc3 | 43 | (define_insn_reservation "r24k_int_load" 2 |
bdd77024 | 44 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
880986c1 DU |
45 | (eq_attr "type" "load")) |
46 | "r24k_iss+r24k_ixu_arith") | |
47 | ||
48 | ||
49 | ;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz, | |
99917bc3 RS |
50 | ;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll, |
51 | ;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh, | |
880986c1 | 52 | ;; xor, xori |
99917bc3 | 53 | ;; (movn/movz is not matched, we'll need to split condmov to |
880986c1 | 54 | ;; differentiate between integer/float moves) |
99917bc3 | 55 | (define_insn_reservation "r24k_int_arith" 1 |
bdd77024 | 56 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
b1a14b78 | 57 | (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt")) |
880986c1 DU |
58 | "r24k_iss+r24k_ixu_arith") |
59 | ||
60 | ||
61 | ;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx | |
62 | ;; 3a. jr/jalr consumer | |
99917bc3 | 63 | (define_insn_reservation "r24k_int_jump" 1 |
bdd77024 | 64 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
880986c1 DU |
65 | (eq_attr "type" "call,jump")) |
66 | "r24k_iss+r24k_ixu_arith") | |
67 | ||
68 | ;; 3b. branch consumer | |
99917bc3 | 69 | (define_insn_reservation "r24k_int_branch" 1 |
bdd77024 | 70 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
880986c1 DU |
71 | (eq_attr "type" "branch")) |
72 | "r24k_iss+r24k_ixu_arith") | |
73 | ||
74 | ||
75 | ;; 4. MDU: fully pipelined multiplier | |
76 | ;; mult - delivers result to hi/lo in 1 cycle (pipelined) | |
99917bc3 | 77 | (define_insn_reservation "r24k_int_mult" 1 |
bdd77024 | 78 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
99917bc3 | 79 | (eq_attr "type" "imul")) |
880986c1 DU |
80 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") |
81 | ||
82 | ;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined) | |
99917bc3 | 83 | (define_insn_reservation "r24k_int_madd" 1 |
bdd77024 | 84 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
99917bc3 | 85 | (eq_attr "type" "imadd")) |
880986c1 DU |
86 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") |
87 | ||
99917bc3 RS |
88 | ;; mul - delivers result to gpr in 5 cycles |
89 | (define_insn_reservation "r24k_int_mul3" 5 | |
bdd77024 | 90 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
99917bc3 | 91 | (eq_attr "type" "imul3")) |
95177e17 | 92 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5") |
880986c1 DU |
93 | |
94 | ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles | |
99917bc3 | 95 | (define_insn_reservation "r24k_int_mfhilo" 5 |
bdd77024 | 96 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
cb00489c | 97 | (eq_attr "type" "mfhi,mflo")) |
880986c1 DU |
98 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") |
99 | ||
100 | ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass | |
99917bc3 | 101 | (define_insn_reservation "r24k_int_mthilo" 1 |
bdd77024 | 102 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
cb00489c | 103 | (eq_attr "type" "mthi,mtlo")) |
880986c1 DU |
104 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") |
105 | ||
99917bc3 | 106 | ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and |
880986c1 | 107 | ;; 8bit, but is tricky to identify. |
99917bc3 | 108 | (define_insn_reservation "r24k_int_div" 36 |
bdd77024 | 109 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
99917bc3 | 110 | (eq_attr "type" "idiv")) |
880986c1 DU |
111 | "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36") |
112 | ||
113 | ||
114 | ;; 5. Cop: cfc1, di, ei, mfc0, mtc0 | |
115 | ;; (Disabled until we add proper cop0 support) | |
99917bc3 | 116 | ;;(define_insn_reservation "r24k_int_cop" 3 |
bdd77024 | 117 | ;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
880986c1 DU |
118 | ;; (eq_attr "type" "cop0")) |
119 | ;; "r24k_iss+r24k_ixu_arith") | |
120 | ||
121 | ||
122 | ;; 6. Store | |
99917bc3 | 123 | (define_insn_reservation "r24k_int_store" 1 |
bdd77024 | 124 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
d28cfc4a | 125 | (eq_attr "type" "store")) |
880986c1 DU |
126 | "r24k_iss+r24k_ixu_arith") |
127 | ||
128 | ||
129 | ;; 7. Multiple instructions | |
99917bc3 | 130 | (define_insn_reservation "r24k_int_multi" 1 |
bdd77024 | 131 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
99917bc3 | 132 | (eq_attr "type" "multi")) |
880986c1 DU |
133 | "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)") |
134 | ||
135 | ||
99917bc3 RS |
136 | ;; 8. Unknowns - Currently these include blockage, consttable and alignment |
137 | ;; rtls. They do not really affect scheduling latency, (blockage affects | |
880986c1 | 138 | ;; scheduling via log links, but not used here). |
99917bc3 | 139 | (define_insn_reservation "r24k_int_unknown" 0 |
bdd77024 | 140 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
3088716e | 141 | (eq_attr "type" "unknown,atomic,syncloop")) |
880986c1 DU |
142 | "r24k_iss") |
143 | ||
144 | ||
145 | ;; 9. Prefetch | |
99917bc3 | 146 | (define_insn_reservation "r24k_int_prefetch" 1 |
bdd77024 | 147 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") |
99917bc3 | 148 | (eq_attr "type" "prefetch,prefetchx")) |
880986c1 DU |
149 | "r24k_iss+r24k_ixu_arith") |
150 | ||
151 | ||
152 | ;; -------------------------------------------------------------- | |
153 | ;; Bypass to Consumer | |
154 | ;; -------------------------------------------------------------- | |
155 | ||
156 | ;; load->next use : 2 cycles (Default) | |
157 | ;; load->load base: 3 cycles | |
158 | ;; load->store base: 3 cycles | |
159 | ;; load->prefetch: 3 cycles | |
160 | (define_bypass 3 "r24k_int_load" "r24k_int_load") | |
d28cfc4a | 161 | (define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p") |
880986c1 DU |
162 | (define_bypass 3 "r24k_int_load" "r24k_int_prefetch") |
163 | ||
164 | ;; arith->next use : 1 cycles (Default) | |
165 | ;; arith->load base: 2 cycles | |
166 | ;; arith->store base: 2 cycles | |
167 | ;; arith->prefetch: 2 cycles | |
168 | (define_bypass 2 "r24k_int_arith" "r24k_int_load") | |
d28cfc4a | 169 | (define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p") |
880986c1 DU |
170 | (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch") |
171 | ||
172 | ;; mul3->next use : 5 cycles (default) | |
173 | ;; mul3->l/s base : 6 cycles | |
174 | ;; mul3->prefetch : 6 cycles | |
95177e17 | 175 | (define_bypass 6 "r24k_int_mul3" "r24k_int_load") |
d28cfc4a | 176 | (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p") |
95177e17 | 177 | (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch") |
880986c1 | 178 | |
d56b9f12 SL |
179 | ;; mul3->madd/msub : 1 cycle |
180 | (define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p") | |
181 | ||
880986c1 | 182 | ;; mfhilo->next use : 5 cycles (default) |
99917bc3 RS |
183 | ;; mfhilo->l/s base : 6 cycles |
184 | ;; mfhilo->prefetch : 6 cycles | |
880986c1 DU |
185 | ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo) |
186 | (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load") | |
d28cfc4a SL |
187 | (define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" |
188 | "!mips_store_data_bypass_p") | |
880986c1 DU |
189 | (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch") |
190 | (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd") | |
191 | ||
192 | ;; cop->next use : 3 cycles (Default) | |
193 | ;; cop->l/s base : 4 cycles | |
194 | ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load") | |
d28cfc4a SL |
195 | ;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" |
196 | ;; "!mips_store_data_bypass_p") | |
880986c1 DU |
197 | |
198 | ;; multi->next use : 1 cycles (Default) | |
199 | ;; multi->l/s base : 2 cycles | |
200 | ;; multi->prefetch : 2 cycles | |
201 | (define_bypass 2 "r24k_int_multi" "r24k_int_load") | |
d28cfc4a | 202 | (define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p") |
880986c1 DU |
203 | (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch") |
204 | ||
205 | ||
ef2e5300 SL |
206 | ;; -------------------------------------------------------------- |
207 | ;; DSP instructions | |
208 | ;; -------------------------------------------------------------- | |
209 | ||
210 | ;; absq, addq, addsc, addu, addwc, bitrev, cmp, cmpgu, cmpu, insv, modsub, | |
211 | ;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl, | |
212 | ;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp | |
213 | (define_insn_reservation "r24k_dsp_alu" 2 | |
214 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") | |
215 | (eq_attr "type" "dspalu,dspalusat")) | |
216 | "r24k_iss+r24k_ixu_arith") | |
217 | ||
218 | ;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq | |
219 | (define_insn_reservation "r24k_dsp_mac" 1 | |
220 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") | |
221 | (eq_attr "type" "dspmac")) | |
222 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") | |
223 | ||
224 | ;; dpaq_sa, dpsq_sa, maq_sa | |
225 | (define_insn_reservation "r24k_dsp_mac_sat" 1 | |
226 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") | |
227 | (eq_attr "type" "dspmacsat")) | |
228 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") | |
229 | ||
230 | ;; extp, extpdp, extpdpv, extpv, extr, extrv | |
231 | (define_insn_reservation "r24k_dsp_acc_ext" 5 | |
232 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") | |
233 | (eq_attr "type" "accext")) | |
234 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") | |
235 | ||
236 | ;; mthlip, shilo, shilov | |
237 | (define_insn_reservation "r24k_dsp_acc_mod" 1 | |
238 | (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") | |
239 | (eq_attr "type" "accmod")) | |
240 | "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") | |
241 | ||
242 | ||
243 | ;; mult/madd->dsp_acc_ext : 4 cycles | |
244 | ;; mult/madd->dsp_acc_mod : 4 cycles | |
245 | (define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_ext") | |
246 | (define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_mod") | |
247 | ||
248 | ;; mthilo->dsp_acc_ext : 4 cycles | |
249 | ;; mthilo->dsp_acc_ext : 4 cycles | |
250 | (define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_ext") | |
251 | (define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_mod") | |
252 | ||
253 | ;; dsp_mac->next use : 1 cycles (default) | |
254 | ;; dsp_mac->dsp_acc_ext : 4 cycles | |
255 | ;; dsp_mac->dsp_acc_mod : 4 cycles | |
256 | (define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_ext") | |
257 | (define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_mod") | |
258 | ||
259 | ;; dsp_mac_sat->next use : 1 cycles (default) | |
260 | ;; dsp_mac_sat->mult/madd : 2 cycles | |
261 | ;; dsp_mac_sat->dsp_mac : 2 cycles | |
262 | ;; dsp_mac_sat->dsp_mac_sat : 2 cycles | |
263 | ;; dsp_mac_sat->dsp_acc_ext : 4 cycles | |
264 | ;; dsp_mac_sat->dsp_acc_mod : 4 cycles | |
265 | (define_bypass 2 "r24k_dsp_mac_sat" "r24k_int_mult") | |
266 | (define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac") | |
267 | (define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac_sat") | |
268 | (define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_ext") | |
269 | (define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_mod") | |
270 | ||
271 | ;; dsp_acc_ext->next use : 5 cycles (default) | |
272 | ;; dsp_acc_ext->l/s base : 6 cycles | |
273 | ;; dsp_acc_ext->prefetch : 6 cycles | |
274 | (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_load") | |
275 | (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_store" | |
276 | "!mips_store_data_bypass_p") | |
277 | (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_prefetch") | |
278 | ||
279 | ;; dsp_acc_mod->next use : 1 cycles (default) | |
280 | ;; dsp_acc_mod->mult/madd : 2 cycles | |
281 | ;; dsp_acc_mod->dsp_mac : 2 cycles | |
282 | ;; dsp_acc_mod->dsp_mac_sat : 2 cycles | |
283 | ;; dsp_acc_mod->dsp_acc_ext : 4 cycles | |
284 | ;; dsp_acc_mod->dsp_acc_mod : 4 cycles | |
285 | (define_bypass 2 "r24k_dsp_acc_mod" "r24k_int_mult") | |
286 | (define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac") | |
287 | (define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac_sat") | |
288 | (define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_ext") | |
289 | (define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_mod") | |
290 | ||
291 | ;; dspalu->next use : 2 cycles (default) | |
292 | ;; dspalu->l/s base : 3 cycles | |
293 | ;; dspalu->prefetch : 3 cycles | |
294 | ;; some pairs of dspalu (addsc/addwc, cmp/pick, wrdsp/insv) : 1 cycle | |
295 | (define_bypass 3 "r24k_dsp_alu" "r24k_int_load") | |
296 | (define_bypass 3 "r24k_dsp_alu" "r24k_int_store" "!mips_store_data_bypass_p") | |
297 | (define_bypass 3 "r24k_dsp_alu" "r24k_int_prefetch") | |
298 | (define_bypass 1 "r24k_dsp_alu" "r24k_dsp_alu" "mips_dspalu_bypass_p") | |
299 | ||
300 | ||
880986c1 DU |
301 | ;; -------------------------------------------------------------- |
302 | ;; Floating Point Instructions | |
303 | ;; -------------------------------------------------------------- | |
304 | ||
305 | (define_cpu_unit "r24k_fpu_arith" "r24k_fpu") | |
306 | ||
307 | ;; The 24k is a single issue cpu, and the fpu runs at half clock speed, | |
308 | ;; so each fpu instruction ties up the shared instruction scheduler for | |
309 | ;; 1 cycle, and the fpu scheduler for 2 cycles. | |
99917bc3 | 310 | ;; |
880986c1 DU |
311 | ;; These timings are therefore twice the values in the 24K manual, |
312 | ;; which are quoted in fpu clocks. | |
313 | ;; | |
bdd77024 | 314 | ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use |
880986c1 DU |
315 | ;; the unscaled timings |
316 | ||
bdd77024 | 317 | (define_reservation "r24kf2_1_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)") |
880986c1 DU |
318 | |
319 | ;; fadd, fabs, fneg | |
bdd77024 RS |
320 | (define_insn_reservation "r24kf2_1_fadd" 8 |
321 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 | 322 | (eq_attr "type" "fadd,fabs,fneg")) |
bdd77024 | 323 | "r24kf2_1_fpu_iss") |
880986c1 DU |
324 | |
325 | ;; fmove, fcmove | |
bdd77024 RS |
326 | (define_insn_reservation "r24kf2_1_fmove" 8 |
327 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 | 328 | (eq_attr "type" "fmove,condmove")) |
bdd77024 | 329 | "r24kf2_1_fpu_iss") |
880986c1 DU |
330 | |
331 | ;; fload | |
bdd77024 RS |
332 | (define_insn_reservation "r24kf2_1_fload" 6 |
333 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 | 334 | (eq_attr "type" "fpload,fpidxload")) |
bdd77024 | 335 | "r24kf2_1_fpu_iss") |
880986c1 DU |
336 | |
337 | ;; fstore | |
bdd77024 RS |
338 | (define_insn_reservation "r24kf2_1_fstore" 2 |
339 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 | 340 | (eq_attr "type" "fpstore")) |
bdd77024 | 341 | "r24kf2_1_fpu_iss") |
880986c1 DU |
342 | |
343 | ;; fmul, fmadd | |
bdd77024 RS |
344 | (define_insn_reservation "r24kf2_1_fmul_sf" 8 |
345 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
346 | (and (eq_attr "type" "fmul,fmadd") |
347 | (eq_attr "mode" "SF"))) | |
bdd77024 | 348 | "r24kf2_1_fpu_iss") |
880986c1 | 349 | |
bdd77024 RS |
350 | (define_insn_reservation "r24kf2_1_fmul_df" 10 |
351 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
352 | (and (eq_attr "type" "fmul,fmadd") |
353 | (eq_attr "mode" "DF"))) | |
bdd77024 | 354 | "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)") |
880986c1 DU |
355 | |
356 | ||
357 | ;; fdiv, fsqrt, frsqrt | |
bdd77024 RS |
358 | (define_insn_reservation "r24kf2_1_fdiv_sf" 34 |
359 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
360 | (and (eq_attr "type" "fdiv,fsqrt,frsqrt") |
361 | (eq_attr "mode" "SF"))) | |
bdd77024 | 362 | "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)") |
880986c1 | 363 | |
bdd77024 RS |
364 | (define_insn_reservation "r24kf2_1_fdiv_df" 64 |
365 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
366 | (and (eq_attr "type" "fdiv,fsqrt") |
367 | (eq_attr "mode" "DF"))) | |
bdd77024 | 368 | "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)") |
880986c1 DU |
369 | |
370 | ;; frsqrt | |
bdd77024 RS |
371 | (define_insn_reservation "r24kf2_1_frsqrt_df" 70 |
372 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
373 | (and (eq_attr "type" "frsqrt") |
374 | (eq_attr "mode" "DF"))) | |
bdd77024 | 375 | "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)") |
880986c1 DU |
376 | |
377 | ;; fcmp | |
bdd77024 RS |
378 | (define_insn_reservation "r24kf2_1_fcmp" 4 |
379 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 | 380 | (eq_attr "type" "fcmp")) |
bdd77024 | 381 | "r24kf2_1_fpu_iss") |
880986c1 DU |
382 | |
383 | ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition) | |
bdd77024 | 384 | (define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove") |
880986c1 DU |
385 | |
386 | ;; fcvt (cvt.d.s, cvt.[sd].[wl]) | |
bdd77024 RS |
387 | (define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8 |
388 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
389 | (and (eq_attr "type" "fcvt") |
390 | (eq_attr "cnv_mode" "I2S,I2D,S2D"))) | |
bdd77024 | 391 | "r24kf2_1_fpu_iss") |
880986c1 DU |
392 | |
393 | ;; fcvt (cvt.s.d) | |
bdd77024 RS |
394 | (define_insn_reservation "r24kf2_1_fcvt_s2d" 12 |
395 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
396 | (and (eq_attr "type" "fcvt") |
397 | (eq_attr "cnv_mode" "D2S"))) | |
bdd77024 | 398 | "r24kf2_1_fpu_iss") |
880986c1 DU |
399 | |
400 | ;; fcvt (cvt.[wl].[sd], etc) | |
bdd77024 RS |
401 | (define_insn_reservation "r24kf2_1_fcvt_f2i" 10 |
402 | (and (eq_attr "cpu" "24kf2_1") | |
880986c1 DU |
403 | (and (eq_attr "type" "fcvt") |
404 | (eq_attr "cnv_mode" "S2I,D2I"))) | |
bdd77024 | 405 | "r24kf2_1_fpu_iss") |
880986c1 DU |
406 | |
407 | ;; fxfer (mfc1, mfhc1, mtc1, mthc1) | |
bdd77024 RS |
408 | (define_insn_reservation "r24kf2_1_fxfer" 4 |
409 | (and (eq_attr "cpu" "24kf2_1") | |
00f9e1ca | 410 | (eq_attr "type" "mfc,mtc")) |
bdd77024 | 411 | "r24kf2_1_fpu_iss") |
880986c1 DU |
412 | |
413 | ;; -------------------------------------------------------------- | |
414 | ;; Bypass to Consumer | |
415 | ;; -------------------------------------------------------------- | |
bdd77024 RS |
416 | ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles |
417 | ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles | |
418 | (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load") | |
d28cfc4a SL |
419 | (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" |
420 | "!mips_store_data_bypass_p") | |
bdd77024 RS |
421 | (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch") |
422 | ||
423 | ;; r24kf2_1_fxfer->l/s base : 5 cycles | |
424 | ;; r24kf2_1_fxfer->prefetch : 5 cycles | |
425 | (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load") | |
d28cfc4a | 426 | (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p") |
bdd77024 | 427 | (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch") |
880986c1 DU |
428 | |
429 | ;; -------------------------------------------------------------- | |
bdd77024 | 430 | ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use |
880986c1 DU |
431 | ;; the unscaled timings |
432 | ;; -------------------------------------------------------------- | |
433 | ||
bdd77024 | 434 | (define_reservation "r24kf1_1_fpu_iss" "r24k_iss+r24k_fpu_arith") |
880986c1 DU |
435 | |
436 | ;; fadd, fabs, fneg | |
bdd77024 RS |
437 | (define_insn_reservation "r24kf1_1_fadd" 4 |
438 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 | 439 | (eq_attr "type" "fadd,fabs,fneg")) |
bdd77024 | 440 | "r24kf1_1_fpu_iss") |
880986c1 DU |
441 | |
442 | ;; fmove, fcmove | |
bdd77024 RS |
443 | (define_insn_reservation "r24kf1_1_fmove" 4 |
444 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 | 445 | (eq_attr "type" "fmove,condmove")) |
bdd77024 | 446 | "r24kf1_1_fpu_iss") |
880986c1 DU |
447 | |
448 | ;; fload | |
bdd77024 RS |
449 | (define_insn_reservation "r24kf1_1_fload" 3 |
450 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 | 451 | (eq_attr "type" "fpload,fpidxload")) |
bdd77024 | 452 | "r24kf1_1_fpu_iss") |
880986c1 DU |
453 | |
454 | ;; fstore | |
bdd77024 RS |
455 | (define_insn_reservation "r24kf1_1_fstore" 1 |
456 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 | 457 | (eq_attr "type" "fpstore")) |
bdd77024 | 458 | "r24kf1_1_fpu_iss") |
880986c1 DU |
459 | |
460 | ;; fmul, fmadd | |
bdd77024 RS |
461 | (define_insn_reservation "r24kf1_1_fmul_sf" 4 |
462 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
463 | (and (eq_attr "type" "fmul,fmadd") |
464 | (eq_attr "mode" "SF"))) | |
bdd77024 | 465 | "r24kf1_1_fpu_iss") |
880986c1 | 466 | |
bdd77024 RS |
467 | (define_insn_reservation "r24kf1_1_fmul_df" 5 |
468 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
469 | (and (eq_attr "type" "fmul,fmadd") |
470 | (eq_attr "mode" "DF"))) | |
bdd77024 | 471 | "r24kf1_1_fpu_iss,r24k_fpu_arith") |
880986c1 DU |
472 | |
473 | ||
474 | ;; fdiv, fsqrt, frsqrt | |
bdd77024 RS |
475 | (define_insn_reservation "r24kf1_1_fdiv_sf" 17 |
476 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
477 | (and (eq_attr "type" "fdiv,fsqrt,frsqrt") |
478 | (eq_attr "mode" "SF"))) | |
bdd77024 | 479 | "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)") |
880986c1 | 480 | |
bdd77024 RS |
481 | (define_insn_reservation "r24kf1_1_fdiv_df" 32 |
482 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
483 | (and (eq_attr "type" "fdiv,fsqrt") |
484 | (eq_attr "mode" "DF"))) | |
bdd77024 | 485 | "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)") |
880986c1 DU |
486 | |
487 | ;; frsqrt | |
bdd77024 RS |
488 | (define_insn_reservation "r24kf1_1_frsqrt_df" 35 |
489 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
490 | (and (eq_attr "type" "frsqrt") |
491 | (eq_attr "mode" "DF"))) | |
bdd77024 | 492 | "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)") |
880986c1 DU |
493 | |
494 | ;; fcmp | |
bdd77024 RS |
495 | (define_insn_reservation "r24kf1_1_fcmp" 2 |
496 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 | 497 | (eq_attr "type" "fcmp")) |
bdd77024 | 498 | "r24kf1_1_fpu_iss") |
880986c1 DU |
499 | |
500 | ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition) | |
bdd77024 | 501 | (define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove") |
880986c1 DU |
502 | |
503 | ;; fcvt (cvt.d.s, cvt.[sd].[wl]) | |
bdd77024 RS |
504 | (define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4 |
505 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
506 | (and (eq_attr "type" "fcvt") |
507 | (eq_attr "cnv_mode" "I2S,I2D,S2D"))) | |
bdd77024 | 508 | "r24kf1_1_fpu_iss") |
880986c1 DU |
509 | |
510 | ;; fcvt (cvt.s.d) | |
bdd77024 RS |
511 | (define_insn_reservation "r24kf1_1_fcvt_s2d" 6 |
512 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
513 | (and (eq_attr "type" "fcvt") |
514 | (eq_attr "cnv_mode" "D2S"))) | |
bdd77024 | 515 | "r24kf1_1_fpu_iss") |
880986c1 DU |
516 | |
517 | ;; fcvt (cvt.[wl].[sd], etc) | |
bdd77024 RS |
518 | (define_insn_reservation "r24kf1_1_fcvt_f2i" 5 |
519 | (and (eq_attr "cpu" "24kf1_1") | |
880986c1 DU |
520 | (and (eq_attr "type" "fcvt") |
521 | (eq_attr "cnv_mode" "S2I,D2I"))) | |
bdd77024 | 522 | "r24kf1_1_fpu_iss") |
880986c1 DU |
523 | |
524 | ;; fxfer (mfc1, mfhc1, mtc1, mthc1) | |
bdd77024 RS |
525 | (define_insn_reservation "r24kf1_1_fxfer" 2 |
526 | (and (eq_attr "cpu" "24kf1_1") | |
00f9e1ca | 527 | (eq_attr "type" "mfc,mtc")) |
bdd77024 | 528 | "r24kf1_1_fpu_iss") |
880986c1 DU |
529 | |
530 | ;; -------------------------------------------------------------- | |
531 | ;; Bypass to Consumer | |
532 | ;; -------------------------------------------------------------- | |
bdd77024 RS |
533 | ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles |
534 | ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles | |
535 | (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load") | |
d28cfc4a SL |
536 | (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" |
537 | "!mips_store_data_bypass_p") | |
bdd77024 RS |
538 | (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch") |
539 | ||
540 | ;; r24kf1_1_fxfer->l/s base : 3 cycles | |
541 | ;; r24kf1_1_fxfer->prefetch : 3 cycles | |
542 | (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load") | |
d28cfc4a | 543 | (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p") |
bdd77024 | 544 | (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch") |
880986c1 | 545 |