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Commit | Line | Data |
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2ac23d05 EC |
1 | ;; DFA based pipeline description for the r3000 |
2 | ;; This is a special pipeline - this is also the default schedule and | |
3 | ;; so we need to schedule instructions that may not exist on the r2k/r3k. | |
4 | ||
b5674962 | 5 | (define_automaton "r3k_alu,r3k_imuldiv") |
2ac23d05 | 6 | |
b5674962 RS |
7 | (define_cpu_unit "r3k_alu" "r3k_alu") |
8 | (define_cpu_unit "r3k_imuldiv" "r3k_imuldiv") | |
2ac23d05 | 9 | |
b5674962 | 10 | (define_insn_reservation "r3k_generic" 1 |
2ac23d05 | 11 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
12 | (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith, |
13 | shift,slt,clz,trap,multi,nop")) | |
2ac23d05 EC |
14 | "r3k_alu") |
15 | ||
b5674962 | 16 | (define_insn_reservation "r3k_load" 2 |
2ac23d05 | 17 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
18 | (eq_attr "type" "load,fpload,fpidxload,xfer")) |
19 | "r3k_alu") | |
2ac23d05 | 20 | |
b5674962 | 21 | (define_insn_reservation "r3k_store" 1 |
2ac23d05 | 22 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
23 | (eq_attr "type" "store,fpstore,fpidxstore")) |
24 | "r3k_alu") | |
2ac23d05 | 25 | |
b5674962 | 26 | (define_insn_reservation "r3k_branch" 1 |
2ac23d05 | 27 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
28 | (eq_attr "type" "branch,jump,call")) |
29 | "r3k_alu") | |
2ac23d05 | 30 | |
b5674962 | 31 | (define_insn_reservation "r3k_hilo" 1 |
2ac23d05 | 32 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
33 | (eq_attr "type" "mfhilo,mthilo")) |
34 | "r3k_imuldiv*3") | |
2ac23d05 | 35 | |
b5674962 | 36 | (define_insn_reservation "r3k_imul" 12 |
2ac23d05 | 37 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
38 | (eq_attr "type" "imul,imadd")) |
39 | "r3k_imuldiv*12") | |
2ac23d05 | 40 | |
b5674962 | 41 | (define_insn_reservation "r3k_idiv" 35 |
2ac23d05 EC |
42 | (and (eq_attr "cpu" "r3000") |
43 | (eq_attr "type" "idiv")) | |
b5674962 RS |
44 | "r3k_imuldiv*35") |
45 | ||
46 | (define_insn_reservation "r3k_fmove" 1 | |
47 | (and (eq_attr "cpu" "r3000") | |
48 | (eq_attr "type" "fabs,fneg,fmove,fcvt")) | |
49 | "r3k_alu") | |
2ac23d05 | 50 | |
b5674962 | 51 | (define_insn_reservation "r3k_fadd" 2 |
2ac23d05 | 52 | (and (eq_attr "cpu" "r3000") |
b5674962 RS |
53 | (eq_attr "type" "fcmp,fadd")) |
54 | "r3k_alu") | |
55 | ||
56 | (define_insn_reservation "r3k_fmul_single" 4 | |
57 | (and (eq_attr "cpu" "r3000") | |
58 | (and (eq_attr "type" "fmul,fmadd") | |
2ac23d05 | 59 | (eq_attr "mode" "SF"))) |
b5674962 | 60 | "r3k_alu") |
2ac23d05 | 61 | |
b5674962 | 62 | (define_insn_reservation "r3k_fmul_double" 5 |
2ac23d05 | 63 | (and (eq_attr "cpu" "r3000") |
b5674962 | 64 | (and (eq_attr "type" "fmul,fmadd") |
2ac23d05 | 65 | (eq_attr "mode" "DF"))) |
b5674962 | 66 | "r3k_alu") |
2ac23d05 | 67 | |
b5674962 | 68 | (define_insn_reservation "r3k_fdiv_single" 12 |
2ac23d05 | 69 | (and (eq_attr "cpu" "r3000") |
b5674962 | 70 | (and (eq_attr "type" "fdiv,fsqrt,frsqrt") |
2ac23d05 | 71 | (eq_attr "mode" "SF"))) |
b5674962 | 72 | "r3k_alu") |
2ac23d05 | 73 | |
b5674962 | 74 | (define_insn_reservation "r3k_fdiv_double" 19 |
2ac23d05 | 75 | (and (eq_attr "cpu" "r3000") |
b5674962 | 76 | (and (eq_attr "type" "fdiv,fsqrt,frsqrt") |
2ac23d05 | 77 | (eq_attr "mode" "DF"))) |
b5674962 | 78 | "r3k_alu") |