projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ac23d05 EC |
1 | ;; DFA based pipeline description for the r3000 |
| 2 | ;; This is a special pipeline - this is also the default schedule and | |
| 3 | ;; so we need to schedule instructions that may not exist on the r2k/r3k. | |
| 4 | ||
| 5 | ;; Generic processor description that assumes that the only latencies are for | |
| 6 | ;; hazards or delay slots, otherwise everything is assumed to issue and execute | |
| 7 | ;; in one cycle. | |
| 8 | (define_automaton "r3k") | |
| 9 | ||
| 10 | (define_cpu_unit "r3k_alu" "r3k") | |
| 11 | ||
| 12 | (define_insn_reservation "r3k_generic_alu" 1 | |
| 13 | (and (eq_attr "cpu" "r3000") | |
| 14 | (eq_attr "type" "unknown,prefetch,prefetchx,condmove,mthilo,const,arith,shift,slt,clz,trap,fmove,fadd,fmadd,fabs,fneg,fcvt,fsqrt,frsqrt,multi,nop")) | |
| 15 | "r3k_alu") | |
| 16 | ||
| 17 | (define_insn_reservation "r3k_load_alu" 2 | |
| 18 | (and (eq_attr "cpu" "r3000") | |
| 19 | (eq_attr "type" "load, fpload, fpidxload, xfer")) | |
| 20 | "r3k_alu*2") | |
| 21 | ||
| 22 | (define_insn_reservation "r3k_call_alu" 2 | |
| 23 | (and (eq_attr "cpu" "r3000") | |
| 24 | (eq_attr "type" "branch,jump,call")) | |
| 25 | "r3k_alu*2") | |
| 26 | ||
| 27 | (define_insn_reservation "r3k_hilo_alu" 3 | |
| 28 | (and (eq_attr "cpu" "r3000") | |
| 29 | (eq_attr "type" "mfhilo")) | |
| 30 | "r3k_alu*3") | |
| 31 | ||
| 32 | (define_insn_reservation "r3k_fcmp_alu" 2 | |
| 33 | (and (eq_attr "cpu" "r3000") | |
| 34 | (eq_attr "type" "fcmp, fadd")) | |
| 35 | "r3k_alu*2") | |
| 36 | ||
| 37 | (define_insn_reservation "r3k_imul_alu" 12 | |
| 38 | (and (eq_attr "cpu" "r3000") | |
| 39 | (eq_attr "type" "imul, imadd")) | |
| 40 | "r3k_alu*12") | |
| 41 | ||
| 42 | (define_insn_reservation "r3k_idiv_alu" 35 | |
| 43 | (and (eq_attr "cpu" "r3000") | |
| 44 | (eq_attr "type" "idiv")) | |
| 45 | "r3k_alu*35") | |
| 46 | ||
| 47 | (define_insn_reservation "r3k_fmul_single_alu" 4 | |
| 48 | (and (eq_attr "cpu" "r3000") | |
| 49 | (and (eq_attr "type" "fmul") | |
| 50 | (eq_attr "mode" "SF"))) | |
| 51 | "r3k_alu*4") | |
| 52 | ||
| 53 | (define_insn_reservation "r3k_fmul_double_alu" 5 | |
| 54 | (and (eq_attr "cpu" "r3000") | |
| 55 | (and (eq_attr "type" "fmul") | |
| 56 | (eq_attr "mode" "DF"))) | |
| 57 | "r3k_alu*5") | |
| 58 | ||
| 59 | (define_insn_reservation "r3k_fdiv_single_alu" 12 | |
| 60 | (and (eq_attr "cpu" "r3000") | |
| 61 | (and (eq_attr "type" "fdiv") | |
| 62 | (eq_attr "mode" "SF"))) | |
| 63 | "r3k_alu*12") | |
| 64 | ||
| 65 | (define_insn_reservation "r3k_fdiv_double_alu" 19 | |
| 66 | (and (eq_attr "cpu" "r3000") | |
| 67 | (and (eq_attr "type" "fdiv") | |
| 68 | (eq_attr "mode" "DF"))) | |
| 69 | "r3k_alu*19") |