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re PR middle-end/20371 (Some corner cases of MS bitfields don't work)
[thirdparty/gcc.git] / gcc / config / mips / 3000.md
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1;; R3000 and TX39 pipeline description.
2;; Copyright (C) 2004 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
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6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published
8;; by the Free Software Foundation; either version 2, or (at your
9;; option) any later version.
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11;; GCC is distributed in the hope that it will be useful, but WITHOUT
12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14;; License for more details.
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16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING. If not, write to the
18;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19;; MA 02111-1307, USA.
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2ac23d05 21
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22;; This file overrides parts of generic.md. It is derived from the
23;; old define_function_unit description.
2ac23d05 24
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25(define_insn_reservation "r3k_load" 2
26 (and (eq_attr "cpu" "r3000,r3900")
27 (eq_attr "type" "load,fpload,fpidxload"))
28 "alu")
2ac23d05 29
b5674962 30(define_insn_reservation "r3k_imul" 12
f10107a1 31 (and (eq_attr "cpu" "r3000,r3900")
b5674962 32 (eq_attr "type" "imul,imadd"))
f10107a1 33 "imuldiv*12")
2ac23d05 34
b5674962 35(define_insn_reservation "r3k_idiv" 35
f10107a1 36 (and (eq_attr "cpu" "r3000,r3900")
2ac23d05 37 (eq_attr "type" "idiv"))
f10107a1 38 "imuldiv*35")
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39
40(define_insn_reservation "r3k_fmove" 1
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41 (and (eq_attr "cpu" "r3000,r3900")
42 (eq_attr "type" "fabs,fneg,fmove"))
43 "alu")
2ac23d05 44
b5674962 45(define_insn_reservation "r3k_fadd" 2
f10107a1 46 (and (eq_attr "cpu" "r3000,r3900")
b5674962 47 (eq_attr "type" "fcmp,fadd"))
f10107a1 48 "alu")
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49
50(define_insn_reservation "r3k_fmul_single" 4
f10107a1 51 (and (eq_attr "cpu" "r3000,r3900")
b5674962 52 (and (eq_attr "type" "fmul,fmadd")
2ac23d05 53 (eq_attr "mode" "SF")))
f10107a1 54 "alu")
2ac23d05 55
b5674962 56(define_insn_reservation "r3k_fmul_double" 5
f10107a1 57 (and (eq_attr "cpu" "r3000,r3900")
b5674962 58 (and (eq_attr "type" "fmul,fmadd")
2ac23d05 59 (eq_attr "mode" "DF")))
f10107a1 60 "alu")
2ac23d05 61
b5674962 62(define_insn_reservation "r3k_fdiv_single" 12
f10107a1 63 (and (eq_attr "cpu" "r3000,r3900")
9ff6992e 64 (and (eq_attr "type" "fdiv,frdiv")
2ac23d05 65 (eq_attr "mode" "SF")))
f10107a1 66 "alu")
2ac23d05 67
b5674962 68(define_insn_reservation "r3k_fdiv_double" 19
f10107a1 69 (and (eq_attr "cpu" "r3000,r3900")
9ff6992e 70 (and (eq_attr "type" "fdiv,frdiv")
2ac23d05 71 (eq_attr "mode" "DF")))
f10107a1 72 "alu")