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8dd58f01 DU |
1 | ;; DFA-based pipeline description for MIPS32 model 74k. |
2 | ;; Contributed by MIPS Technologies and CodeSourcery. | |
3 | ;; | |
4 | ;; Reference: | |
5 | ;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006" | |
6 | ;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006" | |
7 | ;; | |
8 | ;; Copyright (C) 2007 Free Software Foundation, Inc. | |
9 | ;; | |
10 | ;; This file is part of GCC. | |
11 | ;; | |
12 | ;; GCC is free software; you can redistribute it and/or modify it | |
13 | ;; under the terms of the GNU General Public License as published | |
2f83c7d6 | 14 | ;; by the Free Software Foundation; either version 3, or (at your |
8dd58f01 DU |
15 | ;; option) any later version. |
16 | ||
17 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
18 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
19 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
20 | ;; License for more details. | |
21 | ||
22 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
23 | ;; along with GCC; see the file COPYING3. If not see |
24 | ;; <http://www.gnu.org/licenses/>. | |
8dd58f01 DU |
25 | |
26 | (define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu") | |
27 | (define_cpu_unit "r74k_mul" "r74k_mdu_pipe") | |
28 | (define_cpu_unit "r74k_alu" "r74k_alu_pipe") | |
29 | (define_cpu_unit "r74k_agen" "r74k_agen_pipe") | |
30 | (define_cpu_unit "r74k_fpu_arith" "r74k_fpu") | |
31 | (define_cpu_unit "r74k_fpu_ldst" "r74k_fpu") | |
32 | ||
33 | ;; -------------------------------------------------------------- | |
34 | ;; Producers | |
35 | ;; -------------------------------------------------------------- | |
36 | ||
b1a14b78 DU |
37 | ;; ALU: Logicals/Arithmetics |
38 | ;; - Logicals, move (addu/addiu with rt = 0), Set less than, | |
39 | ;; sign extend - 1 cycle | |
40 | (define_insn_reservation "r74k_int_logical" 1 | |
41 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") | |
42 | (eq_attr "type" "logical,move,signext,slt")) | |
43 | "r74k_alu") | |
44 | ||
45 | ;; - Arithmetics - 2 cycles | |
8dd58f01 | 46 | (define_insn_reservation "r74k_int_arith" 2 |
74d4d024 | 47 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
b1a14b78 | 48 | (eq_attr "type" "arith,const,shift,clz")) |
8dd58f01 DU |
49 | "r74k_alu") |
50 | ||
51 | (define_insn_reservation "r74k_int_nop" 0 | |
74d4d024 | 52 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
53 | (eq_attr "type" "nop")) |
54 | "nothing") | |
55 | ||
56 | (define_insn_reservation "r74k_int_cmove" 4 | |
74d4d024 | 57 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
58 | (eq_attr "type" "condmove")) |
59 | "r74k_agen*2") | |
60 | ||
61 | ;; MDU: fully pipelined multiplier | |
d56b9f12 | 62 | ;; mult - delivers result to hi/lo in 4 cycle (pipelined) |
8dd58f01 | 63 | (define_insn_reservation "r74k_int_mult" 4 |
74d4d024 | 64 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
d56b9f12 SL |
65 | (eq_attr "type" "imul")) |
66 | "r74k_alu+r74k_mul") | |
67 | ||
68 | ;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined) | |
69 | (define_insn_reservation "r74k_int_madd" 4 | |
70 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") | |
71 | (eq_attr "type" "imadd")) | |
8dd58f01 DU |
72 | "r74k_alu+r74k_mul") |
73 | ||
74 | ;; mul - delivers result to general register in 7 cycles | |
75 | (define_insn_reservation "r74k_int_mul3" 7 | |
74d4d024 | 76 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
77 | (eq_attr "type" "imul3")) |
78 | "r74k_alu+r74k_mul") | |
79 | ||
80 | ;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles | |
81 | (define_insn_reservation "r74k_int_mfhilo" 7 | |
74d4d024 | 82 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
cb00489c | 83 | (eq_attr "type" "mfhi,mflo")) |
8dd58f01 DU |
84 | "r74k_alu+r74k_mul") |
85 | ||
86 | ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass | |
87 | (define_insn_reservation "r74k_int_mthilo" 7 | |
74d4d024 | 88 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
cb00489c | 89 | (eq_attr "type" "mthi,mtlo")) |
8dd58f01 DU |
90 | "r74k_alu+r74k_mul") |
91 | ||
92 | ;; div - default to 50 cycles for 32bit operands. Faster for 8 bit, | |
93 | ;; but is tricky to identify. | |
94 | (define_insn_reservation "r74k_int_div" 50 | |
74d4d024 | 95 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
96 | (eq_attr "type" "idiv")) |
97 | "r74k_alu+r74k_mul*50") | |
98 | ||
99 | ;; call | |
100 | (define_insn_reservation "r74k_int_call" 1 | |
74d4d024 | 101 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
102 | (eq_attr "type" "call")) |
103 | "r74k_agen") | |
104 | ||
105 | ;; branch/jump | |
106 | (define_insn_reservation "r74k_int_jump" 1 | |
74d4d024 | 107 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
108 | (eq_attr "type" "branch,jump")) |
109 | "r74k_agen") | |
110 | ||
111 | ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs | |
112 | ;; prefetch: prefetch, prefetchx | |
113 | (define_insn_reservation "r74k_int_load" 3 | |
74d4d024 | 114 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
115 | (eq_attr "type" "load,prefetch,prefetchx")) |
116 | "r74k_agen") | |
117 | ||
118 | ;; stores | |
119 | (define_insn_reservation "r74k_int_store" 1 | |
74d4d024 | 120 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
121 | (and (eq_attr "type" "store") |
122 | (eq_attr "mode" "!unknown"))) | |
123 | "r74k_agen") | |
124 | ||
125 | ||
126 | ;; Unknowns - Currently these include blockage, consttable and alignment | |
127 | ;; rtls. They do not really affect scheduling latency, (blockage | |
128 | ;; affects scheduling via log links, but not used here). | |
129 | ;; | |
130 | (define_insn_reservation "r74k_unknown" 1 | |
74d4d024 | 131 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
132 | (eq_attr "type" "unknown")) |
133 | "r74k_alu") | |
134 | ||
135 | (define_insn_reservation "r74k_multi" 10 | |
74d4d024 | 136 | (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") |
8dd58f01 DU |
137 | (eq_attr "type" "multi")) |
138 | "(r74k_alu+r74k_agen)*10") | |
139 | ||
140 | ;; -------------------------------------------------------------- | |
141 | ;; Bypass to Consumer | |
142 | ;; -------------------------------------------------------------- | |
143 | ||
144 | ;; load->next use : 3 cycles (Default) | |
145 | ;; load->load base: 4 cycles | |
146 | ;; load->store base: 4 cycles | |
147 | (define_bypass 4 "r74k_int_load" "r74k_int_load") | |
148 | (define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p") | |
149 | ||
b1a14b78 DU |
150 | ;; logical/move/slt/signext->next use : 1 cycles (Default) |
151 | ;; logical/move/slt/signext->load base: 2 cycles | |
152 | ;; logical/move/slt/signext->store base: 2 cycles | |
153 | (define_bypass 2 "r74k_int_logical" "r74k_int_load") | |
154 | (define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p") | |
155 | ||
8dd58f01 DU |
156 | ;; arith->next use : 2 cycles (Default) |
157 | ;; arith->load base: 3 cycles | |
158 | ;; arith->store base: 3 cycles | |
159 | (define_bypass 3 "r74k_int_arith" "r74k_int_load") | |
160 | (define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p") | |
161 | ||
162 | ;; cmove->next use : 4 cycles (Default) | |
163 | ;; cmove->load base: 5 cycles | |
164 | ;; cmove->store base: 5 cycles | |
165 | (define_bypass 5 "r74k_int_cmove" "r74k_int_load") | |
166 | (define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p") | |
167 | ||
d56b9f12 SL |
168 | ;; mult/madd/msub->int_mfhilo : 4 cycles (default) |
169 | ;; mult->madd/msub : 1 cycles | |
170 | ;; madd/msub->madd/msub : 1 cycles | |
171 | (define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd" | |
172 | "mips_linked_madd_p") | |
173 | (define_bypass 1 "r74k_int_madd" "r74k_int_madd" | |
174 | "mips_linked_madd_p") | |
8dd58f01 DU |
175 | |
176 | ;; -------------------------------------------------------------- | |
177 | ;; Floating Point Instructions | |
178 | ;; -------------------------------------------------------------- | |
179 | ||
bdd77024 | 180 | ;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio. |
8dd58f01 DU |
181 | |
182 | ;; fadd, fabs, fneg, | |
bdd77024 RS |
183 | (define_insn_reservation "r74kf1_1_fadd" 4 |
184 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
185 | (eq_attr "type" "fadd,fabs,fneg")) |
186 | "r74k_fpu_arith") | |
187 | ||
bdd77024 RS |
188 | (define_insn_reservation "r74kf2_1_fadd" 8 |
189 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
190 | (eq_attr "type" "fadd,fabs,fneg")) |
191 | "r74k_fpu_arith*2") | |
192 | ||
74d4d024 DU |
193 | (define_insn_reservation "r74kf3_2_fadd" 6 |
194 | (and (eq_attr "cpu" "74kf3_2") | |
195 | (eq_attr "type" "fadd,fabs,fneg")) | |
196 | "r74k_fpu_arith") | |
197 | ||
8dd58f01 | 198 | ;; fmove, fcmove |
bdd77024 RS |
199 | (define_insn_reservation "r74kf1_1_fmove" 4 |
200 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
201 | (eq_attr "type" "fmove")) |
202 | "r74k_fpu_arith") | |
203 | ||
bdd77024 RS |
204 | (define_insn_reservation "r74kf2_1_fmove" 8 |
205 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
206 | (eq_attr "type" "fmove")) |
207 | "r74k_fpu_arith*2") | |
208 | ||
74d4d024 DU |
209 | (define_insn_reservation "r74kf3_2_fmove" 6 |
210 | (and (eq_attr "cpu" "74kf3_2") | |
211 | (eq_attr "type" "fmove")) | |
212 | "r74k_fpu_arith") | |
213 | ||
8dd58f01 | 214 | ;; fload |
bdd77024 RS |
215 | (define_insn_reservation "r74kf1_1_fload" 4 |
216 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
217 | (eq_attr "type" "fpload,fpidxload")) |
218 | "r74k_agen+r74k_fpu_ldst") | |
219 | ||
bdd77024 RS |
220 | (define_insn_reservation "r74kf2_1_fload" 8 |
221 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
222 | (eq_attr "type" "fpload,fpidxload")) |
223 | "r74k_agen+(r74k_fpu_ldst*2)") | |
224 | ||
74d4d024 DU |
225 | (define_insn_reservation "r74kf3_2_fload" 6 |
226 | (and (eq_attr "cpu" "74kf3_2") | |
227 | (eq_attr "type" "fpload,fpidxload")) | |
228 | "r74k_agen+r74k_fpu_ldst") | |
229 | ||
8dd58f01 | 230 | ;; fstore |
bdd77024 RS |
231 | (define_insn_reservation "r74kf1_1_fstore" 1 |
232 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
233 | (eq_attr "type" "fpstore,fpidxstore")) |
234 | "r74k_agen+r74k_fpu_ldst") | |
235 | ||
bdd77024 RS |
236 | (define_insn_reservation "r74kf2_1_fstore" 2 |
237 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
238 | (eq_attr "type" "fpstore,fpidxstore")) |
239 | "r74k_agen+(r74k_fpu_ldst*2)") | |
240 | ||
74d4d024 DU |
241 | (define_insn_reservation "r74kf3_2_fstore" 1 |
242 | (and (eq_attr "cpu" "74kf3_2") | |
243 | (eq_attr "type" "fpstore,fpidxstore")) | |
244 | "r74k_agen+r74k_fpu_ldst") | |
245 | ||
8dd58f01 | 246 | ;; fmul, fmadd |
bdd77024 RS |
247 | (define_insn_reservation "r74kf1_1_fmul_sf" 4 |
248 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
249 | (and (eq_attr "type" "fmul,fmadd") |
250 | (eq_attr "mode" "SF"))) | |
251 | "r74k_fpu_arith") | |
252 | ||
bdd77024 RS |
253 | (define_insn_reservation "r74kf2_1_fmul_sf" 8 |
254 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
255 | (and (eq_attr "type" "fmul,fmadd") |
256 | (eq_attr "mode" "SF"))) | |
257 | "r74k_fpu_arith*2") | |
258 | ||
74d4d024 DU |
259 | (define_insn_reservation "r74kf3_2_fmul_sf" 6 |
260 | (and (eq_attr "cpu" "74kf3_2") | |
261 | (and (eq_attr "type" "fmul,fmadd") | |
262 | (eq_attr "mode" "SF"))) | |
263 | "r74k_fpu_arith") | |
264 | ||
bdd77024 RS |
265 | (define_insn_reservation "r74kf1_1_fmul_df" 5 |
266 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
267 | (and (eq_attr "type" "fmul,fmadd") |
268 | (eq_attr "mode" "DF"))) | |
269 | "r74k_fpu_arith*2") | |
270 | ||
bdd77024 RS |
271 | (define_insn_reservation "r74kf2_1_fmul_df" 10 |
272 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
273 | (and (eq_attr "type" "fmul,fmadd") |
274 | (eq_attr "mode" "DF"))) | |
275 | "r74k_fpu_arith*4") | |
276 | ||
74d4d024 DU |
277 | (define_insn_reservation "r74kf3_2_fmul_df" 7 |
278 | (and (eq_attr "cpu" "74kf3_2") | |
279 | (and (eq_attr "type" "fmul,fmadd") | |
280 | (eq_attr "mode" "DF"))) | |
281 | "r74k_fpu_arith*2") | |
282 | ||
8dd58f01 | 283 | ;; fdiv, fsqrt |
bdd77024 RS |
284 | (define_insn_reservation "r74kf1_1_fdiv_sf" 17 |
285 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
286 | (and (eq_attr "type" "fdiv,fsqrt") |
287 | (eq_attr "mode" "SF"))) | |
288 | "r74k_fpu_arith*14") | |
289 | ||
bdd77024 RS |
290 | (define_insn_reservation "r74kf2_1_fdiv_sf" 34 |
291 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
292 | (and (eq_attr "type" "fdiv,fsqrt") |
293 | (eq_attr "mode" "SF"))) | |
294 | "r74k_fpu_arith*28") | |
295 | ||
74d4d024 DU |
296 | (define_insn_reservation "r74kf3_2_fdiv_sf" 25 |
297 | (and (eq_attr "cpu" "74kf3_2") | |
298 | (and (eq_attr "type" "fdiv,fsqrt") | |
299 | (eq_attr "mode" "SF"))) | |
300 | "r74k_fpu_arith*14") | |
301 | ||
bdd77024 RS |
302 | (define_insn_reservation "r74kf1_1_fdiv_df" 32 |
303 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
304 | (and (eq_attr "type" "fdiv,fsqrt") |
305 | (eq_attr "mode" "DF"))) | |
306 | "r74k_fpu_arith*29") | |
307 | ||
bdd77024 RS |
308 | (define_insn_reservation "r74kf2_1_fdiv_df" 64 |
309 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
310 | (and (eq_attr "type" "fdiv,fsqrt") |
311 | (eq_attr "mode" "DF"))) | |
312 | "r74k_fpu_arith*58") | |
313 | ||
74d4d024 DU |
314 | (define_insn_reservation "r74kf3_2_fdiv_df" 48 |
315 | (and (eq_attr "cpu" "74kf3_2") | |
316 | (and (eq_attr "type" "fdiv,fsqrt") | |
317 | (eq_attr "mode" "DF"))) | |
318 | "r74k_fpu_arith*29") | |
319 | ||
8dd58f01 | 320 | ;; frsqrt |
bdd77024 RS |
321 | (define_insn_reservation "r74kf1_1_frsqrt_sf" 17 |
322 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
323 | (and (eq_attr "type" "frsqrt") |
324 | (eq_attr "mode" "SF"))) | |
325 | "r74k_fpu_arith*14") | |
326 | ||
bdd77024 RS |
327 | (define_insn_reservation "r74kf2_1_frsqrt_sf" 34 |
328 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
329 | (and (eq_attr "type" "frsqrt") |
330 | (eq_attr "mode" "SF"))) | |
331 | "r74k_fpu_arith*28") | |
332 | ||
74d4d024 DU |
333 | (define_insn_reservation "r74kf3_2_frsqrt_sf" 25 |
334 | (and (eq_attr "cpu" "74kf3_2") | |
335 | (and (eq_attr "type" "frsqrt") | |
336 | (eq_attr "mode" "SF"))) | |
337 | "r74k_fpu_arith*14") | |
338 | ||
bdd77024 RS |
339 | (define_insn_reservation "r74kf1_1_frsqrt_df" 36 |
340 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
341 | (and (eq_attr "type" "frsqrt") |
342 | (eq_attr "mode" "DF"))) | |
343 | "r74k_fpu_arith*31") | |
344 | ||
bdd77024 RS |
345 | (define_insn_reservation "r74kf2_1_frsqrt_df" 72 |
346 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
347 | (and (eq_attr "type" "frsqrt") |
348 | (eq_attr "mode" "DF"))) | |
349 | "r74k_fpu_arith*62") | |
350 | ||
74d4d024 DU |
351 | (define_insn_reservation "r74kf3_2_frsqrt_df" 54 |
352 | (and (eq_attr "cpu" "74kf3_2") | |
353 | (and (eq_attr "type" "frsqrt") | |
354 | (eq_attr "mode" "DF"))) | |
355 | "r74k_fpu_arith*31") | |
356 | ||
8dd58f01 | 357 | ;; fcmp |
bdd77024 RS |
358 | (define_insn_reservation "r74kf1_1_fcmp" 4 |
359 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
360 | (eq_attr "type" "fcmp")) |
361 | "r74k_fpu_arith") | |
362 | ||
bdd77024 RS |
363 | (define_insn_reservation "r74kf2_1_fcmp" 8 |
364 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
365 | (eq_attr "type" "fcmp")) |
366 | "r74k_fpu_arith*2") | |
367 | ||
74d4d024 DU |
368 | (define_insn_reservation "r74kf3_2_fcmp" 6 |
369 | (and (eq_attr "cpu" "74kf3_2") | |
370 | (eq_attr "type" "fcmp")) | |
371 | "r74k_fpu_arith") | |
372 | ||
8dd58f01 | 373 | ;; fcvt |
bdd77024 RS |
374 | (define_insn_reservation "r74kf1_1_fcvt" 4 |
375 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
376 | (eq_attr "type" "fcvt")) |
377 | "r74k_fpu_arith") | |
378 | ||
bdd77024 RS |
379 | (define_insn_reservation "r74kf2_1_fcvt" 8 |
380 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
381 | (eq_attr "type" "fcvt")) |
382 | "r74k_fpu_arith*2") | |
383 | ||
74d4d024 DU |
384 | (define_insn_reservation "r74kf3_2_fcvt" 6 |
385 | (and (eq_attr "cpu" "74kf3_2") | |
386 | (eq_attr "type" "fcvt")) | |
387 | "r74k_fpu_arith") | |
388 | ||
8dd58f01 | 389 | ;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1) |
bdd77024 RS |
390 | (define_insn_reservation "r74kf1_1_fxfer_to_c1" 4 |
391 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
392 | (eq_attr "type" "mtc")) |
393 | "r74k_fpu_arith") | |
394 | ||
bdd77024 RS |
395 | (define_insn_reservation "r74kf2_1_fxfer_to_c1" 8 |
396 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
397 | (eq_attr "type" "mtc")) |
398 | "r74k_fpu_arith*2") | |
399 | ||
74d4d024 DU |
400 | (define_insn_reservation "r74kf3_2_fxfer_to_c1" 6 |
401 | (and (eq_attr "cpu" "74kf3_2") | |
402 | (eq_attr "type" "mtc")) | |
403 | "r74k_fpu_arith") | |
404 | ||
bdd77024 RS |
405 | (define_insn_reservation "r74kf1_1_fxfer_from_c1" 1 |
406 | (and (eq_attr "cpu" "74kf1_1") | |
8dd58f01 DU |
407 | (eq_attr "type" "mfc")) |
408 | "r74k_fpu_arith") | |
409 | ||
bdd77024 RS |
410 | (define_insn_reservation "r74kf2_1_fxfer_from_c1" 2 |
411 | (and (eq_attr "cpu" "74kf2_1") | |
8dd58f01 DU |
412 | (eq_attr "type" "mfc")) |
413 | "r74k_fpu_arith*2") | |
74d4d024 DU |
414 | |
415 | (define_insn_reservation "r74kf3_2_fxfer_from_c1" 1 | |
416 | (and (eq_attr "cpu" "74kf3_2") | |
417 | (eq_attr "type" "mfc")) | |
418 | "r74k_fpu_arith") |