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1 | ;; Constraint definitions for MIPS. |
2 | ;; Copyright (C) 2006 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 2, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING. If not, write to | |
18 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, | |
19 | ;; Boston, MA 02110-1301, USA. | |
20 | ||
21 | ;; Register constraints | |
22 | ||
23 | (define_register_constraint "d" "BASE_REG_CLASS" | |
24 | "An address register. This is equivalent to @code{r} unless | |
25 | generating MIPS16 code.") | |
26 | ||
27 | (define_register_constraint "t" "T_REG" | |
28 | "@internal") | |
29 | ||
30 | (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" | |
31 | "A floating-point register (if available).") | |
32 | ||
48156a39 | 33 | (define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG" |
cbbb5b6d RS |
34 | "The @code{hi} register.") |
35 | ||
48156a39 | 36 | (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG" |
cbbb5b6d RS |
37 | "The @code{lo} register.") |
38 | ||
39 | (define_register_constraint "x" "MD_REGS" | |
40 | "The @code{hi} and @code{lo} registers.") | |
41 | ||
42 | (define_register_constraint "b" "ALL_REGS" | |
43 | "@internal") | |
44 | ||
14976818 | 45 | (define_register_constraint "c" "TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG |
cbbb5b6d RS |
46 | : TARGET_MIPS16 ? M16_NA_REGS |
47 | : GR_REGS" | |
48 | "A register suitable for use in an indirect jump. This will always be | |
49 | @code{$25} for @option{-mabicalls}.") | |
50 | ||
51 | (define_register_constraint "e" "LEA_REGS" | |
52 | "@internal") | |
53 | ||
54 | (define_register_constraint "j" "PIC_FN_ADDR_REG" | |
55 | "@internal") | |
56 | ||
57 | (define_register_constraint "v" "V1_REG" | |
58 | "@internal") | |
59 | ||
60 | (define_register_constraint "y" "GR_REGS" | |
61 | "Equivalent to @code{r}; retained for backwards compatibility.") | |
62 | ||
63 | (define_register_constraint "z" "ST_REGS" | |
64 | "A floating-point condition code register.") | |
65 | ||
66 | (define_register_constraint "A" "DSP_ACC_REGS" | |
67 | "@internal") | |
68 | ||
69 | (define_register_constraint "a" "ACC_REGS" | |
70 | "@internal") | |
71 | ||
72 | (define_register_constraint "B" "COP0_REGS" | |
73 | "@internal") | |
74 | ||
75 | (define_register_constraint "C" "COP2_REGS" | |
76 | "@internal") | |
77 | ||
78 | (define_register_constraint "D" "COP3_REGS" | |
79 | "@internal") | |
80 | ||
7f9844ca RS |
81 | ;; Registers that can be used as the target of multiply-accumulate |
82 | ;; instructions. The core MIPS32 ISA provides a hi/lo madd, | |
83 | ;; but the DSPr2 version allows any accumulator target. | |
84 | (define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS") | |
85 | ||
f348741d RS |
86 | ;; This is a normal rather than a register constraint because we can |
87 | ;; never use the stack pointer as a reload register. | |
88 | (define_constraint "ks" | |
89 | "@internal" | |
90 | (and (match_code "reg") | |
91 | (match_test "REGNO (op) == STACK_POINTER_REGNUM"))) | |
92 | ||
cbbb5b6d RS |
93 | ;; Integer constraints |
94 | ||
95 | (define_constraint "I" | |
96 | "A signed 16-bit constant (for arithmetic instructions)." | |
97 | (and (match_code "const_int") | |
98 | (match_test "SMALL_OPERAND (ival)"))) | |
99 | ||
100 | (define_constraint "J" | |
101 | "Integer zero." | |
102 | (and (match_code "const_int") | |
103 | (match_test "ival == 0"))) | |
104 | ||
105 | (define_constraint "K" | |
106 | "An unsigned 16-bit constant (for logic instructions)." | |
107 | (and (match_code "const_int") | |
108 | (match_test "SMALL_OPERAND_UNSIGNED (ival)"))) | |
109 | ||
110 | (define_constraint "L" | |
111 | "A signed 32-bit constant in which the lower 16 bits are zero. | |
112 | Such constants can be loaded using @code{lui}." | |
113 | (and (match_code "const_int") | |
114 | (match_test "LUI_OPERAND (ival)"))) | |
115 | ||
116 | (define_constraint "M" | |
117 | "A constant that cannot be loaded using @code{lui}, @code{addiu} | |
118 | or @code{ori}." | |
119 | (and (match_code "const_int") | |
120 | (match_test "!SMALL_OPERAND (ival)") | |
121 | (match_test "!SMALL_OPERAND_UNSIGNED (ival)") | |
122 | (match_test "!LUI_OPERAND (ival)"))) | |
123 | ||
124 | (define_constraint "N" | |
125 | "A constant in the range -65535 to -1 (inclusive)." | |
126 | (and (match_code "const_int") | |
127 | (match_test "ival >= -0xffff && ival < 0"))) | |
128 | ||
129 | (define_constraint "O" | |
130 | "A signed 15-bit constant." | |
131 | (and (match_code "const_int") | |
132 | (match_test "ival >= -0x4000 && ival < 0x4000"))) | |
133 | ||
134 | (define_constraint "P" | |
135 | "A constant in the range 1 to 65535 (inclusive)." | |
136 | (and (match_code "const_int") | |
137 | (match_test "ival > 0 && ival < 0x10000"))) | |
138 | ||
139 | ;; Floating-point constraints | |
140 | ||
141 | (define_constraint "G" | |
142 | "Floating-point zero." | |
143 | (and (match_code "const_double") | |
144 | (match_test "op == CONST0_RTX (mode)"))) | |
145 | ||
146 | ;; General constraints | |
147 | ||
148 | (define_constraint "Q" | |
149 | "@internal" | |
150 | (match_operand 0 "const_arith_operand")) | |
151 | ||
152 | (define_memory_constraint "R" | |
153 | "An address that can be used in a non-macro load or store." | |
154 | (and (match_code "mem") | |
155 | (match_test "mips_fetch_insns (op) == 1"))) | |
156 | ||
157 | (define_constraint "S" | |
158 | "@internal | |
159 | A constant call address." | |
160 | (and (match_operand 0 "call_insn_operand") | |
161 | (match_test "CONSTANT_P (op)"))) | |
162 | ||
163 | (define_constraint "T" | |
164 | "@internal | |
165 | A constant @code{move_operand} that cannot be safely loaded into @code{$25} | |
166 | using @code{la}." | |
167 | (and (match_operand 0 "move_operand") | |
168 | (match_test "CONSTANT_P (op)") | |
169 | (match_test "mips_dangerous_for_la25_p (op)"))) | |
170 | ||
171 | (define_constraint "U" | |
172 | "@internal | |
173 | A constant @code{move_operand} that can be safely loaded into @code{$25} | |
174 | using @code{la}." | |
175 | (and (match_operand 0 "move_operand") | |
176 | (match_test "CONSTANT_P (op)") | |
177 | (match_test "!mips_dangerous_for_la25_p (op)"))) | |
178 | ||
179 | (define_memory_constraint "W" | |
180 | "@internal | |
181 | A memory address based on a member of @code{BASE_REG_CLASS}. This is | |
182 | true for all non-mips16 references (although it can sometimes be implicit | |
183 | if @samp{!TARGET_EXPLICIT_RELOCS}). For MIPS16, it excludes stack and | |
184 | constant-pool references." | |
185 | (and (match_code "mem") | |
186 | (match_operand 0 "memory_operand") | |
187 | (ior (match_test "!TARGET_MIPS16") | |
188 | (and (not (match_operand 0 "stack_operand")) | |
189 | (not (match_test "CONSTANT_P (XEXP (op, 0))")))))) | |
190 | ||
191 | (define_constraint "YG" | |
192 | "@internal | |
193 | A vector zero." | |
194 | (and (match_code "const_vector") | |
195 | (match_test "op == CONST0_RTX (mode)"))) | |
196 | ||
197 | (define_constraint "YA" | |
198 | "@internal | |
199 | An unsigned 6-bit constant." | |
200 | (and (match_code "const_int") | |
201 | (match_test "UIMM6_OPERAND (ival)"))) | |
202 | ||
203 | (define_constraint "YB" | |
204 | "@internal | |
205 | A signed 10-bit constant." | |
206 | (and (match_code "const_int") | |
207 | (match_test "IMM10_OPERAND (ival)"))) |