[thirdparty/gcc.git] / gcc / config / mips / constraints.md

;; Constraint definitions for MIPS.
;; Copyright (C) 2006-2024 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; Register constraints

(define_register_constraint "d" "TARGET_MIPS16 ? M16_REGS : GR_REGS"
  "A general-purpose register.  This is equivalent to @code{r} unless
   generating MIPS16 code, in which case the MIPS16 register set is used.")

(define_register_constraint "t" "T_REG"
  "@internal")

(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
  "A floating-point register (if available).")

(define_register_constraint "h" "NO_REGS"
  "Formerly the @code{hi} register.  This constraint is no longer supported.")

(define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
  "The @code{lo} register.  Use this register to store values that are
   no bigger than a word.")

(define_register_constraint "x" "MD_REGS"
  "The concatenated @code{hi} and @code{lo} registers.  Use this register
   to store doubleword values.")

(define_register_constraint "b" "ALL_REGS"
  "@internal")

(define_register_constraint "u" "M16_REGS"
  "@internal")

;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn
;; for details.
(define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
				 : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
				 : GR_REGS"
  "A register suitable for use in an indirect jump.  This will always be
   @code{$25} for @option{-mabicalls}.")

(define_register_constraint "e" "LEA_REGS"
  "@internal")

(define_register_constraint "j" "PIC_FN_ADDR_REG"
  "@internal")

;; Don't use this constraint in gcc code!  It runs the risk of
;; introducing a spill failure; see tls_get_tp_<mode>.
(define_register_constraint "v" "V1_REG"
  "Register @code{$3}.  Do not use this constraint in new code;
   it is retained only for compatibility with glibc.")

(define_register_constraint "y" "GR_REGS"
  "Equivalent to @code{r}; retained for backwards compatibility.")

(define_register_constraint "z" "ST_REGS"
  "A floating-point condition code register.")

(define_register_constraint "A" "DSP_ACC_REGS"
  "@internal")

(define_register_constraint "a" "ACC_REGS"
  "@internal")

(define_register_constraint "B" "COP0_REGS"
  "@internal")

(define_register_constraint "C" "COP2_REGS"
  "@internal")

(define_register_constraint "D" "COP3_REGS"
  "@internal")

;; Registers that can be used as the target of multiply-accumulate
;; instructions.  The core MIPS32 ISA provides a hi/lo madd,
;; but the DSP version allows any accumulator target.
(define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")

(define_register_constraint "kb" "M16_STORE_REGS"
  "@internal")

(define_constraint "kf"
  "@internal"
  (match_operand 0 "force_to_mem_operand"))

;; This is a normal rather than a register constraint because we can
;; never use the stack pointer as a reload register.
(define_constraint "ks"
  "@internal"
  (and (match_code "reg")
       (match_test "REGNO (op) == STACK_POINTER_REGNUM")))

;; Integer constraints

(define_constraint "I"
  "A signed 16-bit constant (for arithmetic instructions)."
  (and (match_code "const_int")
       (match_test "SMALL_OPERAND (ival)")))

(define_constraint "J"
  "Integer zero."
  (and (match_code "const_int")
       (match_test "ival == 0")))

(define_constraint "K"
  "An unsigned 16-bit constant (for logic instructions)."
  (and (match_code "const_int")
       (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
 
(define_constraint "L"
  "A signed 32-bit constant in which the lower 16 bits are zero.
   Such constants can be loaded using @code{lui}."
  (and (match_code "const_int")
       (match_test "LUI_OPERAND (ival)")))

(define_constraint "M"
  "A constant that cannot be loaded using @code{lui}, @code{addiu}
   or @code{ori}."
  (and (match_code "const_int")
       (not (match_test "SMALL_OPERAND (ival)"))
       (not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
       (not (match_test "LUI_OPERAND (ival)"))))

(define_constraint "N"
  "A constant in the range -65535 to -1 (inclusive)."
  (and (match_code "const_int")
       (match_test "ival >= -0xffff && ival < 0")))

(define_constraint "O"
  "A signed 15-bit constant."
  (and (match_code "const_int")
       (match_test "ival >= -0x4000 && ival < 0x4000")))

(define_constraint "P"
  "A constant in the range 1 to 65535 (inclusive)."
  (and (match_code "const_int")
       (match_test "ival > 0 && ival < 0x10000")))

;; Floating-point constraints

(define_constraint "G"
  "Floating-point zero."
  (and (match_code "const_double")
       (match_test "op == CONST0_RTX (mode)")))

;; General constraints

(define_constraint "Q"
  "@internal"
  (match_operand 0 "const_arith_operand"))

(define_memory_constraint "R"
  "An address that can be used in a non-macro load or store."
  (and (match_code "mem")
       (match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))

(define_constraint "S"
  "@internal
   A constant call address."
  (and (match_operand 0 "call_insn_operand")
       (match_test "CONSTANT_P (op)")))

(define_constraint "Udb7"
  "@internal
   A decremented unsigned constant of 7 bits."
  (match_operand 0 "db7_operand"))

(define_constraint "Udb8"
  "@internal
   A decremented unsigned constant of 8 bits."
  (match_operand 0 "db8_operand"))

(define_constraint "Uead"
  "@internal
   A microMIPS encoded ADDIUR2 immediate operand."
  (match_operand 0 "addiur2_operand"))
  
(define_constraint "Uean"
  "@internal
   A microMIPS encoded ANDI operand."
  (match_operand 0 "andi16_operand"))

(define_constraint "Uesp"
  "@internal
   A microMIPS encoded ADDIUSP operand."
  (match_operand 0 "addiusp_operand"))

(define_constraint "Uib3"
  "@internal
   An unsigned, incremented constant of 3 bits."
  (match_operand 0 "ib3_operand"))

(define_constraint "Usb4"
  "@internal
   A signed constant of 4 bits."
  (match_operand 0 "sb4_operand"))

(define_constraint "Usb5"
  "@internal
   A signed constant of 5 bits."
  (match_operand 0 "sb5_operand"))

(define_constraint "Usb8"
  "@internal
   A signed constant of 8 bits."
  (match_operand 0 "sb8_operand"))

(define_constraint "Usd8"
  "@internal
   A signed constant of 8 bits, shifted left three places."
  (match_operand 0 "sd8_operand"))

(define_constraint "Uub8"
  "@internal
   An unsigned constant of 8 bits."
  (match_operand 0 "ub8_operand"))

(define_constraint "Uuw5"
  "@internal
   An unsigned constant of 5 bits, shifted left two places."
  (match_operand 0 "uw5_operand"))

(define_constraint "Uuw6"
  "@internal
   An unsigned constant of 6 bits, shifted left two places."
  (match_operand 0 "uw6_operand"))

(define_constraint "Uuw8"
  "@internal
   An unsigned constant of 8 bits, shifted left two places."
  (match_operand 0 "uw8_operand"))

(define_memory_constraint "W"
  "@internal
   A memory address based on a member of @code{BASE_REG_CLASS}.  This is
   true for all non-mips16 references (although it can sometimes be implicit
   if @samp{!TARGET_EXPLICIT_RELOCS}).  For MIPS16, it excludes stack and
   constant-pool references."
  (and (match_code "mem")
       (match_operand 0 "memory_operand")
       (ior (not (match_test "TARGET_MIPS16"))
	    (and (not (match_operand 0 "stack_operand"))
		 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))

(define_constraint "YG"
  "@internal
   A vector zero."
  (and (match_code "const_vector")
       (match_test "op == CONST0_RTX (mode)")))

(define_constraint "Yz"
  "@internal"
  (match_operand 0 "bit_clear_operand"))

(define_constraint "YA"
  "@internal
   An unsigned 6-bit constant."
  (and (match_code "const_int")
       (match_test "UIMM6_OPERAND (ival)")))

(define_constraint "YB"
  "@internal
   A signed 10-bit constant."
  (and (match_code "const_int")
       (match_test "IMM10_OPERAND (ival)")))

(define_constraint "Yb"
   "@internal"
   (match_operand 0 "qi_mask_operand"))

(define_constraint "Yd"
  "@internal
   A constant @code{move_operand} that can be safely loaded into @code{$25}
   using @code{la}."
  (and (match_operand 0 "move_operand")
       (match_test "CONSTANT_P (op)")
       (not (match_test "mips_dangerous_for_la25_p (op)"))))

(define_constraint "Yf"
  "@internal
   A constant @code{move_operand} that cannot be safely loaded into @code{$25}
   using @code{la}."
  (and (match_operand 0 "move_operand")
       (match_test "CONSTANT_P (op)")
       (match_test "mips_dangerous_for_la25_p (op)")))

(define_constraint "Yh"
   "@internal"
    (match_operand 0 "hi_mask_operand"))

(define_constraint "Yw"
   "@internal"
    (match_operand 0 "si_mask_operand"))

(define_constraint "Yx"
   "@internal"
   (match_operand 0 "low_bitmask_operand"))

(define_constraint "YI"
  "@internal
   A replicated vector const in which the replicated value is in the range
   [-512,511]."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_same_int_p (op, mode, -512, 511)")))

(define_constraint "YC"
  "@internal
   A replicated vector const in which the replicated value has a single
   bit set."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_bitimm_set_p (op, mode)")))

(define_constraint "YZ"
  "@internal
   A replicated vector const in which the replicated value has a single
   bit clear."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_bitimm_clr_p (op, mode)")))

(define_constraint "Unv5"
  "@internal
   A replicated vector const in which the replicated value is in the range
   [-31,0]."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_same_int_p (op, mode, -31, 0)")))

(define_constraint "Uuv5"
  "@internal
   A replicated vector const in which the replicated value is in the range
   [0,31]."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_same_int_p (op, mode, 0, 31)")))

(define_constraint "Usv5"
  "@internal
   A replicated vector const in which the replicated value is in the range
   [-16,15]."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_same_int_p (op, mode, -16, 15)")))

(define_constraint "Uuv6"
  "@internal
   A replicated vector const in which the replicated value is in the range
   [0,63]."
  (and (match_code "const_vector")
       (match_test "mips_const_vector_same_int_p (op, mode, 0, 63)")))

(define_constraint "Urv8"
  "@internal
   A replicated vector const with replicated byte values as well as elements"
  (and (match_code "const_vector")
       (match_test "mips_const_vector_same_bytes_p (op, mode)")))

(define_memory_constraint "ZC"
  "A memory operand whose address is formed by a base register and offset
   that is suitable for use in instructions with the same addressing mode
   as @code{ll} and @code{sc}."
  (and (match_code "mem")
       (if_then_else
	 (match_test "TARGET_MICROMIPS")
	 (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
	 (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
	   (match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)")
	   (match_test "mips_address_insns (XEXP (op, 0), mode, false)")))))

(define_address_constraint "ZD"
  "An address suitable for a @code{prefetch} instruction, or for any other
   instruction with the same addressing mode as @code{prefetch}."
   (if_then_else (match_test "TARGET_MICROMIPS")
		 (match_test "umips_12bit_offset_address_p (op, mode)")
	  (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
			(match_test "mips_9bit_offset_address_p (op, mode)")
			(match_test "mips_address_insns (op, mode, false)"))))

(define_memory_constraint "ZR"
 "@internal
  An address valid for loading/storing register exclusive"
 (match_operand 0 "mem_noofs_operand"))

(define_memory_constraint "ZS"
  "@internal
   A microMIPS memory operand for use with the LWSP/SWSP insns."
  (and (match_code "mem")
       (match_operand 0 "lwsp_swsp_operand")))

(define_memory_constraint "ZT"
  "@internal
   A microMIPS memory operand for use with the LW16/SW16 insns."
  (and (match_code "mem")
       (match_operand 0 "lw16_sw16_operand")))

(define_memory_constraint "ZU"
  "@internal
   A microMIPS memory operand for use with the LHU16/SH16 insns."
  (and (match_code "mem")
       (match_operand 0 "lhu16_sh16_operand")))

(define_memory_constraint "ZV"
  "@internal
   A microMIPS memory operand for use with the SB16 insn."
  (and (match_code "mem")
       (match_operand 0 "sb16_operand")))

(define_memory_constraint "ZW"
  "@internal
   A microMIPS memory operand for use with the LBU16 insn."
  (and (match_code "mem")
       (match_operand 0 "lbu16_operand")))
Commit	Line	Data
cbbb5b6d	1	;; Constraint definitions for MIPS.
a945c346	2	;; Copyright (C) 2006-2024 Free Software Foundation, Inc.
cbbb5b6d RS	3	;;
	4	;; This file is part of GCC.
	5	;;
	6	;; GCC is free software; you can redistribute it and/or modify
	7	;; it under the terms of the GNU General Public License as published by
2f83c7d6	8	;; the Free Software Foundation; either version 3, or (at your option)
cbbb5b6d RS	9	;; any later version.
	10	;;
	11	;; GCC is distributed in the hope that it will be useful,
	12	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	;; GNU General Public License for more details.
	15	;;
	16	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	17	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	18	;; <http://www.gnu.org/licenses/>.
cbbb5b6d RS	19
	20	;; Register constraints
	21
a78cc314	22	(define_register_constraint "d" "TARGET_MIPS16 ? M16_REGS : GR_REGS"
0cb14750 MR	23	"A general-purpose register. This is equivalent to @code{r} unless
0cb14750 MR	24	generating MIPS16 code, in which case the MIPS16 register set is used.")
cbbb5b6d RS	25
	26	(define_register_constraint "t" "T_REG"
	27	"@internal")
	28
	29	(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
	30	"A floating-point register (if available).")
	31
21dfc6dc RS	32	(define_register_constraint "h" "NO_REGS"
21dfc6dc RS	33	"Formerly the @code{hi} register. This constraint is no longer supported.")
cbbb5b6d	34
48156a39	35	(define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
21dfc6dc RS	36	"The @code{lo} register. Use this register to store values that are
21dfc6dc RS	37	no bigger than a word.")
cbbb5b6d RS	38
cbbb5b6d RS	39	(define_register_constraint "x" "MD_REGS"
21dfc6dc RS	40	"The concatenated @code{hi} and @code{lo} registers. Use this register
21dfc6dc RS	41	to store doubleword values.")
cbbb5b6d RS	42
	43	(define_register_constraint "b" "ALL_REGS"
	44	"@internal")
	45
03a7dddb CM	46	(define_register_constraint "u" "M16_REGS"
	47	"@internal")
	48
08d0963a RS	49	;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn
	50	;; for details.
	51	(define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
	52	: TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
cbbb5b6d RS	53	: GR_REGS"
	54	"A register suitable for use in an indirect jump. This will always be
	55	@code{$25} for @option{-mabicalls}.")
	56
	57	(define_register_constraint "e" "LEA_REGS"
	58	"@internal")
	59
	60	(define_register_constraint "j" "PIC_FN_ADDR_REG"
	61	"@internal")
	62
2feaae20 RS	63	;; Don't use this constraint in gcc code! It runs the risk of
	64	;; introducing a spill failure; see tls_get_tp_<mode>.
	65	(define_register_constraint "v" "V1_REG"
	66	"Register @code{$3}. Do not use this constraint in new code;
	67	it is retained only for compatibility with glibc.")
	68
cbbb5b6d RS	69	(define_register_constraint "y" "GR_REGS"
	70	"Equivalent to @code{r}; retained for backwards compatibility.")
	71
	72	(define_register_constraint "z" "ST_REGS"
	73	"A floating-point condition code register.")
	74
	75	(define_register_constraint "A" "DSP_ACC_REGS"
	76	"@internal")
	77
	78	(define_register_constraint "a" "ACC_REGS"
	79	"@internal")
	80
	81	(define_register_constraint "B" "COP0_REGS"
	82	"@internal")
	83
	84	(define_register_constraint "C" "COP2_REGS"
	85	"@internal")
	86
	87	(define_register_constraint "D" "COP3_REGS"
	88	"@internal")
	89
7f9844ca RS	90	;; Registers that can be used as the target of multiply-accumulate
7f9844ca RS	91	;; instructions. The core MIPS32 ISA provides a hi/lo madd,
293b77b0 CF	92	;; but the DSP version allows any accumulator target.
293b77b0 CF	93	(define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
7f9844ca	94
5e7d8b4c RS	95	(define_register_constraint "kb" "M16_STORE_REGS"
	96	"@internal")
	97
206c2d7a RS	98	(define_constraint "kf"
	99	"@internal"
	100	(match_operand 0 "force_to_mem_operand"))
	101
f348741d RS	102	;; This is a normal rather than a register constraint because we can
	103	;; never use the stack pointer as a reload register.
	104	(define_constraint "ks"
	105	"@internal"
	106	(and (match_code "reg")
	107	(match_test "REGNO (op) == STACK_POINTER_REGNUM")))
	108
cbbb5b6d RS	109	;; Integer constraints
	110
	111	(define_constraint "I"
	112	"A signed 16-bit constant (for arithmetic instructions)."
	113	(and (match_code "const_int")
	114	(match_test "SMALL_OPERAND (ival)")))
	115
	116	(define_constraint "J"
	117	"Integer zero."
	118	(and (match_code "const_int")
	119	(match_test "ival == 0")))
	120
	121	(define_constraint "K"
	122	"An unsigned 16-bit constant (for logic instructions)."
	123	(and (match_code "const_int")
	124	(match_test "SMALL_OPERAND_UNSIGNED (ival)")))
	125
	126	(define_constraint "L"
	127	"A signed 32-bit constant in which the lower 16 bits are zero.
	128	Such constants can be loaded using @code{lui}."
	129	(and (match_code "const_int")
	130	(match_test "LUI_OPERAND (ival)")))
	131
	132	(define_constraint "M"
	133	"A constant that cannot be loaded using @code{lui}, @code{addiu}
	134	or @code{ori}."
	135	(and (match_code "const_int")
ae0087f2 RS	136	(not (match_test "SMALL_OPERAND (ival)"))
	137	(not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
	138	(not (match_test "LUI_OPERAND (ival)"))))
cbbb5b6d RS	139
	140	(define_constraint "N"
	141	"A constant in the range -65535 to -1 (inclusive)."
	142	(and (match_code "const_int")
	143	(match_test "ival >= -0xffff && ival < 0")))
	144
	145	(define_constraint "O"
	146	"A signed 15-bit constant."
	147	(and (match_code "const_int")
	148	(match_test "ival >= -0x4000 && ival < 0x4000")))
	149
	150	(define_constraint "P"
	151	"A constant in the range 1 to 65535 (inclusive)."
	152	(and (match_code "const_int")
	153	(match_test "ival > 0 && ival < 0x10000")))
	154
	155	;; Floating-point constraints
	156
	157	(define_constraint "G"
	158	"Floating-point zero."
	159	(and (match_code "const_double")
	160	(match_test "op == CONST0_RTX (mode)")))
	161
	162	;; General constraints
	163
	164	(define_constraint "Q"
	165	"@internal"
	166	(match_operand 0 "const_arith_operand"))
	167
	168	(define_memory_constraint "R"
	169	"An address that can be used in a non-macro load or store."
	170	(and (match_code "mem")
5955b0a3	171	(match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))
cbbb5b6d RS	172
	173	(define_constraint "S"
	174	"@internal
	175	A constant call address."
	176	(and (match_operand 0 "call_insn_operand")
	177	(match_test "CONSTANT_P (op)")))
	178
03a7dddb CM	179	(define_constraint "Udb7"
	180	"@internal
	181	A decremented unsigned constant of 7 bits."
	182	(match_operand 0 "db7_operand"))
	183
cb2558bc RS	184	(define_constraint "Udb8"
	185	"@internal
	186	A decremented unsigned constant of 8 bits."
	187	(match_operand 0 "db8_operand"))
	188
03a7dddb CM	189	(define_constraint "Uead"
	190	"@internal
	191	A microMIPS encoded ADDIUR2 immediate operand."
	192	(match_operand 0 "addiur2_operand"))
	193
	194	(define_constraint "Uean"
	195	"@internal
	196	A microMIPS encoded ANDI operand."
	197	(match_operand 0 "andi16_operand"))
	198
	199	(define_constraint "Uesp"
	200	"@internal
	201	A microMIPS encoded ADDIUSP operand."
	202	(match_operand 0 "addiusp_operand"))
	203
	204	(define_constraint "Uib3"
	205	"@internal
	206	An unsigned, incremented constant of 3 bits."
	207	(match_operand 0 "ib3_operand"))
	208
cb2558bc RS	209	(define_constraint "Usb4"
	210	"@internal
	211	A signed constant of 4 bits."
	212	(match_operand 0 "sb4_operand"))
	213
	214	(define_constraint "Usb5"
	215	"@internal
	216	A signed constant of 5 bits."
	217	(match_operand 0 "sb5_operand"))
	218
	219	(define_constraint "Usb8"
	220	"@internal
	221	A signed constant of 8 bits."
	222	(match_operand 0 "sb8_operand"))
	223
	224	(define_constraint "Usd8"
	225	"@internal
	226	A signed constant of 8 bits, shifted left three places."
	227	(match_operand 0 "sd8_operand"))
	228
	229	(define_constraint "Uub8"
	230	"@internal
	231	An unsigned constant of 8 bits."
	232	(match_operand 0 "ub8_operand"))
	233
	234	(define_constraint "Uuw5"
	235	"@internal
	236	An unsigned constant of 5 bits, shifted left two places."
	237	(match_operand 0 "uw5_operand"))
	238
03a7dddb CM	239	(define_constraint "Uuw6"
	240	"@internal
	241	An unsigned constant of 6 bits, shifted left two places."
	242	(match_operand 0 "uw6_operand"))
	243
cb2558bc	244	(define_constraint "Uuw8"
03a7dddb	245	"@internal
cb2558bc RS	246	An unsigned constant of 8 bits, shifted left two places."
cb2558bc RS	247	(match_operand 0 "uw8_operand"))
03a7dddb	248
cbbb5b6d RS	249	(define_memory_constraint "W"
	250	"@internal
	251	A memory address based on a member of @code{BASE_REG_CLASS}. This is
	252	true for all non-mips16 references (although it can sometimes be implicit
	253	if @samp{!TARGET_EXPLICIT_RELOCS}). For MIPS16, it excludes stack and
	254	constant-pool references."
	255	(and (match_code "mem")
	256	(match_operand 0 "memory_operand")
ae0087f2	257	(ior (not (match_test "TARGET_MIPS16"))
cbbb5b6d RS	258	(and (not (match_operand 0 "stack_operand"))
	259	(not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
	260
	261	(define_constraint "YG"
	262	"@internal
	263	A vector zero."
	264	(and (match_code "const_vector")
	265	(match_test "op == CONST0_RTX (mode)")))
	266
42d6b905 JM	267	(define_constraint "Yz"
	268	"@internal"
	269	(match_operand 0 "bit_clear_operand"))
	270
cbbb5b6d RS	271	(define_constraint "YA"
	272	"@internal
	273	An unsigned 6-bit constant."
	274	(and (match_code "const_int")
	275	(match_test "UIMM6_OPERAND (ival)")))
	276
	277	(define_constraint "YB"
	278	"@internal
	279	A signed 10-bit constant."
	280	(and (match_code "const_int")
	281	(match_test "IMM10_OPERAND (ival)")))
b2c9d70f AN	282
	283	(define_constraint "Yb"
	284	"@internal"
	285	(match_operand 0 "qi_mask_operand"))
	286
4547b7ee RS	287	(define_constraint "Yd"
	288	"@internal
	289	A constant @code{move_operand} that can be safely loaded into @code{$25}
	290	using @code{la}."
	291	(and (match_operand 0 "move_operand")
	292	(match_test "CONSTANT_P (op)")
	293	(not (match_test "mips_dangerous_for_la25_p (op)"))))
	294
	295	(define_constraint "Yf"
	296	"@internal
	297	A constant @code{move_operand} that cannot be safely loaded into @code{$25}
	298	using @code{la}."
	299	(and (match_operand 0 "move_operand")
	300	(match_test "CONSTANT_P (op)")
	301	(match_test "mips_dangerous_for_la25_p (op)")))
	302
b2c9d70f AN	303	(define_constraint "Yh"
	304	"@internal"
	305	(match_operand 0 "hi_mask_operand"))
	306
	307	(define_constraint "Yw"
	308	"@internal"
	309	(match_operand 0 "si_mask_operand"))
	310
	311	(define_constraint "Yx"
	312	"@internal"
	313	(match_operand 0 "low_bitmask_operand"))
6399761a	314
6cf538da RS	315	(define_constraint "YI"
	316	"@internal
	317	A replicated vector const in which the replicated value is in the range
	318	[-512,511]."
	319	(and (match_code "const_vector")
	320	(match_test "mips_const_vector_same_int_p (op, mode, -512, 511)")))
	321
	322	(define_constraint "YC"
	323	"@internal
	324	A replicated vector const in which the replicated value has a single
	325	bit set."
	326	(and (match_code "const_vector")
	327	(match_test "mips_const_vector_bitimm_set_p (op, mode)")))
	328
	329	(define_constraint "YZ"
	330	"@internal
	331	A replicated vector const in which the replicated value has a single
	332	bit clear."
	333	(and (match_code "const_vector")
	334	(match_test "mips_const_vector_bitimm_clr_p (op, mode)")))
	335
	336	(define_constraint "Unv5"
	337	"@internal
	338	A replicated vector const in which the replicated value is in the range
	339	[-31,0]."
	340	(and (match_code "const_vector")
	341	(match_test "mips_const_vector_same_int_p (op, mode, -31, 0)")))
	342
	343	(define_constraint "Uuv5"
	344	"@internal
	345	A replicated vector const in which the replicated value is in the range
	346	[0,31]."
	347	(and (match_code "const_vector")
	348	(match_test "mips_const_vector_same_int_p (op, mode, 0, 31)")))
	349
	350	(define_constraint "Usv5"
	351	"@internal
	352	A replicated vector const in which the replicated value is in the range
	353	[-16,15]."
	354	(and (match_code "const_vector")
	355	(match_test "mips_const_vector_same_int_p (op, mode, -16, 15)")))
	356
	357	(define_constraint "Uuv6"
	358	"@internal
	359	A replicated vector const in which the replicated value is in the range
	360	[0,63]."
	361	(and (match_code "const_vector")
	362	(match_test "mips_const_vector_same_int_p (op, mode, 0, 63)")))
	363
	364	(define_constraint "Urv8"
	365	"@internal
	366	A replicated vector const with replicated byte values as well as elements"
	367	(and (match_code "const_vector")
	368	(match_test "mips_const_vector_same_bytes_p (op, mode)")))
	369
22c4c869	370	(define_memory_constraint "ZC"
047b52f6 MF	371	"A memory operand whose address is formed by a base register and offset
	372	that is suitable for use in instructions with the same addressing mode
	373	as @code{ll} and @code{sc}."
22c4c869 CM	374	(and (match_code "mem")
	375	(if_then_else
	376	(match_test "TARGET_MICROMIPS")
	377	(match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
047b52f6 MF	378	(if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
	379	(match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)")
	380	(match_test "mips_address_insns (XEXP (op, 0), mode, false)")))))
22c4c869 CM	381
22c4c869 CM	382	(define_address_constraint "ZD"
82f84ecb MF	383	"An address suitable for a @code{prefetch} instruction, or for any other
82f84ecb MF	384	instruction with the same addressing mode as @code{prefetch}."
22c4c869 CM	385	(if_then_else (match_test "TARGET_MICROMIPS")
22c4c869 CM	386	(match_test "umips_12bit_offset_address_p (op, mode)")
047b52f6	387	(if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
82f84ecb MF	388	(match_test "mips_9bit_offset_address_p (op, mode)")
82f84ecb MF	389	(match_test "mips_address_insns (op, mode, false)"))))
22c4c869	390
6399761a TV	391	(define_memory_constraint "ZR"
	392	"@internal
	393	An address valid for loading/storing register exclusive"
	394	(match_operand 0 "mem_noofs_operand"))
03a7dddb CM	395
	396	(define_memory_constraint "ZS"
	397	"@internal
	398	A microMIPS memory operand for use with the LWSP/SWSP insns."
	399	(and (match_code "mem")
	400	(match_operand 0 "lwsp_swsp_operand")))
	401
	402	(define_memory_constraint "ZT"
	403	"@internal
	404	A microMIPS memory operand for use with the LW16/SW16 insns."
	405	(and (match_code "mem")
	406	(match_operand 0 "lw16_sw16_operand")))
	407
	408	(define_memory_constraint "ZU"
	409	"@internal
	410	A microMIPS memory operand for use with the LHU16/SH16 insns."
	411	(and (match_code "mem")
	412	(match_operand 0 "lhu16_sh16_operand")))
	413
	414	(define_memory_constraint "ZV"
	415	"@internal
	416	A microMIPS memory operand for use with the SB16 insn."
	417	(and (match_code "mem")
	418	(match_operand 0 "sb16_operand")))
	419
	420	(define_memory_constraint "ZW"
	421	"@internal
	422	A microMIPS memory operand for use with the LBU16 insn."
	423	(and (match_code "mem")
	424	(match_operand 0 "lbu16_operand")))
	425