]>
Commit | Line | Data |
---|---|---|
118ea793 CF |
1 | (define_constants |
2 | [(CCDSP_PO_REGNUM 182) | |
3 | (CCDSP_SC_REGNUM 183) | |
4 | (CCDSP_CA_REGNUM 184) | |
5 | (CCDSP_OU_REGNUM 185) | |
6 | (CCDSP_CC_REGNUM 186) | |
7 | (CCDSP_EF_REGNUM 187)]) | |
8 | ||
3abcb3a7 | 9 | ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE. |
254d1646 RS |
10 | (define_mode_iterator DSP [(SI "ISA_HAS_DSP") |
11 | (V2HI "ISA_HAS_DSP") | |
12 | (V4QI "ISA_HAS_DSP")]) | |
3abcb3a7 HPN |
13 | |
14 | ;; This mode iterator allows v2hi, v4qi for vector/SIMD data. | |
254d1646 RS |
15 | (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP") |
16 | (V4QI "ISA_HAS_DSP")]) | |
3abcb3a7 HPN |
17 | |
18 | ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data. | |
254d1646 RS |
19 | (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP") |
20 | (V2HI "ISA_HAS_DSP")]) | |
118ea793 CF |
21 | |
22 | ;; DSP instructions use q for fixed-point data, and u for integer in the infix. | |
23 | (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) | |
24 | ||
25 | ;; DSP instructions use nothing for fixed-point data, and u for integer in | |
26 | ;; the infix. | |
27 | (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")]) | |
28 | ||
29 | ;; DSP instructions use w, ph, qb in the postfix. | |
30 | (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")]) | |
31 | ||
32 | ;; DSP shift masks for SI, V2HI, V4QI. | |
33 | (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")]) | |
34 | ||
35 | ;; MIPS DSP ASE Revision 0.98 3/24/2005 | |
36 | ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic | |
37 | ;; ADDQ* | |
38 | (define_insn "add<DSPV:mode>3" | |
39 | [(parallel | |
40 | [(set (match_operand:DSPV 0 "register_operand" "=d") | |
41 | (plus:DSPV (match_operand:DSPV 1 "register_operand" "d") | |
42 | (match_operand:DSPV 2 "register_operand" "d"))) | |
43 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
44 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] | |
45 | "" | |
46 | "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" | |
47 | [(set_attr "type" "arith") | |
48 | (set_attr "mode" "SI")]) | |
49 | ||
50 | (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" | |
51 | [(parallel | |
52 | [(set (match_operand:DSP 0 "register_operand" "=d") | |
53 | (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") | |
54 | (match_operand:DSP 2 "register_operand" "d")] | |
55 | UNSPEC_ADDQ_S)) | |
56 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
57 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] | |
58 | "" | |
59 | "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" | |
60 | [(set_attr "type" "arith") | |
61 | (set_attr "mode" "SI")]) | |
62 | ||
63 | ;; SUBQ* | |
64 | (define_insn "sub<DSPV:mode>3" | |
65 | [(parallel | |
66 | [(set (match_operand:DSPV 0 "register_operand" "=d") | |
67 | (minus:DSPV (match_operand:DSPV 1 "register_operand" "d") | |
68 | (match_operand:DSPV 2 "register_operand" "d"))) | |
69 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
70 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] | |
254d1646 | 71 | "ISA_HAS_DSP" |
118ea793 CF |
72 | "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" |
73 | [(set_attr "type" "arith") | |
74 | (set_attr "mode" "SI")]) | |
75 | ||
76 | (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" | |
77 | [(parallel | |
78 | [(set (match_operand:DSP 0 "register_operand" "=d") | |
79 | (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") | |
80 | (match_operand:DSP 2 "register_operand" "d")] | |
81 | UNSPEC_SUBQ_S)) | |
82 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
83 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] | |
254d1646 | 84 | "ISA_HAS_DSP" |
118ea793 CF |
85 | "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" |
86 | [(set_attr "type" "arith") | |
87 | (set_attr "mode" "SI")]) | |
88 | ||
89 | ;; ADDSC | |
90 | (define_insn "mips_addsc" | |
91 | [(parallel | |
92 | [(set (match_operand:SI 0 "register_operand" "=d") | |
93 | (unspec:SI [(match_operand:SI 1 "register_operand" "d") | |
94 | (match_operand:SI 2 "register_operand" "d")] | |
95 | UNSPEC_ADDSC)) | |
96 | (set (reg:CCDSP CCDSP_CA_REGNUM) | |
97 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] | |
254d1646 | 98 | "ISA_HAS_DSP" |
118ea793 CF |
99 | "addsc\t%0,%1,%2" |
100 | [(set_attr "type" "arith") | |
101 | (set_attr "mode" "SI")]) | |
102 | ||
103 | ;; ADDWC | |
104 | (define_insn "mips_addwc" | |
105 | [(parallel | |
106 | [(set (match_operand:SI 0 "register_operand" "=d") | |
107 | (unspec:SI [(match_operand:SI 1 "register_operand" "d") | |
108 | (match_operand:SI 2 "register_operand" "d") | |
109 | (reg:CCDSP CCDSP_CA_REGNUM)] | |
110 | UNSPEC_ADDWC)) | |
111 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
112 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] | |
254d1646 | 113 | "ISA_HAS_DSP" |
118ea793 CF |
114 | "addwc\t%0,%1,%2" |
115 | [(set_attr "type" "arith") | |
116 | (set_attr "mode" "SI")]) | |
117 | ||
118 | ;; MODSUB | |
119 | (define_insn "mips_modsub" | |
120 | [(set (match_operand:SI 0 "register_operand" "=d") | |
121 | (unspec:SI [(match_operand:SI 1 "register_operand" "d") | |
122 | (match_operand:SI 2 "register_operand" "d")] | |
123 | UNSPEC_MODSUB))] | |
254d1646 | 124 | "ISA_HAS_DSP" |
118ea793 CF |
125 | "modsub\t%0,%1,%2" |
126 | [(set_attr "type" "arith") | |
127 | (set_attr "mode" "SI")]) | |
128 | ||
129 | ;; RADDU* | |
130 | (define_insn "mips_raddu_w_qb" | |
131 | [(set (match_operand:SI 0 "register_operand" "=d") | |
132 | (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] | |
133 | UNSPEC_RADDU_W_QB))] | |
254d1646 | 134 | "ISA_HAS_DSP" |
118ea793 CF |
135 | "raddu.w.qb\t%0,%1" |
136 | [(set_attr "type" "arith") | |
137 | (set_attr "mode" "SI")]) | |
138 | ||
139 | ;; ABSQ* | |
140 | (define_insn "mips_absq_s_<DSPQ:dspfmt2>" | |
141 | [(parallel | |
142 | [(set (match_operand:DSPQ 0 "register_operand" "=d") | |
143 | (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] | |
144 | UNSPEC_ABSQ_S)) | |
145 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
146 | (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] | |
254d1646 | 147 | "ISA_HAS_DSP" |
118ea793 CF |
148 | "absq_s.<DSPQ:dspfmt2>\t%0,%1" |
149 | [(set_attr "type" "arith") | |
150 | (set_attr "mode" "SI")]) | |
151 | ||
152 | ;; PRECRQ* | |
153 | (define_insn "mips_precrq_qb_ph" | |
154 | [(set (match_operand:V4QI 0 "register_operand" "=d") | |
155 | (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") | |
156 | (match_operand:V2HI 2 "register_operand" "d")] | |
157 | UNSPEC_PRECRQ_QB_PH))] | |
254d1646 | 158 | "ISA_HAS_DSP" |
118ea793 CF |
159 | "precrq.qb.ph\t%0,%1,%2" |
160 | [(set_attr "type" "arith") | |
161 | (set_attr "mode" "SI")]) | |
162 | ||
163 | (define_insn "mips_precrq_ph_w" | |
164 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
165 | (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") | |
166 | (match_operand:SI 2 "register_operand" "d")] | |
167 | UNSPEC_PRECRQ_PH_W))] | |
254d1646 | 168 | "ISA_HAS_DSP" |
118ea793 CF |
169 | "precrq.ph.w\t%0,%1,%2" |
170 | [(set_attr "type" "arith") | |
171 | (set_attr "mode" "SI")]) | |
172 | ||
173 | (define_insn "mips_precrq_rs_ph_w" | |
174 | [(parallel | |
175 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
176 | (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") | |
177 | (match_operand:SI 2 "register_operand" "d")] | |
178 | UNSPEC_PRECRQ_RS_PH_W)) | |
179 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
180 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] | |
181 | UNSPEC_PRECRQ_RS_PH_W))])] | |
254d1646 | 182 | "ISA_HAS_DSP" |
118ea793 CF |
183 | "precrq_rs.ph.w\t%0,%1,%2" |
184 | [(set_attr "type" "arith") | |
185 | (set_attr "mode" "SI")]) | |
186 | ||
187 | ;; PRECRQU* | |
188 | (define_insn "mips_precrqu_s_qb_ph" | |
189 | [(parallel | |
190 | [(set (match_operand:V4QI 0 "register_operand" "=d") | |
191 | (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") | |
192 | (match_operand:V2HI 2 "register_operand" "d")] | |
193 | UNSPEC_PRECRQU_S_QB_PH)) | |
194 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
195 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] | |
196 | UNSPEC_PRECRQU_S_QB_PH))])] | |
254d1646 | 197 | "ISA_HAS_DSP" |
118ea793 CF |
198 | "precrqu_s.qb.ph\t%0,%1,%2" |
199 | [(set_attr "type" "arith") | |
200 | (set_attr "mode" "SI")]) | |
201 | ||
202 | ;; PRECEQ* | |
203 | (define_insn "mips_preceq_w_phl" | |
204 | [(set (match_operand:SI 0 "register_operand" "=d") | |
205 | (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] | |
206 | UNSPEC_PRECEQ_W_PHL))] | |
254d1646 | 207 | "ISA_HAS_DSP" |
118ea793 CF |
208 | "preceq.w.phl\t%0,%1" |
209 | [(set_attr "type" "arith") | |
210 | (set_attr "mode" "SI")]) | |
211 | ||
212 | (define_insn "mips_preceq_w_phr" | |
213 | [(set (match_operand:SI 0 "register_operand" "=d") | |
214 | (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] | |
215 | UNSPEC_PRECEQ_W_PHR))] | |
254d1646 | 216 | "ISA_HAS_DSP" |
118ea793 CF |
217 | "preceq.w.phr\t%0,%1" |
218 | [(set_attr "type" "arith") | |
219 | (set_attr "mode" "SI")]) | |
220 | ||
221 | ;; PRECEQU* | |
222 | (define_insn "mips_precequ_ph_qbl" | |
223 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
224 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
225 | UNSPEC_PRECEQU_PH_QBL))] | |
254d1646 | 226 | "ISA_HAS_DSP" |
118ea793 CF |
227 | "precequ.ph.qbl\t%0,%1" |
228 | [(set_attr "type" "arith") | |
229 | (set_attr "mode" "SI")]) | |
230 | ||
231 | (define_insn "mips_precequ_ph_qbr" | |
232 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
233 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
234 | UNSPEC_PRECEQU_PH_QBR))] | |
254d1646 | 235 | "ISA_HAS_DSP" |
118ea793 CF |
236 | "precequ.ph.qbr\t%0,%1" |
237 | [(set_attr "type" "arith") | |
238 | (set_attr "mode" "SI")]) | |
239 | ||
240 | (define_insn "mips_precequ_ph_qbla" | |
241 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
242 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
243 | UNSPEC_PRECEQU_PH_QBLA))] | |
254d1646 | 244 | "ISA_HAS_DSP" |
118ea793 CF |
245 | "precequ.ph.qbla\t%0,%1" |
246 | [(set_attr "type" "arith") | |
247 | (set_attr "mode" "SI")]) | |
248 | ||
249 | (define_insn "mips_precequ_ph_qbra" | |
250 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
251 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
252 | UNSPEC_PRECEQU_PH_QBRA))] | |
254d1646 | 253 | "ISA_HAS_DSP" |
118ea793 CF |
254 | "precequ.ph.qbra\t%0,%1" |
255 | [(set_attr "type" "arith") | |
256 | (set_attr "mode" "SI")]) | |
257 | ||
258 | ;; PRECEU* | |
259 | (define_insn "mips_preceu_ph_qbl" | |
260 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
261 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
262 | UNSPEC_PRECEU_PH_QBL))] | |
254d1646 | 263 | "ISA_HAS_DSP" |
118ea793 CF |
264 | "preceu.ph.qbl\t%0,%1" |
265 | [(set_attr "type" "arith") | |
266 | (set_attr "mode" "SI")]) | |
267 | ||
268 | (define_insn "mips_preceu_ph_qbr" | |
269 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
270 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
271 | UNSPEC_PRECEU_PH_QBR))] | |
254d1646 | 272 | "ISA_HAS_DSP" |
118ea793 CF |
273 | "preceu.ph.qbr\t%0,%1" |
274 | [(set_attr "type" "arith") | |
275 | (set_attr "mode" "SI")]) | |
276 | ||
277 | (define_insn "mips_preceu_ph_qbla" | |
278 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
279 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
280 | UNSPEC_PRECEU_PH_QBLA))] | |
254d1646 | 281 | "ISA_HAS_DSP" |
118ea793 CF |
282 | "preceu.ph.qbla\t%0,%1" |
283 | [(set_attr "type" "arith") | |
284 | (set_attr "mode" "SI")]) | |
285 | ||
286 | (define_insn "mips_preceu_ph_qbra" | |
287 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
288 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] | |
289 | UNSPEC_PRECEU_PH_QBRA))] | |
254d1646 | 290 | "ISA_HAS_DSP" |
118ea793 CF |
291 | "preceu.ph.qbra\t%0,%1" |
292 | [(set_attr "type" "arith") | |
293 | (set_attr "mode" "SI")]) | |
294 | ||
295 | ;; Table 2-2. MIPS DSP ASE Instructions: Shift | |
296 | ;; SHLL* | |
297 | (define_insn "mips_shll_<DSPV:dspfmt2>" | |
298 | [(parallel | |
299 | [(set (match_operand:DSPV 0 "register_operand" "=d,d") | |
300 | (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") | |
301 | (match_operand:SI 2 "arith_operand" "I,d")] | |
302 | UNSPEC_SHLL)) | |
303 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
304 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])] | |
254d1646 | 305 | "ISA_HAS_DSP" |
118ea793 CF |
306 | { |
307 | if (which_alternative == 0) | |
308 | { | |
309 | if (INTVAL (operands[2]) | |
310 | & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>) | |
311 | operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>); | |
312 | return "shll.<DSPV:dspfmt2>\t%0,%1,%2"; | |
313 | } | |
314 | return "shllv.<DSPV:dspfmt2>\t%0,%1,%2"; | |
315 | } | |
316 | [(set_attr "type" "shift") | |
317 | (set_attr "mode" "SI")]) | |
318 | ||
319 | (define_insn "mips_shll_s_<DSPQ:dspfmt2>" | |
320 | [(parallel | |
321 | [(set (match_operand:DSPQ 0 "register_operand" "=d,d") | |
322 | (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") | |
323 | (match_operand:SI 2 "arith_operand" "I,d")] | |
324 | UNSPEC_SHLL_S)) | |
325 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
326 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])] | |
254d1646 | 327 | "ISA_HAS_DSP" |
118ea793 CF |
328 | { |
329 | if (which_alternative == 0) | |
330 | { | |
331 | if (INTVAL (operands[2]) | |
332 | & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) | |
333 | operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); | |
334 | return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2"; | |
335 | } | |
336 | return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2"; | |
337 | } | |
338 | [(set_attr "type" "shift") | |
339 | (set_attr "mode" "SI")]) | |
340 | ||
341 | ;; SHRL* | |
342 | (define_insn "mips_shrl_qb" | |
343 | [(set (match_operand:V4QI 0 "register_operand" "=d,d") | |
344 | (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") | |
345 | (match_operand:SI 2 "arith_operand" "I,d")] | |
346 | UNSPEC_SHRL_QB))] | |
254d1646 | 347 | "ISA_HAS_DSP" |
118ea793 CF |
348 | { |
349 | if (which_alternative == 0) | |
350 | { | |
351 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7) | |
352 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7); | |
353 | return "shrl.qb\t%0,%1,%2"; | |
354 | } | |
355 | return "shrlv.qb\t%0,%1,%2"; | |
356 | } | |
357 | [(set_attr "type" "shift") | |
358 | (set_attr "mode" "SI")]) | |
359 | ||
360 | ;; SHRA* | |
361 | (define_insn "mips_shra_ph" | |
362 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
363 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") | |
364 | (match_operand:SI 2 "arith_operand" "I,d")] | |
365 | UNSPEC_SHRA_PH))] | |
254d1646 | 366 | "ISA_HAS_DSP" |
118ea793 CF |
367 | { |
368 | if (which_alternative == 0) | |
369 | { | |
370 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf) | |
371 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf); | |
372 | return "shra.ph\t%0,%1,%2"; | |
373 | } | |
374 | return "shrav.ph\t%0,%1,%2"; | |
375 | } | |
376 | [(set_attr "type" "shift") | |
377 | (set_attr "mode" "SI")]) | |
378 | ||
379 | (define_insn "mips_shra_r_<DSPQ:dspfmt2>" | |
380 | [(set (match_operand:DSPQ 0 "register_operand" "=d,d") | |
381 | (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") | |
382 | (match_operand:SI 2 "arith_operand" "I,d")] | |
383 | UNSPEC_SHRA_R))] | |
254d1646 | 384 | "ISA_HAS_DSP" |
118ea793 CF |
385 | { |
386 | if (which_alternative == 0) | |
387 | { | |
388 | if (INTVAL (operands[2]) | |
389 | & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) | |
390 | operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); | |
391 | return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2"; | |
392 | } | |
393 | return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2"; | |
394 | } | |
395 | [(set_attr "type" "shift") | |
396 | (set_attr "mode" "SI")]) | |
397 | ||
398 | ;; Table 2-3. MIPS DSP ASE Instructions: Multiply | |
399 | ;; MULEU* | |
400 | (define_insn "mips_muleu_s_ph_qbl" | |
401 | [(parallel | |
402 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
403 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") | |
404 | (match_operand:V2HI 2 "register_operand" "d")] | |
405 | UNSPEC_MULEU_S_PH_QBL)) | |
406 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
407 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) | |
408 | (clobber (match_scratch:DI 3 "=x"))])] | |
254d1646 | 409 | "ISA_HAS_DSP" |
118ea793 CF |
410 | "muleu_s.ph.qbl\t%0,%1,%2" |
411 | [(set_attr "type" "imul3") | |
412 | (set_attr "mode" "SI")]) | |
413 | ||
414 | (define_insn "mips_muleu_s_ph_qbr" | |
415 | [(parallel | |
416 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
417 | (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") | |
418 | (match_operand:V2HI 2 "register_operand" "d")] | |
419 | UNSPEC_MULEU_S_PH_QBR)) | |
420 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
421 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) | |
422 | (clobber (match_scratch:DI 3 "=x"))])] | |
254d1646 | 423 | "ISA_HAS_DSP" |
118ea793 CF |
424 | "muleu_s.ph.qbr\t%0,%1,%2" |
425 | [(set_attr "type" "imul3") | |
426 | (set_attr "mode" "SI")]) | |
427 | ||
428 | ;; MULQ* | |
429 | (define_insn "mips_mulq_rs_ph" | |
430 | [(parallel | |
431 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
432 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
433 | (match_operand:V2HI 2 "register_operand" "d")] | |
434 | UNSPEC_MULQ_RS_PH)) | |
435 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
436 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) | |
437 | (clobber (match_scratch:DI 3 "=x"))])] | |
254d1646 | 438 | "ISA_HAS_DSP" |
118ea793 CF |
439 | "mulq_rs.ph\t%0,%1,%2" |
440 | [(set_attr "type" "imul3") | |
441 | (set_attr "mode" "SI")]) | |
442 | ||
443 | ;; MULEQ* | |
444 | (define_insn "mips_muleq_s_w_phl" | |
445 | [(parallel | |
446 | [(set (match_operand:SI 0 "register_operand" "=d") | |
447 | (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") | |
448 | (match_operand:V2HI 2 "register_operand" "d")] | |
449 | UNSPEC_MULEQ_S_W_PHL)) | |
450 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
451 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) | |
452 | (clobber (match_scratch:DI 3 "=x"))])] | |
254d1646 | 453 | "ISA_HAS_DSP" |
118ea793 CF |
454 | "muleq_s.w.phl\t%0,%1,%2" |
455 | [(set_attr "type" "imul3") | |
456 | (set_attr "mode" "SI")]) | |
457 | ||
458 | (define_insn "mips_muleq_s_w_phr" | |
459 | [(parallel | |
460 | [(set (match_operand:SI 0 "register_operand" "=d") | |
461 | (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") | |
462 | (match_operand:V2HI 2 "register_operand" "d")] | |
463 | UNSPEC_MULEQ_S_W_PHR)) | |
464 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
465 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) | |
466 | (clobber (match_scratch:DI 3 "=x"))])] | |
254d1646 | 467 | "ISA_HAS_DSP" |
118ea793 CF |
468 | "muleq_s.w.phr\t%0,%1,%2" |
469 | [(set_attr "type" "imul3") | |
470 | (set_attr "mode" "SI")]) | |
471 | ||
472 | ;; DPAU* | |
473 | (define_insn "mips_dpau_h_qbl" | |
474 | [(set (match_operand:DI 0 "register_operand" "=a") | |
475 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
476 | (match_operand:V4QI 2 "register_operand" "d") | |
477 | (match_operand:V4QI 3 "register_operand" "d")] | |
478 | UNSPEC_DPAU_H_QBL))] | |
254d1646 | 479 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
480 | "dpau.h.qbl\t%q0,%2,%3" |
481 | [(set_attr "type" "imadd") | |
482 | (set_attr "mode" "SI")]) | |
483 | ||
484 | (define_insn "mips_dpau_h_qbr" | |
485 | [(set (match_operand:DI 0 "register_operand" "=a") | |
486 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
487 | (match_operand:V4QI 2 "register_operand" "d") | |
488 | (match_operand:V4QI 3 "register_operand" "d")] | |
489 | UNSPEC_DPAU_H_QBR))] | |
254d1646 | 490 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
491 | "dpau.h.qbr\t%q0,%2,%3" |
492 | [(set_attr "type" "imadd") | |
493 | (set_attr "mode" "SI")]) | |
494 | ||
495 | ;; DPSU* | |
496 | (define_insn "mips_dpsu_h_qbl" | |
497 | [(set (match_operand:DI 0 "register_operand" "=a") | |
498 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
499 | (match_operand:V4QI 2 "register_operand" "d") | |
500 | (match_operand:V4QI 3 "register_operand" "d")] | |
501 | UNSPEC_DPSU_H_QBL))] | |
254d1646 | 502 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
503 | "dpsu.h.qbl\t%q0,%2,%3" |
504 | [(set_attr "type" "imadd") | |
505 | (set_attr "mode" "SI")]) | |
506 | ||
507 | (define_insn "mips_dpsu_h_qbr" | |
508 | [(set (match_operand:DI 0 "register_operand" "=a") | |
509 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
510 | (match_operand:V4QI 2 "register_operand" "d") | |
511 | (match_operand:V4QI 3 "register_operand" "d")] | |
512 | UNSPEC_DPSU_H_QBR))] | |
254d1646 | 513 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
514 | "dpsu.h.qbr\t%q0,%2,%3" |
515 | [(set_attr "type" "imadd") | |
516 | (set_attr "mode" "SI")]) | |
517 | ||
518 | ;; DPAQ* | |
519 | (define_insn "mips_dpaq_s_w_ph" | |
520 | [(parallel | |
521 | [(set (match_operand:DI 0 "register_operand" "=a") | |
522 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
523 | (match_operand:V2HI 2 "register_operand" "d") | |
524 | (match_operand:V2HI 3 "register_operand" "d")] | |
525 | UNSPEC_DPAQ_S_W_PH)) | |
526 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
527 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
528 | UNSPEC_DPAQ_S_W_PH))])] | |
254d1646 | 529 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
530 | "dpaq_s.w.ph\t%q0,%2,%3" |
531 | [(set_attr "type" "imadd") | |
532 | (set_attr "mode" "SI")]) | |
533 | ||
534 | ;; DPSQ* | |
535 | (define_insn "mips_dpsq_s_w_ph" | |
536 | [(parallel | |
537 | [(set (match_operand:DI 0 "register_operand" "=a") | |
538 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
539 | (match_operand:V2HI 2 "register_operand" "d") | |
540 | (match_operand:V2HI 3 "register_operand" "d")] | |
541 | UNSPEC_DPSQ_S_W_PH)) | |
542 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
543 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
544 | UNSPEC_DPSQ_S_W_PH))])] | |
254d1646 | 545 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
546 | "dpsq_s.w.ph\t%q0,%2,%3" |
547 | [(set_attr "type" "imadd") | |
548 | (set_attr "mode" "SI")]) | |
549 | ||
550 | ;; MULSAQ* | |
551 | (define_insn "mips_mulsaq_s_w_ph" | |
552 | [(parallel | |
553 | [(set (match_operand:DI 0 "register_operand" "=a") | |
554 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
555 | (match_operand:V2HI 2 "register_operand" "d") | |
556 | (match_operand:V2HI 3 "register_operand" "d")] | |
557 | UNSPEC_MULSAQ_S_W_PH)) | |
558 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
559 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
560 | UNSPEC_MULSAQ_S_W_PH))])] | |
254d1646 | 561 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
562 | "mulsaq_s.w.ph\t%q0,%2,%3" |
563 | [(set_attr "type" "imadd") | |
564 | (set_attr "mode" "SI")]) | |
565 | ||
566 | ;; DPAQ* | |
567 | (define_insn "mips_dpaq_sa_l_w" | |
568 | [(parallel | |
569 | [(set (match_operand:DI 0 "register_operand" "=a") | |
570 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
571 | (match_operand:SI 2 "register_operand" "d") | |
572 | (match_operand:SI 3 "register_operand" "d")] | |
573 | UNSPEC_DPAQ_SA_L_W)) | |
574 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
575 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
576 | UNSPEC_DPAQ_SA_L_W))])] | |
254d1646 | 577 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
578 | "dpaq_sa.l.w\t%q0,%2,%3" |
579 | [(set_attr "type" "imadd") | |
580 | (set_attr "mode" "SI")]) | |
581 | ||
582 | ;; DPSQ* | |
583 | (define_insn "mips_dpsq_sa_l_w" | |
584 | [(parallel | |
585 | [(set (match_operand:DI 0 "register_operand" "=a") | |
586 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
587 | (match_operand:SI 2 "register_operand" "d") | |
588 | (match_operand:SI 3 "register_operand" "d")] | |
589 | UNSPEC_DPSQ_SA_L_W)) | |
590 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
591 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
592 | UNSPEC_DPSQ_SA_L_W))])] | |
254d1646 | 593 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
594 | "dpsq_sa.l.w\t%q0,%2,%3" |
595 | [(set_attr "type" "imadd") | |
596 | (set_attr "mode" "SI")]) | |
597 | ||
598 | ;; MAQ* | |
599 | (define_insn "mips_maq_s_w_phl" | |
600 | [(parallel | |
601 | [(set (match_operand:DI 0 "register_operand" "=a") | |
602 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
603 | (match_operand:V2HI 2 "register_operand" "d") | |
604 | (match_operand:V2HI 3 "register_operand" "d")] | |
605 | UNSPEC_MAQ_S_W_PHL)) | |
606 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
607 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
608 | UNSPEC_MAQ_S_W_PHL))])] | |
254d1646 | 609 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
610 | "maq_s.w.phl\t%q0,%2,%3" |
611 | [(set_attr "type" "imadd") | |
612 | (set_attr "mode" "SI")]) | |
613 | ||
614 | (define_insn "mips_maq_s_w_phr" | |
615 | [(parallel | |
616 | [(set (match_operand:DI 0 "register_operand" "=a") | |
617 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
618 | (match_operand:V2HI 2 "register_operand" "d") | |
619 | (match_operand:V2HI 3 "register_operand" "d")] | |
620 | UNSPEC_MAQ_S_W_PHR)) | |
621 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
622 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
623 | UNSPEC_MAQ_S_W_PHR))])] | |
254d1646 | 624 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
625 | "maq_s.w.phr\t%q0,%2,%3" |
626 | [(set_attr "type" "imadd") | |
627 | (set_attr "mode" "SI")]) | |
628 | ||
629 | ;; MAQ_SA* | |
630 | (define_insn "mips_maq_sa_w_phl" | |
631 | [(parallel | |
632 | [(set (match_operand:DI 0 "register_operand" "=a") | |
633 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
634 | (match_operand:V2HI 2 "register_operand" "d") | |
635 | (match_operand:V2HI 3 "register_operand" "d")] | |
636 | UNSPEC_MAQ_SA_W_PHL)) | |
637 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
638 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
639 | UNSPEC_MAQ_SA_W_PHL))])] | |
254d1646 | 640 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
641 | "maq_sa.w.phl\t%q0,%2,%3" |
642 | [(set_attr "type" "imadd") | |
643 | (set_attr "mode" "SI")]) | |
644 | ||
645 | (define_insn "mips_maq_sa_w_phr" | |
646 | [(parallel | |
647 | [(set (match_operand:DI 0 "register_operand" "=a") | |
648 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
649 | (match_operand:V2HI 2 "register_operand" "d") | |
650 | (match_operand:V2HI 3 "register_operand" "d")] | |
651 | UNSPEC_MAQ_SA_W_PHR)) | |
652 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
653 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
654 | UNSPEC_MAQ_SA_W_PHR))])] | |
254d1646 | 655 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
656 | "maq_sa.w.phr\t%q0,%2,%3" |
657 | [(set_attr "type" "imadd") | |
658 | (set_attr "mode" "SI")]) | |
659 | ||
660 | ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation | |
661 | ;; BITREV | |
662 | (define_insn "mips_bitrev" | |
663 | [(set (match_operand:SI 0 "register_operand" "=d") | |
664 | (unspec:SI [(match_operand:SI 1 "register_operand" "d")] | |
665 | UNSPEC_BITREV))] | |
254d1646 | 666 | "ISA_HAS_DSP" |
118ea793 CF |
667 | "bitrev\t%0,%1" |
668 | [(set_attr "type" "arith") | |
669 | (set_attr "mode" "SI")]) | |
670 | ||
671 | ;; INSV | |
672 | (define_insn "mips_insv" | |
673 | [(set (match_operand:SI 0 "register_operand" "=d") | |
674 | (unspec:SI [(match_operand:SI 1 "register_operand" "0") | |
675 | (match_operand:SI 2 "register_operand" "d") | |
676 | (reg:CCDSP CCDSP_SC_REGNUM) | |
677 | (reg:CCDSP CCDSP_PO_REGNUM)] | |
678 | UNSPEC_INSV))] | |
254d1646 | 679 | "ISA_HAS_DSP" |
118ea793 CF |
680 | "insv\t%0,%2" |
681 | [(set_attr "type" "arith") | |
682 | (set_attr "mode" "SI")]) | |
683 | ||
684 | ;; REPL* | |
685 | (define_insn "mips_repl_qb" | |
686 | [(set (match_operand:V4QI 0 "register_operand" "=d,d") | |
687 | (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] | |
688 | UNSPEC_REPL_QB))] | |
254d1646 | 689 | "ISA_HAS_DSP" |
118ea793 CF |
690 | { |
691 | if (which_alternative == 0) | |
692 | { | |
693 | if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff) | |
694 | operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); | |
695 | return "repl.qb\t%0,%1"; | |
696 | } | |
697 | return "replv.qb\t%0,%1"; | |
698 | } | |
699 | [(set_attr "type" "arith") | |
700 | (set_attr "mode" "SI")]) | |
701 | ||
702 | (define_insn "mips_repl_ph" | |
703 | [(set (match_operand:V2HI 0 "register_operand" "=d,d") | |
704 | (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] | |
705 | UNSPEC_REPL_PH))] | |
254d1646 | 706 | "ISA_HAS_DSP" |
118ea793 CF |
707 | "@ |
708 | repl.ph\t%0,%1 | |
709 | replv.ph\t%0,%1" | |
710 | [(set_attr "type" "arith") | |
711 | (set_attr "mode" "SI")]) | |
712 | ||
713 | ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick | |
714 | ;; CMPU.* CMP.* | |
715 | (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>" | |
716 | [(set (reg:CCDSP CCDSP_CC_REGNUM) | |
717 | (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") | |
718 | (match_operand:DSPV 1 "register_operand" "d") | |
719 | (reg:CCDSP CCDSP_CC_REGNUM)] | |
720 | UNSPEC_CMP_EQ))] | |
254d1646 | 721 | "ISA_HAS_DSP" |
118ea793 CF |
722 | "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1" |
723 | [(set_attr "type" "arith") | |
724 | (set_attr "mode" "SI")]) | |
725 | ||
726 | (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>" | |
727 | [(set (reg:CCDSP CCDSP_CC_REGNUM) | |
728 | (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") | |
729 | (match_operand:DSPV 1 "register_operand" "d") | |
730 | (reg:CCDSP CCDSP_CC_REGNUM)] | |
731 | UNSPEC_CMP_LT))] | |
254d1646 | 732 | "ISA_HAS_DSP" |
118ea793 CF |
733 | "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1" |
734 | [(set_attr "type" "arith") | |
735 | (set_attr "mode" "SI")]) | |
736 | ||
737 | (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>" | |
738 | [(set (reg:CCDSP CCDSP_CC_REGNUM) | |
739 | (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") | |
740 | (match_operand:DSPV 1 "register_operand" "d") | |
741 | (reg:CCDSP CCDSP_CC_REGNUM)] | |
742 | UNSPEC_CMP_LE))] | |
254d1646 | 743 | "ISA_HAS_DSP" |
118ea793 CF |
744 | "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1" |
745 | [(set_attr "type" "arith") | |
746 | (set_attr "mode" "SI")]) | |
747 | ||
748 | (define_insn "mips_cmpgu_eq_qb" | |
749 | [(set (match_operand:SI 0 "register_operand" "=d") | |
750 | (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") | |
751 | (match_operand:V4QI 2 "register_operand" "d")] | |
752 | UNSPEC_CMPGU_EQ_QB))] | |
254d1646 | 753 | "ISA_HAS_DSP" |
118ea793 CF |
754 | "cmpgu.eq.qb\t%0,%1,%2" |
755 | [(set_attr "type" "arith") | |
756 | (set_attr "mode" "SI")]) | |
757 | ||
758 | (define_insn "mips_cmpgu_lt_qb" | |
759 | [(set (match_operand:SI 0 "register_operand" "=d") | |
760 | (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") | |
761 | (match_operand:V4QI 2 "register_operand" "d")] | |
762 | UNSPEC_CMPGU_LT_QB))] | |
254d1646 | 763 | "ISA_HAS_DSP" |
118ea793 CF |
764 | "cmpgu.lt.qb\t%0,%1,%2" |
765 | [(set_attr "type" "arith") | |
766 | (set_attr "mode" "SI")]) | |
767 | ||
768 | (define_insn "mips_cmpgu_le_qb" | |
769 | [(set (match_operand:SI 0 "register_operand" "=d") | |
770 | (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") | |
771 | (match_operand:V4QI 2 "register_operand" "d")] | |
772 | UNSPEC_CMPGU_LE_QB))] | |
254d1646 | 773 | "ISA_HAS_DSP" |
118ea793 CF |
774 | "cmpgu.le.qb\t%0,%1,%2" |
775 | [(set_attr "type" "arith") | |
776 | (set_attr "mode" "SI")]) | |
777 | ||
778 | ;; PICK* | |
779 | (define_insn "mips_pick_<DSPV:dspfmt2>" | |
780 | [(set (match_operand:DSPV 0 "register_operand" "=d") | |
781 | (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d") | |
782 | (match_operand:DSPV 2 "register_operand" "d") | |
783 | (reg:CCDSP CCDSP_CC_REGNUM)] | |
784 | UNSPEC_PICK))] | |
254d1646 | 785 | "ISA_HAS_DSP" |
118ea793 CF |
786 | "pick.<DSPV:dspfmt2>\t%0,%1,%2" |
787 | [(set_attr "type" "arith") | |
788 | (set_attr "mode" "SI")]) | |
789 | ||
790 | ;; PACKRL* | |
791 | (define_insn "mips_packrl_ph" | |
792 | [(set (match_operand:V2HI 0 "register_operand" "=d") | |
793 | (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") | |
794 | (match_operand:V2HI 2 "register_operand" "d")] | |
795 | UNSPEC_PACKRL_PH))] | |
254d1646 | 796 | "ISA_HAS_DSP" |
118ea793 CF |
797 | "packrl.ph\t%0,%1,%2" |
798 | [(set_attr "type" "arith") | |
799 | (set_attr "mode" "SI")]) | |
800 | ||
801 | ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access | |
802 | ;; EXTR* | |
803 | (define_insn "mips_extr_w" | |
804 | [(parallel | |
805 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
806 | (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") | |
807 | (match_operand:SI 2 "arith_operand" "I,d")] | |
808 | UNSPEC_EXTR_W)) | |
809 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
810 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])] | |
254d1646 | 811 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
812 | { |
813 | if (which_alternative == 0) | |
814 | { | |
815 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) | |
816 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
817 | return "extr.w\t%0,%q1,%2"; | |
818 | } | |
819 | return "extrv.w\t%0,%q1,%2"; | |
820 | } | |
821 | [(set_attr "type" "mfhilo") | |
822 | (set_attr "mode" "SI")]) | |
823 | ||
824 | (define_insn "mips_extr_r_w" | |
825 | [(parallel | |
826 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
827 | (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") | |
828 | (match_operand:SI 2 "arith_operand" "I,d")] | |
829 | UNSPEC_EXTR_R_W)) | |
830 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
831 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])] | |
254d1646 | 832 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
833 | { |
834 | if (which_alternative == 0) | |
835 | { | |
836 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) | |
837 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
838 | return "extr_r.w\t%0,%q1,%2"; | |
839 | } | |
840 | return "extrv_r.w\t%0,%q1,%2"; | |
841 | } | |
842 | [(set_attr "type" "mfhilo") | |
843 | (set_attr "mode" "SI")]) | |
844 | ||
845 | (define_insn "mips_extr_rs_w" | |
846 | [(parallel | |
847 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
848 | (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") | |
849 | (match_operand:SI 2 "arith_operand" "I,d")] | |
850 | UNSPEC_EXTR_RS_W)) | |
851 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
852 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])] | |
254d1646 | 853 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
854 | { |
855 | if (which_alternative == 0) | |
856 | { | |
857 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) | |
858 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
859 | return "extr_rs.w\t%0,%q1,%2"; | |
860 | } | |
861 | return "extrv_rs.w\t%0,%q1,%2"; | |
862 | } | |
863 | [(set_attr "type" "mfhilo") | |
864 | (set_attr "mode" "SI")]) | |
865 | ||
866 | ;; EXTR*_S.H | |
867 | (define_insn "mips_extr_s_h" | |
868 | [(parallel | |
869 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
870 | (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") | |
871 | (match_operand:SI 2 "arith_operand" "I,d")] | |
872 | UNSPEC_EXTR_S_H)) | |
873 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
874 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])] | |
254d1646 | 875 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
876 | { |
877 | if (which_alternative == 0) | |
878 | { | |
879 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) | |
880 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
881 | return "extr_s.h\t%0,%q1,%2"; | |
882 | } | |
883 | return "extrv_s.h\t%0,%q1,%2"; | |
884 | } | |
885 | [(set_attr "type" "mfhilo") | |
886 | (set_attr "mode" "SI")]) | |
887 | ||
888 | ;; EXTP* | |
889 | (define_insn "mips_extp" | |
890 | [(parallel | |
891 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
892 | (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") | |
893 | (match_operand:SI 2 "arith_operand" "I,d") | |
894 | (reg:CCDSP CCDSP_PO_REGNUM)] | |
895 | UNSPEC_EXTP)) | |
896 | (set (reg:CCDSP CCDSP_EF_REGNUM) | |
897 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])] | |
254d1646 | 898 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
899 | { |
900 | if (which_alternative == 0) | |
901 | { | |
902 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) | |
903 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
904 | return "extp\t%0,%q1,%2"; | |
905 | } | |
906 | return "extpv\t%0,%q1,%2"; | |
907 | } | |
908 | [(set_attr "type" "mfhilo") | |
909 | (set_attr "mode" "SI")]) | |
910 | ||
911 | (define_insn "mips_extpdp" | |
912 | [(parallel | |
913 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
914 | (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") | |
915 | (match_operand:SI 2 "arith_operand" "I,d") | |
916 | (reg:CCDSP CCDSP_PO_REGNUM)] | |
917 | UNSPEC_EXTPDP)) | |
918 | (set (reg:CCDSP CCDSP_PO_REGNUM) | |
919 | (unspec:CCDSP [(match_dup 1) (match_dup 2) | |
920 | (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) | |
921 | (set (reg:CCDSP CCDSP_EF_REGNUM) | |
922 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])] | |
254d1646 | 923 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
924 | { |
925 | if (which_alternative == 0) | |
926 | { | |
927 | if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) | |
928 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
929 | return "extpdp\t%0,%q1,%2"; | |
930 | } | |
931 | return "extpdpv\t%0,%q1,%2"; | |
932 | } | |
933 | [(set_attr "type" "mfhilo") | |
934 | (set_attr "mode" "SI")]) | |
935 | ||
936 | ;; SHILO* | |
937 | (define_insn "mips_shilo" | |
938 | [(set (match_operand:DI 0 "register_operand" "=a,a") | |
939 | (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") | |
940 | (match_operand:SI 2 "arith_operand" "I,d")] | |
941 | UNSPEC_SHILO))] | |
254d1646 | 942 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
943 | { |
944 | if (which_alternative == 0) | |
945 | { | |
946 | if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31) | |
947 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
948 | return "shilo\t%q0,%2"; | |
949 | } | |
950 | return "shilov\t%q0,%2"; | |
951 | } | |
952 | [(set_attr "type" "mfhilo") | |
953 | (set_attr "mode" "SI")]) | |
954 | ||
955 | ;; MTHLIP* | |
956 | (define_insn "mips_mthlip" | |
957 | [(parallel | |
958 | [(set (match_operand:DI 0 "register_operand" "=a") | |
959 | (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
960 | (match_operand:SI 2 "register_operand" "d") | |
961 | (reg:CCDSP CCDSP_PO_REGNUM)] | |
962 | UNSPEC_MTHLIP)) | |
963 | (set (reg:CCDSP CCDSP_PO_REGNUM) | |
964 | (unspec:CCDSP [(match_dup 1) (match_dup 2) | |
965 | (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] | |
254d1646 | 966 | "ISA_HAS_DSP && !TARGET_64BIT" |
118ea793 CF |
967 | "mthlip\t%2,%q0" |
968 | [(set_attr "type" "mfhilo") | |
969 | (set_attr "mode" "SI")]) | |
970 | ||
971 | ;; WRDSP | |
972 | (define_insn "mips_wrdsp" | |
973 | [(parallel | |
974 | [(set (reg:CCDSP CCDSP_PO_REGNUM) | |
975 | (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") | |
976 | (match_operand:SI 1 "const_uimm6_operand" "YA")] | |
977 | UNSPEC_WRDSP)) | |
978 | (set (reg:CCDSP CCDSP_SC_REGNUM) | |
979 | (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) | |
980 | (set (reg:CCDSP CCDSP_CA_REGNUM) | |
981 | (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) | |
982 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
983 | (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) | |
984 | (set (reg:CCDSP CCDSP_CC_REGNUM) | |
985 | (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) | |
986 | (set (reg:CCDSP CCDSP_EF_REGNUM) | |
987 | (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] | |
254d1646 | 988 | "ISA_HAS_DSP" |
118ea793 CF |
989 | "wrdsp\t%0,%1" |
990 | [(set_attr "type" "arith") | |
991 | (set_attr "mode" "SI")]) | |
992 | ||
993 | ;; RDDSP | |
994 | (define_insn "mips_rddsp" | |
995 | [(set (match_operand:SI 0 "register_operand" "=d") | |
996 | (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA") | |
997 | (reg:CCDSP CCDSP_PO_REGNUM) | |
998 | (reg:CCDSP CCDSP_SC_REGNUM) | |
999 | (reg:CCDSP CCDSP_CA_REGNUM) | |
1000 | (reg:CCDSP CCDSP_OU_REGNUM) | |
1001 | (reg:CCDSP CCDSP_CC_REGNUM) | |
1002 | (reg:CCDSP CCDSP_EF_REGNUM)] | |
1003 | UNSPEC_RDDSP))] | |
254d1646 | 1004 | "ISA_HAS_DSP" |
118ea793 CF |
1005 | "rddsp\t%0,%1" |
1006 | [(set_attr "type" "arith") | |
1007 | (set_attr "mode" "SI")]) | |
1008 | ||
1009 | ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load | |
1010 | ;; L*X | |
26b69f64 RS |
1011 | (define_expand "mips_lbux" |
1012 | [(match_operand:SI 0 "register_operand") | |
1013 | (match_operand 1 "pmode_register_operand") | |
1014 | (match_operand:SI 2 "register_operand")] | |
1015 | "ISA_HAS_DSP" | |
1016 | { | |
1017 | operands[2] = convert_to_mode (Pmode, operands[2], false); | |
1018 | if (Pmode == SImode) | |
1019 | emit_insn (gen_mips_lbux_si (operands[0], operands[1], operands[2])); | |
1020 | else | |
1021 | emit_insn (gen_mips_lbux_di (operands[0], operands[1], operands[2])); | |
1022 | DONE; | |
1023 | }) | |
1024 | ||
1025 | (define_insn "mips_lbux_<mode>" | |
118ea793 | 1026 | [(set (match_operand:SI 0 "register_operand" "=d") |
26b69f64 RS |
1027 | (zero_extend:SI |
1028 | (mem:QI (plus:P (match_operand:P 1 "register_operand" "d") | |
1029 | (match_operand:P 2 "register_operand" "d")))))] | |
254d1646 | 1030 | "ISA_HAS_DSP" |
118ea793 CF |
1031 | "lbux\t%0,%2(%1)" |
1032 | [(set_attr "type" "load") | |
c5cb5d18 | 1033 | (set_attr "mode" "SI")]) |
118ea793 | 1034 | |
26b69f64 RS |
1035 | (define_expand "mips_lhx" |
1036 | [(match_operand:SI 0 "register_operand") | |
1037 | (match_operand 1 "pmode_register_operand") | |
1038 | (match_operand:SI 2 "register_operand")] | |
1039 | "ISA_HAS_DSP" | |
1040 | { | |
1041 | operands[2] = convert_to_mode (Pmode, operands[2], false); | |
1042 | if (Pmode == SImode) | |
1043 | emit_insn (gen_mips_lhx_si (operands[0], operands[1], operands[2])); | |
1044 | else | |
1045 | emit_insn (gen_mips_lhx_di (operands[0], operands[1], operands[2])); | |
1046 | DONE; | |
1047 | }) | |
1048 | ||
1049 | (define_insn "mips_lhx_<mode>" | |
118ea793 | 1050 | [(set (match_operand:SI 0 "register_operand" "=d") |
26b69f64 RS |
1051 | (zero_extend:SI |
1052 | (mem:HI (plus:P (match_operand:P 1 "register_operand" "d") | |
1053 | (match_operand:P 2 "register_operand" "d")))))] | |
254d1646 | 1054 | "ISA_HAS_DSP" |
118ea793 CF |
1055 | "lhx\t%0,%2(%1)" |
1056 | [(set_attr "type" "load") | |
c5cb5d18 | 1057 | (set_attr "mode" "SI")]) |
118ea793 | 1058 | |
26b69f64 RS |
1059 | (define_expand "mips_lwx" |
1060 | [(match_operand:SI 0 "register_operand") | |
1061 | (match_operand 1 "pmode_register_operand") | |
1062 | (match_operand:SI 2 "register_operand")] | |
1063 | "ISA_HAS_DSP" | |
1064 | { | |
1065 | operands[2] = convert_to_mode (Pmode, operands[2], false); | |
1066 | if (Pmode == SImode) | |
1067 | emit_insn (gen_mips_lwx_si (operands[0], operands[1], operands[2])); | |
1068 | else | |
1069 | emit_insn (gen_mips_lwx_di (operands[0], operands[1], operands[2])); | |
1070 | DONE; | |
1071 | }) | |
1072 | ||
1073 | (define_insn "mips_lwx_<mode>" | |
118ea793 | 1074 | [(set (match_operand:SI 0 "register_operand" "=d") |
26b69f64 RS |
1075 | (mem:SI (plus:P (match_operand:P 1 "register_operand" "d") |
1076 | (match_operand:P 2 "register_operand" "d"))))] | |
254d1646 | 1077 | "ISA_HAS_DSP" |
118ea793 CF |
1078 | "lwx\t%0,%2(%1)" |
1079 | [(set_attr "type" "load") | |
c5cb5d18 | 1080 | (set_attr "mode" "SI")]) |
118ea793 CF |
1081 | |
1082 | ;; Table 2-8. MIPS DSP ASE Instructions: Branch | |
1083 | ;; BPOSGE32 | |
1084 | (define_insn "mips_bposge" | |
1085 | [(set (pc) | |
a8c1d5f8 RS |
1086 | (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM) |
1087 | (match_operand:SI 0 "immediate_operand" "I")) | |
1088 | (label_ref (match_operand 1 "" "")) | |
1089 | (pc)))] | |
254d1646 | 1090 | "ISA_HAS_DSP" |
118ea793 CF |
1091 | "%*bposge%0\t%1%/" |
1092 | [(set_attr "type" "branch") | |
1093 | (set_attr "mode" "none")]) | |
1094 |