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f1717362 1;; Copyright (C) 2007-2016 Free Software Foundation, Inc.
7dfbd804 2;;
3;; This file is part of GCC.
4;;
5;; GCC is free software; you can redistribute it and/or modify
6;; it under the terms of the GNU General Public License as published by
7;; the Free Software Foundation; either version 3, or (at your option)
8;; any later version.
9;;
10;; GCC is distributed in the hope that it will be useful,
11;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13;; GNU General Public License for more details.
14;;
15;; You should have received a copy of the GNU General Public License
16;; along with GCC; see the file COPYING3. If not see
17;; <http://www.gnu.org/licenses/>.
18;;
c1901bc7 19; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
20
5d54fceb 21(define_c_enum "unspec" [
22 UNSPEC_ABSQ_S_QB
23 UNSPEC_ADDU_PH
24 UNSPEC_ADDU_S_PH
25 UNSPEC_ADDUH_QB
26 UNSPEC_ADDUH_R_QB
27 UNSPEC_APPEND
28 UNSPEC_BALIGN
29 UNSPEC_CMPGDU_EQ_QB
30 UNSPEC_CMPGDU_LT_QB
31 UNSPEC_CMPGDU_LE_QB
32 UNSPEC_DPA_W_PH
33 UNSPEC_DPS_W_PH
34 UNSPEC_MADD
35 UNSPEC_MADDU
36 UNSPEC_MSUB
37 UNSPEC_MSUBU
38 UNSPEC_MUL_PH
39 UNSPEC_MUL_S_PH
40 UNSPEC_MULQ_RS_W
41 UNSPEC_MULQ_S_PH
42 UNSPEC_MULQ_S_W
43 UNSPEC_MULSA_W_PH
44 UNSPEC_MULT
45 UNSPEC_MULTU
46 UNSPEC_PRECR_QB_PH
47 UNSPEC_PRECR_SRA_PH_W
48 UNSPEC_PRECR_SRA_R_PH_W
49 UNSPEC_PREPEND
50 UNSPEC_SHRA_QB
51 UNSPEC_SHRA_R_QB
52 UNSPEC_SHRL_PH
53 UNSPEC_SUBU_PH
54 UNSPEC_SUBU_S_PH
55 UNSPEC_SUBUH_QB
56 UNSPEC_SUBUH_R_QB
57 UNSPEC_ADDQH_PH
58 UNSPEC_ADDQH_R_PH
59 UNSPEC_ADDQH_W
60 UNSPEC_ADDQH_R_W
61 UNSPEC_SUBQH_PH
62 UNSPEC_SUBQH_R_PH
63 UNSPEC_SUBQH_W
64 UNSPEC_SUBQH_R_W
65 UNSPEC_DPAX_W_PH
66 UNSPEC_DPSX_W_PH
67 UNSPEC_DPAQX_S_W_PH
68 UNSPEC_DPAQX_SA_W_PH
69 UNSPEC_DPSQX_S_W_PH
70 UNSPEC_DPSQX_SA_W_PH
71])
72
c1901bc7 73(define_insn "mips_absq_s_qb"
01d2893e 74 [(set (match_operand:V4QI 0 "register_operand" "=d")
75 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
76 UNSPEC_ABSQ_S_QB))
77 (set (reg:CCDSP CCDSP_OU_REGNUM)
78 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))]
c19eff17 79 "ISA_HAS_DSPR2"
c1901bc7 80 "absq_s.qb\t%0,%z1"
d4566465 81 [(set_attr "type" "dspalusat")
c1901bc7 82 (set_attr "mode" "SI")])
83
84(define_insn "mips_addu_ph"
01d2893e 85 [(set (match_operand:V2HI 0 "register_operand" "=d")
86 (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
87 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
88 (set (reg:CCDSP CCDSP_OU_REGNUM)
89 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))]
c19eff17 90 "ISA_HAS_DSPR2"
c1901bc7 91 "addu.ph\t%0,%z1,%z2"
d4566465 92 [(set_attr "type" "dspalu")
c1901bc7 93 (set_attr "mode" "SI")])
94
95(define_insn "mips_addu_s_ph"
01d2893e 96 [(set (match_operand:V2HI 0 "register_operand" "=d")
97 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
98 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
99 UNSPEC_ADDU_S_PH))
100 (set (reg:CCDSP CCDSP_OU_REGNUM)
101 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))]
c19eff17 102 "ISA_HAS_DSPR2"
c1901bc7 103 "addu_s.ph\t%0,%z1,%z2"
d4566465 104 [(set_attr "type" "dspalusat")
c1901bc7 105 (set_attr "mode" "SI")])
106
107(define_insn "mips_adduh_qb"
108 [(set (match_operand:V4QI 0 "register_operand" "=d")
109 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
110 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
111 UNSPEC_ADDUH_QB))]
c19eff17 112 "ISA_HAS_DSPR2"
c1901bc7 113 "adduh.qb\t%0,%z1,%z2"
d4566465 114 [(set_attr "type" "dspalu")
c1901bc7 115 (set_attr "mode" "SI")])
116
117(define_insn "mips_adduh_r_qb"
118 [(set (match_operand:V4QI 0 "register_operand" "=d")
119 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
120 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
121 UNSPEC_ADDUH_R_QB))]
c19eff17 122 "ISA_HAS_DSPR2"
c1901bc7 123 "adduh_r.qb\t%0,%z1,%z2"
d4566465 124 [(set_attr "type" "dspalusat")
c1901bc7 125 (set_attr "mode" "SI")])
126
127(define_insn "mips_append"
128 [(set (match_operand:SI 0 "register_operand" "=d")
129 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
130 (match_operand:SI 2 "reg_or_0_operand" "dJ")
131 (match_operand:SI 3 "const_int_operand" "n")]
132 UNSPEC_APPEND))]
c19eff17 133 "ISA_HAS_DSPR2"
c1901bc7 134{
135 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
136 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
137 return "append\t%0,%z2,%3";
138}
d4566465 139 [(set_attr "type" "dspalu")
c1901bc7 140 (set_attr "mode" "SI")])
141
142(define_insn "mips_balign"
143 [(set (match_operand:SI 0 "register_operand" "=d")
144 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
145 (match_operand:SI 2 "reg_or_0_operand" "dJ")
146 (match_operand:SI 3 "const_int_operand" "n")]
147 UNSPEC_BALIGN))]
c19eff17 148 "ISA_HAS_DSPR2"
c1901bc7 149{
150 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
151 operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
152 return "balign\t%0,%z2,%3";
153}
d4566465 154 [(set_attr "type" "dspalu")
c1901bc7 155 (set_attr "mode" "SI")])
156
157(define_insn "mips_cmpgdu_eq_qb"
01d2893e 158 [(set (match_operand:SI 0 "register_operand" "=d")
159 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
160 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
161 UNSPEC_CMPGDU_EQ_QB))
162 (set (reg:CCDSP CCDSP_CC_REGNUM)
163 (unspec:CCDSP [(match_dup 1) (match_dup 2)
164 (reg:CCDSP CCDSP_CC_REGNUM)]
165 UNSPEC_CMPGDU_EQ_QB))]
c19eff17 166 "ISA_HAS_DSPR2"
c1901bc7 167 "cmpgdu.eq.qb\t%0,%z1,%z2"
d4566465 168 [(set_attr "type" "dspalu")
c1901bc7 169 (set_attr "mode" "SI")])
170
171(define_insn "mips_cmpgdu_lt_qb"
01d2893e 172 [(set (match_operand:SI 0 "register_operand" "=d")
173 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
174 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
175 UNSPEC_CMPGDU_LT_QB))
176 (set (reg:CCDSP CCDSP_CC_REGNUM)
177 (unspec:CCDSP [(match_dup 1) (match_dup 2)
178 (reg:CCDSP CCDSP_CC_REGNUM)]
179 UNSPEC_CMPGDU_LT_QB))]
c19eff17 180 "ISA_HAS_DSPR2"
c1901bc7 181 "cmpgdu.lt.qb\t%0,%z1,%z2"
d4566465 182 [(set_attr "type" "dspalu")
c1901bc7 183 (set_attr "mode" "SI")])
184
185(define_insn "mips_cmpgdu_le_qb"
01d2893e 186 [(set (match_operand:SI 0 "register_operand" "=d")
187 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
188 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
189 UNSPEC_CMPGDU_LE_QB))
190 (set (reg:CCDSP CCDSP_CC_REGNUM)
191 (unspec:CCDSP [(match_dup 1) (match_dup 2)
192 (reg:CCDSP CCDSP_CC_REGNUM)]
193 UNSPEC_CMPGDU_LE_QB))]
c19eff17 194 "ISA_HAS_DSPR2"
c1901bc7 195 "cmpgdu.le.qb\t%0,%z1,%z2"
d4566465 196 [(set_attr "type" "dspalu")
c1901bc7 197 (set_attr "mode" "SI")])
198
199(define_insn "mips_dpa_w_ph"
200 [(set (match_operand:DI 0 "register_operand" "=a")
201 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
202 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
203 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
204 UNSPEC_DPA_W_PH))]
c19eff17 205 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 206 "dpa.w.ph\t%q0,%z2,%z3"
d4566465 207 [(set_attr "type" "dspmac")
208 (set_attr "accum_in" "1")
c1901bc7 209 (set_attr "mode" "SI")])
210
211(define_insn "mips_dps_w_ph"
212 [(set (match_operand:DI 0 "register_operand" "=a")
213 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
214 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
215 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
216 UNSPEC_DPS_W_PH))]
c19eff17 217 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 218 "dps.w.ph\t%q0,%z2,%z3"
d4566465 219 [(set_attr "type" "dspmac")
220 (set_attr "accum_in" "1")
c1901bc7 221 (set_attr "mode" "SI")])
222
c1901bc7 223(define_insn "mulv2hi3"
01d2893e 224 [(set (match_operand:V2HI 0 "register_operand" "=d")
225 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
226 (match_operand:V2HI 2 "register_operand" "d")))
227 (set (reg:CCDSP CCDSP_OU_REGNUM)
228 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
229 (clobber (match_scratch:DI 3 "=x"))]
c19eff17 230 "ISA_HAS_DSPR2"
c1901bc7 231 "mul.ph\t%0,%1,%2"
232 [(set_attr "type" "imul3")
233 (set_attr "mode" "SI")])
234
235(define_insn "mips_mul_s_ph"
01d2893e 236 [(set (match_operand:V2HI 0 "register_operand" "=d")
237 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
238 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
239 UNSPEC_MUL_S_PH))
240 (set (reg:CCDSP CCDSP_OU_REGNUM)
241 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
242 (clobber (match_scratch:DI 3 "=x"))]
c19eff17 243 "ISA_HAS_DSPR2"
c1901bc7 244 "mul_s.ph\t%0,%z1,%z2"
245 [(set_attr "type" "imul3")
246 (set_attr "mode" "SI")])
247
248(define_insn "mips_mulq_rs_w"
01d2893e 249 [(set (match_operand:SI 0 "register_operand" "=d")
250 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
251 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
252 UNSPEC_MULQ_RS_W))
253 (set (reg:CCDSP CCDSP_OU_REGNUM)
254 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
255 (clobber (match_scratch:DI 3 "=x"))]
c19eff17 256 "ISA_HAS_DSPR2"
c1901bc7 257 "mulq_rs.w\t%0,%z1,%z2"
258 [(set_attr "type" "imul3")
259 (set_attr "mode" "SI")])
260
261(define_insn "mips_mulq_s_ph"
01d2893e 262 [(set (match_operand:V2HI 0 "register_operand" "=d")
263 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
264 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
265 UNSPEC_MULQ_S_PH))
266 (set (reg:CCDSP CCDSP_OU_REGNUM)
267 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
268 (clobber (match_scratch:DI 3 "=x"))]
c19eff17 269 "ISA_HAS_DSPR2"
c1901bc7 270 "mulq_s.ph\t%0,%z1,%z2"
271 [(set_attr "type" "imul3")
272 (set_attr "mode" "SI")])
273
274(define_insn "mips_mulq_s_w"
01d2893e 275 [(set (match_operand:SI 0 "register_operand" "=d")
276 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
277 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
278 UNSPEC_MULQ_S_W))
279 (set (reg:CCDSP CCDSP_OU_REGNUM)
280 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
281 (clobber (match_scratch:DI 3 "=x"))]
c19eff17 282 "ISA_HAS_DSPR2"
c1901bc7 283 "mulq_s.w\t%0,%z1,%z2"
284 [(set_attr "type" "imul3")
285 (set_attr "mode" "SI")])
286
287(define_insn "mips_mulsa_w_ph"
288 [(set (match_operand:DI 0 "register_operand" "=a")
289 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
290 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
291 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
292 UNSPEC_MULSA_W_PH))]
c19eff17 293 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 294 "mulsa.w.ph\t%q0,%z2,%z3"
d4566465 295 [(set_attr "type" "dspmac")
296 (set_attr "accum_in" "1")
c1901bc7 297 (set_attr "mode" "SI")])
298
c1901bc7 299(define_insn "mips_precr_qb_ph"
300 [(set (match_operand:V4QI 0 "register_operand" "=d")
301 (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
302 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
303 UNSPEC_PRECR_QB_PH))]
c19eff17 304 "ISA_HAS_DSPR2"
c1901bc7 305 "precr.qb.ph\t%0,%z1,%z2"
d4566465 306 [(set_attr "type" "dspalu")
c1901bc7 307 (set_attr "mode" "SI")])
308
309(define_insn "mips_precr_sra_ph_w"
310 [(set (match_operand:V2HI 0 "register_operand" "=d")
311 (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
312 (match_operand:SI 2 "reg_or_0_operand" "dJ")
313 (match_operand:SI 3 "const_int_operand" "n")]
314 UNSPEC_PRECR_SRA_PH_W))]
c19eff17 315 "ISA_HAS_DSPR2"
c1901bc7 316{
317 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
318 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
319 return "precr_sra.ph.w\t%0,%z2,%3";
320}
d4566465 321 [(set_attr "type" "dspalu")
c1901bc7 322 (set_attr "mode" "SI")])
323
324(define_insn "mips_precr_sra_r_ph_w"
325 [(set (match_operand:V2HI 0 "register_operand" "=d")
326 (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
327 (match_operand:SI 2 "reg_or_0_operand" "dJ")
328 (match_operand:SI 3 "const_int_operand" "n")]
329 UNSPEC_PRECR_SRA_R_PH_W))]
c19eff17 330 "ISA_HAS_DSPR2"
c1901bc7 331{
332 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
333 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
334 return "precr_sra_r.ph.w\t%0,%z2,%3";
335}
d4566465 336 [(set_attr "type" "dspalu")
c1901bc7 337 (set_attr "mode" "SI")])
338
339(define_insn "mips_prepend"
340 [(set (match_operand:SI 0 "register_operand" "=d")
341 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
342 (match_operand:SI 2 "reg_or_0_operand" "dJ")
343 (match_operand:SI 3 "const_int_operand" "n")]
344 UNSPEC_PREPEND))]
c19eff17 345 "ISA_HAS_DSPR2"
c1901bc7 346{
347 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
a13b68f1 348 operands[3] = GEN_INT (INTVAL (operands[3]) & 31);
c1901bc7 349 return "prepend\t%0,%z2,%3";
350}
d4566465 351 [(set_attr "type" "dspalu")
c1901bc7 352 (set_attr "mode" "SI")])
353
354(define_insn "mips_shra_qb"
355 [(set (match_operand:V4QI 0 "register_operand" "=d,d")
356 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
357 (match_operand:SI 2 "arith_operand" "I,d")]
358 UNSPEC_SHRA_QB))]
c19eff17 359 "ISA_HAS_DSPR2"
c1901bc7 360{
361 if (which_alternative == 0)
362 {
363 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
364 operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
365 return "shra.qb\t%0,%z1,%2";
366 }
367 return "shrav.qb\t%0,%z1,%2";
368}
d4566465 369 [(set_attr "type" "dspalu")
c1901bc7 370 (set_attr "mode" "SI")])
371
372
373(define_insn "mips_shra_r_qb"
374 [(set (match_operand:V4QI 0 "register_operand" "=d,d")
375 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
376 (match_operand:SI 2 "arith_operand" "I,d")]
377 UNSPEC_SHRA_R_QB))]
c19eff17 378 "ISA_HAS_DSPR2"
c1901bc7 379{
380 if (which_alternative == 0)
381 {
382 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
383 operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
384 return "shra_r.qb\t%0,%z1,%2";
385 }
386 return "shrav_r.qb\t%0,%z1,%2";
387}
d4566465 388 [(set_attr "type" "dspalu")
c1901bc7 389 (set_attr "mode" "SI")])
390
391(define_insn "mips_shrl_ph"
392 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
393 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
394 (match_operand:SI 2 "arith_operand" "I,d")]
395 UNSPEC_SHRL_PH))]
c19eff17 396 "ISA_HAS_DSPR2"
c1901bc7 397{
398 if (which_alternative == 0)
399 {
400 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
401 operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
402 return "shrl.ph\t%0,%z1,%2";
403 }
404 return "shrlv.ph\t%0,%z1,%2";
405}
d4566465 406 [(set_attr "type" "dspalu")
c1901bc7 407 (set_attr "mode" "SI")])
408
409(define_insn "mips_subu_ph"
01d2893e 410 [(set (match_operand:V2HI 0 "register_operand" "=d")
411 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
412 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
413 UNSPEC_SUBU_PH))
414 (set (reg:CCDSP CCDSP_OU_REGNUM)
415 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))]
c19eff17 416 "ISA_HAS_DSPR2"
c1901bc7 417 "subu.ph\t%0,%z1,%z2"
d4566465 418 [(set_attr "type" "dspalu")
c1901bc7 419 (set_attr "mode" "SI")])
420
421(define_insn "mips_subu_s_ph"
01d2893e 422 [(set (match_operand:V2HI 0 "register_operand" "=d")
423 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
424 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
425 UNSPEC_SUBU_S_PH))
426 (set (reg:CCDSP CCDSP_OU_REGNUM)
427 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))]
c19eff17 428 "ISA_HAS_DSPR2"
c1901bc7 429 "subu_s.ph\t%0,%z1,%z2"
d4566465 430 [(set_attr "type" "dspalusat")
c1901bc7 431 (set_attr "mode" "SI")])
432
433(define_insn "mips_subuh_qb"
434 [(set (match_operand:V4QI 0 "register_operand" "=d")
435 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
436 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
437 UNSPEC_SUBUH_QB))]
c19eff17 438 "ISA_HAS_DSPR2"
c1901bc7 439 "subuh.qb\t%0,%z1,%z2"
d4566465 440 [(set_attr "type" "dspalu")
c1901bc7 441 (set_attr "mode" "SI")])
442
443(define_insn "mips_subuh_r_qb"
444 [(set (match_operand:V4QI 0 "register_operand" "=d")
445 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
446 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
447 UNSPEC_SUBUH_R_QB))]
c19eff17 448 "ISA_HAS_DSPR2"
c1901bc7 449 "subuh_r.qb\t%0,%z1,%z2"
d4566465 450 [(set_attr "type" "dspalu")
c1901bc7 451 (set_attr "mode" "SI")])
452
453(define_insn "mips_addqh_ph"
454 [(set (match_operand:V2HI 0 "register_operand" "=d")
455 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
456 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
457 UNSPEC_ADDQH_PH))]
c19eff17 458 "ISA_HAS_DSPR2"
c1901bc7 459 "addqh.ph\t%0,%z1,%z2"
d4566465 460 [(set_attr "type" "dspalu")
c1901bc7 461 (set_attr "mode" "SI")])
462
463(define_insn "mips_addqh_r_ph"
464 [(set (match_operand:V2HI 0 "register_operand" "=d")
465 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
466 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
467 UNSPEC_ADDQH_R_PH))]
c19eff17 468 "ISA_HAS_DSPR2"
c1901bc7 469 "addqh_r.ph\t%0,%z1,%z2"
d4566465 470 [(set_attr "type" "dspalu")
c1901bc7 471 (set_attr "mode" "SI")])
472
473(define_insn "mips_addqh_w"
474 [(set (match_operand:SI 0 "register_operand" "=d")
475 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
476 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
477 UNSPEC_ADDQH_W))]
c19eff17 478 "ISA_HAS_DSPR2"
c1901bc7 479 "addqh.w\t%0,%z1,%z2"
d4566465 480 [(set_attr "type" "dspalu")
c1901bc7 481 (set_attr "mode" "SI")])
482
483(define_insn "mips_addqh_r_w"
484 [(set (match_operand:SI 0 "register_operand" "=d")
485 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
486 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
487 UNSPEC_ADDQH_R_W))]
c19eff17 488 "ISA_HAS_DSPR2"
c1901bc7 489 "addqh_r.w\t%0,%z1,%z2"
d4566465 490 [(set_attr "type" "dspalu")
c1901bc7 491 (set_attr "mode" "SI")])
492
493(define_insn "mips_subqh_ph"
494 [(set (match_operand:V2HI 0 "register_operand" "=d")
495 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
496 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
497 UNSPEC_SUBQH_PH))]
c19eff17 498 "ISA_HAS_DSPR2"
c1901bc7 499 "subqh.ph\t%0,%z1,%z2"
d4566465 500 [(set_attr "type" "dspalu")
c1901bc7 501 (set_attr "mode" "SI")])
502
503(define_insn "mips_subqh_r_ph"
504 [(set (match_operand:V2HI 0 "register_operand" "=d")
505 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
506 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
507 UNSPEC_SUBQH_R_PH))]
c19eff17 508 "ISA_HAS_DSPR2"
c1901bc7 509 "subqh_r.ph\t%0,%z1,%z2"
d4566465 510 [(set_attr "type" "dspalu")
c1901bc7 511 (set_attr "mode" "SI")])
512
513(define_insn "mips_subqh_w"
514 [(set (match_operand:SI 0 "register_operand" "=d")
515 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
516 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
517 UNSPEC_SUBQH_W))]
c19eff17 518 "ISA_HAS_DSPR2"
c1901bc7 519 "subqh.w\t%0,%z1,%z2"
d4566465 520 [(set_attr "type" "dspalu")
c1901bc7 521 (set_attr "mode" "SI")])
522
523(define_insn "mips_subqh_r_w"
524 [(set (match_operand:SI 0 "register_operand" "=d")
525 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
526 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
527 UNSPEC_SUBQH_R_W))]
c19eff17 528 "ISA_HAS_DSPR2"
c1901bc7 529 "subqh_r.w\t%0,%z1,%z2"
d4566465 530 [(set_attr "type" "dspalu")
c1901bc7 531 (set_attr "mode" "SI")])
532
533(define_insn "mips_dpax_w_ph"
534 [(set (match_operand:DI 0 "register_operand" "=a")
535 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
536 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
537 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
538 UNSPEC_DPAX_W_PH))]
c19eff17 539 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 540 "dpax.w.ph\t%q0,%z2,%z3"
d4566465 541 [(set_attr "type" "dspmac")
542 (set_attr "accum_in" "1")
c1901bc7 543 (set_attr "mode" "SI")])
544
545(define_insn "mips_dpsx_w_ph"
546 [(set (match_operand:DI 0 "register_operand" "=a")
547 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
548 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
549 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
550 UNSPEC_DPSX_W_PH))]
c19eff17 551 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 552 "dpsx.w.ph\t%q0,%z2,%z3"
d4566465 553 [(set_attr "type" "dspmac")
554 (set_attr "accum_in" "1")
c1901bc7 555 (set_attr "mode" "SI")])
556
557(define_insn "mips_dpaqx_s_w_ph"
01d2893e 558 [(set (match_operand:DI 0 "register_operand" "=a")
559 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
560 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
561 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
562 UNSPEC_DPAQX_S_W_PH))
563 (set (reg:CCDSP CCDSP_OU_REGNUM)
564 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
565 UNSPEC_DPAQX_S_W_PH))]
c19eff17 566 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 567 "dpaqx_s.w.ph\t%q0,%z2,%z3"
d4566465 568 [(set_attr "type" "dspmac")
569 (set_attr "accum_in" "1")
c1901bc7 570 (set_attr "mode" "SI")])
571
572(define_insn "mips_dpaqx_sa_w_ph"
01d2893e 573 [(set (match_operand:DI 0 "register_operand" "=a")
574 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
575 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
576 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
577 UNSPEC_DPAQX_SA_W_PH))
578 (set (reg:CCDSP CCDSP_OU_REGNUM)
579 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
580 UNSPEC_DPAQX_SA_W_PH))]
c19eff17 581 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 582 "dpaqx_sa.w.ph\t%q0,%z2,%z3"
d4566465 583 [(set_attr "type" "dspmacsat")
584 (set_attr "accum_in" "1")
c1901bc7 585 (set_attr "mode" "SI")])
586
587(define_insn "mips_dpsqx_s_w_ph"
01d2893e 588 [(set (match_operand:DI 0 "register_operand" "=a")
589 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
590 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
591 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
592 UNSPEC_DPSQX_S_W_PH))
593 (set (reg:CCDSP CCDSP_OU_REGNUM)
594 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
595 UNSPEC_DPSQX_S_W_PH))]
c19eff17 596 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 597 "dpsqx_s.w.ph\t%q0,%z2,%z3"
d4566465 598 [(set_attr "type" "dspmac")
599 (set_attr "accum_in" "1")
c1901bc7 600 (set_attr "mode" "SI")])
601
602(define_insn "mips_dpsqx_sa_w_ph"
01d2893e 603 [(set (match_operand:DI 0 "register_operand" "=a")
604 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
605 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
606 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
607 UNSPEC_DPSQX_SA_W_PH))
608 (set (reg:CCDSP CCDSP_OU_REGNUM)
609 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
610 UNSPEC_DPSQX_SA_W_PH))]
c19eff17 611 "ISA_HAS_DSPR2 && !TARGET_64BIT"
c1901bc7 612 "dpsqx_sa.w.ph\t%q0,%z2,%z3"
d4566465 613 [(set_attr "type" "dspmacsat")
614 (set_attr "accum_in" "1")
c1901bc7 615 (set_attr "mode" "SI")])
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