]>
Commit | Line | Data |
---|---|---|
5624e564 | 1 | ;; Copyright (C) 2007-2015 Free Software Foundation, Inc. |
ad41bd84 JM |
2 | ;; |
3 | ;; This file is part of GCC. | |
4 | ;; | |
5 | ;; GCC is free software; you can redistribute it and/or modify | |
6 | ;; it under the terms of the GNU General Public License as published by | |
7 | ;; the Free Software Foundation; either version 3, or (at your option) | |
8 | ;; any later version. | |
9 | ;; | |
10 | ;; GCC is distributed in the hope that it will be useful, | |
11 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | ;; GNU General Public License for more details. | |
14 | ;; | |
15 | ;; You should have received a copy of the GNU General Public License | |
16 | ;; along with GCC; see the file COPYING3. If not see | |
17 | ;; <http://www.gnu.org/licenses/>. | |
18 | ;; | |
9fc777ad CF |
19 | ;; This file contains MIPS instructions that support fixed-point operations. |
20 | ||
21 | ;; All supported fixed-point modes | |
22 | (define_mode_iterator FIXED [(QQ "") (HQ "") (SQ "") (DQ "TARGET_64BIT") | |
23 | (UQQ "") (UHQ "") (USQ "") (UDQ "TARGET_64BIT") | |
24 | (HA "") (SA "") (DA "TARGET_64BIT") | |
25 | (UHA "") (USA "") (UDA "TARGET_64BIT")]) | |
26 | ||
27 | ;; For signed add/sub with saturation | |
28 | (define_mode_iterator ADDSUB [(HQ "") (SQ "") (HA "") (SA "") (V2HQ "") | |
29 | (V2HA "")]) | |
30 | (define_mode_attr addsubfmt [(HQ "ph") (SQ "w") (HA "ph") (SA "w") | |
31 | (V2HQ "ph") (V2HA "ph")]) | |
32 | ||
33 | ;; For unsigned add/sub with saturation | |
254d1646 RS |
34 | (define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2") |
35 | (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP") | |
36 | (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")]) | |
9fc777ad CF |
37 | (define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph") |
38 | (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")]) | |
39 | ||
40 | ;; For signed multiplication with saturation | |
254d1646 RS |
41 | (define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP") |
42 | (SQ "ISA_HAS_DSPR2")]) | |
9fc777ad CF |
43 | (define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")]) |
44 | ||
45 | (define_insn "add<mode>3" | |
46 | [(set (match_operand:FIXED 0 "register_operand" "=d") | |
47 | (plus:FIXED (match_operand:FIXED 1 "register_operand" "d") | |
48 | (match_operand:FIXED 2 "register_operand" "d")))] | |
49 | "" | |
50 | "<d>addu\t%0,%1,%2" | |
51 | [(set_attr "type" "arith") | |
52 | (set_attr "mode" "<IMODE>")]) | |
53 | ||
54 | (define_insn "usadd<mode>3" | |
55 | [(parallel | |
56 | [(set (match_operand:UADDSUB 0 "register_operand" "=d") | |
57 | (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") | |
58 | (match_operand:UADDSUB 2 "register_operand" "d"))) | |
59 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
60 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] | |
61 | "" | |
62 | "addu_s.<uaddsubfmt>\t%0,%1,%2" | |
63 | [(set_attr "type" "arith") | |
64 | (set_attr "mode" "<IMODE>")]) | |
65 | ||
66 | (define_insn "ssadd<mode>3" | |
67 | [(parallel | |
68 | [(set (match_operand:ADDSUB 0 "register_operand" "=d") | |
69 | (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") | |
70 | (match_operand:ADDSUB 2 "register_operand" "d"))) | |
71 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
72 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] | |
254d1646 | 73 | "ISA_HAS_DSP" |
9fc777ad CF |
74 | "addq_s.<addsubfmt>\t%0,%1,%2" |
75 | [(set_attr "type" "arith") | |
76 | (set_attr "mode" "<IMODE>")]) | |
77 | ||
78 | (define_insn "sub<mode>3" | |
79 | [(set (match_operand:FIXED 0 "register_operand" "=d") | |
80 | (minus:FIXED (match_operand:FIXED 1 "register_operand" "d") | |
81 | (match_operand:FIXED 2 "register_operand" "d")))] | |
82 | "" | |
83 | "<d>subu\t%0,%1,%2" | |
84 | [(set_attr "type" "arith") | |
85 | (set_attr "mode" "<IMODE>")]) | |
86 | ||
87 | (define_insn "ussub<mode>3" | |
88 | [(parallel | |
89 | [(set (match_operand:UADDSUB 0 "register_operand" "=d") | |
90 | (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") | |
91 | (match_operand:UADDSUB 2 "register_operand" "d"))) | |
92 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
93 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] | |
94 | "" | |
95 | "subu_s.<uaddsubfmt>\t%0,%1,%2" | |
96 | [(set_attr "type" "arith") | |
97 | (set_attr "mode" "<IMODE>")]) | |
98 | ||
99 | (define_insn "sssub<mode>3" | |
100 | [(parallel | |
101 | [(set (match_operand:ADDSUB 0 "register_operand" "=d") | |
102 | (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") | |
103 | (match_operand:ADDSUB 2 "register_operand" "d"))) | |
104 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
105 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] | |
254d1646 | 106 | "ISA_HAS_DSP" |
9fc777ad CF |
107 | "subq_s.<addsubfmt>\t%0,%1,%2" |
108 | [(set_attr "type" "arith") | |
109 | (set_attr "mode" "<IMODE>")]) | |
110 | ||
111 | (define_insn "ssmul<mode>3" | |
112 | [(parallel | |
113 | [(set (match_operand:MULQ 0 "register_operand" "=d") | |
114 | (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d") | |
115 | (match_operand:MULQ 2 "register_operand" "d"))) | |
116 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
117 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) | |
118 | (clobber (match_scratch:DI 3 "=x"))])] | |
119 | "" | |
120 | "mulq_rs.<mulqfmt>\t%0,%1,%2" | |
121 | [(set_attr "type" "imul3") | |
122 | (set_attr "mode" "<IMODE>")]) | |
123 | ||
124 | (define_insn "ssmaddsqdq4" | |
125 | [(parallel | |
126 | [(set (match_operand:DQ 0 "register_operand" "=a") | |
127 | (ss_plus:DQ | |
128 | (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 | |
129 | "register_operand" "d")) | |
130 | (sat_fract:DQ (match_operand:SQ 2 | |
131 | "register_operand" "d"))) | |
132 | (match_operand:DQ 3 "register_operand" "0"))) | |
133 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
134 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
135 | UNSPEC_DPAQ_SA_L_W))])] | |
254d1646 | 136 | "ISA_HAS_DSP && !TARGET_64BIT" |
9fc777ad CF |
137 | "dpaq_sa.l.w\t%q0,%1,%2" |
138 | [(set_attr "type" "imadd") | |
139 | (set_attr "mode" "SI")]) | |
140 | ||
141 | (define_insn "ssmsubsqdq4" | |
142 | [(parallel | |
143 | [(set (match_operand:DQ 0 "register_operand" "=a") | |
144 | (ss_minus:DQ | |
145 | (match_operand:DQ 3 "register_operand" "0") | |
146 | (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 | |
147 | "register_operand" "d")) | |
148 | (sat_fract:DQ (match_operand:SQ 2 | |
149 | "register_operand" "d"))))) | |
150 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
151 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
152 | UNSPEC_DPSQ_SA_L_W))])] | |
254d1646 | 153 | "ISA_HAS_DSP && !TARGET_64BIT" |
9fc777ad CF |
154 | "dpsq_sa.l.w\t%q0,%1,%2" |
155 | [(set_attr "type" "imadd") | |
156 | (set_attr "mode" "SI")]) |