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9fc777ad CF |
1 | ;; This file contains MIPS instructions that support fixed-point operations. |
2 | ||
3 | ;; All supported fixed-point modes | |
4 | (define_mode_iterator FIXED [(QQ "") (HQ "") (SQ "") (DQ "TARGET_64BIT") | |
5 | (UQQ "") (UHQ "") (USQ "") (UDQ "TARGET_64BIT") | |
6 | (HA "") (SA "") (DA "TARGET_64BIT") | |
7 | (UHA "") (USA "") (UDA "TARGET_64BIT")]) | |
8 | ||
9 | ;; For signed add/sub with saturation | |
10 | (define_mode_iterator ADDSUB [(HQ "") (SQ "") (HA "") (SA "") (V2HQ "") | |
11 | (V2HA "")]) | |
12 | (define_mode_attr addsubfmt [(HQ "ph") (SQ "w") (HA "ph") (SA "w") | |
13 | (V2HQ "ph") (V2HA "ph")]) | |
14 | ||
15 | ;; For unsigned add/sub with saturation | |
16 | (define_mode_iterator UADDSUB [(UQQ "TARGET_DSP") (UHQ "TARGET_DSPR2") | |
17 | (UHA "TARGET_DSPR2") (V4UQQ "TARGET_DSP") | |
18 | (V2UHQ "TARGET_DSPR2") (V2UHA "TARGET_DSPR2")]) | |
19 | (define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph") | |
20 | (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")]) | |
21 | ||
22 | ;; For signed multiplication with saturation | |
23 | (define_mode_iterator MULQ [(V2HQ "TARGET_DSP") (HQ "TARGET_DSP") | |
24 | (SQ "TARGET_DSPR2")]) | |
25 | (define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")]) | |
26 | ||
27 | (define_insn "add<mode>3" | |
28 | [(set (match_operand:FIXED 0 "register_operand" "=d") | |
29 | (plus:FIXED (match_operand:FIXED 1 "register_operand" "d") | |
30 | (match_operand:FIXED 2 "register_operand" "d")))] | |
31 | "" | |
32 | "<d>addu\t%0,%1,%2" | |
33 | [(set_attr "type" "arith") | |
34 | (set_attr "mode" "<IMODE>")]) | |
35 | ||
36 | (define_insn "usadd<mode>3" | |
37 | [(parallel | |
38 | [(set (match_operand:UADDSUB 0 "register_operand" "=d") | |
39 | (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") | |
40 | (match_operand:UADDSUB 2 "register_operand" "d"))) | |
41 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
42 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] | |
43 | "" | |
44 | "addu_s.<uaddsubfmt>\t%0,%1,%2" | |
45 | [(set_attr "type" "arith") | |
46 | (set_attr "mode" "<IMODE>")]) | |
47 | ||
48 | (define_insn "ssadd<mode>3" | |
49 | [(parallel | |
50 | [(set (match_operand:ADDSUB 0 "register_operand" "=d") | |
51 | (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") | |
52 | (match_operand:ADDSUB 2 "register_operand" "d"))) | |
53 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
54 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] | |
55 | "TARGET_DSP" | |
56 | "addq_s.<addsubfmt>\t%0,%1,%2" | |
57 | [(set_attr "type" "arith") | |
58 | (set_attr "mode" "<IMODE>")]) | |
59 | ||
60 | (define_insn "sub<mode>3" | |
61 | [(set (match_operand:FIXED 0 "register_operand" "=d") | |
62 | (minus:FIXED (match_operand:FIXED 1 "register_operand" "d") | |
63 | (match_operand:FIXED 2 "register_operand" "d")))] | |
64 | "" | |
65 | "<d>subu\t%0,%1,%2" | |
66 | [(set_attr "type" "arith") | |
67 | (set_attr "mode" "<IMODE>")]) | |
68 | ||
69 | (define_insn "ussub<mode>3" | |
70 | [(parallel | |
71 | [(set (match_operand:UADDSUB 0 "register_operand" "=d") | |
72 | (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") | |
73 | (match_operand:UADDSUB 2 "register_operand" "d"))) | |
74 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
75 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] | |
76 | "" | |
77 | "subu_s.<uaddsubfmt>\t%0,%1,%2" | |
78 | [(set_attr "type" "arith") | |
79 | (set_attr "mode" "<IMODE>")]) | |
80 | ||
81 | (define_insn "sssub<mode>3" | |
82 | [(parallel | |
83 | [(set (match_operand:ADDSUB 0 "register_operand" "=d") | |
84 | (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") | |
85 | (match_operand:ADDSUB 2 "register_operand" "d"))) | |
86 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
87 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] | |
88 | "TARGET_DSP" | |
89 | "subq_s.<addsubfmt>\t%0,%1,%2" | |
90 | [(set_attr "type" "arith") | |
91 | (set_attr "mode" "<IMODE>")]) | |
92 | ||
93 | (define_insn "ssmul<mode>3" | |
94 | [(parallel | |
95 | [(set (match_operand:MULQ 0 "register_operand" "=d") | |
96 | (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d") | |
97 | (match_operand:MULQ 2 "register_operand" "d"))) | |
98 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
99 | (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) | |
100 | (clobber (match_scratch:DI 3 "=x"))])] | |
101 | "" | |
102 | "mulq_rs.<mulqfmt>\t%0,%1,%2" | |
103 | [(set_attr "type" "imul3") | |
104 | (set_attr "mode" "<IMODE>")]) | |
105 | ||
106 | (define_insn "ssmaddsqdq4" | |
107 | [(parallel | |
108 | [(set (match_operand:DQ 0 "register_operand" "=a") | |
109 | (ss_plus:DQ | |
110 | (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 | |
111 | "register_operand" "d")) | |
112 | (sat_fract:DQ (match_operand:SQ 2 | |
113 | "register_operand" "d"))) | |
114 | (match_operand:DQ 3 "register_operand" "0"))) | |
115 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
116 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
117 | UNSPEC_DPAQ_SA_L_W))])] | |
118 | "TARGET_DSP && !TARGET_64BIT" | |
119 | "dpaq_sa.l.w\t%q0,%1,%2" | |
120 | [(set_attr "type" "imadd") | |
121 | (set_attr "mode" "SI")]) | |
122 | ||
123 | (define_insn "ssmsubsqdq4" | |
124 | [(parallel | |
125 | [(set (match_operand:DQ 0 "register_operand" "=a") | |
126 | (ss_minus:DQ | |
127 | (match_operand:DQ 3 "register_operand" "0") | |
128 | (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 | |
129 | "register_operand" "d")) | |
130 | (sat_fract:DQ (match_operand:SQ 2 | |
131 | "register_operand" "d"))))) | |
132 | (set (reg:CCDSP CCDSP_OU_REGNUM) | |
133 | (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] | |
134 | UNSPEC_DPSQ_SA_L_W))])] | |
135 | "TARGET_DSP && !TARGET_64BIT" | |
136 | "dpsq_sa.l.w\t%q0,%1,%2" | |
137 | [(set_attr "type" "imadd") | |
138 | (set_attr "mode" "SI")]) |