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dfad12b5 | 1 | /* Subroutines used for MIPS code generation. |
214be03f | 2 | Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
ef78aed6 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
770da00a | 4 | 2011, 2012 |
6fb5fa3c | 5 | Free Software Foundation, Inc. |
cee98a59 | 6 | Contributed by A. Lichnewsky, lich@inria.inria.fr. |
b2a68403 | 7 | Changes by Michael Meissner, meissner@osf.org. |
85f65093 | 8 | 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and |
147255d8 | 9 | Brendan Eich, brendan@microunity.com. |
cee98a59 | 10 | |
7ec022b2 | 11 | This file is part of GCC. |
cee98a59 | 12 | |
7ec022b2 | 13 | GCC is free software; you can redistribute it and/or modify |
cee98a59 | 14 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
cee98a59 MM |
16 | any later version. |
17 | ||
7ec022b2 | 18 | GCC is distributed in the hope that it will be useful, |
cee98a59 MM |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
24 | along with GCC; see the file COPYING3. If not see |
25 | <http://www.gnu.org/licenses/>. */ | |
cee98a59 MM |
26 | |
27 | #include "config.h" | |
50b2596f | 28 | #include "system.h" |
4977bab6 ZW |
29 | #include "coretypes.h" |
30 | #include "tm.h" | |
cee98a59 MM |
31 | #include "rtl.h" |
32 | #include "regs.h" | |
33 | #include "hard-reg-set.h" | |
cee98a59 MM |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
cee98a59 | 36 | #include "insn-attr.h" |
cee98a59 | 37 | #include "recog.h" |
c5c76735 | 38 | #include "output.h" |
cee98a59 | 39 | #include "tree.h" |
49ad7cfa | 40 | #include "function.h" |
cee98a59 | 41 | #include "expr.h" |
c15c90bb | 42 | #include "optabs.h" |
e2ff10a9 | 43 | #include "libfuncs.h" |
cee98a59 | 44 | #include "flags.h" |
2bcb2ab3 | 45 | #include "reload.h" |
bd9f1972 | 46 | #include "tm_p.h" |
d07d525a | 47 | #include "ggc.h" |
7719ffbf | 48 | #include "gstab.h" |
920ae24b RH |
49 | #include "hashtab.h" |
50 | #include "debug.h" | |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
cafe096b | 53 | #include "integrate.h" |
2743a50a | 54 | #include "langhooks.h" |
b85aed9e | 55 | #include "cfglayout.h" |
dc884a86 | 56 | #include "sched-int.h" |
726a989a | 57 | #include "gimple.h" |
912f2dac | 58 | #include "bitmap.h" |
566dfd71 | 59 | #include "diagnostic.h" |
5aa62249 | 60 | #include "target-globals.h" |
96e45421 | 61 | #include "opts.h" |
cee98a59 | 62 | |
65239d20 | 63 | /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ |
108b61d5 RS |
64 | #define UNSPEC_ADDRESS_P(X) \ |
65 | (GET_CODE (X) == UNSPEC \ | |
66 | && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ | |
67 | && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) | |
68 | ||
69 | /* Extract the symbol or label from UNSPEC wrapper X. */ | |
70 | #define UNSPEC_ADDRESS(X) \ | |
71 | XVECEXP (X, 0, 0) | |
72 | ||
73 | /* Extract the symbol type from UNSPEC wrapper X. */ | |
74 | #define UNSPEC_ADDRESS_TYPE(X) \ | |
75 | ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) | |
76 | ||
be763023 | 77 | /* The maximum distance between the top of the stack frame and the |
e1260576 RS |
78 | value $sp has when we save and restore registers. |
79 | ||
80 | The value for normal-mode code must be a SMALL_OPERAND and must | |
81 | preserve the maximum stack alignment. We therefore use a value | |
82 | of 0x7ff0 in this case. | |
83 | ||
84 | MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by | |
85 | up to 0x7f8 bytes and can usually save or restore all the registers | |
86 | that we need to save or restore. (Note that we can only use these | |
87 | instructions for o32, for which the stack alignment is 8 bytes.) | |
88 | ||
89 | We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and | |
90 | RESTORE are not available. We can then use unextended instructions | |
91 | to save and restore registers, and to allocate and deallocate the top | |
92 | part of the frame. */ | |
93 | #define MIPS_MAX_FIRST_STACK_STEP \ | |
94 | (!TARGET_MIPS16 ? 0x7ff0 \ | |
95 | : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \ | |
96 | : TARGET_64BIT ? 0x100 : 0x400) | |
be763023 | 97 | |
dc884a86 RS |
98 | /* True if INSN is a mips.md pattern or asm statement. */ |
99 | #define USEFUL_INSN_P(INSN) \ | |
006b29ab | 100 | (NONDEBUG_INSN_P (INSN) \ |
dc884a86 RS |
101 | && GET_CODE (PATTERN (INSN)) != USE \ |
102 | && GET_CODE (PATTERN (INSN)) != CLOBBER \ | |
103 | && GET_CODE (PATTERN (INSN)) != ADDR_VEC \ | |
104 | && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC) | |
105 | ||
106 | /* If INSN is a delayed branch sequence, return the first instruction | |
107 | in the sequence, otherwise return INSN itself. */ | |
108 | #define SEQ_BEGIN(INSN) \ | |
109 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
110 | ? XVECEXP (PATTERN (INSN), 0, 0) \ | |
111 | : (INSN)) | |
112 | ||
113 | /* Likewise for the last instruction in a delayed branch sequence. */ | |
114 | #define SEQ_END(INSN) \ | |
115 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
116 | ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \ | |
117 | : (INSN)) | |
118 | ||
119 | /* Execute the following loop body with SUBINSN set to each instruction | |
120 | between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */ | |
121 | #define FOR_EACH_SUBINSN(SUBINSN, INSN) \ | |
122 | for ((SUBINSN) = SEQ_BEGIN (INSN); \ | |
123 | (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \ | |
124 | (SUBINSN) = NEXT_INSN (SUBINSN)) | |
cafe096b | 125 | |
e1260576 RS |
126 | /* True if bit BIT is set in VALUE. */ |
127 | #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) | |
128 | ||
c640a3bd RS |
129 | /* Return the opcode for a ptr_mode load of the form: |
130 | ||
131 | l[wd] DEST, OFFSET(BASE). */ | |
132 | #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \ | |
133 | (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \ | |
134 | | ((BASE) << 21) \ | |
135 | | ((DEST) << 16) \ | |
136 | | (OFFSET)) | |
137 | ||
138 | /* Return the opcode to move register SRC into register DEST. */ | |
139 | #define MIPS_MOVE(DEST, SRC) \ | |
140 | ((TARGET_64BIT ? 0x2d : 0x21) \ | |
141 | | ((DEST) << 11) \ | |
142 | | ((SRC) << 21)) | |
143 | ||
144 | /* Return the opcode for: | |
145 | ||
146 | lui DEST, VALUE. */ | |
147 | #define MIPS_LUI(DEST, VALUE) \ | |
148 | ((0xf << 26) | ((DEST) << 16) | (VALUE)) | |
149 | ||
150 | /* Return the opcode to jump to register DEST. */ | |
151 | #define MIPS_JR(DEST) \ | |
152 | (((DEST) << 21) | 0x8) | |
153 | ||
154 | /* Return the opcode for: | |
155 | ||
156 | bal . + (1 + OFFSET) * 4. */ | |
157 | #define MIPS_BAL(OFFSET) \ | |
158 | ((0x1 << 26) | (0x11 << 16) | (OFFSET)) | |
159 | ||
160 | /* Return the usual opcode for a nop. */ | |
161 | #define MIPS_NOP 0 | |
162 | ||
cafe096b EC |
163 | /* Classifies an address. |
164 | ||
cafe096b EC |
165 | ADDRESS_REG |
166 | A natural register + offset address. The register satisfies | |
167 | mips_valid_base_register_p and the offset is a const_arith_operand. | |
168 | ||
169 | ADDRESS_LO_SUM | |
170 | A LO_SUM rtx. The first operand is a valid base register and | |
171 | the second operand is a symbolic address. | |
172 | ||
173 | ADDRESS_CONST_INT | |
174 | A signed 16-bit constant address. | |
175 | ||
176 | ADDRESS_SYMBOLIC: | |
65239d20 | 177 | A constant symbolic address. */ |
cafe096b | 178 | enum mips_address_type { |
cafe096b EC |
179 | ADDRESS_REG, |
180 | ADDRESS_LO_SUM, | |
181 | ADDRESS_CONST_INT, | |
182 | ADDRESS_SYMBOLIC | |
183 | }; | |
184 | ||
41030557 RS |
185 | /* Macros to create an enumeration identifier for a function prototype. */ |
186 | #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B | |
187 | #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C | |
188 | #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D | |
189 | #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E | |
190 | ||
65239d20 RS |
191 | /* Classifies the prototype of a built-in function. */ |
192 | enum mips_function_type { | |
41030557 RS |
193 | #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST, |
194 | #include "config/mips/mips-ftypes.def" | |
195 | #undef DEF_MIPS_FTYPE | |
4ca1f68f RS |
196 | MIPS_MAX_FTYPE_MAX |
197 | }; | |
198 | ||
65239d20 RS |
199 | /* Specifies how a built-in function should be converted into rtl. */ |
200 | enum mips_builtin_type { | |
201 | /* The function corresponds directly to an .md pattern. The return | |
4ca1f68f RS |
202 | value is mapped to operand 0 and the arguments are mapped to |
203 | operands 1 and above. */ | |
204 | MIPS_BUILTIN_DIRECT, | |
205 | ||
65239d20 | 206 | /* The function corresponds directly to an .md pattern. There is no return |
118ea793 CF |
207 | value and the arguments are mapped to operands 0 and above. */ |
208 | MIPS_BUILTIN_DIRECT_NO_TARGET, | |
209 | ||
65239d20 | 210 | /* The function corresponds to a comparison instruction followed by |
4ca1f68f RS |
211 | a mips_cond_move_tf_ps pattern. The first two arguments are the |
212 | values to compare and the second two arguments are the vector | |
213 | operands for the movt.ps or movf.ps instruction (in assembly order). */ | |
214 | MIPS_BUILTIN_MOVF, | |
215 | MIPS_BUILTIN_MOVT, | |
216 | ||
65239d20 | 217 | /* The function corresponds to a V2SF comparison instruction. Operand 0 |
4ca1f68f RS |
218 | of this instruction is the result of the comparison, which has mode |
219 | CCV2 or CCV4. The function arguments are mapped to operands 1 and | |
220 | above. The function's return value is an SImode boolean that is | |
221 | true under the following conditions: | |
222 | ||
223 | MIPS_BUILTIN_CMP_ANY: one of the registers is true | |
224 | MIPS_BUILTIN_CMP_ALL: all of the registers are true | |
225 | MIPS_BUILTIN_CMP_LOWER: the first register is true | |
226 | MIPS_BUILTIN_CMP_UPPER: the second register is true. */ | |
227 | MIPS_BUILTIN_CMP_ANY, | |
228 | MIPS_BUILTIN_CMP_ALL, | |
229 | MIPS_BUILTIN_CMP_UPPER, | |
230 | MIPS_BUILTIN_CMP_LOWER, | |
231 | ||
232 | /* As above, but the instruction only sets a single $fcc register. */ | |
118ea793 CF |
233 | MIPS_BUILTIN_CMP_SINGLE, |
234 | ||
235 | /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ | |
236 | MIPS_BUILTIN_BPOSGE32 | |
4ca1f68f RS |
237 | }; |
238 | ||
65239d20 | 239 | /* Invoke MACRO (COND) for each C.cond.fmt condition. */ |
308cd611 RS |
240 | #define MIPS_FP_CONDITIONS(MACRO) \ |
241 | MACRO (f), \ | |
242 | MACRO (un), \ | |
243 | MACRO (eq), \ | |
244 | MACRO (ueq), \ | |
245 | MACRO (olt), \ | |
246 | MACRO (ult), \ | |
247 | MACRO (ole), \ | |
248 | MACRO (ule), \ | |
249 | MACRO (sf), \ | |
250 | MACRO (ngle), \ | |
251 | MACRO (seq), \ | |
252 | MACRO (ngl), \ | |
253 | MACRO (lt), \ | |
254 | MACRO (nge), \ | |
255 | MACRO (le), \ | |
256 | MACRO (ngt) | |
257 | ||
258 | /* Enumerates the codes above as MIPS_FP_COND_<X>. */ | |
259 | #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X | |
260 | enum mips_fp_condition { | |
261 | MIPS_FP_CONDITIONS (DECLARE_MIPS_COND) | |
262 | }; | |
263 | ||
264 | /* Index X provides the string representation of MIPS_FP_COND_<X>. */ | |
265 | #define STRINGIFY(X) #X | |
266 | static const char *const mips_fp_conditions[] = { | |
267 | MIPS_FP_CONDITIONS (STRINGIFY) | |
268 | }; | |
269 | ||
16dc5c28 | 270 | /* Information about a function's frame layout. */ |
d1b38208 | 271 | struct GTY(()) mips_frame_info { |
37017f4d RS |
272 | /* The size of the frame in bytes. */ |
273 | HOST_WIDE_INT total_size; | |
274 | ||
275 | /* The number of bytes allocated to variables. */ | |
276 | HOST_WIDE_INT var_size; | |
277 | ||
278 | /* The number of bytes allocated to outgoing function arguments. */ | |
279 | HOST_WIDE_INT args_size; | |
280 | ||
281 | /* The number of bytes allocated to the .cprestore slot, or 0 if there | |
282 | is no such slot. */ | |
283 | HOST_WIDE_INT cprestore_size; | |
284 | ||
37017f4d RS |
285 | /* Bit X is set if the function saves or restores GPR X. */ |
286 | unsigned int mask; | |
287 | ||
288 | /* Likewise FPR X. */ | |
289 | unsigned int fmask; | |
290 | ||
e19da24c CF |
291 | /* Likewise doubleword accumulator X ($acX). */ |
292 | unsigned int acc_mask; | |
293 | ||
294 | /* The number of GPRs, FPRs, doubleword accumulators and COP0 | |
295 | registers saved. */ | |
37017f4d RS |
296 | unsigned int num_gp; |
297 | unsigned int num_fp; | |
e19da24c CF |
298 | unsigned int num_acc; |
299 | unsigned int num_cop0_regs; | |
37017f4d | 300 | |
e19da24c CF |
301 | /* The offset of the topmost GPR, FPR, accumulator and COP0-register |
302 | save slots from the top of the frame, or zero if no such slots are | |
303 | needed. */ | |
37017f4d RS |
304 | HOST_WIDE_INT gp_save_offset; |
305 | HOST_WIDE_INT fp_save_offset; | |
e19da24c CF |
306 | HOST_WIDE_INT acc_save_offset; |
307 | HOST_WIDE_INT cop0_save_offset; | |
37017f4d RS |
308 | |
309 | /* Likewise, but giving offsets from the bottom of the frame. */ | |
310 | HOST_WIDE_INT gp_sp_offset; | |
311 | HOST_WIDE_INT fp_sp_offset; | |
e19da24c CF |
312 | HOST_WIDE_INT acc_sp_offset; |
313 | HOST_WIDE_INT cop0_sp_offset; | |
37017f4d | 314 | |
c376dbfb DD |
315 | /* Similar, but the value passed to _mcount. */ |
316 | HOST_WIDE_INT ra_fp_offset; | |
317 | ||
ba6adec4 | 318 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ |
f374e413 RS |
319 | HOST_WIDE_INT arg_pointer_offset; |
320 | ||
ba6adec4 | 321 | /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ |
f374e413 | 322 | HOST_WIDE_INT hard_frame_pointer_offset; |
b2471838 RS |
323 | }; |
324 | ||
d1b38208 | 325 | struct GTY(()) machine_function { |
65239d20 | 326 | /* The register returned by mips16_gp_pseudo_reg; see there for details. */ |
c8d1b2b7 | 327 | rtx mips16_gp_pseudo_rtx; |
b2471838 | 328 | |
4001cd89 RS |
329 | /* The number of extra stack bytes taken up by register varargs. |
330 | This area is allocated by the callee at the very top of the frame. */ | |
331 | int varargs_size; | |
332 | ||
65239d20 | 333 | /* The current frame information, calculated by mips_compute_frame_info. */ |
b2471838 RS |
334 | struct mips_frame_info frame; |
335 | ||
8d9d9172 RS |
336 | /* The register to use as the function's global pointer, or INVALID_REGNUM |
337 | if the function doesn't need one. */ | |
f833ffd4 | 338 | unsigned int global_pointer; |
6f2993e5 | 339 | |
0c433c31 RS |
340 | /* How many instructions it takes to load a label into $AT, or 0 if |
341 | this property hasn't yet been calculated. */ | |
5a486834 | 342 | unsigned int load_label_num_insns; |
0c433c31 | 343 | |
6f2993e5 RS |
344 | /* True if mips_adjust_insn_length should ignore an instruction's |
345 | hazard attribute. */ | |
346 | bool ignore_hazard_length_p; | |
347 | ||
348 | /* True if the whole function is suitable for .set noreorder and | |
349 | .set nomacro. */ | |
350 | bool all_noreorder_p; | |
108b61d5 | 351 | |
0c433c31 RS |
352 | /* True if the function has "inflexible" and "flexible" references |
353 | to the global pointer. See mips_cfun_has_inflexible_gp_ref_p | |
354 | and mips_cfun_has_flexible_gp_ref_p for details. */ | |
355 | bool has_inflexible_gp_insn_p; | |
356 | bool has_flexible_gp_insn_p; | |
357 | ||
358 | /* True if the function's prologue must load the global pointer | |
359 | value into pic_offset_table_rtx and store the same value in | |
360 | the function's cprestore slot (if any). Even if this value | |
361 | is currently false, we may decide to set it to true later; | |
362 | see mips_must_initialize_gp_p () for details. */ | |
363 | bool must_initialize_gp_p; | |
364 | ||
365 | /* True if the current function must restore $gp after any potential | |
366 | clobber. This value is only meaningful during the first post-epilogue | |
367 | split_insns pass; see mips_must_initialize_gp_p () for details. */ | |
368 | bool must_restore_gp_when_clobbered_p; | |
d6076cee | 369 | |
e19da24c CF |
370 | /* True if this is an interrupt handler. */ |
371 | bool interrupt_handler_p; | |
372 | ||
373 | /* True if this is an interrupt handler that uses shadow registers. */ | |
374 | bool use_shadow_register_set_p; | |
375 | ||
376 | /* True if this is an interrupt handler that should keep interrupts | |
377 | masked. */ | |
378 | bool keep_interrupts_masked_p; | |
379 | ||
380 | /* True if this is an interrupt handler that should use DERET | |
381 | instead of ERET. */ | |
382 | bool use_debug_exception_return_p; | |
c8d1b2b7 AO |
383 | }; |
384 | ||
4d72536e | 385 | /* Information about a single argument. */ |
65239d20 | 386 | struct mips_arg_info { |
4d72536e RS |
387 | /* True if the argument is passed in a floating-point register, or |
388 | would have been if we hadn't run out of registers. */ | |
389 | bool fpr_p; | |
390 | ||
4d72536e RS |
391 | /* The number of words passed in registers, rounded up. */ |
392 | unsigned int reg_words; | |
393 | ||
b11a9d5f RS |
394 | /* For EABI, the offset of the first register from GP_ARG_FIRST or |
395 | FP_ARG_FIRST. For other ABIs, the offset of the first register from | |
396 | the start of the ABI's argument structure (see the CUMULATIVE_ARGS | |
397 | comment for details). | |
398 | ||
399 | The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely | |
4d72536e RS |
400 | on the stack. */ |
401 | unsigned int reg_offset; | |
402 | ||
403 | /* The number of words that must be passed on the stack, rounded up. */ | |
404 | unsigned int stack_words; | |
405 | ||
406 | /* The offset from the start of the stack overflow area of the argument's | |
a0ab749a | 407 | first stack word. Only meaningful when STACK_WORDS is nonzero. */ |
4d72536e RS |
408 | unsigned int stack_offset; |
409 | }; | |
c8d1b2b7 | 410 | |
cafe096b EC |
411 | /* Information about an address described by mips_address_type. |
412 | ||
cafe096b EC |
413 | ADDRESS_CONST_INT |
414 | No fields are used. | |
415 | ||
416 | ADDRESS_REG | |
417 | REG is the base register and OFFSET is the constant offset. | |
418 | ||
419 | ADDRESS_LO_SUM | |
65239d20 RS |
420 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE |
421 | is the type of symbol it references. | |
cafe096b EC |
422 | |
423 | ADDRESS_SYMBOLIC | |
65239d20 RS |
424 | SYMBOL_TYPE is the type of symbol that the address references. */ |
425 | struct mips_address_info { | |
108b61d5 | 426 | enum mips_address_type type; |
cafe096b EC |
427 | rtx reg; |
428 | rtx offset; | |
108b61d5 | 429 | enum mips_symbol_type symbol_type; |
cafe096b EC |
430 | }; |
431 | ||
b259a9a6 RS |
432 | /* One stage in a constant building sequence. These sequences have |
433 | the form: | |
434 | ||
435 | A = VALUE[0] | |
436 | A = A CODE[1] VALUE[1] | |
437 | A = A CODE[2] VALUE[2] | |
438 | ... | |
439 | ||
440 | where A is an accumulator, each CODE[i] is a binary rtl operation | |
65239d20 | 441 | and each VALUE[i] is a constant integer. CODE[0] is undefined. */ |
b259a9a6 RS |
442 | struct mips_integer_op { |
443 | enum rtx_code code; | |
444 | unsigned HOST_WIDE_INT value; | |
445 | }; | |
446 | ||
b259a9a6 RS |
447 | /* The largest number of operations needed to load an integer constant. |
448 | The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. | |
449 | When the lowest bit is clear, we can try, but reject a sequence with | |
450 | an extra SLL at the end. */ | |
451 | #define MIPS_MAX_INTEGER_OPS 7 | |
452 | ||
e1260576 RS |
453 | /* Information about a MIPS16e SAVE or RESTORE instruction. */ |
454 | struct mips16e_save_restore_info { | |
455 | /* The number of argument registers saved by a SAVE instruction. | |
456 | 0 for RESTORE instructions. */ | |
457 | unsigned int nargs; | |
458 | ||
459 | /* Bit X is set if the instruction saves or restores GPR X. */ | |
460 | unsigned int mask; | |
461 | ||
462 | /* The total number of bytes to allocate. */ | |
463 | HOST_WIDE_INT size; | |
464 | }; | |
b259a9a6 | 465 | |
faa832a7 AS |
466 | /* Costs of various operations on the different architectures. */ |
467 | ||
468 | struct mips_rtx_cost_data | |
469 | { | |
470 | unsigned short fp_add; | |
471 | unsigned short fp_mult_sf; | |
472 | unsigned short fp_mult_df; | |
473 | unsigned short fp_div_sf; | |
474 | unsigned short fp_div_df; | |
475 | unsigned short int_mult_si; | |
476 | unsigned short int_mult_di; | |
477 | unsigned short int_div_si; | |
478 | unsigned short int_div_di; | |
479 | unsigned short branch_cost; | |
480 | unsigned short memory_latency; | |
481 | }; | |
482 | ||
cee98a59 MM |
483 | /* Global variables for machine-dependent things. */ |
484 | ||
65239d20 RS |
485 | /* The -G setting, or the configuration's default small-data limit if |
486 | no -G option is given. */ | |
487 | static unsigned int mips_small_data_threshold; | |
cee98a59 | 488 | |
65239d20 RS |
489 | /* The number of file directives written by mips_output_filename. */ |
490 | int num_source_filenames; | |
cee98a59 | 491 | |
65239d20 RS |
492 | /* The name that appeared in the last .file directive written by |
493 | mips_output_filename, or "" if mips_output_filename hasn't | |
494 | written anything yet. */ | |
ab77a036 RS |
495 | const char *current_function_file = ""; |
496 | ||
65239d20 RS |
497 | /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */ |
498 | int sdb_label_count; | |
cee98a59 | 499 | |
65239d20 | 500 | /* Arrays that map GCC register numbers to debugger register numbers. */ |
ab77a036 RS |
501 | int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; |
502 | int mips_dwarf_regno[FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 503 | |
3bd0817d RS |
504 | /* Information about the current function's epilogue, used only while |
505 | expanding it. */ | |
506 | static struct { | |
507 | /* A list of queued REG_CFA_RESTORE notes. */ | |
508 | rtx cfa_restores; | |
509 | ||
510 | /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */ | |
511 | rtx cfa_reg; | |
512 | HOST_WIDE_INT cfa_offset; | |
513 | ||
514 | /* The offset of the CFA from the stack pointer while restoring | |
515 | registers. */ | |
516 | HOST_WIDE_INT cfa_restore_sp_offset; | |
517 | } mips_epilogue; | |
518 | ||
65239d20 | 519 | /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */ |
cf5fb4b0 RS |
520 | struct mips_asm_switch mips_noreorder = { "reorder", 0 }; |
521 | struct mips_asm_switch mips_nomacro = { "macro", 0 }; | |
522 | struct mips_asm_switch mips_noat = { "at", 0 }; | |
cee98a59 | 523 | |
65239d20 RS |
524 | /* True if we're writing out a branch-likely instruction rather than a |
525 | normal branch. */ | |
526 | static bool mips_branch_likely; | |
cee98a59 | 527 | |
65239d20 | 528 | /* The current instruction-set architecture. */ |
24609606 | 529 | enum processor mips_arch; |
a27fb29b | 530 | const struct mips_cpu_info *mips_arch_info; |
7dac2f89 | 531 | |
65239d20 | 532 | /* The processor that we should tune the code for. */ |
24609606 | 533 | enum processor mips_tune; |
a27fb29b | 534 | const struct mips_cpu_info *mips_tune_info; |
7dac2f89 | 535 | |
65239d20 | 536 | /* The ISA level associated with mips_arch. */ |
cee98a59 MM |
537 | int mips_isa; |
538 | ||
65239d20 RS |
539 | /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */ |
540 | static const struct mips_cpu_info *mips_isa_option_info; | |
ab77a036 | 541 | |
65239d20 | 542 | /* Which cost information to use. */ |
faa832a7 | 543 | static const struct mips_rtx_cost_data *mips_cost; |
c1bd2d66 | 544 | |
65239d20 | 545 | /* The ambient target flags, excluding MASK_MIPS16. */ |
f9e4a411 | 546 | static int mips_base_target_flags; |
65239d20 RS |
547 | |
548 | /* True if MIPS16 is the default mode. */ | |
60730ade | 549 | bool mips_base_mips16; |
65239d20 RS |
550 | |
551 | /* The ambient values of other global variables. */ | |
f9e4a411 SL |
552 | static int mips_base_schedule_insns; /* flag_schedule_insns */ |
553 | static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */ | |
8d1d0dee | 554 | static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */ |
f9e4a411 SL |
555 | static int mips_base_align_loops; /* align_loops */ |
556 | static int mips_base_align_jumps; /* align_jumps */ | |
557 | static int mips_base_align_functions; /* align_functions */ | |
f9e4a411 | 558 | |
65239d20 RS |
559 | /* Index [M][R] is true if register R is allowed to hold a value of mode M. */ |
560 | bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 561 | |
65239d20 RS |
562 | /* Index C is true if character C is a valid PRINT_OPERAND punctation |
563 | character. */ | |
6e9e0126 | 564 | static bool mips_print_operand_punct[256]; |
cee98a59 | 565 | |
cafe096b EC |
566 | static GTY (()) int mips_output_filename_first_time = 1; |
567 | ||
108b61d5 | 568 | /* mips_split_p[X] is true if symbols of type X can be split by |
65239d20 | 569 | mips_split_symbol. */ |
ea462dd0 | 570 | bool mips_split_p[NUM_SYMBOL_TYPES]; |
108b61d5 | 571 | |
08d0963a RS |
572 | /* mips_split_hi_p[X] is true if the high parts of symbols of type X |
573 | can be split by mips_split_symbol. */ | |
574 | bool mips_split_hi_p[NUM_SYMBOL_TYPES]; | |
575 | ||
ddaf8125 RS |
576 | /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be |
577 | forced into a PC-relative constant pool. */ | |
578 | bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES]; | |
579 | ||
108b61d5 RS |
580 | /* mips_lo_relocs[X] is the relocation to use when a symbol of type X |
581 | appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or | |
582 | if they are matched by a special .md file pattern. */ | |
ddaf8125 | 583 | const char *mips_lo_relocs[NUM_SYMBOL_TYPES]; |
108b61d5 RS |
584 | |
585 | /* Likewise for HIGHs. */ | |
ddaf8125 | 586 | const char *mips_hi_relocs[NUM_SYMBOL_TYPES]; |
108b61d5 | 587 | |
5aa62249 RS |
588 | /* Target state for MIPS16. */ |
589 | struct target_globals *mips16_globals; | |
590 | ||
646e6f41 JZ |
591 | /* Cached value of can_issue_more. This is cached in mips_variable_issue hook |
592 | and returned from mips_sched_reorder2. */ | |
593 | static int cached_can_issue_more; | |
594 | ||
65239d20 RS |
595 | /* Index R is the smallest register class that contains register R. */ |
596 | const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { | |
08d0963a | 597 | LEA_REGS, LEA_REGS, M16_REGS, V1_REG, |
2bcb2ab3 | 598 | M16_REGS, M16_REGS, M16_REGS, M16_REGS, |
cafe096b EC |
599 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, |
600 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
08d0963a | 601 | M16_REGS, M16_REGS, LEA_REGS, LEA_REGS, |
cafe096b EC |
602 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, |
603 | T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, | |
604 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
cee98a59 MM |
605 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
606 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
607 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
608 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
609 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
610 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
611 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
612 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
48156a39 | 613 | MD0_REG, MD1_REG, NO_REGS, ST_REGS, |
b8eb88d0 | 614 | ST_REGS, ST_REGS, ST_REGS, ST_REGS, |
cafe096b | 615 | ST_REGS, ST_REGS, ST_REGS, NO_REGS, |
7314c7dd | 616 | NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS, |
d604bca3 MH |
617 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, |
618 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
619 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
620 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
621 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
622 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
623 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
624 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
625 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
626 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
627 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
628 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
629 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
630 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
631 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
632 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
633 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
634 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
635 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
636 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
637 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
638 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
639 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
118ea793 CF |
640 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, |
641 | DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, | |
642 | DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS, | |
643 | ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS | |
cee98a59 MM |
644 | }; |
645 | ||
65239d20 | 646 | /* The value of TARGET_ATTRIBUTE_TABLE. */ |
6bc7bc14 | 647 | static const struct attribute_spec mips_attribute_table[] = { |
62d784f7 KT |
648 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
649 | om_diagnostic } */ | |
650 | { "long_call", 0, 0, false, true, true, NULL, false }, | |
651 | { "far", 0, 0, false, true, true, NULL, false }, | |
652 | { "near", 0, 0, false, true, true, NULL, false }, | |
65239d20 RS |
653 | /* We would really like to treat "mips16" and "nomips16" as type |
654 | attributes, but GCC doesn't provide the hooks we need to support | |
655 | the right conversion rules. As declaration attributes, they affect | |
656 | code generation but don't carry other semantics. */ | |
62d784f7 KT |
657 | { "mips16", 0, 0, true, false, false, NULL, false }, |
658 | { "nomips16", 0, 0, true, false, false, NULL, false }, | |
e19da24c | 659 | /* Allow functions to be specified as interrupt handlers */ |
62d784f7 KT |
660 | { "interrupt", 0, 0, false, true, true, NULL, false }, |
661 | { "use_shadow_register_set", 0, 0, false, true, true, NULL, false }, | |
662 | { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false }, | |
663 | { "use_debug_exception_return", 0, 0, false, true, true, NULL, false }, | |
664 | { NULL, 0, 0, false, false, false, NULL, false } | |
4dbdb061 | 665 | }; |
672a6f42 | 666 | \f |
d371df6f JM |
667 | /* A table describing all the processors GCC knows about; see |
668 | mips-cpus.def for details. */ | |
65239d20 | 669 | static const struct mips_cpu_info mips_cpu_info_table[] = { |
d371df6f JM |
670 | #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \ |
671 | { NAME, CPU, ISA, FLAGS }, | |
672 | #include "mips-cpus.def" | |
673 | #undef MIPS_CPU | |
a27fb29b | 674 | }; |
c1bd2d66 | 675 | |
65239d20 | 676 | /* Default costs. If these are used for a processor we should look |
ff5c4582 | 677 | up the actual costs. */ |
c1bd2d66 EC |
678 | #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ |
679 | COSTS_N_INSNS (7), /* fp_mult_sf */ \ | |
680 | COSTS_N_INSNS (8), /* fp_mult_df */ \ | |
681 | COSTS_N_INSNS (23), /* fp_div_sf */ \ | |
682 | COSTS_N_INSNS (36), /* fp_div_df */ \ | |
683 | COSTS_N_INSNS (10), /* int_mult_si */ \ | |
684 | COSTS_N_INSNS (10), /* int_mult_di */ \ | |
685 | COSTS_N_INSNS (69), /* int_div_si */ \ | |
686 | COSTS_N_INSNS (69), /* int_div_di */ \ | |
687 | 2, /* branch_cost */ \ | |
688 | 4 /* memory_latency */ | |
689 | ||
65239d20 RS |
690 | /* Floating-point costs for processors without an FPU. Just assume that |
691 | all floating-point libcalls are very expensive. */ | |
c1bd2d66 EC |
692 | #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ |
693 | COSTS_N_INSNS (256), /* fp_mult_sf */ \ | |
694 | COSTS_N_INSNS (256), /* fp_mult_df */ \ | |
695 | COSTS_N_INSNS (256), /* fp_div_sf */ \ | |
696 | COSTS_N_INSNS (256) /* fp_div_df */ | |
697 | ||
65239d20 RS |
698 | /* Costs to use when optimizing for size. */ |
699 | static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { | |
700 | COSTS_N_INSNS (1), /* fp_add */ | |
701 | COSTS_N_INSNS (1), /* fp_mult_sf */ | |
702 | COSTS_N_INSNS (1), /* fp_mult_df */ | |
703 | COSTS_N_INSNS (1), /* fp_div_sf */ | |
704 | COSTS_N_INSNS (1), /* fp_div_df */ | |
705 | COSTS_N_INSNS (1), /* int_mult_si */ | |
706 | COSTS_N_INSNS (1), /* int_mult_di */ | |
707 | COSTS_N_INSNS (1), /* int_div_si */ | |
708 | COSTS_N_INSNS (1), /* int_div_di */ | |
709 | 2, /* branch_cost */ | |
710 | 4 /* memory_latency */ | |
711 | }; | |
712 | ||
713 | /* Costs to use when optimizing for speed, indexed by processor. */ | |
24609606 RS |
714 | static const struct mips_rtx_cost_data |
715 | mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = { | |
65239d20 RS |
716 | { /* R3000 */ |
717 | COSTS_N_INSNS (2), /* fp_add */ | |
718 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
719 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
720 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
721 | COSTS_N_INSNS (19), /* fp_div_df */ | |
722 | COSTS_N_INSNS (12), /* int_mult_si */ | |
723 | COSTS_N_INSNS (12), /* int_mult_di */ | |
724 | COSTS_N_INSNS (35), /* int_div_si */ | |
725 | COSTS_N_INSNS (35), /* int_div_di */ | |
726 | 1, /* branch_cost */ | |
727 | 4 /* memory_latency */ | |
728 | }, | |
729 | { /* 4KC */ | |
730 | SOFT_FP_COSTS, | |
731 | COSTS_N_INSNS (6), /* int_mult_si */ | |
732 | COSTS_N_INSNS (6), /* int_mult_di */ | |
733 | COSTS_N_INSNS (36), /* int_div_si */ | |
734 | COSTS_N_INSNS (36), /* int_div_di */ | |
735 | 1, /* branch_cost */ | |
736 | 4 /* memory_latency */ | |
737 | }, | |
738 | { /* 4KP */ | |
739 | SOFT_FP_COSTS, | |
740 | COSTS_N_INSNS (36), /* int_mult_si */ | |
741 | COSTS_N_INSNS (36), /* int_mult_di */ | |
742 | COSTS_N_INSNS (37), /* int_div_si */ | |
743 | COSTS_N_INSNS (37), /* int_div_di */ | |
744 | 1, /* branch_cost */ | |
745 | 4 /* memory_latency */ | |
746 | }, | |
747 | { /* 5KC */ | |
748 | SOFT_FP_COSTS, | |
749 | COSTS_N_INSNS (4), /* int_mult_si */ | |
750 | COSTS_N_INSNS (11), /* int_mult_di */ | |
751 | COSTS_N_INSNS (36), /* int_div_si */ | |
752 | COSTS_N_INSNS (68), /* int_div_di */ | |
753 | 1, /* branch_cost */ | |
754 | 4 /* memory_latency */ | |
755 | }, | |
756 | { /* 5KF */ | |
757 | COSTS_N_INSNS (4), /* fp_add */ | |
758 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
759 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
760 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
761 | COSTS_N_INSNS (32), /* fp_div_df */ | |
762 | COSTS_N_INSNS (4), /* int_mult_si */ | |
763 | COSTS_N_INSNS (11), /* int_mult_di */ | |
764 | COSTS_N_INSNS (36), /* int_div_si */ | |
765 | COSTS_N_INSNS (68), /* int_div_di */ | |
766 | 1, /* branch_cost */ | |
767 | 4 /* memory_latency */ | |
768 | }, | |
769 | { /* 20KC */ | |
770 | COSTS_N_INSNS (4), /* fp_add */ | |
771 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
772 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
773 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
774 | COSTS_N_INSNS (32), /* fp_div_df */ | |
775 | COSTS_N_INSNS (4), /* int_mult_si */ | |
776 | COSTS_N_INSNS (7), /* int_mult_di */ | |
777 | COSTS_N_INSNS (42), /* int_div_si */ | |
778 | COSTS_N_INSNS (72), /* int_div_di */ | |
779 | 1, /* branch_cost */ | |
780 | 4 /* memory_latency */ | |
781 | }, | |
782 | { /* 24KC */ | |
783 | SOFT_FP_COSTS, | |
784 | COSTS_N_INSNS (5), /* int_mult_si */ | |
785 | COSTS_N_INSNS (5), /* int_mult_di */ | |
786 | COSTS_N_INSNS (41), /* int_div_si */ | |
787 | COSTS_N_INSNS (41), /* int_div_di */ | |
788 | 1, /* branch_cost */ | |
789 | 4 /* memory_latency */ | |
790 | }, | |
791 | { /* 24KF2_1 */ | |
792 | COSTS_N_INSNS (8), /* fp_add */ | |
793 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
794 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
795 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
796 | COSTS_N_INSNS (64), /* fp_div_df */ | |
797 | COSTS_N_INSNS (5), /* int_mult_si */ | |
798 | COSTS_N_INSNS (5), /* int_mult_di */ | |
799 | COSTS_N_INSNS (41), /* int_div_si */ | |
800 | COSTS_N_INSNS (41), /* int_div_di */ | |
801 | 1, /* branch_cost */ | |
802 | 4 /* memory_latency */ | |
803 | }, | |
804 | { /* 24KF1_1 */ | |
805 | COSTS_N_INSNS (4), /* fp_add */ | |
806 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
807 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
808 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
809 | COSTS_N_INSNS (32), /* fp_div_df */ | |
810 | COSTS_N_INSNS (5), /* int_mult_si */ | |
811 | COSTS_N_INSNS (5), /* int_mult_di */ | |
812 | COSTS_N_INSNS (41), /* int_div_si */ | |
813 | COSTS_N_INSNS (41), /* int_div_di */ | |
814 | 1, /* branch_cost */ | |
815 | 4 /* memory_latency */ | |
816 | }, | |
817 | { /* 74KC */ | |
818 | SOFT_FP_COSTS, | |
819 | COSTS_N_INSNS (5), /* int_mult_si */ | |
820 | COSTS_N_INSNS (5), /* int_mult_di */ | |
821 | COSTS_N_INSNS (41), /* int_div_si */ | |
822 | COSTS_N_INSNS (41), /* int_div_di */ | |
823 | 1, /* branch_cost */ | |
824 | 4 /* memory_latency */ | |
825 | }, | |
826 | { /* 74KF2_1 */ | |
827 | COSTS_N_INSNS (8), /* fp_add */ | |
828 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
829 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
830 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
831 | COSTS_N_INSNS (64), /* fp_div_df */ | |
832 | COSTS_N_INSNS (5), /* int_mult_si */ | |
833 | COSTS_N_INSNS (5), /* int_mult_di */ | |
834 | COSTS_N_INSNS (41), /* int_div_si */ | |
835 | COSTS_N_INSNS (41), /* int_div_di */ | |
836 | 1, /* branch_cost */ | |
837 | 4 /* memory_latency */ | |
838 | }, | |
839 | { /* 74KF1_1 */ | |
840 | COSTS_N_INSNS (4), /* fp_add */ | |
841 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
842 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
843 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
844 | COSTS_N_INSNS (32), /* fp_div_df */ | |
845 | COSTS_N_INSNS (5), /* int_mult_si */ | |
846 | COSTS_N_INSNS (5), /* int_mult_di */ | |
847 | COSTS_N_INSNS (41), /* int_div_si */ | |
848 | COSTS_N_INSNS (41), /* int_div_di */ | |
849 | 1, /* branch_cost */ | |
850 | 4 /* memory_latency */ | |
851 | }, | |
852 | { /* 74KF3_2 */ | |
853 | COSTS_N_INSNS (6), /* fp_add */ | |
854 | COSTS_N_INSNS (6), /* fp_mult_sf */ | |
855 | COSTS_N_INSNS (7), /* fp_mult_df */ | |
856 | COSTS_N_INSNS (25), /* fp_div_sf */ | |
857 | COSTS_N_INSNS (48), /* fp_div_df */ | |
858 | COSTS_N_INSNS (5), /* int_mult_si */ | |
859 | COSTS_N_INSNS (5), /* int_mult_di */ | |
860 | COSTS_N_INSNS (41), /* int_div_si */ | |
861 | COSTS_N_INSNS (41), /* int_div_di */ | |
862 | 1, /* branch_cost */ | |
863 | 4 /* memory_latency */ | |
864 | }, | |
33db2060 MS |
865 | { /* Loongson-2E */ |
866 | DEFAULT_COSTS | |
867 | }, | |
868 | { /* Loongson-2F */ | |
869 | DEFAULT_COSTS | |
870 | }, | |
98824c6f MS |
871 | { /* Loongson-3A */ |
872 | DEFAULT_COSTS | |
873 | }, | |
65239d20 RS |
874 | { /* M4k */ |
875 | DEFAULT_COSTS | |
d97e6aca AN |
876 | }, |
877 | /* Octeon */ | |
878 | { | |
879 | SOFT_FP_COSTS, | |
880 | COSTS_N_INSNS (5), /* int_mult_si */ | |
881 | COSTS_N_INSNS (5), /* int_mult_di */ | |
882 | COSTS_N_INSNS (72), /* int_div_si */ | |
883 | COSTS_N_INSNS (72), /* int_div_di */ | |
884 | 1, /* branch_cost */ | |
885 | 4 /* memory_latency */ | |
38a53a0e AP |
886 | }, |
887 | /* Octeon II */ | |
888 | { | |
889 | SOFT_FP_COSTS, | |
890 | COSTS_N_INSNS (6), /* int_mult_si */ | |
891 | COSTS_N_INSNS (6), /* int_mult_di */ | |
892 | COSTS_N_INSNS (18), /* int_div_si */ | |
893 | COSTS_N_INSNS (35), /* int_div_di */ | |
894 | 4, /* branch_cost */ | |
895 | 4 /* memory_latency */ | |
65239d20 RS |
896 | }, |
897 | { /* R3900 */ | |
898 | COSTS_N_INSNS (2), /* fp_add */ | |
899 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
900 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
901 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
902 | COSTS_N_INSNS (19), /* fp_div_df */ | |
903 | COSTS_N_INSNS (2), /* int_mult_si */ | |
904 | COSTS_N_INSNS (2), /* int_mult_di */ | |
905 | COSTS_N_INSNS (35), /* int_div_si */ | |
906 | COSTS_N_INSNS (35), /* int_div_di */ | |
907 | 1, /* branch_cost */ | |
908 | 4 /* memory_latency */ | |
909 | }, | |
910 | { /* R6000 */ | |
911 | COSTS_N_INSNS (3), /* fp_add */ | |
912 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
913 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
914 | COSTS_N_INSNS (15), /* fp_div_sf */ | |
915 | COSTS_N_INSNS (16), /* fp_div_df */ | |
916 | COSTS_N_INSNS (17), /* int_mult_si */ | |
917 | COSTS_N_INSNS (17), /* int_mult_di */ | |
918 | COSTS_N_INSNS (38), /* int_div_si */ | |
919 | COSTS_N_INSNS (38), /* int_div_di */ | |
920 | 2, /* branch_cost */ | |
921 | 6 /* memory_latency */ | |
922 | }, | |
923 | { /* R4000 */ | |
924 | COSTS_N_INSNS (6), /* fp_add */ | |
925 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
926 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
927 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
928 | COSTS_N_INSNS (36), /* fp_div_df */ | |
929 | COSTS_N_INSNS (10), /* int_mult_si */ | |
930 | COSTS_N_INSNS (10), /* int_mult_di */ | |
931 | COSTS_N_INSNS (69), /* int_div_si */ | |
932 | COSTS_N_INSNS (69), /* int_div_di */ | |
933 | 2, /* branch_cost */ | |
934 | 6 /* memory_latency */ | |
935 | }, | |
936 | { /* R4100 */ | |
937 | DEFAULT_COSTS | |
938 | }, | |
939 | { /* R4111 */ | |
940 | DEFAULT_COSTS | |
941 | }, | |
942 | { /* R4120 */ | |
943 | DEFAULT_COSTS | |
944 | }, | |
945 | { /* R4130 */ | |
946 | /* The only costs that appear to be updated here are | |
947 | integer multiplication. */ | |
948 | SOFT_FP_COSTS, | |
949 | COSTS_N_INSNS (4), /* int_mult_si */ | |
950 | COSTS_N_INSNS (6), /* int_mult_di */ | |
951 | COSTS_N_INSNS (69), /* int_div_si */ | |
952 | COSTS_N_INSNS (69), /* int_div_di */ | |
953 | 1, /* branch_cost */ | |
954 | 4 /* memory_latency */ | |
955 | }, | |
956 | { /* R4300 */ | |
957 | DEFAULT_COSTS | |
958 | }, | |
959 | { /* R4600 */ | |
960 | DEFAULT_COSTS | |
961 | }, | |
962 | { /* R4650 */ | |
963 | DEFAULT_COSTS | |
964 | }, | |
965 | { /* R5000 */ | |
966 | COSTS_N_INSNS (6), /* fp_add */ | |
967 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
968 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
969 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
970 | COSTS_N_INSNS (36), /* fp_div_df */ | |
971 | COSTS_N_INSNS (5), /* int_mult_si */ | |
972 | COSTS_N_INSNS (5), /* int_mult_di */ | |
973 | COSTS_N_INSNS (36), /* int_div_si */ | |
974 | COSTS_N_INSNS (36), /* int_div_di */ | |
975 | 1, /* branch_cost */ | |
976 | 4 /* memory_latency */ | |
977 | }, | |
978 | { /* R5400 */ | |
979 | COSTS_N_INSNS (6), /* fp_add */ | |
980 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
981 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
982 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
983 | COSTS_N_INSNS (59), /* fp_div_df */ | |
984 | COSTS_N_INSNS (3), /* int_mult_si */ | |
985 | COSTS_N_INSNS (4), /* int_mult_di */ | |
986 | COSTS_N_INSNS (42), /* int_div_si */ | |
987 | COSTS_N_INSNS (74), /* int_div_di */ | |
988 | 1, /* branch_cost */ | |
989 | 4 /* memory_latency */ | |
990 | }, | |
991 | { /* R5500 */ | |
992 | COSTS_N_INSNS (6), /* fp_add */ | |
993 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
994 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
995 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
996 | COSTS_N_INSNS (59), /* fp_div_df */ | |
997 | COSTS_N_INSNS (5), /* int_mult_si */ | |
998 | COSTS_N_INSNS (9), /* int_mult_di */ | |
999 | COSTS_N_INSNS (42), /* int_div_si */ | |
1000 | COSTS_N_INSNS (74), /* int_div_di */ | |
1001 | 1, /* branch_cost */ | |
1002 | 4 /* memory_latency */ | |
1003 | }, | |
1004 | { /* R7000 */ | |
1005 | /* The only costs that are changed here are | |
1006 | integer multiplication. */ | |
1007 | COSTS_N_INSNS (6), /* fp_add */ | |
1008 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1009 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1010 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1011 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1012 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1013 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1014 | COSTS_N_INSNS (69), /* int_div_si */ | |
1015 | COSTS_N_INSNS (69), /* int_div_di */ | |
1016 | 1, /* branch_cost */ | |
1017 | 4 /* memory_latency */ | |
1018 | }, | |
1019 | { /* R8000 */ | |
1020 | DEFAULT_COSTS | |
1021 | }, | |
1022 | { /* R9000 */ | |
1023 | /* The only costs that are changed here are | |
1024 | integer multiplication. */ | |
1025 | COSTS_N_INSNS (6), /* fp_add */ | |
1026 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1027 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1028 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1029 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1030 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1031 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1032 | COSTS_N_INSNS (69), /* int_div_si */ | |
1033 | COSTS_N_INSNS (69), /* int_div_di */ | |
1034 | 1, /* branch_cost */ | |
1035 | 4 /* memory_latency */ | |
1036 | }, | |
7a3446ec JK |
1037 | { /* R1x000 */ |
1038 | COSTS_N_INSNS (2), /* fp_add */ | |
1039 | COSTS_N_INSNS (2), /* fp_mult_sf */ | |
1040 | COSTS_N_INSNS (2), /* fp_mult_df */ | |
1041 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
1042 | COSTS_N_INSNS (19), /* fp_div_df */ | |
1043 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1044 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1045 | COSTS_N_INSNS (34), /* int_div_si */ | |
1046 | COSTS_N_INSNS (66), /* int_div_di */ | |
1047 | 1, /* branch_cost */ | |
1048 | 4 /* memory_latency */ | |
1049 | }, | |
65239d20 RS |
1050 | { /* SB1 */ |
1051 | /* These costs are the same as the SB-1A below. */ | |
1052 | COSTS_N_INSNS (4), /* fp_add */ | |
1053 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1054 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1055 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1056 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1057 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1058 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1059 | COSTS_N_INSNS (36), /* int_div_si */ | |
1060 | COSTS_N_INSNS (68), /* int_div_di */ | |
1061 | 1, /* branch_cost */ | |
1062 | 4 /* memory_latency */ | |
1063 | }, | |
1064 | { /* SB1-A */ | |
1065 | /* These costs are the same as the SB-1 above. */ | |
1066 | COSTS_N_INSNS (4), /* fp_add */ | |
1067 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1068 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1069 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1070 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1071 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1072 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1073 | COSTS_N_INSNS (36), /* int_div_si */ | |
1074 | COSTS_N_INSNS (68), /* int_div_di */ | |
1075 | 1, /* branch_cost */ | |
1076 | 4 /* memory_latency */ | |
1077 | }, | |
1078 | { /* SR71000 */ | |
1079 | DEFAULT_COSTS | |
1080 | }, | |
d0ae31b0 | 1081 | { /* XLR */ |
0051ef59 | 1082 | SOFT_FP_COSTS, |
d0ae31b0 SM |
1083 | COSTS_N_INSNS (8), /* int_mult_si */ |
1084 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1085 | COSTS_N_INSNS (72), /* int_div_si */ | |
1086 | COSTS_N_INSNS (72), /* int_div_di */ | |
1087 | 1, /* branch_cost */ | |
1088 | 4 /* memory_latency */ | |
1089 | } | |
65239d20 | 1090 | }; |
a27fb29b | 1091 | \f |
ee3ee488 | 1092 | static rtx mips_find_pic_call_symbol (rtx, rtx, bool); |
faa832a7 AS |
1093 | static int mips_register_move_cost (enum machine_mode, reg_class_t, |
1094 | reg_class_t); | |
c2ed6cf8 | 1095 | static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree); |
b53da244 | 1096 | \f |
65239d20 | 1097 | /* This hash table keeps track of implicit "mips16" and "nomips16" attributes |
ab77a036 | 1098 | for -mflip_mips16. It maps decl names onto a boolean mode setting. */ |
d1b38208 | 1099 | struct GTY (()) mflip_mips16_entry { |
ab77a036 RS |
1100 | const char *name; |
1101 | bool mips16_p; | |
1102 | }; | |
1103 | static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab; | |
4dbdb061 | 1104 | |
ab77a036 | 1105 | /* Hash table callbacks for mflip_mips16_htab. */ |
4dbdb061 | 1106 | |
ab77a036 RS |
1107 | static hashval_t |
1108 | mflip_mips16_htab_hash (const void *entry) | |
1109 | { | |
1110 | return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name); | |
1111 | } | |
912f2dac | 1112 | |
ab77a036 RS |
1113 | static int |
1114 | mflip_mips16_htab_eq (const void *entry, const void *name) | |
1115 | { | |
1116 | return strcmp (((const struct mflip_mips16_entry *) entry)->name, | |
1117 | (const char *) name) == 0; | |
1118 | } | |
ea462dd0 | 1119 | |
65239d20 RS |
1120 | /* True if -mflip-mips16 should next add an attribute for the default MIPS16 |
1121 | mode, false if it should next add an attribute for the opposite mode. */ | |
1122 | static GTY(()) bool mips16_flipper; | |
cd3a59b3 | 1123 | |
ab77a036 RS |
1124 | /* DECL is a function that needs a default "mips16" or "nomips16" attribute |
1125 | for -mflip-mips16. Return true if it should use "mips16" and false if | |
1126 | it should use "nomips16". */ | |
a44380d2 | 1127 | |
ab77a036 RS |
1128 | static bool |
1129 | mflip_mips16_use_mips16_p (tree decl) | |
1130 | { | |
1131 | struct mflip_mips16_entry *entry; | |
1132 | const char *name; | |
1133 | hashval_t hash; | |
1134 | void **slot; | |
076a5ce6 | 1135 | |
ab77a036 RS |
1136 | /* Use the opposite of the command-line setting for anonymous decls. */ |
1137 | if (!DECL_NAME (decl)) | |
1138 | return !mips_base_mips16; | |
cd3a59b3 | 1139 | |
ab77a036 RS |
1140 | if (!mflip_mips16_htab) |
1141 | mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash, | |
1142 | mflip_mips16_htab_eq, NULL); | |
cd3a59b3 | 1143 | |
ab77a036 RS |
1144 | name = IDENTIFIER_POINTER (DECL_NAME (decl)); |
1145 | hash = htab_hash_string (name); | |
1146 | slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT); | |
1147 | entry = (struct mflip_mips16_entry *) *slot; | |
1148 | if (!entry) | |
1149 | { | |
1150 | mips16_flipper = !mips16_flipper; | |
a9429e29 | 1151 | entry = ggc_alloc_mflip_mips16_entry (); |
ab77a036 RS |
1152 | entry->name = name; |
1153 | entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16; | |
1154 | *slot = entry; | |
1155 | } | |
1156 | return entry->mips16_p; | |
1157 | } | |
1158 | \f | |
cd3a59b3 SL |
1159 | /* Predicates to test for presence of "near" and "far"/"long_call" |
1160 | attributes on the given TYPE. */ | |
1161 | ||
1162 | static bool | |
3101faab | 1163 | mips_near_type_p (const_tree type) |
cd3a59b3 SL |
1164 | { |
1165 | return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; | |
1166 | } | |
1167 | ||
1168 | static bool | |
3101faab | 1169 | mips_far_type_p (const_tree type) |
cd3a59b3 SL |
1170 | { |
1171 | return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL | |
1172 | || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); | |
1173 | } | |
1174 | ||
65239d20 | 1175 | /* Similar predicates for "mips16"/"nomips16" function attributes. */ |
f9e4a411 SL |
1176 | |
1177 | static bool | |
9a6dfb47 | 1178 | mips_mips16_decl_p (const_tree decl) |
f9e4a411 | 1179 | { |
9a6dfb47 | 1180 | return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL; |
f9e4a411 SL |
1181 | } |
1182 | ||
1183 | static bool | |
9a6dfb47 | 1184 | mips_nomips16_decl_p (const_tree decl) |
f9e4a411 | 1185 | { |
9a6dfb47 | 1186 | return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL; |
f9e4a411 | 1187 | } |
cd3a59b3 | 1188 | |
e19da24c CF |
1189 | /* Check if the interrupt attribute is set for a function. */ |
1190 | ||
1191 | static bool | |
1192 | mips_interrupt_type_p (tree type) | |
1193 | { | |
1194 | return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; | |
1195 | } | |
1196 | ||
1197 | /* Check if the attribute to use shadow register set is set for a function. */ | |
1198 | ||
1199 | static bool | |
1200 | mips_use_shadow_register_set_p (tree type) | |
1201 | { | |
1202 | return lookup_attribute ("use_shadow_register_set", | |
1203 | TYPE_ATTRIBUTES (type)) != NULL; | |
1204 | } | |
1205 | ||
1206 | /* Check if the attribute to keep interrupts masked is set for a function. */ | |
1207 | ||
1208 | static bool | |
1209 | mips_keep_interrupts_masked_p (tree type) | |
1210 | { | |
1211 | return lookup_attribute ("keep_interrupts_masked", | |
1212 | TYPE_ATTRIBUTES (type)) != NULL; | |
1213 | } | |
1214 | ||
1215 | /* Check if the attribute to use debug exception return is set for | |
1216 | a function. */ | |
1217 | ||
1218 | static bool | |
1219 | mips_use_debug_exception_return_p (tree type) | |
1220 | { | |
1221 | return lookup_attribute ("use_debug_exception_return", | |
1222 | TYPE_ATTRIBUTES (type)) != NULL; | |
1223 | } | |
1224 | ||
ab77a036 RS |
1225 | /* Return true if function DECL is a MIPS16 function. Return the ambient |
1226 | setting if DECL is null. */ | |
cd3a59b3 | 1227 | |
ab77a036 RS |
1228 | static bool |
1229 | mips_use_mips16_mode_p (tree decl) | |
cd3a59b3 | 1230 | { |
ab77a036 RS |
1231 | if (decl) |
1232 | { | |
1233 | /* Nested functions must use the same frame pointer as their | |
1234 | parent and must therefore use the same ISA mode. */ | |
1235 | tree parent = decl_function_context (decl); | |
1236 | if (parent) | |
1237 | decl = parent; | |
1238 | if (mips_mips16_decl_p (decl)) | |
1239 | return true; | |
1240 | if (mips_nomips16_decl_p (decl)) | |
1241 | return false; | |
1242 | } | |
1243 | return mips_base_mips16; | |
1244 | } | |
1245 | ||
65239d20 | 1246 | /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ |
ab77a036 RS |
1247 | |
1248 | static int | |
1249 | mips_comp_type_attributes (const_tree type1, const_tree type2) | |
1250 | { | |
cd3a59b3 SL |
1251 | /* Disallow mixed near/far attributes. */ |
1252 | if (mips_far_type_p (type1) && mips_near_type_p (type2)) | |
1253 | return 0; | |
1254 | if (mips_near_type_p (type1) && mips_far_type_p (type2)) | |
1255 | return 0; | |
cd3a59b3 SL |
1256 | return 1; |
1257 | } | |
ab77a036 RS |
1258 | |
1259 | /* Implement TARGET_INSERT_ATTRIBUTES. */ | |
1260 | ||
1261 | static void | |
1262 | mips_insert_attributes (tree decl, tree *attributes) | |
1263 | { | |
1264 | const char *name; | |
1265 | bool mips16_p, nomips16_p; | |
1266 | ||
1267 | /* Check for "mips16" and "nomips16" attributes. */ | |
1268 | mips16_p = lookup_attribute ("mips16", *attributes) != NULL; | |
1269 | nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL; | |
1270 | if (TREE_CODE (decl) != FUNCTION_DECL) | |
1271 | { | |
1272 | if (mips16_p) | |
1273 | error ("%qs attribute only applies to functions", "mips16"); | |
1274 | if (nomips16_p) | |
1275 | error ("%qs attribute only applies to functions", "nomips16"); | |
1276 | } | |
1277 | else | |
1278 | { | |
1279 | mips16_p |= mips_mips16_decl_p (decl); | |
1280 | nomips16_p |= mips_nomips16_decl_p (decl); | |
1281 | if (mips16_p || nomips16_p) | |
1282 | { | |
65239d20 | 1283 | /* DECL cannot be simultaneously "mips16" and "nomips16". */ |
ab77a036 | 1284 | if (mips16_p && nomips16_p) |
29d08eba | 1285 | error ("%qE cannot have both %<mips16%> and " |
ab77a036 | 1286 | "%<nomips16%> attributes", |
29d08eba | 1287 | DECL_NAME (decl)); |
ab77a036 RS |
1288 | } |
1289 | else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl)) | |
1290 | { | |
1291 | /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a | |
1292 | "mips16" attribute, arbitrarily pick one. We must pick the same | |
1293 | setting for duplicate declarations of a function. */ | |
1294 | name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16"; | |
1295 | *attributes = tree_cons (get_identifier (name), NULL, *attributes); | |
1296 | } | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ | |
1301 | ||
1302 | static tree | |
1303 | mips_merge_decl_attributes (tree olddecl, tree newdecl) | |
1304 | { | |
1305 | /* The decls' "mips16" and "nomips16" attributes must match exactly. */ | |
1306 | if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl)) | |
29d08eba JM |
1307 | error ("%qE redeclared with conflicting %qs attributes", |
1308 | DECL_NAME (newdecl), "mips16"); | |
ab77a036 | 1309 | if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl)) |
29d08eba JM |
1310 | error ("%qE redeclared with conflicting %qs attributes", |
1311 | DECL_NAME (newdecl), "nomips16"); | |
ab77a036 RS |
1312 | |
1313 | return merge_attributes (DECL_ATTRIBUTES (olddecl), | |
1314 | DECL_ATTRIBUTES (newdecl)); | |
1315 | } | |
cee98a59 | 1316 | \f |
e1260576 RS |
1317 | /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR |
1318 | and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */ | |
1319 | ||
1320 | static void | |
1321 | mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr) | |
1322 | { | |
47ac44d6 | 1323 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
e1260576 RS |
1324 | { |
1325 | *base_ptr = XEXP (x, 0); | |
1326 | *offset_ptr = INTVAL (XEXP (x, 1)); | |
1327 | } | |
1328 | else | |
1329 | { | |
1330 | *base_ptr = x; | |
1331 | *offset_ptr = 0; | |
1332 | } | |
1333 | } | |
1334 | \f | |
ab77a036 RS |
1335 | static unsigned int mips_build_integer (struct mips_integer_op *, |
1336 | unsigned HOST_WIDE_INT); | |
1337 | ||
65239d20 | 1338 | /* A subroutine of mips_build_integer, with the same interface. |
ab77a036 RS |
1339 | Assume that the final action in the sequence should be a left shift. */ |
1340 | ||
1341 | static unsigned int | |
1342 | mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value) | |
1343 | { | |
1344 | unsigned int i, shift; | |
1345 | ||
1346 | /* Shift VALUE right until its lowest bit is set. Shift arithmetically | |
1347 | since signed numbers are easier to load than unsigned ones. */ | |
1348 | shift = 0; | |
1349 | while ((value & 1) == 0) | |
1350 | value /= 2, shift++; | |
1351 | ||
1352 | i = mips_build_integer (codes, value); | |
1353 | codes[i].code = ASHIFT; | |
1354 | codes[i].value = shift; | |
1355 | return i + 1; | |
1356 | } | |
1357 | ||
ab77a036 RS |
1358 | /* As for mips_build_shift, but assume that the final action will be |
1359 | an IOR or PLUS operation. */ | |
1360 | ||
1361 | static unsigned int | |
1362 | mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) | |
1363 | { | |
1364 | unsigned HOST_WIDE_INT high; | |
1365 | unsigned int i; | |
1366 | ||
1367 | high = value & ~(unsigned HOST_WIDE_INT) 0xffff; | |
1368 | if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000) | |
1369 | { | |
65239d20 RS |
1370 | /* The constant is too complex to load with a simple LUI/ORI pair, |
1371 | so we want to give the recursive call as many trailing zeros as | |
1372 | possible. In this case, we know bit 16 is set and that the | |
1373 | low 16 bits form a negative number. If we subtract that number | |
1374 | from VALUE, we will clear at least the lowest 17 bits, maybe more. */ | |
ab77a036 RS |
1375 | i = mips_build_integer (codes, CONST_HIGH_PART (value)); |
1376 | codes[i].code = PLUS; | |
1377 | codes[i].value = CONST_LOW_PART (value); | |
1378 | } | |
1379 | else | |
1380 | { | |
65239d20 RS |
1381 | /* Either this is a simple LUI/ORI pair, or clearing the lowest 16 |
1382 | bits gives a value with at least 17 trailing zeros. */ | |
ab77a036 RS |
1383 | i = mips_build_integer (codes, high); |
1384 | codes[i].code = IOR; | |
1385 | codes[i].value = value & 0xffff; | |
1386 | } | |
1387 | return i + 1; | |
1388 | } | |
1389 | ||
ab77a036 RS |
1390 | /* Fill CODES with a sequence of rtl operations to load VALUE. |
1391 | Return the number of operations needed. */ | |
1392 | ||
1393 | static unsigned int | |
1394 | mips_build_integer (struct mips_integer_op *codes, | |
1395 | unsigned HOST_WIDE_INT value) | |
1396 | { | |
1397 | if (SMALL_OPERAND (value) | |
1398 | || SMALL_OPERAND_UNSIGNED (value) | |
1399 | || LUI_OPERAND (value)) | |
1400 | { | |
1401 | /* The value can be loaded with a single instruction. */ | |
1402 | codes[0].code = UNKNOWN; | |
1403 | codes[0].value = value; | |
1404 | return 1; | |
1405 | } | |
1406 | else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value))) | |
1407 | { | |
1408 | /* Either the constant is a simple LUI/ORI combination or its | |
1409 | lowest bit is set. We don't want to shift in this case. */ | |
1410 | return mips_build_lower (codes, value); | |
1411 | } | |
1412 | else if ((value & 0xffff) == 0) | |
1413 | { | |
1414 | /* The constant will need at least three actions. The lowest | |
1415 | 16 bits are clear, so the final action will be a shift. */ | |
1416 | return mips_build_shift (codes, value); | |
1417 | } | |
1418 | else | |
1419 | { | |
1420 | /* The final action could be a shift, add or inclusive OR. | |
1421 | Rather than use a complex condition to select the best | |
1422 | approach, try both mips_build_shift and mips_build_lower | |
1423 | and pick the one that gives the shortest sequence. | |
1424 | Note that this case is only used once per constant. */ | |
1425 | struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS]; | |
1426 | unsigned int cost, alt_cost; | |
1427 | ||
1428 | cost = mips_build_shift (codes, value); | |
1429 | alt_cost = mips_build_lower (alt_codes, value); | |
1430 | if (alt_cost < cost) | |
1431 | { | |
1432 | memcpy (codes, alt_codes, alt_cost * sizeof (codes[0])); | |
1433 | cost = alt_cost; | |
1434 | } | |
1435 | return cost; | |
1436 | } | |
1437 | } | |
1438 | \f | |
1a627b35 RS |
1439 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
1440 | ||
1441 | static bool | |
1442 | mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
1443 | { | |
1444 | return mips_const_insns (x) > 0; | |
1445 | } | |
1446 | \f | |
ddaf8125 RS |
1447 | /* Return a SYMBOL_REF for a MIPS16 function called NAME. */ |
1448 | ||
1449 | static rtx | |
1450 | mips16_stub_function (const char *name) | |
1451 | { | |
1452 | rtx x; | |
1453 | ||
1454 | x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
1455 | SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION); | |
1456 | return x; | |
1457 | } | |
1458 | \f | |
08d0963a RS |
1459 | /* Return true if symbols of type TYPE require a GOT access. */ |
1460 | ||
1461 | static bool | |
1462 | mips_got_symbol_type_p (enum mips_symbol_type type) | |
1463 | { | |
1464 | switch (type) | |
1465 | { | |
1466 | case SYMBOL_GOT_PAGE_OFST: | |
1467 | case SYMBOL_GOT_DISP: | |
1468 | return true; | |
1469 | ||
1470 | default: | |
1471 | return false; | |
1472 | } | |
1473 | } | |
1474 | ||
ab77a036 RS |
1475 | /* Return true if X is a thread-local symbol. */ |
1476 | ||
1477 | static bool | |
65239d20 | 1478 | mips_tls_symbol_p (rtx x) |
ab77a036 RS |
1479 | { |
1480 | return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
1481 | } | |
1482 | ||
08e7ceb3 RS |
1483 | /* Return true if SYMBOL_REF X is associated with a global symbol |
1484 | (in the STB_GLOBAL sense). */ | |
1485 | ||
1486 | static bool | |
3101faab | 1487 | mips_global_symbol_p (const_rtx x) |
08e7ceb3 | 1488 | { |
65239d20 | 1489 | const_tree decl = SYMBOL_REF_DECL (x); |
08e7ceb3 | 1490 | |
08e7ceb3 | 1491 | if (!decl) |
08d0963a | 1492 | return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x); |
08e7ceb3 RS |
1493 | |
1494 | /* Weakref symbols are not TREE_PUBLIC, but their targets are global | |
1495 | or weak symbols. Relocations in the object file will be against | |
1496 | the target symbol, so it's that symbol's binding that matters here. */ | |
1497 | return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl)); | |
1498 | } | |
1499 | ||
08d0963a RS |
1500 | /* Return true if function X is a libgcc MIPS16 stub function. */ |
1501 | ||
1502 | static bool | |
1503 | mips16_stub_function_p (const_rtx x) | |
1504 | { | |
1505 | return (GET_CODE (x) == SYMBOL_REF | |
1506 | && strncmp (XSTR (x, 0), "__mips16_", 9) == 0); | |
1507 | } | |
1508 | ||
1509 | /* Return true if function X is a locally-defined and locally-binding | |
1510 | MIPS16 function. */ | |
1511 | ||
1512 | static bool | |
1513 | mips16_local_function_p (const_rtx x) | |
1514 | { | |
1515 | return (GET_CODE (x) == SYMBOL_REF | |
1516 | && SYMBOL_REF_LOCAL_P (x) | |
1517 | && !SYMBOL_REF_EXTERNAL_P (x) | |
1518 | && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x))); | |
1519 | } | |
1520 | ||
08e7ceb3 RS |
1521 | /* Return true if SYMBOL_REF X binds locally. */ |
1522 | ||
1523 | static bool | |
3101faab | 1524 | mips_symbol_binds_local_p (const_rtx x) |
08e7ceb3 RS |
1525 | { |
1526 | return (SYMBOL_REF_DECL (x) | |
1527 | ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) | |
1528 | : SYMBOL_REF_LOCAL_P (x)); | |
1529 | } | |
1530 | ||
a318179e RS |
1531 | /* Return true if rtx constants of mode MODE should be put into a small |
1532 | data section. */ | |
1533 | ||
1534 | static bool | |
1535 | mips_rtx_constant_in_small_data_p (enum machine_mode mode) | |
1536 | { | |
1537 | return (!TARGET_EMBEDDED_DATA | |
1538 | && TARGET_LOCAL_SDATA | |
65239d20 | 1539 | && GET_MODE_SIZE (mode) <= mips_small_data_threshold); |
a318179e RS |
1540 | } |
1541 | ||
ab77a036 RS |
1542 | /* Return true if X should not be moved directly into register $25. |
1543 | We need this because many versions of GAS will treat "la $25,foo" as | |
1544 | part of a call sequence and so allow a global "foo" to be lazily bound. */ | |
1545 | ||
1546 | bool | |
1547 | mips_dangerous_for_la25_p (rtx x) | |
1548 | { | |
1549 | return (!TARGET_EXPLICIT_RELOCS | |
1550 | && TARGET_USE_GOT | |
1551 | && GET_CODE (x) == SYMBOL_REF | |
1552 | && mips_global_symbol_p (x)); | |
1553 | } | |
1554 | ||
08d0963a RS |
1555 | /* Return true if calls to X might need $25 to be valid on entry. */ |
1556 | ||
1557 | bool | |
1558 | mips_use_pic_fn_addr_reg_p (const_rtx x) | |
1559 | { | |
1560 | if (!TARGET_USE_PIC_FN_ADDR_REG) | |
1561 | return false; | |
1562 | ||
1563 | /* MIPS16 stub functions are guaranteed not to use $25. */ | |
1564 | if (mips16_stub_function_p (x)) | |
1565 | return false; | |
1566 | ||
e21d5757 DJ |
1567 | if (GET_CODE (x) == SYMBOL_REF) |
1568 | { | |
1569 | /* If PLTs and copy relocations are available, the static linker | |
1570 | will make sure that $25 is valid on entry to the target function. */ | |
1571 | if (TARGET_ABICALLS_PIC0) | |
1572 | return false; | |
1573 | ||
1574 | /* Locally-defined functions use absolute accesses to set up | |
1575 | the global pointer. */ | |
1576 | if (TARGET_ABSOLUTE_ABICALLS | |
1577 | && mips_symbol_binds_local_p (x) | |
1578 | && !SYMBOL_REF_EXTERNAL_P (x)) | |
1579 | return false; | |
1580 | } | |
08d0963a RS |
1581 | |
1582 | return true; | |
1583 | } | |
1584 | ||
280fcbfa RS |
1585 | /* Return the method that should be used to access SYMBOL_REF or |
1586 | LABEL_REF X in context CONTEXT. */ | |
cafe096b EC |
1587 | |
1588 | static enum mips_symbol_type | |
3101faab | 1589 | mips_classify_symbol (const_rtx x, enum mips_symbol_context context) |
cee98a59 | 1590 | { |
8cb6400c RS |
1591 | if (TARGET_RTP_PIC) |
1592 | return SYMBOL_GOT_DISP; | |
1593 | ||
cafe096b | 1594 | if (GET_CODE (x) == LABEL_REF) |
76cbf5bf | 1595 | { |
4377fad9 RS |
1596 | /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16 |
1597 | code and if we know that the label is in the current function's | |
1598 | text section. LABEL_REFs are used for jump tables as well as | |
1599 | text labels, so we must check whether jump tables live in the | |
1600 | text section. */ | |
1601 | if (TARGET_MIPS16_SHORT_JUMP_TABLES | |
1602 | && !LABEL_REF_NONLOCAL_P (x)) | |
67da85da | 1603 | return SYMBOL_PC_RELATIVE; |
65239d20 | 1604 | |
d9870b7e | 1605 | if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) |
08e7ceb3 | 1606 | return SYMBOL_GOT_PAGE_OFST; |
65239d20 | 1607 | |
67da85da | 1608 | return SYMBOL_ABSOLUTE; |
76cbf5bf | 1609 | } |
cee98a59 | 1610 | |
7ad769fe | 1611 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
2bcb2ab3 | 1612 | |
69229b81 DJ |
1613 | if (SYMBOL_REF_TLS_MODEL (x)) |
1614 | return SYMBOL_TLS; | |
1615 | ||
cafe096b EC |
1616 | if (CONSTANT_POOL_ADDRESS_P (x)) |
1617 | { | |
c93c5160 RS |
1618 | if (TARGET_MIPS16_TEXT_LOADS) |
1619 | return SYMBOL_PC_RELATIVE; | |
1620 | ||
1621 | if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM) | |
67da85da | 1622 | return SYMBOL_PC_RELATIVE; |
cee98a59 | 1623 | |
a318179e | 1624 | if (mips_rtx_constant_in_small_data_p (get_pool_mode (x))) |
67da85da | 1625 | return SYMBOL_GP_RELATIVE; |
cafe096b EC |
1626 | } |
1627 | ||
3ac25120 RS |
1628 | /* Do not use small-data accesses for weak symbols; they may end up |
1629 | being zero. */ | |
65239d20 | 1630 | if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x)) |
67da85da | 1631 | return SYMBOL_GP_RELATIVE; |
b8898790 | 1632 | |
e06e2776 RS |
1633 | /* Don't use GOT accesses for locally-binding symbols when -mno-shared |
1634 | is in effect. */ | |
e21d5757 | 1635 | if (TARGET_ABICALLS_PIC2 |
e06e2776 | 1636 | && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))) |
f6149877 | 1637 | { |
08e7ceb3 RS |
1638 | /* There are three cases to consider: |
1639 | ||
1640 | - o32 PIC (either with or without explicit relocs) | |
1641 | - n32/n64 PIC without explicit relocs | |
1642 | - n32/n64 PIC with explicit relocs | |
1643 | ||
1644 | In the first case, both local and global accesses will use an | |
1645 | R_MIPS_GOT16 relocation. We must correctly predict which of | |
1646 | the two semantics (local or global) the assembler and linker | |
1647 | will apply. The choice depends on the symbol's binding rather | |
1648 | than its visibility. | |
f6149877 | 1649 | |
08e7ceb3 RS |
1650 | In the second case, the assembler will not use R_MIPS_GOT16 |
1651 | relocations, but it chooses between local and global accesses | |
1652 | in the same way as for o32 PIC. | |
1653 | ||
1654 | In the third case we have more freedom since both forms of | |
1655 | access will work for any kind of symbol. However, there seems | |
1656 | little point in doing things differently. */ | |
1657 | if (mips_global_symbol_p (x)) | |
1658 | return SYMBOL_GOT_DISP; | |
1659 | ||
1660 | return SYMBOL_GOT_PAGE_OFST; | |
f6149877 | 1661 | } |
cafe096b | 1662 | |
67da85da | 1663 | return SYMBOL_ABSOLUTE; |
cee98a59 MM |
1664 | } |
1665 | ||
65239d20 RS |
1666 | /* Classify the base of symbolic expression X, given that X appears in |
1667 | context CONTEXT. */ | |
6d992de0 RS |
1668 | |
1669 | static enum mips_symbol_type | |
1670 | mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context) | |
1671 | { | |
1672 | rtx offset; | |
1673 | ||
1674 | split_const (x, &x, &offset); | |
1675 | if (UNSPEC_ADDRESS_P (x)) | |
1676 | return UNSPEC_ADDRESS_TYPE (x); | |
1677 | ||
1678 | return mips_classify_symbol (x, context); | |
1679 | } | |
1680 | ||
6de36441 | 1681 | /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN |
65239d20 | 1682 | is the alignment in bytes of SYMBOL_REF X. */ |
8b5fb3a3 DD |
1683 | |
1684 | static bool | |
1685 | mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset) | |
1686 | { | |
65239d20 | 1687 | HOST_WIDE_INT align; |
8b5fb3a3 | 1688 | |
65239d20 RS |
1689 | align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1; |
1690 | return IN_RANGE (offset, 0, align - 1); | |
8b5fb3a3 DD |
1691 | } |
1692 | ||
280fcbfa RS |
1693 | /* Return true if X is a symbolic constant that can be used in context |
1694 | CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ | |
108b61d5 | 1695 | |
96a30b18 | 1696 | bool |
280fcbfa RS |
1697 | mips_symbolic_constant_p (rtx x, enum mips_symbol_context context, |
1698 | enum mips_symbol_type *symbol_type) | |
108b61d5 | 1699 | { |
7ffb5e78 | 1700 | rtx offset; |
108b61d5 | 1701 | |
7ffb5e78 | 1702 | split_const (x, &x, &offset); |
108b61d5 | 1703 | if (UNSPEC_ADDRESS_P (x)) |
8b5fb3a3 DD |
1704 | { |
1705 | *symbol_type = UNSPEC_ADDRESS_TYPE (x); | |
1706 | x = UNSPEC_ADDRESS (x); | |
1707 | } | |
108b61d5 | 1708 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) |
69229b81 | 1709 | { |
280fcbfa | 1710 | *symbol_type = mips_classify_symbol (x, context); |
69229b81 DJ |
1711 | if (*symbol_type == SYMBOL_TLS) |
1712 | return false; | |
1713 | } | |
108b61d5 RS |
1714 | else |
1715 | return false; | |
1716 | ||
7ffb5e78 | 1717 | if (offset == const0_rtx) |
108b61d5 RS |
1718 | return true; |
1719 | ||
1720 | /* Check whether a nonzero offset is valid for the underlying | |
1721 | relocations. */ | |
1722 | switch (*symbol_type) | |
1723 | { | |
67da85da | 1724 | case SYMBOL_ABSOLUTE: |
e245bd81 RS |
1725 | case SYMBOL_64_HIGH: |
1726 | case SYMBOL_64_MID: | |
1727 | case SYMBOL_64_LOW: | |
62973ffe RS |
1728 | /* If the target has 64-bit pointers and the object file only |
1729 | supports 32-bit symbols, the values of those symbols will be | |
1730 | sign-extended. In this case we can't allow an arbitrary offset | |
1731 | in case the 32-bit value X + OFFSET has a different sign from X. */ | |
1732 | if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS) | |
7ffb5e78 | 1733 | return offset_within_block_p (x, INTVAL (offset)); |
62973ffe RS |
1734 | |
1735 | /* In other cases the relocations can handle any offset. */ | |
108b61d5 RS |
1736 | return true; |
1737 | ||
67da85da | 1738 | case SYMBOL_PC_RELATIVE: |
76cbf5bf RS |
1739 | /* Allow constant pool references to be converted to LABEL+CONSTANT. |
1740 | In this case, we no longer have access to the underlying constant, | |
1741 | but the original symbol-based access was known to be valid. */ | |
1742 | if (GET_CODE (x) == LABEL_REF) | |
1743 | return true; | |
1744 | ||
1745 | /* Fall through. */ | |
1746 | ||
67da85da | 1747 | case SYMBOL_GP_RELATIVE: |
62973ffe | 1748 | /* Make sure that the offset refers to something within the |
7ffb5e78 | 1749 | same object block. This should guarantee that the final |
62973ffe | 1750 | PC- or GP-relative offset is within the 16-bit limit. */ |
7ffb5e78 | 1751 | return offset_within_block_p (x, INTVAL (offset)); |
108b61d5 | 1752 | |
08e7ceb3 | 1753 | case SYMBOL_GOT_PAGE_OFST: |
108b61d5 | 1754 | case SYMBOL_GOTOFF_PAGE: |
08e7ceb3 RS |
1755 | /* If the symbol is global, the GOT entry will contain the symbol's |
1756 | address, and we will apply a 16-bit offset after loading it. | |
1757 | If the symbol is local, the linker should provide enough local | |
1758 | GOT entries for a 16-bit offset, but larger offsets may lead | |
1759 | to GOT overflow. */ | |
7ffb5e78 | 1760 | return SMALL_INT (offset); |
108b61d5 | 1761 | |
8b5fb3a3 DD |
1762 | case SYMBOL_TPREL: |
1763 | case SYMBOL_DTPREL: | |
1764 | /* There is no carry between the HI and LO REL relocations, so the | |
1765 | offset is only valid if we know it won't lead to such a carry. */ | |
1766 | return mips_offset_within_alignment_p (x, INTVAL (offset)); | |
1767 | ||
08e7ceb3 RS |
1768 | case SYMBOL_GOT_DISP: |
1769 | case SYMBOL_GOTOFF_DISP: | |
108b61d5 RS |
1770 | case SYMBOL_GOTOFF_CALL: |
1771 | case SYMBOL_GOTOFF_LOADGP: | |
69229b81 DJ |
1772 | case SYMBOL_TLSGD: |
1773 | case SYMBOL_TLSLDM: | |
69229b81 DJ |
1774 | case SYMBOL_GOTTPREL: |
1775 | case SYMBOL_TLS: | |
8cb6400c | 1776 | case SYMBOL_HALF: |
108b61d5 RS |
1777 | return false; |
1778 | } | |
7ad769fe | 1779 | gcc_unreachable (); |
108b61d5 | 1780 | } |
ab77a036 RS |
1781 | \f |
1782 | /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a | |
1783 | single instruction. We rely on the fact that, in the worst case, | |
1784 | all instructions involved in a MIPS16 address calculation are usually | |
1785 | extended ones. */ | |
108b61d5 | 1786 | |
ab77a036 RS |
1787 | static int |
1788 | mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode) | |
cee98a59 | 1789 | { |
ddaf8125 RS |
1790 | if (mips_use_pcrel_pool_p[(int) type]) |
1791 | { | |
1792 | if (mode == MAX_MACHINE_MODE) | |
1793 | /* LEAs will be converted into constant-pool references by | |
1794 | mips_reorg. */ | |
1795 | type = SYMBOL_PC_RELATIVE; | |
1796 | else | |
1797 | /* The constant must be loaded and then dereferenced. */ | |
1798 | return 0; | |
1799 | } | |
1800 | ||
ab77a036 | 1801 | switch (type) |
bcbc6b7f | 1802 | { |
ab77a036 RS |
1803 | case SYMBOL_ABSOLUTE: |
1804 | /* When using 64-bit symbols, we need 5 preparatory instructions, | |
1805 | such as: | |
bcbc6b7f | 1806 | |
ab77a036 RS |
1807 | lui $at,%highest(symbol) |
1808 | daddiu $at,$at,%higher(symbol) | |
1809 | dsll $at,$at,16 | |
1810 | daddiu $at,$at,%hi(symbol) | |
1811 | dsll $at,$at,16 | |
bcbc6b7f | 1812 | |
ab77a036 | 1813 | The final address is then $at + %lo(symbol). With 32-bit |
65239d20 RS |
1814 | symbols we just need a preparatory LUI for normal mode and |
1815 | a preparatory LI and SLL for MIPS16. */ | |
ab77a036 | 1816 | return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; |
bcbc6b7f | 1817 | |
ab77a036 RS |
1818 | case SYMBOL_GP_RELATIVE: |
1819 | /* Treat GP-relative accesses as taking a single instruction on | |
1820 | MIPS16 too; the copy of $gp can often be shared. */ | |
1821 | return 1; | |
b8eb88d0 | 1822 | |
67da85da | 1823 | case SYMBOL_PC_RELATIVE: |
65239d20 RS |
1824 | /* PC-relative constants can be only be used with ADDIUPC, |
1825 | DADDIUPC, LWPC and LDPC. */ | |
fbb96ac5 RS |
1826 | if (mode == MAX_MACHINE_MODE |
1827 | || GET_MODE_SIZE (mode) == 4 | |
1828 | || GET_MODE_SIZE (mode) == 8) | |
1829 | return 1; | |
1830 | ||
65239d20 | 1831 | /* The constant must be loaded using ADDIUPC or DADDIUPC first. */ |
fbb96ac5 | 1832 | return 0; |
b8eb88d0 | 1833 | |
08e7ceb3 | 1834 | case SYMBOL_GOT_DISP: |
fbb96ac5 RS |
1835 | /* The constant will have to be loaded from the GOT before it |
1836 | is used in an address. */ | |
1837 | if (mode != MAX_MACHINE_MODE) | |
1838 | return 0; | |
1839 | ||
1840 | /* Fall through. */ | |
1841 | ||
1842 | case SYMBOL_GOT_PAGE_OFST: | |
65239d20 RS |
1843 | /* Unless -funit-at-a-time is in effect, we can't be sure whether the |
1844 | local/global classification is accurate. The worst cases are: | |
2bcb2ab3 | 1845 | |
f6149877 RS |
1846 | (1) For local symbols when generating o32 or o64 code. The assembler |
1847 | will use: | |
108b61d5 | 1848 | |
f6149877 RS |
1849 | lw $at,%got(symbol) |
1850 | nop | |
108b61d5 | 1851 | |
f6149877 | 1852 | ...and the final address will be $at + %lo(symbol). |
108b61d5 | 1853 | |
f6149877 RS |
1854 | (2) For global symbols when -mxgot. The assembler will use: |
1855 | ||
1856 | lui $at,%got_hi(symbol) | |
1857 | (d)addu $at,$at,$gp | |
1858 | ||
1859 | ...and the final address will be $at + %got_lo(symbol). */ | |
1860 | return 3; | |
108b61d5 RS |
1861 | |
1862 | case SYMBOL_GOTOFF_PAGE: | |
08e7ceb3 | 1863 | case SYMBOL_GOTOFF_DISP: |
108b61d5 RS |
1864 | case SYMBOL_GOTOFF_CALL: |
1865 | case SYMBOL_GOTOFF_LOADGP: | |
e245bd81 RS |
1866 | case SYMBOL_64_HIGH: |
1867 | case SYMBOL_64_MID: | |
1868 | case SYMBOL_64_LOW: | |
69229b81 DJ |
1869 | case SYMBOL_TLSGD: |
1870 | case SYMBOL_TLSLDM: | |
1871 | case SYMBOL_DTPREL: | |
1872 | case SYMBOL_GOTTPREL: | |
1873 | case SYMBOL_TPREL: | |
fbb96ac5 RS |
1874 | case SYMBOL_HALF: |
1875 | /* A 16-bit constant formed by a single relocation, or a 32-bit | |
1876 | constant formed from a high 16-bit relocation and a low 16-bit | |
65239d20 RS |
1877 | relocation. Use mips_split_p to determine which. 32-bit |
1878 | constants need an "lui; addiu" sequence for normal mode and | |
1879 | an "li; sll; addiu" sequence for MIPS16 mode. */ | |
c93c5160 | 1880 | return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2; |
69229b81 DJ |
1881 | |
1882 | case SYMBOL_TLS: | |
1883 | /* We don't treat a bare TLS symbol as a constant. */ | |
1884 | return 0; | |
2bcb2ab3 | 1885 | } |
7ad769fe | 1886 | gcc_unreachable (); |
cafe096b | 1887 | } |
2bcb2ab3 | 1888 | |
fbb96ac5 RS |
1889 | /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed |
1890 | to load symbols of type TYPE into a register. Return 0 if the given | |
1891 | type of symbol cannot be used as an immediate operand. | |
1892 | ||
1893 | Otherwise, return the number of instructions needed to load or store | |
1894 | values of mode MODE to or from addresses of type TYPE. Return 0 if | |
1895 | the given type of symbol is not valid in addresses. | |
1896 | ||
1897 | In both cases, treat extended MIPS16 instructions as two instructions. */ | |
1898 | ||
1899 | static int | |
1900 | mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode) | |
1901 | { | |
1902 | return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1); | |
1903 | } | |
65239d20 RS |
1904 | \f |
1905 | /* A for_each_rtx callback. Stop the search if *X references a | |
1906 | thread-local symbol. */ | |
96a30b18 | 1907 | |
ab77a036 RS |
1908 | static int |
1909 | mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
96a30b18 | 1910 | { |
65239d20 | 1911 | return mips_tls_symbol_p (*x); |
96a30b18 | 1912 | } |
2bcb2ab3 | 1913 | |
65239d20 | 1914 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
cee98a59 | 1915 | |
cafe096b | 1916 | static bool |
1a627b35 | 1917 | mips_cannot_force_const_mem (enum machine_mode mode, rtx x) |
cee98a59 | 1918 | { |
08d0963a | 1919 | enum mips_symbol_type type; |
ab77a036 RS |
1920 | rtx base, offset; |
1921 | ||
08d0963a RS |
1922 | /* There is no assembler syntax for expressing an address-sized |
1923 | high part. */ | |
1924 | if (GET_CODE (x) == HIGH) | |
1925 | return true; | |
1926 | ||
1927 | /* As an optimization, reject constants that mips_legitimize_move | |
1928 | can expand inline. | |
1929 | ||
1930 | Suppose we have a multi-instruction sequence that loads constant C | |
1931 | into register R. If R does not get allocated a hard register, and | |
1932 | R is used in an operand that allows both registers and memory | |
1933 | references, reload will consider forcing C into memory and using | |
1934 | one of the instruction's memory alternatives. Returning false | |
1935 | here will force it to use an input reload instead. */ | |
1a627b35 | 1936 | if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x)) |
08d0963a | 1937 | return true; |
ab77a036 | 1938 | |
08d0963a | 1939 | split_const (x, &base, &offset); |
ddaf8125 | 1940 | if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)) |
08d0963a | 1941 | { |
ddaf8125 RS |
1942 | /* See whether we explicitly want these symbols in the pool. */ |
1943 | if (mips_use_pcrel_pool_p[(int) type]) | |
1944 | return false; | |
1945 | ||
08d0963a RS |
1946 | /* The same optimization as for CONST_INT. */ |
1947 | if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0) | |
ab77a036 RS |
1948 | return true; |
1949 | ||
08d0963a RS |
1950 | /* If MIPS16 constant pools live in the text section, they should |
1951 | not refer to anything that might need run-time relocation. */ | |
1952 | if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type)) | |
ab77a036 | 1953 | return true; |
cafe096b | 1954 | } |
ab77a036 | 1955 | |
65239d20 RS |
1956 | /* TLS symbols must be computed by mips_legitimize_move. */ |
1957 | if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL)) | |
ab77a036 RS |
1958 | return true; |
1959 | ||
cafe096b EC |
1960 | return false; |
1961 | } | |
cee98a59 | 1962 | |
ab77a036 RS |
1963 | /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for |
1964 | constants when we're using a per-function constant pool. */ | |
cee98a59 | 1965 | |
ab77a036 RS |
1966 | static bool |
1967 | mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1968 | const_rtx x ATTRIBUTE_UNUSED) | |
1969 | { | |
1970 | return !TARGET_MIPS16_PCREL_LOADS; | |
1971 | } | |
1972 | \f | |
65239d20 RS |
1973 | /* Return true if register REGNO is a valid base register for mode MODE. |
1974 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
cee98a59 | 1975 | |
cafe096b | 1976 | int |
65239d20 RS |
1977 | mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, |
1978 | bool strict_p) | |
cafe096b | 1979 | { |
ab77a036 RS |
1980 | if (!HARD_REGISTER_NUM_P (regno)) |
1981 | { | |
65239d20 | 1982 | if (!strict_p) |
ab77a036 RS |
1983 | return true; |
1984 | regno = reg_renumber[regno]; | |
1985 | } | |
cafe096b | 1986 | |
ab77a036 RS |
1987 | /* These fake registers will be eliminated to either the stack or |
1988 | hard frame pointer, both of which are usually valid base registers. | |
1989 | Reload deals with the cases where the eliminated form isn't valid. */ | |
1990 | if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) | |
1991 | return true; | |
1992 | ||
65239d20 | 1993 | /* In MIPS16 mode, the stack pointer can only address word and doubleword |
ab77a036 RS |
1994 | values, nothing smaller. There are two problems here: |
1995 | ||
1996 | (a) Instantiating virtual registers can introduce new uses of the | |
1997 | stack pointer. If these virtual registers are valid addresses, | |
1998 | the stack pointer should be too. | |
1999 | ||
2000 | (b) Most uses of the stack pointer are not made explicit until | |
2001 | FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated. | |
2002 | We don't know until that stage whether we'll be eliminating to the | |
2003 | stack pointer (which needs the restriction) or the hard frame | |
2004 | pointer (which doesn't). | |
2005 | ||
2006 | All in all, it seems more consistent to only enforce this restriction | |
2007 | during and after reload. */ | |
2008 | if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) | |
65239d20 | 2009 | return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; |
ab77a036 RS |
2010 | |
2011 | return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); | |
2012 | } | |
2013 | ||
65239d20 RS |
2014 | /* Return true if X is a valid base register for mode MODE. |
2015 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
ab77a036 RS |
2016 | |
2017 | static bool | |
65239d20 | 2018 | mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p) |
ab77a036 | 2019 | { |
65239d20 | 2020 | if (!strict_p && GET_CODE (x) == SUBREG) |
ab77a036 RS |
2021 | x = SUBREG_REG (x); |
2022 | ||
2023 | return (REG_P (x) | |
65239d20 | 2024 | && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); |
ab77a036 RS |
2025 | } |
2026 | ||
fa21a761 RS |
2027 | /* Return true if, for every base register BASE_REG, (plus BASE_REG X) |
2028 | can address a value of mode MODE. */ | |
2029 | ||
2030 | static bool | |
2031 | mips_valid_offset_p (rtx x, enum machine_mode mode) | |
2032 | { | |
2033 | /* Check that X is a signed 16-bit number. */ | |
2034 | if (!const_arith_operand (x, Pmode)) | |
2035 | return false; | |
2036 | ||
2037 | /* We may need to split multiword moves, so make sure that every word | |
2038 | is accessible. */ | |
2039 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2040 | && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) | |
2041 | return false; | |
2042 | ||
2043 | return true; | |
2044 | } | |
2045 | ||
2046 | /* Return true if a LO_SUM can address a value of mode MODE when the | |
2047 | LO_SUM symbol has type SYMBOL_TYPE. */ | |
2048 | ||
2049 | static bool | |
2050 | mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode) | |
2051 | { | |
2052 | /* Check that symbols of type SYMBOL_TYPE can be used to access values | |
2053 | of mode MODE. */ | |
2054 | if (mips_symbol_insns (symbol_type, mode) == 0) | |
2055 | return false; | |
2056 | ||
2057 | /* Check that there is a known low-part relocation. */ | |
2058 | if (mips_lo_relocs[symbol_type] == NULL) | |
2059 | return false; | |
2060 | ||
2061 | /* We may need to split multiword moves, so make sure that each word | |
2062 | can be accessed without inducing a carry. This is mainly needed | |
2063 | for o64, which has historically only guaranteed 64-bit alignment | |
2064 | for 128-bit types. */ | |
2065 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2066 | && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) | |
2067 | return false; | |
2068 | ||
2069 | return true; | |
2070 | } | |
2071 | ||
ab77a036 | 2072 | /* Return true if X is a valid address for machine mode MODE. If it is, |
65239d20 RS |
2073 | fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in |
2074 | effect. */ | |
ab77a036 RS |
2075 | |
2076 | static bool | |
2077 | mips_classify_address (struct mips_address_info *info, rtx x, | |
65239d20 | 2078 | enum machine_mode mode, bool strict_p) |
ab77a036 RS |
2079 | { |
2080 | switch (GET_CODE (x)) | |
2081 | { | |
2082 | case REG: | |
2083 | case SUBREG: | |
2084 | info->type = ADDRESS_REG; | |
2085 | info->reg = x; | |
2086 | info->offset = const0_rtx; | |
65239d20 | 2087 | return mips_valid_base_register_p (info->reg, mode, strict_p); |
ab77a036 RS |
2088 | |
2089 | case PLUS: | |
2090 | info->type = ADDRESS_REG; | |
2091 | info->reg = XEXP (x, 0); | |
2092 | info->offset = XEXP (x, 1); | |
65239d20 | 2093 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2094 | && mips_valid_offset_p (info->offset, mode)); |
ab77a036 RS |
2095 | |
2096 | case LO_SUM: | |
2097 | info->type = ADDRESS_LO_SUM; | |
2098 | info->reg = XEXP (x, 0); | |
2099 | info->offset = XEXP (x, 1); | |
2100 | /* We have to trust the creator of the LO_SUM to do something vaguely | |
2101 | sane. Target-independent code that creates a LO_SUM should also | |
2102 | create and verify the matching HIGH. Target-independent code that | |
2103 | adds an offset to a LO_SUM must prove that the offset will not | |
2104 | induce a carry. Failure to do either of these things would be | |
2105 | a bug, and we are not required to check for it here. The MIPS | |
2106 | backend itself should only create LO_SUMs for valid symbolic | |
2107 | constants, with the high part being either a HIGH or a copy | |
2108 | of _gp. */ | |
2109 | info->symbol_type | |
2110 | = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM); | |
65239d20 | 2111 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2112 | && mips_valid_lo_sum_p (info->symbol_type, mode)); |
ab77a036 RS |
2113 | |
2114 | case CONST_INT: | |
2115 | /* Small-integer addresses don't occur very often, but they | |
2116 | are legitimate if $0 is a valid base register. */ | |
2117 | info->type = ADDRESS_CONST_INT; | |
2118 | return !TARGET_MIPS16 && SMALL_INT (x); | |
2119 | ||
2120 | case CONST: | |
2121 | case LABEL_REF: | |
2122 | case SYMBOL_REF: | |
2123 | info->type = ADDRESS_SYMBOLIC; | |
2124 | return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM, | |
2125 | &info->symbol_type) | |
2126 | && mips_symbol_insns (info->symbol_type, mode) > 0 | |
2127 | && !mips_split_p[info->symbol_type]); | |
2128 | ||
2129 | default: | |
2130 | return false; | |
2131 | } | |
2132 | } | |
2133 | ||
c6c3dba9 | 2134 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ |
ab77a036 | 2135 | |
c6c3dba9 | 2136 | static bool |
65239d20 | 2137 | mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) |
ab77a036 RS |
2138 | { |
2139 | struct mips_address_info addr; | |
2140 | ||
65239d20 | 2141 | return mips_classify_address (&addr, x, mode, strict_p); |
ab77a036 RS |
2142 | } |
2143 | ||
2144 | /* Return true if X is a legitimate $sp-based address for mode MDOE. */ | |
2145 | ||
2146 | bool | |
2147 | mips_stack_address_p (rtx x, enum machine_mode mode) | |
2148 | { | |
2149 | struct mips_address_info addr; | |
2150 | ||
2151 | return (mips_classify_address (&addr, x, mode, false) | |
2152 | && addr.type == ADDRESS_REG | |
2153 | && addr.reg == stack_pointer_rtx); | |
2154 | } | |
2155 | ||
65239d20 RS |
2156 | /* Return true if ADDR matches the pattern for the LWXS load scaled indexed |
2157 | address instruction. Note that such addresses are not considered | |
331d9186 | 2158 | legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use |
65239d20 | 2159 | is so restricted. */ |
ab77a036 RS |
2160 | |
2161 | static bool | |
2162 | mips_lwxs_address_p (rtx addr) | |
2163 | { | |
2164 | if (ISA_HAS_LWXS | |
2165 | && GET_CODE (addr) == PLUS | |
2166 | && REG_P (XEXP (addr, 1))) | |
2167 | { | |
2168 | rtx offset = XEXP (addr, 0); | |
2169 | if (GET_CODE (offset) == MULT | |
2170 | && REG_P (XEXP (offset, 0)) | |
47ac44d6 | 2171 | && CONST_INT_P (XEXP (offset, 1)) |
ab77a036 RS |
2172 | && INTVAL (XEXP (offset, 1)) == 4) |
2173 | return true; | |
2174 | } | |
2175 | return false; | |
2176 | } | |
770da00a AP |
2177 | |
2178 | /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load | |
2179 | indexed address instruction. Note that such addresses are | |
2180 | not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P | |
2181 | sense, because their use is so restricted. */ | |
2182 | ||
2183 | static bool | |
2184 | mips_lx_address_p (rtx addr, enum machine_mode mode) | |
2185 | { | |
2186 | if (GET_CODE (addr) != PLUS | |
2187 | || !REG_P (XEXP (addr, 0)) | |
2188 | || !REG_P (XEXP (addr, 1))) | |
2189 | return false; | |
2190 | if (ISA_HAS_LBX && mode == QImode) | |
2191 | return true; | |
2192 | if (ISA_HAS_LHX && mode == HImode) | |
2193 | return true; | |
2194 | if (ISA_HAS_LWX && mode == SImode) | |
2195 | return true; | |
2196 | if (ISA_HAS_LDX && mode == DImode) | |
2197 | return true; | |
2198 | return false; | |
2199 | } | |
65239d20 RS |
2200 | \f |
2201 | /* Return true if a value at OFFSET bytes from base register BASE can be | |
2202 | accessed using an unextended MIPS16 instruction. MODE is the mode of | |
2203 | the value. | |
ab77a036 RS |
2204 | |
2205 | Usually the offset in an unextended instruction is a 5-bit field. | |
65239d20 RS |
2206 | The offset is unsigned and shifted left once for LH and SH, twice |
2207 | for LW and SW, and so on. An exception is LWSP and SWSP, which have | |
2208 | an 8-bit immediate field that's shifted left twice. */ | |
ab77a036 RS |
2209 | |
2210 | static bool | |
65239d20 RS |
2211 | mips16_unextended_reference_p (enum machine_mode mode, rtx base, |
2212 | unsigned HOST_WIDE_INT offset) | |
ab77a036 | 2213 | { |
fd2d6b1b | 2214 | if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0) |
ab77a036 RS |
2215 | { |
2216 | if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) | |
65239d20 RS |
2217 | return offset < 256U * GET_MODE_SIZE (mode); |
2218 | return offset < 32U * GET_MODE_SIZE (mode); | |
ab77a036 RS |
2219 | } |
2220 | return false; | |
2221 | } | |
2222 | ||
ab77a036 | 2223 | /* Return the number of instructions needed to load or store a value |
65239d20 RS |
2224 | of mode MODE at address X. Return 0 if X isn't valid for MODE. |
2225 | Assume that multiword moves may need to be split into word moves | |
2226 | if MIGHT_SPLIT_P, otherwise assume that a single load or store is | |
2227 | enough. | |
ab77a036 | 2228 | |
65239d20 | 2229 | For MIPS16 code, count extended instructions as two instructions. */ |
ab77a036 RS |
2230 | |
2231 | int | |
2232 | mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p) | |
2233 | { | |
2234 | struct mips_address_info addr; | |
2235 | int factor; | |
2236 | ||
2237 | /* BLKmode is used for single unaligned loads and stores and should | |
2238 | not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty | |
2239 | meaningless, so we have to single it out as a special case one way | |
2240 | or the other.) */ | |
5955b0a3 | 2241 | if (mode != BLKmode && might_split_p) |
656f37ee | 2242 | factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
5955b0a3 RS |
2243 | else |
2244 | factor = 1; | |
656f37ee | 2245 | |
108b61d5 RS |
2246 | if (mips_classify_address (&addr, x, mode, false)) |
2247 | switch (addr.type) | |
2248 | { | |
2249 | case ADDRESS_REG: | |
2250 | if (TARGET_MIPS16 | |
65239d20 RS |
2251 | && !mips16_unextended_reference_p (mode, addr.reg, |
2252 | UINTVAL (addr.offset))) | |
108b61d5 RS |
2253 | return factor * 2; |
2254 | return factor; | |
cafe096b | 2255 | |
108b61d5 | 2256 | case ADDRESS_LO_SUM: |
65239d20 | 2257 | return TARGET_MIPS16 ? factor * 2 : factor; |
4fef83a7 | 2258 | |
108b61d5 RS |
2259 | case ADDRESS_CONST_INT: |
2260 | return factor; | |
cafe096b | 2261 | |
108b61d5 | 2262 | case ADDRESS_SYMBOLIC: |
fbb96ac5 | 2263 | return factor * mips_symbol_insns (addr.symbol_type, mode); |
108b61d5 RS |
2264 | } |
2265 | return 0; | |
cafe096b EC |
2266 | } |
2267 | ||
65239d20 RS |
2268 | /* Return the number of instructions needed to load constant X. |
2269 | Return 0 if X isn't a valid constant. */ | |
cafe096b EC |
2270 | |
2271 | int | |
b4966b1b | 2272 | mips_const_insns (rtx x) |
cafe096b | 2273 | { |
b259a9a6 | 2274 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; |
108b61d5 | 2275 | enum mips_symbol_type symbol_type; |
7ffb5e78 | 2276 | rtx offset; |
cafe096b EC |
2277 | |
2278 | switch (GET_CODE (x)) | |
2279 | { | |
cafe096b | 2280 | case HIGH: |
c93c5160 RS |
2281 | if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA, |
2282 | &symbol_type) | |
108b61d5 RS |
2283 | || !mips_split_p[symbol_type]) |
2284 | return 0; | |
2285 | ||
65239d20 RS |
2286 | /* This is simply an LUI for normal mode. It is an extended |
2287 | LI followed by an extended SLL for MIPS16. */ | |
c93c5160 | 2288 | return TARGET_MIPS16 ? 4 : 1; |
cee98a59 MM |
2289 | |
2290 | case CONST_INT: | |
2bcb2ab3 | 2291 | if (TARGET_MIPS16) |
cafe096b EC |
2292 | /* Unsigned 8-bit constants can be loaded using an unextended |
2293 | LI instruction. Unsigned 16-bit constants can be loaded | |
2294 | using an extended LI. Negative constants must be loaded | |
2295 | using LI and then negated. */ | |
65239d20 | 2296 | return (IN_RANGE (INTVAL (x), 0, 255) ? 1 |
cafe096b | 2297 | : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 |
65239d20 | 2298 | : IN_RANGE (-INTVAL (x), 0, 255) ? 2 |
cafe096b EC |
2299 | : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 |
2300 | : 0); | |
2301 | ||
b259a9a6 | 2302 | return mips_build_integer (codes, INTVAL (x)); |
cee98a59 | 2303 | |
cafe096b | 2304 | case CONST_DOUBLE: |
06a4ab70 | 2305 | case CONST_VECTOR: |
65239d20 RS |
2306 | /* Allow zeros for normal mode, where we can use $0. */ |
2307 | return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; | |
cee98a59 | 2308 | |
108b61d5 RS |
2309 | case CONST: |
2310 | if (CONST_GP_P (x)) | |
2311 | return 1; | |
2312 | ||
2313 | /* See if we can refer to X directly. */ | |
280fcbfa | 2314 | if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type)) |
fbb96ac5 | 2315 | return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE); |
108b61d5 RS |
2316 | |
2317 | /* Otherwise try splitting the constant into a base and offset. | |
08d0963a RS |
2318 | If the offset is a 16-bit value, we can load the base address |
2319 | into a register and then use (D)ADDIU to add in the offset. | |
2320 | If the offset is larger, we can load the base and offset | |
2321 | into separate registers and add them together with (D)ADDU. | |
2322 | However, the latter is only possible before reload; during | |
2323 | and after reload, we must have the option of forcing the | |
2324 | constant into the pool instead. */ | |
7ffb5e78 | 2325 | split_const (x, &x, &offset); |
108b61d5 | 2326 | if (offset != 0) |
cafe096b | 2327 | { |
108b61d5 RS |
2328 | int n = mips_const_insns (x); |
2329 | if (n != 0) | |
2330 | { | |
7ffb5e78 | 2331 | if (SMALL_INT (offset)) |
108b61d5 | 2332 | return n + 1; |
fbbf66e7 | 2333 | else if (!targetm.cannot_force_const_mem (GET_MODE (x), x)) |
7ffb5e78 | 2334 | return n + 1 + mips_build_integer (codes, INTVAL (offset)); |
108b61d5 RS |
2335 | } |
2336 | } | |
2337 | return 0; | |
cee98a59 | 2338 | |
108b61d5 RS |
2339 | case SYMBOL_REF: |
2340 | case LABEL_REF: | |
fbb96ac5 RS |
2341 | return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA), |
2342 | MAX_MACHINE_MODE); | |
cee98a59 | 2343 | |
108b61d5 RS |
2344 | default: |
2345 | return 0; | |
cafe096b EC |
2346 | } |
2347 | } | |
cee98a59 | 2348 | |
c5cb5d18 RS |
2349 | /* X is a doubleword constant that can be handled by splitting it into |
2350 | two words and loading each word separately. Return the number of | |
2351 | instructions required to do this. */ | |
2352 | ||
2353 | int | |
2354 | mips_split_const_insns (rtx x) | |
2355 | { | |
2356 | unsigned int low, high; | |
2357 | ||
2358 | low = mips_const_insns (mips_subword (x, false)); | |
2359 | high = mips_const_insns (mips_subword (x, true)); | |
2360 | gcc_assert (low > 0 && high > 0); | |
2361 | return low + high; | |
2362 | } | |
2363 | ||
5955b0a3 RS |
2364 | /* Return the number of instructions needed to implement INSN, |
2365 | given that it loads from or stores to MEM. Count extended | |
65239d20 | 2366 | MIPS16 instructions as two instructions. */ |
f5963e61 | 2367 | |
cafe096b | 2368 | int |
5955b0a3 | 2369 | mips_load_store_insns (rtx mem, rtx insn) |
cafe096b | 2370 | { |
5955b0a3 RS |
2371 | enum machine_mode mode; |
2372 | bool might_split_p; | |
2373 | rtx set; | |
2374 | ||
2375 | gcc_assert (MEM_P (mem)); | |
2376 | mode = GET_MODE (mem); | |
2377 | ||
2378 | /* Try to prove that INSN does not need to be split. */ | |
2379 | might_split_p = true; | |
2380 | if (GET_MODE_BITSIZE (mode) == 64) | |
2381 | { | |
2382 | set = single_set (insn); | |
2383 | if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) | |
2384 | might_split_p = false; | |
2385 | } | |
2386 | ||
2387 | return mips_address_insns (XEXP (mem, 0), mode, might_split_p); | |
cafe096b | 2388 | } |
2bcb2ab3 | 2389 | |
46490403 MR |
2390 | /* Return the number of instructions needed for an integer division. */ |
2391 | ||
2392 | int | |
2393 | mips_idiv_insns (void) | |
2394 | { | |
2395 | int count; | |
2396 | ||
2397 | count = 1; | |
2398 | if (TARGET_CHECK_ZERO_DIV) | |
9f0df97a DD |
2399 | { |
2400 | if (GENERATE_DIVIDE_TRAPS) | |
2401 | count++; | |
2402 | else | |
2403 | count += 2; | |
2404 | } | |
66083422 | 2405 | |
6ba7b547 | 2406 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) |
46490403 MR |
2407 | count++; |
2408 | return count; | |
2409 | } | |
50d32cf6 | 2410 | \f |
51e7252a RS |
2411 | /* Emit a move from SRC to DEST. Assume that the move expanders can |
2412 | handle all moves if !can_create_pseudo_p (). The distinction is | |
2413 | important because, unlike emit_move_insn, the move expanders know | |
2414 | how to force Pmode objects into the constant pool even when the | |
2415 | constant pool address is not itself legitimate. */ | |
2416 | ||
2417 | rtx | |
2418 | mips_emit_move (rtx dest, rtx src) | |
2419 | { | |
2420 | return (can_create_pseudo_p () | |
2421 | ? emit_move_insn (dest, src) | |
2422 | : emit_move_insn_1 (dest, src)); | |
2423 | } | |
108b61d5 | 2424 | |
d48a3196 CF |
2425 | /* Emit an instruction of the form (set TARGET (CODE OP0)). */ |
2426 | ||
2427 | static void | |
2428 | mips_emit_unary (enum rtx_code code, rtx target, rtx op0) | |
2429 | { | |
2430 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2431 | gen_rtx_fmt_e (code, GET_MODE (op0), op0))); | |
2432 | } | |
2433 | ||
2434 | /* Compute (CODE OP0) and store the result in a new register of mode MODE. | |
2435 | Return that new register. */ | |
2436 | ||
2437 | static rtx | |
2438 | mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0) | |
2439 | { | |
2440 | rtx reg; | |
2441 | ||
2442 | reg = gen_reg_rtx (mode); | |
2443 | mips_emit_unary (code, reg, op0); | |
2444 | return reg; | |
2445 | } | |
2446 | ||
ab77a036 RS |
2447 | /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ |
2448 | ||
a2ccf3c2 | 2449 | void |
ab77a036 RS |
2450 | mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) |
2451 | { | |
2452 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2453 | gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); | |
2454 | } | |
2455 | ||
49bce30a RS |
2456 | /* Compute (CODE OP0 OP1) and store the result in a new register |
2457 | of mode MODE. Return that new register. */ | |
2458 | ||
2459 | static rtx | |
2460 | mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1) | |
2461 | { | |
2462 | rtx reg; | |
2463 | ||
2464 | reg = gen_reg_rtx (mode); | |
2465 | mips_emit_binary (code, reg, op0, op1); | |
2466 | return reg; | |
2467 | } | |
2468 | ||
65239d20 | 2469 | /* Copy VALUE to a register and return that register. If new pseudos |
108b61d5 RS |
2470 | are allowed, copy it into a new register, otherwise use DEST. */ |
2471 | ||
2472 | static rtx | |
2473 | mips_force_temporary (rtx dest, rtx value) | |
2474 | { | |
b3a13419 | 2475 | if (can_create_pseudo_p ()) |
108b61d5 RS |
2476 | return force_reg (Pmode, value); |
2477 | else | |
2478 | { | |
65239d20 | 2479 | mips_emit_move (dest, value); |
108b61d5 RS |
2480 | return dest; |
2481 | } | |
cafe096b | 2482 | } |
dbc90b65 RS |
2483 | |
2484 | /* Emit a call sequence with call pattern PATTERN and return the call | |
2485 | instruction itself (which is not necessarily the last instruction | |
08d0963a RS |
2486 | emitted). ORIG_ADDR is the original, unlegitimized address, |
2487 | ADDR is the legitimized form, and LAZY_P is true if the call | |
2488 | address is lazily-bound. */ | |
dbc90b65 RS |
2489 | |
2490 | static rtx | |
08d0963a | 2491 | mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p) |
dbc90b65 | 2492 | { |
08d0963a | 2493 | rtx insn, reg; |
dbc90b65 RS |
2494 | |
2495 | insn = emit_call_insn (pattern); | |
2496 | ||
08d0963a RS |
2497 | if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr)) |
2498 | { | |
2499 | /* MIPS16 JALRs only take MIPS16 registers. If the target | |
2500 | function requires $25 to be valid on entry, we must copy it | |
2501 | there separately. The move instruction can be put in the | |
2502 | call's delay slot. */ | |
2503 | reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
2504 | emit_insn_before (gen_move_insn (reg, addr), insn); | |
2505 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
2506 | } | |
2507 | ||
dbc90b65 | 2508 | if (lazy_p) |
08d0963a | 2509 | /* Lazy-binding stubs require $gp to be valid on entry. */ |
dbc90b65 RS |
2510 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2511 | ||
2512 | if (TARGET_USE_GOT) | |
2513 | { | |
2514 | /* See the comment above load_call<mode> for details. */ | |
2515 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2516 | gen_rtx_REG (Pmode, GOT_VERSION_REGNUM)); | |
2517 | emit_insn (gen_update_got_version ()); | |
2518 | } | |
2519 | return insn; | |
2520 | } | |
65239d20 | 2521 | \f |
7462a715 RS |
2522 | /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, |
2523 | then add CONST_INT OFFSET to the result. */ | |
2524 | ||
2525 | static rtx | |
2526 | mips_unspec_address_offset (rtx base, rtx offset, | |
2527 | enum mips_symbol_type symbol_type) | |
2528 | { | |
2529 | base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), | |
2530 | UNSPEC_ADDRESS_FIRST + symbol_type); | |
2531 | if (offset != const0_rtx) | |
2532 | base = gen_rtx_PLUS (Pmode, base, offset); | |
2533 | return gen_rtx_CONST (Pmode, base); | |
2534 | } | |
2535 | ||
2536 | /* Return an UNSPEC address with underlying address ADDRESS and symbol | |
2537 | type SYMBOL_TYPE. */ | |
2538 | ||
2539 | rtx | |
2540 | mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) | |
2541 | { | |
2542 | rtx base, offset; | |
2543 | ||
2544 | split_const (address, &base, &offset); | |
2545 | return mips_unspec_address_offset (base, offset, symbol_type); | |
2546 | } | |
2547 | ||
b53da244 AN |
2548 | /* If OP is an UNSPEC address, return the address to which it refers, |
2549 | otherwise return OP itself. */ | |
2550 | ||
2551 | static rtx | |
2552 | mips_strip_unspec_address (rtx op) | |
2553 | { | |
2554 | rtx base, offset; | |
2555 | ||
2556 | split_const (op, &base, &offset); | |
2557 | if (UNSPEC_ADDRESS_P (base)) | |
2558 | op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset)); | |
2559 | return op; | |
2560 | } | |
2561 | ||
7462a715 RS |
2562 | /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the |
2563 | high part to BASE and return the result. Just return BASE otherwise. | |
2564 | TEMP is as for mips_force_temporary. | |
2565 | ||
2566 | The returned expression can be used as the first operand to a LO_SUM. */ | |
2567 | ||
2568 | static rtx | |
2569 | mips_unspec_offset_high (rtx temp, rtx base, rtx addr, | |
2570 | enum mips_symbol_type symbol_type) | |
2571 | { | |
2572 | if (mips_split_p[symbol_type]) | |
2573 | { | |
2574 | addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); | |
2575 | addr = mips_force_temporary (temp, addr); | |
2576 | base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base)); | |
2577 | } | |
2578 | return base; | |
2579 | } | |
2580 | \f | |
5ca3d30c RS |
2581 | /* Return an instruction that copies $gp into register REG. We want |
2582 | GCC to treat the register's value as constant, so that its value | |
2583 | can be rematerialized on demand. */ | |
2584 | ||
2585 | static rtx | |
2586 | gen_load_const_gp (rtx reg) | |
2587 | { | |
81a478c8 | 2588 | return PMODE_INSN (gen_load_const_gp, (reg)); |
5ca3d30c RS |
2589 | } |
2590 | ||
65239d20 RS |
2591 | /* Return a pseudo register that contains the value of $gp throughout |
2592 | the current function. Such registers are needed by MIPS16 functions, | |
2593 | for which $gp itself is not a valid base register or addition operand. */ | |
ab77a036 RS |
2594 | |
2595 | static rtx | |
2596 | mips16_gp_pseudo_reg (void) | |
2597 | { | |
2598 | if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) | |
ab77a036 | 2599 | { |
08d0963a RS |
2600 | rtx insn, scan; |
2601 | ||
8a7a250d RS |
2602 | cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); |
2603 | ||
08d0963a RS |
2604 | push_topmost_sequence (); |
2605 | ||
2606 | scan = get_insns (); | |
2607 | while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan))) | |
2608 | scan = NEXT_INSN (scan); | |
ab77a036 | 2609 | |
ab77a036 | 2610 | insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); |
08d0963a | 2611 | emit_insn_after (insn, scan); |
ab77a036 | 2612 | |
ab77a036 | 2613 | pop_topmost_sequence (); |
ab77a036 RS |
2614 | } |
2615 | ||
2616 | return cfun->machine->mips16_gp_pseudo_rtx; | |
2617 | } | |
cafe096b | 2618 | |
08d0963a RS |
2619 | /* Return a base register that holds pic_offset_table_rtx. |
2620 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2621 | ||
2622 | rtx | |
2623 | mips_pic_base_register (rtx temp) | |
2624 | { | |
2625 | if (!TARGET_MIPS16) | |
2626 | return pic_offset_table_rtx; | |
2627 | ||
8a7a250d | 2628 | if (currently_expanding_to_rtl) |
08d0963a RS |
2629 | return mips16_gp_pseudo_reg (); |
2630 | ||
8a7a250d RS |
2631 | if (can_create_pseudo_p ()) |
2632 | temp = gen_reg_rtx (Pmode); | |
2633 | ||
08d0963a RS |
2634 | if (TARGET_USE_GOT) |
2635 | /* The first post-reload split exposes all references to $gp | |
2636 | (both uses and definitions). All references must remain | |
2637 | explicit after that point. | |
2638 | ||
2639 | It is safe to introduce uses of $gp at any time, so for | |
2640 | simplicity, we do that before the split too. */ | |
2641 | mips_emit_move (temp, pic_offset_table_rtx); | |
2642 | else | |
2643 | emit_insn (gen_load_const_gp (temp)); | |
2644 | return temp; | |
2645 | } | |
2646 | ||
b53da244 AN |
2647 | /* Return the RHS of a load_call<mode> insn. */ |
2648 | ||
2649 | static rtx | |
2650 | mips_unspec_call (rtx reg, rtx symbol) | |
2651 | { | |
2652 | rtvec vec; | |
2653 | ||
2654 | vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM)); | |
2655 | return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL); | |
2656 | } | |
2657 | ||
2658 | /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol | |
2659 | reference. Return NULL_RTX otherwise. */ | |
2660 | ||
2661 | static rtx | |
2662 | mips_strip_unspec_call (rtx src) | |
2663 | { | |
2664 | if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL) | |
2665 | return mips_strip_unspec_address (XVECEXP (src, 0, 1)); | |
2666 | return NULL_RTX; | |
2667 | } | |
2668 | ||
08d0963a RS |
2669 | /* Create and return a GOT reference of type TYPE for address ADDR. |
2670 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2671 | ||
2672 | rtx | |
2673 | mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type) | |
2674 | { | |
2675 | rtx base, high, lo_sum_symbol; | |
2676 | ||
2677 | base = mips_pic_base_register (temp); | |
2678 | ||
2679 | /* If we used the temporary register to load $gp, we can't use | |
2680 | it for the high part as well. */ | |
2681 | if (temp != NULL && reg_overlap_mentioned_p (base, temp)) | |
2682 | temp = NULL; | |
2683 | ||
2684 | high = mips_unspec_offset_high (temp, base, addr, type); | |
2685 | lo_sum_symbol = mips_unspec_address (addr, type); | |
2686 | ||
2687 | if (type == SYMBOL_GOTOFF_CALL) | |
b53da244 | 2688 | return mips_unspec_call (high, lo_sum_symbol); |
08d0963a | 2689 | else |
81a478c8 | 2690 | return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol)); |
08d0963a RS |
2691 | } |
2692 | ||
390ea488 RS |
2693 | /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise |
2694 | it appears in a MEM of that mode. Return true if ADDR is a legitimate | |
08d0963a RS |
2695 | constant in that context and can be split into high and low parts. |
2696 | If so, and if LOW_OUT is nonnull, emit the high part and store the | |
2697 | low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. | |
cafe096b | 2698 | |
390ea488 | 2699 | TEMP is as for mips_force_temporary and is used to load the high |
08d0963a RS |
2700 | part into a register. |
2701 | ||
2702 | When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be | |
2703 | a legitimize SET_SRC for an .md pattern, otherwise the low part | |
2704 | is guaranteed to be a legitimate address for mode MODE. */ | |
390ea488 RS |
2705 | |
2706 | bool | |
08d0963a | 2707 | mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out) |
cafe096b | 2708 | { |
390ea488 RS |
2709 | enum mips_symbol_context context; |
2710 | enum mips_symbol_type symbol_type; | |
108b61d5 | 2711 | rtx high; |
cafe096b | 2712 | |
390ea488 RS |
2713 | context = (mode == MAX_MACHINE_MODE |
2714 | ? SYMBOL_CONTEXT_LEA | |
2715 | : SYMBOL_CONTEXT_MEM); | |
08d0963a | 2716 | if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA) |
1732457d | 2717 | { |
08d0963a RS |
2718 | addr = XEXP (addr, 0); |
2719 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
2720 | && mips_symbol_insns (symbol_type, mode) > 0 | |
2721 | && mips_split_hi_p[symbol_type]) | |
390ea488 | 2722 | { |
08d0963a RS |
2723 | if (low_out) |
2724 | switch (symbol_type) | |
2725 | { | |
2726 | case SYMBOL_GOT_PAGE_OFST: | |
2727 | /* The high part of a page/ofst pair is loaded from the GOT. */ | |
2728 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE); | |
2729 | break; | |
2730 | ||
2731 | default: | |
2732 | gcc_unreachable (); | |
2733 | } | |
2734 | return true; | |
390ea488 | 2735 | } |
08d0963a RS |
2736 | } |
2737 | else | |
2738 | { | |
2739 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
2740 | && mips_symbol_insns (symbol_type, mode) > 0 | |
2741 | && mips_split_p[symbol_type]) | |
390ea488 | 2742 | { |
08d0963a RS |
2743 | if (low_out) |
2744 | switch (symbol_type) | |
2745 | { | |
2746 | case SYMBOL_GOT_DISP: | |
2747 | /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */ | |
2748 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP); | |
2749 | break; | |
2750 | ||
2751 | case SYMBOL_GP_RELATIVE: | |
2752 | high = mips_pic_base_register (temp); | |
2753 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
2754 | break; | |
2755 | ||
2756 | default: | |
2757 | high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); | |
2758 | high = mips_force_temporary (temp, high); | |
2759 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
2760 | break; | |
2761 | } | |
2762 | return true; | |
390ea488 | 2763 | } |
1732457d | 2764 | } |
08d0963a | 2765 | return false; |
cafe096b EC |
2766 | } |
2767 | ||
b73ce23b RS |
2768 | /* Return a legitimate address for REG + OFFSET. TEMP is as for |
2769 | mips_force_temporary; it is only needed when OFFSET is not a | |
2770 | SMALL_OPERAND. */ | |
cafe096b | 2771 | |
108b61d5 | 2772 | static rtx |
b73ce23b | 2773 | mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) |
cafe096b | 2774 | { |
108b61d5 | 2775 | if (!SMALL_OPERAND (offset)) |
b73ce23b RS |
2776 | { |
2777 | rtx high; | |
65239d20 | 2778 | |
b73ce23b RS |
2779 | if (TARGET_MIPS16) |
2780 | { | |
2781 | /* Load the full offset into a register so that we can use | |
2782 | an unextended instruction for the address itself. */ | |
2783 | high = GEN_INT (offset); | |
2784 | offset = 0; | |
2785 | } | |
2786 | else | |
2787 | { | |
6d8f135b JW |
2788 | /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. |
2789 | The addition inside the macro CONST_HIGH_PART may cause an | |
2790 | overflow, so we need to force a sign-extension check. */ | |
2791 | high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); | |
b73ce23b RS |
2792 | offset = CONST_LOW_PART (offset); |
2793 | } | |
2794 | high = mips_force_temporary (temp, high); | |
2795 | reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); | |
2796 | } | |
2797 | return plus_constant (reg, offset); | |
cafe096b | 2798 | } |
65239d20 RS |
2799 | \f |
2800 | /* The __tls_get_attr symbol. */ | |
69229b81 DJ |
2801 | static GTY(()) rtx mips_tls_symbol; |
2802 | ||
65239d20 RS |
2803 | /* Return an instruction sequence that calls __tls_get_addr. SYM is |
2804 | the TLS symbol we are referencing and TYPE is the symbol type to use | |
2805 | (either global dynamic or local dynamic). V0 is an RTX for the | |
2806 | return value location. */ | |
2807 | ||
69229b81 DJ |
2808 | static rtx |
2809 | mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0) | |
2810 | { | |
dbc90b65 | 2811 | rtx insn, loc, a0; |
69229b81 DJ |
2812 | |
2813 | a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); | |
2814 | ||
2815 | if (!mips_tls_symbol) | |
2816 | mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2817 | ||
2818 | loc = mips_unspec_address (sym, type); | |
2819 | ||
2820 | start_sequence (); | |
2821 | ||
2822 | emit_insn (gen_rtx_SET (Pmode, a0, | |
2823 | gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); | |
08d0963a RS |
2824 | insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol, |
2825 | const0_rtx, NULL_RTX, false); | |
becfd6e5 | 2826 | RTL_CONST_CALL_P (insn) = 1; |
69229b81 DJ |
2827 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); |
2828 | insn = get_insns (); | |
2829 | ||
2830 | end_sequence (); | |
2831 | ||
2832 | return insn; | |
2833 | } | |
2834 | ||
256f27f1 RS |
2835 | /* Return a pseudo register that contains the current thread pointer. */ |
2836 | ||
2837 | static rtx | |
2838 | mips_get_tp (void) | |
2839 | { | |
ddaf8125 | 2840 | rtx tp, fn; |
256f27f1 RS |
2841 | |
2842 | tp = gen_reg_rtx (Pmode); | |
ddaf8125 RS |
2843 | if (TARGET_MIPS16) |
2844 | { | |
2845 | fn = mips16_stub_function ("__mips16_rdhwr"); | |
2846 | if (!call_insn_operand (fn, VOIDmode)) | |
2847 | fn = force_reg (Pmode, fn); | |
2848 | emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn))); | |
2849 | } | |
256f27f1 | 2850 | else |
ddaf8125 | 2851 | emit_insn (PMODE_INSN (gen_tls_get_tp, (tp))); |
256f27f1 RS |
2852 | return tp; |
2853 | } | |
2854 | ||
65239d20 RS |
2855 | /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return |
2856 | its address. The return value will be both a valid address and a valid | |
2857 | SET_SRC (either a REG or a LO_SUM). */ | |
69229b81 DJ |
2858 | |
2859 | static rtx | |
2860 | mips_legitimize_tls_address (rtx loc) | |
2861 | { | |
ddaf8125 | 2862 | rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset; |
69229b81 DJ |
2863 | enum tls_model model; |
2864 | ||
69229b81 | 2865 | model = SYMBOL_REF_TLS_MODEL (loc); |
4afa41f1 RS |
2866 | /* Only TARGET_ABICALLS code can have more than one module; other |
2867 | code must be be static and should not use a GOT. All TLS models | |
2868 | reduce to local exec in this situation. */ | |
2869 | if (!TARGET_ABICALLS) | |
2870 | model = TLS_MODEL_LOCAL_EXEC; | |
69229b81 DJ |
2871 | |
2872 | switch (model) | |
2873 | { | |
2874 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
65239d20 | 2875 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
2876 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0); |
2877 | dest = gen_reg_rtx (Pmode); | |
2878 | emit_libcall_block (insn, dest, v0, loc); | |
2879 | break; | |
2880 | ||
2881 | case TLS_MODEL_LOCAL_DYNAMIC: | |
65239d20 | 2882 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
2883 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0); |
2884 | tmp1 = gen_reg_rtx (Pmode); | |
2885 | ||
2886 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2887 | share the LDM result with other LD model accesses. */ | |
2888 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2889 | UNSPEC_TLS_LDM); | |
2890 | emit_libcall_block (insn, tmp1, v0, eqv); | |
2891 | ||
ddaf8125 RS |
2892 | offset = mips_unspec_address (loc, SYMBOL_DTPREL); |
2893 | if (mips_split_p[SYMBOL_DTPREL]) | |
2894 | { | |
2895 | tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL); | |
2896 | dest = gen_rtx_LO_SUM (Pmode, tmp2, offset); | |
2897 | } | |
2898 | else | |
2899 | dest = expand_binop (Pmode, add_optab, tmp1, offset, | |
2900 | 0, 0, OPTAB_DIRECT); | |
69229b81 DJ |
2901 | break; |
2902 | ||
2903 | case TLS_MODEL_INITIAL_EXEC: | |
256f27f1 | 2904 | tp = mips_get_tp (); |
69229b81 DJ |
2905 | tmp1 = gen_reg_rtx (Pmode); |
2906 | tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); | |
2907 | if (Pmode == DImode) | |
256f27f1 | 2908 | emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 2909 | else |
256f27f1 | 2910 | emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 2911 | dest = gen_reg_rtx (Pmode); |
256f27f1 | 2912 | emit_insn (gen_add3_insn (dest, tmp1, tp)); |
69229b81 DJ |
2913 | break; |
2914 | ||
2915 | case TLS_MODEL_LOCAL_EXEC: | |
ddaf8125 RS |
2916 | tmp1 = mips_get_tp (); |
2917 | offset = mips_unspec_address (loc, SYMBOL_TPREL); | |
2918 | if (mips_split_p[SYMBOL_TPREL]) | |
2919 | { | |
2920 | tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL); | |
2921 | dest = gen_rtx_LO_SUM (Pmode, tmp2, offset); | |
2922 | } | |
2923 | else | |
2924 | dest = expand_binop (Pmode, add_optab, tmp1, offset, | |
2925 | 0, 0, OPTAB_DIRECT); | |
69229b81 DJ |
2926 | break; |
2927 | ||
2928 | default: | |
107a4b41 | 2929 | gcc_unreachable (); |
69229b81 | 2930 | } |
69229b81 DJ |
2931 | return dest; |
2932 | } | |
65239d20 | 2933 | \f |
fa21a761 RS |
2934 | /* If X is not a valid address for mode MODE, force it into a register. */ |
2935 | ||
2936 | static rtx | |
2937 | mips_force_address (rtx x, enum machine_mode mode) | |
2938 | { | |
2939 | if (!mips_legitimate_address_p (mode, x, false)) | |
2940 | x = force_reg (Pmode, x); | |
2941 | return x; | |
2942 | } | |
2943 | ||
506d7b68 | 2944 | /* This function is used to implement LEGITIMIZE_ADDRESS. If X can |
cafe096b | 2945 | be legitimized in a way that the generic machinery might not expect, |
506d7b68 | 2946 | return a new address, otherwise return NULL. MODE is the mode of |
cafe096b | 2947 | the memory being accessed. */ |
910628b8 | 2948 | |
506d7b68 PB |
2949 | static rtx |
2950 | mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
2951 | enum machine_mode mode) | |
7dac2f89 | 2952 | { |
fa21a761 | 2953 | rtx base, addr; |
65239d20 RS |
2954 | HOST_WIDE_INT offset; |
2955 | ||
506d7b68 PB |
2956 | if (mips_tls_symbol_p (x)) |
2957 | return mips_legitimize_tls_address (x); | |
69229b81 | 2958 | |
108b61d5 | 2959 | /* See if the address can split into a high part and a LO_SUM. */ |
506d7b68 PB |
2960 | if (mips_split_symbol (NULL, x, mode, &addr)) |
2961 | return mips_force_address (addr, mode); | |
910628b8 | 2962 | |
65239d20 | 2963 | /* Handle BASE + OFFSET using mips_add_offset. */ |
506d7b68 | 2964 | mips_split_plus (x, &base, &offset); |
65239d20 | 2965 | if (offset != 0) |
cafe096b | 2966 | { |
65239d20 RS |
2967 | if (!mips_valid_base_register_p (base, mode, false)) |
2968 | base = copy_to_mode_reg (Pmode, base); | |
fa21a761 | 2969 | addr = mips_add_offset (NULL, base, offset); |
506d7b68 | 2970 | return mips_force_address (addr, mode); |
cafe096b | 2971 | } |
506d7b68 PB |
2972 | |
2973 | return x; | |
50c0000c | 2974 | } |
c94c9817 | 2975 | |
65239d20 | 2976 | /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */ |
b259a9a6 | 2977 | |
ea462dd0 | 2978 | void |
65239d20 | 2979 | mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) |
b259a9a6 RS |
2980 | { |
2981 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; | |
2982 | enum machine_mode mode; | |
65239d20 | 2983 | unsigned int i, num_ops; |
b259a9a6 RS |
2984 | rtx x; |
2985 | ||
2986 | mode = GET_MODE (dest); | |
65239d20 | 2987 | num_ops = mips_build_integer (codes, value); |
b259a9a6 RS |
2988 | |
2989 | /* Apply each binary operation to X. Invariant: X is a legitimate | |
2990 | source operand for a SET pattern. */ | |
2991 | x = GEN_INT (codes[0].value); | |
65239d20 | 2992 | for (i = 1; i < num_ops; i++) |
b259a9a6 | 2993 | { |
b3a13419 | 2994 | if (!can_create_pseudo_p ()) |
ea462dd0 RS |
2995 | { |
2996 | emit_insn (gen_rtx_SET (VOIDmode, temp, x)); | |
2997 | x = temp; | |
2998 | } | |
b259a9a6 RS |
2999 | else |
3000 | x = force_reg (mode, x); | |
3001 | x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); | |
3002 | } | |
3003 | ||
3004 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
3005 | } | |
3006 | ||
cafe096b EC |
3007 | /* Subroutine of mips_legitimize_move. Move constant SRC into register |
3008 | DEST given that SRC satisfies immediate_operand but doesn't satisfy | |
3009 | move_operand. */ | |
3010 | ||
3011 | static void | |
b4966b1b | 3012 | mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src) |
c94c9817 | 3013 | { |
7ffb5e78 | 3014 | rtx base, offset; |
cafe096b | 3015 | |
ea462dd0 RS |
3016 | /* Split moves of big integers into smaller pieces. */ |
3017 | if (splittable_const_int_operand (src, mode)) | |
b259a9a6 | 3018 | { |
ea462dd0 | 3019 | mips_move_integer (dest, dest, INTVAL (src)); |
b259a9a6 RS |
3020 | return; |
3021 | } | |
3022 | ||
ea462dd0 | 3023 | /* Split moves of symbolic constants into high/low pairs. */ |
390ea488 | 3024 | if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) |
69229b81 | 3025 | { |
390ea488 | 3026 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); |
69229b81 DJ |
3027 | return; |
3028 | } | |
3029 | ||
65239d20 RS |
3030 | /* Generate the appropriate access sequences for TLS symbols. */ |
3031 | if (mips_tls_symbol_p (src)) | |
cafe096b | 3032 | { |
51e7252a | 3033 | mips_emit_move (dest, mips_legitimize_tls_address (src)); |
cafe096b EC |
3034 | return; |
3035 | } | |
3036 | ||
edede024 SL |
3037 | /* If we have (const (plus symbol offset)), and that expression cannot |
3038 | be forced into memory, load the symbol first and add in the offset. | |
3039 | In non-MIPS16 mode, prefer to do this even if the constant _can_ be | |
3040 | forced into memory, as it usually produces better code. */ | |
7ffb5e78 | 3041 | split_const (src, &base, &offset); |
edede024 | 3042 | if (offset != const0_rtx |
fbbf66e7 | 3043 | && (targetm.cannot_force_const_mem (mode, src) |
edede024 | 3044 | || (!TARGET_MIPS16 && can_create_pseudo_p ()))) |
cafe096b | 3045 | { |
108b61d5 | 3046 | base = mips_force_temporary (dest, base); |
65239d20 | 3047 | mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset))); |
cafe096b EC |
3048 | return; |
3049 | } | |
3050 | ||
3051 | src = force_const_mem (mode, src); | |
3052 | ||
3053 | /* When using explicit relocs, constant pool references are sometimes | |
108b61d5 | 3054 | not legitimate addresses. */ |
390ea488 | 3055 | mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); |
51e7252a | 3056 | mips_emit_move (dest, src); |
c94c9817 MM |
3057 | } |
3058 | ||
65239d20 | 3059 | /* If (set DEST SRC) is not a valid move instruction, emit an equivalent |
cafe096b EC |
3060 | sequence that is valid. */ |
3061 | ||
3062 | bool | |
b4966b1b | 3063 | mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src) |
c94c9817 | 3064 | { |
cafe096b | 3065 | if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) |
7dac2f89 | 3066 | { |
51e7252a | 3067 | mips_emit_move (dest, force_reg (mode, src)); |
cafe096b | 3068 | return true; |
7dac2f89 EC |
3069 | } |
3070 | ||
fc31c7ca | 3071 | /* We need to deal with constants that would be legitimate |
65239d20 | 3072 | immediate_operands but aren't legitimate move_operands. */ |
fc31c7ca | 3073 | if (CONSTANT_P (src) && !move_operand (src, mode)) |
cafe096b EC |
3074 | { |
3075 | mips_legitimize_const_move (mode, dest, src); | |
3076 | set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); | |
3077 | return true; | |
3078 | } | |
3079 | return false; | |
3080 | } | |
cee98a59 | 3081 | \f |
65239d20 RS |
3082 | /* Return true if value X in context CONTEXT is a small-data address |
3083 | that can be rewritten as a LO_SUM. */ | |
ab77a036 RS |
3084 | |
3085 | static bool | |
3086 | mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context) | |
3087 | { | |
3088 | enum mips_symbol_type symbol_type; | |
3089 | ||
08d0963a RS |
3090 | return (mips_lo_relocs[SYMBOL_GP_RELATIVE] |
3091 | && !mips_split_p[SYMBOL_GP_RELATIVE] | |
ab77a036 RS |
3092 | && mips_symbolic_constant_p (x, context, &symbol_type) |
3093 | && symbol_type == SYMBOL_GP_RELATIVE); | |
3094 | } | |
3095 | ||
ab77a036 RS |
3096 | /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the |
3097 | containing MEM, or null if none. */ | |
3098 | ||
3099 | static int | |
3100 | mips_small_data_pattern_1 (rtx *loc, void *data) | |
3101 | { | |
3102 | enum mips_symbol_context context; | |
3103 | ||
e906c889 RS |
3104 | /* Ignore things like "g" constraints in asms. We make no particular |
3105 | guarantee about which symbolic constants are acceptable as asm operands | |
3106 | versus which must be forced into a GPR. */ | |
3107 | if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS) | |
ab77a036 RS |
3108 | return -1; |
3109 | ||
3110 | if (MEM_P (*loc)) | |
3111 | { | |
3112 | if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc)) | |
3113 | return 1; | |
3114 | return -1; | |
3115 | } | |
3116 | ||
3117 | context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA; | |
3118 | return mips_rewrite_small_data_p (*loc, context); | |
3119 | } | |
3120 | ||
3121 | /* Return true if OP refers to small data symbols directly, not through | |
3122 | a LO_SUM. */ | |
3123 | ||
3124 | bool | |
3125 | mips_small_data_pattern_p (rtx op) | |
3126 | { | |
65239d20 | 3127 | return for_each_rtx (&op, mips_small_data_pattern_1, NULL); |
ab77a036 | 3128 | } |
65239d20 | 3129 | |
ab77a036 RS |
3130 | /* A for_each_rtx callback, used by mips_rewrite_small_data. |
3131 | DATA is the containing MEM, or null if none. */ | |
3132 | ||
3133 | static int | |
3134 | mips_rewrite_small_data_1 (rtx *loc, void *data) | |
3135 | { | |
3136 | enum mips_symbol_context context; | |
3137 | ||
3138 | if (MEM_P (*loc)) | |
3139 | { | |
3140 | for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc); | |
3141 | return -1; | |
3142 | } | |
3143 | ||
3144 | context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA; | |
3145 | if (mips_rewrite_small_data_p (*loc, context)) | |
3146 | *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc); | |
3147 | ||
3148 | if (GET_CODE (*loc) == LO_SUM) | |
3149 | return -1; | |
3150 | ||
3151 | return 0; | |
3152 | } | |
3153 | ||
65239d20 RS |
3154 | /* Rewrite instruction pattern PATTERN so that it refers to small data |
3155 | using explicit relocations. */ | |
ab77a036 RS |
3156 | |
3157 | rtx | |
65239d20 | 3158 | mips_rewrite_small_data (rtx pattern) |
ab77a036 | 3159 | { |
65239d20 RS |
3160 | pattern = copy_insn (pattern); |
3161 | for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL); | |
3162 | return pattern; | |
ab77a036 RS |
3163 | } |
3164 | \f | |
65239d20 RS |
3165 | /* We need a lot of little routines to check the range of MIPS16 immediate |
3166 | operands. */ | |
2bcb2ab3 GK |
3167 | |
3168 | static int | |
b4966b1b | 3169 | m16_check_op (rtx op, int low, int high, int mask) |
2bcb2ab3 | 3170 | { |
47ac44d6 | 3171 | return (CONST_INT_P (op) |
65239d20 | 3172 | && IN_RANGE (INTVAL (op), low, high) |
2bcb2ab3 GK |
3173 | && (INTVAL (op) & mask) == 0); |
3174 | } | |
3175 | ||
3176 | int | |
b4966b1b | 3177 | m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3178 | { |
3179 | return m16_check_op (op, 0x1, 0x8, 0); | |
3180 | } | |
3181 | ||
3182 | int | |
b4966b1b | 3183 | m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3184 | { |
65239d20 | 3185 | return m16_check_op (op, -0x8, 0x7, 0); |
2bcb2ab3 GK |
3186 | } |
3187 | ||
3188 | int | |
b4966b1b | 3189 | m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3190 | { |
65239d20 | 3191 | return m16_check_op (op, -0x7, 0x8, 0); |
2bcb2ab3 GK |
3192 | } |
3193 | ||
3194 | int | |
b4966b1b | 3195 | m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3196 | { |
65239d20 | 3197 | return m16_check_op (op, -0x10, 0xf, 0); |
2bcb2ab3 GK |
3198 | } |
3199 | ||
3200 | int | |
b4966b1b | 3201 | m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3202 | { |
65239d20 | 3203 | return m16_check_op (op, -0xf, 0x10, 0); |
2bcb2ab3 GK |
3204 | } |
3205 | ||
3206 | int | |
b4966b1b | 3207 | m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3208 | { |
65239d20 | 3209 | return m16_check_op (op, -0x10 << 2, 0xf << 2, 3); |
2bcb2ab3 GK |
3210 | } |
3211 | ||
3212 | int | |
b4966b1b | 3213 | m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3214 | { |
65239d20 | 3215 | return m16_check_op (op, -0xf << 2, 0x10 << 2, 3); |
2bcb2ab3 GK |
3216 | } |
3217 | ||
3218 | int | |
b4966b1b | 3219 | m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3220 | { |
65239d20 | 3221 | return m16_check_op (op, -0x80, 0x7f, 0); |
2bcb2ab3 GK |
3222 | } |
3223 | ||
3224 | int | |
b4966b1b | 3225 | m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3226 | { |
65239d20 | 3227 | return m16_check_op (op, -0x7f, 0x80, 0); |
2bcb2ab3 GK |
3228 | } |
3229 | ||
3230 | int | |
b4966b1b | 3231 | m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3232 | { |
3233 | return m16_check_op (op, 0x0, 0xff, 0); | |
3234 | } | |
3235 | ||
3236 | int | |
b4966b1b | 3237 | m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3238 | { |
65239d20 | 3239 | return m16_check_op (op, -0xff, 0x0, 0); |
2bcb2ab3 GK |
3240 | } |
3241 | ||
3242 | int | |
b4966b1b | 3243 | m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3244 | { |
65239d20 | 3245 | return m16_check_op (op, -0x1, 0xfe, 0); |
2bcb2ab3 GK |
3246 | } |
3247 | ||
3248 | int | |
b4966b1b | 3249 | m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3250 | { |
3251 | return m16_check_op (op, 0x0, 0xff << 2, 3); | |
3252 | } | |
3253 | ||
3254 | int | |
b4966b1b | 3255 | m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3256 | { |
65239d20 | 3257 | return m16_check_op (op, -0xff << 2, 0x0, 3); |
2bcb2ab3 GK |
3258 | } |
3259 | ||
3260 | int | |
b4966b1b | 3261 | m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3262 | { |
65239d20 | 3263 | return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7); |
2bcb2ab3 GK |
3264 | } |
3265 | ||
3266 | int | |
b4966b1b | 3267 | m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3268 | { |
65239d20 | 3269 | return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7); |
2bcb2ab3 | 3270 | } |
cee98a59 | 3271 | \f |
8144a1a8 RS |
3272 | /* The cost of loading values from the constant pool. It should be |
3273 | larger than the cost of any constant we want to synthesize inline. */ | |
8144a1a8 RS |
3274 | #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8) |
3275 | ||
3276 | /* Return the cost of X when used as an operand to the MIPS16 instruction | |
3277 | that implements CODE. Return -1 if there is no such instruction, or if | |
3278 | X is not a valid immediate operand for it. */ | |
3279 | ||
3280 | static int | |
3281 | mips16_constant_cost (int code, HOST_WIDE_INT x) | |
3282 | { | |
3283 | switch (code) | |
3284 | { | |
3285 | case ASHIFT: | |
3286 | case ASHIFTRT: | |
3287 | case LSHIFTRT: | |
3288 | /* Shifts by between 1 and 8 bits (inclusive) are unextended, | |
3289 | other shifts are extended. The shift patterns truncate the shift | |
3290 | count to the right size, so there are no out-of-range values. */ | |
3291 | if (IN_RANGE (x, 1, 8)) | |
3292 | return 0; | |
3293 | return COSTS_N_INSNS (1); | |
3294 | ||
3295 | case PLUS: | |
3296 | if (IN_RANGE (x, -128, 127)) | |
3297 | return 0; | |
3298 | if (SMALL_OPERAND (x)) | |
3299 | return COSTS_N_INSNS (1); | |
3300 | return -1; | |
3301 | ||
3302 | case LEU: | |
3303 | /* Like LE, but reject the always-true case. */ | |
3304 | if (x == -1) | |
3305 | return -1; | |
3306 | case LE: | |
3307 | /* We add 1 to the immediate and use SLT. */ | |
3308 | x += 1; | |
3309 | case XOR: | |
3310 | /* We can use CMPI for an xor with an unsigned 16-bit X. */ | |
3311 | case LT: | |
3312 | case LTU: | |
3313 | if (IN_RANGE (x, 0, 255)) | |
3314 | return 0; | |
3315 | if (SMALL_OPERAND_UNSIGNED (x)) | |
3316 | return COSTS_N_INSNS (1); | |
3317 | return -1; | |
3318 | ||
3319 | case EQ: | |
3320 | case NE: | |
3321 | /* Equality comparisons with 0 are cheap. */ | |
3322 | if (x == 0) | |
3323 | return 0; | |
3324 | return -1; | |
3325 | ||
3326 | default: | |
3327 | return -1; | |
3328 | } | |
3329 | } | |
3330 | ||
3331 | /* Return true if there is a non-MIPS16 instruction that implements CODE | |
3332 | and if that instruction accepts X as an immediate operand. */ | |
3333 | ||
3334 | static int | |
3335 | mips_immediate_operand_p (int code, HOST_WIDE_INT x) | |
3336 | { | |
3337 | switch (code) | |
3338 | { | |
3339 | case ASHIFT: | |
3340 | case ASHIFTRT: | |
3341 | case LSHIFTRT: | |
3342 | /* All shift counts are truncated to a valid constant. */ | |
3343 | return true; | |
3344 | ||
3345 | case ROTATE: | |
3346 | case ROTATERT: | |
3347 | /* Likewise rotates, if the target supports rotates at all. */ | |
3348 | return ISA_HAS_ROR; | |
3349 | ||
3350 | case AND: | |
3351 | case IOR: | |
3352 | case XOR: | |
3353 | /* These instructions take 16-bit unsigned immediates. */ | |
3354 | return SMALL_OPERAND_UNSIGNED (x); | |
3355 | ||
3356 | case PLUS: | |
3357 | case LT: | |
3358 | case LTU: | |
3359 | /* These instructions take 16-bit signed immediates. */ | |
3360 | return SMALL_OPERAND (x); | |
3361 | ||
3362 | case EQ: | |
3363 | case NE: | |
3364 | case GT: | |
3365 | case GTU: | |
3366 | /* The "immediate" forms of these instructions are really | |
3367 | implemented as comparisons with register 0. */ | |
3368 | return x == 0; | |
3369 | ||
3370 | case GE: | |
3371 | case GEU: | |
3372 | /* Likewise, meaning that the only valid immediate operand is 1. */ | |
3373 | return x == 1; | |
3374 | ||
3375 | case LE: | |
3376 | /* We add 1 to the immediate and use SLT. */ | |
3377 | return SMALL_OPERAND (x + 1); | |
3378 | ||
3379 | case LEU: | |
3380 | /* Likewise SLTU, but reject the always-true case. */ | |
3381 | return SMALL_OPERAND (x + 1) && x + 1 != 0; | |
3382 | ||
3383 | case SIGN_EXTRACT: | |
3384 | case ZERO_EXTRACT: | |
3385 | /* The bit position and size are immediate operands. */ | |
3386 | return ISA_HAS_EXT_INS; | |
3387 | ||
3388 | default: | |
3389 | /* By default assume that $0 can be used for 0. */ | |
3390 | return x == 0; | |
3391 | } | |
3392 | } | |
3393 | ||
3394 | /* Return the cost of binary operation X, given that the instruction | |
3395 | sequence for a word-sized or smaller operation has cost SINGLE_COST | |
53d66977 AN |
3396 | and that the sequence of a double-word operation has cost DOUBLE_COST. |
3397 | If SPEED is true, optimize for speed otherwise optimize for size. */ | |
8144a1a8 RS |
3398 | |
3399 | static int | |
53d66977 | 3400 | mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) |
8144a1a8 RS |
3401 | { |
3402 | int cost; | |
3403 | ||
3404 | if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) | |
3405 | cost = double_cost; | |
3406 | else | |
3407 | cost = single_cost; | |
3408 | return (cost | |
5e8f01f4 | 3409 | + set_src_cost (XEXP (x, 0), speed) |
68f932c4 | 3410 | + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed)); |
8144a1a8 RS |
3411 | } |
3412 | ||
3413 | /* Return the cost of floating-point multiplications of mode MODE. */ | |
3414 | ||
3415 | static int | |
3416 | mips_fp_mult_cost (enum machine_mode mode) | |
3417 | { | |
3418 | return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; | |
3419 | } | |
3420 | ||
3421 | /* Return the cost of floating-point divisions of mode MODE. */ | |
3422 | ||
3423 | static int | |
3424 | mips_fp_div_cost (enum machine_mode mode) | |
3425 | { | |
3426 | return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; | |
3427 | } | |
3428 | ||
3429 | /* Return the cost of sign-extending OP to mode MODE, not including the | |
3430 | cost of OP itself. */ | |
3431 | ||
3432 | static int | |
3433 | mips_sign_extend_cost (enum machine_mode mode, rtx op) | |
3434 | { | |
3435 | if (MEM_P (op)) | |
3436 | /* Extended loads are as cheap as unextended ones. */ | |
3437 | return 0; | |
3438 | ||
3439 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3440 | /* A sign extension from SImode to DImode in 64-bit mode is free. */ | |
3441 | return 0; | |
3442 | ||
3443 | if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E) | |
3444 | /* We can use SEB or SEH. */ | |
3445 | return COSTS_N_INSNS (1); | |
3446 | ||
3447 | /* We need to use a shift left and a shift right. */ | |
3448 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3449 | } | |
3450 | ||
3451 | /* Return the cost of zero-extending OP to mode MODE, not including the | |
3452 | cost of OP itself. */ | |
3453 | ||
3454 | static int | |
3455 | mips_zero_extend_cost (enum machine_mode mode, rtx op) | |
3456 | { | |
3457 | if (MEM_P (op)) | |
3458 | /* Extended loads are as cheap as unextended ones. */ | |
3459 | return 0; | |
3460 | ||
3461 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3462 | /* We need a shift left by 32 bits and a shift right by 32 bits. */ | |
3463 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3464 | ||
3465 | if (GENERATE_MIPS16E) | |
3466 | /* We can use ZEB or ZEH. */ | |
3467 | return COSTS_N_INSNS (1); | |
3468 | ||
3469 | if (TARGET_MIPS16) | |
3470 | /* We need to load 0xff or 0xffff into a register and use AND. */ | |
3471 | return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3); | |
3472 | ||
3473 | /* We can use ANDI. */ | |
3474 | return COSTS_N_INSNS (1); | |
3475 | } | |
3476 | ||
3477 | /* Implement TARGET_RTX_COSTS. */ | |
3478 | ||
cafe096b | 3479 | static bool |
68f932c4 RS |
3480 | mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
3481 | int *total, bool speed) | |
cafe096b EC |
3482 | { |
3483 | enum machine_mode mode = GET_MODE (x); | |
c1bd2d66 | 3484 | bool float_mode_p = FLOAT_MODE_P (mode); |
8144a1a8 RS |
3485 | int cost; |
3486 | rtx addr; | |
3487 | ||
3488 | /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't | |
3489 | appear in the instruction stream, and the cost of a comparison is | |
3490 | really the cost of the branch or scc condition. At the time of | |
65239d20 | 3491 | writing, GCC only uses an explicit outer COMPARE code when optabs |
8144a1a8 RS |
3492 | is testing whether a constant is expensive enough to force into a |
3493 | register. We want optabs to pass such constants through the MIPS | |
3494 | expanders instead, so make all constants very cheap here. */ | |
3495 | if (outer_code == COMPARE) | |
3496 | { | |
3497 | gcc_assert (CONSTANT_P (x)); | |
3498 | *total = 0; | |
3499 | return true; | |
3500 | } | |
c1bd2d66 | 3501 | |
cafe096b EC |
3502 | switch (code) |
3503 | { | |
3504 | case CONST_INT: | |
8144a1a8 RS |
3505 | /* Treat *clear_upper32-style ANDs as having zero cost in the |
3506 | second operand. The cost is entirely in the first operand. | |
3507 | ||
3508 | ??? This is needed because we would otherwise try to CSE | |
3509 | the constant operand. Although that's the right thing for | |
3510 | instructions that continue to be a register operation throughout | |
3511 | compilation, it is disastrous for instructions that could | |
3512 | later be converted into a memory operation. */ | |
3513 | if (TARGET_64BIT | |
3514 | && outer_code == AND | |
3515 | && UINTVAL (x) == 0xffffffff) | |
3516 | { | |
3517 | *total = 0; | |
3518 | return true; | |
3519 | } | |
cafe096b | 3520 | |
8144a1a8 RS |
3521 | if (TARGET_MIPS16) |
3522 | { | |
3523 | cost = mips16_constant_cost (outer_code, INTVAL (x)); | |
3524 | if (cost >= 0) | |
c1bd2d66 | 3525 | { |
8144a1a8 | 3526 | *total = cost; |
c1bd2d66 EC |
3527 | return true; |
3528 | } | |
8144a1a8 RS |
3529 | } |
3530 | else | |
3531 | { | |
3532 | /* When not optimizing for size, we care more about the cost | |
3533 | of hot code, and hot code is often in a loop. If a constant | |
3534 | operand needs to be forced into a register, we will often be | |
3535 | able to hoist the constant load out of the loop, so the load | |
3536 | should not contribute to the cost. */ | |
53d66977 | 3537 | if (speed || mips_immediate_operand_p (outer_code, INTVAL (x))) |
c1bd2d66 EC |
3538 | { |
3539 | *total = 0; | |
3540 | return true; | |
3541 | } | |
3542 | } | |
8144a1a8 | 3543 | /* Fall through. */ |
cafe096b EC |
3544 | |
3545 | case CONST: | |
3546 | case SYMBOL_REF: | |
3547 | case LABEL_REF: | |
3548 | case CONST_DOUBLE: | |
206c2d7a RS |
3549 | if (force_to_mem_operand (x, VOIDmode)) |
3550 | { | |
3551 | *total = COSTS_N_INSNS (1); | |
3552 | return true; | |
3553 | } | |
8144a1a8 RS |
3554 | cost = mips_const_insns (x); |
3555 | if (cost > 0) | |
108b61d5 | 3556 | { |
8144a1a8 RS |
3557 | /* If the constant is likely to be stored in a GPR, SETs of |
3558 | single-insn constants are as cheap as register sets; we | |
3559 | never want to CSE them. | |
3560 | ||
3561 | Don't reduce the cost of storing a floating-point zero in | |
3562 | FPRs. If we have a zero in an FPR for other reasons, we | |
3563 | can get better cfg-cleanup and delayed-branch results by | |
3564 | using it consistently, rather than using $0 sometimes and | |
3565 | an FPR at other times. Also, moves between floating-point | |
3566 | registers are sometimes cheaper than (D)MTC1 $0. */ | |
3567 | if (cost == 1 | |
3568 | && outer_code == SET | |
3569 | && !(float_mode_p && TARGET_HARD_FLOAT)) | |
3570 | cost = 0; | |
3571 | /* When non-MIPS16 code loads a constant N>1 times, we rarely | |
3572 | want to CSE the constant itself. It is usually better to | |
3573 | have N copies of the last operation in the sequence and one | |
3574 | shared copy of the other operations. (Note that this is | |
3575 | not true for MIPS16 code, where the final operation in the | |
3576 | sequence is often an extended instruction.) | |
3577 | ||
3578 | Also, if we have a CONST_INT, we don't know whether it is | |
3579 | for a word or doubleword operation, so we cannot rely on | |
3580 | the result of mips_build_integer. */ | |
3581 | else if (!TARGET_MIPS16 | |
3582 | && (outer_code == SET || mode == VOIDmode)) | |
3583 | cost = 1; | |
3584 | *total = COSTS_N_INSNS (cost); | |
108b61d5 RS |
3585 | return true; |
3586 | } | |
8144a1a8 RS |
3587 | /* The value will need to be fetched from the constant pool. */ |
3588 | *total = CONSTANT_POOL_COST; | |
3589 | return true; | |
3590 | ||
3591 | case MEM: | |
3592 | /* If the address is legitimate, return the number of | |
3593 | instructions it needs. */ | |
3594 | addr = XEXP (x, 0); | |
3595 | cost = mips_address_insns (addr, mode, true); | |
3596 | if (cost > 0) | |
108b61d5 | 3597 | { |
8144a1a8 | 3598 | *total = COSTS_N_INSNS (cost + 1); |
108b61d5 RS |
3599 | return true; |
3600 | } | |
8144a1a8 | 3601 | /* Check for a scaled indexed address. */ |
770da00a AP |
3602 | if (mips_lwxs_address_p (addr) |
3603 | || mips_lx_address_p (addr, mode)) | |
8144a1a8 RS |
3604 | { |
3605 | *total = COSTS_N_INSNS (2); | |
3606 | return true; | |
3607 | } | |
3608 | /* Otherwise use the default handling. */ | |
3609 | return false; | |
cafe096b EC |
3610 | |
3611 | case FFS: | |
3612 | *total = COSTS_N_INSNS (6); | |
8144a1a8 | 3613 | return false; |
cafe096b EC |
3614 | |
3615 | case NOT: | |
8144a1a8 RS |
3616 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); |
3617 | return false; | |
cafe096b EC |
3618 | |
3619 | case AND: | |
8144a1a8 RS |
3620 | /* Check for a *clear_upper32 pattern and treat it like a zero |
3621 | extension. See the pattern's comment for details. */ | |
3622 | if (TARGET_64BIT | |
3623 | && mode == DImode | |
3624 | && CONST_INT_P (XEXP (x, 1)) | |
3625 | && UINTVAL (XEXP (x, 1)) == 0xffffffff) | |
3626 | { | |
3627 | *total = (mips_zero_extend_cost (mode, XEXP (x, 0)) | |
5e8f01f4 | 3628 | + set_src_cost (XEXP (x, 0), speed)); |
8144a1a8 RS |
3629 | return true; |
3630 | } | |
3631 | /* Fall through. */ | |
3632 | ||
cafe096b EC |
3633 | case IOR: |
3634 | case XOR: | |
8144a1a8 | 3635 | /* Double-word operations use two single-word operations. */ |
53d66977 AN |
3636 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2), |
3637 | speed); | |
8144a1a8 | 3638 | return true; |
cafe096b EC |
3639 | |
3640 | case ASHIFT: | |
3641 | case ASHIFTRT: | |
3642 | case LSHIFTRT: | |
8144a1a8 RS |
3643 | case ROTATE: |
3644 | case ROTATERT: | |
3645 | if (CONSTANT_P (XEXP (x, 1))) | |
53d66977 AN |
3646 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3647 | speed); | |
8144a1a8 | 3648 | else |
53d66977 AN |
3649 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12), |
3650 | speed); | |
8144a1a8 | 3651 | return true; |
cafe096b EC |
3652 | |
3653 | case ABS: | |
c1bd2d66 | 3654 | if (float_mode_p) |
8144a1a8 | 3655 | *total = mips_cost->fp_add; |
cafe096b EC |
3656 | else |
3657 | *total = COSTS_N_INSNS (4); | |
8144a1a8 | 3658 | return false; |
cafe096b EC |
3659 | |
3660 | case LO_SUM: | |
8144a1a8 RS |
3661 | /* Low-part immediates need an extended MIPS16 instruction. */ |
3662 | *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1) | |
5e8f01f4 | 3663 | + set_src_cost (XEXP (x, 0), speed)); |
8144a1a8 RS |
3664 | return true; |
3665 | ||
3666 | case LT: | |
3667 | case LTU: | |
3668 | case LE: | |
3669 | case LEU: | |
3670 | case GT: | |
3671 | case GTU: | |
3672 | case GE: | |
3673 | case GEU: | |
3674 | case EQ: | |
3675 | case NE: | |
3676 | case UNORDERED: | |
3677 | case LTGT: | |
3678 | /* Branch comparisons have VOIDmode, so use the first operand's | |
3679 | mode instead. */ | |
3680 | mode = GET_MODE (XEXP (x, 0)); | |
3681 | if (FLOAT_MODE_P (mode)) | |
3682 | { | |
3683 | *total = mips_cost->fp_add; | |
3684 | return false; | |
3685 | } | |
53d66977 AN |
3686 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3687 | speed); | |
cafe096b EC |
3688 | return true; |
3689 | ||
cafe096b | 3690 | case MINUS: |
8144a1a8 | 3691 | if (float_mode_p |
b51469a5 | 3692 | && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) |
8144a1a8 RS |
3693 | && TARGET_FUSED_MADD |
3694 | && !HONOR_NANS (mode) | |
3695 | && !HONOR_SIGNED_ZEROS (mode)) | |
3696 | { | |
3697 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
3698 | associated patterns. */ | |
3699 | rtx op0 = XEXP (x, 0); | |
3700 | rtx op1 = XEXP (x, 1); | |
3701 | if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) | |
3702 | { | |
3703 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
3704 | + set_src_cost (XEXP (XEXP (op0, 0), 0), speed) |
3705 | + set_src_cost (XEXP (op0, 1), speed) | |
3706 | + set_src_cost (op1, speed)); | |
8144a1a8 RS |
3707 | return true; |
3708 | } | |
3709 | if (GET_CODE (op1) == MULT) | |
3710 | { | |
3711 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
3712 | + set_src_cost (op0, speed) |
3713 | + set_src_cost (XEXP (op1, 0), speed) | |
3714 | + set_src_cost (XEXP (op1, 1), speed)); | |
8144a1a8 RS |
3715 | return true; |
3716 | } | |
3717 | } | |
3718 | /* Fall through. */ | |
3719 | ||
3720 | case PLUS: | |
c1bd2d66 EC |
3721 | if (float_mode_p) |
3722 | { | |
65239d20 RS |
3723 | /* If this is part of a MADD or MSUB, treat the PLUS as |
3724 | being free. */ | |
8144a1a8 RS |
3725 | if (ISA_HAS_FP4 |
3726 | && TARGET_FUSED_MADD | |
3727 | && GET_CODE (XEXP (x, 0)) == MULT) | |
3728 | *total = 0; | |
3729 | else | |
3730 | *total = mips_cost->fp_add; | |
3731 | return false; | |
c1bd2d66 EC |
3732 | } |
3733 | ||
8144a1a8 RS |
3734 | /* Double-word operations require three single-word operations and |
3735 | an SLTU. The MIPS16 version then needs to move the result of | |
3736 | the SLTU from $24 to a MIPS16 register. */ | |
3737 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), | |
53d66977 AN |
3738 | COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4), |
3739 | speed); | |
8144a1a8 | 3740 | return true; |
cafe096b EC |
3741 | |
3742 | case NEG: | |
8144a1a8 | 3743 | if (float_mode_p |
b51469a5 | 3744 | && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) |
8144a1a8 RS |
3745 | && TARGET_FUSED_MADD |
3746 | && !HONOR_NANS (mode) | |
3747 | && HONOR_SIGNED_ZEROS (mode)) | |
3748 | { | |
3749 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
3750 | associated patterns. */ | |
3751 | rtx op = XEXP (x, 0); | |
3752 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) | |
3753 | && GET_CODE (XEXP (op, 0)) == MULT) | |
3754 | { | |
3755 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
3756 | + set_src_cost (XEXP (XEXP (op, 0), 0), speed) |
3757 | + set_src_cost (XEXP (XEXP (op, 0), 1), speed) | |
3758 | + set_src_cost (XEXP (op, 1), speed)); | |
8144a1a8 RS |
3759 | return true; |
3760 | } | |
3761 | } | |
3762 | ||
3763 | if (float_mode_p) | |
3764 | *total = mips_cost->fp_add; | |
3765 | else | |
3766 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); | |
cafe096b EC |
3767 | return false; |
3768 | ||
3769 | case MULT: | |
8144a1a8 RS |
3770 | if (float_mode_p) |
3771 | *total = mips_fp_mult_cost (mode); | |
3772 | else if (mode == DImode && !TARGET_64BIT) | |
3773 | /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions, | |
3774 | where the mulsidi3 always includes an MFHI and an MFLO. */ | |
53d66977 AN |
3775 | *total = (speed |
3776 | ? mips_cost->int_mult_si * 3 + 6 | |
3777 | : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)); | |
3778 | else if (!speed) | |
8144a1a8 RS |
3779 | *total = (ISA_HAS_MUL3 ? 1 : 2); |
3780 | else if (mode == DImode) | |
c1bd2d66 | 3781 | *total = mips_cost->int_mult_di; |
8144a1a8 RS |
3782 | else |
3783 | *total = mips_cost->int_mult_si; | |
3784 | return false; | |
cafe096b EC |
3785 | |
3786 | case DIV: | |
8144a1a8 | 3787 | /* Check for a reciprocal. */ |
a1569a0e RS |
3788 | if (float_mode_p |
3789 | && ISA_HAS_FP4 | |
3790 | && flag_unsafe_math_optimizations | |
3791 | && XEXP (x, 0) == CONST1_RTX (mode)) | |
8144a1a8 | 3792 | { |
a1569a0e RS |
3793 | if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) |
3794 | /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the | |
3795 | division as being free. */ | |
5e8f01f4 | 3796 | *total = set_src_cost (XEXP (x, 1), speed); |
a1569a0e | 3797 | else |
bbbbb16a | 3798 | *total = (mips_fp_div_cost (mode) |
5e8f01f4 | 3799 | + set_src_cost (XEXP (x, 1), speed)); |
a1569a0e | 3800 | return true; |
8144a1a8 RS |
3801 | } |
3802 | /* Fall through. */ | |
3803 | ||
3804 | case SQRT: | |
cafe096b | 3805 | case MOD: |
c1bd2d66 EC |
3806 | if (float_mode_p) |
3807 | { | |
8144a1a8 RS |
3808 | *total = mips_fp_div_cost (mode); |
3809 | return false; | |
c1bd2d66 | 3810 | } |
031a26c5 | 3811 | /* Fall through. */ |
cafe096b EC |
3812 | |
3813 | case UDIV: | |
3814 | case UMOD: | |
53d66977 | 3815 | if (!speed) |
8144a1a8 RS |
3816 | { |
3817 | /* It is our responsibility to make division by a power of 2 | |
3818 | as cheap as 2 register additions if we want the division | |
3819 | expanders to be used for such operations; see the setting | |
3820 | of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16 | |
3821 | should always produce shorter code than using | |
3822 | expand_sdiv2_pow2. */ | |
3823 | if (TARGET_MIPS16 | |
3824 | && CONST_INT_P (XEXP (x, 1)) | |
3825 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
3826 | { | |
5e8f01f4 | 3827 | *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed); |
8144a1a8 RS |
3828 | return true; |
3829 | } | |
3830 | *total = COSTS_N_INSNS (mips_idiv_insns ()); | |
3831 | } | |
3832 | else if (mode == DImode) | |
c1bd2d66 | 3833 | *total = mips_cost->int_div_di; |
cafe096b | 3834 | else |
c1bd2d66 | 3835 | *total = mips_cost->int_div_si; |
8144a1a8 | 3836 | return false; |
cafe096b EC |
3837 | |
3838 | case SIGN_EXTEND: | |
8144a1a8 RS |
3839 | *total = mips_sign_extend_cost (mode, XEXP (x, 0)); |
3840 | return false; | |
cafe096b EC |
3841 | |
3842 | case ZERO_EXTEND: | |
a1c48edc RS |
3843 | if (outer_code == SET |
3844 | && ISA_HAS_BADDU | |
3845 | && (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
3846 | || GET_CODE (XEXP (x, 0)) == SUBREG) | |
3847 | && GET_MODE (XEXP (x, 0)) == QImode | |
3848 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) | |
3849 | { | |
3850 | *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); | |
3851 | return true; | |
3852 | } | |
8144a1a8 RS |
3853 | *total = mips_zero_extend_cost (mode, XEXP (x, 0)); |
3854 | return false; | |
cafe096b | 3855 | |
c1bd2d66 EC |
3856 | case FLOAT: |
3857 | case UNSIGNED_FLOAT: | |
3858 | case FIX: | |
3859 | case FLOAT_EXTEND: | |
3860 | case FLOAT_TRUNCATE: | |
c1bd2d66 | 3861 | *total = mips_cost->fp_add; |
8144a1a8 | 3862 | return false; |
c1bd2d66 | 3863 | |
cafe096b EC |
3864 | default: |
3865 | return false; | |
3866 | } | |
3867 | } | |
3868 | ||
65239d20 | 3869 | /* Implement TARGET_ADDRESS_COST. */ |
cafe096b EC |
3870 | |
3871 | static int | |
f40751dd | 3872 | mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED) |
cafe096b | 3873 | { |
5955b0a3 | 3874 | return mips_address_insns (addr, SImode, false); |
cafe096b | 3875 | } |
cee98a59 | 3876 | \f |
6f5a62e9 RS |
3877 | /* Information about a single instruction in a multi-instruction |
3878 | asm sequence. */ | |
3879 | struct mips_multi_member { | |
3880 | /* True if this is a label, false if it is code. */ | |
3881 | bool is_label_p; | |
3882 | ||
3883 | /* The output_asm_insn format of the instruction. */ | |
3884 | const char *format; | |
3885 | ||
3886 | /* The operands to the instruction. */ | |
3887 | rtx operands[MAX_RECOG_OPERANDS]; | |
3888 | }; | |
3889 | typedef struct mips_multi_member mips_multi_member; | |
3890 | ||
3891 | /* Vector definitions for the above. */ | |
3892 | DEF_VEC_O(mips_multi_member); | |
3893 | DEF_VEC_ALLOC_O(mips_multi_member, heap); | |
3894 | ||
3895 | /* The instructions that make up the current multi-insn sequence. */ | |
3896 | static VEC (mips_multi_member, heap) *mips_multi_members; | |
3897 | ||
3898 | /* How many instructions (as opposed to labels) are in the current | |
3899 | multi-insn sequence. */ | |
3900 | static unsigned int mips_multi_num_insns; | |
3901 | ||
3902 | /* Start a new multi-insn sequence. */ | |
3903 | ||
3904 | static void | |
3905 | mips_multi_start (void) | |
3906 | { | |
3907 | VEC_truncate (mips_multi_member, mips_multi_members, 0); | |
3908 | mips_multi_num_insns = 0; | |
3909 | } | |
3910 | ||
3911 | /* Add a new, uninitialized member to the current multi-insn sequence. */ | |
3912 | ||
3913 | static struct mips_multi_member * | |
3914 | mips_multi_add (void) | |
3915 | { | |
3916 | return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0); | |
3917 | } | |
3918 | ||
3919 | /* Add a normal insn with the given asm format to the current multi-insn | |
3920 | sequence. The other arguments are a null-terminated list of operands. */ | |
3921 | ||
3922 | static void | |
3923 | mips_multi_add_insn (const char *format, ...) | |
3924 | { | |
3925 | struct mips_multi_member *member; | |
3926 | va_list ap; | |
3927 | unsigned int i; | |
3928 | rtx op; | |
3929 | ||
3930 | member = mips_multi_add (); | |
3931 | member->is_label_p = false; | |
3932 | member->format = format; | |
3933 | va_start (ap, format); | |
3934 | i = 0; | |
3935 | while ((op = va_arg (ap, rtx))) | |
3936 | member->operands[i++] = op; | |
3937 | va_end (ap); | |
3938 | mips_multi_num_insns++; | |
3939 | } | |
3940 | ||
3941 | /* Add the given label definition to the current multi-insn sequence. | |
3942 | The definition should include the colon. */ | |
3943 | ||
3944 | static void | |
3945 | mips_multi_add_label (const char *label) | |
3946 | { | |
3947 | struct mips_multi_member *member; | |
3948 | ||
3949 | member = mips_multi_add (); | |
3950 | member->is_label_p = true; | |
3951 | member->format = label; | |
3952 | } | |
3953 | ||
3954 | /* Return the index of the last member of the current multi-insn sequence. */ | |
3955 | ||
3956 | static unsigned int | |
3957 | mips_multi_last_index (void) | |
3958 | { | |
3959 | return VEC_length (mips_multi_member, mips_multi_members) - 1; | |
3960 | } | |
3961 | ||
3962 | /* Add a copy of an existing instruction to the current multi-insn | |
3963 | sequence. I is the index of the instruction that should be copied. */ | |
3964 | ||
3965 | static void | |
3966 | mips_multi_copy_insn (unsigned int i) | |
3967 | { | |
3968 | struct mips_multi_member *member; | |
3969 | ||
3970 | member = mips_multi_add (); | |
3971 | memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i), | |
3972 | sizeof (*member)); | |
3973 | gcc_assert (!member->is_label_p); | |
3974 | } | |
3975 | ||
3976 | /* Change the operand of an existing instruction in the current | |
3977 | multi-insn sequence. I is the index of the instruction, | |
3978 | OP is the index of the operand, and X is the new value. */ | |
3979 | ||
3980 | static void | |
3981 | mips_multi_set_operand (unsigned int i, unsigned int op, rtx x) | |
3982 | { | |
3983 | VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x; | |
3984 | } | |
3985 | ||
3986 | /* Write out the asm code for the current multi-insn sequence. */ | |
3987 | ||
3988 | static void | |
3989 | mips_multi_write (void) | |
3990 | { | |
3991 | struct mips_multi_member *member; | |
3992 | unsigned int i; | |
3993 | ||
ac47786e | 3994 | FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member) |
6f5a62e9 RS |
3995 | if (member->is_label_p) |
3996 | fprintf (asm_out_file, "%s\n", member->format); | |
3997 | else | |
3998 | output_asm_insn (member->format, member->operands); | |
3999 | } | |
4000 | \f | |
5b0f0db6 RS |
4001 | /* Return one word of double-word value OP, taking into account the fixed |
4002 | endianness of certain registers. HIGH_P is true to select the high part, | |
4003 | false to select the low part. */ | |
92544bdf | 4004 | |
5b0f0db6 | 4005 | rtx |
65239d20 | 4006 | mips_subword (rtx op, bool high_p) |
5b0f0db6 | 4007 | { |
0064fbe9 | 4008 | unsigned int byte, offset; |
5b0f0db6 | 4009 | enum machine_mode mode; |
cee98a59 | 4010 | |
5b0f0db6 RS |
4011 | mode = GET_MODE (op); |
4012 | if (mode == VOIDmode) | |
21dfc6dc | 4013 | mode = TARGET_64BIT ? TImode : DImode; |
cee98a59 | 4014 | |
5b0f0db6 RS |
4015 | if (TARGET_BIG_ENDIAN ? !high_p : high_p) |
4016 | byte = UNITS_PER_WORD; | |
4017 | else | |
4018 | byte = 0; | |
cee98a59 | 4019 | |
48156a39 | 4020 | if (FP_REG_RTX_P (op)) |
0064fbe9 RS |
4021 | { |
4022 | /* Paired FPRs are always ordered little-endian. */ | |
4023 | offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0); | |
4024 | return gen_rtx_REG (word_mode, REGNO (op) + offset); | |
4025 | } | |
cee98a59 | 4026 | |
66083422 | 4027 | if (MEM_P (op)) |
108b61d5 | 4028 | return mips_rewrite_small_data (adjust_address (op, word_mode, byte)); |
b8eb88d0 | 4029 | |
5b0f0db6 RS |
4030 | return simplify_gen_subreg (word_mode, op, mode, byte); |
4031 | } | |
cee98a59 | 4032 | |
5b0f0db6 | 4033 | /* Return true if a 64-bit move from SRC to DEST should be split into two. */ |
cee98a59 | 4034 | |
5b0f0db6 | 4035 | bool |
b4966b1b | 4036 | mips_split_64bit_move_p (rtx dest, rtx src) |
5b0f0db6 RS |
4037 | { |
4038 | if (TARGET_64BIT) | |
4039 | return false; | |
cee98a59 | 4040 | |
65239d20 RS |
4041 | /* FPR-to-FPR moves can be done in a single instruction, if they're |
4042 | allowed at all. */ | |
5b0f0db6 RS |
4043 | if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) |
4044 | return false; | |
cee98a59 | 4045 | |
f457938f RS |
4046 | /* Check for floating-point loads and stores. */ |
4047 | if (ISA_HAS_LDC1_SDC1) | |
5b0f0db6 | 4048 | { |
66083422 | 4049 | if (FP_REG_RTX_P (dest) && MEM_P (src)) |
5b0f0db6 | 4050 | return false; |
66083422 | 4051 | if (FP_REG_RTX_P (src) && MEM_P (dest)) |
5b0f0db6 RS |
4052 | return false; |
4053 | } | |
4054 | return true; | |
4055 | } | |
b8eb88d0 | 4056 | |
0064fbe9 RS |
4057 | /* Split a doubleword move from SRC to DEST. On 32-bit targets, |
4058 | this function handles 64-bit moves for which mips_split_64bit_move_p | |
4059 | holds. For 64-bit targets, this function handles 128-bit moves. */ | |
cee98a59 | 4060 | |
5b0f0db6 | 4061 | void |
0064fbe9 | 4062 | mips_split_doubleword_move (rtx dest, rtx src) |
5b0f0db6 | 4063 | { |
21dfc6dc RS |
4064 | rtx low_dest; |
4065 | ||
0064fbe9 | 4066 | if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) |
5b0f0db6 | 4067 | { |
0064fbe9 RS |
4068 | if (!TARGET_64BIT && GET_MODE (dest) == DImode) |
4069 | emit_insn (gen_move_doubleword_fprdi (dest, src)); | |
4070 | else if (!TARGET_64BIT && GET_MODE (dest) == DFmode) | |
4071 | emit_insn (gen_move_doubleword_fprdf (dest, src)); | |
e5a2b69d RS |
4072 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode) |
4073 | emit_insn (gen_move_doubleword_fprv2sf (dest, src)); | |
93581857 MS |
4074 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode) |
4075 | emit_insn (gen_move_doubleword_fprv2si (dest, src)); | |
4076 | else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode) | |
4077 | emit_insn (gen_move_doubleword_fprv4hi (dest, src)); | |
4078 | else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode) | |
4079 | emit_insn (gen_move_doubleword_fprv8qi (dest, src)); | |
0064fbe9 RS |
4080 | else if (TARGET_64BIT && GET_MODE (dest) == TFmode) |
4081 | emit_insn (gen_move_doubleword_fprtf (dest, src)); | |
6f428062 | 4082 | else |
0064fbe9 | 4083 | gcc_unreachable (); |
5b0f0db6 | 4084 | } |
21dfc6dc RS |
4085 | else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) |
4086 | { | |
4087 | low_dest = mips_subword (dest, false); | |
4088 | mips_emit_move (low_dest, mips_subword (src, false)); | |
4089 | if (TARGET_64BIT) | |
4090 | emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); | |
4091 | else | |
4092 | emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); | |
4093 | } | |
4094 | else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) | |
4095 | { | |
4096 | mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); | |
4097 | if (TARGET_64BIT) | |
4098 | emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); | |
4099 | else | |
4100 | emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); | |
4101 | } | |
5b0f0db6 RS |
4102 | else |
4103 | { | |
4104 | /* The operation can be split into two normal moves. Decide in | |
4105 | which order to do them. */ | |
65239d20 | 4106 | low_dest = mips_subword (dest, false); |
66083422 | 4107 | if (REG_P (low_dest) |
5b0f0db6 | 4108 | && reg_overlap_mentioned_p (low_dest, src)) |
cee98a59 | 4109 | { |
65239d20 RS |
4110 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); |
4111 | mips_emit_move (low_dest, mips_subword (src, false)); | |
cee98a59 | 4112 | } |
5b0f0db6 | 4113 | else |
cee98a59 | 4114 | { |
65239d20 RS |
4115 | mips_emit_move (low_dest, mips_subword (src, false)); |
4116 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); | |
cee98a59 | 4117 | } |
5b0f0db6 RS |
4118 | } |
4119 | } | |
4120 | \f | |
4121 | /* Return the appropriate instructions to move SRC into DEST. Assume | |
4122 | that SRC is operand 1 and DEST is operand 0. */ | |
cee98a59 | 4123 | |
5b0f0db6 | 4124 | const char * |
b4966b1b | 4125 | mips_output_move (rtx dest, rtx src) |
5b0f0db6 RS |
4126 | { |
4127 | enum rtx_code dest_code, src_code; | |
65239d20 | 4128 | enum machine_mode mode; |
c93c5160 | 4129 | enum mips_symbol_type symbol_type; |
5b0f0db6 | 4130 | bool dbl_p; |
cee98a59 | 4131 | |
5b0f0db6 RS |
4132 | dest_code = GET_CODE (dest); |
4133 | src_code = GET_CODE (src); | |
65239d20 RS |
4134 | mode = GET_MODE (dest); |
4135 | dbl_p = (GET_MODE_SIZE (mode) == 8); | |
cee98a59 | 4136 | |
5b0f0db6 RS |
4137 | if (dbl_p && mips_split_64bit_move_p (dest, src)) |
4138 | return "#"; | |
910628b8 | 4139 | |
5b0f0db6 | 4140 | if ((src_code == REG && GP_REG_P (REGNO (src))) |
65239d20 | 4141 | || (!TARGET_MIPS16 && src == CONST0_RTX (mode))) |
5b0f0db6 RS |
4142 | { |
4143 | if (dest_code == REG) | |
910628b8 | 4144 | { |
5b0f0db6 | 4145 | if (GP_REG_P (REGNO (dest))) |
245115a4 | 4146 | return "move\t%0,%z1"; |
cafe096b | 4147 | |
21dfc6dc RS |
4148 | /* Moves to HI are handled by special .md insns. */ |
4149 | if (REGNO (dest) == LO_REGNUM) | |
4150 | return "mtlo\t%z1"; | |
cafe096b | 4151 | |
118ea793 CF |
4152 | if (DSP_ACC_REG_P (REGNO (dest))) |
4153 | { | |
4154 | static char retval[] = "mt__\t%z1,%q0"; | |
65239d20 | 4155 | |
118ea793 CF |
4156 | retval[2] = reg_names[REGNO (dest)][4]; |
4157 | retval[3] = reg_names[REGNO (dest)][5]; | |
4158 | return retval; | |
4159 | } | |
4160 | ||
5b0f0db6 | 4161 | if (FP_REG_P (REGNO (dest))) |
65239d20 | 4162 | return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0"; |
cafe096b | 4163 | |
5b0f0db6 RS |
4164 | if (ALL_COP_REG_P (REGNO (dest))) |
4165 | { | |
4166 | static char retval[] = "dmtc_\t%z1,%0"; | |
cafe096b | 4167 | |
5b0f0db6 | 4168 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); |
65239d20 | 4169 | return dbl_p ? retval : retval + 1; |
5b0f0db6 RS |
4170 | } |
4171 | } | |
4172 | if (dest_code == MEM) | |
21dfc6dc RS |
4173 | switch (GET_MODE_SIZE (mode)) |
4174 | { | |
4175 | case 1: return "sb\t%z1,%0"; | |
4176 | case 2: return "sh\t%z1,%0"; | |
4177 | case 4: return "sw\t%z1,%0"; | |
4178 | case 8: return "sd\t%z1,%0"; | |
4179 | } | |
cee98a59 | 4180 | } |
5b0f0db6 | 4181 | if (dest_code == REG && GP_REG_P (REGNO (dest))) |
cee98a59 | 4182 | { |
5b0f0db6 | 4183 | if (src_code == REG) |
cee98a59 | 4184 | { |
21dfc6dc RS |
4185 | /* Moves from HI are handled by special .md insns. */ |
4186 | if (REGNO (src) == LO_REGNUM) | |
4187 | { | |
4188 | /* When generating VR4120 or VR4130 code, we use MACC and | |
4189 | DMACC instead of MFLO. This avoids both the normal | |
4190 | MIPS III HI/LO hazards and the errata related to | |
4191 | -mfix-vr4130. */ | |
4192 | if (ISA_HAS_MACCHI) | |
4193 | return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; | |
4194 | return "mflo\t%0"; | |
4195 | } | |
65239d20 | 4196 | |
118ea793 CF |
4197 | if (DSP_ACC_REG_P (REGNO (src))) |
4198 | { | |
4199 | static char retval[] = "mf__\t%0,%q1"; | |
65239d20 | 4200 | |
118ea793 CF |
4201 | retval[2] = reg_names[REGNO (src)][4]; |
4202 | retval[3] = reg_names[REGNO (src)][5]; | |
4203 | return retval; | |
4204 | } | |
4205 | ||
5b0f0db6 | 4206 | if (FP_REG_P (REGNO (src))) |
65239d20 | 4207 | return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1"; |
cee98a59 | 4208 | |
5b0f0db6 | 4209 | if (ALL_COP_REG_P (REGNO (src))) |
d604bca3 | 4210 | { |
5b0f0db6 | 4211 | static char retval[] = "dmfc_\t%0,%1"; |
d604bca3 | 4212 | |
5b0f0db6 | 4213 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); |
65239d20 | 4214 | return dbl_p ? retval : retval + 1; |
d604bca3 | 4215 | } |
65239d20 RS |
4216 | |
4217 | if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC) | |
4218 | return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1"; | |
cee98a59 MM |
4219 | } |
4220 | ||
5b0f0db6 | 4221 | if (src_code == MEM) |
21dfc6dc RS |
4222 | switch (GET_MODE_SIZE (mode)) |
4223 | { | |
4224 | case 1: return "lbu\t%0,%1"; | |
4225 | case 2: return "lhu\t%0,%1"; | |
4226 | case 4: return "lw\t%0,%1"; | |
4227 | case 8: return "ld\t%0,%1"; | |
4228 | } | |
cee98a59 | 4229 | |
5b0f0db6 | 4230 | if (src_code == CONST_INT) |
cee98a59 | 4231 | { |
65239d20 RS |
4232 | /* Don't use the X format for the operand itself, because that |
4233 | will give out-of-range numbers for 64-bit hosts and 32-bit | |
4234 | targets. */ | |
5b0f0db6 RS |
4235 | if (!TARGET_MIPS16) |
4236 | return "li\t%0,%1\t\t\t# %X1"; | |
4237 | ||
65239d20 | 4238 | if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) |
5b0f0db6 RS |
4239 | return "li\t%0,%1"; |
4240 | ||
65239d20 | 4241 | if (SMALL_OPERAND_UNSIGNED (-INTVAL (src))) |
bb732af8 | 4242 | return "#"; |
cee98a59 MM |
4243 | } |
4244 | ||
5b0f0db6 | 4245 | if (src_code == HIGH) |
c93c5160 | 4246 | return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; |
5b0f0db6 | 4247 | |
108b61d5 RS |
4248 | if (CONST_GP_P (src)) |
4249 | return "move\t%0,%1"; | |
7dac2f89 | 4250 | |
c93c5160 RS |
4251 | if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type) |
4252 | && mips_lo_relocs[symbol_type] != 0) | |
4253 | { | |
4254 | /* A signed 16-bit constant formed by applying a relocation | |
4255 | operator to a symbolic address. */ | |
4256 | gcc_assert (!mips_split_p[symbol_type]); | |
4257 | return "li\t%0,%R1"; | |
4258 | } | |
4259 | ||
108b61d5 | 4260 | if (symbolic_operand (src, VOIDmode)) |
c93c5160 RS |
4261 | { |
4262 | gcc_assert (TARGET_MIPS16 | |
4263 | ? TARGET_MIPS16_TEXT_LOADS | |
4264 | : !TARGET_EXPLICIT_RELOCS); | |
65239d20 | 4265 | return dbl_p ? "dla\t%0,%1" : "la\t%0,%1"; |
c93c5160 | 4266 | } |
cee98a59 | 4267 | } |
5b0f0db6 RS |
4268 | if (src_code == REG && FP_REG_P (REGNO (src))) |
4269 | { | |
4270 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
06a4ab70 CF |
4271 | { |
4272 | if (GET_MODE (dest) == V2SFmode) | |
4273 | return "mov.ps\t%0,%1"; | |
4274 | else | |
65239d20 | 4275 | return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1"; |
06a4ab70 | 4276 | } |
cee98a59 | 4277 | |
5b0f0db6 | 4278 | if (dest_code == MEM) |
65239d20 | 4279 | return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0"; |
5b0f0db6 RS |
4280 | } |
4281 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
cee98a59 | 4282 | { |
5b0f0db6 | 4283 | if (src_code == MEM) |
65239d20 | 4284 | return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1"; |
cee98a59 | 4285 | } |
5b0f0db6 RS |
4286 | if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM) |
4287 | { | |
4288 | static char retval[] = "l_c_\t%0,%1"; | |
cee98a59 | 4289 | |
5b0f0db6 RS |
4290 | retval[1] = (dbl_p ? 'd' : 'w'); |
4291 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); | |
4292 | return retval; | |
4293 | } | |
4294 | if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src))) | |
4295 | { | |
4296 | static char retval[] = "s_c_\t%1,%0"; | |
cee98a59 | 4297 | |
5b0f0db6 RS |
4298 | retval[1] = (dbl_p ? 'd' : 'w'); |
4299 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); | |
4300 | return retval; | |
4301 | } | |
7ad769fe | 4302 | gcc_unreachable (); |
cee98a59 | 4303 | } |
b2471838 | 4304 | \f |
65239d20 RS |
4305 | /* Return true if CMP1 is a suitable second operand for integer ordering |
4306 | test CODE. See also the *sCC patterns in mips.md. */ | |
34b650b3 | 4307 | |
a012718f | 4308 | static bool |
65239d20 | 4309 | mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) |
a012718f RS |
4310 | { |
4311 | switch (code) | |
34b650b3 | 4312 | { |
a012718f RS |
4313 | case GT: |
4314 | case GTU: | |
4315 | return reg_or_0_operand (cmp1, VOIDmode); | |
34b650b3 | 4316 | |
a012718f RS |
4317 | case GE: |
4318 | case GEU: | |
4319 | return !TARGET_MIPS16 && cmp1 == const1_rtx; | |
34b650b3 | 4320 | |
a012718f RS |
4321 | case LT: |
4322 | case LTU: | |
4323 | return arith_operand (cmp1, VOIDmode); | |
34b650b3 | 4324 | |
a012718f RS |
4325 | case LE: |
4326 | return sle_operand (cmp1, VOIDmode); | |
34b650b3 | 4327 | |
a012718f RS |
4328 | case LEU: |
4329 | return sleu_operand (cmp1, VOIDmode); | |
34b650b3 | 4330 | |
a012718f | 4331 | default: |
7ad769fe | 4332 | gcc_unreachable (); |
34b650b3 | 4333 | } |
a012718f | 4334 | } |
34b650b3 | 4335 | |
65239d20 RS |
4336 | /* Return true if *CMP1 (of mode MODE) is a valid second operand for |
4337 | integer ordering test *CODE, or if an equivalent combination can | |
4338 | be formed by adjusting *CODE and *CMP1. When returning true, update | |
4339 | *CODE and *CMP1 with the chosen code and operand, otherwise leave | |
4340 | them alone. */ | |
ecd48505 EC |
4341 | |
4342 | static bool | |
65239d20 RS |
4343 | mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, |
4344 | enum machine_mode mode) | |
ecd48505 | 4345 | { |
213ce6f2 | 4346 | HOST_WIDE_INT plus_one; |
ecd48505 | 4347 | |
65239d20 | 4348 | if (mips_int_order_operand_ok_p (*code, *cmp1)) |
213ce6f2 | 4349 | return true; |
d8934cf1 | 4350 | |
47ac44d6 | 4351 | if (CONST_INT_P (*cmp1)) |
213ce6f2 RS |
4352 | switch (*code) |
4353 | { | |
4354 | case LE: | |
4355 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4356 | if (INTVAL (*cmp1) < plus_one) | |
4357 | { | |
4358 | *code = LT; | |
4359 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4360 | return true; | |
4361 | } | |
4362 | break; | |
4363 | ||
4364 | case LEU: | |
4365 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4366 | if (plus_one != 0) | |
4367 | { | |
4368 | *code = LTU; | |
4369 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4370 | return true; | |
4371 | } | |
4372 | break; | |
4373 | ||
4374 | default: | |
4375 | break; | |
4376 | } | |
ecd48505 | 4377 | return false; |
ecd48505 EC |
4378 | } |
4379 | ||
65239d20 | 4380 | /* Compare CMP0 and CMP1 using ordering test CODE and store the result |
5fb79e4c AN |
4381 | in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR |
4382 | is nonnull, it's OK to set TARGET to the inverse of the result and | |
4383 | flip *INVERT_PTR instead. */ | |
f5963e61 | 4384 | |
a012718f | 4385 | static void |
65239d20 | 4386 | mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, |
a012718f RS |
4387 | rtx target, rtx cmp0, rtx cmp1) |
4388 | { | |
65239d20 RS |
4389 | enum machine_mode mode; |
4390 | ||
213ce6f2 RS |
4391 | /* First see if there is a MIPS instruction that can do this operation. |
4392 | If not, try doing the same for the inverse operation. If that also | |
4393 | fails, force CMP1 into a register and try again. */ | |
5fb79e4c | 4394 | mode = GET_MODE (cmp0); |
65239d20 | 4395 | if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) |
ecd48505 | 4396 | mips_emit_binary (code, target, cmp0, cmp1); |
bbdb5552 MM |
4397 | else |
4398 | { | |
a012718f | 4399 | enum rtx_code inv_code = reverse_condition (code); |
65239d20 | 4400 | if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode)) |
a012718f | 4401 | { |
65239d20 RS |
4402 | cmp1 = force_reg (mode, cmp1); |
4403 | mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); | |
a012718f RS |
4404 | } |
4405 | else if (invert_ptr == 0) | |
2bcb2ab3 | 4406 | { |
49bce30a RS |
4407 | rtx inv_target; |
4408 | ||
4409 | inv_target = mips_force_binary (GET_MODE (target), | |
4410 | inv_code, cmp0, cmp1); | |
a012718f | 4411 | mips_emit_binary (XOR, target, inv_target, const1_rtx); |
2bcb2ab3 GK |
4412 | } |
4413 | else | |
4414 | { | |
a012718f RS |
4415 | *invert_ptr = !*invert_ptr; |
4416 | mips_emit_binary (inv_code, target, cmp0, cmp1); | |
2bcb2ab3 | 4417 | } |
34b650b3 | 4418 | } |
a012718f | 4419 | } |
34b650b3 | 4420 | |
a012718f RS |
4421 | /* Return a register that is zero iff CMP0 and CMP1 are equal. |
4422 | The register will have the same mode as CMP0. */ | |
34b650b3 | 4423 | |
a012718f RS |
4424 | static rtx |
4425 | mips_zero_if_equal (rtx cmp0, rtx cmp1) | |
4426 | { | |
4427 | if (cmp1 == const0_rtx) | |
4428 | return cmp0; | |
2bcb2ab3 | 4429 | |
f1286257 RS |
4430 | if (uns_arith_operand (cmp1, VOIDmode)) |
4431 | return expand_binop (GET_MODE (cmp0), xor_optab, | |
4432 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); | |
4433 | ||
4434 | return expand_binop (GET_MODE (cmp0), sub_optab, | |
a012718f RS |
4435 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); |
4436 | } | |
4437 | ||
ec4fc7ed | 4438 | /* Convert *CODE into a code that can be used in a floating-point |
65239d20 | 4439 | scc instruction (C.cond.fmt). Return true if the values of |
ec4fc7ed RS |
4440 | the condition code registers will be inverted, with 0 indicating |
4441 | that the condition holds. */ | |
4442 | ||
4443 | static bool | |
65239d20 | 4444 | mips_reversed_fp_cond (enum rtx_code *code) |
ec4fc7ed RS |
4445 | { |
4446 | switch (*code) | |
4447 | { | |
4448 | case NE: | |
4449 | case LTGT: | |
4450 | case ORDERED: | |
4451 | *code = reverse_condition_maybe_unordered (*code); | |
4452 | return true; | |
4453 | ||
4454 | default: | |
4455 | return false; | |
4456 | } | |
4457 | } | |
4458 | ||
bb592806 | 4459 | /* Convert a comparison into something that can be used in a branch or |
f90b7a5a PB |
4460 | conditional move. On entry, *OP0 and *OP1 are the values being |
4461 | compared and *CODE is the code used to compare them. | |
bb592806 RS |
4462 | |
4463 | Update *CODE, *OP0 and *OP1 so that they describe the final comparison. | |
65239d20 | 4464 | If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible, |
bb592806 RS |
4465 | otherwise any standard branch condition can be used. The standard branch |
4466 | conditions are: | |
4467 | ||
65239d20 | 4468 | - EQ or NE between two registers. |
bb592806 RS |
4469 | - any comparison between a register and zero. */ |
4470 | ||
4471 | static void | |
4472 | mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) | |
4473 | { | |
f90b7a5a PB |
4474 | rtx cmp_op0 = *op0; |
4475 | rtx cmp_op1 = *op1; | |
4476 | ||
4477 | if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) | |
bb592806 | 4478 | { |
f90b7a5a PB |
4479 | if (!need_eq_ne_p && *op1 == const0_rtx) |
4480 | ; | |
bb592806 RS |
4481 | else if (*code == EQ || *code == NE) |
4482 | { | |
4483 | if (need_eq_ne_p) | |
4484 | { | |
f90b7a5a | 4485 | *op0 = mips_zero_if_equal (cmp_op0, cmp_op1); |
bb592806 RS |
4486 | *op1 = const0_rtx; |
4487 | } | |
4488 | else | |
f90b7a5a | 4489 | *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); |
bb592806 RS |
4490 | } |
4491 | else | |
4492 | { | |
4493 | /* The comparison needs a separate scc instruction. Store the | |
4494 | result of the scc in *OP0 and compare it against zero. */ | |
4495 | bool invert = false; | |
f90b7a5a PB |
4496 | *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); |
4497 | mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1); | |
bb592806 | 4498 | *code = (invert ? EQ : NE); |
65239d20 | 4499 | *op1 = const0_rtx; |
bb592806 RS |
4500 | } |
4501 | } | |
f90b7a5a | 4502 | else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0))) |
9fc777ad CF |
4503 | { |
4504 | *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM); | |
f90b7a5a | 4505 | mips_emit_binary (*code, *op0, cmp_op0, cmp_op1); |
9fc777ad CF |
4506 | *code = NE; |
4507 | *op1 = const0_rtx; | |
4508 | } | |
bb592806 RS |
4509 | else |
4510 | { | |
4511 | enum rtx_code cmp_code; | |
4512 | ||
65239d20 | 4513 | /* Floating-point tests use a separate C.cond.fmt comparison to |
bb592806 RS |
4514 | set a condition code register. The branch or conditional move |
4515 | will then compare that register against zero. | |
4516 | ||
4517 | Set CMP_CODE to the code of the comparison instruction and | |
4518 | *CODE to the code that the branch or move should use. */ | |
ec4fc7ed | 4519 | cmp_code = *code; |
65239d20 | 4520 | *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; |
bb592806 RS |
4521 | *op0 = (ISA_HAS_8CC |
4522 | ? gen_reg_rtx (CCmode) | |
4523 | : gen_rtx_REG (CCmode, FPSW_REGNUM)); | |
4524 | *op1 = const0_rtx; | |
f90b7a5a | 4525 | mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); |
bb592806 RS |
4526 | } |
4527 | } | |
4528 | \f | |
f90b7a5a PB |
4529 | /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] |
4530 | and OPERAND[3]. Store the result in OPERANDS[0]. | |
a012718f | 4531 | |
f90b7a5a PB |
4532 | On 64-bit targets, the mode of the comparison and target will always be |
4533 | SImode, thus possibly narrower than that of the comparison's operands. */ | |
34b650b3 | 4534 | |
f90b7a5a PB |
4535 | void |
4536 | mips_expand_scc (rtx operands[]) | |
a012718f | 4537 | { |
f90b7a5a PB |
4538 | rtx target = operands[0]; |
4539 | enum rtx_code code = GET_CODE (operands[1]); | |
4540 | rtx op0 = operands[2]; | |
4541 | rtx op1 = operands[3]; | |
4542 | ||
4543 | gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); | |
a012718f | 4544 | |
a012718f RS |
4545 | if (code == EQ || code == NE) |
4546 | { | |
5299815b | 4547 | if (ISA_HAS_SEQ_SNE |
f90b7a5a PB |
4548 | && reg_imm10_operand (op1, GET_MODE (op1))) |
4549 | mips_emit_binary (code, target, op0, op1); | |
5299815b AN |
4550 | else |
4551 | { | |
f90b7a5a | 4552 | rtx zie = mips_zero_if_equal (op0, op1); |
5299815b AN |
4553 | mips_emit_binary (code, target, zie, const0_rtx); |
4554 | } | |
a012718f RS |
4555 | } |
4556 | else | |
f90b7a5a | 4557 | mips_emit_int_order_test (code, 0, target, op0, op1); |
34b650b3 | 4558 | } |
8ab907e8 | 4559 | |
f90b7a5a PB |
4560 | /* Compare OPERANDS[1] with OPERANDS[2] using comparison code |
4561 | CODE and jump to OPERANDS[3] if the condition holds. */ | |
cee98a59 MM |
4562 | |
4563 | void | |
f90b7a5a | 4564 | mips_expand_conditional_branch (rtx *operands) |
cee98a59 | 4565 | { |
f90b7a5a PB |
4566 | enum rtx_code code = GET_CODE (operands[0]); |
4567 | rtx op0 = operands[1]; | |
4568 | rtx op1 = operands[2]; | |
4569 | rtx condition; | |
f5963e61 | 4570 | |
bb592806 | 4571 | mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16); |
a8c1d5f8 | 4572 | condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
f90b7a5a | 4573 | emit_jump_insn (gen_condjump (condition, operands[3])); |
b8eb88d0 | 4574 | } |
34b650b3 | 4575 | |
ec4fc7ed RS |
4576 | /* Implement: |
4577 | ||
4578 | (set temp (COND:CCV2 CMP_OP0 CMP_OP1)) | |
4579 | (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */ | |
4580 | ||
4581 | void | |
4582 | mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src, | |
4583 | enum rtx_code cond, rtx cmp_op0, rtx cmp_op1) | |
4584 | { | |
4585 | rtx cmp_result; | |
4586 | bool reversed_p; | |
4587 | ||
65239d20 | 4588 | reversed_p = mips_reversed_fp_cond (&cond); |
ec4fc7ed RS |
4589 | cmp_result = gen_reg_rtx (CCV2mode); |
4590 | emit_insn (gen_scc_ps (cmp_result, | |
4591 | gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1))); | |
4592 | if (reversed_p) | |
4593 | emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src, | |
4594 | cmp_result)); | |
4595 | else | |
4596 | emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src, | |
4597 | cmp_result)); | |
4598 | } | |
4599 | ||
f90b7a5a PB |
4600 | /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] |
4601 | if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */ | |
cee98a59 | 4602 | |
b8eb88d0 | 4603 | void |
65239d20 | 4604 | mips_expand_conditional_move (rtx *operands) |
b8eb88d0 | 4605 | { |
f90b7a5a PB |
4606 | rtx cond; |
4607 | enum rtx_code code = GET_CODE (operands[1]); | |
4608 | rtx op0 = XEXP (operands[1], 0); | |
4609 | rtx op1 = XEXP (operands[1], 1); | |
c5c76735 | 4610 | |
bb592806 | 4611 | mips_emit_compare (&code, &op0, &op1, true); |
f90b7a5a | 4612 | cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); |
bb592806 | 4613 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
65239d20 | 4614 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond, |
c5c76735 | 4615 | operands[2], operands[3]))); |
b8eb88d0 | 4616 | } |
a0b6cdee | 4617 | |
f90b7a5a | 4618 | /* Perform the comparison in COMPARISON, then trap if the condition holds. */ |
a0b6cdee GM |
4619 | |
4620 | void | |
f90b7a5a | 4621 | mips_expand_conditional_trap (rtx comparison) |
a0b6cdee GM |
4622 | { |
4623 | rtx op0, op1; | |
65239d20 | 4624 | enum machine_mode mode; |
f90b7a5a | 4625 | enum rtx_code code; |
a0b6cdee | 4626 | |
65239d20 RS |
4627 | /* MIPS conditional trap instructions don't have GT or LE flavors, |
4628 | so we must swap the operands and convert to LT and GE respectively. */ | |
f90b7a5a | 4629 | code = GET_CODE (comparison); |
65239d20 | 4630 | switch (code) |
a0b6cdee | 4631 | { |
65239d20 RS |
4632 | case GT: |
4633 | case LE: | |
4634 | case GTU: | |
4635 | case LEU: | |
4636 | code = swap_condition (code); | |
f90b7a5a PB |
4637 | op0 = XEXP (comparison, 1); |
4638 | op1 = XEXP (comparison, 0); | |
65239d20 RS |
4639 | break; |
4640 | ||
4641 | default: | |
f90b7a5a PB |
4642 | op0 = XEXP (comparison, 0); |
4643 | op1 = XEXP (comparison, 1); | |
65239d20 | 4644 | break; |
a0b6cdee | 4645 | } |
65239d20 | 4646 | |
f90b7a5a | 4647 | mode = GET_MODE (XEXP (comparison, 0)); |
886ce862 RS |
4648 | op0 = force_reg (mode, op0); |
4649 | if (!arith_operand (op1, mode)) | |
a0b6cdee GM |
4650 | op1 = force_reg (mode, op1); |
4651 | ||
4652 | emit_insn (gen_rtx_TRAP_IF (VOIDmode, | |
65239d20 RS |
4653 | gen_rtx_fmt_ee (code, mode, op0, op1), |
4654 | const0_rtx)); | |
a0b6cdee | 4655 | } |
cee98a59 | 4656 | \f |
65239d20 | 4657 | /* Initialize *CUM for a call to a function of type FNTYPE. */ |
ab77a036 RS |
4658 | |
4659 | void | |
65239d20 | 4660 | mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype) |
9a6dfb47 | 4661 | { |
65239d20 RS |
4662 | memset (cum, 0, sizeof (*cum)); |
4663 | cum->prototype = (fntype && prototype_p (fntype)); | |
4664 | cum->gp_reg_found = (cum->prototype && stdarg_p (fntype)); | |
9a6dfb47 RS |
4665 | } |
4666 | ||
ab77a036 RS |
4667 | /* Fill INFO with information about a single argument. CUM is the |
4668 | cumulative state for earlier arguments. MODE is the mode of this | |
4669 | argument and TYPE is its type (if known). NAMED is true if this | |
4670 | is a named (fixed) argument rather than a variable one. */ | |
4671 | ||
4672 | static void | |
65239d20 | 4673 | mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum, |
c8717ea3 | 4674 | enum machine_mode mode, const_tree type, bool named) |
08e7ceb3 | 4675 | { |
ab77a036 RS |
4676 | bool doubleword_aligned_p; |
4677 | unsigned int num_bytes, num_words, max_regs; | |
08e7ceb3 | 4678 | |
ab77a036 RS |
4679 | /* Work out the size of the argument. */ |
4680 | num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
4681 | num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
b85aed9e | 4682 | |
ab77a036 RS |
4683 | /* Decide whether it should go in a floating-point register, assuming |
4684 | one is free. Later code checks for availability. | |
b85aed9e | 4685 | |
ab77a036 RS |
4686 | The checks against UNITS_PER_FPVALUE handle the soft-float and |
4687 | single-float cases. */ | |
4688 | switch (mips_abi) | |
e8b7a137 | 4689 | { |
ab77a036 RS |
4690 | case ABI_EABI: |
4691 | /* The EABI conventions have traditionally been defined in terms | |
4692 | of TYPE_MODE, regardless of the actual type. */ | |
4693 | info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
7dab511c | 4694 | || mode == V2SFmode) |
ab77a036 RS |
4695 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); |
4696 | break; | |
b85aed9e | 4697 | |
ab77a036 RS |
4698 | case ABI_32: |
4699 | case ABI_O64: | |
4700 | /* Only leading floating-point scalars are passed in | |
4701 | floating-point registers. We also handle vector floats the same | |
4702 | say, which is OK because they are not covered by the standard ABI. */ | |
4703 | info->fpr_p = (!cum->gp_reg_found | |
4704 | && cum->arg_number < 2 | |
65239d20 RS |
4705 | && (type == 0 |
4706 | || SCALAR_FLOAT_TYPE_P (type) | |
ab77a036 RS |
4707 | || VECTOR_FLOAT_TYPE_P (type)) |
4708 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7dab511c | 4709 | || mode == V2SFmode) |
ab77a036 RS |
4710 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); |
4711 | break; | |
cafe096b | 4712 | |
ab77a036 RS |
4713 | case ABI_N32: |
4714 | case ABI_64: | |
65239d20 RS |
4715 | /* Scalar, complex and vector floating-point types are passed in |
4716 | floating-point registers, as long as this is a named rather | |
4717 | than a variable argument. */ | |
ab77a036 RS |
4718 | info->fpr_p = (named |
4719 | && (type == 0 || FLOAT_TYPE_P (type)) | |
4720 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4721 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
7dab511c | 4722 | || mode == V2SFmode) |
ab77a036 | 4723 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); |
3c53850d | 4724 | |
ab77a036 RS |
4725 | /* ??? According to the ABI documentation, the real and imaginary |
4726 | parts of complex floats should be passed in individual registers. | |
4727 | The real and imaginary parts of stack arguments are supposed | |
4728 | to be contiguous and there should be an extra word of padding | |
4729 | at the end. | |
cafe096b | 4730 | |
ab77a036 RS |
4731 | This has two problems. First, it makes it impossible to use a |
4732 | single "void *" va_list type, since register and stack arguments | |
4733 | are passed differently. (At the time of writing, MIPSpro cannot | |
4734 | handle complex float varargs correctly.) Second, it's unclear | |
4735 | what should happen when there is only one register free. | |
3c53850d | 4736 | |
ab77a036 RS |
4737 | For now, we assume that named complex floats should go into FPRs |
4738 | if there are two FPRs free, otherwise they should be passed in the | |
4739 | same way as a struct containing two floats. */ | |
4740 | if (info->fpr_p | |
4741 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4742 | && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) | |
4743 | { | |
4744 | if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) | |
4745 | info->fpr_p = false; | |
4746 | else | |
4747 | num_words = 2; | |
4748 | } | |
4749 | break; | |
cafe096b | 4750 | |
ab77a036 RS |
4751 | default: |
4752 | gcc_unreachable (); | |
cafe096b | 4753 | } |
3c53850d | 4754 | |
ab77a036 | 4755 | /* See whether the argument has doubleword alignment. */ |
c2ed6cf8 NF |
4756 | doubleword_aligned_p = (mips_function_arg_boundary (mode, type) |
4757 | > BITS_PER_WORD); | |
3c53850d | 4758 | |
ab77a036 RS |
4759 | /* Set REG_OFFSET to the register count we're interested in. |
4760 | The EABI allocates the floating-point registers separately, | |
4761 | but the other ABIs allocate them like integer registers. */ | |
4762 | info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p | |
4763 | ? cum->num_fprs | |
4764 | : cum->num_gprs); | |
cafe096b | 4765 | |
ab77a036 RS |
4766 | /* Advance to an even register if the argument is doubleword-aligned. */ |
4767 | if (doubleword_aligned_p) | |
4768 | info->reg_offset += info->reg_offset & 1; | |
cafe096b | 4769 | |
ab77a036 RS |
4770 | /* Work out the offset of a stack argument. */ |
4771 | info->stack_offset = cum->stack_words; | |
4772 | if (doubleword_aligned_p) | |
4773 | info->stack_offset += info->stack_offset & 1; | |
cafe096b | 4774 | |
ab77a036 | 4775 | max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; |
f9e4a411 | 4776 | |
ab77a036 RS |
4777 | /* Partition the argument between registers and stack. */ |
4778 | info->reg_words = MIN (num_words, max_regs); | |
4779 | info->stack_words = num_words - info->reg_words; | |
4780 | } | |
f9e4a411 | 4781 | |
65239d20 RS |
4782 | /* INFO describes a register argument that has the normal format for the |
4783 | argument's mode. Return the register it uses, assuming that FPRs are | |
4784 | available if HARD_FLOAT_P. */ | |
1ec3b87b | 4785 | |
ab77a036 RS |
4786 | static unsigned int |
4787 | mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p) | |
4788 | { | |
4789 | if (!info->fpr_p || !hard_float_p) | |
4790 | return GP_ARG_FIRST + info->reg_offset; | |
4791 | else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0) | |
4792 | /* In o32, the second argument is always passed in $f14 | |
4793 | for TARGET_DOUBLE_FLOAT, regardless of whether the | |
4794 | first argument was a word or doubleword. */ | |
4795 | return FP_ARG_FIRST + 2; | |
4796 | else | |
4797 | return FP_ARG_FIRST + info->reg_offset; | |
cafe096b | 4798 | } |
d12b8c85 | 4799 | |
65239d20 RS |
4800 | /* Implement TARGET_STRICT_ARGUMENT_NAMING. */ |
4801 | ||
ab77a036 | 4802 | static bool |
d5cc9181 | 4803 | mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) |
ab77a036 RS |
4804 | { |
4805 | return !TARGET_OLDABI; | |
4806 | } | |
d12b8c85 | 4807 | |
c8717ea3 | 4808 | /* Implement TARGET_FUNCTION_ARG. */ |
d12b8c85 | 4809 | |
c8717ea3 | 4810 | static rtx |
d5cc9181 | 4811 | mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
c8717ea3 | 4812 | const_tree type, bool named) |
d12b8c85 | 4813 | { |
d5cc9181 | 4814 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
ab77a036 | 4815 | struct mips_arg_info info; |
d12b8c85 | 4816 | |
ab77a036 | 4817 | /* We will be called with a mode of VOIDmode after the last argument |
65239d20 RS |
4818 | has been seen. Whatever we return will be passed to the call expander. |
4819 | If we need a MIPS16 fp_code, return a REG with the code stored as | |
4820 | the mode. */ | |
ab77a036 RS |
4821 | if (mode == VOIDmode) |
4822 | { | |
4823 | if (TARGET_MIPS16 && cum->fp_code != 0) | |
4824 | return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0); | |
ab77a036 | 4825 | else |
65239d20 | 4826 | return NULL; |
ab77a036 | 4827 | } |
d12b8c85 | 4828 | |
65239d20 | 4829 | mips_get_arg_info (&info, cum, mode, type, named); |
b2471838 | 4830 | |
ab77a036 RS |
4831 | /* Return straight away if the whole argument is passed on the stack. */ |
4832 | if (info.reg_offset == MAX_ARGS_IN_REGISTERS) | |
65239d20 | 4833 | return NULL; |
b2471838 | 4834 | |
65239d20 RS |
4835 | /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure |
4836 | contains a double in its entirety, then that 64-bit chunk is passed | |
4837 | in a floating-point register. */ | |
4838 | if (TARGET_NEWABI | |
4839 | && TARGET_HARD_FLOAT | |
4840 | && named | |
4841 | && type != 0 | |
ab77a036 | 4842 | && TREE_CODE (type) == RECORD_TYPE |
ab77a036 | 4843 | && TYPE_SIZE_UNIT (type) |
65239d20 | 4844 | && host_integerp (TYPE_SIZE_UNIT (type), 1)) |
ab77a036 | 4845 | { |
ab77a036 | 4846 | tree field; |
b2471838 | 4847 | |
ab77a036 | 4848 | /* First check to see if there is any such field. */ |
910ad8de | 4849 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
ab77a036 | 4850 | if (TREE_CODE (field) == FIELD_DECL |
65239d20 | 4851 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
4852 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD |
4853 | && host_integerp (bit_position (field), 0) | |
4854 | && int_bit_position (field) % BITS_PER_WORD == 0) | |
4855 | break; | |
cee98a59 | 4856 | |
ab77a036 RS |
4857 | if (field != 0) |
4858 | { | |
4859 | /* Now handle the special case by returning a PARALLEL | |
4860 | indicating where each 64-bit chunk goes. INFO.REG_WORDS | |
4861 | chunks are passed in registers. */ | |
4862 | unsigned int i; | |
4863 | HOST_WIDE_INT bitpos; | |
4864 | rtx ret; | |
730cf822 | 4865 | |
ab77a036 RS |
4866 | /* assign_parms checks the mode of ENTRY_PARM, so we must |
4867 | use the actual mode here. */ | |
4868 | ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); | |
cee98a59 | 4869 | |
ab77a036 RS |
4870 | bitpos = 0; |
4871 | field = TYPE_FIELDS (type); | |
4872 | for (i = 0; i < info.reg_words; i++) | |
4873 | { | |
4874 | rtx reg; | |
cee98a59 | 4875 | |
910ad8de | 4876 | for (; field; field = DECL_CHAIN (field)) |
ab77a036 RS |
4877 | if (TREE_CODE (field) == FIELD_DECL |
4878 | && int_bit_position (field) >= bitpos) | |
4879 | break; | |
cee98a59 | 4880 | |
ab77a036 RS |
4881 | if (field |
4882 | && int_bit_position (field) == bitpos | |
65239d20 | 4883 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
4884 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) |
4885 | reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); | |
4886 | else | |
4887 | reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); | |
4888 | ||
4889 | XVECEXP (ret, 0, i) | |
4890 | = gen_rtx_EXPR_LIST (VOIDmode, reg, | |
4891 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4892 | ||
4893 | bitpos += BITS_PER_WORD; | |
4894 | } | |
4895 | return ret; | |
4896 | } | |
4897 | } | |
4898 | ||
4899 | /* Handle the n32/n64 conventions for passing complex floating-point | |
4900 | arguments in FPR pairs. The real part goes in the lower register | |
4901 | and the imaginary part goes in the upper register. */ | |
4902 | if (TARGET_NEWABI | |
4903 | && info.fpr_p | |
4904 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
cee98a59 | 4905 | { |
ab77a036 RS |
4906 | rtx real, imag; |
4907 | enum machine_mode inner; | |
65239d20 | 4908 | unsigned int regno; |
ab77a036 RS |
4909 | |
4910 | inner = GET_MODE_INNER (mode); | |
65239d20 | 4911 | regno = FP_ARG_FIRST + info.reg_offset; |
ab77a036 RS |
4912 | if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) |
4913 | { | |
4914 | /* Real part in registers, imaginary part on stack. */ | |
4915 | gcc_assert (info.stack_words == info.reg_words); | |
65239d20 | 4916 | return gen_rtx_REG (inner, regno); |
ab77a036 | 4917 | } |
e0ec4c3b RS |
4918 | else |
4919 | { | |
ab77a036 RS |
4920 | gcc_assert (info.stack_words == 0); |
4921 | real = gen_rtx_EXPR_LIST (VOIDmode, | |
65239d20 | 4922 | gen_rtx_REG (inner, regno), |
ab77a036 RS |
4923 | const0_rtx); |
4924 | imag = gen_rtx_EXPR_LIST (VOIDmode, | |
4925 | gen_rtx_REG (inner, | |
65239d20 | 4926 | regno + info.reg_words / 2), |
ab77a036 RS |
4927 | GEN_INT (GET_MODE_SIZE (inner))); |
4928 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); | |
e0ec4c3b | 4929 | } |
730cf822 | 4930 | } |
f5963e61 | 4931 | |
ab77a036 | 4932 | return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); |
cee98a59 | 4933 | } |
cee98a59 | 4934 | |
c8717ea3 | 4935 | /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ |
cee98a59 | 4936 | |
c8717ea3 | 4937 | static void |
d5cc9181 | 4938 | mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
c8717ea3 | 4939 | const_tree type, bool named) |
842eb20e | 4940 | { |
d5cc9181 | 4941 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
ab77a036 | 4942 | struct mips_arg_info info; |
842eb20e | 4943 | |
65239d20 | 4944 | mips_get_arg_info (&info, cum, mode, type, named); |
842eb20e | 4945 | |
ab77a036 RS |
4946 | if (!info.fpr_p) |
4947 | cum->gp_reg_found = true; | |
910628b8 | 4948 | |
65239d20 RS |
4949 | /* See the comment above the CUMULATIVE_ARGS structure in mips.h for |
4950 | an explanation of what this code does. It assumes that we're using | |
4951 | either the o32 or the o64 ABI, both of which pass at most 2 arguments | |
4952 | in FPRs. */ | |
ab77a036 RS |
4953 | if (cum->arg_number < 2 && info.fpr_p) |
4954 | cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2); | |
910628b8 | 4955 | |
65239d20 RS |
4956 | /* Advance the register count. This has the effect of setting |
4957 | num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned | |
4958 | argument required us to skip the final GPR and pass the whole | |
4959 | argument on the stack. */ | |
ab77a036 RS |
4960 | if (mips_abi != ABI_EABI || !info.fpr_p) |
4961 | cum->num_gprs = info.reg_offset + info.reg_words; | |
4962 | else if (info.reg_words > 0) | |
4963 | cum->num_fprs += MAX_FPRS_PER_FMT; | |
910628b8 | 4964 | |
65239d20 | 4965 | /* Advance the stack word count. */ |
ab77a036 RS |
4966 | if (info.stack_words > 0) |
4967 | cum->stack_words = info.stack_offset + info.stack_words; | |
842eb20e | 4968 | |
ab77a036 RS |
4969 | cum->arg_number++; |
4970 | } | |
842eb20e | 4971 | |
ab77a036 | 4972 | /* Implement TARGET_ARG_PARTIAL_BYTES. */ |
842eb20e | 4973 | |
ab77a036 | 4974 | static int |
d5cc9181 | 4975 | mips_arg_partial_bytes (cumulative_args_t cum, |
ab77a036 RS |
4976 | enum machine_mode mode, tree type, bool named) |
4977 | { | |
4978 | struct mips_arg_info info; | |
f5963e61 | 4979 | |
d5cc9181 | 4980 | mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named); |
ab77a036 RS |
4981 | return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; |
4982 | } | |
147255d8 | 4983 | |
c2ed6cf8 NF |
4984 | /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at |
4985 | least PARM_BOUNDARY bits of alignment, but will be given anything up | |
ab77a036 | 4986 | to STACK_BOUNDARY bits if the type requires it. */ |
f5963e61 | 4987 | |
c2ed6cf8 | 4988 | static unsigned int |
c8717ea3 | 4989 | mips_function_arg_boundary (enum machine_mode mode, const_tree type) |
ab77a036 RS |
4990 | { |
4991 | unsigned int alignment; | |
4992 | ||
4993 | alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
4994 | if (alignment < PARM_BOUNDARY) | |
4995 | alignment = PARM_BOUNDARY; | |
4996 | if (alignment > STACK_BOUNDARY) | |
4997 | alignment = STACK_BOUNDARY; | |
4998 | return alignment; | |
730cf822 | 4999 | } |
df770e04 | 5000 | |
ab77a036 RS |
5001 | /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return |
5002 | upward rather than downward. In other words, return true if the | |
5003 | first byte of the stack slot has useful data, false if the last | |
5004 | byte does. */ | |
df770e04 | 5005 | |
ab77a036 RS |
5006 | bool |
5007 | mips_pad_arg_upward (enum machine_mode mode, const_tree type) | |
df770e04 | 5008 | { |
ab77a036 RS |
5009 | /* On little-endian targets, the first byte of every stack argument |
5010 | is passed in the first byte of the stack slot. */ | |
5011 | if (!BYTES_BIG_ENDIAN) | |
5012 | return true; | |
df770e04 | 5013 | |
ab77a036 RS |
5014 | /* Otherwise, integral types are padded downward: the last byte of a |
5015 | stack argument is passed in the last byte of the stack slot. */ | |
5016 | if (type != 0 | |
5017 | ? (INTEGRAL_TYPE_P (type) | |
5018 | || POINTER_TYPE_P (type) | |
5019 | || FIXED_POINT_TYPE_P (type)) | |
65239d20 | 5020 | : (SCALAR_INT_MODE_P (mode) |
ab77a036 RS |
5021 | || ALL_SCALAR_FIXED_POINT_MODE_P (mode))) |
5022 | return false; | |
df770e04 | 5023 | |
ab77a036 RS |
5024 | /* Big-endian o64 pads floating-point arguments downward. */ |
5025 | if (mips_abi == ABI_O64) | |
5026 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5027 | return false; | |
df770e04 | 5028 | |
ab77a036 RS |
5029 | /* Other types are padded upward for o32, o64, n32 and n64. */ |
5030 | if (mips_abi != ABI_EABI) | |
5031 | return true; | |
df770e04 | 5032 | |
ab77a036 RS |
5033 | /* Arguments smaller than a stack slot are padded downward. */ |
5034 | if (mode != BLKmode) | |
65239d20 | 5035 | return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY; |
ab77a036 | 5036 | else |
65239d20 | 5037 | return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT); |
ab77a036 | 5038 | } |
df770e04 | 5039 | |
ab77a036 RS |
5040 | /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN |
5041 | if the least significant byte of the register has useful data. Return | |
5042 | the opposite if the most significant byte does. */ | |
0cebb05d | 5043 | |
730cf822 | 5044 | bool |
ab77a036 | 5045 | mips_pad_reg_upward (enum machine_mode mode, tree type) |
730cf822 | 5046 | { |
ab77a036 RS |
5047 | /* No shifting is required for floating-point arguments. */ |
5048 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5049 | return !BYTES_BIG_ENDIAN; | |
5050 | ||
5051 | /* Otherwise, apply the same padding to register arguments as we do | |
5052 | to stack arguments. */ | |
5053 | return mips_pad_arg_upward (mode, type); | |
842eb20e | 5054 | } |
cee98a59 | 5055 | |
ab77a036 | 5056 | /* Return nonzero when an argument must be passed by reference. */ |
cee98a59 | 5057 | |
ab77a036 | 5058 | static bool |
d5cc9181 | 5059 | mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ab77a036 RS |
5060 | enum machine_mode mode, const_tree type, |
5061 | bool named ATTRIBUTE_UNUSED) | |
5062 | { | |
5063 | if (mips_abi == ABI_EABI) | |
5064 | { | |
5065 | int size; | |
cee98a59 | 5066 | |
ab77a036 RS |
5067 | /* ??? How should SCmode be handled? */ |
5068 | if (mode == DImode || mode == DFmode | |
5069 | || mode == DQmode || mode == UDQmode | |
5070 | || mode == DAmode || mode == UDAmode) | |
5071 | return 0; | |
cee98a59 | 5072 | |
ab77a036 RS |
5073 | size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); |
5074 | return size == -1 || size > UNITS_PER_WORD; | |
5075 | } | |
5076 | else | |
cee98a59 | 5077 | { |
ab77a036 RS |
5078 | /* If we have a variable-sized parameter, we have no choice. */ |
5079 | return targetm.calls.must_pass_in_stack (mode, type); | |
cee98a59 | 5080 | } |
cee98a59 MM |
5081 | } |
5082 | ||
65239d20 RS |
5083 | /* Implement TARGET_CALLEE_COPIES. */ |
5084 | ||
ab77a036 | 5085 | static bool |
d5cc9181 | 5086 | mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ab77a036 RS |
5087 | enum machine_mode mode ATTRIBUTE_UNUSED, |
5088 | const_tree type ATTRIBUTE_UNUSED, bool named) | |
5089 | { | |
5090 | return mips_abi == ABI_EABI && named; | |
5091 | } | |
5092 | \f | |
5093 | /* See whether VALTYPE is a record whose fields should be returned in | |
5094 | floating-point registers. If so, return the number of fields and | |
5095 | list them in FIELDS (which should have two elements). Return 0 | |
5096 | otherwise. | |
b4966b1b | 5097 | |
ab77a036 RS |
5098 | For n32 & n64, a structure with one or two fields is returned in |
5099 | floating-point registers as long as every field has a floating-point | |
5100 | type. */ | |
b4966b1b | 5101 | |
ab77a036 RS |
5102 | static int |
5103 | mips_fpr_return_fields (const_tree valtype, tree *fields) | |
4d72536e | 5104 | { |
ab77a036 RS |
5105 | tree field; |
5106 | int i; | |
4d72536e | 5107 | |
ab77a036 RS |
5108 | if (!TARGET_NEWABI) |
5109 | return 0; | |
4d72536e | 5110 | |
ab77a036 RS |
5111 | if (TREE_CODE (valtype) != RECORD_TYPE) |
5112 | return 0; | |
4d72536e | 5113 | |
ab77a036 | 5114 | i = 0; |
910ad8de | 5115 | for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field)) |
ae043003 | 5116 | { |
ab77a036 RS |
5117 | if (TREE_CODE (field) != FIELD_DECL) |
5118 | continue; | |
ae043003 | 5119 | |
a3d97724 | 5120 | if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) |
ab77a036 | 5121 | return 0; |
ae043003 | 5122 | |
ab77a036 RS |
5123 | if (i == 2) |
5124 | return 0; | |
ae043003 | 5125 | |
ab77a036 RS |
5126 | fields[i++] = field; |
5127 | } | |
5128 | return i; | |
5129 | } | |
ae043003 | 5130 | |
ab77a036 RS |
5131 | /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return |
5132 | a value in the most significant part of $2/$3 if: | |
ae043003 | 5133 | |
ab77a036 | 5134 | - the target is big-endian; |
ae043003 | 5135 | |
ab77a036 RS |
5136 | - the value has a structure or union type (we generalize this to |
5137 | cover aggregates from other languages too); and | |
4d72536e | 5138 | |
ab77a036 | 5139 | - the structure is not returned in floating-point registers. */ |
4d72536e | 5140 | |
ab77a036 RS |
5141 | static bool |
5142 | mips_return_in_msb (const_tree valtype) | |
5143 | { | |
5144 | tree fields[2]; | |
4d72536e | 5145 | |
ab77a036 RS |
5146 | return (TARGET_NEWABI |
5147 | && TARGET_BIG_ENDIAN | |
5148 | && AGGREGATE_TYPE_P (valtype) | |
5149 | && mips_fpr_return_fields (valtype, fields) == 0); | |
4d72536e RS |
5150 | } |
5151 | ||
ab77a036 RS |
5152 | /* Return true if the function return value MODE will get returned in a |
5153 | floating-point register. */ | |
a38e0142 | 5154 | |
ab77a036 RS |
5155 | static bool |
5156 | mips_return_mode_in_fpr_p (enum machine_mode mode) | |
a38e0142 | 5157 | { |
ab77a036 | 5158 | return ((GET_MODE_CLASS (mode) == MODE_FLOAT |
7dab511c | 5159 | || mode == V2SFmode |
ab77a036 RS |
5160 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
5161 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); | |
a38e0142 SL |
5162 | } |
5163 | ||
fd0d4c1f RS |
5164 | /* Return the representation of an FPR return register when the |
5165 | value being returned in FP_RETURN has mode VALUE_MODE and the | |
5166 | return type itself has mode TYPE_MODE. On NewABI targets, | |
5167 | the two modes may be different for structures like: | |
5168 | ||
5169 | struct __attribute__((packed)) foo { float f; } | |
5170 | ||
5171 | where we return the SFmode value of "f" in FP_RETURN, but where | |
5172 | the structure itself has mode BLKmode. */ | |
5173 | ||
5174 | static rtx | |
5175 | mips_return_fpr_single (enum machine_mode type_mode, | |
5176 | enum machine_mode value_mode) | |
5177 | { | |
5178 | rtx x; | |
5179 | ||
5180 | x = gen_rtx_REG (value_mode, FP_RETURN); | |
5181 | if (type_mode != value_mode) | |
5182 | { | |
5183 | x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); | |
5184 | x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); | |
5185 | } | |
5186 | return x; | |
5187 | } | |
5188 | ||
ab77a036 RS |
5189 | /* Return a composite value in a pair of floating-point registers. |
5190 | MODE1 and OFFSET1 are the mode and byte offset for the first value, | |
5191 | likewise MODE2 and OFFSET2 for the second. MODE is the mode of the | |
5192 | complete value. | |
cee98a59 | 5193 | |
ab77a036 RS |
5194 | For n32 & n64, $f0 always holds the first value and $f2 the second. |
5195 | Otherwise the values are packed together as closely as possible. */ | |
cee98a59 | 5196 | |
ab77a036 RS |
5197 | static rtx |
5198 | mips_return_fpr_pair (enum machine_mode mode, | |
5199 | enum machine_mode mode1, HOST_WIDE_INT offset1, | |
5200 | enum machine_mode mode2, HOST_WIDE_INT offset2) | |
5201 | { | |
5202 | int inc; | |
cee98a59 | 5203 | |
ab77a036 RS |
5204 | inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT); |
5205 | return gen_rtx_PARALLEL | |
5206 | (mode, | |
5207 | gen_rtvec (2, | |
5208 | gen_rtx_EXPR_LIST (VOIDmode, | |
5209 | gen_rtx_REG (mode1, FP_RETURN), | |
5210 | GEN_INT (offset1)), | |
5211 | gen_rtx_EXPR_LIST (VOIDmode, | |
5212 | gen_rtx_REG (mode2, FP_RETURN + inc), | |
5213 | GEN_INT (offset2)))); | |
cee98a59 | 5214 | |
cee98a59 MM |
5215 | } |
5216 | ||
47be3d6d AS |
5217 | /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE. |
5218 | For normal calls, VALTYPE is the return type and MODE is VOIDmode. | |
5219 | For libcalls, VALTYPE is null and MODE is the mode of the return value. */ | |
cee98a59 | 5220 | |
47be3d6d AS |
5221 | static rtx |
5222 | mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type, | |
5223 | enum machine_mode mode) | |
ab77a036 RS |
5224 | { |
5225 | if (valtype) | |
cee98a59 | 5226 | { |
ab77a036 | 5227 | tree fields[2]; |
65239d20 | 5228 | int unsigned_p; |
47be3d6d AS |
5229 | const_tree func; |
5230 | ||
5231 | if (fn_decl_or_type && DECL_P (fn_decl_or_type)) | |
5232 | func = fn_decl_or_type; | |
5233 | else | |
5234 | func = NULL; | |
cee98a59 | 5235 | |
ab77a036 | 5236 | mode = TYPE_MODE (valtype); |
65239d20 | 5237 | unsigned_p = TYPE_UNSIGNED (valtype); |
4d72536e | 5238 | |
cde0f3fd PB |
5239 | /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, |
5240 | return values, promote the mode here too. */ | |
5241 | mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); | |
0e5a4ad8 | 5242 | |
ab77a036 RS |
5243 | /* Handle structures whose fields are returned in $f0/$f2. */ |
5244 | switch (mips_fpr_return_fields (valtype, fields)) | |
a20b7b05 | 5245 | { |
ab77a036 | 5246 | case 1: |
fd0d4c1f RS |
5247 | return mips_return_fpr_single (mode, |
5248 | TYPE_MODE (TREE_TYPE (fields[0]))); | |
4d72536e | 5249 | |
ab77a036 RS |
5250 | case 2: |
5251 | return mips_return_fpr_pair (mode, | |
5252 | TYPE_MODE (TREE_TYPE (fields[0])), | |
5253 | int_byte_position (fields[0]), | |
5254 | TYPE_MODE (TREE_TYPE (fields[1])), | |
5255 | int_byte_position (fields[1])); | |
5256 | } | |
4d72536e | 5257 | |
ab77a036 RS |
5258 | /* If a value is passed in the most significant part of a register, see |
5259 | whether we have to round the mode up to a whole number of words. */ | |
5260 | if (mips_return_in_msb (valtype)) | |
5261 | { | |
5262 | HOST_WIDE_INT size = int_size_in_bytes (valtype); | |
5263 | if (size % UNITS_PER_WORD != 0) | |
a20b7b05 | 5264 | { |
ab77a036 RS |
5265 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; |
5266 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4d72536e | 5267 | } |
3f1f8d8c | 5268 | } |
ab77a036 RS |
5269 | |
5270 | /* For EABI, the class of return register depends entirely on MODE. | |
5271 | For example, "struct { some_type x; }" and "union { some_type x; }" | |
5272 | are returned in the same way as a bare "some_type" would be. | |
5273 | Other ABIs only use FPRs for scalar, complex or vector types. */ | |
5274 | if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype)) | |
5275 | return gen_rtx_REG (mode, GP_RETURN); | |
3f1f8d8c MM |
5276 | } |
5277 | ||
ab77a036 | 5278 | if (!TARGET_MIPS16) |
ae043003 | 5279 | { |
ab77a036 RS |
5280 | /* Handle long doubles for n32 & n64. */ |
5281 | if (mode == TFmode) | |
5282 | return mips_return_fpr_pair (mode, | |
5283 | DImode, 0, | |
5284 | DImode, GET_MODE_SIZE (mode) / 2); | |
ae043003 | 5285 | |
ab77a036 | 5286 | if (mips_return_mode_in_fpr_p (mode)) |
0882b52e | 5287 | { |
ab77a036 RS |
5288 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
5289 | return mips_return_fpr_pair (mode, | |
5290 | GET_MODE_INNER (mode), 0, | |
5291 | GET_MODE_INNER (mode), | |
5292 | GET_MODE_SIZE (mode) / 2); | |
5293 | else | |
5294 | return gen_rtx_REG (mode, FP_RETURN); | |
0882b52e | 5295 | } |
ae043003 RS |
5296 | } |
5297 | ||
ab77a036 | 5298 | return gen_rtx_REG (mode, GP_RETURN); |
cee98a59 MM |
5299 | } |
5300 | ||
47be3d6d AS |
5301 | /* Implement TARGET_FUNCTION_VALUE. */ |
5302 | ||
5303 | static rtx | |
5304 | mips_function_value (const_tree valtype, const_tree fn_decl_or_type, | |
5305 | bool outgoing ATTRIBUTE_UNUSED) | |
5306 | { | |
5307 | return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode); | |
5308 | } | |
5309 | ||
5310 | /* Implement TARGET_LIBCALL_VALUE. */ | |
5311 | ||
5312 | static rtx | |
5313 | mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) | |
5314 | { | |
5315 | return mips_function_value_1 (NULL_TREE, NULL_TREE, mode); | |
5316 | } | |
5317 | ||
5318 | /* Implement TARGET_FUNCTION_VALUE_REGNO_P. | |
5319 | ||
5320 | On the MIPS, R2 R3 and F0 F2 are the only register thus used. | |
5321 | Currently, R2 and F0 are only implemented here (C has no complex type). */ | |
5322 | ||
5323 | static bool | |
5324 | mips_function_value_regno_p (const unsigned int regno) | |
5325 | { | |
5326 | if (regno == GP_RETURN | |
5327 | || regno == FP_RETURN | |
5328 | || (LONG_DOUBLE_TYPE_SIZE == 128 | |
5329 | && FP_RETURN != GP_RETURN | |
5330 | && regno == FP_RETURN + 2)) | |
5331 | return true; | |
5332 | ||
5333 | return false; | |
5334 | } | |
5335 | ||
65239d20 RS |
5336 | /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs, |
5337 | all BLKmode objects are returned in memory. Under the n32, n64 | |
5338 | and embedded ABIs, small structures are returned in a register. | |
ab77a036 RS |
5339 | Objects with varying size must still be returned in memory, of |
5340 | course. */ | |
b4966b1b | 5341 | |
ab77a036 RS |
5342 | static bool |
5343 | mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) | |
648bb159 | 5344 | { |
65239d20 RS |
5345 | return (TARGET_OLDABI |
5346 | ? TYPE_MODE (type) == BLKmode | |
5347 | : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD)); | |
648bb159 | 5348 | } |
4d72536e | 5349 | \f |
65239d20 RS |
5350 | /* Implement TARGET_SETUP_INCOMING_VARARGS. */ |
5351 | ||
0c8da560 | 5352 | static void |
d5cc9181 | 5353 | mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode, |
4001cd89 RS |
5354 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5355 | int no_rtl) | |
4d72536e RS |
5356 | { |
5357 | CUMULATIVE_ARGS local_cum; | |
5358 | int gp_saved, fp_saved; | |
cee98a59 | 5359 | |
4d72536e RS |
5360 | /* The caller has advanced CUM up to, but not beyond, the last named |
5361 | argument. Advance a local copy of CUM past the last "real" named | |
6c535c69 | 5362 | argument, to find out how many registers are left over. */ |
d5cc9181 JR |
5363 | local_cum = *get_cumulative_args (cum); |
5364 | mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, | |
5365 | true); | |
4d72536e RS |
5366 | |
5367 | /* Found out how many registers we need to save. */ | |
bb63e5a0 | 5368 | gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; |
4d72536e | 5369 | fp_saved = (EABI_FLOAT_VARARGS_P |
bb63e5a0 | 5370 | ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs |
4d72536e | 5371 | : 0); |
cee98a59 | 5372 | |
4d72536e | 5373 | if (!no_rtl) |
cee98a59 | 5374 | { |
4d72536e RS |
5375 | if (gp_saved > 0) |
5376 | { | |
5377 | rtx ptr, mem; | |
5378 | ||
4001cd89 RS |
5379 | ptr = plus_constant (virtual_incoming_args_rtx, |
5380 | REG_PARM_STACK_SPACE (cfun->decl) | |
5381 | - gp_saved * UNITS_PER_WORD); | |
8d0e1e43 | 5382 | mem = gen_frame_mem (BLKmode, ptr); |
520d96c6 | 5383 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
4d72536e | 5384 | |
520d96c6 RS |
5385 | move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, |
5386 | mem, gp_saved); | |
4d72536e RS |
5387 | } |
5388 | if (fp_saved > 0) | |
5389 | { | |
5390 | /* We can't use move_block_from_reg, because it will use | |
031a26c5 | 5391 | the wrong mode. */ |
4d72536e RS |
5392 | enum machine_mode mode; |
5393 | int off, i; | |
cee98a59 | 5394 | |
4d72536e | 5395 | /* Set OFF to the offset from virtual_incoming_args_rtx of |
71cc389b | 5396 | the first float register. The FP save area lies below |
4d72536e | 5397 | the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */ |
65239d20 | 5398 | off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE; |
4d72536e | 5399 | off -= fp_saved * UNITS_PER_FPREG; |
cee98a59 | 5400 | |
4d72536e RS |
5401 | mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; |
5402 | ||
e8ab09c1 SL |
5403 | for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; |
5404 | i += MAX_FPRS_PER_FMT) | |
4d72536e | 5405 | { |
520d96c6 RS |
5406 | rtx ptr, mem; |
5407 | ||
5408 | ptr = plus_constant (virtual_incoming_args_rtx, off); | |
8d0e1e43 | 5409 | mem = gen_frame_mem (mode, ptr); |
520d96c6 | 5410 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
51e7252a | 5411 | mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i)); |
8a381273 | 5412 | off += UNITS_PER_HWFPVALUE; |
4d72536e RS |
5413 | } |
5414 | } | |
5415 | } | |
4001cd89 RS |
5416 | if (REG_PARM_STACK_SPACE (cfun->decl) == 0) |
5417 | cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD | |
5418 | + fp_saved * UNITS_PER_FPREG); | |
cee98a59 | 5419 | } |
4d72536e | 5420 | |
65239d20 | 5421 | /* Implement TARGET_BUILTIN_VA_LIST. */ |
4fe12442 | 5422 | |
c35d187f RH |
5423 | static tree |
5424 | mips_build_builtin_va_list (void) | |
5d3f2bd5 | 5425 | { |
4d72536e | 5426 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5427 | { |
65239d20 RS |
5428 | /* We keep 3 pointers, and two offsets. |
5429 | ||
5430 | Two pointers are to the overflow area, which starts at the CFA. | |
5431 | One of these is constant, for addressing into the GPR save area | |
5432 | below it. The other is advanced up the stack through the | |
5433 | overflow region. | |
5434 | ||
5435 | The third pointer is to the bottom of the GPR save area. | |
5436 | Since the FPR save area is just below it, we can address | |
5437 | FPR slots off this pointer. | |
5438 | ||
5439 | We also keep two one-byte offsets, which are to be subtracted | |
5440 | from the constant pointers to yield addresses in the GPR and | |
5441 | FPR save areas. These are downcounted as float or non-float | |
5442 | arguments are used, and when they get to zero, the argument | |
5443 | must be obtained from the overflow region. */ | |
7a0ec607 CD |
5444 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record; |
5445 | tree array, index; | |
5d3f2bd5 | 5446 | |
65239d20 | 5447 | record = lang_hooks.types.make_type (RECORD_TYPE); |
5d3f2bd5 | 5448 | |
4c4bde29 AH |
5449 | f_ovfl = build_decl (BUILTINS_LOCATION, |
5450 | FIELD_DECL, get_identifier ("__overflow_argptr"), | |
65239d20 | 5451 | ptr_type_node); |
4c4bde29 AH |
5452 | f_gtop = build_decl (BUILTINS_LOCATION, |
5453 | FIELD_DECL, get_identifier ("__gpr_top"), | |
65239d20 | 5454 | ptr_type_node); |
4c4bde29 AH |
5455 | f_ftop = build_decl (BUILTINS_LOCATION, |
5456 | FIELD_DECL, get_identifier ("__fpr_top"), | |
65239d20 | 5457 | ptr_type_node); |
4c4bde29 AH |
5458 | f_goff = build_decl (BUILTINS_LOCATION, |
5459 | FIELD_DECL, get_identifier ("__gpr_offset"), | |
65239d20 | 5460 | unsigned_char_type_node); |
4c4bde29 AH |
5461 | f_foff = build_decl (BUILTINS_LOCATION, |
5462 | FIELD_DECL, get_identifier ("__fpr_offset"), | |
65239d20 | 5463 | unsigned_char_type_node); |
7a0ec607 CD |
5464 | /* Explicitly pad to the size of a pointer, so that -Wpadded won't |
5465 | warn on every user file. */ | |
7d60be94 | 5466 | index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1); |
7a0ec607 CD |
5467 | array = build_array_type (unsigned_char_type_node, |
5468 | build_index_type (index)); | |
4c4bde29 AH |
5469 | f_res = build_decl (BUILTINS_LOCATION, |
5470 | FIELD_DECL, get_identifier ("__reserved"), array); | |
5d3f2bd5 | 5471 | |
4fe12442 DL |
5472 | DECL_FIELD_CONTEXT (f_ovfl) = record; |
5473 | DECL_FIELD_CONTEXT (f_gtop) = record; | |
5474 | DECL_FIELD_CONTEXT (f_ftop) = record; | |
5475 | DECL_FIELD_CONTEXT (f_goff) = record; | |
5476 | DECL_FIELD_CONTEXT (f_foff) = record; | |
7a0ec607 | 5477 | DECL_FIELD_CONTEXT (f_res) = record; |
5d3f2bd5 | 5478 | |
4fe12442 | 5479 | TYPE_FIELDS (record) = f_ovfl; |
910ad8de NF |
5480 | DECL_CHAIN (f_ovfl) = f_gtop; |
5481 | DECL_CHAIN (f_gtop) = f_ftop; | |
5482 | DECL_CHAIN (f_ftop) = f_goff; | |
5483 | DECL_CHAIN (f_goff) = f_foff; | |
5484 | DECL_CHAIN (f_foff) = f_res; | |
5d3f2bd5 | 5485 | |
4fe12442 | 5486 | layout_type (record); |
5d3f2bd5 RH |
5487 | return record; |
5488 | } | |
9aaa1ee8 | 5489 | else if (TARGET_IRIX6) |
4f1cad00 RH |
5490 | /* On IRIX 6, this type is 'char *'. */ |
5491 | return build_pointer_type (char_type_node); | |
5d3f2bd5 | 5492 | else |
4f1cad00 RH |
5493 | /* Otherwise, we use 'void *'. */ |
5494 | return ptr_type_node; | |
5d3f2bd5 RH |
5495 | } |
5496 | ||
d7bd8aeb | 5497 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ |
5d3f2bd5 | 5498 | |
d7bd8aeb | 5499 | static void |
b4966b1b | 5500 | mips_va_start (tree valist, rtx nextarg) |
5d3f2bd5 | 5501 | { |
4001cd89 | 5502 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5503 | { |
4001cd89 RS |
5504 | const CUMULATIVE_ARGS *cum; |
5505 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; | |
5506 | tree ovfl, gtop, ftop, goff, foff; | |
5507 | tree t; | |
4fe12442 | 5508 | int gpr_save_area_size; |
4001cd89 RS |
5509 | int fpr_save_area_size; |
5510 | int fpr_offset; | |
4fe12442 | 5511 | |
38173d38 | 5512 | cum = &crtl->args.info; |
4d72536e | 5513 | gpr_save_area_size |
bb63e5a0 | 5514 | = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD; |
4001cd89 RS |
5515 | fpr_save_area_size |
5516 | = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG; | |
4d72536e | 5517 | |
4001cd89 | 5518 | f_ovfl = TYPE_FIELDS (va_list_type_node); |
910ad8de NF |
5519 | f_gtop = DECL_CHAIN (f_ovfl); |
5520 | f_ftop = DECL_CHAIN (f_gtop); | |
5521 | f_goff = DECL_CHAIN (f_ftop); | |
5522 | f_foff = DECL_CHAIN (f_goff); | |
4001cd89 | 5523 | |
47a25a46 RG |
5524 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5525 | NULL_TREE); | |
5526 | gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, | |
5527 | NULL_TREE); | |
5528 | ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, | |
5529 | NULL_TREE); | |
5530 | goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, | |
5531 | NULL_TREE); | |
5532 | foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, | |
5533 | NULL_TREE); | |
4001cd89 RS |
5534 | |
5535 | /* Emit code to initialize OVFL, which points to the next varargs | |
5536 | stack argument. CUM->STACK_WORDS gives the number of stack | |
5537 | words used by named arguments. */ | |
5538 | t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); | |
5539 | if (cum->stack_words > 0) | |
5d49b6a7 | 5540 | t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD); |
726a989a | 5541 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); |
4001cd89 RS |
5542 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5543 | ||
5544 | /* Emit code to initialize GTOP, the top of the GPR save area. */ | |
5545 | t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); | |
726a989a | 5546 | t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); |
4001cd89 RS |
5547 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5548 | ||
5549 | /* Emit code to initialize FTOP, the top of the FPR save area. | |
5550 | This address is gpr_save_area_bytes below GTOP, rounded | |
5551 | down to the next fp-aligned boundary. */ | |
5552 | t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); | |
5553 | fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1; | |
65239d20 | 5554 | fpr_offset &= -UNITS_PER_FPVALUE; |
4001cd89 | 5555 | if (fpr_offset) |
5d49b6a7 | 5556 | t = fold_build_pointer_plus_hwi (t, -fpr_offset); |
726a989a | 5557 | t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t); |
4001cd89 RS |
5558 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5559 | ||
5560 | /* Emit code to initialize GOFF, the offset from GTOP of the | |
5561 | next GPR argument. */ | |
726a989a | 5562 | t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff, |
e0681eaa | 5563 | build_int_cst (TREE_TYPE (goff), gpr_save_area_size)); |
4001cd89 RS |
5564 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5565 | ||
5566 | /* Likewise emit code to initialize FOFF, the offset from FTOP | |
5567 | of the next FPR argument. */ | |
726a989a | 5568 | t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff, |
e0681eaa | 5569 | build_int_cst (TREE_TYPE (foff), fpr_save_area_size)); |
4001cd89 | 5570 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5d3f2bd5 RH |
5571 | } |
5572 | else | |
4001cd89 RS |
5573 | { |
5574 | nextarg = plus_constant (nextarg, -cfun->machine->varargs_size); | |
5575 | std_expand_builtin_va_start (valist, nextarg); | |
5576 | } | |
5d3f2bd5 | 5577 | } |
65239d20 | 5578 | |
4566de10 RS |
5579 | /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized |
5580 | types as well. */ | |
5581 | ||
5582 | static tree | |
5583 | mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, | |
5584 | gimple_seq *post_p) | |
5585 | { | |
5586 | tree addr, t, type_size, rounded_size, valist_tmp; | |
5587 | unsigned HOST_WIDE_INT align, boundary; | |
5588 | bool indirect; | |
5589 | ||
5590 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); | |
5591 | if (indirect) | |
5592 | type = build_pointer_type (type); | |
5593 | ||
5594 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
5595 | boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type); | |
5596 | ||
5597 | /* When we align parameter on stack for caller, if the parameter | |
5598 | alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be | |
5599 | aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee | |
5600 | here with caller. */ | |
5601 | if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT) | |
5602 | boundary = MAX_SUPPORTED_STACK_ALIGNMENT; | |
5603 | ||
5604 | boundary /= BITS_PER_UNIT; | |
5605 | ||
5606 | /* Hoist the valist value into a temporary for the moment. */ | |
5607 | valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL); | |
5608 | ||
5609 | /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually | |
5610 | requires greater alignment, we must perform dynamic alignment. */ | |
5611 | if (boundary > align) | |
5612 | { | |
5613 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, | |
5614 | fold_build_pointer_plus_hwi (valist_tmp, boundary - 1)); | |
5615 | gimplify_and_add (t, pre_p); | |
5616 | ||
5617 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, | |
5618 | fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist), | |
5619 | valist_tmp, | |
5620 | build_int_cst (TREE_TYPE (valist), -boundary))); | |
5621 | gimplify_and_add (t, pre_p); | |
5622 | } | |
5623 | else | |
5624 | boundary = align; | |
5625 | ||
5626 | /* If the actual alignment is less than the alignment of the type, | |
5627 | adjust the type accordingly so that we don't assume strict alignment | |
5628 | when dereferencing the pointer. */ | |
5629 | boundary *= BITS_PER_UNIT; | |
5630 | if (boundary < TYPE_ALIGN (type)) | |
5631 | { | |
5632 | type = build_variant_type_copy (type); | |
5633 | TYPE_ALIGN (type) = boundary; | |
5634 | } | |
5635 | ||
5636 | /* Compute the rounded size of the type. */ | |
5637 | type_size = size_in_bytes (type); | |
5638 | rounded_size = round_up (type_size, align); | |
5639 | ||
5640 | /* Reduce rounded_size so it's sharable with the postqueue. */ | |
5641 | gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue); | |
5642 | ||
5643 | /* Get AP. */ | |
5644 | addr = valist_tmp; | |
5645 | if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size)) | |
5646 | { | |
5647 | /* Small args are padded downward. */ | |
5648 | t = fold_build2_loc (input_location, GT_EXPR, sizetype, | |
5649 | rounded_size, size_int (align)); | |
5650 | t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node, | |
5651 | size_binop (MINUS_EXPR, rounded_size, type_size)); | |
5652 | addr = fold_build_pointer_plus (addr, t); | |
5653 | } | |
5654 | ||
5655 | /* Compute new value for AP. */ | |
5656 | t = fold_build_pointer_plus (valist_tmp, rounded_size); | |
5657 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
5658 | gimplify_and_add (t, pre_p); | |
5659 | ||
5660 | addr = fold_convert (build_pointer_type (type), addr); | |
5661 | ||
5662 | if (indirect) | |
5663 | addr = build_va_arg_indirect_ref (addr); | |
5664 | ||
5665 | return build_va_arg_indirect_ref (addr); | |
5666 | } | |
5667 | ||
65239d20 | 5668 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ |
5d3f2bd5 | 5669 | |
0310e537 | 5670 | static tree |
726a989a RB |
5671 | mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
5672 | gimple_seq *post_p) | |
5d3f2bd5 | 5673 | { |
0310e537 | 5674 | tree addr; |
65239d20 | 5675 | bool indirect_p; |
0310e537 | 5676 | |
65239d20 RS |
5677 | indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
5678 | if (indirect_p) | |
0310e537 | 5679 | type = build_pointer_type (type); |
5d3f2bd5 | 5680 | |
65239d20 | 5681 | if (!EABI_FLOAT_VARARGS_P) |
4566de10 | 5682 | addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
0310e537 | 5683 | else |
5d3f2bd5 | 5684 | { |
0310e537 RH |
5685 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; |
5686 | tree ovfl, top, off, align; | |
65239d20 | 5687 | HOST_WIDE_INT size, rsize, osize; |
0310e537 RH |
5688 | tree t, u; |
5689 | ||
5690 | f_ovfl = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
5691 | f_gtop = DECL_CHAIN (f_ovfl); |
5692 | f_ftop = DECL_CHAIN (f_gtop); | |
5693 | f_goff = DECL_CHAIN (f_ftop); | |
5694 | f_foff = DECL_CHAIN (f_goff); | |
0310e537 | 5695 | |
65239d20 | 5696 | /* Let: |
0310e537 | 5697 | |
65239d20 | 5698 | TOP be the top of the GPR or FPR save area; |
0310e537 RH |
5699 | OFF be the offset from TOP of the next register; |
5700 | ADDR_RTX be the address of the argument; | |
65239d20 | 5701 | SIZE be the number of bytes in the argument type; |
0310e537 | 5702 | RSIZE be the number of bytes used to store the argument |
65239d20 | 5703 | when it's in the register save area; and |
0310e537 | 5704 | OSIZE be the number of bytes used to store it when it's |
65239d20 | 5705 | in the stack overflow area. |
0310e537 RH |
5706 | |
5707 | The code we want is: | |
5708 | ||
5709 | 1: off &= -rsize; // round down | |
5710 | 2: if (off != 0) | |
5711 | 3: { | |
65239d20 RS |
5712 | 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0); |
5713 | 5: off -= rsize; | |
0310e537 RH |
5714 | 6: } |
5715 | 7: else | |
5716 | 8: { | |
65239d20 RS |
5717 | 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize; |
5718 | 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0); | |
5719 | 11: ovfl += osize; | |
5720 | 14: } | |
0310e537 RH |
5721 | |
5722 | [1] and [9] can sometimes be optimized away. */ | |
5723 | ||
47a25a46 RG |
5724 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5725 | NULL_TREE); | |
65239d20 | 5726 | size = int_size_in_bytes (type); |
0310e537 RH |
5727 | |
5728 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT | |
5729 | && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE) | |
5d3f2bd5 | 5730 | { |
6d8d5435 RS |
5731 | top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), |
5732 | unshare_expr (valist), f_ftop, NULL_TREE); | |
5733 | off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), | |
5734 | unshare_expr (valist), f_foff, NULL_TREE); | |
0310e537 | 5735 | |
65239d20 RS |
5736 | /* When va_start saves FPR arguments to the stack, each slot |
5737 | takes up UNITS_PER_HWFPVALUE bytes, regardless of the | |
5738 | argument's precision. */ | |
0310e537 RH |
5739 | rsize = UNITS_PER_HWFPVALUE; |
5740 | ||
5741 | /* Overflow arguments are padded to UNITS_PER_WORD bytes | |
5742 | (= PARM_BOUNDARY bits). This can be different from RSIZE | |
5743 | in two cases: | |
5744 | ||
5745 | (1) On 32-bit targets when TYPE is a structure such as: | |
5746 | ||
5747 | struct s { float f; }; | |
5748 | ||
5749 | Such structures are passed in paired FPRs, so RSIZE | |
5750 | will be 8 bytes. However, the structure only takes | |
5751 | up 4 bytes of memory, so OSIZE will only be 4. | |
5752 | ||
5753 | (2) In combinations such as -mgp64 -msingle-float | |
65239d20 RS |
5754 | -fshort-double. Doubles passed in registers will then take |
5755 | up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the | |
5756 | stack take up UNITS_PER_WORD bytes. */ | |
0310e537 | 5757 | osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD); |
5d3f2bd5 | 5758 | } |
4d72536e RS |
5759 | else |
5760 | { | |
6d8d5435 RS |
5761 | top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), |
5762 | unshare_expr (valist), f_gtop, NULL_TREE); | |
5763 | off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), | |
5764 | unshare_expr (valist), f_goff, NULL_TREE); | |
65239d20 | 5765 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; |
0310e537 | 5766 | if (rsize > UNITS_PER_WORD) |
4fe12442 | 5767 | { |
0310e537 | 5768 | /* [1] Emit code for: off &= -rsize. */ |
6d8d5435 | 5769 | t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off), |
3179cf8c | 5770 | build_int_cst (TREE_TYPE (off), -rsize)); |
6d8d5435 | 5771 | gimplify_assign (unshare_expr (off), t, pre_p); |
4d72536e | 5772 | } |
0310e537 RH |
5773 | osize = rsize; |
5774 | } | |
a85cd407 | 5775 | |
0310e537 | 5776 | /* [2] Emit code to branch if off == 0. */ |
1ab9ec7b | 5777 | t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off), |
47a25a46 RG |
5778 | build_int_cst (TREE_TYPE (off), 0)); |
5779 | addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); | |
0310e537 RH |
5780 | |
5781 | /* [5] Emit code for: off -= rsize. We do this as a form of | |
65239d20 | 5782 | post-decrement not available to C. */ |
7d60be94 | 5783 | t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize)); |
47a25a46 | 5784 | t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t); |
65239d20 RS |
5785 | |
5786 | /* [4] Emit code for: | |
5787 | addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */ | |
0310e537 | 5788 | t = fold_convert (sizetype, t); |
5be014d5 | 5789 | t = fold_build1 (NEGATE_EXPR, sizetype, t); |
5d49b6a7 | 5790 | t = fold_build_pointer_plus (top, t); |
0310e537 | 5791 | if (BYTES_BIG_ENDIAN && rsize > size) |
5d49b6a7 | 5792 | t = fold_build_pointer_plus_hwi (t, rsize - size); |
0310e537 | 5793 | COND_EXPR_THEN (addr) = t; |
a85cd407 | 5794 | |
0310e537 RH |
5795 | if (osize > UNITS_PER_WORD) |
5796 | { | |
65239d20 | 5797 | /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */ |
5d49b6a7 RG |
5798 | t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1); |
5799 | u = build_int_cst (TREE_TYPE (t), -osize); | |
1ab9ec7b | 5800 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u); |
6d8d5435 RS |
5801 | align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), |
5802 | unshare_expr (ovfl), t); | |
4d72536e | 5803 | } |
0310e537 RH |
5804 | else |
5805 | align = NULL; | |
5806 | ||
65239d20 RS |
5807 | /* [10, 11] Emit code for: |
5808 | addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0) | |
5809 | ovfl += osize. */ | |
5810 | u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize)); | |
47a25a46 | 5811 | t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u); |
0310e537 | 5812 | if (BYTES_BIG_ENDIAN && osize > size) |
5d49b6a7 | 5813 | t = fold_build_pointer_plus_hwi (t, osize - size); |
5d3f2bd5 | 5814 | |
65239d20 | 5815 | /* String [9] and [10, 11] together. */ |
0310e537 | 5816 | if (align) |
47a25a46 | 5817 | t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t); |
0310e537 | 5818 | COND_EXPR_ELSE (addr) = t; |
5d3f2bd5 | 5819 | |
0310e537 | 5820 | addr = fold_convert (build_pointer_type (type), addr); |
d6e9821f | 5821 | addr = build_va_arg_indirect_ref (addr); |
0310e537 | 5822 | } |
e72ed4a7 | 5823 | |
65239d20 | 5824 | if (indirect_p) |
d6e9821f | 5825 | addr = build_va_arg_indirect_ref (addr); |
5d3f2bd5 | 5826 | |
0310e537 | 5827 | return addr; |
5d3f2bd5 RH |
5828 | } |
5829 | \f | |
b2b61607 RS |
5830 | /* Start a definition of function NAME. MIPS16_P indicates whether the |
5831 | function contains MIPS16 code. */ | |
5832 | ||
5833 | static void | |
5834 | mips_start_function_definition (const char *name, bool mips16_p) | |
5835 | { | |
5836 | if (mips16_p) | |
5837 | fprintf (asm_out_file, "\t.set\tmips16\n"); | |
5838 | else | |
5839 | fprintf (asm_out_file, "\t.set\tnomips16\n"); | |
5840 | ||
5841 | if (!flag_inhibit_size_directive) | |
5842 | { | |
5843 | fputs ("\t.ent\t", asm_out_file); | |
5844 | assemble_name (asm_out_file, name); | |
5845 | fputs ("\n", asm_out_file); | |
5846 | } | |
5847 | ||
5848 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function"); | |
5849 | ||
5850 | /* Start the definition proper. */ | |
5851 | assemble_name (asm_out_file, name); | |
5852 | fputs (":\n", asm_out_file); | |
5853 | } | |
5854 | ||
5855 | /* End a function definition started by mips_start_function_definition. */ | |
5856 | ||
5857 | static void | |
5858 | mips_end_function_definition (const char *name) | |
5859 | { | |
5860 | if (!flag_inhibit_size_directive) | |
5861 | { | |
5862 | fputs ("\t.end\t", asm_out_file); | |
5863 | assemble_name (asm_out_file, name); | |
5864 | fputs ("\n", asm_out_file); | |
5865 | } | |
5866 | } | |
5867 | \f | |
7462a715 RS |
5868 | /* Return true if calls to X can use R_MIPS_CALL* relocations. */ |
5869 | ||
5870 | static bool | |
5871 | mips_ok_for_lazy_binding_p (rtx x) | |
5872 | { | |
5873 | return (TARGET_USE_GOT | |
5874 | && GET_CODE (x) == SYMBOL_REF | |
08d0963a | 5875 | && !SYMBOL_REF_BIND_NOW_P (x) |
7462a715 RS |
5876 | && !mips_symbol_binds_local_p (x)); |
5877 | } | |
5878 | ||
08d0963a RS |
5879 | /* Load function address ADDR into register DEST. TYPE is as for |
5880 | mips_expand_call. Return true if we used an explicit lazy-binding | |
5881 | sequence. */ | |
7462a715 RS |
5882 | |
5883 | static bool | |
08d0963a | 5884 | mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr) |
7462a715 RS |
5885 | { |
5886 | /* If we're generating PIC, and this call is to a global function, | |
5887 | try to allow its address to be resolved lazily. This isn't | |
5888 | possible for sibcalls when $gp is call-saved because the value | |
5889 | of $gp on entry to the stub would be our caller's gp, not ours. */ | |
5890 | if (TARGET_EXPLICIT_RELOCS | |
08d0963a | 5891 | && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP) |
7462a715 RS |
5892 | && mips_ok_for_lazy_binding_p (addr)) |
5893 | { | |
08d0963a RS |
5894 | addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL); |
5895 | emit_insn (gen_rtx_SET (VOIDmode, dest, addr)); | |
7462a715 RS |
5896 | return true; |
5897 | } | |
5898 | else | |
5899 | { | |
5900 | mips_emit_move (dest, addr); | |
5901 | return false; | |
5902 | } | |
5903 | } | |
5904 | \f | |
08d0963a RS |
5905 | /* Each locally-defined hard-float MIPS16 function has a local symbol |
5906 | associated with it. This hash table maps the function symbol (FUNC) | |
5907 | to the local symbol (LOCAL). */ | |
d1b38208 | 5908 | struct GTY(()) mips16_local_alias { |
08d0963a RS |
5909 | rtx func; |
5910 | rtx local; | |
5911 | }; | |
5912 | static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases; | |
5913 | ||
5914 | /* Hash table callbacks for mips16_local_aliases. */ | |
5915 | ||
5916 | static hashval_t | |
5917 | mips16_local_aliases_hash (const void *entry) | |
5918 | { | |
5919 | const struct mips16_local_alias *alias; | |
5920 | ||
5921 | alias = (const struct mips16_local_alias *) entry; | |
5922 | return htab_hash_string (XSTR (alias->func, 0)); | |
5923 | } | |
5924 | ||
5925 | static int | |
5926 | mips16_local_aliases_eq (const void *entry1, const void *entry2) | |
5927 | { | |
5928 | const struct mips16_local_alias *alias1, *alias2; | |
5929 | ||
5930 | alias1 = (const struct mips16_local_alias *) entry1; | |
5931 | alias2 = (const struct mips16_local_alias *) entry2; | |
5932 | return rtx_equal_p (alias1->func, alias2->func); | |
5933 | } | |
5934 | ||
5935 | /* FUNC is the symbol for a locally-defined hard-float MIPS16 function. | |
5936 | Return a local alias for it, creating a new one if necessary. */ | |
5937 | ||
5938 | static rtx | |
5939 | mips16_local_alias (rtx func) | |
5940 | { | |
5941 | struct mips16_local_alias *alias, tmp_alias; | |
5942 | void **slot; | |
5943 | ||
5944 | /* Create the hash table if this is the first call. */ | |
5945 | if (mips16_local_aliases == NULL) | |
5946 | mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash, | |
5947 | mips16_local_aliases_eq, NULL); | |
5948 | ||
5949 | /* Look up the function symbol, creating a new entry if need be. */ | |
5950 | tmp_alias.func = func; | |
5951 | slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT); | |
5952 | gcc_assert (slot != NULL); | |
5953 | ||
5954 | alias = (struct mips16_local_alias *) *slot; | |
5955 | if (alias == NULL) | |
5956 | { | |
5957 | const char *func_name, *local_name; | |
5958 | rtx local; | |
5959 | ||
5960 | /* Create a new SYMBOL_REF for the local symbol. The choice of | |
5961 | __fn_local_* is based on the __fn_stub_* names that we've | |
5962 | traditionally used for the non-MIPS16 stub. */ | |
5963 | func_name = targetm.strip_name_encoding (XSTR (func, 0)); | |
5964 | local_name = ACONCAT (("__fn_local_", func_name, NULL)); | |
5965 | local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name)); | |
5966 | SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL; | |
5967 | ||
5968 | /* Create a new structure to represent the mapping. */ | |
a9429e29 | 5969 | alias = ggc_alloc_mips16_local_alias (); |
08d0963a RS |
5970 | alias->func = func; |
5971 | alias->local = local; | |
5972 | *slot = alias; | |
5973 | } | |
5974 | return alias->local; | |
5975 | } | |
5976 | \f | |
65239d20 RS |
5977 | /* A chained list of functions for which mips16_build_call_stub has already |
5978 | generated a stub. NAME is the name of the function and FP_RET_P is true | |
5979 | if the function returns a value in floating-point registers. */ | |
5980 | struct mips16_stub { | |
ab77a036 RS |
5981 | struct mips16_stub *next; |
5982 | char *name; | |
65239d20 | 5983 | bool fp_ret_p; |
ab77a036 | 5984 | }; |
ab77a036 | 5985 | static struct mips16_stub *mips16_stubs; |
b4966b1b | 5986 | |
65239d20 RS |
5987 | /* Return the two-character string that identifies floating-point |
5988 | return mode MODE in the name of a MIPS16 function stub. */ | |
b4966b1b | 5989 | |
ab77a036 RS |
5990 | static const char * |
5991 | mips16_call_stub_mode_suffix (enum machine_mode mode) | |
5992 | { | |
5993 | if (mode == SFmode) | |
5994 | return "sf"; | |
5995 | else if (mode == DFmode) | |
5996 | return "df"; | |
5997 | else if (mode == SCmode) | |
5998 | return "sc"; | |
5999 | else if (mode == DCmode) | |
6000 | return "dc"; | |
6001 | else if (mode == V2SFmode) | |
6002 | return "df"; | |
6003 | else | |
6004 | gcc_unreachable (); | |
6005 | } | |
b4966b1b | 6006 | |
5b372d33 RS |
6007 | /* Write instructions to move a 32-bit value between general register |
6008 | GPREG and floating-point register FPREG. DIRECTION is 't' to move | |
6009 | from GPREG to FPREG and 'f' to move in the opposite direction. */ | |
6010 | ||
6011 | static void | |
6012 | mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
6013 | { | |
6014 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6015 | reg_names[gpreg], reg_names[fpreg]); | |
6016 | } | |
6017 | ||
6018 | /* Likewise for 64-bit values. */ | |
6019 | ||
6020 | static void | |
6021 | mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
6022 | { | |
6023 | if (TARGET_64BIT) | |
6024 | fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction, | |
6025 | reg_names[gpreg], reg_names[fpreg]); | |
6026 | else if (TARGET_FLOAT64) | |
6027 | { | |
6028 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6029 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
6030 | fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction, | |
6031 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]); | |
6032 | } | |
6033 | else | |
6034 | { | |
6035 | /* Move the least-significant word. */ | |
6036 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6037 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
6038 | /* ...then the most significant word. */ | |
6039 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6040 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]); | |
6041 | } | |
6042 | } | |
6043 | ||
6044 | /* Write out code to move floating-point arguments into or out of | |
23fdf75c | 6045 | general registers. FP_CODE is the code describing which arguments |
5b372d33 RS |
6046 | are present (see the comment above the definition of CUMULATIVE_ARGS |
6047 | in mips.h). DIRECTION is as for mips_output_32bit_xfer. */ | |
b4966b1b | 6048 | |
ab77a036 | 6049 | static void |
5b372d33 | 6050 | mips_output_args_xfer (int fp_code, char direction) |
ab77a036 | 6051 | { |
5b372d33 | 6052 | unsigned int gparg, fparg, f; |
ab77a036 | 6053 | CUMULATIVE_ARGS cum; |
b4966b1b | 6054 | |
65239d20 | 6055 | /* This code only works for o32 and o64. */ |
ab77a036 | 6056 | gcc_assert (TARGET_OLDABI); |
b4966b1b | 6057 | |
65239d20 | 6058 | mips_init_cumulative_args (&cum, NULL); |
b4966b1b | 6059 | |
ab77a036 RS |
6060 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
6061 | { | |
6062 | enum machine_mode mode; | |
6063 | struct mips_arg_info info; | |
b4966b1b | 6064 | |
ab77a036 RS |
6065 | if ((f & 3) == 1) |
6066 | mode = SFmode; | |
6067 | else if ((f & 3) == 2) | |
6068 | mode = DFmode; | |
6069 | else | |
6070 | gcc_unreachable (); | |
b4966b1b | 6071 | |
65239d20 | 6072 | mips_get_arg_info (&info, &cum, mode, NULL, true); |
ab77a036 RS |
6073 | gparg = mips_arg_regno (&info, false); |
6074 | fparg = mips_arg_regno (&info, true); | |
b4966b1b | 6075 | |
ab77a036 | 6076 | if (mode == SFmode) |
5b372d33 | 6077 | mips_output_32bit_xfer (direction, gparg, fparg); |
ab77a036 | 6078 | else |
5b372d33 | 6079 | mips_output_64bit_xfer (direction, gparg, fparg); |
b4966b1b | 6080 | |
d5cc9181 | 6081 | mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true); |
b4966b1b | 6082 | } |
b4966b1b RS |
6083 | } |
6084 | ||
65239d20 RS |
6085 | /* Write a MIPS16 stub for the current function. This stub is used |
6086 | for functions which take arguments in the floating-point registers. | |
6087 | It is normal-mode code that moves the floating-point arguments | |
6088 | into the general registers and then jumps to the MIPS16 code. */ | |
b4966b1b | 6089 | |
ab77a036 | 6090 | static void |
65239d20 | 6091 | mips16_build_function_stub (void) |
b4966b1b | 6092 | { |
08d0963a | 6093 | const char *fnname, *alias_name, *separator; |
ab77a036 | 6094 | char *secname, *stubname; |
65239d20 | 6095 | tree stubdecl; |
ab77a036 | 6096 | unsigned int f; |
08d0963a | 6097 | rtx symbol, alias; |
b4966b1b | 6098 | |
65239d20 | 6099 | /* Create the name of the stub, and its unique section. */ |
08d0963a RS |
6100 | symbol = XEXP (DECL_RTL (current_function_decl), 0); |
6101 | alias = mips16_local_alias (symbol); | |
6102 | ||
6103 | fnname = targetm.strip_name_encoding (XSTR (symbol, 0)); | |
6104 | alias_name = targetm.strip_name_encoding (XSTR (alias, 0)); | |
65239d20 RS |
6105 | secname = ACONCAT ((".mips16.fn.", fnname, NULL)); |
6106 | stubname = ACONCAT (("__fn_stub_", fnname, NULL)); | |
6107 | ||
6108 | /* Build a decl for the stub. */ | |
4c4bde29 AH |
6109 | stubdecl = build_decl (BUILTINS_LOCATION, |
6110 | FUNCTION_DECL, get_identifier (stubname), | |
b861891b | 6111 | build_function_type_list (void_type_node, NULL_TREE)); |
ab77a036 | 6112 | DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); |
4c4bde29 AH |
6113 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6114 | RESULT_DECL, NULL_TREE, void_type_node); | |
b4966b1b | 6115 | |
65239d20 | 6116 | /* Output a comment. */ |
23fdf75c RS |
6117 | fprintf (asm_out_file, "\t# Stub function for %s (", |
6118 | current_function_name ()); | |
65239d20 | 6119 | separator = ""; |
38173d38 | 6120 | for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2) |
b4966b1b | 6121 | { |
65239d20 | 6122 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6123 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6124 | separator = ", "; |
b4966b1b | 6125 | } |
23fdf75c | 6126 | fprintf (asm_out_file, ")\n"); |
9226543b | 6127 | |
b2b61607 RS |
6128 | /* Start the function definition. */ |
6129 | assemble_start_function (stubdecl, stubname); | |
6130 | mips_start_function_definition (stubname, false); | |
e689b870 | 6131 | |
e21d5757 DJ |
6132 | /* If generating pic2 code, either set up the global pointer or |
6133 | switch to pic0. */ | |
6134 | if (TARGET_ABICALLS_PIC2) | |
08d0963a | 6135 | { |
e21d5757 DJ |
6136 | if (TARGET_ABSOLUTE_ABICALLS) |
6137 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
6138 | else | |
6139 | { | |
6140 | output_asm_insn ("%(.cpload\t%^%)", NULL); | |
6141 | /* Emit an R_MIPS_NONE relocation to tell the linker what the | |
6142 | target function is. Use a local GOT access when loading the | |
6143 | symbol, to cut down on the number of unnecessary GOT entries | |
6144 | for stubs that aren't needed. */ | |
6145 | output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol); | |
6146 | symbol = alias; | |
6147 | } | |
08d0963a RS |
6148 | } |
6149 | ||
e21d5757 | 6150 | /* Load the address of the MIPS16 function into $25. Do this first so |
6a68a258 RS |
6151 | that targets with coprocessor interlocks can use an MFC1 to fill the |
6152 | delay slot. */ | |
e21d5757 | 6153 | output_asm_insn ("la\t%^,%0", &symbol); |
e689b870 | 6154 | |
65239d20 | 6155 | /* Move the arguments from floating-point registers to general registers. */ |
38173d38 | 6156 | mips_output_args_xfer (crtl->args.info.fp_code, 'f'); |
e689b870 | 6157 | |
65239d20 | 6158 | /* Jump to the MIPS16 function. */ |
e21d5757 | 6159 | output_asm_insn ("jr\t%^", NULL); |
d8934cf1 | 6160 | |
e21d5757 | 6161 | if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS) |
08d0963a RS |
6162 | fprintf (asm_out_file, "\t.option\tpic2\n"); |
6163 | ||
b2b61607 | 6164 | mips_end_function_definition (stubname); |
e689b870 | 6165 | |
08d0963a RS |
6166 | /* If the linker needs to create a dynamic symbol for the target |
6167 | function, it will associate the symbol with the stub (which, | |
6168 | unlike the target function, follows the proper calling conventions). | |
6169 | It is therefore useful to have a local alias for the target function, | |
6170 | so that it can still be identified as MIPS16 code. As an optimization, | |
6171 | this symbol can also be used for indirect MIPS16 references from | |
6172 | within this file. */ | |
6173 | ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname); | |
6174 | ||
ab77a036 | 6175 | switch_to_section (function_section (current_function_decl)); |
e689b870 DU |
6176 | } |
6177 | ||
5f5fe6d9 RS |
6178 | /* The current function is a MIPS16 function that returns a value in an FPR. |
6179 | Copy the return value from its soft-float to its hard-float location. | |
6180 | libgcc2 has special non-MIPS16 helper functions for each case. */ | |
6181 | ||
6182 | static void | |
6183 | mips16_copy_fpr_return_value (void) | |
6184 | { | |
08d0963a RS |
6185 | rtx fn, insn, retval; |
6186 | tree return_type; | |
5f5fe6d9 | 6187 | enum machine_mode return_mode; |
08d0963a | 6188 | const char *name; |
5f5fe6d9 RS |
6189 | |
6190 | return_type = DECL_RESULT (current_function_decl); | |
6191 | return_mode = DECL_MODE (return_type); | |
6192 | ||
08d0963a RS |
6193 | name = ACONCAT (("__mips16_ret_", |
6194 | mips16_call_stub_mode_suffix (return_mode), | |
6195 | NULL)); | |
6196 | fn = mips16_stub_function (name); | |
6197 | ||
6198 | /* The function takes arguments in $2 (and possibly $3), so calls | |
6199 | to it cannot be lazily bound. */ | |
6200 | SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW; | |
6201 | ||
6202 | /* Model the call as something that takes the GPR return value as | |
6203 | argument and returns an "updated" value. */ | |
6204 | retval = gen_rtx_REG (return_mode, GP_RETURN); | |
6205 | insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn, | |
6206 | const0_rtx, NULL_RTX, false); | |
6207 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval); | |
5f5fe6d9 RS |
6208 | } |
6209 | ||
08d0963a | 6210 | /* Consider building a stub for a MIPS16 call to function *FN_PTR. |
65239d20 RS |
6211 | RETVAL is the location of the return value, or null if this is |
6212 | a "call" rather than a "call_value". ARGS_SIZE is the size of the | |
6213 | arguments and FP_CODE is the code built by mips_function_arg; | |
b53da244 | 6214 | see the comment before the fp_code field in CUMULATIVE_ARGS for details. |
d33289b2 | 6215 | |
08d0963a RS |
6216 | There are three alternatives: |
6217 | ||
6218 | - If a stub was needed, emit the call and return the call insn itself. | |
6219 | ||
6220 | - If we can avoid using a stub by redirecting the call, set *FN_PTR | |
6221 | to the new target and return null. | |
6222 | ||
6223 | - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR | |
6224 | unmodified. | |
f9e4a411 | 6225 | |
65239d20 RS |
6226 | A stub is needed for calls to functions that, in normal mode, |
6227 | receive arguments in FPRs or return values in FPRs. The stub | |
6228 | copies the arguments from their soft-float positions to their | |
6229 | hard-float positions, calls the real function, then copies the | |
6230 | return value from its hard-float position to its soft-float | |
6231 | position. | |
f9e4a411 | 6232 | |
08d0963a RS |
6233 | We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub. |
6234 | If *FN_PTR turns out to be to a non-MIPS16 function, the linker | |
6235 | automatically redirects the JAL to the stub, otherwise the JAL | |
6236 | continues to call FN directly. */ | |
65239d20 | 6237 | |
dbc90b65 | 6238 | static rtx |
08d0963a | 6239 | mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code) |
f9e4a411 | 6240 | { |
ab77a036 | 6241 | const char *fnname; |
65239d20 | 6242 | bool fp_ret_p; |
ab77a036 | 6243 | struct mips16_stub *l; |
08d0963a | 6244 | rtx insn, fn; |
f9e4a411 | 6245 | |
65239d20 | 6246 | /* We don't need to do anything if we aren't in MIPS16 mode, or if |
ab77a036 RS |
6247 | we were invoked with the -msoft-float option. */ |
6248 | if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI) | |
dbc90b65 | 6249 | return NULL_RTX; |
f9e4a411 | 6250 | |
65239d20 | 6251 | /* Figure out whether the value might come back in a floating-point |
ab77a036 | 6252 | register. */ |
65239d20 | 6253 | fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval)); |
f9e4a411 | 6254 | |
65239d20 RS |
6255 | /* We don't need to do anything if there were no floating-point |
6256 | arguments and the value will not be returned in a floating-point | |
ab77a036 | 6257 | register. */ |
65239d20 | 6258 | if (fp_code == 0 && !fp_ret_p) |
dbc90b65 | 6259 | return NULL_RTX; |
f9e4a411 | 6260 | |
ab77a036 | 6261 | /* We don't need to do anything if this is a call to a special |
65239d20 | 6262 | MIPS16 support function. */ |
08d0963a RS |
6263 | fn = *fn_ptr; |
6264 | if (mips16_stub_function_p (fn)) | |
dbc90b65 | 6265 | return NULL_RTX; |
f9e4a411 | 6266 | |
62835cee RS |
6267 | /* If we're calling a locally-defined MIPS16 function, we know that |
6268 | it will return values in both the "soft-float" and "hard-float" | |
6269 | registers. There is no need to use a stub to move the latter | |
6270 | to the former. */ | |
6271 | if (fp_code == 0 && mips16_local_function_p (fn)) | |
6272 | return NULL_RTX; | |
6273 | ||
ab77a036 RS |
6274 | /* This code will only work for o32 and o64 abis. The other ABI's |
6275 | require more sophisticated support. */ | |
6276 | gcc_assert (TARGET_OLDABI); | |
f9e4a411 | 6277 | |
65239d20 RS |
6278 | /* If we're calling via a function pointer, use one of the magic |
6279 | libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination. | |
6280 | Each stub expects the function address to arrive in register $2. */ | |
08d0963a RS |
6281 | if (GET_CODE (fn) != SYMBOL_REF |
6282 | || !call_insn_operand (fn, VOIDmode)) | |
f9e4a411 | 6283 | { |
ab77a036 | 6284 | char buf[30]; |
08d0963a RS |
6285 | rtx stub_fn, insn, addr; |
6286 | bool lazy_p; | |
6287 | ||
6288 | /* If this is a locally-defined and locally-binding function, | |
6289 | avoid the stub by calling the local alias directly. */ | |
6290 | if (mips16_local_function_p (fn)) | |
6291 | { | |
6292 | *fn_ptr = mips16_local_alias (fn); | |
6293 | return NULL_RTX; | |
6294 | } | |
f9e4a411 | 6295 | |
65239d20 RS |
6296 | /* Create a SYMBOL_REF for the libgcc.a function. */ |
6297 | if (fp_ret_p) | |
ab77a036 RS |
6298 | sprintf (buf, "__mips16_call_stub_%s_%d", |
6299 | mips16_call_stub_mode_suffix (GET_MODE (retval)), | |
6300 | fp_code); | |
f9e4a411 | 6301 | else |
65239d20 | 6302 | sprintf (buf, "__mips16_call_stub_%d", fp_code); |
08d0963a RS |
6303 | stub_fn = mips16_stub_function (buf); |
6304 | ||
6305 | /* The function uses $2 as an argument, so calls to it | |
6306 | cannot be lazily bound. */ | |
6307 | SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW; | |
f9e4a411 | 6308 | |
65239d20 | 6309 | /* Load the target function into $2. */ |
08d0963a RS |
6310 | addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); |
6311 | lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn); | |
f9e4a411 | 6312 | |
65239d20 | 6313 | /* Emit the call. */ |
08d0963a RS |
6314 | insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn, |
6315 | args_size, NULL_RTX, lazy_p); | |
f9e4a411 | 6316 | |
65239d20 | 6317 | /* Tell GCC that this call does indeed use the value of $2. */ |
08d0963a | 6318 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr); |
f9e4a411 | 6319 | |
65239d20 | 6320 | /* If we are handling a floating-point return value, we need to |
ab77a036 RS |
6321 | save $18 in the function prologue. Putting a note on the |
6322 | call will mean that df_regs_ever_live_p ($18) will be true if the | |
6323 | call is not eliminated, and we can check that in the prologue | |
6324 | code. */ | |
65239d20 | 6325 | if (fp_ret_p) |
ab77a036 RS |
6326 | CALL_INSN_FUNCTION_USAGE (insn) = |
6327 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6328 | gen_rtx_CLOBBER (VOIDmode, |
6329 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6330 | CALL_INSN_FUNCTION_USAGE (insn)); |
f9e4a411 | 6331 | |
dbc90b65 | 6332 | return insn; |
ab77a036 | 6333 | } |
f9e4a411 | 6334 | |
ab77a036 RS |
6335 | /* We know the function we are going to call. If we have already |
6336 | built a stub, we don't need to do anything further. */ | |
ab77a036 RS |
6337 | fnname = targetm.strip_name_encoding (XSTR (fn, 0)); |
6338 | for (l = mips16_stubs; l != NULL; l = l->next) | |
6339 | if (strcmp (l->name, fnname) == 0) | |
6340 | break; | |
d33289b2 | 6341 | |
ab77a036 | 6342 | if (l == NULL) |
f9e4a411 | 6343 | { |
65239d20 RS |
6344 | const char *separator; |
6345 | char *secname, *stubname; | |
6346 | tree stubid, stubdecl; | |
6347 | unsigned int f; | |
8d1d0dee | 6348 | |
65239d20 | 6349 | /* If the function does not return in FPRs, the special stub |
ab77a036 | 6350 | section is named |
65239d20 RS |
6351 | .mips16.call.FNNAME |
6352 | ||
6353 | If the function does return in FPRs, the stub section is named | |
ab77a036 | 6354 | .mips16.call.fp.FNNAME |
f9e4a411 | 6355 | |
65239d20 RS |
6356 | Build a decl for the stub. */ |
6357 | secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "", | |
6358 | fnname, NULL)); | |
6359 | stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "", | |
6360 | fnname, NULL)); | |
ab77a036 | 6361 | stubid = get_identifier (stubname); |
4c4bde29 AH |
6362 | stubdecl = build_decl (BUILTINS_LOCATION, |
6363 | FUNCTION_DECL, stubid, | |
b861891b NF |
6364 | build_function_type_list (void_type_node, |
6365 | NULL_TREE)); | |
ab77a036 | 6366 | DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); |
4c4bde29 AH |
6367 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6368 | RESULT_DECL, NULL_TREE, | |
65239d20 | 6369 | void_type_node); |
9a6dfb47 | 6370 | |
65239d20 | 6371 | /* Output a comment. */ |
ab77a036 | 6372 | fprintf (asm_out_file, "\t# Stub function to call %s%s (", |
65239d20 | 6373 | (fp_ret_p |
ab77a036 RS |
6374 | ? (GET_MODE (retval) == SFmode ? "float " : "double ") |
6375 | : ""), | |
6376 | fnname); | |
65239d20 | 6377 | separator = ""; |
ab77a036 RS |
6378 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
6379 | { | |
65239d20 | 6380 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6381 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6382 | separator = ", "; |
ab77a036 RS |
6383 | } |
6384 | fprintf (asm_out_file, ")\n"); | |
f9e4a411 | 6385 | |
b2b61607 | 6386 | /* Start the function definition. */ |
ab77a036 | 6387 | assemble_start_function (stubdecl, stubname); |
b2b61607 | 6388 | mips_start_function_definition (stubname, false); |
8ce4afa3 | 6389 | |
5adeb246 RS |
6390 | if (fp_ret_p) |
6391 | { | |
6392 | fprintf (asm_out_file, "\t.cfi_startproc\n"); | |
6393 | ||
6394 | /* Create a fake CFA 4 bytes below the stack pointer. | |
6395 | This works around unwinders (like libgcc's) that expect | |
6396 | the CFA for non-signal frames to be unique. */ | |
6397 | fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n"); | |
6398 | ||
6399 | /* "Save" $sp in itself so we don't use the fake CFA. | |
6400 | This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */ | |
6401 | fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n"); | |
6402 | } | |
6403 | else | |
ab77a036 | 6404 | { |
e21d5757 | 6405 | /* Load the address of the MIPS16 function into $25. Do this |
6a68a258 RS |
6406 | first so that targets with coprocessor interlocks can use |
6407 | an MFC1 to fill the delay slot. */ | |
08d0963a RS |
6408 | if (TARGET_EXPLICIT_RELOCS) |
6409 | { | |
6410 | output_asm_insn ("lui\t%^,%%hi(%0)", &fn); | |
6411 | output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn); | |
6412 | } | |
6413 | else | |
6414 | output_asm_insn ("la\t%^,%0", &fn); | |
6a68a258 RS |
6415 | } |
6416 | ||
65239d20 RS |
6417 | /* Move the arguments from general registers to floating-point |
6418 | registers. */ | |
6a68a258 RS |
6419 | mips_output_args_xfer (fp_code, 't'); |
6420 | ||
5adeb246 | 6421 | if (fp_ret_p) |
ab77a036 | 6422 | { |
65239d20 RS |
6423 | /* Save the return address in $18 and call the non-MIPS16 function. |
6424 | The stub's caller knows that $18 might be clobbered, even though | |
6425 | $18 is usually a call-saved register. */ | |
ab77a036 | 6426 | fprintf (asm_out_file, "\tmove\t%s,%s\n", |
293593b1 | 6427 | reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]); |
b53da244 | 6428 | output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn); |
5adeb246 | 6429 | fprintf (asm_out_file, "\t.cfi_register 31,18\n"); |
65239d20 RS |
6430 | |
6431 | /* Move the result from floating-point registers to | |
6432 | general registers. */ | |
ab77a036 RS |
6433 | switch (GET_MODE (retval)) |
6434 | { | |
6435 | case SCmode: | |
93f63c68 RS |
6436 | mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN, |
6437 | TARGET_BIG_ENDIAN | |
6438 | ? FP_REG_FIRST + MAX_FPRS_PER_FMT | |
6439 | : FP_REG_FIRST); | |
6440 | mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN, | |
6441 | TARGET_LITTLE_ENDIAN | |
6442 | ? FP_REG_FIRST + MAX_FPRS_PER_FMT | |
6443 | : FP_REG_FIRST); | |
ab77a036 RS |
6444 | if (GET_MODE (retval) == SCmode && TARGET_64BIT) |
6445 | { | |
6446 | /* On 64-bit targets, complex floats are returned in | |
6447 | a single GPR, such that "sd" on a suitably-aligned | |
6448 | target would store the value correctly. */ | |
93f63c68 RS |
6449 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", |
6450 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN], | |
6451 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); | |
ab77a036 | 6452 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", |
5b372d33 RS |
6453 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN], |
6454 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]); | |
93f63c68 RS |
6455 | fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n", |
6456 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN], | |
6457 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); | |
ab77a036 | 6458 | fprintf (asm_out_file, "\tor\t%s,%s,%s\n", |
5b372d33 RS |
6459 | reg_names[GP_RETURN], |
6460 | reg_names[GP_RETURN], | |
6461 | reg_names[GP_RETURN + 1]); | |
ab77a036 RS |
6462 | } |
6463 | break; | |
f9e4a411 | 6464 | |
93f63c68 RS |
6465 | case SFmode: |
6466 | mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST); | |
6467 | break; | |
6468 | ||
ab77a036 | 6469 | case DCmode: |
5b372d33 RS |
6470 | mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD), |
6471 | FP_REG_FIRST + MAX_FPRS_PER_FMT); | |
ab77a036 RS |
6472 | /* Fall though. */ |
6473 | case DFmode: | |
6474 | case V2SFmode: | |
5b372d33 | 6475 | mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST); |
ab77a036 | 6476 | break; |
9a6dfb47 | 6477 | |
ab77a036 RS |
6478 | default: |
6479 | gcc_unreachable (); | |
6480 | } | |
65239d20 | 6481 | fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]); |
5adeb246 RS |
6482 | fprintf (asm_out_file, "\t.cfi_endproc\n"); |
6483 | } | |
6484 | else | |
6485 | { | |
6486 | /* Jump to the previously-loaded address. */ | |
6487 | output_asm_insn ("jr\t%^", NULL); | |
ab77a036 | 6488 | } |
9a6dfb47 | 6489 | |
ab77a036 RS |
6490 | #ifdef ASM_DECLARE_FUNCTION_SIZE |
6491 | ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); | |
6492 | #endif | |
9a6dfb47 | 6493 | |
b2b61607 | 6494 | mips_end_function_definition (stubname); |
9a6dfb47 | 6495 | |
ab77a036 | 6496 | /* Record this stub. */ |
65239d20 | 6497 | l = XNEW (struct mips16_stub); |
ab77a036 | 6498 | l->name = xstrdup (fnname); |
65239d20 | 6499 | l->fp_ret_p = fp_ret_p; |
ab77a036 RS |
6500 | l->next = mips16_stubs; |
6501 | mips16_stubs = l; | |
6502 | } | |
9a6dfb47 | 6503 | |
65239d20 | 6504 | /* If we expect a floating-point return value, but we've built a |
ab77a036 | 6505 | stub which does not expect one, then we're in trouble. We can't |
65239d20 | 6506 | use the existing stub, because it won't handle the floating-point |
ab77a036 RS |
6507 | value. We can't build a new stub, because the linker won't know |
6508 | which stub to use for the various calls in this object file. | |
6509 | Fortunately, this case is illegal, since it means that a function | |
6510 | was declared in two different ways in a single compilation. */ | |
65239d20 | 6511 | if (fp_ret_p && !l->fp_ret_p) |
ab77a036 | 6512 | error ("cannot handle inconsistent calls to %qs", fnname); |
9a6dfb47 | 6513 | |
ab77a036 | 6514 | if (retval == NULL_RTX) |
65239d20 | 6515 | insn = gen_call_internal_direct (fn, args_size); |
ab77a036 | 6516 | else |
65239d20 | 6517 | insn = gen_call_value_internal_direct (retval, fn, args_size); |
08d0963a | 6518 | insn = mips_emit_call_insn (insn, fn, fn, false); |
9a6dfb47 | 6519 | |
65239d20 RS |
6520 | /* If we are calling a stub which handles a floating-point return |
6521 | value, we need to arrange to save $18 in the prologue. We do this | |
6522 | by marking the function call as using the register. The prologue | |
6523 | will later see that it is used, and emit code to save it. */ | |
6524 | if (fp_ret_p) | |
ab77a036 RS |
6525 | CALL_INSN_FUNCTION_USAGE (insn) = |
6526 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6527 | gen_rtx_CLOBBER (VOIDmode, |
6528 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6529 | CALL_INSN_FUNCTION_USAGE (insn)); |
9a6dfb47 | 6530 | |
dbc90b65 | 6531 | return insn; |
9a6dfb47 | 6532 | } |
ab77a036 | 6533 | \f |
08d0963a RS |
6534 | /* Expand a call of type TYPE. RESULT is where the result will go (null |
6535 | for "call"s and "sibcall"s), ADDR is the address of the function, | |
6536 | ARGS_SIZE is the size of the arguments and AUX is the value passed | |
6537 | to us by mips_function_arg. LAZY_P is true if this call already | |
6538 | involves a lazily-bound function address (such as when calling | |
6539 | functions through a MIPS16 hard-float stub). | |
f9e4a411 | 6540 | |
dbc90b65 RS |
6541 | Return the call itself. */ |
6542 | ||
6543 | rtx | |
08d0963a RS |
6544 | mips_expand_call (enum mips_call_type type, rtx result, rtx addr, |
6545 | rtx args_size, rtx aux, bool lazy_p) | |
f9e4a411 | 6546 | { |
ab77a036 | 6547 | rtx orig_addr, pattern, insn; |
08d0963a | 6548 | int fp_code; |
d522e7a2 | 6549 | |
08d0963a RS |
6550 | fp_code = aux == 0 ? 0 : (int) GET_MODE (aux); |
6551 | insn = mips16_build_call_stub (result, &addr, args_size, fp_code); | |
6552 | if (insn) | |
6553 | { | |
6554 | gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL); | |
6555 | return insn; | |
6556 | } | |
6557 | ; | |
ab77a036 | 6558 | orig_addr = addr; |
ab77a036 | 6559 | if (!call_insn_operand (addr, VOIDmode)) |
d522e7a2 | 6560 | { |
08d0963a RS |
6561 | if (type == MIPS_CALL_EPILOGUE) |
6562 | addr = MIPS_EPILOGUE_TEMP (Pmode); | |
6563 | else | |
6564 | addr = gen_reg_rtx (Pmode); | |
6565 | lazy_p |= mips_load_call_address (type, addr, orig_addr); | |
ab77a036 | 6566 | } |
d522e7a2 | 6567 | |
08d0963a | 6568 | if (result == 0) |
65239d20 | 6569 | { |
08d0963a | 6570 | rtx (*fn) (rtx, rtx); |
d522e7a2 | 6571 | |
0c433c31 | 6572 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6573 | fn = gen_sibcall_internal; |
6574 | else | |
6575 | fn = gen_call_internal; | |
6576 | ||
6577 | pattern = fn (addr, args_size); | |
6578 | } | |
ab77a036 RS |
6579 | else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) |
6580 | { | |
fd0d4c1f | 6581 | /* Handle return values created by mips_return_fpr_pair. */ |
08d0963a | 6582 | rtx (*fn) (rtx, rtx, rtx, rtx); |
ab77a036 | 6583 | rtx reg1, reg2; |
d522e7a2 | 6584 | |
0c433c31 | 6585 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6586 | fn = gen_sibcall_value_multiple_internal; |
6587 | else | |
6588 | fn = gen_call_value_multiple_internal; | |
6589 | ||
ab77a036 RS |
6590 | reg1 = XEXP (XVECEXP (result, 0, 0), 0); |
6591 | reg2 = XEXP (XVECEXP (result, 0, 1), 0); | |
08d0963a | 6592 | pattern = fn (reg1, addr, args_size, reg2); |
ab77a036 RS |
6593 | } |
6594 | else | |
fd0d4c1f | 6595 | { |
08d0963a RS |
6596 | rtx (*fn) (rtx, rtx, rtx); |
6597 | ||
0c433c31 | 6598 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6599 | fn = gen_sibcall_value_internal; |
6600 | else | |
6601 | fn = gen_call_value_internal; | |
6602 | ||
fd0d4c1f RS |
6603 | /* Handle return values created by mips_return_fpr_single. */ |
6604 | if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) | |
6605 | result = XEXP (XVECEXP (result, 0, 0), 0); | |
08d0963a | 6606 | pattern = fn (result, addr, args_size); |
fd0d4c1f | 6607 | } |
d522e7a2 | 6608 | |
08d0963a RS |
6609 | return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p); |
6610 | } | |
6611 | ||
6612 | /* Split call instruction INSN into a $gp-clobbering call and | |
6613 | (where necessary) an instruction to restore $gp from its save slot. | |
6614 | CALL_PATTERN is the pattern of the new call. */ | |
6615 | ||
6616 | void | |
6617 | mips_split_call (rtx insn, rtx call_pattern) | |
6618 | { | |
82220036 | 6619 | emit_call_insn (call_pattern); |
08d0963a RS |
6620 | if (!find_reg_note (insn, REG_NORETURN, 0)) |
6621 | /* Pick a temporary register that is suitable for both MIPS16 and | |
6622 | non-MIPS16 code. $4 and $5 are used for returning complex double | |
6623 | values in soft-float code, so $6 is the first suitable candidate. */ | |
0c433c31 | 6624 | mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2)); |
d522e7a2 | 6625 | } |
a27fb29b | 6626 | |
ab77a036 RS |
6627 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ |
6628 | ||
6629 | static bool | |
6630 | mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) | |
cee98a59 | 6631 | { |
ab77a036 RS |
6632 | if (!TARGET_SIBCALLS) |
6633 | return false; | |
cee98a59 | 6634 | |
e19da24c CF |
6635 | /* Interrupt handlers need special epilogue code and therefore can't |
6636 | use sibcalls. */ | |
6637 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
6638 | return false; | |
6639 | ||
ab77a036 RS |
6640 | /* We can't do a sibcall if the called function is a MIPS16 function |
6641 | because there is no direct "jx" instruction equivalent to "jalx" to | |
9be10a79 RS |
6642 | switch the ISA mode. We only care about cases where the sibling |
6643 | and normal calls would both be direct. */ | |
cf900097 RS |
6644 | if (decl |
6645 | && mips_use_mips16_mode_p (decl) | |
9be10a79 | 6646 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)) |
ab77a036 | 6647 | return false; |
d1138d8e | 6648 | |
0b6e1647 RS |
6649 | /* When -minterlink-mips16 is in effect, assume that non-locally-binding |
6650 | functions could be MIPS16 ones unless an attribute explicitly tells | |
6651 | us otherwise. */ | |
ab77a036 RS |
6652 | if (TARGET_INTERLINK_MIPS16 |
6653 | && decl | |
dd748704 | 6654 | && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl)) |
ab77a036 RS |
6655 | && !mips_nomips16_decl_p (decl) |
6656 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)) | |
6657 | return false; | |
cee98a59 | 6658 | |
ab77a036 RS |
6659 | /* Otherwise OK. */ |
6660 | return true; | |
6661 | } | |
6662 | \f | |
6663 | /* Emit code to move general operand SRC into condition-code | |
65239d20 | 6664 | register DEST given that SCRATCH is a scratch TFmode FPR. |
ab77a036 | 6665 | The sequence is: |
147255d8 | 6666 | |
ab77a036 RS |
6667 | FP1 = SRC |
6668 | FP2 = 0.0f | |
6669 | DEST = FP2 < FP1 | |
5ae590d7 | 6670 | |
65239d20 | 6671 | where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */ |
f5963e61 | 6672 | |
ab77a036 | 6673 | void |
65239d20 | 6674 | mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch) |
ab77a036 RS |
6675 | { |
6676 | rtx fp1, fp2; | |
ade6c319 | 6677 | |
ab77a036 RS |
6678 | /* Change the source to SFmode. */ |
6679 | if (MEM_P (src)) | |
6680 | src = adjust_address (src, SFmode, 0); | |
6681 | else if (REG_P (src) || GET_CODE (src) == SUBREG) | |
6682 | src = gen_rtx_REG (SFmode, true_regnum (src)); | |
1bd9166e | 6683 | |
ab77a036 RS |
6684 | fp1 = gen_rtx_REG (SFmode, REGNO (scratch)); |
6685 | fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT); | |
f1d5187e | 6686 | |
ab77a036 RS |
6687 | mips_emit_move (copy_rtx (fp1), src); |
6688 | mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode)); | |
6689 | emit_insn (gen_slt_sf (dest, fp2, fp1)); | |
6690 | } | |
6691 | \f | |
0d8f5d62 RS |
6692 | /* Implement MOVE_BY_PIECES_P. */ |
6693 | ||
6694 | bool | |
6695 | mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) | |
6696 | { | |
6697 | if (HAVE_movmemsi) | |
6698 | { | |
6699 | /* movmemsi is meant to generate code that is at least as good as | |
6700 | move_by_pieces. However, movmemsi effectively uses a by-pieces | |
6701 | implementation both for moves smaller than a word and for | |
6702 | word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT | |
6703 | bytes. We should allow the tree-level optimisers to do such | |
6704 | moves by pieces, as it often exposes other optimization | |
6705 | opportunities. We might as well continue to use movmemsi at | |
6706 | the rtl level though, as it produces better code when | |
6707 | scheduling is disabled (such as at -O). */ | |
6708 | if (currently_expanding_to_rtl) | |
6709 | return false; | |
6710 | if (align < BITS_PER_WORD) | |
6711 | return size < UNITS_PER_WORD; | |
6712 | return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT; | |
6713 | } | |
6714 | /* The default value. If this becomes a target hook, we should | |
6715 | call the default definition instead. */ | |
6716 | return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1) | |
6717 | < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ())); | |
6718 | } | |
6719 | ||
6720 | /* Implement STORE_BY_PIECES_P. */ | |
6721 | ||
6722 | bool | |
6723 | mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) | |
6724 | { | |
6725 | /* Storing by pieces involves moving constants into registers | |
6726 | of size MIN (ALIGN, BITS_PER_WORD), then storing them. | |
6727 | We need to decide whether it is cheaper to load the address of | |
6728 | constant data into a register and use a block move instead. */ | |
6729 | ||
6730 | /* If the data is only byte aligned, then: | |
6731 | ||
6732 | (a1) A block move of less than 4 bytes would involve three 3 LBs and | |
6733 | 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs | |
6734 | instead. | |
6735 | ||
6736 | (a2) A block move of 4 bytes from aligned source data can use an | |
6737 | LW/SWL/SWR sequence. This is often better than the 4 LIs and | |
6738 | 4 SBs that we would generate when storing by pieces. */ | |
6739 | if (align <= BITS_PER_UNIT) | |
6740 | return size < 4; | |
6741 | ||
6742 | /* If the data is 2-byte aligned, then: | |
6743 | ||
6744 | (b1) A block move of less than 4 bytes would use a combination of LBs, | |
6745 | LHs, SBs and SHs. We get better code by using single-instruction | |
6746 | LIs, SBs and SHs instead. | |
6747 | ||
6748 | (b2) A block move of 4 bytes from aligned source data would again use | |
6749 | an LW/SWL/SWR sequence. In most cases, loading the address of | |
6750 | the source data would require at least one extra instruction. | |
6751 | It is often more efficient to use 2 single-instruction LIs and | |
6752 | 2 SHs instead. | |
6753 | ||
6754 | (b3) A block move of up to 3 additional bytes would be like (b1). | |
6755 | ||
6756 | (b4) A block move of 8 bytes from aligned source data can use two | |
6757 | LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both | |
6758 | sequences are better than the 4 LIs and 4 SHs that we'd generate | |
6759 | when storing by pieces. | |
6760 | ||
6761 | The reasoning for higher alignments is similar: | |
6762 | ||
6763 | (c1) A block move of less than 4 bytes would be the same as (b1). | |
6764 | ||
6765 | (c2) A block move of 4 bytes would use an LW/SW sequence. Again, | |
6766 | loading the address of the source data would typically require | |
6767 | at least one extra instruction. It is generally better to use | |
6768 | LUI/ORI/SW instead. | |
6769 | ||
6770 | (c3) A block move of up to 3 additional bytes would be like (b1). | |
6771 | ||
6772 | (c4) A block move of 8 bytes can use two LW/SW sequences or a single | |
6773 | LD/SD sequence, and in these cases we've traditionally preferred | |
6774 | the memory copy over the more bulky constant moves. */ | |
6775 | return size < 8; | |
6776 | } | |
6777 | ||
ab77a036 RS |
6778 | /* Emit straight-line code to move LENGTH bytes from SRC to DEST. |
6779 | Assume that the areas do not overlap. */ | |
7dac2f89 | 6780 | |
ab77a036 RS |
6781 | static void |
6782 | mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) | |
6783 | { | |
6784 | HOST_WIDE_INT offset, delta; | |
6785 | unsigned HOST_WIDE_INT bits; | |
6786 | int i; | |
6787 | enum machine_mode mode; | |
6788 | rtx *regs; | |
6789 | ||
6790 | /* Work out how many bits to move at a time. If both operands have | |
6791 | half-word alignment, it is usually better to move in half words. | |
6792 | For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr | |
6793 | and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr. | |
6794 | Otherwise move word-sized chunks. */ | |
6795 | if (MEM_ALIGN (src) == BITS_PER_WORD / 2 | |
6796 | && MEM_ALIGN (dest) == BITS_PER_WORD / 2) | |
6797 | bits = BITS_PER_WORD / 2; | |
d81ecf52 | 6798 | else |
ab77a036 | 6799 | bits = BITS_PER_WORD; |
c1bd2d66 | 6800 | |
ab77a036 RS |
6801 | mode = mode_for_size (bits, MODE_INT, 0); |
6802 | delta = bits / BITS_PER_UNIT; | |
a05bea76 | 6803 | |
ab77a036 | 6804 | /* Allocate a buffer for the temporary registers. */ |
5ead67f6 | 6805 | regs = XALLOCAVEC (rtx, length / delta); |
ab77a036 RS |
6806 | |
6807 | /* Load as many BITS-sized chunks as possible. Use a normal load if | |
6808 | the source has enough alignment, otherwise use left/right pairs. */ | |
6809 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
cee98a59 | 6810 | { |
ab77a036 RS |
6811 | regs[i] = gen_reg_rtx (mode); |
6812 | if (MEM_ALIGN (src) >= bits) | |
6813 | mips_emit_move (regs[i], adjust_address (src, mode, offset)); | |
7dac2f89 | 6814 | else |
ab77a036 RS |
6815 | { |
6816 | rtx part = adjust_address (src, BLKmode, offset); | |
65239d20 | 6817 | if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0)) |
ab77a036 RS |
6818 | gcc_unreachable (); |
6819 | } | |
a27fb29b | 6820 | } |
cee98a59 | 6821 | |
ab77a036 RS |
6822 | /* Copy the chunks to the destination. */ |
6823 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
6824 | if (MEM_ALIGN (dest) >= bits) | |
6825 | mips_emit_move (adjust_address (dest, mode, offset), regs[i]); | |
6826 | else | |
6827 | { | |
6828 | rtx part = adjust_address (dest, BLKmode, offset); | |
65239d20 | 6829 | if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0)) |
ab77a036 RS |
6830 | gcc_unreachable (); |
6831 | } | |
6832 | ||
6833 | /* Mop up any left-over bytes. */ | |
6834 | if (offset < length) | |
a27fb29b | 6835 | { |
ab77a036 RS |
6836 | src = adjust_address (src, BLKmode, offset); |
6837 | dest = adjust_address (dest, BLKmode, offset); | |
6838 | move_by_pieces (dest, src, length - offset, | |
6839 | MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); | |
cee98a59 | 6840 | } |
ab77a036 | 6841 | } |
f8151871 | 6842 | |
ab77a036 RS |
6843 | /* Helper function for doing a loop-based block operation on memory |
6844 | reference MEM. Each iteration of the loop will operate on LENGTH | |
6845 | bytes of MEM. | |
cee98a59 | 6846 | |
ab77a036 RS |
6847 | Create a new base register for use within the loop and point it to |
6848 | the start of MEM. Create a new memory reference that uses this | |
6849 | register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ | |
33563487 | 6850 | |
ab77a036 RS |
6851 | static void |
6852 | mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, | |
6853 | rtx *loop_reg, rtx *loop_mem) | |
6854 | { | |
6855 | *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); | |
af34e51e | 6856 | |
ab77a036 RS |
6857 | /* Although the new mem does not refer to a known location, |
6858 | it does keep up to LENGTH bytes of alignment. */ | |
6859 | *loop_mem = change_address (mem, BLKmode, *loop_reg); | |
6860 | set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); | |
6861 | } | |
142ee136 | 6862 | |
a1c6b246 RS |
6863 | /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER |
6864 | bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that | |
6865 | the memory regions do not overlap. */ | |
d9870b7e | 6866 | |
ab77a036 | 6867 | static void |
a1c6b246 RS |
6868 | mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, |
6869 | HOST_WIDE_INT bytes_per_iter) | |
ab77a036 | 6870 | { |
f90b7a5a | 6871 | rtx label, src_reg, dest_reg, final_src, test; |
ab77a036 | 6872 | HOST_WIDE_INT leftover; |
8cb6400c | 6873 | |
a1c6b246 | 6874 | leftover = length % bytes_per_iter; |
ab77a036 | 6875 | length -= leftover; |
dc884a86 | 6876 | |
ab77a036 | 6877 | /* Create registers and memory references for use within the loop. */ |
a1c6b246 RS |
6878 | mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); |
6879 | mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); | |
cfa31150 | 6880 | |
ab77a036 RS |
6881 | /* Calculate the value that SRC_REG should have after the last iteration |
6882 | of the loop. */ | |
6883 | final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), | |
6884 | 0, 0, OPTAB_WIDEN); | |
6885 | ||
6886 | /* Emit the start of the loop. */ | |
6887 | label = gen_label_rtx (); | |
6888 | emit_label (label); | |
6889 | ||
6890 | /* Emit the loop body. */ | |
a1c6b246 | 6891 | mips_block_move_straight (dest, src, bytes_per_iter); |
ab77a036 RS |
6892 | |
6893 | /* Move on to the next block. */ | |
a1c6b246 RS |
6894 | mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter)); |
6895 | mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter)); | |
ab77a036 RS |
6896 | |
6897 | /* Emit the loop condition. */ | |
f90b7a5a | 6898 | test = gen_rtx_NE (VOIDmode, src_reg, final_src); |
ab77a036 | 6899 | if (Pmode == DImode) |
f90b7a5a | 6900 | emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); |
ab77a036 | 6901 | else |
f90b7a5a | 6902 | emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); |
ab77a036 RS |
6903 | |
6904 | /* Mop up any left-over bytes. */ | |
6905 | if (leftover) | |
6906 | mips_block_move_straight (dest, src, leftover); | |
6907 | } | |
6908 | ||
65239d20 RS |
6909 | /* Expand a movmemsi instruction, which copies LENGTH bytes from |
6910 | memory reference SRC to memory reference DEST. */ | |
ab77a036 RS |
6911 | |
6912 | bool | |
6913 | mips_expand_block_move (rtx dest, rtx src, rtx length) | |
6914 | { | |
47ac44d6 | 6915 | if (CONST_INT_P (length)) |
a318179e | 6916 | { |
a1c6b246 | 6917 | if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT) |
a318179e | 6918 | { |
ab77a036 RS |
6919 | mips_block_move_straight (dest, src, INTVAL (length)); |
6920 | return true; | |
a318179e | 6921 | } |
ab77a036 | 6922 | else if (optimize) |
a318179e | 6923 | { |
a1c6b246 RS |
6924 | mips_block_move_loop (dest, src, INTVAL (length), |
6925 | MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); | |
ab77a036 | 6926 | return true; |
a318179e RS |
6927 | } |
6928 | } | |
ab77a036 RS |
6929 | return false; |
6930 | } | |
6931 | \f | |
ab77a036 | 6932 | /* Expand a loop of synci insns for the address range [BEGIN, END). */ |
cafe096b | 6933 | |
ab77a036 RS |
6934 | void |
6935 | mips_expand_synci_loop (rtx begin, rtx end) | |
6936 | { | |
d48a3196 CF |
6937 | rtx inc, label, end_label, cmp_result, mask, length; |
6938 | ||
6939 | /* Create end_label. */ | |
6940 | end_label = gen_label_rtx (); | |
6941 | ||
6942 | /* Check if begin equals end. */ | |
6943 | cmp_result = gen_rtx_EQ (VOIDmode, begin, end); | |
6944 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
06a4ab70 | 6945 | |
65239d20 | 6946 | /* Load INC with the cache line size (rdhwr INC,$1). */ |
9d50ba21 | 6947 | inc = gen_reg_rtx (Pmode); |
81a478c8 | 6948 | emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc))); |
06a4ab70 | 6949 | |
d48a3196 CF |
6950 | /* Check if inc is 0. */ |
6951 | cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx); | |
6952 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
6953 | ||
6954 | /* Calculate mask. */ | |
6955 | mask = mips_force_unary (Pmode, NEG, inc); | |
6956 | ||
6957 | /* Mask out begin by mask. */ | |
6958 | begin = mips_force_binary (Pmode, AND, begin, mask); | |
6959 | ||
6960 | /* Calculate length. */ | |
6961 | length = mips_force_binary (Pmode, MINUS, end, begin); | |
6962 | ||
ab77a036 RS |
6963 | /* Loop back to here. */ |
6964 | label = gen_label_rtx (); | |
6965 | emit_label (label); | |
06a4ab70 | 6966 | |
ab77a036 | 6967 | emit_insn (gen_synci (begin)); |
06a4ab70 | 6968 | |
d48a3196 CF |
6969 | /* Update length. */ |
6970 | mips_emit_binary (MINUS, length, length, inc); | |
32041385 | 6971 | |
d48a3196 | 6972 | /* Update begin. */ |
ab77a036 | 6973 | mips_emit_binary (PLUS, begin, begin, inc); |
cee98a59 | 6974 | |
d48a3196 CF |
6975 | /* Check if length is greater than 0. */ |
6976 | cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx); | |
ab77a036 | 6977 | emit_jump_insn (gen_condjump (cmp_result, label)); |
d48a3196 CF |
6978 | |
6979 | emit_label (end_label); | |
ab77a036 RS |
6980 | } |
6981 | \f | |
06d19617 DD |
6982 | /* Expand a QI or HI mode atomic memory operation. |
6983 | ||
6984 | GENERATOR contains a pointer to the gen_* function that generates | |
6985 | the SI mode underlying atomic operation using masks that we | |
6986 | calculate. | |
6987 | ||
6988 | RESULT is the return register for the operation. Its value is NULL | |
6989 | if unused. | |
6990 | ||
6991 | MEM is the location of the atomic access. | |
6992 | ||
6993 | OLDVAL is the first operand for the operation. | |
6994 | ||
6995 | NEWVAL is the optional second operand for the operation. Its value | |
6996 | is NULL if unused. */ | |
49bce30a RS |
6997 | |
6998 | void | |
06d19617 DD |
6999 | mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator, |
7000 | rtx result, rtx mem, rtx oldval, rtx newval) | |
49bce30a RS |
7001 | { |
7002 | rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask; | |
06d19617 DD |
7003 | rtx unshifted_mask_reg, mask, inverted_mask, si_op; |
7004 | rtx res = NULL; | |
977502ff DD |
7005 | enum machine_mode mode; |
7006 | ||
7007 | mode = GET_MODE (mem); | |
49bce30a RS |
7008 | |
7009 | /* Compute the address of the containing SImode value. */ | |
7010 | orig_addr = force_reg (Pmode, XEXP (mem, 0)); | |
7011 | memsi_addr = mips_force_binary (Pmode, AND, orig_addr, | |
7012 | force_reg (Pmode, GEN_INT (-4))); | |
7013 | ||
7014 | /* Create a memory reference for it. */ | |
7015 | memsi = gen_rtx_MEM (SImode, memsi_addr); | |
7016 | set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); | |
7017 | MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); | |
7018 | ||
7019 | /* Work out the byte offset of the QImode or HImode value, | |
7020 | counting from the least significant byte. */ | |
7021 | shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3)); | |
7022 | if (TARGET_BIG_ENDIAN) | |
977502ff | 7023 | mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2)); |
49bce30a RS |
7024 | |
7025 | /* Multiply by eight to convert the shift value from bytes to bits. */ | |
7026 | mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3)); | |
7027 | ||
7028 | /* Make the final shift an SImode value, so that it can be used in | |
7029 | SImode operations. */ | |
7030 | shiftsi = force_reg (SImode, gen_lowpart (SImode, shift)); | |
7031 | ||
7032 | /* Set MASK to an inclusive mask of the QImode or HImode value. */ | |
977502ff DD |
7033 | unshifted_mask = GEN_INT (GET_MODE_MASK (mode)); |
7034 | unshifted_mask_reg = force_reg (SImode, unshifted_mask); | |
7035 | mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi); | |
49bce30a RS |
7036 | |
7037 | /* Compute the equivalent exclusive mask. */ | |
7038 | inverted_mask = gen_reg_rtx (SImode); | |
7039 | emit_insn (gen_rtx_SET (VOIDmode, inverted_mask, | |
7040 | gen_rtx_NOT (SImode, mask))); | |
7041 | ||
7042 | /* Shift the old value into place. */ | |
977502ff DD |
7043 | if (oldval != const0_rtx) |
7044 | { | |
7045 | oldval = convert_modes (SImode, mode, oldval, true); | |
7046 | oldval = force_reg (SImode, oldval); | |
7047 | oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi); | |
7048 | } | |
49bce30a RS |
7049 | |
7050 | /* Do the same for the new value. */ | |
06d19617 | 7051 | if (newval && newval != const0_rtx) |
977502ff DD |
7052 | { |
7053 | newval = convert_modes (SImode, mode, newval, true); | |
7054 | newval = force_reg (SImode, newval); | |
7055 | newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi); | |
7056 | } | |
49bce30a RS |
7057 | |
7058 | /* Do the SImode atomic access. */ | |
06d19617 DD |
7059 | if (result) |
7060 | res = gen_reg_rtx (SImode); | |
7061 | if (newval) | |
7062 | si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval); | |
7063 | else if (result) | |
7064 | si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval); | |
7065 | else | |
7066 | si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval); | |
7067 | ||
7068 | emit_insn (si_op); | |
7069 | ||
7070 | if (result) | |
7071 | { | |
7072 | /* Shift and convert the result. */ | |
7073 | mips_emit_binary (AND, res, res, mask); | |
7074 | mips_emit_binary (LSHIFTRT, res, res, shiftsi); | |
7075 | mips_emit_move (result, gen_lowpart (GET_MODE (result), res)); | |
7076 | } | |
49bce30a RS |
7077 | } |
7078 | ||
ab77a036 RS |
7079 | /* Return true if it is possible to use left/right accesses for a |
7080 | bitfield of WIDTH bits starting BITPOS bits into *OP. When | |
7081 | returning true, update *OP, *LEFT and *RIGHT as follows: | |
cee98a59 | 7082 | |
ab77a036 | 7083 | *OP is a BLKmode reference to the whole field. |
cee98a59 | 7084 | |
ab77a036 RS |
7085 | *LEFT is a QImode reference to the first byte if big endian or |
7086 | the last byte if little endian. This address can be used in the | |
65239d20 | 7087 | left-side instructions (LWL, SWL, LDL, SDL). |
cee98a59 | 7088 | |
ab77a036 RS |
7089 | *RIGHT is a QImode reference to the opposite end of the field and |
7090 | can be used in the patterning right-side instruction. */ | |
cee98a59 | 7091 | |
ab77a036 | 7092 | static bool |
65239d20 | 7093 | mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos, |
ab77a036 RS |
7094 | rtx *left, rtx *right) |
7095 | { | |
7096 | rtx first, last; | |
77d4f3a4 | 7097 | |
ab77a036 RS |
7098 | /* Check that the operand really is a MEM. Not all the extv and |
7099 | extzv predicates are checked. */ | |
7100 | if (!MEM_P (*op)) | |
7101 | return false; | |
cee98a59 | 7102 | |
ab77a036 RS |
7103 | /* Check that the size is valid. */ |
7104 | if (width != 32 && (!TARGET_64BIT || width != 64)) | |
7105 | return false; | |
cee98a59 | 7106 | |
ab77a036 RS |
7107 | /* We can only access byte-aligned values. Since we are always passed |
7108 | a reference to the first byte of the field, it is not necessary to | |
7109 | do anything with BITPOS after this check. */ | |
7110 | if (bitpos % BITS_PER_UNIT != 0) | |
7111 | return false; | |
34b650b3 | 7112 | |
ab77a036 RS |
7113 | /* Reject aligned bitfields: we want to use a normal load or store |
7114 | instead of a left/right pair. */ | |
7115 | if (MEM_ALIGN (*op) >= width) | |
7116 | return false; | |
06a4ab70 | 7117 | |
ab77a036 RS |
7118 | /* Adjust *OP to refer to the whole field. This also has the effect |
7119 | of legitimizing *OP's address for BLKmode, possibly simplifying it. */ | |
7120 | *op = adjust_address (*op, BLKmode, 0); | |
f5541398 | 7121 | set_mem_size (*op, width / BITS_PER_UNIT); |
06a4ab70 | 7122 | |
ab77a036 RS |
7123 | /* Get references to both ends of the field. We deliberately don't |
7124 | use the original QImode *OP for FIRST since the new BLKmode one | |
7125 | might have a simpler address. */ | |
7126 | first = adjust_address (*op, QImode, 0); | |
7127 | last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1); | |
cee98a59 | 7128 | |
ab77a036 | 7129 | /* Allocate to LEFT and RIGHT according to endianness. LEFT should |
65239d20 | 7130 | correspond to the MSB and RIGHT to the LSB. */ |
ab77a036 RS |
7131 | if (TARGET_BIG_ENDIAN) |
7132 | *left = first, *right = last; | |
7133 | else | |
7134 | *left = last, *right = first; | |
cee98a59 | 7135 | |
ab77a036 RS |
7136 | return true; |
7137 | } | |
cee98a59 | 7138 | |
65239d20 RS |
7139 | /* Try to use left/right loads to expand an "extv" or "extzv" pattern. |
7140 | DEST, SRC, WIDTH and BITPOS are the operands passed to the expander; | |
7141 | the operation is the equivalent of: | |
7142 | ||
7143 | (set DEST (*_extract SRC WIDTH BITPOS)) | |
cee98a59 | 7144 | |
65239d20 | 7145 | Return true on success. */ |
cee98a59 | 7146 | |
ab77a036 | 7147 | bool |
65239d20 RS |
7148 | mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width, |
7149 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
7150 | { |
7151 | rtx left, right, temp; | |
7152 | ||
65239d20 RS |
7153 | /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will |
7154 | be a paradoxical word_mode subreg. This is the only case in which | |
ab77a036 RS |
7155 | we allow the destination to be larger than the source. */ |
7156 | if (GET_CODE (dest) == SUBREG | |
7157 | && GET_MODE (dest) == DImode | |
ab77a036 RS |
7158 | && GET_MODE (SUBREG_REG (dest)) == SImode) |
7159 | dest = SUBREG_REG (dest); | |
7160 | ||
7161 | /* After the above adjustment, the destination must be the same | |
7162 | width as the source. */ | |
7163 | if (GET_MODE_BITSIZE (GET_MODE (dest)) != width) | |
7164 | return false; | |
7165 | ||
7166 | if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right)) | |
7167 | return false; | |
7168 | ||
7169 | temp = gen_reg_rtx (GET_MODE (dest)); | |
7170 | if (GET_MODE (dest) == DImode) | |
7171 | { | |
7172 | emit_insn (gen_mov_ldl (temp, src, left)); | |
7173 | emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp)); | |
7174 | } | |
7175 | else | |
7176 | { | |
7177 | emit_insn (gen_mov_lwl (temp, src, left)); | |
7178 | emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); | |
cee98a59 | 7179 | } |
ab77a036 RS |
7180 | return true; |
7181 | } | |
bfed8dac | 7182 | |
65239d20 RS |
7183 | /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH, |
7184 | BITPOS and SRC are the operands passed to the expander; the operation | |
7185 | is the equivalent of: | |
7186 | ||
7187 | (set (zero_extract DEST WIDTH BITPOS) SRC) | |
efa3896a | 7188 | |
65239d20 | 7189 | Return true on success. */ |
cafe096b | 7190 | |
ab77a036 | 7191 | bool |
65239d20 RS |
7192 | mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, |
7193 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
7194 | { |
7195 | rtx left, right; | |
7196 | enum machine_mode mode; | |
6ba7b547 | 7197 | |
ab77a036 RS |
7198 | if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right)) |
7199 | return false; | |
f9e4a411 | 7200 | |
ab77a036 RS |
7201 | mode = mode_for_size (width, MODE_INT, 0); |
7202 | src = gen_lowpart (mode, src); | |
ab77a036 RS |
7203 | if (mode == DImode) |
7204 | { | |
7205 | emit_insn (gen_mov_sdl (dest, src, left)); | |
7206 | emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); | |
7207 | } | |
7208 | else | |
7209 | { | |
7210 | emit_insn (gen_mov_swl (dest, src, left)); | |
7211 | emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); | |
7212 | } | |
7213 | return true; | |
c8d1b2b7 AO |
7214 | } |
7215 | ||
ab77a036 | 7216 | /* Return true if X is a MEM with the same size as MODE. */ |
48156a39 | 7217 | |
ab77a036 RS |
7218 | bool |
7219 | mips_mem_fits_mode_p (enum machine_mode mode, rtx x) | |
48156a39 | 7220 | { |
f5541398 RS |
7221 | return (MEM_P (x) |
7222 | && MEM_SIZE_KNOWN_P (x) | |
7223 | && MEM_SIZE (x) == GET_MODE_SIZE (mode)); | |
48156a39 NS |
7224 | } |
7225 | ||
65239d20 | 7226 | /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the |
ab77a036 RS |
7227 | source of an "ext" instruction or the destination of an "ins" |
7228 | instruction. OP must be a register operand and the following | |
7229 | conditions must hold: | |
ac8ab9fe | 7230 | |
65239d20 RS |
7231 | 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op)) |
7232 | 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
7233 | 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
ab77a036 RS |
7234 | |
7235 | Also reject lengths equal to a word as they are better handled | |
7236 | by the move patterns. */ | |
7237 | ||
7238 | bool | |
65239d20 | 7239 | mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) |
ac8ab9fe | 7240 | { |
ab77a036 RS |
7241 | if (!ISA_HAS_EXT_INS |
7242 | || !register_operand (op, VOIDmode) | |
7243 | || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) | |
7244 | return false; | |
ac8ab9fe | 7245 | |
65239d20 RS |
7246 | if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1)) |
7247 | return false; | |
ac8ab9fe | 7248 | |
65239d20 | 7249 | if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op))) |
ab77a036 RS |
7250 | return false; |
7251 | ||
7252 | return true; | |
ac8ab9fe | 7253 | } |
49912bcd AN |
7254 | |
7255 | /* Check if MASK and SHIFT are valid in mask-low-and-shift-left | |
7256 | operation if MAXLEN is the maxium length of consecutive bits that | |
7257 | can make up MASK. MODE is the mode of the operation. See | |
7258 | mask_low_and_shift_len for the actual definition. */ | |
7259 | ||
7260 | bool | |
7261 | mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen) | |
7262 | { | |
7263 | return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen); | |
7264 | } | |
7265 | ||
b2c9d70f AN |
7266 | /* Return true iff OP1 and OP2 are valid operands together for the |
7267 | *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider, | |
7268 | see the table in the comment before the pattern. */ | |
7269 | ||
7270 | bool | |
7271 | and_operands_ok (enum machine_mode mode, rtx op1, rtx op2) | |
7272 | { | |
7273 | return (memory_operand (op1, mode) | |
7274 | ? and_load_operand (op2, mode) | |
7275 | : and_reg_operand (op2, mode)); | |
7276 | } | |
7277 | ||
49912bcd AN |
7278 | /* The canonical form of a mask-low-and-shift-left operation is |
7279 | (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits | |
7280 | cleared. Thus we need to shift MASK to the right before checking if it | |
7281 | is a valid mask value. MODE is the mode of the operation. If true | |
7282 | return the length of the mask, otherwise return -1. */ | |
7283 | ||
7284 | int | |
7285 | mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift) | |
7286 | { | |
7287 | HOST_WIDE_INT shval; | |
7288 | ||
7289 | shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1); | |
7290 | return exact_log2 ((UINTVAL (mask) >> shval) + 1); | |
7291 | } | |
ab77a036 | 7292 | \f |
65239d20 | 7293 | /* Return true if -msplit-addresses is selected and should be honored. |
ac8ab9fe | 7294 | |
65239d20 RS |
7295 | -msplit-addresses is a half-way house between explicit relocations |
7296 | and the traditional assembler macros. It can split absolute 32-bit | |
7297 | symbolic constants into a high/lo_sum pair but uses macros for other | |
7298 | sorts of access. | |
ab77a036 RS |
7299 | |
7300 | Like explicit relocation support for REL targets, it relies | |
7301 | on GNU extensions in the assembler and the linker. | |
7302 | ||
7303 | Although this code should work for -O0, it has traditionally | |
7304 | been treated as an optimization. */ | |
7305 | ||
65239d20 RS |
7306 | static bool |
7307 | mips_split_addresses_p (void) | |
c8d1b2b7 | 7308 | { |
65239d20 RS |
7309 | return (TARGET_SPLIT_ADDRESSES |
7310 | && optimize | |
7311 | && !TARGET_MIPS16 | |
7312 | && !flag_pic | |
7313 | && !ABI_HAS_64BIT_SYMBOLS); | |
cee98a59 MM |
7314 | } |
7315 | ||
65239d20 | 7316 | /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */ |
2bcb2ab3 | 7317 | |
ab77a036 RS |
7318 | static void |
7319 | mips_init_relocs (void) | |
2bcb2ab3 | 7320 | { |
ab77a036 | 7321 | memset (mips_split_p, '\0', sizeof (mips_split_p)); |
08d0963a | 7322 | memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p)); |
ddaf8125 | 7323 | memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p)); |
ab77a036 RS |
7324 | memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs)); |
7325 | memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs)); | |
2bcb2ab3 | 7326 | |
ddaf8125 RS |
7327 | if (TARGET_MIPS16_PCREL_LOADS) |
7328 | mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true; | |
7329 | else | |
ab77a036 | 7330 | { |
ddaf8125 | 7331 | if (ABI_HAS_64BIT_SYMBOLS) |
ab77a036 | 7332 | { |
ddaf8125 RS |
7333 | if (TARGET_EXPLICIT_RELOCS) |
7334 | { | |
7335 | mips_split_p[SYMBOL_64_HIGH] = true; | |
7336 | mips_hi_relocs[SYMBOL_64_HIGH] = "%highest("; | |
7337 | mips_lo_relocs[SYMBOL_64_HIGH] = "%higher("; | |
ab77a036 | 7338 | |
ddaf8125 RS |
7339 | mips_split_p[SYMBOL_64_MID] = true; |
7340 | mips_hi_relocs[SYMBOL_64_MID] = "%higher("; | |
7341 | mips_lo_relocs[SYMBOL_64_MID] = "%hi("; | |
ab77a036 | 7342 | |
ddaf8125 RS |
7343 | mips_split_p[SYMBOL_64_LOW] = true; |
7344 | mips_hi_relocs[SYMBOL_64_LOW] = "%hi("; | |
7345 | mips_lo_relocs[SYMBOL_64_LOW] = "%lo("; | |
ab77a036 | 7346 | |
ddaf8125 RS |
7347 | mips_split_p[SYMBOL_ABSOLUTE] = true; |
7348 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7349 | } | |
ab77a036 | 7350 | } |
ddaf8125 | 7351 | else |
ab77a036 | 7352 | { |
ddaf8125 RS |
7353 | if (TARGET_EXPLICIT_RELOCS |
7354 | || mips_split_addresses_p () | |
7355 | || TARGET_MIPS16) | |
7356 | { | |
7357 | mips_split_p[SYMBOL_ABSOLUTE] = true; | |
7358 | mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; | |
7359 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7360 | } | |
ab77a036 RS |
7361 | } |
7362 | } | |
2bcb2ab3 GK |
7363 | |
7364 | if (TARGET_MIPS16) | |
7365 | { | |
ab77a036 RS |
7366 | /* The high part is provided by a pseudo copy of $gp. */ |
7367 | mips_split_p[SYMBOL_GP_RELATIVE] = true; | |
7368 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel("; | |
2bcb2ab3 | 7369 | } |
08d0963a RS |
7370 | else if (TARGET_EXPLICIT_RELOCS) |
7371 | /* Small data constants are kept whole until after reload, | |
7372 | then lowered by mips_rewrite_small_data. */ | |
7373 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel("; | |
2bcb2ab3 | 7374 | |
ab77a036 RS |
7375 | if (TARGET_EXPLICIT_RELOCS) |
7376 | { | |
ab77a036 RS |
7377 | mips_split_p[SYMBOL_GOT_PAGE_OFST] = true; |
7378 | if (TARGET_NEWABI) | |
7379 | { | |
7380 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page("; | |
7381 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst("; | |
7382 | } | |
7383 | else | |
7384 | { | |
7385 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got("; | |
7386 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo("; | |
7387 | } | |
08d0963a RS |
7388 | if (TARGET_MIPS16) |
7389 | /* Expose the use of $28 as soon as possible. */ | |
7390 | mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true; | |
cee98a59 | 7391 | |
ab77a036 RS |
7392 | if (TARGET_XGOT) |
7393 | { | |
7394 | /* The HIGH and LO_SUM are matched by special .md patterns. */ | |
7395 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
cee98a59 | 7396 | |
ab77a036 RS |
7397 | mips_split_p[SYMBOL_GOTOFF_DISP] = true; |
7398 | mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi("; | |
7399 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo("; | |
c831afd5 | 7400 | |
ab77a036 RS |
7401 | mips_split_p[SYMBOL_GOTOFF_CALL] = true; |
7402 | mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi("; | |
7403 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo("; | |
7404 | } | |
7405 | else | |
7406 | { | |
7407 | if (TARGET_NEWABI) | |
7408 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp("; | |
7409 | else | |
7410 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got("; | |
7411 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16("; | |
08d0963a RS |
7412 | if (TARGET_MIPS16) |
7413 | /* Expose the use of $28 as soon as possible. */ | |
7414 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
ab77a036 RS |
7415 | } |
7416 | } | |
a50f2a09 | 7417 | |
ab77a036 RS |
7418 | if (TARGET_NEWABI) |
7419 | { | |
7420 | mips_split_p[SYMBOL_GOTOFF_LOADGP] = true; | |
7421 | mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel("; | |
7422 | mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel("; | |
c831afd5 | 7423 | } |
f5963e61 | 7424 | |
ab77a036 RS |
7425 | mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd("; |
7426 | mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm("; | |
65239d20 | 7427 | |
ddaf8125 RS |
7428 | if (TARGET_MIPS16_PCREL_LOADS) |
7429 | { | |
7430 | mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true; | |
7431 | mips_use_pcrel_pool_p[SYMBOL_TPREL] = true; | |
7432 | } | |
7433 | else | |
7434 | { | |
7435 | mips_split_p[SYMBOL_DTPREL] = true; | |
7436 | mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi("; | |
7437 | mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo("; | |
65239d20 | 7438 | |
ddaf8125 RS |
7439 | mips_split_p[SYMBOL_TPREL] = true; |
7440 | mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi("; | |
7441 | mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo("; | |
7442 | } | |
cee98a59 | 7443 | |
ddaf8125 | 7444 | mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel("; |
ab77a036 | 7445 | mips_lo_relocs[SYMBOL_HALF] = "%half("; |
cee98a59 | 7446 | } |
ab77a036 | 7447 | |
ab77a036 RS |
7448 | /* Print symbolic operand OP, which is part of a HIGH or LO_SUM |
7449 | in context CONTEXT. RELOCS is the array of relocations to use. */ | |
7450 | ||
7451 | static void | |
65239d20 RS |
7452 | mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context, |
7453 | const char **relocs) | |
ab77a036 RS |
7454 | { |
7455 | enum mips_symbol_type symbol_type; | |
7456 | const char *p; | |
7457 | ||
7458 | symbol_type = mips_classify_symbolic_expression (op, context); | |
65239d20 | 7459 | gcc_assert (relocs[symbol_type]); |
ab77a036 RS |
7460 | |
7461 | fputs (relocs[symbol_type], file); | |
7462 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7463 | for (p = relocs[symbol_type]; *p != 0; p++) | |
7464 | if (*p == '(') | |
7465 | fputc (')', file); | |
7466 | } | |
7467 | ||
cf5fb4b0 RS |
7468 | /* Start a new block with the given asm switch enabled. If we need |
7469 | to print a directive, emit PREFIX before it and SUFFIX after it. */ | |
7470 | ||
7471 | static void | |
7472 | mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7473 | const char *prefix, const char *suffix) | |
7474 | { | |
7475 | if (asm_switch->nesting_level == 0) | |
7476 | fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix); | |
7477 | asm_switch->nesting_level++; | |
7478 | } | |
7479 | ||
7480 | /* Likewise, but end a block. */ | |
7481 | ||
7482 | static void | |
7483 | mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7484 | const char *prefix, const char *suffix) | |
7485 | { | |
7486 | gcc_assert (asm_switch->nesting_level); | |
7487 | asm_switch->nesting_level--; | |
7488 | if (asm_switch->nesting_level == 0) | |
7489 | fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix); | |
7490 | } | |
7491 | ||
7492 | /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1 | |
7493 | that either print a complete line or print nothing. */ | |
7494 | ||
7495 | void | |
7496 | mips_push_asm_switch (struct mips_asm_switch *asm_switch) | |
7497 | { | |
7498 | mips_push_asm_switch_1 (asm_switch, "\t", "\n"); | |
7499 | } | |
7500 | ||
7501 | void | |
7502 | mips_pop_asm_switch (struct mips_asm_switch *asm_switch) | |
7503 | { | |
7504 | mips_pop_asm_switch_1 (asm_switch, "\t", "\n"); | |
7505 | } | |
7506 | ||
07045266 | 7507 | /* Print the text for PRINT_OPERAND punctation character CH to FILE. |
dfad12b5 RS |
7508 | The punctuation characters are: |
7509 | ||
07045266 RS |
7510 | '(' Start a nested ".set noreorder" block. |
7511 | ')' End a nested ".set noreorder" block. | |
7512 | '[' Start a nested ".set noat" block. | |
7513 | ']' End a nested ".set noat" block. | |
7514 | '<' Start a nested ".set nomacro" block. | |
7515 | '>' End a nested ".set nomacro" block. | |
7516 | '*' Behave like %(%< if generating a delayed-branch sequence. | |
7517 | '#' Print a nop if in a ".set noreorder" block. | |
7518 | '/' Like '#', but do nothing within a delayed-branch sequence. | |
7519 | '?' Print "l" if mips_branch_likely is true | |
ee9a72e5 | 7520 | '~' Print a nop if mips_branch_likely is true |
ffa9d0b1 | 7521 | '.' Print the name of the register with a hard-wired zero (zero or $0). |
07045266 | 7522 | '@' Print the name of the assembler temporary register (at or $1). |
2bcb2ab3 | 7523 | '^' Print the name of the pic call-through register (t9 or $25). |
f833ffd4 | 7524 | '+' Print the name of the gp register (usually gp or $28). |
07045266 | 7525 | '$' Print the name of the stack pointer register (sp or $29). |
cee98a59 | 7526 | |
07045266 | 7527 | See also mips_init_print_operand_pucnt. */ |
cee98a59 | 7528 | |
07045266 RS |
7529 | static void |
7530 | mips_print_operand_punctuation (FILE *file, int ch) | |
7531 | { | |
7532 | switch (ch) | |
cee98a59 | 7533 | { |
07045266 | 7534 | case '(': |
cf5fb4b0 | 7535 | mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t"); |
07045266 | 7536 | break; |
cee98a59 | 7537 | |
07045266 | 7538 | case ')': |
cf5fb4b0 | 7539 | mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", ""); |
07045266 | 7540 | break; |
cee98a59 | 7541 | |
07045266 | 7542 | case '[': |
cf5fb4b0 | 7543 | mips_push_asm_switch_1 (&mips_noat, "", "\n\t"); |
07045266 | 7544 | break; |
ffa9d0b1 | 7545 | |
07045266 | 7546 | case ']': |
cf5fb4b0 | 7547 | mips_pop_asm_switch_1 (&mips_noat, "\n\t", ""); |
07045266 | 7548 | break; |
cee98a59 | 7549 | |
07045266 | 7550 | case '<': |
cf5fb4b0 | 7551 | mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t"); |
07045266 | 7552 | break; |
2bcb2ab3 | 7553 | |
07045266 | 7554 | case '>': |
cf5fb4b0 | 7555 | mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", ""); |
07045266 | 7556 | break; |
2bcb2ab3 | 7557 | |
07045266 RS |
7558 | case '*': |
7559 | if (final_sequence != 0) | |
7560 | { | |
7561 | mips_print_operand_punctuation (file, '('); | |
7562 | mips_print_operand_punctuation (file, '<'); | |
7563 | } | |
7564 | break; | |
cee98a59 | 7565 | |
07045266 | 7566 | case '#': |
cf5fb4b0 | 7567 | if (mips_noreorder.nesting_level > 0) |
07045266 RS |
7568 | fputs ("\n\tnop", file); |
7569 | break; | |
cee98a59 | 7570 | |
07045266 RS |
7571 | case '/': |
7572 | /* Print an extra newline so that the delayed insn is separated | |
7573 | from the following ones. This looks neater and is consistent | |
7574 | with non-nop delayed sequences. */ | |
cf5fb4b0 | 7575 | if (mips_noreorder.nesting_level > 0 && final_sequence == 0) |
07045266 RS |
7576 | fputs ("\n\tnop\n", file); |
7577 | break; | |
cee98a59 | 7578 | |
07045266 RS |
7579 | case '?': |
7580 | if (mips_branch_likely) | |
7581 | putc ('l', file); | |
7582 | break; | |
cee98a59 | 7583 | |
ee9a72e5 JK |
7584 | case '~': |
7585 | if (mips_branch_likely) | |
7586 | fputs ("\n\tnop", file); | |
7587 | break; | |
7588 | ||
07045266 RS |
7589 | case '.': |
7590 | fputs (reg_names[GP_REG_FIRST + 0], file); | |
7591 | break; | |
cee98a59 | 7592 | |
07045266 | 7593 | case '@': |
293593b1 | 7594 | fputs (reg_names[AT_REGNUM], file); |
07045266 | 7595 | break; |
6f2993e5 | 7596 | |
07045266 RS |
7597 | case '^': |
7598 | fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file); | |
7599 | break; | |
cee98a59 | 7600 | |
07045266 RS |
7601 | case '+': |
7602 | fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); | |
7603 | break; | |
cee98a59 | 7604 | |
07045266 RS |
7605 | case '$': |
7606 | fputs (reg_names[STACK_POINTER_REGNUM], file); | |
7607 | break; | |
cee98a59 | 7608 | |
07045266 RS |
7609 | default: |
7610 | gcc_unreachable (); | |
7611 | break; | |
7612 | } | |
7613 | } | |
cee98a59 | 7614 | |
07045266 | 7615 | /* Initialize mips_print_operand_punct. */ |
cee98a59 | 7616 | |
07045266 RS |
7617 | static void |
7618 | mips_init_print_operand_punct (void) | |
7619 | { | |
7620 | const char *p; | |
cee98a59 | 7621 | |
6f5a62e9 | 7622 | for (p = "()[]<>*#/?~.@^+$"; *p; p++) |
07045266 RS |
7623 | mips_print_operand_punct[(unsigned char) *p] = true; |
7624 | } | |
cee98a59 | 7625 | |
07045266 RS |
7626 | /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction |
7627 | associated with condition CODE. Print the condition part of the | |
7628 | opcode to FILE. */ | |
cee98a59 | 7629 | |
07045266 RS |
7630 | static void |
7631 | mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter) | |
7632 | { | |
7633 | switch (code) | |
7634 | { | |
7635 | case EQ: | |
7636 | case NE: | |
7637 | case GT: | |
7638 | case GE: | |
7639 | case LT: | |
7640 | case LE: | |
7641 | case GTU: | |
7642 | case GEU: | |
7643 | case LTU: | |
7644 | case LEU: | |
7645 | /* Conveniently, the MIPS names for these conditions are the same | |
7646 | as their RTL equivalents. */ | |
7647 | fputs (GET_RTX_NAME (code), file); | |
7648 | break; | |
cee98a59 | 7649 | |
07045266 RS |
7650 | default: |
7651 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
7652 | break; | |
7653 | } | |
7654 | } | |
cee98a59 | 7655 | |
07045266 | 7656 | /* Likewise floating-point branches. */ |
f5963e61 | 7657 | |
07045266 RS |
7658 | static void |
7659 | mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter) | |
7660 | { | |
7661 | switch (code) | |
7662 | { | |
7663 | case EQ: | |
7664 | fputs ("c1f", file); | |
7665 | break; | |
efa3896a | 7666 | |
07045266 RS |
7667 | case NE: |
7668 | fputs ("c1t", file); | |
7669 | break; | |
66471b47 | 7670 | |
07045266 RS |
7671 | default: |
7672 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
7673 | break; | |
7674 | } | |
7675 | } | |
66471b47 | 7676 | |
6e9e0126 NF |
7677 | /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
7678 | ||
7679 | static bool | |
7680 | mips_print_operand_punct_valid_p (unsigned char code) | |
7681 | { | |
7682 | return mips_print_operand_punct[code]; | |
7683 | } | |
7684 | ||
7685 | /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are: | |
f5963e61 | 7686 | |
07045266 RS |
7687 | 'X' Print CONST_INT OP in hexadecimal format. |
7688 | 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format. | |
7689 | 'd' Print CONST_INT OP in decimal. | |
49912bcd | 7690 | 'm' Print one less than CONST_INT OP in decimal. |
07045266 RS |
7691 | 'h' Print the high-part relocation associated with OP, after stripping |
7692 | any outermost HIGH. | |
7693 | 'R' Print the low-part relocation associated with OP. | |
7694 | 'C' Print the integer branch condition for comparison OP. | |
7695 | 'N' Print the inverse of the integer branch condition for comparison OP. | |
7696 | 'F' Print the FPU branch condition for comparison OP. | |
7697 | 'W' Print the inverse of the FPU branch condition for comparison OP. | |
7698 | 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...), | |
7699 | 'z' for (eq:?I ...), 'n' for (ne:?I ...). | |
7700 | 't' Like 'T', but with the EQ/NE cases reversed | |
7701 | 'Y' Print mips_fp_conditions[INTVAL (OP)] | |
7702 | 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing. | |
7703 | 'q' Print a DSP accumulator register. | |
7704 | 'D' Print the second part of a double-word register or memory operand. | |
7705 | 'L' Print the low-order register in a double-word register operand. | |
7706 | 'M' Print high-order register in a double-word register operand. | |
7707 | 'z' Print $0 if OP is zero, otherwise print OP normally. */ | |
7708 | ||
6e9e0126 | 7709 | static void |
65239d20 | 7710 | mips_print_operand (FILE *file, rtx op, int letter) |
07045266 RS |
7711 | { |
7712 | enum rtx_code code; | |
cee98a59 | 7713 | |
6e9e0126 | 7714 | if (mips_print_operand_punct_valid_p (letter)) |
cee98a59 | 7715 | { |
07045266 | 7716 | mips_print_operand_punctuation (file, letter); |
cee98a59 MM |
7717 | return; |
7718 | } | |
7719 | ||
07045266 | 7720 | gcc_assert (op); |
cee98a59 | 7721 | code = GET_CODE (op); |
2a0b0bf5 | 7722 | |
07045266 RS |
7723 | switch (letter) |
7724 | { | |
7725 | case 'X': | |
47ac44d6 | 7726 | if (CONST_INT_P (op)) |
07045266 RS |
7727 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); |
7728 | else | |
7729 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7730 | break; | |
cee98a59 | 7731 | |
07045266 | 7732 | case 'x': |
47ac44d6 | 7733 | if (CONST_INT_P (op)) |
07045266 RS |
7734 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff); |
7735 | else | |
7736 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7737 | break; | |
0ff83799 | 7738 | |
07045266 | 7739 | case 'd': |
47ac44d6 | 7740 | if (CONST_INT_P (op)) |
07045266 RS |
7741 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op)); |
7742 | else | |
7743 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7744 | break; | |
0ff83799 | 7745 | |
49912bcd | 7746 | case 'm': |
47ac44d6 | 7747 | if (CONST_INT_P (op)) |
49912bcd AN |
7748 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1); |
7749 | else | |
7750 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7751 | break; | |
7752 | ||
07045266 RS |
7753 | case 'h': |
7754 | if (code == HIGH) | |
108b61d5 | 7755 | op = XEXP (op, 0); |
65239d20 | 7756 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs); |
07045266 RS |
7757 | break; |
7758 | ||
7759 | case 'R': | |
65239d20 | 7760 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs); |
07045266 | 7761 | break; |
108b61d5 | 7762 | |
07045266 RS |
7763 | case 'C': |
7764 | mips_print_int_branch_condition (file, code, letter); | |
7765 | break; | |
108b61d5 | 7766 | |
07045266 RS |
7767 | case 'N': |
7768 | mips_print_int_branch_condition (file, reverse_condition (code), letter); | |
7769 | break; | |
7770 | ||
7771 | case 'F': | |
7772 | mips_print_float_branch_condition (file, code, letter); | |
7773 | break; | |
7774 | ||
7775 | case 'W': | |
7776 | mips_print_float_branch_condition (file, reverse_condition (code), | |
7777 | letter); | |
7778 | break; | |
7779 | ||
7780 | case 'T': | |
7781 | case 't': | |
7782 | { | |
7783 | int truth = (code == NE) == (letter == 'T'); | |
7784 | fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); | |
7785 | } | |
7786 | break; | |
7787 | ||
7788 | case 'Y': | |
7789 | if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions)) | |
7790 | fputs (mips_fp_conditions[UINTVAL (op)], file); | |
308cd611 | 7791 | else |
07045266 RS |
7792 | output_operand_lossage ("'%%%c' is not a valid operand prefix", |
7793 | letter); | |
7794 | break; | |
06a4ab70 | 7795 | |
07045266 | 7796 | case 'Z': |
308cd611 RS |
7797 | if (ISA_HAS_8CC) |
7798 | { | |
65239d20 | 7799 | mips_print_operand (file, op, 0); |
308cd611 RS |
7800 | fputc (',', file); |
7801 | } | |
07045266 | 7802 | break; |
118ea793 | 7803 | |
07045266 RS |
7804 | case 'q': |
7805 | if (code == REG && MD_REG_P (REGNO (op))) | |
118ea793 | 7806 | fprintf (file, "$ac0"); |
07045266 RS |
7807 | else if (code == REG && DSP_ACC_REG_P (REGNO (op))) |
7808 | fprintf (file, "$ac%c", reg_names[REGNO (op)][3]); | |
51c6b247 | 7809 | else |
07045266 RS |
7810 | output_operand_lossage ("invalid use of '%%%c'", letter); |
7811 | break; | |
cee98a59 | 7812 | |
07045266 RS |
7813 | default: |
7814 | switch (code) | |
7815 | { | |
7816 | case REG: | |
7817 | { | |
7818 | unsigned int regno = REGNO (op); | |
7819 | if ((letter == 'M' && TARGET_LITTLE_ENDIAN) | |
7820 | || (letter == 'L' && TARGET_BIG_ENDIAN) | |
7821 | || letter == 'D') | |
7822 | regno++; | |
b0907a6c AN |
7823 | else if (letter && letter != 'z' && letter != 'M' && letter != 'L') |
7824 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
e19da24c CF |
7825 | /* We need to print $0 .. $31 for COP0 registers. */ |
7826 | if (COP0_REG_P (regno)) | |
7827 | fprintf (file, "$%s", ®_names[regno][4]); | |
7828 | else | |
7829 | fprintf (file, "%s", reg_names[regno]); | |
07045266 RS |
7830 | } |
7831 | break; | |
cee98a59 | 7832 | |
07045266 RS |
7833 | case MEM: |
7834 | if (letter == 'D') | |
7835 | output_address (plus_constant (XEXP (op, 0), 4)); | |
b0907a6c AN |
7836 | else if (letter && letter != 'z') |
7837 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
7838 | else |
7839 | output_address (XEXP (op, 0)); | |
7840 | break; | |
cee98a59 | 7841 | |
07045266 RS |
7842 | default: |
7843 | if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) | |
7844 | fputs (reg_names[GP_REG_FIRST], file); | |
b0907a6c AN |
7845 | else if (letter && letter != 'z') |
7846 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
7847 | else if (CONST_GP_P (op)) |
7848 | fputs (reg_names[GLOBAL_POINTER_REGNUM], file); | |
7849 | else | |
7850 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7851 | break; | |
7852 | } | |
b3c90666 | 7853 | } |
108b61d5 | 7854 | } |
07045266 | 7855 | |
6e9e0126 | 7856 | /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ |
cee98a59 | 7857 | |
6e9e0126 | 7858 | static void |
65239d20 | 7859 | mips_print_operand_address (FILE *file, rtx x) |
cafe096b EC |
7860 | { |
7861 | struct mips_address_info addr; | |
cee98a59 | 7862 | |
108b61d5 RS |
7863 | if (mips_classify_address (&addr, x, word_mode, true)) |
7864 | switch (addr.type) | |
7865 | { | |
7866 | case ADDRESS_REG: | |
65239d20 | 7867 | mips_print_operand (file, addr.offset, 0); |
108b61d5 RS |
7868 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
7869 | return; | |
7870 | ||
7871 | case ADDRESS_LO_SUM: | |
65239d20 RS |
7872 | mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM, |
7873 | mips_lo_relocs); | |
108b61d5 RS |
7874 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
7875 | return; | |
7876 | ||
7877 | case ADDRESS_CONST_INT: | |
4767c570 | 7878 | output_addr_const (file, x); |
65239d20 | 7879 | fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); |
4767c570 RS |
7880 | return; |
7881 | ||
108b61d5 | 7882 | case ADDRESS_SYMBOLIC: |
c93c5160 | 7883 | output_addr_const (file, mips_strip_unspec_address (x)); |
108b61d5 RS |
7884 | return; |
7885 | } | |
7ad769fe | 7886 | gcc_unreachable (); |
cee98a59 | 7887 | } |
301d03af | 7888 | \f |
65239d20 | 7889 | /* Implement TARGET_ENCODE_SECTION_INFO. */ |
ab77a036 RS |
7890 | |
7891 | static void | |
7892 | mips_encode_section_info (tree decl, rtx rtl, int first) | |
7893 | { | |
7894 | default_encode_section_info (decl, rtl, first); | |
7895 | ||
7896 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
7897 | { | |
7898 | rtx symbol = XEXP (rtl, 0); | |
7899 | tree type = TREE_TYPE (decl); | |
7900 | ||
65239d20 | 7901 | /* Encode whether the symbol is short or long. */ |
ab77a036 RS |
7902 | if ((TARGET_LONG_CALLS && !mips_near_type_p (type)) |
7903 | || mips_far_type_p (type)) | |
7904 | SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; | |
7905 | } | |
7906 | } | |
7907 | ||
7908 | /* Implement TARGET_SELECT_RTX_SECTION. */ | |
7909 | ||
7910 | static section * | |
7911 | mips_select_rtx_section (enum machine_mode mode, rtx x, | |
7912 | unsigned HOST_WIDE_INT align) | |
7913 | { | |
7914 | /* ??? Consider using mergeable small data sections. */ | |
7915 | if (mips_rtx_constant_in_small_data_p (mode)) | |
7916 | return get_named_section (NULL, ".sdata", 0); | |
7917 | ||
7918 | return default_elf_select_rtx_section (mode, x, align); | |
7919 | } | |
7920 | ||
7921 | /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. | |
7922 | ||
7923 | The complication here is that, with the combination TARGET_ABICALLS | |
e21d5757 DJ |
7924 | && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use |
7925 | absolute addresses, and should therefore not be included in the | |
7926 | read-only part of a DSO. Handle such cases by selecting a normal | |
7927 | data section instead of a read-only one. The logic apes that in | |
7928 | default_function_rodata_section. */ | |
ab77a036 RS |
7929 | |
7930 | static section * | |
7931 | mips_function_rodata_section (tree decl) | |
7932 | { | |
e21d5757 | 7933 | if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD) |
ab77a036 RS |
7934 | return default_function_rodata_section (decl); |
7935 | ||
7936 | if (decl && DECL_SECTION_NAME (decl)) | |
7937 | { | |
7938 | const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
7939 | if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0) | |
7940 | { | |
7941 | char *rname = ASTRDUP (name); | |
7942 | rname[14] = 'd'; | |
7943 | return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl); | |
7944 | } | |
65239d20 RS |
7945 | else if (flag_function_sections |
7946 | && flag_data_sections | |
ab77a036 RS |
7947 | && strncmp (name, ".text.", 6) == 0) |
7948 | { | |
7949 | char *rname = ASTRDUP (name); | |
7950 | memcpy (rname + 1, "data", 4); | |
7951 | return get_section (rname, SECTION_WRITE, decl); | |
7952 | } | |
7953 | } | |
7954 | return data_section; | |
7955 | } | |
7956 | ||
65239d20 | 7957 | /* Implement TARGET_IN_SMALL_DATA_P. */ |
ab77a036 RS |
7958 | |
7959 | static bool | |
7960 | mips_in_small_data_p (const_tree decl) | |
7961 | { | |
65239d20 | 7962 | unsigned HOST_WIDE_INT size; |
ab77a036 RS |
7963 | |
7964 | if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL) | |
7965 | return false; | |
7966 | ||
65239d20 RS |
7967 | /* We don't yet generate small-data references for -mabicalls |
7968 | or VxWorks RTP code. See the related -G handling in | |
525c561d | 7969 | mips_option_override. */ |
ab77a036 RS |
7970 | if (TARGET_ABICALLS || TARGET_VXWORKS_RTP) |
7971 | return false; | |
7972 | ||
7973 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) | |
7974 | { | |
7975 | const char *name; | |
7976 | ||
7977 | /* Reject anything that isn't in a known small-data section. */ | |
7978 | name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
7979 | if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) | |
7980 | return false; | |
7981 | ||
7982 | /* If a symbol is defined externally, the assembler will use the | |
7983 | usual -G rules when deciding how to implement macros. */ | |
7984 | if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl)) | |
7985 | return true; | |
7986 | } | |
7987 | else if (TARGET_EMBEDDED_DATA) | |
7988 | { | |
7989 | /* Don't put constants into the small data section: we want them | |
7990 | to be in ROM rather than RAM. */ | |
7991 | if (TREE_CODE (decl) != VAR_DECL) | |
7992 | return false; | |
7993 | ||
7994 | if (TREE_READONLY (decl) | |
7995 | && !TREE_SIDE_EFFECTS (decl) | |
7996 | && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl)))) | |
7997 | return false; | |
7998 | } | |
7999 | ||
8000 | /* Enforce -mlocal-sdata. */ | |
8001 | if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl)) | |
8002 | return false; | |
8003 | ||
8004 | /* Enforce -mextern-sdata. */ | |
8005 | if (!TARGET_EXTERN_SDATA && DECL_P (decl)) | |
8006 | { | |
8007 | if (DECL_EXTERNAL (decl)) | |
8008 | return false; | |
8009 | if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL) | |
8010 | return false; | |
8011 | } | |
8012 | ||
2a4430a6 RS |
8013 | /* We have traditionally not treated zero-sized objects as small data, |
8014 | so this is now effectively part of the ABI. */ | |
ab77a036 | 8015 | size = int_size_in_bytes (TREE_TYPE (decl)); |
2a4430a6 | 8016 | return size > 0 && size <= mips_small_data_threshold; |
ab77a036 RS |
8017 | } |
8018 | ||
8019 | /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use | |
8020 | anchors for small data: the GP register acts as an anchor in that | |
8021 | case. We also don't want to use them for PC-relative accesses, | |
8022 | where the PC acts as an anchor. */ | |
8023 | ||
8024 | static bool | |
8025 | mips_use_anchors_for_symbol_p (const_rtx symbol) | |
8026 | { | |
8027 | switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM)) | |
8028 | { | |
8029 | case SYMBOL_PC_RELATIVE: | |
8030 | case SYMBOL_GP_RELATIVE: | |
8031 | return false; | |
8032 | ||
8033 | default: | |
8034 | return default_use_anchors_for_symbol_p (symbol); | |
8035 | } | |
8036 | } | |
8037 | \f | |
8038 | /* The MIPS debug format wants all automatic variables and arguments | |
8039 | to be in terms of the virtual frame pointer (stack pointer before | |
8040 | any adjustment in the function), while the MIPS 3.0 linker wants | |
8041 | the frame pointer to be the stack pointer after the initial | |
8042 | adjustment. So, we do the adjustment here. The arg pointer (which | |
8043 | is eliminated) points to the virtual frame pointer, while the frame | |
8044 | pointer (which may be eliminated) points to the stack pointer after | |
8045 | the initial adjustments. */ | |
8046 | ||
8047 | HOST_WIDE_INT | |
8048 | mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) | |
8049 | { | |
8050 | rtx offset2 = const0_rtx; | |
8051 | rtx reg = eliminate_constant_term (addr, &offset2); | |
8052 | ||
8053 | if (offset == 0) | |
8054 | offset = INTVAL (offset2); | |
8055 | ||
65239d20 RS |
8056 | if (reg == stack_pointer_rtx |
8057 | || reg == frame_pointer_rtx | |
ab77a036 RS |
8058 | || reg == hard_frame_pointer_rtx) |
8059 | { | |
f374e413 RS |
8060 | offset -= cfun->machine->frame.total_size; |
8061 | if (reg == hard_frame_pointer_rtx) | |
8062 | offset += cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
8063 | } |
8064 | ||
8065 | /* sdbout_parms does not want this to crash for unrecognized cases. */ | |
8066 | #if 0 | |
8067 | else if (reg != arg_pointer_rtx) | |
8068 | fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer", | |
8069 | addr); | |
8070 | #endif | |
8071 | ||
8072 | return offset; | |
8073 | } | |
8074 | \f | |
65239d20 | 8075 | /* Implement ASM_OUTPUT_EXTERNAL. */ |
cee98a59 | 8076 | |
f8fdb503 L |
8077 | void |
8078 | mips_output_external (FILE *file, tree decl, const char *name) | |
5619cc87 | 8079 | { |
f8fdb503 | 8080 | default_elf_asm_output_external (file, decl, name); |
5619cc87 | 8081 | |
f8fdb503 L |
8082 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
8083 | set in order to avoid putting out names that are never really | |
8084 | used. */ | |
8085 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
6773a41c | 8086 | { |
f8fdb503 L |
8087 | if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl)) |
8088 | { | |
65239d20 RS |
8089 | /* When using assembler macros, emit .extern directives for |
8090 | all small-data externs so that the assembler knows how | |
8091 | big they are. | |
8092 | ||
8093 | In most cases it would be safe (though pointless) to emit | |
8094 | .externs for other symbols too. One exception is when an | |
8095 | object is within the -G limit but declared by the user to | |
8096 | be in a section other than .sbss or .sdata. */ | |
f8fdb503 L |
8097 | fputs ("\t.extern\t", file); |
8098 | assemble_name (file, name); | |
8099 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n", | |
8100 | int_size_in_bytes (TREE_TYPE (decl))); | |
8101 | } | |
6773a41c | 8102 | } |
cee98a59 | 8103 | } |
65239d20 | 8104 | |
b5f5d41d | 8105 | /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */ |
cee98a59 | 8106 | |
b5f5d41d | 8107 | static void |
b4966b1b | 8108 | mips_output_filename (FILE *stream, const char *name) |
cee98a59 | 8109 | { |
8b0397a6 DJ |
8110 | /* If we are emitting DWARF-2, let dwarf2out handle the ".file" |
8111 | directives. */ | |
8112 | if (write_symbols == DWARF2_DEBUG) | |
8113 | return; | |
cafe096b | 8114 | else if (mips_output_filename_first_time) |
cee98a59 | 8115 | { |
cafe096b | 8116 | mips_output_filename_first_time = 0; |
82563d35 | 8117 | num_source_filenames += 1; |
cee98a59 | 8118 | current_function_file = name; |
3e487b21 ZW |
8119 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
8120 | output_quoted_string (stream, name); | |
8121 | putc ('\n', stream); | |
cee98a59 | 8122 | } |
3e487b21 ZW |
8123 | /* If we are emitting stabs, let dbxout.c handle this (except for |
8124 | the mips_output_filename_first_time case). */ | |
2bacb292 | 8125 | else if (write_symbols == DBX_DEBUG) |
3e487b21 | 8126 | return; |
cee98a59 | 8127 | else if (name != current_function_file |
d82783b6 | 8128 | && strcmp (name, current_function_file) != 0) |
cee98a59 | 8129 | { |
82563d35 | 8130 | num_source_filenames += 1; |
d82783b6 | 8131 | current_function_file = name; |
3e487b21 ZW |
8132 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
8133 | output_quoted_string (stream, name); | |
8134 | putc ('\n', stream); | |
cee98a59 MM |
8135 | } |
8136 | } | |
ab77a036 | 8137 | |
65239d20 | 8138 | /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
ab77a036 | 8139 | |
9a4a025a | 8140 | static void ATTRIBUTE_UNUSED |
ab77a036 RS |
8141 | mips_output_dwarf_dtprel (FILE *file, int size, rtx x) |
8142 | { | |
8143 | switch (size) | |
8144 | { | |
8145 | case 4: | |
8146 | fputs ("\t.dtprelword\t", file); | |
8147 | break; | |
8148 | ||
8149 | case 8: | |
8150 | fputs ("\t.dtpreldword\t", file); | |
8151 | break; | |
8152 | ||
8153 | default: | |
8154 | gcc_unreachable (); | |
8155 | } | |
8156 | output_addr_const (file, x); | |
8157 | fputs ("+0x8000", file); | |
8158 | } | |
8159 | ||
8160 | /* Implement TARGET_DWARF_REGISTER_SPAN. */ | |
8161 | ||
8162 | static rtx | |
8163 | mips_dwarf_register_span (rtx reg) | |
8164 | { | |
8165 | rtx high, low; | |
8166 | enum machine_mode mode; | |
8167 | ||
8168 | /* By default, GCC maps increasing register numbers to increasing | |
8169 | memory locations, but paired FPRs are always little-endian, | |
8170 | regardless of the prevailing endianness. */ | |
8171 | mode = GET_MODE (reg); | |
8172 | if (FP_REG_P (REGNO (reg)) | |
8173 | && TARGET_BIG_ENDIAN | |
8174 | && MAX_FPRS_PER_FMT > 1 | |
8175 | && GET_MODE_SIZE (mode) > UNITS_PER_FPREG) | |
8176 | { | |
8177 | gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE); | |
8178 | high = mips_subword (reg, true); | |
8179 | low = mips_subword (reg, false); | |
8180 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low)); | |
8181 | } | |
8182 | ||
8183 | return NULL_RTX; | |
8184 | } | |
65239d20 RS |
8185 | |
8186 | /* Implement ASM_OUTPUT_ASCII. */ | |
b3276c7a | 8187 | |
7dac2f89 | 8188 | void |
65239d20 | 8189 | mips_output_ascii (FILE *stream, const char *string, size_t len) |
b3276c7a GK |
8190 | { |
8191 | size_t i; | |
65239d20 | 8192 | int cur_pos; |
b3276c7a | 8193 | |
65239d20 RS |
8194 | cur_pos = 17; |
8195 | fprintf (stream, "\t.ascii\t\""); | |
7dac2f89 EC |
8196 | for (i = 0; i < len; i++) |
8197 | { | |
65239d20 | 8198 | int c; |
7dac2f89 | 8199 | |
65239d20 | 8200 | c = (unsigned char) string[i]; |
c5ff069d | 8201 | if (ISPRINT (c)) |
7dac2f89 | 8202 | { |
c5ff069d | 8203 | if (c == '\\' || c == '\"') |
7dac2f89 | 8204 | { |
c5ff069d | 8205 | putc ('\\', stream); |
7dac2f89 EC |
8206 | cur_pos++; |
8207 | } | |
c5ff069d ZW |
8208 | putc (c, stream); |
8209 | cur_pos++; | |
8210 | } | |
8211 | else | |
8212 | { | |
8213 | fprintf (stream, "\\%03o", c); | |
8214 | cur_pos += 4; | |
7dac2f89 EC |
8215 | } |
8216 | ||
8217 | if (cur_pos > 72 && i+1 < len) | |
8218 | { | |
8219 | cur_pos = 17; | |
65239d20 | 8220 | fprintf (stream, "\"\n\t.ascii\t\""); |
7dac2f89 EC |
8221 | } |
8222 | } | |
8223 | fprintf (stream, "\"\n"); | |
b3276c7a | 8224 | } |
65239d20 | 8225 | |
ddaf8125 RS |
8226 | /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR. |
8227 | Update *ADDR with the operand that should be printed. */ | |
8228 | ||
8229 | const char * | |
8230 | mips_output_tls_reloc_directive (rtx *addr) | |
8231 | { | |
8232 | enum mips_symbol_type type; | |
8233 | ||
8234 | type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA); | |
8235 | *addr = mips_strip_unspec_address (*addr); | |
8236 | switch (type) | |
8237 | { | |
8238 | case SYMBOL_DTPREL: | |
8239 | return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0"; | |
8240 | ||
8241 | case SYMBOL_TPREL: | |
8242 | return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0"; | |
8243 | ||
8244 | default: | |
8245 | gcc_unreachable (); | |
8246 | } | |
8247 | } | |
8248 | ||
ab77a036 | 8249 | /* Emit either a label, .comm, or .lcomm directive. When using assembler |
65239d20 RS |
8250 | macros, mark the symbol as written so that mips_asm_output_external |
8251 | won't emit an .extern for it. STREAM is the output file, NAME is the | |
8252 | name of the symbol, INIT_STRING is the string that should be written | |
8253 | before the symbol and FINAL_STRING is the string that should be | |
8254 | written after it. FINAL_STRING is a printf format that consumes the | |
8255 | remaining arguments. */ | |
35f5add9 RS |
8256 | |
8257 | void | |
ab77a036 RS |
8258 | mips_declare_object (FILE *stream, const char *name, const char *init_string, |
8259 | const char *final_string, ...) | |
35f5add9 | 8260 | { |
ab77a036 | 8261 | va_list ap; |
35f5add9 | 8262 | |
ab77a036 RS |
8263 | fputs (init_string, stream); |
8264 | assemble_name (stream, name); | |
8265 | va_start (ap, final_string); | |
8266 | vfprintf (stream, final_string, ap); | |
8267 | va_end (ap); | |
8268 | ||
8269 | if (!TARGET_EXPLICIT_RELOCS) | |
8270 | { | |
8271 | tree name_tree = get_identifier (name); | |
8272 | TREE_ASM_WRITTEN (name_tree) = 1; | |
35f5add9 | 8273 | } |
48b2e0a7 RS |
8274 | } |
8275 | ||
8276 | /* Declare a common object of SIZE bytes using asm directive INIT_STRING. | |
8277 | NAME is the name of the object and ALIGN is the required alignment | |
8278 | in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third | |
8279 | alignment argument. */ | |
8280 | ||
8281 | void | |
8282 | mips_declare_common_object (FILE *stream, const char *name, | |
8283 | const char *init_string, | |
8284 | unsigned HOST_WIDE_INT size, | |
8285 | unsigned int align, bool takes_alignment_p) | |
8286 | { | |
8287 | if (!takes_alignment_p) | |
35f5add9 | 8288 | { |
35f5add9 RS |
8289 | size += (align / BITS_PER_UNIT) - 1; |
8290 | size -= size % (align / BITS_PER_UNIT); | |
48b2e0a7 | 8291 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
8292 | "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size); |
8293 | } | |
8294 | else | |
48b2e0a7 | 8295 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
8296 | "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n", |
8297 | size, align / BITS_PER_UNIT); | |
8298 | } | |
8299 | ||
ab77a036 RS |
8300 | /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the |
8301 | elfos.h version, but we also need to handle -muninit-const-in-rodata. */ | |
9987501f MM |
8302 | |
8303 | void | |
ab77a036 RS |
8304 | mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name, |
8305 | unsigned HOST_WIDE_INT size, | |
8306 | unsigned int align) | |
9987501f | 8307 | { |
ab77a036 RS |
8308 | /* If the target wants uninitialized const declarations in |
8309 | .rdata then don't put them in .comm. */ | |
65239d20 RS |
8310 | if (TARGET_EMBEDDED_DATA |
8311 | && TARGET_UNINIT_CONST_IN_RODATA | |
8312 | && TREE_CODE (decl) == VAR_DECL | |
8313 | && TREE_READONLY (decl) | |
ab77a036 | 8314 | && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) |
9987501f | 8315 | { |
ab77a036 RS |
8316 | if (TREE_PUBLIC (decl) && DECL_NAME (decl)) |
8317 | targetm.asm_out.globalize_label (stream, name); | |
8318 | ||
8319 | switch_to_section (readonly_data_section); | |
8320 | ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); | |
8321 | mips_declare_object (stream, name, "", | |
8322 | ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", | |
8323 | size); | |
9987501f | 8324 | } |
ab77a036 RS |
8325 | else |
8326 | mips_declare_common_object (stream, name, "\n\t.comm\t", | |
8327 | size, align, true); | |
9987501f | 8328 | } |
c1115ccd RS |
8329 | |
8330 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8331 | extern int size_directive_output; | |
8332 | ||
8333 | /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF | |
65239d20 | 8334 | definitions except that it uses mips_declare_object to emit the label. */ |
c1115ccd RS |
8335 | |
8336 | void | |
b4966b1b RS |
8337 | mips_declare_object_name (FILE *stream, const char *name, |
8338 | tree decl ATTRIBUTE_UNUSED) | |
c1115ccd RS |
8339 | { |
8340 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
82563d35 | 8341 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); |
c1115ccd RS |
8342 | #endif |
8343 | ||
82563d35 RS |
8344 | size_directive_output = 0; |
8345 | if (!flag_inhibit_size_directive && DECL_SIZE (decl)) | |
8346 | { | |
8347 | HOST_WIDE_INT size; | |
c1115ccd | 8348 | |
82563d35 RS |
8349 | size_directive_output = 1; |
8350 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8351 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
c1115ccd RS |
8352 | } |
8353 | ||
99a3237a | 8354 | mips_declare_object (stream, name, "", ":\n"); |
c1115ccd RS |
8355 | } |
8356 | ||
8357 | /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */ | |
8358 | ||
8359 | void | |
b4966b1b | 8360 | mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end) |
c1115ccd RS |
8361 | { |
8362 | const char *name; | |
8363 | ||
8364 | name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
82563d35 | 8365 | if (!flag_inhibit_size_directive |
c1115ccd | 8366 | && DECL_SIZE (decl) != 0 |
65239d20 RS |
8367 | && !at_end |
8368 | && top_level | |
c1115ccd RS |
8369 | && DECL_INITIAL (decl) == error_mark_node |
8370 | && !size_directive_output) | |
8371 | { | |
8372 | HOST_WIDE_INT size; | |
8373 | ||
8374 | size_directive_output = 1; | |
8375 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8376 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8377 | } | |
8378 | } | |
8379 | #endif | |
dbe9742d | 8380 | \f |
5f5fe6d9 RS |
8381 | /* Return the FOO in the name of the ".mdebug.FOO" section associated |
8382 | with the current ABI. */ | |
8383 | ||
8384 | static const char * | |
8385 | mips_mdebug_abi_name (void) | |
8386 | { | |
8387 | switch (mips_abi) | |
8388 | { | |
8389 | case ABI_32: | |
8390 | return "abi32"; | |
8391 | case ABI_O64: | |
8392 | return "abiO64"; | |
8393 | case ABI_N32: | |
8394 | return "abiN32"; | |
8395 | case ABI_64: | |
63553059 | 8396 | return "abi64"; |
5f5fe6d9 RS |
8397 | case ABI_EABI: |
8398 | return TARGET_64BIT ? "eabi64" : "eabi32"; | |
8399 | default: | |
8400 | gcc_unreachable (); | |
8401 | } | |
8402 | } | |
8403 | ||
ab77a036 | 8404 | /* Implement TARGET_ASM_FILE_START. */ |
108b61d5 | 8405 | |
ab77a036 RS |
8406 | static void |
8407 | mips_file_start (void) | |
108b61d5 | 8408 | { |
ab77a036 | 8409 | default_file_start (); |
108b61d5 | 8410 | |
65239d20 RS |
8411 | /* Generate a special section to describe the ABI switches used to |
8412 | produce the resultant binary. This is unnecessary on IRIX and | |
8413 | causes unwanted warnings from the native linker. */ | |
9aaa1ee8 | 8414 | if (!TARGET_IRIX6) |
ab77a036 | 8415 | { |
65239d20 RS |
8416 | /* Record the ABI itself. Modern versions of binutils encode |
8417 | this information in the ELF header flags, but GDB needs the | |
8418 | information in order to correctly debug binaries produced by | |
8419 | older binutils. See the function mips_gdbarch_init in | |
8420 | gdb/mips-tdep.c. */ | |
ab77a036 | 8421 | fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n", |
5f5fe6d9 | 8422 | mips_mdebug_abi_name ()); |
280fcbfa | 8423 | |
ab77a036 RS |
8424 | /* There is no ELF header flag to distinguish long32 forms of the |
8425 | EABI from long64 forms. Emit a special section to help tools | |
8426 | such as GDB. Do the same for o64, which is sometimes used with | |
8427 | -mlong64. */ | |
8428 | if (mips_abi == ABI_EABI || mips_abi == ABI_O64) | |
8429 | fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n" | |
8430 | "\t.previous\n", TARGET_LONG64 ? 64 : 32); | |
108b61d5 | 8431 | |
ab77a036 | 8432 | #ifdef HAVE_AS_GNU_ATTRIBUTE |
9f946bc1 RS |
8433 | { |
8434 | int attr; | |
8435 | ||
8436 | /* No floating-point operations, -mno-float. */ | |
8437 | if (TARGET_NO_FLOAT) | |
8438 | attr = 0; | |
8439 | /* Soft-float code, -msoft-float. */ | |
8440 | else if (!TARGET_HARD_FLOAT_ABI) | |
8441 | attr = 3; | |
8442 | /* Single-float code, -msingle-float. */ | |
8443 | else if (!TARGET_DOUBLE_FLOAT) | |
8444 | attr = 2; | |
8445 | /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */ | |
8446 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
8447 | attr = 4; | |
8448 | /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */ | |
8449 | else | |
8450 | attr = 1; | |
8451 | ||
8452 | fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr); | |
8453 | } | |
ab77a036 | 8454 | #endif |
280fcbfa RS |
8455 | } |
8456 | ||
65239d20 | 8457 | /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */ |
ab77a036 | 8458 | if (TARGET_ABICALLS) |
e21d5757 DJ |
8459 | { |
8460 | fprintf (asm_out_file, "\t.abicalls\n"); | |
8461 | if (TARGET_ABICALLS_PIC0) | |
8462 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
8463 | } | |
108b61d5 | 8464 | |
ab77a036 RS |
8465 | if (flag_verbose_asm) |
8466 | fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", | |
8467 | ASM_COMMENT_START, | |
65239d20 | 8468 | mips_small_data_threshold, mips_arch_info->name, mips_isa); |
108b61d5 RS |
8469 | } |
8470 | \f | |
65239d20 | 8471 | /* Make the last instruction frame-related and note that it performs |
ab77a036 | 8472 | the operation described by FRAME_PATTERN. */ |
108b61d5 | 8473 | |
ab77a036 RS |
8474 | static void |
8475 | mips_set_frame_expr (rtx frame_pattern) | |
108b61d5 | 8476 | { |
ab77a036 | 8477 | rtx insn; |
280fcbfa | 8478 | |
ab77a036 RS |
8479 | insn = get_last_insn (); |
8480 | RTX_FRAME_RELATED_P (insn) = 1; | |
8481 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8482 | frame_pattern, | |
8483 | REG_NOTES (insn)); | |
8484 | } | |
280fcbfa | 8485 | |
ab77a036 RS |
8486 | /* Return a frame-related rtx that stores REG at MEM. |
8487 | REG must be a single register. */ | |
108b61d5 | 8488 | |
ab77a036 RS |
8489 | static rtx |
8490 | mips_frame_set (rtx mem, rtx reg) | |
8491 | { | |
8492 | rtx set; | |
108b61d5 | 8493 | |
ab77a036 RS |
8494 | set = gen_rtx_SET (VOIDmode, mem, reg); |
8495 | RTX_FRAME_RELATED_P (set) = 1; | |
a38e0142 | 8496 | |
ab77a036 | 8497 | return set; |
a38e0142 | 8498 | } |
a7449961 BS |
8499 | |
8500 | /* Record that the epilogue has restored call-saved register REG. */ | |
8501 | ||
8502 | static void | |
8503 | mips_add_cfa_restore (rtx reg) | |
8504 | { | |
8505 | mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, | |
8506 | mips_epilogue.cfa_restores); | |
8507 | } | |
ab77a036 RS |
8508 | \f |
8509 | /* If a MIPS16e SAVE or RESTORE instruction saves or restores register | |
8510 | mips16e_s2_s8_regs[X], it must also save the registers in indexes | |
8511 | X + 1 onwards. Likewise mips16e_a0_a3_regs. */ | |
8512 | static const unsigned char mips16e_s2_s8_regs[] = { | |
8513 | 30, 23, 22, 21, 20, 19, 18 | |
8514 | }; | |
8515 | static const unsigned char mips16e_a0_a3_regs[] = { | |
8516 | 4, 5, 6, 7 | |
8517 | }; | |
a38e0142 | 8518 | |
ab77a036 RS |
8519 | /* A list of the registers that can be saved by the MIPS16e SAVE instruction, |
8520 | ordered from the uppermost in memory to the lowest in memory. */ | |
8521 | static const unsigned char mips16e_save_restore_regs[] = { | |
8522 | 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4 | |
8523 | }; | |
f833ffd4 | 8524 | |
e1260576 RS |
8525 | /* Return the index of the lowest X in the range [0, SIZE) for which |
8526 | bit REGS[X] is set in MASK. Return SIZE if there is no such X. */ | |
8527 | ||
8528 | static unsigned int | |
8529 | mips16e_find_first_register (unsigned int mask, const unsigned char *regs, | |
8530 | unsigned int size) | |
8531 | { | |
8532 | unsigned int i; | |
8533 | ||
8534 | for (i = 0; i < size; i++) | |
8535 | if (BITSET_P (mask, regs[i])) | |
8536 | break; | |
8537 | ||
8538 | return i; | |
8539 | } | |
8540 | ||
37017f4d RS |
8541 | /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR |
8542 | is the number of set bits. If *MASK_PTR contains REGS[X] for some X | |
8543 | in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same | |
8544 | is true for all indexes (X, SIZE). */ | |
e1260576 RS |
8545 | |
8546 | static void | |
8547 | mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs, | |
37017f4d | 8548 | unsigned int size, unsigned int *num_regs_ptr) |
e1260576 RS |
8549 | { |
8550 | unsigned int i; | |
8551 | ||
8552 | i = mips16e_find_first_register (*mask_ptr, regs, size); | |
8553 | for (i++; i < size; i++) | |
8554 | if (!BITSET_P (*mask_ptr, regs[i])) | |
8555 | { | |
37017f4d | 8556 | *num_regs_ptr += 1; |
e1260576 RS |
8557 | *mask_ptr |= 1 << regs[i]; |
8558 | } | |
8559 | } | |
f833ffd4 | 8560 | |
ab77a036 RS |
8561 | /* Return a simplified form of X using the register values in REG_VALUES. |
8562 | REG_VALUES[R] is the last value assigned to hard register R, or null | |
8563 | if R has not been modified. | |
cee98a59 | 8564 | |
ab77a036 | 8565 | This function is rather limited, but is good enough for our purposes. */ |
cee98a59 | 8566 | |
ab77a036 RS |
8567 | static rtx |
8568 | mips16e_collect_propagate_value (rtx x, rtx *reg_values) | |
cee98a59 | 8569 | { |
ab77a036 | 8570 | x = avoid_constant_pool_reference (x); |
cee98a59 | 8571 | |
ab77a036 | 8572 | if (UNARY_P (x)) |
9e800206 | 8573 | { |
65239d20 | 8574 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
ab77a036 RS |
8575 | return simplify_gen_unary (GET_CODE (x), GET_MODE (x), |
8576 | x0, GET_MODE (XEXP (x, 0))); | |
9e800206 RH |
8577 | } |
8578 | ||
ab77a036 | 8579 | if (ARITHMETIC_P (x)) |
e1260576 | 8580 | { |
65239d20 RS |
8581 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
8582 | rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values); | |
ab77a036 | 8583 | return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1); |
e1260576 RS |
8584 | } |
8585 | ||
ab77a036 RS |
8586 | if (REG_P (x) |
8587 | && reg_values[REGNO (x)] | |
8588 | && !rtx_unstable_p (reg_values[REGNO (x)])) | |
8589 | return reg_values[REGNO (x)]; | |
cee98a59 | 8590 | |
ab77a036 RS |
8591 | return x; |
8592 | } | |
33563487 | 8593 | |
ab77a036 RS |
8594 | /* Return true if (set DEST SRC) stores an argument register into its |
8595 | caller-allocated save slot, storing the number of that argument | |
8596 | register in *REGNO_PTR if so. REG_VALUES is as for | |
8597 | mips16e_collect_propagate_value. */ | |
cee98a59 | 8598 | |
ab77a036 RS |
8599 | static bool |
8600 | mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values, | |
8601 | unsigned int *regno_ptr) | |
8602 | { | |
8603 | unsigned int argno, regno; | |
8604 | HOST_WIDE_INT offset, required_offset; | |
8605 | rtx addr, base; | |
2bcb2ab3 | 8606 | |
ab77a036 RS |
8607 | /* Check that this is a word-mode store. */ |
8608 | if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode) | |
8609 | return false; | |
258d81a8 | 8610 | |
ab77a036 RS |
8611 | /* Check that the register being saved is an unmodified argument |
8612 | register. */ | |
8613 | regno = REGNO (src); | |
65239d20 | 8614 | if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno]) |
ab77a036 RS |
8615 | return false; |
8616 | argno = regno - GP_ARG_FIRST; | |
e88fb323 | 8617 | |
65239d20 RS |
8618 | /* Check whether the address is an appropriate stack-pointer or |
8619 | frame-pointer access. */ | |
ab77a036 RS |
8620 | addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values); |
8621 | mips_split_plus (addr, &base, &offset); | |
8622 | required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD; | |
8623 | if (base == hard_frame_pointer_rtx) | |
f374e413 | 8624 | required_offset -= cfun->machine->frame.hard_frame_pointer_offset; |
ab77a036 RS |
8625 | else if (base != stack_pointer_rtx) |
8626 | return false; | |
8627 | if (offset != required_offset) | |
8628 | return false; | |
cee98a59 | 8629 | |
ab77a036 RS |
8630 | *regno_ptr = regno; |
8631 | return true; | |
cee98a59 | 8632 | } |
b2471838 | 8633 | |
ab77a036 RS |
8634 | /* A subroutine of mips_expand_prologue, called only when generating |
8635 | MIPS16e SAVE instructions. Search the start of the function for any | |
8636 | instructions that save argument registers into their caller-allocated | |
8637 | save slots. Delete such instructions and return a value N such that | |
8638 | saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted | |
8639 | instructions redundant. */ | |
b2471838 | 8640 | |
ab77a036 RS |
8641 | static unsigned int |
8642 | mips16e_collect_argument_saves (void) | |
8643 | { | |
8644 | rtx reg_values[FIRST_PSEUDO_REGISTER]; | |
8645 | rtx insn, next, set, dest, src; | |
8646 | unsigned int nargs, regno; | |
84879759 | 8647 | |
ab77a036 RS |
8648 | push_topmost_sequence (); |
8649 | nargs = 0; | |
8650 | memset (reg_values, 0, sizeof (reg_values)); | |
8651 | for (insn = get_insns (); insn; insn = next) | |
b2471838 | 8652 | { |
ab77a036 | 8653 | next = NEXT_INSN (insn); |
006b29ab | 8654 | if (NOTE_P (insn) || DEBUG_INSN_P (insn)) |
ab77a036 | 8655 | continue; |
b2471838 | 8656 | |
ab77a036 RS |
8657 | if (!INSN_P (insn)) |
8658 | break; | |
b2471838 | 8659 | |
ab77a036 RS |
8660 | set = PATTERN (insn); |
8661 | if (GET_CODE (set) != SET) | |
8662 | break; | |
8663 | ||
8664 | dest = SET_DEST (set); | |
8665 | src = SET_SRC (set); | |
8666 | if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no)) | |
8667 | { | |
8668 | if (!BITSET_P (cfun->machine->frame.mask, regno)) | |
8669 | { | |
8670 | delete_insn (insn); | |
8671 | nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1); | |
8672 | } | |
8673 | } | |
8674 | else if (REG_P (dest) && GET_MODE (dest) == word_mode) | |
8675 | reg_values[REGNO (dest)] | |
8676 | = mips16e_collect_propagate_value (src, reg_values); | |
8677 | else | |
8678 | break; | |
b2471838 | 8679 | } |
ab77a036 | 8680 | pop_topmost_sequence (); |
b2471838 | 8681 | |
ab77a036 RS |
8682 | return nargs; |
8683 | } | |
b2471838 | 8684 | |
ab77a036 | 8685 | /* Return a move between register REGNO and memory location SP + OFFSET. |
42ae51f4 RS |
8686 | REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE. |
8687 | Make the move a load if RESTORE_P, otherwise make it a store. */ | |
67070ffe | 8688 | |
ab77a036 | 8689 | static rtx |
42ae51f4 RS |
8690 | mips16e_save_restore_reg (bool restore_p, bool reg_parm_p, |
8691 | HOST_WIDE_INT offset, unsigned int regno) | |
67070ffe | 8692 | { |
ab77a036 | 8693 | rtx reg, mem; |
1cbfdb1f | 8694 | |
ab77a036 RS |
8695 | mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset)); |
8696 | reg = gen_rtx_REG (SImode, regno); | |
42ae51f4 | 8697 | if (restore_p) |
3bd0817d | 8698 | { |
a7449961 | 8699 | mips_add_cfa_restore (reg); |
3bd0817d RS |
8700 | return gen_rtx_SET (VOIDmode, reg, mem); |
8701 | } | |
42ae51f4 RS |
8702 | if (reg_parm_p) |
8703 | return gen_rtx_SET (VOIDmode, mem, reg); | |
8704 | return mips_frame_set (mem, reg); | |
1cbfdb1f RS |
8705 | } |
8706 | ||
ab77a036 RS |
8707 | /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which. |
8708 | The instruction must: | |
1cbfdb1f | 8709 | |
ab77a036 RS |
8710 | - Allocate or deallocate SIZE bytes in total; SIZE is known |
8711 | to be nonzero. | |
cee98a59 | 8712 | |
ab77a036 RS |
8713 | - Save or restore as many registers in *MASK_PTR as possible. |
8714 | The instruction saves the first registers at the top of the | |
8715 | allocated area, with the other registers below it. | |
cee98a59 | 8716 | |
ab77a036 | 8717 | - Save NARGS argument registers above the allocated area. |
b85aed9e | 8718 | |
ab77a036 | 8719 | (NARGS is always zero if RESTORE_P.) |
b85aed9e | 8720 | |
ab77a036 RS |
8721 | The SAVE and RESTORE instructions cannot save and restore all general |
8722 | registers, so there may be some registers left over for the caller to | |
8723 | handle. Destructively modify *MASK_PTR so that it contains the registers | |
8724 | that still need to be saved or restored. The caller can save these | |
8725 | registers in the memory immediately below *OFFSET_PTR, which is a | |
8726 | byte offset from the bottom of the allocated stack area. */ | |
d9870b7e | 8727 | |
ab77a036 RS |
8728 | static rtx |
8729 | mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr, | |
8730 | HOST_WIDE_INT *offset_ptr, unsigned int nargs, | |
8731 | HOST_WIDE_INT size) | |
d9870b7e | 8732 | { |
ab77a036 RS |
8733 | rtx pattern, set; |
8734 | HOST_WIDE_INT offset, top_offset; | |
8735 | unsigned int i, regno; | |
8736 | int n; | |
8cb6400c | 8737 | |
ddc4af9c | 8738 | gcc_assert (cfun->machine->frame.num_fp == 0); |
d9870b7e | 8739 | |
ab77a036 RS |
8740 | /* Calculate the number of elements in the PARALLEL. We need one element |
8741 | for the stack adjustment, one for each argument register save, and one | |
8742 | for each additional register move. */ | |
8743 | n = 1 + nargs; | |
8744 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
8745 | if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i])) | |
8746 | n++; | |
d9870b7e | 8747 | |
ab77a036 RS |
8748 | /* Create the final PARALLEL. */ |
8749 | pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n)); | |
8750 | n = 0; | |
d9870b7e | 8751 | |
ab77a036 RS |
8752 | /* Add the stack pointer adjustment. */ |
8753 | set = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8754 | plus_constant (stack_pointer_rtx, | |
8755 | restore_p ? size : -size)); | |
8756 | RTX_FRAME_RELATED_P (set) = 1; | |
8757 | XVECEXP (pattern, 0, n++) = set; | |
d9870b7e | 8758 | |
ab77a036 RS |
8759 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
8760 | top_offset = restore_p ? size : 0; | |
b85aed9e | 8761 | |
ab77a036 RS |
8762 | /* Save the arguments. */ |
8763 | for (i = 0; i < nargs; i++) | |
8764 | { | |
6e75e6e3 | 8765 | offset = top_offset + i * UNITS_PER_WORD; |
42ae51f4 RS |
8766 | set = mips16e_save_restore_reg (restore_p, true, offset, |
8767 | GP_ARG_FIRST + i); | |
ab77a036 RS |
8768 | XVECEXP (pattern, 0, n++) = set; |
8769 | } | |
d9870b7e | 8770 | |
ab77a036 RS |
8771 | /* Then fill in the other register moves. */ |
8772 | offset = top_offset; | |
8773 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
b85aed9e | 8774 | { |
ab77a036 RS |
8775 | regno = mips16e_save_restore_regs[i]; |
8776 | if (BITSET_P (*mask_ptr, regno)) | |
d9870b7e | 8777 | { |
ab77a036 | 8778 | offset -= UNITS_PER_WORD; |
42ae51f4 | 8779 | set = mips16e_save_restore_reg (restore_p, false, offset, regno); |
ab77a036 RS |
8780 | XVECEXP (pattern, 0, n++) = set; |
8781 | *mask_ptr &= ~(1 << regno); | |
d9870b7e | 8782 | } |
ab77a036 | 8783 | } |
b85aed9e | 8784 | |
ab77a036 | 8785 | /* Tell the caller what offset it should use for the remaining registers. */ |
b87bc4e8 | 8786 | *offset_ptr = size + (offset - top_offset); |
d9870b7e | 8787 | |
ab77a036 | 8788 | gcc_assert (n == XVECLEN (pattern, 0)); |
8cb6400c | 8789 | |
ab77a036 | 8790 | return pattern; |
b85aed9e RS |
8791 | } |
8792 | ||
ab77a036 RS |
8793 | /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack |
8794 | pointer. Return true if PATTERN matches the kind of instruction | |
8795 | generated by mips16e_build_save_restore. If INFO is nonnull, | |
8796 | initialize it when returning true. */ | |
cee98a59 | 8797 | |
ab77a036 RS |
8798 | bool |
8799 | mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust, | |
8800 | struct mips16e_save_restore_info *info) | |
cee98a59 | 8801 | { |
37017f4d RS |
8802 | unsigned int i, nargs, mask, extra; |
8803 | HOST_WIDE_INT top_offset, save_offset, offset; | |
ab77a036 RS |
8804 | rtx set, reg, mem, base; |
8805 | int n; | |
cee98a59 | 8806 | |
ab77a036 RS |
8807 | if (!GENERATE_MIPS16E_SAVE_RESTORE) |
8808 | return false; | |
2bcb2ab3 | 8809 | |
ab77a036 RS |
8810 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
8811 | top_offset = adjust > 0 ? adjust : 0; | |
f9e4a411 | 8812 | |
ab77a036 | 8813 | /* Interpret all other members of the PARALLEL. */ |
6e75e6e3 | 8814 | save_offset = top_offset - UNITS_PER_WORD; |
ab77a036 RS |
8815 | mask = 0; |
8816 | nargs = 0; | |
8817 | i = 0; | |
8818 | for (n = 1; n < XVECLEN (pattern, 0); n++) | |
e9a25f70 | 8819 | { |
ab77a036 RS |
8820 | /* Check that we have a SET. */ |
8821 | set = XVECEXP (pattern, 0, n); | |
8822 | if (GET_CODE (set) != SET) | |
8823 | return false; | |
3c7404d3 | 8824 | |
ab77a036 RS |
8825 | /* Check that the SET is a load (if restoring) or a store |
8826 | (if saving). */ | |
8827 | mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set); | |
8828 | if (!MEM_P (mem)) | |
8829 | return false; | |
3c7404d3 | 8830 | |
ab77a036 RS |
8831 | /* Check that the address is the sum of the stack pointer and a |
8832 | possibly-zero constant offset. */ | |
8833 | mips_split_plus (XEXP (mem, 0), &base, &offset); | |
8834 | if (base != stack_pointer_rtx) | |
8835 | return false; | |
82563d35 | 8836 | |
ab77a036 RS |
8837 | /* Check that SET's other operand is a register. */ |
8838 | reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set); | |
8839 | if (!REG_P (reg)) | |
8840 | return false; | |
e9a25f70 | 8841 | |
ab77a036 | 8842 | /* Check for argument saves. */ |
6e75e6e3 | 8843 | if (offset == top_offset + nargs * UNITS_PER_WORD |
ab77a036 RS |
8844 | && REGNO (reg) == GP_ARG_FIRST + nargs) |
8845 | nargs++; | |
8846 | else if (offset == save_offset) | |
8847 | { | |
8848 | while (mips16e_save_restore_regs[i++] != REGNO (reg)) | |
8849 | if (i == ARRAY_SIZE (mips16e_save_restore_regs)) | |
8850 | return false; | |
a50f2a09 | 8851 | |
ab77a036 | 8852 | mask |= 1 << REGNO (reg); |
6e75e6e3 | 8853 | save_offset -= UNITS_PER_WORD; |
ab77a036 RS |
8854 | } |
8855 | else | |
8856 | return false; | |
e9a25f70 | 8857 | } |
ffa9d0b1 | 8858 | |
ab77a036 RS |
8859 | /* Check that the restrictions on register ranges are met. */ |
8860 | extra = 0; | |
8861 | mips16e_mask_registers (&mask, mips16e_s2_s8_regs, | |
8862 | ARRAY_SIZE (mips16e_s2_s8_regs), &extra); | |
8863 | mips16e_mask_registers (&mask, mips16e_a0_a3_regs, | |
8864 | ARRAY_SIZE (mips16e_a0_a3_regs), &extra); | |
8865 | if (extra != 0) | |
8866 | return false; | |
8867 | ||
8868 | /* Make sure that the topmost argument register is not saved twice. | |
8869 | The checks above ensure that the same is then true for the other | |
8870 | argument registers. */ | |
8871 | if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1)) | |
8872 | return false; | |
8873 | ||
8874 | /* Pass back information, if requested. */ | |
8875 | if (info) | |
6f2993e5 | 8876 | { |
ab77a036 RS |
8877 | info->nargs = nargs; |
8878 | info->mask = mask; | |
8879 | info->size = (adjust > 0 ? adjust : -adjust); | |
6f2993e5 | 8880 | } |
b85aed9e | 8881 | |
ab77a036 | 8882 | return true; |
f833ffd4 | 8883 | } |
be763023 | 8884 | |
ab77a036 RS |
8885 | /* Add a MIPS16e SAVE or RESTORE register-range argument to string S |
8886 | for the register range [MIN_REG, MAX_REG]. Return a pointer to | |
8887 | the null terminator. */ | |
be763023 | 8888 | |
ab77a036 RS |
8889 | static char * |
8890 | mips16e_add_register_range (char *s, unsigned int min_reg, | |
8891 | unsigned int max_reg) | |
8892 | { | |
8893 | if (min_reg != max_reg) | |
8894 | s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]); | |
8895 | else | |
8896 | s += sprintf (s, ",%s", reg_names[min_reg]); | |
8897 | return s; | |
be763023 RS |
8898 | } |
8899 | ||
ab77a036 RS |
8900 | /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction. |
8901 | PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */ | |
be763023 | 8902 | |
ab77a036 RS |
8903 | const char * |
8904 | mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust) | |
be763023 | 8905 | { |
ab77a036 | 8906 | static char buffer[300]; |
1de2bc2a | 8907 | |
ab77a036 RS |
8908 | struct mips16e_save_restore_info info; |
8909 | unsigned int i, end; | |
8910 | char *s; | |
1de2bc2a | 8911 | |
ab77a036 RS |
8912 | /* Parse the pattern. */ |
8913 | if (!mips16e_save_restore_pattern_p (pattern, adjust, &info)) | |
8914 | gcc_unreachable (); | |
be763023 | 8915 | |
ab77a036 RS |
8916 | /* Add the mnemonic. */ |
8917 | s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t"); | |
8918 | s += strlen (s); | |
be763023 | 8919 | |
ab77a036 RS |
8920 | /* Save the arguments. */ |
8921 | if (info.nargs > 1) | |
8922 | s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST], | |
8923 | reg_names[GP_ARG_FIRST + info.nargs - 1]); | |
8924 | else if (info.nargs == 1) | |
8925 | s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]); | |
be763023 | 8926 | |
ab77a036 RS |
8927 | /* Emit the amount of stack space to allocate or deallocate. */ |
8928 | s += sprintf (s, "%d", (int) info.size); | |
be763023 | 8929 | |
ab77a036 RS |
8930 | /* Save or restore $16. */ |
8931 | if (BITSET_P (info.mask, 16)) | |
8932 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]); | |
936b1317 | 8933 | |
ab77a036 RS |
8934 | /* Save or restore $17. */ |
8935 | if (BITSET_P (info.mask, 17)) | |
8936 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]); | |
be763023 | 8937 | |
ab77a036 RS |
8938 | /* Save or restore registers in the range $s2...$s8, which |
8939 | mips16e_s2_s8_regs lists in decreasing order. Note that this | |
8940 | is a software register range; the hardware registers are not | |
8941 | numbered consecutively. */ | |
8942 | end = ARRAY_SIZE (mips16e_s2_s8_regs); | |
8943 | i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end); | |
8944 | if (i < end) | |
8945 | s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1], | |
8946 | mips16e_s2_s8_regs[i]); | |
be763023 | 8947 | |
ab77a036 RS |
8948 | /* Save or restore registers in the range $a0...$a3. */ |
8949 | end = ARRAY_SIZE (mips16e_a0_a3_regs); | |
8950 | i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end); | |
8951 | if (i < end) | |
8952 | s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i], | |
8953 | mips16e_a0_a3_regs[end - 1]); | |
e1260576 | 8954 | |
ab77a036 | 8955 | /* Save or restore $31. */ |
293593b1 RS |
8956 | if (BITSET_P (info.mask, RETURN_ADDR_REGNUM)) |
8957 | s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]); | |
e1260576 | 8958 | |
ab77a036 | 8959 | return buffer; |
e1260576 | 8960 | } |
ab77a036 | 8961 | \f |
0c433c31 RS |
8962 | /* Return true if the current function returns its value in a floating-point |
8963 | register in MIPS16 mode. */ | |
e1260576 | 8964 | |
ab77a036 | 8965 | static bool |
0c433c31 | 8966 | mips16_cfun_returns_in_fpr_p (void) |
ab77a036 | 8967 | { |
0c433c31 RS |
8968 | tree return_type = DECL_RESULT (current_function_decl); |
8969 | return (TARGET_MIPS16 | |
8970 | && TARGET_HARD_FLOAT_ABI | |
8971 | && !aggregate_value_p (return_type, current_function_decl) | |
8972 | && mips_return_mode_in_fpr_p (DECL_MODE (return_type))); | |
8973 | } | |
e1260576 | 8974 | |
0c433c31 RS |
8975 | /* Return true if predicate PRED is true for at least one instruction. |
8976 | Cache the result in *CACHE, and assume that the result is true | |
8977 | if *CACHE is already true. */ | |
8978 | ||
8979 | static bool | |
8980 | mips_find_gp_ref (bool *cache, bool (*pred) (rtx)) | |
8981 | { | |
8982 | rtx insn; | |
8983 | ||
8984 | if (!*cache) | |
8985 | { | |
ab77a036 RS |
8986 | push_topmost_sequence (); |
8987 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
0c433c31 | 8988 | if (USEFUL_INSN_P (insn) && pred (insn)) |
65239d20 | 8989 | { |
0c433c31 | 8990 | *cache = true; |
65239d20 RS |
8991 | break; |
8992 | } | |
ab77a036 | 8993 | pop_topmost_sequence (); |
ab77a036 | 8994 | } |
0c433c31 | 8995 | return *cache; |
ab77a036 | 8996 | } |
e1260576 | 8997 | |
0c433c31 RS |
8998 | /* Return true if INSN refers to the global pointer in an "inflexible" way. |
8999 | See mips_cfun_has_inflexible_gp_ref_p for details. */ | |
7462a715 RS |
9000 | |
9001 | static bool | |
0c433c31 | 9002 | mips_insn_has_inflexible_gp_ref_p (rtx insn) |
7462a715 | 9003 | { |
0c433c31 RS |
9004 | /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE |
9005 | indicate that the target could be a traditional MIPS | |
9006 | lazily-binding stub. */ | |
9007 | return find_reg_fusage (insn, USE, pic_offset_table_rtx); | |
9008 | } | |
9009 | ||
9010 | /* Return true if the current function refers to the global pointer | |
9011 | in a way that forces $28 to be valid. This means that we can't | |
9012 | change the choice of global pointer, even for NewABI code. | |
9013 | ||
9014 | One example of this (and one which needs several checks) is that | |
9015 | $28 must be valid when calling traditional MIPS lazy-binding stubs. | |
9016 | (This restriction does not apply to PLTs.) */ | |
9017 | ||
9018 | static bool | |
9019 | mips_cfun_has_inflexible_gp_ref_p (void) | |
9020 | { | |
9021 | /* If the function has a nonlocal goto, $28 must hold the correct | |
9022 | global pointer for the target function. That is, the target | |
9023 | of the goto implicitly uses $28. */ | |
9024 | if (crtl->has_nonlocal_goto) | |
9025 | return true; | |
9026 | ||
9027 | if (TARGET_ABICALLS_PIC2) | |
9028 | { | |
9029 | /* Symbolic accesses implicitly use the global pointer unless | |
9030 | -mexplicit-relocs is in effect. JAL macros to symbolic addresses | |
9031 | might go to traditional MIPS lazy-binding stubs. */ | |
9032 | if (!TARGET_EXPLICIT_RELOCS) | |
9033 | return true; | |
9034 | ||
9035 | /* FUNCTION_PROFILER includes a JAL to _mcount, which again | |
9036 | can be lazily-bound. */ | |
9037 | if (crtl->profile) | |
9038 | return true; | |
9039 | ||
9040 | /* MIPS16 functions that return in FPRs need to call an | |
9041 | external libgcc routine. This call is only made explict | |
9042 | during mips_expand_epilogue, and it too might be lazily bound. */ | |
9043 | if (mips16_cfun_returns_in_fpr_p ()) | |
9044 | return true; | |
9045 | } | |
9046 | ||
9047 | return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p, | |
9048 | mips_insn_has_inflexible_gp_ref_p); | |
9049 | } | |
9050 | ||
9051 | /* Return true if INSN refers to the global pointer in a "flexible" way. | |
9052 | See mips_cfun_has_flexible_gp_ref_p for details. */ | |
9053 | ||
9054 | static bool | |
9055 | mips_insn_has_flexible_gp_ref_p (rtx insn) | |
9056 | { | |
9057 | return (get_attr_got (insn) != GOT_UNSET | |
9058 | || mips_small_data_pattern_p (PATTERN (insn)) | |
9059 | || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn))); | |
9060 | } | |
9061 | ||
9062 | /* Return true if the current function references the global pointer, | |
9063 | but if those references do not inherently require the global pointer | |
9064 | to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */ | |
9065 | ||
9066 | static bool | |
9067 | mips_cfun_has_flexible_gp_ref_p (void) | |
9068 | { | |
9069 | /* Reload can sometimes introduce constant pool references | |
9070 | into a function that otherwise didn't need them. For example, | |
9071 | suppose we have an instruction like: | |
9072 | ||
9073 | (set (reg:DF R1) (float:DF (reg:SI R2))) | |
9074 | ||
9075 | If R2 turns out to be a constant such as 1, the instruction may | |
9076 | have a REG_EQUAL note saying that R1 == 1.0. Reload then has | |
9077 | the option of using this constant if R2 doesn't get allocated | |
9078 | to a register. | |
9079 | ||
9080 | In cases like these, reload will have added the constant to the | |
9081 | pool but no instruction will yet refer to it. */ | |
9082 | if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool) | |
9083 | return true; | |
9084 | ||
9085 | return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p, | |
9086 | mips_insn_has_flexible_gp_ref_p); | |
7462a715 RS |
9087 | } |
9088 | ||
ab77a036 | 9089 | /* Return the register that should be used as the global pointer |
8d9d9172 RS |
9090 | within this function. Return INVALID_REGNUM if the function |
9091 | doesn't need a global pointer. */ | |
e1260576 | 9092 | |
ab77a036 RS |
9093 | static unsigned int |
9094 | mips_global_pointer (void) | |
e1260576 | 9095 | { |
ab77a036 | 9096 | unsigned int regno; |
e1260576 | 9097 | |
ab77a036 RS |
9098 | /* $gp is always available unless we're using a GOT. */ |
9099 | if (!TARGET_USE_GOT) | |
9100 | return GLOBAL_POINTER_REGNUM; | |
e1260576 | 9101 | |
0c433c31 RS |
9102 | /* If there are inflexible references to $gp, we must use the |
9103 | standard register. */ | |
9104 | if (mips_cfun_has_inflexible_gp_ref_p ()) | |
ab77a036 | 9105 | return GLOBAL_POINTER_REGNUM; |
e1260576 | 9106 | |
0c433c31 RS |
9107 | /* If there are no current references to $gp, then the only uses |
9108 | we can introduce later are those involved in long branches. */ | |
9109 | if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ()) | |
9110 | return INVALID_REGNUM; | |
e21d5757 | 9111 | |
0c433c31 RS |
9112 | /* If the global pointer is call-saved, try to use a call-clobbered |
9113 | alternative. */ | |
ab77a036 RS |
9114 | if (TARGET_CALL_SAVED_GP && current_function_is_leaf) |
9115 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) | |
9116 | if (!df_regs_ever_live_p (regno) | |
9117 | && call_really_used_regs[regno] | |
9118 | && !fixed_regs[regno] | |
9119 | && regno != PIC_FUNCTION_ADDR_REGNUM) | |
9120 | return regno; | |
e1260576 | 9121 | |
ab77a036 | 9122 | return GLOBAL_POINTER_REGNUM; |
e1260576 RS |
9123 | } |
9124 | ||
293593b1 | 9125 | /* Return true if the current function's prologue must load the global |
0c433c31 RS |
9126 | pointer value into pic_offset_table_rtx and store the same value in |
9127 | the function's cprestore slot (if any). | |
9128 | ||
9129 | One problem we have to deal with is that, when emitting GOT-based | |
9130 | position independent code, long-branch sequences will need to load | |
9131 | the address of the branch target from the GOT. We don't know until | |
9132 | the very end of compilation whether (and where) the function needs | |
9133 | long branches, so we must ensure that _any_ branch can access the | |
9134 | global pointer in some form. However, we do not want to pessimize | |
9135 | the usual case in which all branches are short. | |
9136 | ||
9137 | We handle this as follows: | |
9138 | ||
9139 | (1) During reload, we set cfun->machine->global_pointer to | |
9140 | INVALID_REGNUM if we _know_ that the current function | |
9141 | doesn't need a global pointer. This is only valid if | |
9142 | long branches don't need the GOT. | |
9143 | ||
9144 | Otherwise, we assume that we might need a global pointer | |
9145 | and pick an appropriate register. | |
9146 | ||
9147 | (2) If cfun->machine->global_pointer != INVALID_REGNUM, | |
9148 | we ensure that the global pointer is available at every | |
9149 | block boundary bar entry and exit. We do this in one of two ways: | |
9150 | ||
9151 | - If the function has a cprestore slot, we ensure that this | |
9152 | slot is valid at every branch. However, as explained in | |
9153 | point (6) below, there is no guarantee that pic_offset_table_rtx | |
9154 | itself is valid if new uses of the global pointer are introduced | |
9155 | after the first post-epilogue split. | |
9156 | ||
9157 | We guarantee that the cprestore slot is valid by loading it | |
9158 | into a fake register, CPRESTORE_SLOT_REGNUM. We then make | |
9159 | this register live at every block boundary bar function entry | |
9160 | and exit. It is then invalid to move the load (and thus the | |
9161 | preceding store) across a block boundary. | |
9162 | ||
9163 | - If the function has no cprestore slot, we guarantee that | |
9164 | pic_offset_table_rtx itself is valid at every branch. | |
9165 | ||
9166 | See mips_eh_uses for the handling of the register liveness. | |
9167 | ||
9168 | (3) During prologue and epilogue generation, we emit "ghost" | |
9169 | placeholder instructions to manipulate the global pointer. | |
9170 | ||
9171 | (4) During prologue generation, we set cfun->machine->must_initialize_gp_p | |
9172 | and cfun->machine->must_restore_gp_when_clobbered_p if we already know | |
9173 | that the function needs a global pointer. (There is no need to set | |
9174 | them earlier than this, and doing it as late as possible leads to | |
9175 | fewer false positives.) | |
9176 | ||
9177 | (5) If cfun->machine->must_initialize_gp_p is true during a | |
9178 | split_insns pass, we split the ghost instructions into real | |
9179 | instructions. These split instructions can then be optimized in | |
9180 | the usual way. Otherwise, we keep the ghost instructions intact, | |
9181 | and optimize for the case where they aren't needed. We still | |
9182 | have the option of splitting them later, if we need to introduce | |
9183 | new uses of the global pointer. | |
9184 | ||
9185 | For example, the scheduler ignores a ghost instruction that | |
9186 | stores $28 to the stack, but it handles the split form of | |
9187 | the ghost instruction as an ordinary store. | |
9188 | ||
9189 | (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p | |
9190 | is true during the first post-epilogue split_insns pass, we split | |
9191 | calls and restore_gp patterns into instructions that explicitly | |
9192 | load pic_offset_table_rtx from the cprestore slot. Otherwise, | |
9193 | we split these patterns into instructions that _don't_ load from | |
9194 | the cprestore slot. | |
9195 | ||
9196 | If cfun->machine->must_restore_gp_when_clobbered_p is true at the | |
9197 | time of the split, then any instructions that exist at that time | |
9198 | can make free use of pic_offset_table_rtx. However, if we want | |
9199 | to introduce new uses of the global pointer after the split, | |
9200 | we must explicitly load the value from the cprestore slot, since | |
9201 | pic_offset_table_rtx itself might not be valid at a given point | |
9202 | in the function. | |
9203 | ||
9204 | The idea is that we want to be able to delete redundant | |
9205 | loads from the cprestore slot in the usual case where no | |
9206 | long branches are needed. | |
9207 | ||
9208 | (7) If cfun->machine->must_initialize_gp_p is still false at the end | |
9209 | of md_reorg, we decide whether the global pointer is needed for | |
9210 | long branches. If so, we set cfun->machine->must_initialize_gp_p | |
9211 | to true and split the ghost instructions into real instructions | |
9212 | at that stage. | |
9213 | ||
9214 | Note that the ghost instructions must have a zero length for three reasons: | |
9215 | ||
9216 | - Giving the length of the underlying $gp sequence might cause | |
9217 | us to use long branches in cases where they aren't really needed. | |
9218 | ||
9219 | - They would perturb things like alignment calculations. | |
9220 | ||
9221 | - More importantly, the hazard detection in md_reorg relies on | |
9222 | empty instructions having a zero length. | |
9223 | ||
9224 | If we find a long branch and split the ghost instructions at the | |
9225 | end of md_reorg, the split could introduce more long branches. | |
9226 | That isn't a problem though, because we still do the split before | |
9227 | the final shorten_branches pass. | |
9228 | ||
9229 | This is extremely ugly, but it seems like the best compromise between | |
9230 | correctness and efficiency. */ | |
9231 | ||
9232 | bool | |
9233 | mips_must_initialize_gp_p (void) | |
9234 | { | |
9235 | return cfun->machine->must_initialize_gp_p; | |
9236 | } | |
9237 | ||
e19da24c CF |
9238 | /* Return true if REGNO is a register that is ordinarily call-clobbered |
9239 | but must nevertheless be preserved by an interrupt handler. */ | |
9240 | ||
9241 | static bool | |
9242 | mips_interrupt_extra_call_saved_reg_p (unsigned int regno) | |
9243 | { | |
9244 | if (MD_REG_P (regno)) | |
9245 | return true; | |
9246 | ||
9247 | if (TARGET_DSP && DSP_ACC_REG_P (regno)) | |
9248 | return true; | |
9249 | ||
9250 | if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p) | |
9251 | { | |
9252 | /* $0 is hard-wired. */ | |
9253 | if (regno == GP_REG_FIRST) | |
9254 | return false; | |
9255 | ||
9256 | /* The interrupt handler can treat kernel registers as | |
9257 | scratch registers. */ | |
9258 | if (KERNEL_REG_P (regno)) | |
9259 | return false; | |
9260 | ||
9261 | /* The function will return the stack pointer to its original value | |
9262 | anyway. */ | |
9263 | if (regno == STACK_POINTER_REGNUM) | |
9264 | return false; | |
9265 | ||
9266 | /* Otherwise, return true for registers that aren't ordinarily | |
9267 | call-clobbered. */ | |
9268 | return call_really_used_regs[regno]; | |
9269 | } | |
9270 | ||
9271 | return false; | |
9272 | } | |
9273 | ||
7cc003b5 RS |
9274 | /* Return true if the current function should treat register REGNO |
9275 | as call-saved. */ | |
e1260576 | 9276 | |
ab77a036 | 9277 | static bool |
7cc003b5 RS |
9278 | mips_cfun_call_saved_reg_p (unsigned int regno) |
9279 | { | |
b14ee6c9 RS |
9280 | /* If the user makes an ordinarily-call-saved register global, |
9281 | that register is no longer call-saved. */ | |
9282 | if (global_regs[regno]) | |
9283 | return false; | |
9284 | ||
e19da24c CF |
9285 | /* Interrupt handlers need to save extra registers. */ |
9286 | if (cfun->machine->interrupt_handler_p | |
9287 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
9288 | return true; | |
9289 | ||
7cc003b5 RS |
9290 | /* call_insns preserve $28 unless they explicitly say otherwise, |
9291 | so call_really_used_regs[] treats $28 as call-saved. However, | |
9292 | we want the ABI property rather than the default call_insn | |
9293 | property here. */ | |
9294 | return (regno == GLOBAL_POINTER_REGNUM | |
9295 | ? TARGET_CALL_SAVED_GP | |
9296 | : !call_really_used_regs[regno]); | |
9297 | } | |
9298 | ||
9299 | /* Return true if the function body might clobber register REGNO. | |
9300 | We know that REGNO is call-saved. */ | |
9301 | ||
9302 | static bool | |
9303 | mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno) | |
ab77a036 | 9304 | { |
7cc003b5 RS |
9305 | /* Some functions should be treated as clobbering all call-saved |
9306 | registers. */ | |
9307 | if (crtl->saves_all_registers) | |
4817c43b | 9308 | return true; |
e1260576 | 9309 | |
7cc003b5 RS |
9310 | /* DF handles cases where a register is explicitly referenced in |
9311 | the rtl. Incoming values are passed in call-clobbered registers, | |
9312 | so we can assume that any live call-saved register is set within | |
9313 | the function. */ | |
9314 | if (df_regs_ever_live_p (regno)) | |
ab77a036 | 9315 | return true; |
e1260576 | 9316 | |
7cc003b5 RS |
9317 | /* Check for registers that are clobbered by FUNCTION_PROFILER. |
9318 | These clobbers are not explicit in the rtl. */ | |
9319 | if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno)) | |
9320 | return true; | |
9321 | ||
9322 | /* If we're using a call-saved global pointer, the function's | |
9323 | prologue will need to set it up. */ | |
9324 | if (cfun->machine->global_pointer == regno) | |
ab77a036 | 9325 | return true; |
106b3d40 | 9326 | |
7cc003b5 RS |
9327 | /* The function's prologue will need to set the frame pointer if |
9328 | frame_pointer_needed. */ | |
ab77a036 RS |
9329 | if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) |
9330 | return true; | |
e1260576 | 9331 | |
7cc003b5 RS |
9332 | /* If a MIPS16 function returns a value in FPRs, its epilogue |
9333 | will need to call an external libgcc routine. This yet-to-be | |
9334 | generated call_insn will clobber $31. */ | |
293593b1 | 9335 | if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ()) |
ab77a036 | 9336 | return true; |
e1260576 | 9337 | |
e19da24c CF |
9338 | /* If REGNO is ordinarily call-clobbered, we must assume that any |
9339 | called function could modify it. */ | |
9340 | if (cfun->machine->interrupt_handler_p | |
9341 | && !current_function_is_leaf | |
9342 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
9343 | return true; | |
9344 | ||
7cc003b5 RS |
9345 | return false; |
9346 | } | |
9347 | ||
9348 | /* Return true if the current function must save register REGNO. */ | |
9349 | ||
9350 | static bool | |
9351 | mips_save_reg_p (unsigned int regno) | |
9352 | { | |
9353 | if (mips_cfun_call_saved_reg_p (regno)) | |
9354 | { | |
9355 | if (mips_cfun_might_clobber_call_saved_reg_p (regno)) | |
9356 | return true; | |
9357 | ||
9358 | /* Save both registers in an FPR pair if either one is used. This is | |
9359 | needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd | |
9360 | register to be used without the even register. */ | |
9361 | if (FP_REG_P (regno) | |
9362 | && MAX_FPRS_PER_FMT == 2 | |
9363 | && mips_cfun_might_clobber_call_saved_reg_p (regno + 1)) | |
9364 | return true; | |
9365 | } | |
9366 | ||
9367 | /* We need to save the incoming return address if __builtin_eh_return | |
9368 | is being used to set a different return address. */ | |
293593b1 | 9369 | if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) |
ab77a036 | 9370 | return true; |
e1260576 | 9371 | |
ab77a036 | 9372 | return false; |
e1260576 RS |
9373 | } |
9374 | ||
16dc5c28 | 9375 | /* Populate the current function's mips_frame_info structure. |
e1260576 | 9376 | |
ab77a036 | 9377 | MIPS stack frames look like: |
e1260576 | 9378 | |
37017f4d RS |
9379 | +-------------------------------+ |
9380 | | | | |
9381 | | incoming stack arguments | | |
9382 | | | | |
9383 | +-------------------------------+ | |
9384 | | | | |
9385 | | caller-allocated save area | | |
9386 | A | for register arguments | | |
9387 | | | | |
9388 | +-------------------------------+ <-- incoming stack pointer | |
9389 | | | | |
9390 | | callee-allocated save area | | |
9391 | B | for arguments that are | | |
9392 | | split between registers and | | |
9393 | | the stack | | |
9394 | | | | |
9395 | +-------------------------------+ <-- arg_pointer_rtx | |
9396 | | | | |
9397 | C | callee-allocated save area | | |
9398 | | for register varargs | | |
9399 | | | | |
e19da24c CF |
9400 | +-------------------------------+ <-- frame_pointer_rtx |
9401 | | | + cop0_sp_offset | |
9402 | | COP0 reg save area | + UNITS_PER_WORD | |
9403 | | | | |
9404 | +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset | |
9405 | | | + UNITS_PER_WORD | |
9406 | | accumulator save area | | |
9407 | | | | |
ba6adec4 | 9408 | +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset |
37017f4d RS |
9409 | | | + UNITS_PER_HWFPVALUE |
9410 | | FPR save area | | |
9411 | | | | |
ba6adec4 | 9412 | +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset |
37017f4d RS |
9413 | | | + UNITS_PER_WORD |
9414 | | GPR save area | | |
9415 | | | | |
ba6adec4 AN |
9416 | +-------------------------------+ <-- frame_pointer_rtx with |
9417 | | | \ -fstack-protector | |
37017f4d RS |
9418 | | local variables | | var_size |
9419 | | | / | |
9420 | +-------------------------------+ | |
9421 | | | \ | |
9422 | | $gp save area | | cprestore_size | |
9423 | | | / | |
9424 | P +-------------------------------+ <-- hard_frame_pointer_rtx for | |
ba6adec4 AN |
9425 | | | \ MIPS16 code |
9426 | | outgoing stack arguments | | | |
9427 | | | | | |
9428 | +-------------------------------+ | args_size | |
9429 | | | | | |
9430 | | caller-allocated save area | | | |
9431 | | for register arguments | | | |
9432 | | | / | |
37017f4d | 9433 | +-------------------------------+ <-- stack_pointer_rtx |
ba6adec4 AN |
9434 | frame_pointer_rtx without |
9435 | -fstack-protector | |
37017f4d RS |
9436 | hard_frame_pointer_rtx for |
9437 | non-MIPS16 code. | |
9438 | ||
9439 | At least two of A, B and C will be empty. | |
9440 | ||
9441 | Dynamic stack allocations such as alloca insert data at point P. | |
9442 | They decrease stack_pointer_rtx but leave frame_pointer_rtx and | |
9443 | hard_frame_pointer_rtx unchanged. */ | |
e1260576 | 9444 | |
16dc5c28 RS |
9445 | static void |
9446 | mips_compute_frame_info (void) | |
ab77a036 | 9447 | { |
37017f4d | 9448 | struct mips_frame_info *frame; |
16dc5c28 | 9449 | HOST_WIDE_INT offset, size; |
37017f4d | 9450 | unsigned int regno, i; |
e1260576 | 9451 | |
e19da24c CF |
9452 | /* Set this function's interrupt properties. */ |
9453 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
9454 | { | |
9455 | if (!ISA_MIPS32R2) | |
9456 | error ("the %<interrupt%> attribute requires a MIPS32r2 processor"); | |
9457 | else if (TARGET_HARD_FLOAT) | |
9458 | error ("the %<interrupt%> attribute requires %<-msoft-float%>"); | |
9459 | else if (TARGET_MIPS16) | |
9460 | error ("interrupt handlers cannot be MIPS16 functions"); | |
9461 | else | |
9462 | { | |
9463 | cfun->machine->interrupt_handler_p = true; | |
9464 | cfun->machine->use_shadow_register_set_p = | |
9465 | mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl)); | |
9466 | cfun->machine->keep_interrupts_masked_p = | |
9467 | mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl)); | |
9468 | cfun->machine->use_debug_exception_return_p = | |
9469 | mips_use_debug_exception_return_p (TREE_TYPE | |
9470 | (current_function_decl)); | |
9471 | } | |
9472 | } | |
9473 | ||
37017f4d RS |
9474 | frame = &cfun->machine->frame; |
9475 | memset (frame, 0, sizeof (*frame)); | |
16dc5c28 | 9476 | size = get_frame_size (); |
e1260576 | 9477 | |
37017f4d | 9478 | cfun->machine->global_pointer = mips_global_pointer (); |
e1260576 | 9479 | |
ba6adec4 AN |
9480 | /* The first two blocks contain the outgoing argument area and the $gp save |
9481 | slot. This area isn't needed in leaf functions, but if the | |
9482 | target-independent frame size is nonzero, we have already committed to | |
9483 | allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */ | |
9484 | if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf) | |
37017f4d RS |
9485 | { |
9486 | /* The MIPS 3.0 linker does not like functions that dynamically | |
9487 | allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it | |
9488 | looks like we are trying to create a second frame pointer to the | |
9489 | function, so allocate some stack space to make it happy. */ | |
e3b5732b | 9490 | if (cfun->calls_alloca) |
37017f4d RS |
9491 | frame->args_size = REG_PARM_STACK_SPACE (cfun->decl); |
9492 | else | |
9493 | frame->args_size = 0; | |
9494 | frame->cprestore_size = 0; | |
9495 | } | |
9496 | else | |
9497 | { | |
38173d38 | 9498 | frame->args_size = crtl->outgoing_args_size; |
ba6adec4 | 9499 | frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE; |
37017f4d RS |
9500 | } |
9501 | offset = frame->args_size + frame->cprestore_size; | |
e1260576 | 9502 | |
37017f4d RS |
9503 | /* Move above the local variables. */ |
9504 | frame->var_size = MIPS_STACK_ALIGN (size); | |
9505 | offset += frame->var_size; | |
e1260576 | 9506 | |
37017f4d | 9507 | /* Find out which GPRs we need to save. */ |
ab77a036 RS |
9508 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) |
9509 | if (mips_save_reg_p (regno)) | |
9510 | { | |
37017f4d RS |
9511 | frame->num_gp++; |
9512 | frame->mask |= 1 << (regno - GP_REG_FIRST); | |
ab77a036 | 9513 | } |
e1260576 | 9514 | |
37017f4d RS |
9515 | /* If this function calls eh_return, we must also save and restore the |
9516 | EH data registers. */ | |
e3b5732b | 9517 | if (crtl->calls_eh_return) |
37017f4d RS |
9518 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) |
9519 | { | |
9520 | frame->num_gp++; | |
9521 | frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); | |
9522 | } | |
e1260576 | 9523 | |
ab77a036 RS |
9524 | /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers: |
9525 | $a3-$a0 and $s2-$s8. If we save one register in the range, we must | |
9526 | save all later registers too. */ | |
9527 | if (GENERATE_MIPS16E_SAVE_RESTORE) | |
9528 | { | |
37017f4d RS |
9529 | mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs, |
9530 | ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp); | |
9531 | mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs, | |
9532 | ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp); | |
9533 | } | |
9534 | ||
9535 | /* Move above the GPR save area. */ | |
9536 | if (frame->num_gp > 0) | |
9537 | { | |
ddc4af9c | 9538 | offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD); |
37017f4d | 9539 | frame->gp_sp_offset = offset - UNITS_PER_WORD; |
ab77a036 | 9540 | } |
e1260576 | 9541 | |
37017f4d | 9542 | /* Find out which FPRs we need to save. This loop must iterate over |
e19da24c | 9543 | the same space as its companion in mips_for_each_saved_gpr_and_fpr. */ |
ab77a036 | 9544 | if (TARGET_HARD_FLOAT) |
37017f4d | 9545 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT) |
ab77a036 RS |
9546 | if (mips_save_reg_p (regno)) |
9547 | { | |
37017f4d RS |
9548 | frame->num_fp += MAX_FPRS_PER_FMT; |
9549 | frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST); | |
ab77a036 | 9550 | } |
e1260576 | 9551 | |
37017f4d RS |
9552 | /* Move above the FPR save area. */ |
9553 | if (frame->num_fp > 0) | |
e1260576 | 9554 | { |
ddc4af9c | 9555 | offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG); |
37017f4d | 9556 | frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; |
e1260576 RS |
9557 | } |
9558 | ||
e19da24c CF |
9559 | /* Add in space for the interrupt context information. */ |
9560 | if (cfun->machine->interrupt_handler_p) | |
9561 | { | |
9562 | /* Check HI/LO. */ | |
9563 | if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM)) | |
9564 | { | |
9565 | frame->num_acc++; | |
9566 | frame->acc_mask |= (1 << 0); | |
9567 | } | |
9568 | ||
9569 | /* Check accumulators 1, 2, 3. */ | |
9570 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
9571 | if (mips_save_reg_p (i) || mips_save_reg_p (i + 1)) | |
9572 | { | |
9573 | frame->num_acc++; | |
9574 | frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1); | |
9575 | } | |
9576 | ||
9577 | /* All interrupt context functions need space to preserve STATUS. */ | |
9578 | frame->num_cop0_regs++; | |
9579 | ||
9580 | /* If we don't keep interrupts masked, we need to save EPC. */ | |
9581 | if (!cfun->machine->keep_interrupts_masked_p) | |
9582 | frame->num_cop0_regs++; | |
9583 | } | |
9584 | ||
9585 | /* Move above the accumulator save area. */ | |
9586 | if (frame->num_acc > 0) | |
9587 | { | |
9588 | /* Each accumulator needs 2 words. */ | |
9589 | offset += frame->num_acc * 2 * UNITS_PER_WORD; | |
9590 | frame->acc_sp_offset = offset - UNITS_PER_WORD; | |
9591 | } | |
9592 | ||
9593 | /* Move above the COP0 register save area. */ | |
9594 | if (frame->num_cop0_regs > 0) | |
9595 | { | |
9596 | offset += frame->num_cop0_regs * UNITS_PER_WORD; | |
9597 | frame->cop0_sp_offset = offset - UNITS_PER_WORD; | |
9598 | } | |
9599 | ||
37017f4d RS |
9600 | /* Move above the callee-allocated varargs save area. */ |
9601 | offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size); | |
f374e413 | 9602 | frame->arg_pointer_offset = offset; |
e1260576 | 9603 | |
37017f4d | 9604 | /* Move above the callee-allocated area for pretend stack arguments. */ |
38173d38 | 9605 | offset += crtl->args.pretend_args_size; |
37017f4d RS |
9606 | frame->total_size = offset; |
9607 | ||
9608 | /* Work out the offsets of the save areas from the top of the frame. */ | |
9609 | if (frame->gp_sp_offset > 0) | |
9610 | frame->gp_save_offset = frame->gp_sp_offset - offset; | |
9611 | if (frame->fp_sp_offset > 0) | |
9612 | frame->fp_save_offset = frame->fp_sp_offset - offset; | |
e19da24c CF |
9613 | if (frame->acc_sp_offset > 0) |
9614 | frame->acc_save_offset = frame->acc_sp_offset - offset; | |
9615 | if (frame->num_cop0_regs > 0) | |
9616 | frame->cop0_save_offset = frame->cop0_sp_offset - offset; | |
ab77a036 | 9617 | |
f374e413 RS |
9618 | /* MIPS16 code offsets the frame pointer by the size of the outgoing |
9619 | arguments. This tends to increase the chances of using unextended | |
9620 | instructions for local variables and incoming arguments. */ | |
9621 | if (TARGET_MIPS16) | |
9622 | frame->hard_frame_pointer_offset = frame->args_size; | |
e1260576 RS |
9623 | } |
9624 | ||
ab77a036 RS |
9625 | /* Return the style of GP load sequence that is being used for the |
9626 | current function. */ | |
e1260576 | 9627 | |
ab77a036 RS |
9628 | enum mips_loadgp_style |
9629 | mips_current_loadgp_style (void) | |
e1260576 | 9630 | { |
8d9d9172 | 9631 | if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM) |
ab77a036 | 9632 | return LOADGP_NONE; |
e1260576 | 9633 | |
ab77a036 RS |
9634 | if (TARGET_RTP_PIC) |
9635 | return LOADGP_RTP; | |
e1260576 | 9636 | |
ab77a036 RS |
9637 | if (TARGET_ABSOLUTE_ABICALLS) |
9638 | return LOADGP_ABSOLUTE; | |
e1260576 | 9639 | |
ab77a036 RS |
9640 | return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; |
9641 | } | |
65239d20 | 9642 | |
b52b1749 | 9643 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
29c4d304 | 9644 | |
b52b1749 | 9645 | static bool |
29c4d304 RS |
9646 | mips_frame_pointer_required (void) |
9647 | { | |
9648 | /* If the function contains dynamic stack allocations, we need to | |
9649 | use the frame pointer to access the static parts of the frame. */ | |
e3b5732b | 9650 | if (cfun->calls_alloca) |
29c4d304 RS |
9651 | return true; |
9652 | ||
9653 | /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise, | |
9654 | reload may be unable to compute the address of a local variable, | |
9655 | since there is no way to add a large constant to the stack pointer | |
9656 | without using a second temporary register. */ | |
9657 | if (TARGET_MIPS16) | |
9658 | { | |
16dc5c28 | 9659 | mips_compute_frame_info (); |
29c4d304 RS |
9660 | if (!SMALL_OPERAND (cfun->machine->frame.total_size)) |
9661 | return true; | |
9662 | } | |
9663 | ||
9664 | return false; | |
9665 | } | |
9666 | ||
7b5cbb57 AS |
9667 | /* Make sure that we're not trying to eliminate to the wrong hard frame |
9668 | pointer. */ | |
9669 | ||
9670 | static bool | |
9671 | mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
9672 | { | |
9673 | return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); | |
9674 | } | |
9675 | ||
65239d20 RS |
9676 | /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer |
9677 | or argument pointer. TO is either the stack pointer or hard frame | |
9678 | pointer. */ | |
e1260576 | 9679 | |
ab77a036 RS |
9680 | HOST_WIDE_INT |
9681 | mips_initial_elimination_offset (int from, int to) | |
9682 | { | |
9683 | HOST_WIDE_INT offset; | |
9684 | ||
16dc5c28 | 9685 | mips_compute_frame_info (); |
ab77a036 | 9686 | |
ba6adec4 | 9687 | /* Set OFFSET to the offset from the end-of-prologue stack pointer. */ |
ab77a036 RS |
9688 | switch (from) |
9689 | { | |
9690 | case FRAME_POINTER_REGNUM: | |
ba6adec4 AN |
9691 | if (FRAME_GROWS_DOWNWARD) |
9692 | offset = (cfun->machine->frame.args_size | |
9693 | + cfun->machine->frame.cprestore_size | |
9694 | + cfun->machine->frame.var_size); | |
9695 | else | |
9696 | offset = 0; | |
ab77a036 RS |
9697 | break; |
9698 | ||
9699 | case ARG_POINTER_REGNUM: | |
f374e413 | 9700 | offset = cfun->machine->frame.arg_pointer_offset; |
ab77a036 RS |
9701 | break; |
9702 | ||
9703 | default: | |
9704 | gcc_unreachable (); | |
9705 | } | |
9706 | ||
f374e413 RS |
9707 | if (to == HARD_FRAME_POINTER_REGNUM) |
9708 | offset -= cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
9709 | |
9710 | return offset; | |
e1260576 | 9711 | } |
ab77a036 | 9712 | \f |
dbc90b65 | 9713 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */ |
e1260576 | 9714 | |
ab77a036 RS |
9715 | static void |
9716 | mips_extra_live_on_entry (bitmap regs) | |
9717 | { | |
dbc90b65 RS |
9718 | if (TARGET_USE_GOT) |
9719 | { | |
9720 | /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up | |
9721 | the global pointer. */ | |
9722 | if (!TARGET_ABSOLUTE_ABICALLS) | |
9723 | bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM); | |
9724 | ||
08d0963a RS |
9725 | /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of |
9726 | the global pointer. */ | |
9727 | if (TARGET_MIPS16) | |
9728 | bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM); | |
9729 | ||
dbc90b65 RS |
9730 | /* See the comment above load_call<mode> for details. */ |
9731 | bitmap_set_bit (regs, GOT_VERSION_REGNUM); | |
9732 | } | |
ab77a036 | 9733 | } |
e1260576 | 9734 | |
65239d20 RS |
9735 | /* Implement RETURN_ADDR_RTX. We do not support moving back to a |
9736 | previous frame. */ | |
ab77a036 RS |
9737 | |
9738 | rtx | |
9739 | mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) | |
e1260576 | 9740 | { |
ab77a036 RS |
9741 | if (count != 0) |
9742 | return const0_rtx; | |
e1260576 | 9743 | |
293593b1 | 9744 | return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); |
ab77a036 | 9745 | } |
e1260576 | 9746 | |
ab77a036 RS |
9747 | /* Emit code to change the current function's return address to |
9748 | ADDRESS. SCRATCH is available as a scratch register, if needed. | |
9749 | ADDRESS and SCRATCH are both word-mode GPRs. */ | |
e1260576 | 9750 | |
ab77a036 RS |
9751 | void |
9752 | mips_set_return_address (rtx address, rtx scratch) | |
9753 | { | |
9754 | rtx slot_address; | |
e1260576 | 9755 | |
293593b1 | 9756 | gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); |
ab77a036 RS |
9757 | slot_address = mips_add_offset (scratch, stack_pointer_rtx, |
9758 | cfun->machine->frame.gp_sp_offset); | |
8d0e1e43 | 9759 | mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); |
e1260576 | 9760 | } |
be763023 | 9761 | |
0c433c31 | 9762 | /* Return true if the current function has a cprestore slot. */ |
0fb5ac6f | 9763 | |
0c433c31 RS |
9764 | bool |
9765 | mips_cfun_has_cprestore_slot_p (void) | |
9766 | { | |
9767 | return (cfun->machine->global_pointer != INVALID_REGNUM | |
9768 | && cfun->machine->frame.cprestore_size > 0); | |
9769 | } | |
9770 | ||
9771 | /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the | |
9772 | cprestore slot. LOAD_P is true if the caller wants to load from | |
9773 | the cprestore slot; it is false if the caller wants to store to | |
9774 | the slot. */ | |
9775 | ||
9776 | static void | |
9777 | mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset, | |
9778 | bool load_p) | |
0fb5ac6f | 9779 | { |
08d0963a | 9780 | const struct mips_frame_info *frame; |
0fb5ac6f | 9781 | |
08d0963a | 9782 | frame = &cfun->machine->frame; |
0c433c31 RS |
9783 | /* .cprestore always uses the stack pointer instead of the frame pointer. |
9784 | We have a free choice for direct stores for non-MIPS16 functions, | |
9785 | and for MIPS16 functions whose cprestore slot is in range of the | |
9786 | stack pointer. Using the stack pointer would sometimes give more | |
9787 | (early) scheduling freedom, but using the frame pointer would | |
9788 | sometimes give more (late) scheduling freedom. It's hard to | |
9789 | predict which applies to a given function, so let's keep things | |
9790 | simple. | |
9791 | ||
9792 | Loads must always use the frame pointer in functions that call | |
9793 | alloca, and there's little benefit to using the stack pointer | |
9794 | otherwise. */ | |
9795 | if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p)) | |
9796 | { | |
9797 | *base = hard_frame_pointer_rtx; | |
9798 | *offset = frame->args_size - frame->hard_frame_pointer_offset; | |
08d0963a RS |
9799 | } |
9800 | else | |
9801 | { | |
0c433c31 RS |
9802 | *base = stack_pointer_rtx; |
9803 | *offset = frame->args_size; | |
08d0963a | 9804 | } |
0c433c31 RS |
9805 | } |
9806 | ||
9807 | /* Return true if X is the load or store address of the cprestore slot; | |
9808 | LOAD_P says which. */ | |
9809 | ||
9810 | bool | |
9811 | mips_cprestore_address_p (rtx x, bool load_p) | |
9812 | { | |
9813 | rtx given_base, required_base; | |
9814 | HOST_WIDE_INT given_offset, required_offset; | |
9815 | ||
9816 | mips_split_plus (x, &given_base, &given_offset); | |
9817 | mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p); | |
9818 | return given_base == required_base && given_offset == required_offset; | |
9819 | } | |
9820 | ||
9821 | /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are | |
9822 | going to load from it, false if we are going to store to it. | |
9823 | Use TEMP as a temporary register if need be. */ | |
9824 | ||
9825 | static rtx | |
9826 | mips_cprestore_slot (rtx temp, bool load_p) | |
9827 | { | |
9828 | rtx base; | |
9829 | HOST_WIDE_INT offset; | |
9830 | ||
9831 | mips_get_cprestore_base_and_offset (&base, &offset, load_p); | |
08d0963a RS |
9832 | return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset)); |
9833 | } | |
9834 | ||
0c433c31 RS |
9835 | /* Emit instructions to save global pointer value GP into cprestore |
9836 | slot MEM. OFFSET is the offset that MEM applies to the base register. | |
9837 | ||
9838 | MEM may not be a legitimate address. If it isn't, TEMP is a | |
9839 | temporary register that can be used, otherwise it is a SCRATCH. */ | |
9840 | ||
9841 | void | |
9842 | mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp) | |
9843 | { | |
9844 | if (TARGET_CPRESTORE_DIRECTIVE) | |
9845 | { | |
9846 | gcc_assert (gp == pic_offset_table_rtx); | |
81a478c8 | 9847 | emit_insn (PMODE_INSN (gen_cprestore, (mem, offset))); |
0c433c31 RS |
9848 | } |
9849 | else | |
9850 | mips_emit_move (mips_cprestore_slot (temp, false), gp); | |
9851 | } | |
9852 | ||
08d0963a | 9853 | /* Restore $gp from its save slot, using TEMP as a temporary base register |
0c433c31 RS |
9854 | if need be. This function is for o32 and o64 abicalls only. |
9855 | ||
9856 | See mips_must_initialize_gp_p for details about how we manage the | |
9857 | global pointer. */ | |
08d0963a RS |
9858 | |
9859 | void | |
0c433c31 | 9860 | mips_restore_gp_from_cprestore_slot (rtx temp) |
08d0963a | 9861 | { |
0c433c31 | 9862 | gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed); |
f833ffd4 | 9863 | |
0c433c31 | 9864 | if (!cfun->machine->must_restore_gp_when_clobbered_p) |
c870c233 RS |
9865 | { |
9866 | emit_note (NOTE_INSN_DELETED); | |
9867 | return; | |
9868 | } | |
e21d5757 | 9869 | |
08d0963a RS |
9870 | if (TARGET_MIPS16) |
9871 | { | |
0c433c31 | 9872 | mips_emit_move (temp, mips_cprestore_slot (temp, true)); |
08d0963a RS |
9873 | mips_emit_move (pic_offset_table_rtx, temp); |
9874 | } | |
9875 | else | |
0c433c31 | 9876 | mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true)); |
ab77a036 RS |
9877 | if (!TARGET_EXPLICIT_RELOCS) |
9878 | emit_insn (gen_blockage ()); | |
9879 | } | |
9880 | \f | |
9881 | /* A function to save or store a register. The first argument is the | |
9882 | register and the second is the stack slot. */ | |
9883 | typedef void (*mips_save_restore_fn) (rtx, rtx); | |
cee98a59 | 9884 | |
ab77a036 RS |
9885 | /* Use FN to save or restore register REGNO. MODE is the register's |
9886 | mode and OFFSET is the offset of its save slot from the current | |
9887 | stack pointer. */ | |
e1260576 | 9888 | |
ab77a036 RS |
9889 | static void |
9890 | mips_save_restore_reg (enum machine_mode mode, int regno, | |
9891 | HOST_WIDE_INT offset, mips_save_restore_fn fn) | |
9892 | { | |
9893 | rtx mem; | |
e1260576 | 9894 | |
ab77a036 | 9895 | mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset)); |
ab77a036 RS |
9896 | fn (gen_rtx_REG (mode, regno), mem); |
9897 | } | |
e1260576 | 9898 | |
e19da24c CF |
9899 | /* Call FN for each accumlator that is saved by the current function. |
9900 | SP_OFFSET is the offset of the current stack pointer from the start | |
9901 | of the frame. */ | |
9902 | ||
9903 | static void | |
9904 | mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn) | |
9905 | { | |
9906 | HOST_WIDE_INT offset; | |
9907 | int regno; | |
9908 | ||
9909 | offset = cfun->machine->frame.acc_sp_offset - sp_offset; | |
9910 | if (BITSET_P (cfun->machine->frame.acc_mask, 0)) | |
9911 | { | |
9912 | mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn); | |
9913 | offset -= UNITS_PER_WORD; | |
9914 | mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn); | |
9915 | offset -= UNITS_PER_WORD; | |
9916 | } | |
9917 | ||
9918 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) | |
9919 | if (BITSET_P (cfun->machine->frame.acc_mask, | |
9920 | ((regno - DSP_ACC_REG_FIRST) / 2) + 1)) | |
9921 | { | |
9922 | mips_save_restore_reg (word_mode, regno, offset, fn); | |
9923 | offset -= UNITS_PER_WORD; | |
9924 | } | |
9925 | } | |
9926 | ||
ab77a036 RS |
9927 | /* Call FN for each register that is saved by the current function. |
9928 | SP_OFFSET is the offset of the current stack pointer from the start | |
9929 | of the frame. */ | |
a94dbf2c | 9930 | |
ab77a036 | 9931 | static void |
e19da24c CF |
9932 | mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, |
9933 | mips_save_restore_fn fn) | |
ab77a036 RS |
9934 | { |
9935 | enum machine_mode fpr_mode; | |
9936 | HOST_WIDE_INT offset; | |
9937 | int regno; | |
2bcb2ab3 | 9938 | |
ab77a036 RS |
9939 | /* Save registers starting from high to low. The debuggers prefer at least |
9940 | the return register be stored at func+4, and also it allows us not to | |
9941 | need a nop in the epilogue if at least one register is reloaded in | |
9942 | addition to return address. */ | |
9943 | offset = cfun->machine->frame.gp_sp_offset - sp_offset; | |
9944 | for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) | |
9945 | if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) | |
9946 | { | |
c376dbfb DD |
9947 | /* Record the ra offset for use by mips_function_profiler. */ |
9948 | if (regno == RETURN_ADDR_REGNUM) | |
9949 | cfun->machine->frame.ra_fp_offset = offset + sp_offset; | |
6e75e6e3 RS |
9950 | mips_save_restore_reg (word_mode, regno, offset, fn); |
9951 | offset -= UNITS_PER_WORD; | |
ab77a036 RS |
9952 | } |
9953 | ||
9954 | /* This loop must iterate over the same space as its companion in | |
16dc5c28 | 9955 | mips_compute_frame_info. */ |
ab77a036 RS |
9956 | offset = cfun->machine->frame.fp_sp_offset - sp_offset; |
9957 | fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); | |
65239d20 | 9958 | for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; |
ab77a036 RS |
9959 | regno >= FP_REG_FIRST; |
9960 | regno -= MAX_FPRS_PER_FMT) | |
9961 | if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) | |
9962 | { | |
9963 | mips_save_restore_reg (fpr_mode, regno, offset, fn); | |
9964 | offset -= GET_MODE_SIZE (fpr_mode); | |
9965 | } | |
9966 | } | |
0c433c31 RS |
9967 | |
9968 | /* Return true if a move between register REGNO and its save slot (MEM) | |
9969 | can be done in a single move. LOAD_P is true if we are loading | |
9970 | from the slot, false if we are storing to it. */ | |
9971 | ||
9972 | static bool | |
9973 | mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p) | |
9974 | { | |
9975 | /* There is a specific MIPS16 instruction for saving $31 to the stack. */ | |
293593b1 | 9976 | if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM) |
0c433c31 RS |
9977 | return false; |
9978 | ||
9979 | return mips_secondary_reload_class (REGNO_REG_CLASS (regno), | |
9980 | GET_MODE (mem), mem, load_p) == NO_REGS; | |
9981 | } | |
9982 | ||
9983 | /* Emit a move from SRC to DEST, given that one of them is a register | |
9984 | save slot and that the other is a register. TEMP is a temporary | |
9985 | GPR of the same mode that is available if need be. */ | |
9986 | ||
9987 | void | |
9988 | mips_emit_save_slot_move (rtx dest, rtx src, rtx temp) | |
9989 | { | |
9990 | unsigned int regno; | |
9991 | rtx mem; | |
9992 | ||
9993 | if (REG_P (src)) | |
9994 | { | |
9995 | regno = REGNO (src); | |
9996 | mem = dest; | |
9997 | } | |
9998 | else | |
9999 | { | |
10000 | regno = REGNO (dest); | |
10001 | mem = src; | |
10002 | } | |
10003 | ||
10004 | if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ()) | |
10005 | { | |
10006 | /* We don't yet know whether we'll need this instruction or not. | |
10007 | Postpone the decision by emitting a ghost move. This move | |
10008 | is specifically not frame-related; only the split version is. */ | |
10009 | if (TARGET_64BIT) | |
10010 | emit_insn (gen_move_gpdi (dest, src)); | |
10011 | else | |
10012 | emit_insn (gen_move_gpsi (dest, src)); | |
10013 | return; | |
10014 | } | |
10015 | ||
10016 | if (regno == HI_REGNUM) | |
10017 | { | |
10018 | if (REG_P (dest)) | |
10019 | { | |
10020 | mips_emit_move (temp, src); | |
10021 | if (TARGET_64BIT) | |
10022 | emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST), | |
10023 | temp, gen_rtx_REG (DImode, LO_REGNUM))); | |
10024 | else | |
10025 | emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST), | |
10026 | temp, gen_rtx_REG (SImode, LO_REGNUM))); | |
10027 | } | |
10028 | else | |
10029 | { | |
10030 | if (TARGET_64BIT) | |
10031 | emit_insn (gen_mfhidi_ti (temp, | |
10032 | gen_rtx_REG (TImode, MD_REG_FIRST))); | |
10033 | else | |
10034 | emit_insn (gen_mfhisi_di (temp, | |
10035 | gen_rtx_REG (DImode, MD_REG_FIRST))); | |
10036 | mips_emit_move (dest, temp); | |
10037 | } | |
10038 | } | |
10039 | else if (mips_direct_save_slot_move_p (regno, mem, mem == src)) | |
10040 | mips_emit_move (dest, src); | |
10041 | else | |
10042 | { | |
10043 | gcc_assert (!reg_overlap_mentioned_p (dest, temp)); | |
10044 | mips_emit_move (temp, src); | |
10045 | mips_emit_move (dest, temp); | |
10046 | } | |
10047 | if (MEM_P (dest)) | |
10048 | mips_set_frame_expr (mips_frame_set (dest, src)); | |
10049 | } | |
ab77a036 RS |
10050 | \f |
10051 | /* If we're generating n32 or n64 abicalls, and the current function | |
10052 | does not use $28 as its global pointer, emit a cplocal directive. | |
10053 | Use pic_offset_table_rtx as the argument to the directive. */ | |
10054 | ||
10055 | static void | |
10056 | mips_output_cplocal (void) | |
10057 | { | |
10058 | if (!TARGET_EXPLICIT_RELOCS | |
0c433c31 | 10059 | && mips_must_initialize_gp_p () |
ab77a036 RS |
10060 | && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM) |
10061 | output_asm_insn (".cplocal %+", 0); | |
10062 | } | |
10063 | ||
65239d20 | 10064 | /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */ |
ab77a036 RS |
10065 | |
10066 | static void | |
10067 | mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
10068 | { | |
10069 | const char *fnname; | |
ab77a036 RS |
10070 | |
10071 | #ifdef SDB_DEBUGGING_INFO | |
10072 | if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) | |
10073 | SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); | |
10074 | #endif | |
10075 | ||
65239d20 RS |
10076 | /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle |
10077 | floating-point arguments. */ | |
ab77a036 RS |
10078 | if (TARGET_MIPS16 |
10079 | && TARGET_HARD_FLOAT_ABI | |
38173d38 | 10080 | && crtl->args.info.fp_code != 0) |
65239d20 | 10081 | mips16_build_function_stub (); |
ab77a036 | 10082 | |
b2b61607 RS |
10083 | /* Get the function name the same way that toplev.c does before calling |
10084 | assemble_start_function. This is needed so that the name used here | |
10085 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
10086 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
10087 | mips_start_function_definition (fnname, TARGET_MIPS16); | |
f833ffd4 | 10088 | |
65239d20 | 10089 | /* Output MIPS-specific frame information. */ |
ab77a036 RS |
10090 | if (!flag_inhibit_size_directive) |
10091 | { | |
65239d20 RS |
10092 | const struct mips_frame_info *frame; |
10093 | ||
10094 | frame = &cfun->machine->frame; | |
10095 | ||
10096 | /* .frame FRAMEREG, FRAMESIZE, RETREG. */ | |
ab77a036 RS |
10097 | fprintf (file, |
10098 | "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t" | |
65239d20 RS |
10099 | "# vars= " HOST_WIDE_INT_PRINT_DEC |
10100 | ", regs= %d/%d" | |
ab77a036 RS |
10101 | ", args= " HOST_WIDE_INT_PRINT_DEC |
10102 | ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", | |
65239d20 RS |
10103 | reg_names[frame_pointer_needed |
10104 | ? HARD_FRAME_POINTER_REGNUM | |
10105 | : STACK_POINTER_REGNUM], | |
f374e413 | 10106 | (frame_pointer_needed |
65239d20 RS |
10107 | ? frame->total_size - frame->hard_frame_pointer_offset |
10108 | : frame->total_size), | |
293593b1 | 10109 | reg_names[RETURN_ADDR_REGNUM], |
65239d20 RS |
10110 | frame->var_size, |
10111 | frame->num_gp, frame->num_fp, | |
10112 | frame->args_size, | |
10113 | frame->cprestore_size); | |
be763023 | 10114 | |
65239d20 | 10115 | /* .mask MASK, OFFSET. */ |
ab77a036 | 10116 | fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", |
65239d20 | 10117 | frame->mask, frame->gp_save_offset); |
d8d5b1e1 | 10118 | |
65239d20 RS |
10119 | /* .fmask MASK, OFFSET. */ |
10120 | fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", | |
10121 | frame->fmask, frame->fp_save_offset); | |
ab77a036 RS |
10122 | } |
10123 | ||
65239d20 RS |
10124 | /* Handle the initialization of $gp for SVR4 PIC, if applicable. |
10125 | Also emit the ".set noreorder; .set nomacro" sequence for functions | |
10126 | that need it. */ | |
0c433c31 RS |
10127 | if (mips_must_initialize_gp_p () |
10128 | && mips_current_loadgp_style () == LOADGP_OLDABI) | |
ab77a036 | 10129 | { |
08d0963a RS |
10130 | if (TARGET_MIPS16) |
10131 | { | |
10132 | /* This is a fixed-form sequence. The position of the | |
10133 | first two instructions is important because of the | |
10134 | way _gp_disp is defined. */ | |
10135 | output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); | |
10136 | output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); | |
10137 | output_asm_insn ("sll\t$2,16", 0); | |
10138 | output_asm_insn ("addu\t$2,$3", 0); | |
10139 | } | |
ab77a036 | 10140 | else |
cf5fb4b0 RS |
10141 | { |
10142 | /* .cpload must be in a .set noreorder but not a | |
10143 | .set nomacro block. */ | |
10144 | mips_push_asm_switch (&mips_noreorder); | |
10145 | output_asm_insn (".cpload\t%^", 0); | |
10146 | if (!cfun->machine->all_noreorder_p) | |
10147 | mips_pop_asm_switch (&mips_noreorder); | |
10148 | else | |
10149 | mips_push_asm_switch (&mips_nomacro); | |
10150 | } | |
ab77a036 RS |
10151 | } |
10152 | else if (cfun->machine->all_noreorder_p) | |
cf5fb4b0 RS |
10153 | { |
10154 | mips_push_asm_switch (&mips_noreorder); | |
10155 | mips_push_asm_switch (&mips_nomacro); | |
10156 | } | |
ab77a036 RS |
10157 | |
10158 | /* Tell the assembler which register we're using as the global | |
10159 | pointer. This is needed for thunks, since they can use either | |
10160 | explicit relocs or assembler macros. */ | |
10161 | mips_output_cplocal (); | |
cee98a59 | 10162 | } |
ab77a036 | 10163 | |
65239d20 | 10164 | /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */ |
b5e9dd03 | 10165 | |
08c148a8 | 10166 | static void |
b4966b1b RS |
10167 | mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
10168 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
cee98a59 | 10169 | { |
b2b61607 RS |
10170 | const char *fnname; |
10171 | ||
b85aed9e | 10172 | /* Reinstate the normal $gp. */ |
6fb5fa3c | 10173 | SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM); |
b85aed9e RS |
10174 | mips_output_cplocal (); |
10175 | ||
6f2993e5 RS |
10176 | if (cfun->machine->all_noreorder_p) |
10177 | { | |
cf5fb4b0 RS |
10178 | mips_pop_asm_switch (&mips_nomacro); |
10179 | mips_pop_asm_switch (&mips_noreorder); | |
6f2993e5 RS |
10180 | } |
10181 | ||
b2b61607 RS |
10182 | /* Get the function name the same way that toplev.c does before calling |
10183 | assemble_start_function. This is needed so that the name used here | |
10184 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
10185 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
10186 | mips_end_function_definition (fnname); | |
cee98a59 | 10187 | } |
0fb5ac6f | 10188 | \f |
d9b59f56 RS |
10189 | /* Emit an optimisation barrier for accesses to the current frame. */ |
10190 | ||
10191 | static void | |
10192 | mips_frame_barrier (void) | |
10193 | { | |
10194 | emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx)); | |
10195 | } | |
10196 | ||
ab77a036 | 10197 | /* Save register REG to MEM. Make the instruction frame-related. */ |
be763023 RS |
10198 | |
10199 | static void | |
ab77a036 | 10200 | mips_save_reg (rtx reg, rtx mem) |
be763023 | 10201 | { |
ab77a036 | 10202 | if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) |
be763023 | 10203 | { |
ab77a036 RS |
10204 | rtx x1, x2; |
10205 | ||
10206 | if (mips_split_64bit_move_p (mem, reg)) | |
10207 | mips_split_doubleword_move (mem, reg); | |
10208 | else | |
10209 | mips_emit_move (mem, reg); | |
10210 | ||
65239d20 RS |
10211 | x1 = mips_frame_set (mips_subword (mem, false), |
10212 | mips_subword (reg, false)); | |
10213 | x2 = mips_frame_set (mips_subword (mem, true), | |
10214 | mips_subword (reg, true)); | |
ab77a036 | 10215 | mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2))); |
be763023 RS |
10216 | } |
10217 | else | |
0c433c31 | 10218 | mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg))); |
be763023 RS |
10219 | } |
10220 | ||
ab77a036 | 10221 | /* The __gnu_local_gp symbol. */ |
be763023 | 10222 | |
ab77a036 | 10223 | static GTY(()) rtx mips_gnu_local_gp; |
0fb5ac6f | 10224 | |
ab77a036 RS |
10225 | /* If we're generating n32 or n64 abicalls, emit instructions |
10226 | to set up the global pointer. */ | |
0fb5ac6f | 10227 | |
ab77a036 RS |
10228 | static void |
10229 | mips_emit_loadgp (void) | |
10230 | { | |
5557aad2 | 10231 | rtx addr, offset, incoming_address, base, index, pic_reg; |
d33289b2 | 10232 | |
08d0963a | 10233 | pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; |
ab77a036 | 10234 | switch (mips_current_loadgp_style ()) |
a38e0142 | 10235 | { |
ab77a036 RS |
10236 | case LOADGP_ABSOLUTE: |
10237 | if (mips_gnu_local_gp == NULL) | |
10238 | { | |
10239 | mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); | |
10240 | SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; | |
10241 | } | |
81a478c8 RS |
10242 | emit_insn (PMODE_INSN (gen_loadgp_absolute, |
10243 | (pic_reg, mips_gnu_local_gp))); | |
ab77a036 | 10244 | break; |
a38e0142 | 10245 | |
08d0963a RS |
10246 | case LOADGP_OLDABI: |
10247 | /* Added by mips_output_function_prologue. */ | |
10248 | break; | |
10249 | ||
ab77a036 RS |
10250 | case LOADGP_NEWABI: |
10251 | addr = XEXP (DECL_RTL (current_function_decl), 0); | |
10252 | offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP); | |
10253 | incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
81a478c8 RS |
10254 | emit_insn (PMODE_INSN (gen_loadgp_newabi, |
10255 | (pic_reg, offset, incoming_address))); | |
ab77a036 | 10256 | break; |
a38e0142 | 10257 | |
ab77a036 RS |
10258 | case LOADGP_RTP: |
10259 | base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE)); | |
10260 | index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX)); | |
81a478c8 | 10261 | emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index))); |
ab77a036 RS |
10262 | break; |
10263 | ||
10264 | default: | |
de9f679d | 10265 | return; |
ab77a036 | 10266 | } |
08d0963a RS |
10267 | |
10268 | if (TARGET_MIPS16) | |
81a478c8 RS |
10269 | emit_insn (PMODE_INSN (gen_copygp_mips16, |
10270 | (pic_offset_table_rtx, pic_reg))); | |
08d0963a | 10271 | |
de9f679d RS |
10272 | /* Emit a blockage if there are implicit uses of the GP register. |
10273 | This includes profiled functions, because FUNCTION_PROFILE uses | |
10274 | a jal macro. */ | |
10275 | if (!TARGET_EXPLICIT_RELOCS || crtl->profile) | |
10276 | emit_insn (gen_loadgp_blockage ()); | |
ab77a036 RS |
10277 | } |
10278 | ||
e19da24c CF |
10279 | /* A for_each_rtx callback. Stop the search if *X is a kernel register. */ |
10280 | ||
10281 | static int | |
10282 | mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED) | |
10283 | { | |
47ac44d6 | 10284 | return REG_P (*x) && KERNEL_REG_P (REGNO (*x)); |
e19da24c CF |
10285 | } |
10286 | ||
65239d20 | 10287 | /* Expand the "prologue" pattern. */ |
ab77a036 RS |
10288 | |
10289 | void | |
10290 | mips_expand_prologue (void) | |
10291 | { | |
65239d20 | 10292 | const struct mips_frame_info *frame; |
ab77a036 RS |
10293 | HOST_WIDE_INT size; |
10294 | unsigned int nargs; | |
10295 | rtx insn; | |
10296 | ||
8d9d9172 | 10297 | if (cfun->machine->global_pointer != INVALID_REGNUM) |
0c433c31 RS |
10298 | { |
10299 | /* Check whether an insn uses pic_offset_table_rtx, either explicitly | |
10300 | or implicitly. If so, we can commit to using a global pointer | |
10301 | straight away, otherwise we need to defer the decision. */ | |
10302 | if (mips_cfun_has_inflexible_gp_ref_p () | |
10303 | || mips_cfun_has_flexible_gp_ref_p ()) | |
10304 | { | |
10305 | cfun->machine->must_initialize_gp_p = true; | |
10306 | cfun->machine->must_restore_gp_when_clobbered_p = true; | |
10307 | } | |
10308 | ||
10309 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); | |
10310 | } | |
ab77a036 | 10311 | |
65239d20 RS |
10312 | frame = &cfun->machine->frame; |
10313 | size = frame->total_size; | |
ab77a036 | 10314 | |
a11e0df4 | 10315 | if (flag_stack_usage_info) |
d3c12306 EB |
10316 | current_function_static_stack_size = size; |
10317 | ||
ab77a036 RS |
10318 | /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP |
10319 | bytes beforehand; this is enough to cover the register save area | |
10320 | without going out of range. */ | |
e19da24c CF |
10321 | if (((frame->mask | frame->fmask | frame->acc_mask) != 0) |
10322 | || frame->num_cop0_regs > 0) | |
ab77a036 RS |
10323 | { |
10324 | HOST_WIDE_INT step1; | |
10325 | ||
10326 | step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); | |
ab77a036 RS |
10327 | if (GENERATE_MIPS16E_SAVE_RESTORE) |
10328 | { | |
10329 | HOST_WIDE_INT offset; | |
10330 | unsigned int mask, regno; | |
10331 | ||
10332 | /* Try to merge argument stores into the save instruction. */ | |
10333 | nargs = mips16e_collect_argument_saves (); | |
10334 | ||
10335 | /* Build the save instruction. */ | |
65239d20 | 10336 | mask = frame->mask; |
ab77a036 RS |
10337 | insn = mips16e_build_save_restore (false, &mask, &offset, |
10338 | nargs, step1); | |
10339 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
d9b59f56 | 10340 | mips_frame_barrier (); |
ab77a036 RS |
10341 | size -= step1; |
10342 | ||
10343 | /* Check if we need to save other registers. */ | |
10344 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
10345 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
10346 | { | |
6e75e6e3 RS |
10347 | offset -= UNITS_PER_WORD; |
10348 | mips_save_restore_reg (word_mode, regno, | |
10349 | offset, mips_save_reg); | |
ab77a036 RS |
10350 | } |
10351 | } | |
10352 | else | |
10353 | { | |
e19da24c CF |
10354 | if (cfun->machine->interrupt_handler_p) |
10355 | { | |
10356 | HOST_WIDE_INT offset; | |
10357 | rtx mem; | |
10358 | ||
10359 | /* If this interrupt is using a shadow register set, we need to | |
10360 | get the stack pointer from the previous register set. */ | |
10361 | if (cfun->machine->use_shadow_register_set_p) | |
10362 | emit_insn (gen_mips_rdpgpr (stack_pointer_rtx, | |
10363 | stack_pointer_rtx)); | |
10364 | ||
10365 | if (!cfun->machine->keep_interrupts_masked_p) | |
10366 | { | |
10367 | /* Move from COP0 Cause to K0. */ | |
10368 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM), | |
10369 | gen_rtx_REG (SImode, | |
10370 | COP0_CAUSE_REG_NUM))); | |
10371 | /* Move from COP0 EPC to K1. */ | |
10372 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
10373 | gen_rtx_REG (SImode, | |
10374 | COP0_EPC_REG_NUM))); | |
10375 | } | |
10376 | ||
10377 | /* Allocate the first part of the frame. */ | |
10378 | insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, | |
10379 | GEN_INT (-step1)); | |
10380 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
d9b59f56 | 10381 | mips_frame_barrier (); |
e19da24c CF |
10382 | size -= step1; |
10383 | ||
10384 | /* Start at the uppermost location for saving. */ | |
10385 | offset = frame->cop0_sp_offset - size; | |
10386 | if (!cfun->machine->keep_interrupts_masked_p) | |
10387 | { | |
10388 | /* Push EPC into its stack slot. */ | |
10389 | mem = gen_frame_mem (word_mode, | |
10390 | plus_constant (stack_pointer_rtx, | |
10391 | offset)); | |
10392 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
10393 | offset -= UNITS_PER_WORD; | |
10394 | } | |
10395 | ||
10396 | /* Move from COP0 Status to K1. */ | |
10397 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
10398 | gen_rtx_REG (SImode, | |
10399 | COP0_STATUS_REG_NUM))); | |
10400 | ||
10401 | /* Right justify the RIPL in k0. */ | |
10402 | if (!cfun->machine->keep_interrupts_masked_p) | |
10403 | emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), | |
10404 | gen_rtx_REG (SImode, K0_REG_NUM), | |
10405 | GEN_INT (CAUSE_IPL))); | |
10406 | ||
10407 | /* Push Status into its stack slot. */ | |
10408 | mem = gen_frame_mem (word_mode, | |
10409 | plus_constant (stack_pointer_rtx, offset)); | |
10410 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
10411 | offset -= UNITS_PER_WORD; | |
10412 | ||
10413 | /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ | |
10414 | if (!cfun->machine->keep_interrupts_masked_p) | |
10415 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10416 | GEN_INT (6), | |
10417 | GEN_INT (SR_IPL), | |
10418 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10419 | ||
10420 | if (!cfun->machine->keep_interrupts_masked_p) | |
10421 | /* Enable interrupts by clearing the KSU ERL and EXL bits. | |
10422 | IE is already the correct value, so we don't have to do | |
10423 | anything explicit. */ | |
10424 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10425 | GEN_INT (4), | |
10426 | GEN_INT (SR_EXL), | |
10427 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
10428 | else | |
10429 | /* Disable interrupts by clearing the KSU, ERL, EXL, | |
10430 | and IE bits. */ | |
10431 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10432 | GEN_INT (5), | |
10433 | GEN_INT (SR_IE), | |
10434 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
10435 | } | |
10436 | else | |
10437 | { | |
10438 | insn = gen_add3_insn (stack_pointer_rtx, | |
10439 | stack_pointer_rtx, | |
10440 | GEN_INT (-step1)); | |
10441 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
d9b59f56 | 10442 | mips_frame_barrier (); |
e19da24c CF |
10443 | size -= step1; |
10444 | } | |
10445 | mips_for_each_saved_acc (size, mips_save_reg); | |
10446 | mips_for_each_saved_gpr_and_fpr (size, mips_save_reg); | |
ab77a036 RS |
10447 | } |
10448 | } | |
10449 | ||
10450 | /* Allocate the rest of the frame. */ | |
10451 | if (size > 0) | |
10452 | { | |
10453 | if (SMALL_OPERAND (-size)) | |
10454 | RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10455 | stack_pointer_rtx, | |
10456 | GEN_INT (-size)))) = 1; | |
10457 | else | |
10458 | { | |
10459 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size)); | |
10460 | if (TARGET_MIPS16) | |
10461 | { | |
10462 | /* There are no instructions to add or subtract registers | |
10463 | from the stack pointer, so use the frame pointer as a | |
10464 | temporary. We should always be using a frame pointer | |
10465 | in this case anyway. */ | |
10466 | gcc_assert (frame_pointer_needed); | |
10467 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
10468 | emit_insn (gen_sub3_insn (hard_frame_pointer_rtx, | |
10469 | hard_frame_pointer_rtx, | |
10470 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10471 | mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx); | |
10472 | } | |
10473 | else | |
10474 | emit_insn (gen_sub3_insn (stack_pointer_rtx, | |
10475 | stack_pointer_rtx, | |
10476 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10477 | ||
10478 | /* Describe the combined effect of the previous instructions. */ | |
10479 | mips_set_frame_expr | |
10480 | (gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
10481 | plus_constant (stack_pointer_rtx, -size))); | |
10482 | } | |
d9b59f56 | 10483 | mips_frame_barrier (); |
ab77a036 RS |
10484 | } |
10485 | ||
f374e413 | 10486 | /* Set up the frame pointer, if we're using one. */ |
ab77a036 RS |
10487 | if (frame_pointer_needed) |
10488 | { | |
f374e413 RS |
10489 | HOST_WIDE_INT offset; |
10490 | ||
65239d20 | 10491 | offset = frame->hard_frame_pointer_offset; |
f374e413 | 10492 | if (offset == 0) |
ab77a036 | 10493 | { |
f374e413 RS |
10494 | insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); |
10495 | RTX_FRAME_RELATED_P (insn) = 1; | |
10496 | } | |
10497 | else if (SMALL_OPERAND (offset)) | |
10498 | { | |
10499 | insn = gen_add3_insn (hard_frame_pointer_rtx, | |
10500 | stack_pointer_rtx, GEN_INT (offset)); | |
10501 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
ab77a036 RS |
10502 | } |
10503 | else | |
f374e413 RS |
10504 | { |
10505 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset)); | |
10506 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
10507 | emit_insn (gen_add3_insn (hard_frame_pointer_rtx, | |
10508 | hard_frame_pointer_rtx, | |
10509 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10510 | mips_set_frame_expr | |
10511 | (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, | |
10512 | plus_constant (stack_pointer_rtx, offset))); | |
10513 | } | |
ab77a036 RS |
10514 | } |
10515 | ||
10516 | mips_emit_loadgp (); | |
10517 | ||
65239d20 | 10518 | /* Initialize the $gp save slot. */ |
0c433c31 | 10519 | if (mips_cfun_has_cprestore_slot_p ()) |
08d0963a | 10520 | { |
0c433c31 RS |
10521 | rtx base, mem, gp, temp; |
10522 | HOST_WIDE_INT offset; | |
10523 | ||
10524 | mips_get_cprestore_base_and_offset (&base, &offset, false); | |
10525 | mem = gen_frame_mem (Pmode, plus_constant (base, offset)); | |
10526 | gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; | |
10527 | temp = (SMALL_OPERAND (offset) | |
10528 | ? gen_rtx_SCRATCH (Pmode) | |
10529 | : MIPS_PROLOGUE_TEMP (Pmode)); | |
81a478c8 RS |
10530 | emit_insn (PMODE_INSN (gen_potential_cprestore, |
10531 | (mem, GEN_INT (offset), gp, temp))); | |
0c433c31 RS |
10532 | |
10533 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
10534 | mem = gen_frame_mem (Pmode, plus_constant (base, offset)); | |
81a478c8 | 10535 | emit_insn (PMODE_INSN (gen_use_cprestore, (mem))); |
08d0963a | 10536 | } |
ab77a036 | 10537 | |
e19da24c CF |
10538 | /* We need to search back to the last use of K0 or K1. */ |
10539 | if (cfun->machine->interrupt_handler_p) | |
10540 | { | |
10541 | for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn)) | |
10542 | if (INSN_P (insn) | |
10543 | && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL)) | |
10544 | break; | |
10545 | /* Emit a move from K1 to COP0 Status after insn. */ | |
10546 | gcc_assert (insn != NULL_RTX); | |
10547 | emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
10548 | gen_rtx_REG (SImode, K1_REG_NUM)), | |
10549 | insn); | |
10550 | } | |
10551 | ||
ab77a036 RS |
10552 | /* If we are profiling, make sure no instructions are scheduled before |
10553 | the call to mcount. */ | |
e3b5732b | 10554 | if (crtl->profile) |
ab77a036 RS |
10555 | emit_insn (gen_blockage ()); |
10556 | } | |
10557 | \f | |
3bd0817d RS |
10558 | /* Attach all pending register saves to the previous instruction. |
10559 | Return that instruction. */ | |
10560 | ||
10561 | static rtx | |
10562 | mips_epilogue_emit_cfa_restores (void) | |
10563 | { | |
10564 | rtx insn; | |
10565 | ||
10566 | insn = get_last_insn (); | |
10567 | gcc_assert (insn && !REG_NOTES (insn)); | |
10568 | if (mips_epilogue.cfa_restores) | |
10569 | { | |
10570 | RTX_FRAME_RELATED_P (insn) = 1; | |
10571 | REG_NOTES (insn) = mips_epilogue.cfa_restores; | |
10572 | mips_epilogue.cfa_restores = 0; | |
10573 | } | |
10574 | return insn; | |
10575 | } | |
10576 | ||
10577 | /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is | |
10578 | now at REG + OFFSET. */ | |
10579 | ||
10580 | static void | |
10581 | mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset) | |
10582 | { | |
10583 | rtx insn; | |
10584 | ||
10585 | insn = mips_epilogue_emit_cfa_restores (); | |
10586 | if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset) | |
10587 | { | |
10588 | RTX_FRAME_RELATED_P (insn) = 1; | |
10589 | REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, | |
10590 | plus_constant (reg, offset), | |
10591 | REG_NOTES (insn)); | |
10592 | mips_epilogue.cfa_reg = reg; | |
10593 | mips_epilogue.cfa_offset = offset; | |
10594 | } | |
10595 | } | |
10596 | ||
10597 | /* Emit instructions to restore register REG from slot MEM. Also update | |
10598 | the cfa_restores list. */ | |
ab77a036 RS |
10599 | |
10600 | static void | |
10601 | mips_restore_reg (rtx reg, rtx mem) | |
10602 | { | |
65239d20 | 10603 | /* There's no MIPS16 instruction to load $31 directly. Load into |
ab77a036 | 10604 | $7 instead and adjust the return insn appropriately. */ |
293593b1 | 10605 | if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM) |
65239d20 | 10606 | reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7); |
a7449961 BS |
10607 | else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) |
10608 | { | |
10609 | mips_add_cfa_restore (mips_subword (reg, true)); | |
10610 | mips_add_cfa_restore (mips_subword (reg, false)); | |
10611 | } | |
3bd0817d | 10612 | else |
a7449961 | 10613 | mips_add_cfa_restore (reg); |
ab77a036 | 10614 | |
0c433c31 | 10615 | mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg))); |
3bd0817d RS |
10616 | if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg)) |
10617 | /* The CFA is currently defined in terms of the register whose | |
10618 | value we have just restored. Redefine the CFA in terms of | |
10619 | the stack pointer. */ | |
10620 | mips_epilogue_set_cfa (stack_pointer_rtx, | |
10621 | mips_epilogue.cfa_restore_sp_offset); | |
ab77a036 RS |
10622 | } |
10623 | ||
d9b59f56 RS |
10624 | /* Emit code to set the stack pointer to BASE + OFFSET, given that |
10625 | BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame. | |
10626 | BASE, if not the stack pointer, is available as a temporary. */ | |
10627 | ||
10628 | static void | |
10629 | mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size) | |
10630 | { | |
10631 | if (base == stack_pointer_rtx && offset == const0_rtx) | |
10632 | return; | |
10633 | ||
10634 | mips_frame_barrier (); | |
10635 | if (offset == const0_rtx) | |
10636 | { | |
10637 | emit_move_insn (stack_pointer_rtx, base); | |
10638 | mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size); | |
10639 | } | |
10640 | else if (TARGET_MIPS16 && base != stack_pointer_rtx) | |
10641 | { | |
10642 | emit_insn (gen_add3_insn (base, base, offset)); | |
10643 | mips_epilogue_set_cfa (base, new_frame_size); | |
10644 | emit_move_insn (stack_pointer_rtx, base); | |
10645 | } | |
10646 | else | |
10647 | { | |
10648 | emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset)); | |
10649 | mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size); | |
10650 | } | |
10651 | } | |
10652 | ||
2f7e2abb RS |
10653 | /* Emit any instructions needed before a return. */ |
10654 | ||
10655 | void | |
10656 | mips_expand_before_return (void) | |
10657 | { | |
10658 | /* When using a call-clobbered gp, we start out with unified call | |
10659 | insns that include instructions to restore the gp. We then split | |
10660 | these unified calls after reload. These split calls explicitly | |
10661 | clobber gp, so there is no need to define | |
10662 | PIC_OFFSET_TABLE_REG_CALL_CLOBBERED. | |
10663 | ||
10664 | For consistency, we should also insert an explicit clobber of $28 | |
10665 | before return insns, so that the post-reload optimizers know that | |
10666 | the register is not live on exit. */ | |
10667 | if (TARGET_CALL_CLOBBERED_GP) | |
10668 | emit_clobber (pic_offset_table_rtx); | |
10669 | } | |
10670 | ||
65239d20 RS |
10671 | /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P |
10672 | says which. */ | |
ab77a036 RS |
10673 | |
10674 | void | |
65239d20 | 10675 | mips_expand_epilogue (bool sibcall_p) |
ab77a036 | 10676 | { |
65239d20 | 10677 | const struct mips_frame_info *frame; |
ab77a036 | 10678 | HOST_WIDE_INT step1, step2; |
d9b59f56 | 10679 | rtx base, adjust, insn; |
ab77a036 RS |
10680 | |
10681 | if (!sibcall_p && mips_can_use_return_insn ()) | |
10682 | { | |
10683 | emit_jump_insn (gen_return ()); | |
10684 | return; | |
10685 | } | |
10686 | ||
65239d20 | 10687 | /* In MIPS16 mode, if the return value should go into a floating-point |
ab77a036 RS |
10688 | register, we need to call a helper routine to copy it over. */ |
10689 | if (mips16_cfun_returns_in_fpr_p ()) | |
5f5fe6d9 | 10690 | mips16_copy_fpr_return_value (); |
1f2d8f51 | 10691 | |
be763023 RS |
10692 | /* Split the frame into two. STEP1 is the amount of stack we should |
10693 | deallocate before restoring the registers. STEP2 is the amount we | |
10694 | should deallocate afterwards. | |
10695 | ||
10696 | Start off by assuming that no registers need to be restored. */ | |
65239d20 RS |
10697 | frame = &cfun->machine->frame; |
10698 | step1 = frame->total_size; | |
be763023 RS |
10699 | step2 = 0; |
10700 | ||
f374e413 | 10701 | /* Work out which register holds the frame address. */ |
be763023 RS |
10702 | if (!frame_pointer_needed) |
10703 | base = stack_pointer_rtx; | |
10704 | else | |
0fb5ac6f | 10705 | { |
be763023 | 10706 | base = hard_frame_pointer_rtx; |
65239d20 | 10707 | step1 -= frame->hard_frame_pointer_offset; |
0fb5ac6f | 10708 | } |
3bd0817d RS |
10709 | mips_epilogue.cfa_reg = base; |
10710 | mips_epilogue.cfa_offset = step1; | |
10711 | mips_epilogue.cfa_restores = NULL_RTX; | |
0fb5ac6f | 10712 | |
be763023 RS |
10713 | /* If we need to restore registers, deallocate as much stack as |
10714 | possible in the second step without going out of range. */ | |
e19da24c CF |
10715 | if ((frame->mask | frame->fmask | frame->acc_mask) != 0 |
10716 | || frame->num_cop0_regs > 0) | |
0fb5ac6f | 10717 | { |
be763023 RS |
10718 | step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP); |
10719 | step1 -= step2; | |
10720 | } | |
f5963e61 | 10721 | |
d9b59f56 RS |
10722 | /* Get an rtx for STEP1 that we can add to BASE. */ |
10723 | adjust = GEN_INT (step1); | |
10724 | if (!SMALL_OPERAND (step1)) | |
be763023 | 10725 | { |
d9b59f56 RS |
10726 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust); |
10727 | adjust = MIPS_EPILOGUE_TEMP (Pmode); | |
be763023 | 10728 | } |
d9b59f56 | 10729 | mips_deallocate_stack (base, adjust, step2); |
282cb01b | 10730 | |
14976818 RS |
10731 | /* If we're using addressing macros, $gp is implicitly used by all |
10732 | SYMBOL_REFs. We must emit a blockage insn before restoring $gp | |
10733 | from the stack. */ | |
10734 | if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS) | |
be763023 | 10735 | emit_insn (gen_blockage ()); |
282cb01b | 10736 | |
3bd0817d | 10737 | mips_epilogue.cfa_restore_sp_offset = step2; |
65239d20 | 10738 | if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0) |
e1260576 RS |
10739 | { |
10740 | unsigned int regno, mask; | |
10741 | HOST_WIDE_INT offset; | |
10742 | rtx restore; | |
10743 | ||
10744 | /* Generate the restore instruction. */ | |
65239d20 | 10745 | mask = frame->mask; |
e1260576 RS |
10746 | restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2); |
10747 | ||
10748 | /* Restore any other registers manually. */ | |
10749 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
10750 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
10751 | { | |
6e75e6e3 RS |
10752 | offset -= UNITS_PER_WORD; |
10753 | mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg); | |
e1260576 | 10754 | } |
be763023 | 10755 | |
e1260576 RS |
10756 | /* Restore the remaining registers and deallocate the final bit |
10757 | of the frame. */ | |
d9b59f56 | 10758 | mips_frame_barrier (); |
e1260576 | 10759 | emit_insn (restore); |
3bd0817d | 10760 | mips_epilogue_set_cfa (stack_pointer_rtx, 0); |
e1260576 RS |
10761 | } |
10762 | else | |
10763 | { | |
10764 | /* Restore the registers. */ | |
e19da24c CF |
10765 | mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg); |
10766 | mips_for_each_saved_gpr_and_fpr (frame->total_size - step2, | |
10767 | mips_restore_reg); | |
e1260576 | 10768 | |
e19da24c CF |
10769 | if (cfun->machine->interrupt_handler_p) |
10770 | { | |
10771 | HOST_WIDE_INT offset; | |
10772 | rtx mem; | |
10773 | ||
10774 | offset = frame->cop0_sp_offset - (frame->total_size - step2); | |
10775 | if (!cfun->machine->keep_interrupts_masked_p) | |
10776 | { | |
10777 | /* Restore the original EPC. */ | |
10778 | mem = gen_frame_mem (word_mode, | |
10779 | plus_constant (stack_pointer_rtx, offset)); | |
10780 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); | |
10781 | offset -= UNITS_PER_WORD; | |
10782 | ||
10783 | /* Move to COP0 EPC. */ | |
10784 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM), | |
10785 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10786 | } | |
10787 | ||
10788 | /* Restore the original Status. */ | |
10789 | mem = gen_frame_mem (word_mode, | |
10790 | plus_constant (stack_pointer_rtx, offset)); | |
10791 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); | |
10792 | offset -= UNITS_PER_WORD; | |
10793 | ||
10794 | /* If we don't use shoadow register set, we need to update SP. */ | |
d9b59f56 RS |
10795 | if (!cfun->machine->use_shadow_register_set_p) |
10796 | mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0); | |
3bd0817d RS |
10797 | else |
10798 | /* The choice of position is somewhat arbitrary in this case. */ | |
10799 | mips_epilogue_emit_cfa_restores (); | |
e19da24c CF |
10800 | |
10801 | /* Move to COP0 Status. */ | |
10802 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
10803 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10804 | } | |
10805 | else | |
d9b59f56 RS |
10806 | /* Deallocate the final bit of the frame. */ |
10807 | mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0); | |
e1260576 | 10808 | } |
3bd0817d | 10809 | gcc_assert (!mips_epilogue.cfa_restores); |
91e01231 | 10810 | |
71cc389b | 10811 | /* Add in the __builtin_eh_return stack adjustment. We need to |
65239d20 | 10812 | use a temporary in MIPS16 code. */ |
e3b5732b | 10813 | if (crtl->calls_eh_return) |
be763023 RS |
10814 | { |
10815 | if (TARGET_MIPS16) | |
10816 | { | |
51e7252a | 10817 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx); |
be763023 RS |
10818 | emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode), |
10819 | MIPS_EPILOGUE_TEMP (Pmode), | |
10820 | EH_RETURN_STACKADJ_RTX)); | |
51e7252a | 10821 | mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode)); |
9e800206 | 10822 | } |
be763023 RS |
10823 | else |
10824 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10825 | stack_pointer_rtx, | |
10826 | EH_RETURN_STACKADJ_RTX)); | |
0fb5ac6f | 10827 | } |
be763023 | 10828 | |
cafe096b EC |
10829 | if (!sibcall_p) |
10830 | { | |
2f7e2abb | 10831 | mips_expand_before_return (); |
e19da24c CF |
10832 | if (cfun->machine->interrupt_handler_p) |
10833 | { | |
10834 | /* Interrupt handlers generate eret or deret. */ | |
10835 | if (cfun->machine->use_debug_exception_return_p) | |
10836 | emit_jump_insn (gen_mips_deret ()); | |
10837 | else | |
10838 | emit_jump_insn (gen_mips_eret ()); | |
10839 | } | |
10840 | else | |
10841 | { | |
35511751 | 10842 | rtx pat; |
e19da24c CF |
10843 | |
10844 | /* When generating MIPS16 code, the normal | |
10845 | mips_for_each_saved_gpr_and_fpr path will restore the return | |
10846 | address into $7 rather than $31. */ | |
10847 | if (TARGET_MIPS16 | |
10848 | && !GENERATE_MIPS16E_SAVE_RESTORE | |
293593b1 | 10849 | && BITSET_P (frame->mask, RETURN_ADDR_REGNUM)) |
35511751 BS |
10850 | { |
10851 | /* simple_returns cannot rely on values that are only available | |
10852 | on paths through the epilogue (because return paths that do | |
10853 | not pass through the epilogue may nevertheless reuse a | |
10854 | simple_return that occurs at the end of the epilogue). | |
10855 | Use a normal return here instead. */ | |
10856 | rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7); | |
10857 | pat = gen_return_internal (reg); | |
10858 | } | |
e19da24c | 10859 | else |
35511751 BS |
10860 | { |
10861 | rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); | |
10862 | pat = gen_simple_return_internal (reg); | |
10863 | } | |
10864 | emit_jump_insn (pat); | |
e19da24c CF |
10865 | } |
10866 | } | |
10867 | ||
10868 | /* Search from the beginning to the first use of K0 or K1. */ | |
10869 | if (cfun->machine->interrupt_handler_p | |
10870 | && !cfun->machine->keep_interrupts_masked_p) | |
10871 | { | |
10872 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
10873 | if (INSN_P (insn) | |
10874 | && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL)) | |
10875 | break; | |
10876 | gcc_assert (insn != NULL_RTX); | |
10877 | /* Insert disable interrupts before the first use of K0 or K1. */ | |
10878 | emit_insn_before (gen_mips_di (), insn); | |
10879 | emit_insn_before (gen_mips_ehb (), insn); | |
cafe096b | 10880 | } |
cee98a59 | 10881 | } |
cee98a59 | 10882 | \f |
f5963e61 | 10883 | /* Return nonzero if this function is known to have a null epilogue. |
cee98a59 MM |
10884 | This allows the optimizer to omit jumps to jumps if no stack |
10885 | was created. */ | |
10886 | ||
65239d20 | 10887 | bool |
b4966b1b | 10888 | mips_can_use_return_insn (void) |
cee98a59 | 10889 | { |
e19da24c CF |
10890 | /* Interrupt handlers need to go through the epilogue. */ |
10891 | if (cfun->machine->interrupt_handler_p) | |
10892 | return false; | |
10893 | ||
65239d20 RS |
10894 | if (!reload_completed) |
10895 | return false; | |
cee98a59 | 10896 | |
e3b5732b | 10897 | if (crtl->profile) |
65239d20 | 10898 | return false; |
1f2d8f51 | 10899 | |
65239d20 RS |
10900 | /* In MIPS16 mode, a function that returns a floating-point value |
10901 | needs to arrange to copy the return value into the floating-point | |
2bcb2ab3 | 10902 | registers. */ |
a38e0142 | 10903 | if (mips16_cfun_returns_in_fpr_p ()) |
65239d20 | 10904 | return false; |
2bcb2ab3 | 10905 | |
16dc5c28 | 10906 | return cfun->machine->frame.total_size == 0; |
cee98a59 | 10907 | } |
9753d4e4 | 10908 | \f |
5f5fe6d9 RS |
10909 | /* Return true if register REGNO can store a value of mode MODE. |
10910 | The result of this function is cached in mips_hard_regno_mode_ok. */ | |
10911 | ||
10912 | static bool | |
10913 | mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode) | |
10914 | { | |
10915 | unsigned int size; | |
0a2aaacc | 10916 | enum mode_class mclass; |
5f5fe6d9 RS |
10917 | |
10918 | if (mode == CCV2mode) | |
10919 | return (ISA_HAS_8CC | |
10920 | && ST_REG_P (regno) | |
10921 | && (regno - ST_REG_FIRST) % 2 == 0); | |
10922 | ||
10923 | if (mode == CCV4mode) | |
10924 | return (ISA_HAS_8CC | |
10925 | && ST_REG_P (regno) | |
10926 | && (regno - ST_REG_FIRST) % 4 == 0); | |
10927 | ||
10928 | if (mode == CCmode) | |
10929 | { | |
10930 | if (!ISA_HAS_8CC) | |
10931 | return regno == FPSW_REGNUM; | |
10932 | ||
10933 | return (ST_REG_P (regno) | |
10934 | || GP_REG_P (regno) | |
10935 | || FP_REG_P (regno)); | |
10936 | } | |
10937 | ||
10938 | size = GET_MODE_SIZE (mode); | |
0a2aaacc | 10939 | mclass = GET_MODE_CLASS (mode); |
5f5fe6d9 RS |
10940 | |
10941 | if (GP_REG_P (regno)) | |
10942 | return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; | |
10943 | ||
10944 | if (FP_REG_P (regno) | |
10945 | && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0 | |
10946 | || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG))) | |
10947 | { | |
10948 | /* Allow TFmode for CCmode reloads. */ | |
10949 | if (mode == TFmode && ISA_HAS_8CC) | |
10950 | return true; | |
10951 | ||
93581857 MS |
10952 | /* Allow 64-bit vector modes for Loongson-2E/2F. */ |
10953 | if (TARGET_LOONGSON_VECTORS | |
10954 | && (mode == V2SImode | |
10955 | || mode == V4HImode | |
10956 | || mode == V8QImode | |
10957 | || mode == DImode)) | |
10958 | return true; | |
10959 | ||
0a2aaacc KG |
10960 | if (mclass == MODE_FLOAT |
10961 | || mclass == MODE_COMPLEX_FLOAT | |
10962 | || mclass == MODE_VECTOR_FLOAT) | |
5f5fe6d9 RS |
10963 | return size <= UNITS_PER_FPVALUE; |
10964 | ||
10965 | /* Allow integer modes that fit into a single register. We need | |
10966 | to put integers into FPRs when using instructions like CVT | |
10967 | and TRUNC. There's no point allowing sizes smaller than a word, | |
10968 | because the FPU has no appropriate load/store instructions. */ | |
0a2aaacc | 10969 | if (mclass == MODE_INT) |
5f5fe6d9 RS |
10970 | return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG; |
10971 | } | |
10972 | ||
10973 | if (ACC_REG_P (regno) | |
10974 | && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) | |
10975 | { | |
21dfc6dc RS |
10976 | if (MD_REG_P (regno)) |
10977 | { | |
10978 | /* After a multiplication or division, clobbering HI makes | |
10979 | the value of LO unpredictable, and vice versa. This means | |
10980 | that, for all interesting cases, HI and LO are effectively | |
10981 | a single register. | |
10982 | ||
10983 | We model this by requiring that any value that uses HI | |
10984 | also uses LO. */ | |
10985 | if (size <= UNITS_PER_WORD * 2) | |
10986 | return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); | |
10987 | } | |
10988 | else | |
10989 | { | |
10990 | /* DSP accumulators do not have the same restrictions as | |
10991 | HI and LO, so we can treat them as normal doubleword | |
10992 | registers. */ | |
10993 | if (size <= UNITS_PER_WORD) | |
10994 | return true; | |
5f5fe6d9 | 10995 | |
21dfc6dc RS |
10996 | if (size <= UNITS_PER_WORD * 2 |
10997 | && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) | |
10998 | return true; | |
10999 | } | |
5f5fe6d9 RS |
11000 | } |
11001 | ||
11002 | if (ALL_COP_REG_P (regno)) | |
0a2aaacc | 11003 | return mclass == MODE_INT && size <= UNITS_PER_WORD; |
5f5fe6d9 | 11004 | |
dbc90b65 RS |
11005 | if (regno == GOT_VERSION_REGNUM) |
11006 | return mode == SImode; | |
11007 | ||
5f5fe6d9 RS |
11008 | return false; |
11009 | } | |
11010 | ||
c862c910 | 11011 | /* Implement HARD_REGNO_NREGS. */ |
b85aed9e | 11012 | |
ab77a036 RS |
11013 | unsigned int |
11014 | mips_hard_regno_nregs (int regno, enum machine_mode mode) | |
b85aed9e | 11015 | { |
ab77a036 | 11016 | if (ST_REG_P (regno)) |
c862c910 RS |
11017 | /* The size of FP status registers is always 4, because they only hold |
11018 | CCmode values, and CCmode is always considered to be 4 bytes wide. */ | |
11019 | return (GET_MODE_SIZE (mode) + 3) / 4; | |
b85aed9e | 11020 | |
c862c910 RS |
11021 | if (FP_REG_P (regno)) |
11022 | return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; | |
e440de0e | 11023 | |
c862c910 RS |
11024 | /* All other registers are word-sized. */ |
11025 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
11026 | } | |
6fb5fa3c | 11027 | |
c862c910 RS |
11028 | /* Implement CLASS_MAX_NREGS, taking the maximum of the cases |
11029 | in mips_hard_regno_nregs. */ | |
f5678792 | 11030 | |
ab77a036 | 11031 | int |
0a2aaacc | 11032 | mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode) |
ab77a036 | 11033 | { |
c862c910 RS |
11034 | int size; |
11035 | HARD_REG_SET left; | |
11036 | ||
11037 | size = 0x8000; | |
0a2aaacc | 11038 | COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); |
c862c910 RS |
11039 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) |
11040 | { | |
894113c3 RS |
11041 | if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode)) |
11042 | size = MIN (size, 4); | |
c862c910 RS |
11043 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); |
11044 | } | |
11045 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) | |
11046 | { | |
894113c3 RS |
11047 | if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode)) |
11048 | size = MIN (size, UNITS_PER_FPREG); | |
c862c910 RS |
11049 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); |
11050 | } | |
11051 | if (!hard_reg_set_empty_p (left)) | |
11052 | size = MIN (size, UNITS_PER_WORD); | |
11053 | return (GET_MODE_SIZE (mode) + size - 1) / size; | |
ab77a036 | 11054 | } |
b85aed9e | 11055 | |
65239d20 | 11056 | /* Implement CANNOT_CHANGE_MODE_CLASS. */ |
b85aed9e | 11057 | |
ab77a036 | 11058 | bool |
7dab511c RH |
11059 | mips_cannot_change_mode_class (enum machine_mode from, |
11060 | enum machine_mode to, | |
0a2aaacc | 11061 | enum reg_class rclass) |
ab77a036 | 11062 | { |
7dab511c RH |
11063 | /* Allow conversions between different Loongson integer vectors, |
11064 | and between those vectors and DImode. */ | |
11065 | if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8 | |
11066 | && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to)) | |
11067 | return false; | |
11068 | ||
11069 | /* Otherwise, there are several problems with changing the modes of | |
11070 | values in floating-point registers: | |
b85aed9e | 11071 | |
ab77a036 | 11072 | - When a multi-word value is stored in paired floating-point |
dd5a833e MS |
11073 | registers, the first register always holds the low word. We |
11074 | therefore can't allow FPRs to change between single-word and | |
11075 | multi-word modes on big-endian targets. | |
b85aed9e | 11076 | |
dd5a833e MS |
11077 | - GCC assumes that each word of a multiword register can be |
11078 | accessed individually using SUBREGs. This is not true for | |
11079 | floating-point registers if they are bigger than a word. | |
b85aed9e | 11080 | |
ab77a036 | 11081 | - Loading a 32-bit value into a 64-bit floating-point register |
dd5a833e MS |
11082 | will not sign-extend the value, despite what LOAD_EXTEND_OP |
11083 | says. We can't allow FPRs to change from SImode to a wider | |
11084 | mode on 64-bit targets. | |
b85aed9e | 11085 | |
dd5a833e MS |
11086 | - If the FPU has already interpreted a value in one format, we |
11087 | must not ask it to treat the value as having a different | |
11088 | format. | |
b85aed9e | 11089 | |
43029c10 | 11090 | We therefore disallow all mode changes involving FPRs. */ |
7dab511c | 11091 | |
0a2aaacc | 11092 | return reg_classes_intersect_p (FP_REGS, rclass); |
ab77a036 | 11093 | } |
b85aed9e | 11094 | |
42db504c SB |
11095 | /* Implement target hook small_register_classes_for_mode_p. */ |
11096 | ||
11097 | static bool | |
11098 | mips_small_register_classes_for_mode_p (enum machine_mode mode | |
11099 | ATTRIBUTE_UNUSED) | |
11100 | { | |
11101 | return TARGET_MIPS16; | |
11102 | } | |
11103 | ||
ab77a036 | 11104 | /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */ |
b85aed9e | 11105 | |
ab77a036 RS |
11106 | static bool |
11107 | mips_mode_ok_for_mov_fmt_p (enum machine_mode mode) | |
11108 | { | |
11109 | switch (mode) | |
b85aed9e | 11110 | { |
ab77a036 RS |
11111 | case SFmode: |
11112 | return TARGET_HARD_FLOAT; | |
b85aed9e | 11113 | |
ab77a036 RS |
11114 | case DFmode: |
11115 | return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT; | |
b85aed9e | 11116 | |
ab77a036 RS |
11117 | case V2SFmode: |
11118 | return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT; | |
b85aed9e | 11119 | |
ab77a036 RS |
11120 | default: |
11121 | return false; | |
b85aed9e | 11122 | } |
b85aed9e | 11123 | } |
9753d4e4 | 11124 | |
e5a2b69d RS |
11125 | /* Implement MODES_TIEABLE_P. */ |
11126 | ||
11127 | bool | |
11128 | mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
11129 | { | |
11130 | /* FPRs allow no mode punning, so it's not worth tying modes if we'd | |
11131 | prefer to put one of them in FPRs. */ | |
11132 | return (mode1 == mode2 | |
11133 | || (!mips_mode_ok_for_mov_fmt_p (mode1) | |
11134 | && !mips_mode_ok_for_mov_fmt_p (mode2))); | |
11135 | } | |
11136 | ||
ef78aed6 | 11137 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
7dac2f89 | 11138 | |
ef78aed6 AS |
11139 | static reg_class_t |
11140 | mips_preferred_reload_class (rtx x, reg_class_t rclass) | |
ab77a036 | 11141 | { |
0a2aaacc | 11142 | if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass)) |
ab77a036 | 11143 | return LEA_REGS; |
9753d4e4 | 11144 | |
0a2aaacc | 11145 | if (reg_class_subset_p (FP_REGS, rclass) |
ab77a036 RS |
11146 | && mips_mode_ok_for_mov_fmt_p (GET_MODE (x))) |
11147 | return FP_REGS; | |
94b9aa66 | 11148 | |
0a2aaacc KG |
11149 | if (reg_class_subset_p (GR_REGS, rclass)) |
11150 | rclass = GR_REGS; | |
94b9aa66 | 11151 | |
0a2aaacc KG |
11152 | if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass)) |
11153 | rclass = M16_REGS; | |
d6b5193b | 11154 | |
0a2aaacc | 11155 | return rclass; |
94b9aa66 RS |
11156 | } |
11157 | ||
aea8cb37 RS |
11158 | /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. |
11159 | Return a "canonical" class to represent it in later calculations. */ | |
91455597 | 11160 | |
faa832a7 AS |
11161 | static reg_class_t |
11162 | mips_canonicalize_move_class (reg_class_t rclass) | |
ab77a036 | 11163 | { |
aea8cb37 RS |
11164 | /* All moves involving accumulator registers have the same cost. */ |
11165 | if (reg_class_subset_p (rclass, ACC_REGS)) | |
11166 | rclass = ACC_REGS; | |
11167 | ||
11168 | /* Likewise promote subclasses of general registers to the most | |
11169 | interesting containing class. */ | |
11170 | if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS)) | |
11171 | rclass = M16_REGS; | |
11172 | else if (reg_class_subset_p (rclass, GENERAL_REGS)) | |
11173 | rclass = GENERAL_REGS; | |
11174 | ||
11175 | return rclass; | |
11176 | } | |
11177 | ||
11178 | /* Return the cost of moving a value of mode MODE from a register of | |
11179 | class FROM to a GPR. Return 0 for classes that are unions of other | |
11180 | classes handled by this function. */ | |
11181 | ||
11182 | static int | |
11183 | mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
faa832a7 | 11184 | reg_class_t from) |
aea8cb37 RS |
11185 | { |
11186 | switch (from) | |
9753d4e4 | 11187 | { |
aea8cb37 RS |
11188 | case GENERAL_REGS: |
11189 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
11190 | return 2; | |
11191 | ||
11192 | case ACC_REGS: | |
11193 | /* MFLO and MFHI. */ | |
11194 | return 6; | |
11195 | ||
11196 | case FP_REGS: | |
11197 | /* MFC1, etc. */ | |
11198 | return 4; | |
11199 | ||
11200 | case ST_REGS: | |
11201 | /* LUI followed by MOVF. */ | |
11202 | return 4; | |
11203 | ||
11204 | case COP0_REGS: | |
11205 | case COP2_REGS: | |
11206 | case COP3_REGS: | |
11207 | /* This choice of value is historical. */ | |
11208 | return 5; | |
11209 | ||
11210 | default: | |
11211 | return 0; | |
9753d4e4 | 11212 | } |
aea8cb37 RS |
11213 | } |
11214 | ||
11215 | /* Return the cost of moving a value of mode MODE from a GPR to a | |
11216 | register of class TO. Return 0 for classes that are unions of | |
11217 | other classes handled by this function. */ | |
11218 | ||
11219 | static int | |
faa832a7 | 11220 | mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to) |
aea8cb37 RS |
11221 | { |
11222 | switch (to) | |
9753d4e4 | 11223 | { |
aea8cb37 RS |
11224 | case GENERAL_REGS: |
11225 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
11226 | return 2; | |
11227 | ||
11228 | case ACC_REGS: | |
11229 | /* MTLO and MTHI. */ | |
11230 | return 6; | |
11231 | ||
11232 | case FP_REGS: | |
11233 | /* MTC1, etc. */ | |
11234 | return 4; | |
11235 | ||
11236 | case ST_REGS: | |
11237 | /* A secondary reload through an FPR scratch. */ | |
11238 | return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS) | |
11239 | + mips_register_move_cost (mode, FP_REGS, ST_REGS)); | |
11240 | ||
11241 | case COP0_REGS: | |
11242 | case COP2_REGS: | |
11243 | case COP3_REGS: | |
11244 | /* This choice of value is historical. */ | |
11245 | return 5; | |
11246 | ||
11247 | default: | |
11248 | return 0; | |
9753d4e4 | 11249 | } |
aea8cb37 RS |
11250 | } |
11251 | ||
faa832a7 | 11252 | /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the |
aea8cb37 RS |
11253 | maximum of the move costs for subclasses; regclass will work out |
11254 | the maximum for us. */ | |
11255 | ||
faa832a7 | 11256 | static int |
aea8cb37 | 11257 | mips_register_move_cost (enum machine_mode mode, |
faa832a7 | 11258 | reg_class_t from, reg_class_t to) |
aea8cb37 | 11259 | { |
faa832a7 | 11260 | reg_class_t dregs; |
aea8cb37 RS |
11261 | int cost1, cost2; |
11262 | ||
11263 | from = mips_canonicalize_move_class (from); | |
11264 | to = mips_canonicalize_move_class (to); | |
11265 | ||
11266 | /* Handle moves that can be done without using general-purpose registers. */ | |
11267 | if (from == FP_REGS) | |
a318179e | 11268 | { |
aea8cb37 RS |
11269 | if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode)) |
11270 | /* MOV.FMT. */ | |
ab77a036 | 11271 | return 4; |
aea8cb37 RS |
11272 | if (to == ST_REGS) |
11273 | /* The sequence generated by mips_expand_fcc_reload. */ | |
11274 | return 8; | |
ab77a036 | 11275 | } |
aea8cb37 RS |
11276 | |
11277 | /* Handle cases in which only one class deviates from the ideal. */ | |
11278 | dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS; | |
11279 | if (from == dregs) | |
11280 | return mips_move_from_gpr_cost (mode, to); | |
11281 | if (to == dregs) | |
11282 | return mips_move_to_gpr_cost (mode, from); | |
11283 | ||
11284 | /* Handles cases that require a GPR temporary. */ | |
11285 | cost1 = mips_move_to_gpr_cost (mode, from); | |
11286 | if (cost1 != 0) | |
ab77a036 | 11287 | { |
aea8cb37 RS |
11288 | cost2 = mips_move_from_gpr_cost (mode, to); |
11289 | if (cost2 != 0) | |
11290 | return cost1 + cost2; | |
a318179e RS |
11291 | } |
11292 | ||
aea8cb37 | 11293 | return 0; |
9753d4e4 | 11294 | } |
ea462dd0 | 11295 | |
faa832a7 AS |
11296 | /* Implement TARGET_MEMORY_MOVE_COST. */ |
11297 | ||
11298 | static int | |
11299 | mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) | |
11300 | { | |
11301 | return (mips_cost->memory_latency | |
11302 | + memory_move_secondary_cost (mode, rclass, in)); | |
11303 | } | |
11304 | ||
65239d20 | 11305 | /* Return the register class required for a secondary register when |
0a2aaacc | 11306 | copying between one of the registers in RCLASS and value X, which |
65239d20 RS |
11307 | has mode MODE. X is the source of the move if IN_P, otherwise it |
11308 | is the destination. Return NO_REGS if no secondary register is | |
11309 | needed. */ | |
ea462dd0 | 11310 | |
ab77a036 | 11311 | enum reg_class |
0a2aaacc | 11312 | mips_secondary_reload_class (enum reg_class rclass, |
65239d20 | 11313 | enum machine_mode mode, rtx x, bool in_p) |
ea462dd0 | 11314 | { |
ab77a036 | 11315 | int regno; |
ea462dd0 | 11316 | |
ab77a036 RS |
11317 | /* If X is a constant that cannot be loaded into $25, it must be loaded |
11318 | into some other GPR. No other register class allows a direct move. */ | |
11319 | if (mips_dangerous_for_la25_p (x)) | |
0a2aaacc | 11320 | return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS; |
c988af2b | 11321 | |
ab77a036 RS |
11322 | regno = true_regnum (x); |
11323 | if (TARGET_MIPS16) | |
11324 | { | |
11325 | /* In MIPS16 mode, every move must involve a member of M16_REGS. */ | |
0a2aaacc | 11326 | if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno)) |
ab77a036 | 11327 | return M16_REGS; |
c988af2b | 11328 | |
ab77a036 RS |
11329 | return NO_REGS; |
11330 | } | |
c988af2b | 11331 | |
ab77a036 RS |
11332 | /* Copying from accumulator registers to anywhere other than a general |
11333 | register requires a temporary general register. */ | |
0a2aaacc | 11334 | if (reg_class_subset_p (rclass, ACC_REGS)) |
ab77a036 RS |
11335 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; |
11336 | if (ACC_REG_P (regno)) | |
0a2aaacc | 11337 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
c988af2b | 11338 | |
ab77a036 | 11339 | /* We can only copy a value to a condition code register from a |
65239d20 RS |
11340 | floating-point register, and even then we require a scratch |
11341 | floating-point register. We can only copy a value out of a | |
11342 | condition-code register into a general register. */ | |
0a2aaacc | 11343 | if (reg_class_subset_p (rclass, ST_REGS)) |
c988af2b | 11344 | { |
ab77a036 RS |
11345 | if (in_p) |
11346 | return FP_REGS; | |
11347 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; | |
11348 | } | |
11349 | if (ST_REG_P (regno)) | |
11350 | { | |
11351 | if (!in_p) | |
11352 | return FP_REGS; | |
0a2aaacc | 11353 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 | 11354 | } |
c988af2b | 11355 | |
0a2aaacc | 11356 | if (reg_class_subset_p (rclass, FP_REGS)) |
ab77a036 RS |
11357 | { |
11358 | if (MEM_P (x) | |
11359 | && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)) | |
11360 | /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use | |
11361 | pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */ | |
11362 | return NO_REGS; | |
c988af2b | 11363 | |
ab77a036 RS |
11364 | if (GP_REG_P (regno) || x == CONST0_RTX (mode)) |
11365 | /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */ | |
11366 | return NO_REGS; | |
c988af2b | 11367 | |
fbbf66e7 | 11368 | if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x)) |
ab77a036 RS |
11369 | /* We can force the constant to memory and use lwc1 |
11370 | and ldc1. As above, we will use pairs of lwc1s if | |
11371 | ldc1 is not supported. */ | |
11372 | return NO_REGS; | |
11373 | ||
11374 | if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode)) | |
11375 | /* In this case we can use mov.fmt. */ | |
11376 | return NO_REGS; | |
11377 | ||
11378 | /* Otherwise, we need to reload through an integer register. */ | |
11379 | return GR_REGS; | |
c988af2b | 11380 | } |
ab77a036 | 11381 | if (FP_REG_P (regno)) |
0a2aaacc | 11382 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 RS |
11383 | |
11384 | return NO_REGS; | |
c988af2b RS |
11385 | } |
11386 | ||
65239d20 | 11387 | /* Implement TARGET_MODE_REP_EXTENDED. */ |
c988af2b | 11388 | |
ab77a036 RS |
11389 | static int |
11390 | mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep) | |
11391 | { | |
65239d20 | 11392 | /* On 64-bit targets, SImode register values are sign-extended to DImode. */ |
ab77a036 RS |
11393 | if (TARGET_64BIT && mode == SImode && mode_rep == DImode) |
11394 | return SIGN_EXTEND; | |
c988af2b | 11395 | |
ab77a036 RS |
11396 | return UNKNOWN; |
11397 | } | |
65239d20 RS |
11398 | \f |
11399 | /* Implement TARGET_VALID_POINTER_MODE. */ | |
c988af2b | 11400 | |
ab77a036 RS |
11401 | static bool |
11402 | mips_valid_pointer_mode (enum machine_mode mode) | |
11403 | { | |
65239d20 | 11404 | return mode == SImode || (TARGET_64BIT && mode == DImode); |
ab77a036 | 11405 | } |
c988af2b | 11406 | |
65239d20 | 11407 | /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */ |
c988af2b RS |
11408 | |
11409 | static bool | |
ab77a036 | 11410 | mips_vector_mode_supported_p (enum machine_mode mode) |
c988af2b | 11411 | { |
ab77a036 RS |
11412 | switch (mode) |
11413 | { | |
11414 | case V2SFmode: | |
11415 | return TARGET_PAIRED_SINGLE_FLOAT; | |
c988af2b | 11416 | |
ab77a036 RS |
11417 | case V2HImode: |
11418 | case V4QImode: | |
11419 | case V2HQmode: | |
11420 | case V2UHQmode: | |
11421 | case V2HAmode: | |
11422 | case V2UHAmode: | |
11423 | case V4QQmode: | |
11424 | case V4UQQmode: | |
11425 | return TARGET_DSP; | |
c988af2b | 11426 | |
93581857 MS |
11427 | case V2SImode: |
11428 | case V4HImode: | |
11429 | case V8QImode: | |
11430 | return TARGET_LOONGSON_VECTORS; | |
11431 | ||
ab77a036 RS |
11432 | default: |
11433 | return false; | |
11434 | } | |
11435 | } | |
c988af2b | 11436 | |
ab77a036 | 11437 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ |
c988af2b | 11438 | |
ab77a036 RS |
11439 | static bool |
11440 | mips_scalar_mode_supported_p (enum machine_mode mode) | |
c988af2b | 11441 | { |
ab77a036 RS |
11442 | if (ALL_FIXED_POINT_MODE_P (mode) |
11443 | && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) | |
11444 | return true; | |
c988af2b | 11445 | |
ab77a036 | 11446 | return default_scalar_mode_supported_p (mode); |
c988af2b | 11447 | } |
65239d20 | 11448 | \f |
cc4b5170 | 11449 | /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ |
26983c22 | 11450 | |
cc4b5170 RG |
11451 | static enum machine_mode |
11452 | mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED) | |
26983c22 | 11453 | { |
cc4b5170 RG |
11454 | if (TARGET_PAIRED_SINGLE_FLOAT |
11455 | && mode == SFmode) | |
11456 | return V2SFmode; | |
11457 | return word_mode; | |
26983c22 L |
11458 | } |
11459 | ||
65239d20 | 11460 | /* Implement TARGET_INIT_LIBFUNCS. */ |
c988af2b | 11461 | |
ab77a036 RS |
11462 | static void |
11463 | mips_init_libfuncs (void) | |
33563487 | 11464 | { |
ab77a036 | 11465 | if (TARGET_FIX_VR4120) |
c6e6f5c1 | 11466 | { |
65239d20 RS |
11467 | /* Register the special divsi3 and modsi3 functions needed to work |
11468 | around VR4120 division errata. */ | |
ab77a036 RS |
11469 | set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); |
11470 | set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); | |
33563487 JW |
11471 | } |
11472 | ||
ab77a036 | 11473 | if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI) |
a38e0142 | 11474 | { |
65239d20 | 11475 | /* Register the MIPS16 -mhard-float stubs. */ |
ab77a036 RS |
11476 | set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3"); |
11477 | set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3"); | |
11478 | set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3"); | |
11479 | set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3"); | |
c988af2b | 11480 | |
ab77a036 RS |
11481 | set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2"); |
11482 | set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2"); | |
11483 | set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2"); | |
11484 | set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2"); | |
11485 | set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2"); | |
11486 | set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2"); | |
11487 | set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2"); | |
c988af2b | 11488 | |
ab77a036 RS |
11489 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi"); |
11490 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf"); | |
11491 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf"); | |
293a36eb | 11492 | |
ab77a036 RS |
11493 | if (TARGET_DOUBLE_FLOAT) |
11494 | { | |
11495 | set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3"); | |
11496 | set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3"); | |
11497 | set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3"); | |
11498 | set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3"); | |
293a36eb | 11499 | |
ab77a036 RS |
11500 | set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2"); |
11501 | set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2"); | |
11502 | set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2"); | |
11503 | set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2"); | |
11504 | set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2"); | |
11505 | set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2"); | |
11506 | set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2"); | |
293a36eb | 11507 | |
65239d20 RS |
11508 | set_conv_libfunc (sext_optab, DFmode, SFmode, |
11509 | "__mips16_extendsfdf2"); | |
11510 | set_conv_libfunc (trunc_optab, SFmode, DFmode, | |
11511 | "__mips16_truncdfsf2"); | |
11512 | set_conv_libfunc (sfix_optab, SImode, DFmode, | |
11513 | "__mips16_fix_truncdfsi"); | |
11514 | set_conv_libfunc (sfloat_optab, DFmode, SImode, | |
11515 | "__mips16_floatsidf"); | |
11516 | set_conv_libfunc (ufloat_optab, DFmode, SImode, | |
11517 | "__mips16_floatunsidf"); | |
ab77a036 | 11518 | } |
0310e537 | 11519 | } |
e2ff10a9 RS |
11520 | |
11521 | /* The MIPS16 ISA does not have an encoding for "sync", so we rely | |
722d8b7b RH |
11522 | on an external non-MIPS16 routine to implement __sync_synchronize. |
11523 | Similarly for the rest of the ll/sc libfuncs. */ | |
e2ff10a9 | 11524 | if (TARGET_MIPS16) |
722d8b7b RH |
11525 | { |
11526 | synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); | |
11527 | init_sync_libfuncs (UNITS_PER_WORD); | |
11528 | } | |
6cdd5672 RH |
11529 | } |
11530 | ||
0c433c31 RS |
11531 | /* Build up a multi-insn sequence that loads label TARGET into $AT. */ |
11532 | ||
11533 | static void | |
11534 | mips_process_load_label (rtx target) | |
11535 | { | |
11536 | rtx base, gp, intop; | |
11537 | HOST_WIDE_INT offset; | |
11538 | ||
11539 | mips_multi_start (); | |
11540 | switch (mips_abi) | |
11541 | { | |
11542 | case ABI_N32: | |
11543 | mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0); | |
11544 | mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
11545 | break; | |
11546 | ||
11547 | case ABI_64: | |
11548 | mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0); | |
11549 | mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
11550 | break; | |
11551 | ||
11552 | default: | |
11553 | gp = pic_offset_table_rtx; | |
11554 | if (mips_cfun_has_cprestore_slot_p ()) | |
11555 | { | |
11556 | gp = gen_rtx_REG (Pmode, AT_REGNUM); | |
11557 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
11558 | if (!SMALL_OPERAND (offset)) | |
11559 | { | |
11560 | intop = GEN_INT (CONST_HIGH_PART (offset)); | |
11561 | mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0); | |
11562 | mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0); | |
11563 | ||
11564 | base = gp; | |
11565 | offset = CONST_LOW_PART (offset); | |
11566 | } | |
11567 | intop = GEN_INT (offset); | |
11568 | if (ISA_HAS_LOAD_DELAY) | |
11569 | mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0); | |
11570 | else | |
11571 | mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0); | |
11572 | } | |
11573 | if (ISA_HAS_LOAD_DELAY) | |
11574 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0); | |
11575 | else | |
11576 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0); | |
11577 | mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0); | |
11578 | break; | |
11579 | } | |
11580 | } | |
11581 | ||
11582 | /* Return the number of instructions needed to load a label into $AT. */ | |
11583 | ||
11584 | static unsigned int | |
5a486834 | 11585 | mips_load_label_num_insns (void) |
0c433c31 | 11586 | { |
5a486834 | 11587 | if (cfun->machine->load_label_num_insns == 0) |
0c433c31 RS |
11588 | { |
11589 | mips_process_load_label (pc_rtx); | |
5a486834 | 11590 | cfun->machine->load_label_num_insns = mips_multi_num_insns; |
0c433c31 | 11591 | } |
5a486834 | 11592 | return cfun->machine->load_label_num_insns; |
0c433c31 RS |
11593 | } |
11594 | ||
11595 | /* Emit an asm sequence to start a noat block and load the address | |
11596 | of a label into $1. */ | |
11597 | ||
11598 | void | |
11599 | mips_output_load_label (rtx target) | |
11600 | { | |
11601 | mips_push_asm_switch (&mips_noat); | |
11602 | if (TARGET_EXPLICIT_RELOCS) | |
11603 | { | |
11604 | mips_process_load_label (target); | |
11605 | mips_multi_write (); | |
11606 | } | |
11607 | else | |
11608 | { | |
11609 | if (Pmode == DImode) | |
11610 | output_asm_insn ("dla\t%@,%0", &target); | |
11611 | else | |
11612 | output_asm_insn ("la\t%@,%0", &target); | |
11613 | } | |
11614 | } | |
11615 | ||
ab77a036 RS |
11616 | /* Return the length of INSN. LENGTH is the initial length computed by |
11617 | attributes in the machine-description file. */ | |
97ab1175 | 11618 | |
ab77a036 RS |
11619 | int |
11620 | mips_adjust_insn_length (rtx insn, int length) | |
cff9f8d5 | 11621 | { |
0c433c31 RS |
11622 | /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length |
11623 | of a PIC long-branch sequence. Substitute the correct value. */ | |
11624 | if (length == MAX_PIC_BRANCH_LENGTH | |
11625 | && INSN_CODE (insn) >= 0 | |
11626 | && get_attr_type (insn) == TYPE_BRANCH) | |
11627 | { | |
11628 | /* Add the branch-over instruction and its delay slot, if this | |
11629 | is a conditional branch. */ | |
11630 | length = simplejump_p (insn) ? 0 : 8; | |
11631 | ||
11632 | /* Load the label into $AT and jump to it. Ignore the delay | |
11633 | slot of the jump. */ | |
5a486834 | 11634 | length += 4 * mips_load_label_num_insns() + 4; |
0c433c31 RS |
11635 | } |
11636 | ||
ab77a036 RS |
11637 | /* A unconditional jump has an unfilled delay slot if it is not part |
11638 | of a sequence. A conditional jump normally has a delay slot, but | |
11639 | does not on MIPS16. */ | |
11640 | if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn))) | |
11641 | length += 4; | |
6f428062 | 11642 | |
ab77a036 RS |
11643 | /* See how many nops might be needed to avoid hardware hazards. */ |
11644 | if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0) | |
11645 | switch (get_attr_hazard (insn)) | |
11646 | { | |
11647 | case HAZARD_NONE: | |
11648 | break; | |
6f428062 | 11649 | |
ab77a036 RS |
11650 | case HAZARD_DELAY: |
11651 | length += 4; | |
11652 | break; | |
6f428062 | 11653 | |
ab77a036 RS |
11654 | case HAZARD_HILO: |
11655 | length += 8; | |
11656 | break; | |
11657 | } | |
3d30741b | 11658 | |
65239d20 RS |
11659 | /* In order to make it easier to share MIPS16 and non-MIPS16 patterns, |
11660 | the .md file length attributes are 4-based for both modes. | |
11661 | Adjust the MIPS16 ones here. */ | |
ab77a036 RS |
11662 | if (TARGET_MIPS16) |
11663 | length /= 2; | |
3d30741b | 11664 | |
ab77a036 | 11665 | return length; |
cff9f8d5 AH |
11666 | } |
11667 | ||
ab77a036 | 11668 | /* Return the assembly code for INSN, which has the operands given by |
0c433c31 RS |
11669 | OPERANDS, and which branches to OPERANDS[0] if some condition is true. |
11670 | BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0] | |
ab77a036 RS |
11671 | is in range of a direct branch. BRANCH_IF_FALSE is an inverted |
11672 | version of BRANCH_IF_TRUE. */ | |
a6008bd8 | 11673 | |
ab77a036 RS |
11674 | const char * |
11675 | mips_output_conditional_branch (rtx insn, rtx *operands, | |
11676 | const char *branch_if_true, | |
11677 | const char *branch_if_false) | |
a6008bd8 | 11678 | { |
ab77a036 RS |
11679 | unsigned int length; |
11680 | rtx taken, not_taken; | |
a6008bd8 | 11681 | |
0c433c31 | 11682 | gcc_assert (LABEL_P (operands[0])); |
4cba945d | 11683 | |
ab77a036 RS |
11684 | length = get_attr_length (insn); |
11685 | if (length <= 8) | |
11686 | { | |
11687 | /* Just a simple conditional branch. */ | |
11688 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
11689 | return branch_if_true; | |
11690 | } | |
a6008bd8 | 11691 | |
ab77a036 RS |
11692 | /* Generate a reversed branch around a direct jump. This fallback does |
11693 | not use branch-likely instructions. */ | |
11694 | mips_branch_likely = false; | |
11695 | not_taken = gen_label_rtx (); | |
0c433c31 | 11696 | taken = operands[0]; |
2bcb2ab3 | 11697 | |
ab77a036 | 11698 | /* Generate the reversed branch to NOT_TAKEN. */ |
0c433c31 | 11699 | operands[0] = not_taken; |
ab77a036 | 11700 | output_asm_insn (branch_if_false, operands); |
3d30741b | 11701 | |
ab77a036 RS |
11702 | /* If INSN has a delay slot, we must provide delay slots for both the |
11703 | branch to NOT_TAKEN and the conditional jump. We must also ensure | |
11704 | that INSN's delay slot is executed in the appropriate cases. */ | |
11705 | if (final_sequence) | |
a6008bd8 | 11706 | { |
ab77a036 RS |
11707 | /* This first delay slot will always be executed, so use INSN's |
11708 | delay slot if is not annulled. */ | |
11709 | if (!INSN_ANNULLED_BRANCH_P (insn)) | |
11710 | { | |
11711 | final_scan_insn (XVECEXP (final_sequence, 0, 1), | |
11712 | asm_out_file, optimize, 1, NULL); | |
11713 | INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; | |
11714 | } | |
11715 | else | |
11716 | output_asm_insn ("nop", 0); | |
11717 | fprintf (asm_out_file, "\n"); | |
a6008bd8 | 11718 | } |
cafe096b | 11719 | |
ab77a036 | 11720 | /* Output the unconditional branch to TAKEN. */ |
0c433c31 RS |
11721 | if (TARGET_ABSOLUTE_JUMPS) |
11722 | output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken); | |
ab77a036 | 11723 | else |
b8eb88d0 | 11724 | { |
0c433c31 | 11725 | mips_output_load_label (taken); |
ab77a036 | 11726 | output_asm_insn ("jr\t%@%]%/", 0); |
b8eb88d0 ILT |
11727 | } |
11728 | ||
ab77a036 RS |
11729 | /* Now deal with its delay slot; see above. */ |
11730 | if (final_sequence) | |
8214bf98 | 11731 | { |
ab77a036 RS |
11732 | /* This delay slot will only be executed if the branch is taken. |
11733 | Use INSN's delay slot if is annulled. */ | |
11734 | if (INSN_ANNULLED_BRANCH_P (insn)) | |
11735 | { | |
11736 | final_scan_insn (XVECEXP (final_sequence, 0, 1), | |
11737 | asm_out_file, optimize, 1, NULL); | |
11738 | INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; | |
11739 | } | |
11740 | else | |
11741 | output_asm_insn ("nop", 0); | |
11742 | fprintf (asm_out_file, "\n"); | |
2bcb2ab3 GK |
11743 | } |
11744 | ||
ab77a036 | 11745 | /* Output NOT_TAKEN. */ |
65239d20 RS |
11746 | targetm.asm_out.internal_label (asm_out_file, "L", |
11747 | CODE_LABEL_NUMBER (not_taken)); | |
ab77a036 | 11748 | return ""; |
46299de9 | 11749 | } |
d604bca3 | 11750 | |
0c433c31 | 11751 | /* Return the assembly code for INSN, which branches to OPERANDS[0] |
65239d20 | 11752 | if some ordering condition is true. The condition is given by |
0c433c31 RS |
11753 | OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of |
11754 | OPERANDS[1]. OPERANDS[2] is the comparison's first operand; | |
ab77a036 | 11755 | its second is always zero. */ |
4977bab6 | 11756 | |
ab77a036 RS |
11757 | const char * |
11758 | mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p) | |
4977bab6 | 11759 | { |
ab77a036 | 11760 | const char *branch[2]; |
62d9f2e9 | 11761 | |
0c433c31 | 11762 | /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true. |
ab77a036 | 11763 | Make BRANCH[0] branch on the inverse condition. */ |
0c433c31 | 11764 | switch (GET_CODE (operands[1])) |
118ea793 | 11765 | { |
ab77a036 RS |
11766 | /* These cases are equivalent to comparisons against zero. */ |
11767 | case LEU: | |
11768 | inverted_p = !inverted_p; | |
11769 | /* Fall through. */ | |
11770 | case GTU: | |
0c433c31 RS |
11771 | branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0"); |
11772 | branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0"); | |
ab77a036 | 11773 | break; |
118ea793 | 11774 | |
ab77a036 RS |
11775 | /* These cases are always true or always false. */ |
11776 | case LTU: | |
11777 | inverted_p = !inverted_p; | |
11778 | /* Fall through. */ | |
11779 | case GEU: | |
0c433c31 RS |
11780 | branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0"); |
11781 | branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0"); | |
ab77a036 | 11782 | break; |
118ea793 CF |
11783 | |
11784 | default: | |
0c433c31 RS |
11785 | branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0"); |
11786 | branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0"); | |
ab77a036 | 11787 | break; |
118ea793 | 11788 | } |
ab77a036 | 11789 | return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); |
06a4ab70 | 11790 | } |
ab77a036 | 11791 | \f |
6f5a62e9 RS |
11792 | /* Start a block of code that needs access to the LL, SC and SYNC |
11793 | instructions. */ | |
11794 | ||
11795 | static void | |
11796 | mips_start_ll_sc_sync_block (void) | |
11797 | { | |
11798 | if (!ISA_HAS_LL_SC) | |
11799 | { | |
11800 | output_asm_insn (".set\tpush", 0); | |
11801 | output_asm_insn (".set\tmips2", 0); | |
11802 | } | |
11803 | } | |
11804 | ||
11805 | /* End a block started by mips_start_ll_sc_sync_block. */ | |
11806 | ||
11807 | static void | |
11808 | mips_end_ll_sc_sync_block (void) | |
11809 | { | |
11810 | if (!ISA_HAS_LL_SC) | |
11811 | output_asm_insn (".set\tpop", 0); | |
11812 | } | |
11813 | ||
11814 | /* Output and/or return the asm template for a sync instruction. */ | |
ee9a72e5 JK |
11815 | |
11816 | const char * | |
6f5a62e9 | 11817 | mips_output_sync (void) |
ee9a72e5 | 11818 | { |
6f5a62e9 RS |
11819 | mips_start_ll_sc_sync_block (); |
11820 | output_asm_insn ("sync", 0); | |
11821 | mips_end_ll_sc_sync_block (); | |
11822 | return ""; | |
11823 | } | |
40a4a37b | 11824 | |
6f5a62e9 RS |
11825 | /* Return the asm template associated with sync_insn1 value TYPE. |
11826 | IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */ | |
068ca03a | 11827 | |
6f5a62e9 RS |
11828 | static const char * |
11829 | mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p) | |
11830 | { | |
11831 | switch (type) | |
11832 | { | |
11833 | case SYNC_INSN1_MOVE: | |
11834 | return "move\t%0,%z2"; | |
11835 | case SYNC_INSN1_LI: | |
11836 | return "li\t%0,%2"; | |
11837 | case SYNC_INSN1_ADDU: | |
11838 | return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2"; | |
11839 | case SYNC_INSN1_ADDIU: | |
11840 | return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2"; | |
11841 | case SYNC_INSN1_SUBU: | |
11842 | return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2"; | |
11843 | case SYNC_INSN1_AND: | |
11844 | return "and\t%0,%1,%z2"; | |
11845 | case SYNC_INSN1_ANDI: | |
11846 | return "andi\t%0,%1,%2"; | |
11847 | case SYNC_INSN1_OR: | |
11848 | return "or\t%0,%1,%z2"; | |
11849 | case SYNC_INSN1_ORI: | |
11850 | return "ori\t%0,%1,%2"; | |
11851 | case SYNC_INSN1_XOR: | |
11852 | return "xor\t%0,%1,%z2"; | |
11853 | case SYNC_INSN1_XORI: | |
11854 | return "xori\t%0,%1,%2"; | |
11855 | } | |
11856 | gcc_unreachable (); | |
11857 | } | |
11858 | ||
11859 | /* Return the asm template associated with sync_insn2 value TYPE. */ | |
11860 | ||
11861 | static const char * | |
11862 | mips_sync_insn2_template (enum attr_sync_insn2 type) | |
11863 | { | |
11864 | switch (type) | |
11865 | { | |
11866 | case SYNC_INSN2_NOP: | |
11867 | gcc_unreachable (); | |
11868 | case SYNC_INSN2_AND: | |
11869 | return "and\t%0,%1,%z2"; | |
11870 | case SYNC_INSN2_XOR: | |
11871 | return "xor\t%0,%1,%z2"; | |
11872 | case SYNC_INSN2_NOT: | |
11873 | return "nor\t%0,%1,%."; | |
11874 | } | |
11875 | gcc_unreachable (); | |
11876 | } | |
11877 | ||
11878 | /* OPERANDS are the operands to a sync loop instruction and INDEX is | |
11879 | the value of the one of the sync_* attributes. Return the operand | |
11880 | referred to by the attribute, or DEFAULT_VALUE if the insn doesn't | |
11881 | have the associated attribute. */ | |
11882 | ||
11883 | static rtx | |
11884 | mips_get_sync_operand (rtx *operands, int index, rtx default_value) | |
11885 | { | |
11886 | if (index > 0) | |
11887 | default_value = operands[index - 1]; | |
11888 | return default_value; | |
11889 | } | |
11890 | ||
11891 | /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn | |
11892 | sequence for it. */ | |
11893 | ||
11894 | static void | |
11895 | mips_process_sync_loop (rtx insn, rtx *operands) | |
11896 | { | |
11897 | rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask; | |
11898 | rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3; | |
11899 | unsigned int tmp3_insn; | |
11900 | enum attr_sync_insn1 insn1; | |
11901 | enum attr_sync_insn2 insn2; | |
11902 | bool is_64bit_p; | |
11903 | ||
11904 | /* Read an operand from the sync_WHAT attribute and store it in | |
11905 | variable WHAT. DEFAULT is the default value if no attribute | |
11906 | is specified. */ | |
11907 | #define READ_OPERAND(WHAT, DEFAULT) \ | |
11908 | WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \ | |
11909 | DEFAULT) | |
11910 | ||
11911 | /* Read the memory. */ | |
11912 | READ_OPERAND (mem, 0); | |
11913 | gcc_assert (mem); | |
11914 | is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64); | |
11915 | ||
11916 | /* Read the other attributes. */ | |
11917 | at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM); | |
11918 | READ_OPERAND (oldval, at); | |
11919 | READ_OPERAND (newval, at); | |
11920 | READ_OPERAND (inclusive_mask, 0); | |
11921 | READ_OPERAND (exclusive_mask, 0); | |
11922 | READ_OPERAND (required_oldval, 0); | |
11923 | READ_OPERAND (insn1_op2, 0); | |
11924 | insn1 = get_attr_sync_insn1 (insn); | |
11925 | insn2 = get_attr_sync_insn2 (insn); | |
11926 | ||
11927 | mips_multi_start (); | |
11928 | ||
11929 | /* Output the release side of the memory barrier. */ | |
11930 | if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES) | |
916e9b31 DD |
11931 | { |
11932 | if (required_oldval == 0 && TARGET_OCTEON) | |
11933 | { | |
11934 | /* Octeon doesn't reorder reads, so a full barrier can be | |
11935 | created by using SYNCW to order writes combined with the | |
11936 | write from the following SC. When the SC successfully | |
11937 | completes, we know that all preceding writes are also | |
11938 | committed to the coherent memory system. It is possible | |
11939 | for a single SYNCW to fail, but a pair of them will never | |
11940 | fail, so we use two. */ | |
11941 | mips_multi_add_insn ("syncw", NULL); | |
11942 | mips_multi_add_insn ("syncw", NULL); | |
11943 | } | |
11944 | else | |
11945 | mips_multi_add_insn ("sync", NULL); | |
11946 | } | |
6f5a62e9 RS |
11947 | |
11948 | /* Output the branch-back label. */ | |
11949 | mips_multi_add_label ("1:"); | |
11950 | ||
11951 | /* OLDVAL = *MEM. */ | |
11952 | mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1", | |
11953 | oldval, mem, NULL); | |
11954 | ||
11955 | /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */ | |
11956 | if (required_oldval) | |
11957 | { | |
11958 | if (inclusive_mask == 0) | |
11959 | tmp1 = oldval; | |
11960 | else | |
11961 | { | |
11962 | gcc_assert (oldval != at); | |
11963 | mips_multi_add_insn ("and\t%0,%1,%2", | |
11964 | at, oldval, inclusive_mask, NULL); | |
11965 | tmp1 = at; | |
11966 | } | |
11967 | mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL); | |
11968 | } | |
11969 | ||
11970 | /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */ | |
11971 | if (exclusive_mask == 0) | |
11972 | tmp1 = const0_rtx; | |
11973 | else | |
11974 | { | |
11975 | gcc_assert (oldval != at); | |
11976 | mips_multi_add_insn ("and\t%0,%1,%z2", | |
11977 | at, oldval, exclusive_mask, NULL); | |
11978 | tmp1 = at; | |
11979 | } | |
11980 | ||
11981 | /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2). | |
11982 | ||
11983 | We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit | |
11984 | at least one instruction in that case. */ | |
11985 | if (insn1 == SYNC_INSN1_MOVE | |
11986 | && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP)) | |
11987 | tmp2 = insn1_op2; | |
11988 | else | |
068ca03a | 11989 | { |
6f5a62e9 RS |
11990 | mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p), |
11991 | newval, oldval, insn1_op2, NULL); | |
11992 | tmp2 = newval; | |
068ca03a | 11993 | } |
6f5a62e9 RS |
11994 | |
11995 | /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */ | |
11996 | if (insn2 == SYNC_INSN2_NOP) | |
11997 | tmp3 = tmp2; | |
11998 | else | |
11999 | { | |
12000 | mips_multi_add_insn (mips_sync_insn2_template (insn2), | |
12001 | newval, tmp2, inclusive_mask, NULL); | |
12002 | tmp3 = newval; | |
12003 | } | |
12004 | tmp3_insn = mips_multi_last_index (); | |
12005 | ||
12006 | /* $AT = $TMP1 | $TMP3. */ | |
12007 | if (tmp1 == const0_rtx || tmp3 == const0_rtx) | |
12008 | { | |
12009 | mips_multi_set_operand (tmp3_insn, 0, at); | |
12010 | tmp3 = at; | |
12011 | } | |
12012 | else | |
12013 | { | |
12014 | gcc_assert (tmp1 != tmp3); | |
12015 | mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL); | |
12016 | } | |
12017 | ||
12018 | /* if (!commit (*MEM = $AT)) goto 1. | |
12019 | ||
12020 | This will sometimes be a delayed branch; see the write code below | |
12021 | for details. */ | |
12022 | mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); | |
12023 | mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); | |
12024 | ||
12025 | /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ | |
12026 | if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) | |
12027 | { | |
12028 | mips_multi_copy_insn (tmp3_insn); | |
12029 | mips_multi_set_operand (mips_multi_last_index (), 0, newval); | |
12030 | } | |
12031 | else | |
12032 | mips_multi_add_insn ("nop", NULL); | |
12033 | ||
12034 | /* Output the acquire side of the memory barrier. */ | |
12035 | if (TARGET_SYNC_AFTER_SC) | |
12036 | mips_multi_add_insn ("sync", NULL); | |
12037 | ||
12038 | /* Output the exit label, if needed. */ | |
12039 | if (required_oldval) | |
12040 | mips_multi_add_label ("2:"); | |
12041 | ||
12042 | #undef READ_OPERAND | |
12043 | } | |
12044 | ||
12045 | /* Output and/or return the asm template for sync loop INSN, which has | |
12046 | the operands given by OPERANDS. */ | |
12047 | ||
12048 | const char * | |
12049 | mips_output_sync_loop (rtx insn, rtx *operands) | |
12050 | { | |
12051 | mips_process_sync_loop (insn, operands); | |
12052 | ||
12053 | /* Use branch-likely instructions to work around the LL/SC R10000 | |
12054 | errata. */ | |
12055 | mips_branch_likely = TARGET_FIX_R10000; | |
12056 | ||
12057 | mips_push_asm_switch (&mips_noreorder); | |
12058 | mips_push_asm_switch (&mips_nomacro); | |
12059 | mips_push_asm_switch (&mips_noat); | |
12060 | mips_start_ll_sc_sync_block (); | |
12061 | ||
12062 | mips_multi_write (); | |
12063 | ||
12064 | mips_end_ll_sc_sync_block (); | |
12065 | mips_pop_asm_switch (&mips_noat); | |
12066 | mips_pop_asm_switch (&mips_nomacro); | |
12067 | mips_pop_asm_switch (&mips_noreorder); | |
12068 | ||
12069 | return ""; | |
12070 | } | |
12071 | ||
12072 | /* Return the number of individual instructions in sync loop INSN, | |
12073 | which has the operands given by OPERANDS. */ | |
12074 | ||
12075 | unsigned int | |
12076 | mips_sync_loop_insns (rtx insn, rtx *operands) | |
12077 | { | |
12078 | mips_process_sync_loop (insn, operands); | |
12079 | return mips_multi_num_insns; | |
ee9a72e5 JK |
12080 | } |
12081 | \f | |
65239d20 RS |
12082 | /* Return the assembly code for DIV or DDIV instruction DIVISION, which has |
12083 | the operands given by OPERANDS. Add in a divide-by-zero check if needed. | |
9fc777ad | 12084 | |
ab77a036 RS |
12085 | When working around R4000 and R4400 errata, we need to make sure that |
12086 | the division is not immediately followed by a shift[1][2]. We also | |
12087 | need to stop the division from being put into a branch delay slot[3]. | |
12088 | The easiest way to avoid both problems is to add a nop after the | |
12089 | division. When a divide-by-zero check is needed, this nop can be | |
12090 | used to fill the branch delay slot. | |
9fc777ad | 12091 | |
ab77a036 RS |
12092 | [1] If a double-word or a variable shift executes immediately |
12093 | after starting an integer division, the shift may give an | |
12094 | incorrect result. See quotations of errata #16 and #28 from | |
12095 | "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" | |
12096 | in mips.md for details. | |
9fc777ad | 12097 | |
ab77a036 RS |
12098 | [2] A similar bug to [1] exists for all revisions of the |
12099 | R4000 and the R4400 when run in an MC configuration. | |
12100 | From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0": | |
d34053ed | 12101 | |
ab77a036 | 12102 | "19. In this following sequence: |
2bcb2ab3 | 12103 | |
ab77a036 RS |
12104 | ddiv (or ddivu or div or divu) |
12105 | dsll32 (or dsrl32, dsra32) | |
d6076cee | 12106 | |
ab77a036 RS |
12107 | if an MPT stall occurs, while the divide is slipping the cpu |
12108 | pipeline, then the following double shift would end up with an | |
12109 | incorrect result. | |
2bcb2ab3 | 12110 | |
ab77a036 RS |
12111 | Workaround: The compiler needs to avoid generating any |
12112 | sequence with divide followed by extended double shift." | |
2bcb2ab3 | 12113 | |
ab77a036 RS |
12114 | This erratum is also present in "MIPS R4400MC Errata, Processor |
12115 | Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0 | |
12116 | & 3.0" as errata #10 and #4, respectively. | |
2bcb2ab3 | 12117 | |
ab77a036 RS |
12118 | [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" |
12119 | (also valid for MIPS R4000MC processors): | |
2bcb2ab3 | 12120 | |
ab77a036 | 12121 | "52. R4000SC: This bug does not apply for the R4000PC. |
2bcb2ab3 | 12122 | |
ab77a036 | 12123 | There are two flavors of this bug: |
2bcb2ab3 | 12124 | |
ab77a036 RS |
12125 | 1) If the instruction just after divide takes an RF exception |
12126 | (tlb-refill, tlb-invalid) and gets an instruction cache | |
12127 | miss (both primary and secondary) and the line which is | |
12128 | currently in secondary cache at this index had the first | |
12129 | data word, where the bits 5..2 are set, then R4000 would | |
12130 | get a wrong result for the div. | |
a38e0142 | 12131 | |
ab77a036 RS |
12132 | ##1 |
12133 | nop | |
12134 | div r8, r9 | |
12135 | ------------------- # end-of page. -tlb-refill | |
12136 | nop | |
12137 | ##2 | |
12138 | nop | |
12139 | div r8, r9 | |
12140 | ------------------- # end-of page. -tlb-invalid | |
12141 | nop | |
a38e0142 | 12142 | |
ab77a036 RS |
12143 | 2) If the divide is in the taken branch delay slot, where the |
12144 | target takes RF exception and gets an I-cache miss for the | |
12145 | exception vector or where I-cache miss occurs for the | |
12146 | target address, under the above mentioned scenarios, the | |
12147 | div would get wrong results. | |
a38e0142 | 12148 | |
ab77a036 RS |
12149 | ##1 |
12150 | j r2 # to next page mapped or unmapped | |
12151 | div r8,r9 # this bug would be there as long | |
12152 | # as there is an ICache miss and | |
12153 | nop # the "data pattern" is present | |
2bcb2ab3 | 12154 | |
ab77a036 RS |
12155 | ##2 |
12156 | beq r0, r0, NextPage # to Next page | |
12157 | div r8,r9 | |
12158 | nop | |
a38e0142 | 12159 | |
ab77a036 RS |
12160 | This bug is present for div, divu, ddiv, and ddivu |
12161 | instructions. | |
a38e0142 | 12162 | |
ab77a036 RS |
12163 | Workaround: For item 1), OS could make sure that the next page |
12164 | after the divide instruction is also mapped. For item 2), the | |
12165 | compiler could make sure that the divide instruction is not in | |
12166 | the branch delay slot." | |
2bcb2ab3 | 12167 | |
ab77a036 RS |
12168 | These processors have PRId values of 0x00004220 and 0x00004300 for |
12169 | the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */ | |
2bcb2ab3 | 12170 | |
ab77a036 RS |
12171 | const char * |
12172 | mips_output_division (const char *division, rtx *operands) | |
2bcb2ab3 | 12173 | { |
ab77a036 | 12174 | const char *s; |
2bcb2ab3 | 12175 | |
ab77a036 RS |
12176 | s = division; |
12177 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) | |
2bcb2ab3 | 12178 | { |
ab77a036 RS |
12179 | output_asm_insn (s, operands); |
12180 | s = "nop"; | |
2bcb2ab3 | 12181 | } |
ab77a036 | 12182 | if (TARGET_CHECK_ZERO_DIV) |
3c7404d3 | 12183 | { |
ab77a036 RS |
12184 | if (TARGET_MIPS16) |
12185 | { | |
12186 | output_asm_insn (s, operands); | |
12187 | s = "bnez\t%2,1f\n\tbreak\t7\n1:"; | |
12188 | } | |
12189 | else if (GENERATE_DIVIDE_TRAPS) | |
67e67979 DU |
12190 | { |
12191 | /* Avoid long replay penalty on load miss by putting the trap before | |
12192 | the divide. */ | |
12193 | if (TUNE_74K) | |
12194 | output_asm_insn ("teq\t%2,%.,7", operands); | |
12195 | else | |
12196 | { | |
12197 | output_asm_insn (s, operands); | |
12198 | s = "teq\t%2,%.,7"; | |
12199 | } | |
12200 | } | |
ab77a036 RS |
12201 | else |
12202 | { | |
12203 | output_asm_insn ("%(bne\t%2,%.,1f", operands); | |
12204 | output_asm_insn (s, operands); | |
12205 | s = "break\t7%)\n1:"; | |
12206 | } | |
3c7404d3 | 12207 | } |
ab77a036 RS |
12208 | return s; |
12209 | } | |
12210 | \f | |
65239d20 RS |
12211 | /* Return true if IN_INSN is a multiply-add or multiply-subtract |
12212 | instruction and if OUT_INSN assigns to the accumulator operand. */ | |
2bcb2ab3 | 12213 | |
ab77a036 | 12214 | bool |
65239d20 | 12215 | mips_linked_madd_p (rtx out_insn, rtx in_insn) |
ab77a036 RS |
12216 | { |
12217 | rtx x; | |
2bcb2ab3 | 12218 | |
65239d20 | 12219 | x = single_set (in_insn); |
ab77a036 RS |
12220 | if (x == 0) |
12221 | return false; | |
2bcb2ab3 | 12222 | |
ab77a036 | 12223 | x = SET_SRC (x); |
2bcb2ab3 | 12224 | |
ab77a036 RS |
12225 | if (GET_CODE (x) == PLUS |
12226 | && GET_CODE (XEXP (x, 0)) == MULT | |
65239d20 | 12227 | && reg_set_p (XEXP (x, 1), out_insn)) |
ab77a036 | 12228 | return true; |
2bcb2ab3 | 12229 | |
ab77a036 RS |
12230 | if (GET_CODE (x) == MINUS |
12231 | && GET_CODE (XEXP (x, 1)) == MULT | |
65239d20 | 12232 | && reg_set_p (XEXP (x, 0), out_insn)) |
ab77a036 | 12233 | return true; |
2bcb2ab3 | 12234 | |
ab77a036 | 12235 | return false; |
2bcb2ab3 GK |
12236 | } |
12237 | ||
65239d20 RS |
12238 | /* True if the dependency between OUT_INSN and IN_INSN is on the store |
12239 | data rather than the address. We need this because the cprestore | |
12240 | pattern is type "store", but is defined using an UNSPEC_VOLATILE, | |
12241 | which causes the default routine to abort. We just return false | |
12242 | for that case. */ | |
2bcb2ab3 | 12243 | |
65239d20 | 12244 | bool |
ab77a036 | 12245 | mips_store_data_bypass_p (rtx out_insn, rtx in_insn) |
2bcb2ab3 | 12246 | { |
ab77a036 RS |
12247 | if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) |
12248 | return false; | |
2bcb2ab3 | 12249 | |
65239d20 | 12250 | return !store_data_bypass_p (out_insn, in_insn); |
ab77a036 RS |
12251 | } |
12252 | \f | |
58684fa0 MK |
12253 | |
12254 | /* Variables and flags used in scheduler hooks when tuning for | |
12255 | Loongson 2E/2F. */ | |
12256 | static struct | |
12257 | { | |
12258 | /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch | |
12259 | strategy. */ | |
12260 | ||
12261 | /* If true, then next ALU1/2 instruction will go to ALU1. */ | |
12262 | bool alu1_turn_p; | |
12263 | ||
12264 | /* If true, then next FALU1/2 unstruction will go to FALU1. */ | |
12265 | bool falu1_turn_p; | |
12266 | ||
12267 | /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */ | |
12268 | int alu1_core_unit_code; | |
12269 | int alu2_core_unit_code; | |
12270 | int falu1_core_unit_code; | |
12271 | int falu2_core_unit_code; | |
12272 | ||
12273 | /* True if current cycle has a multi instruction. | |
12274 | This flag is used in mips_ls2_dfa_post_advance_cycle. */ | |
12275 | bool cycle_has_multi_p; | |
12276 | ||
12277 | /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units. | |
12278 | These are used in mips_ls2_dfa_post_advance_cycle to initialize | |
12279 | DFA state. | |
12280 | E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2 | |
12281 | instruction to go ALU1. */ | |
12282 | rtx alu1_turn_enabled_insn; | |
12283 | rtx alu2_turn_enabled_insn; | |
12284 | rtx falu1_turn_enabled_insn; | |
12285 | rtx falu2_turn_enabled_insn; | |
12286 | } mips_ls2; | |
12287 | ||
ab77a036 RS |
12288 | /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output |
12289 | dependencies have no cost, except on the 20Kc where output-dependence | |
12290 | is treated like input-dependence. */ | |
2bcb2ab3 | 12291 | |
ab77a036 RS |
12292 | static int |
12293 | mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, | |
12294 | rtx dep ATTRIBUTE_UNUSED, int cost) | |
12295 | { | |
12296 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT | |
12297 | && TUNE_20KC) | |
12298 | return cost; | |
12299 | if (REG_NOTE_KIND (link) != 0) | |
12300 | return 0; | |
12301 | return cost; | |
12302 | } | |
a38e0142 | 12303 | |
ab77a036 RS |
12304 | /* Return the number of instructions that can be issued per cycle. */ |
12305 | ||
12306 | static int | |
12307 | mips_issue_rate (void) | |
a38e0142 | 12308 | { |
ab77a036 | 12309 | switch (mips_tune) |
a38e0142 | 12310 | { |
ab77a036 RS |
12311 | case PROCESSOR_74KC: |
12312 | case PROCESSOR_74KF2_1: | |
12313 | case PROCESSOR_74KF1_1: | |
12314 | case PROCESSOR_74KF3_2: | |
12315 | /* The 74k is not strictly quad-issue cpu, but can be seen as one | |
12316 | by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns, | |
65239d20 RS |
12317 | but in reality only a maximum of 3 insns can be issued as |
12318 | floating-point loads and stores also require a slot in the | |
12319 | AGEN pipe. */ | |
7a3446ec JK |
12320 | case PROCESSOR_R10000: |
12321 | /* All R10K Processors are quad-issue (being the first MIPS | |
12322 | processors to support this feature). */ | |
12323 | return 4; | |
ab77a036 RS |
12324 | |
12325 | case PROCESSOR_20KC: | |
12326 | case PROCESSOR_R4130: | |
12327 | case PROCESSOR_R5400: | |
12328 | case PROCESSOR_R5500: | |
12329 | case PROCESSOR_R7000: | |
12330 | case PROCESSOR_R9000: | |
ce00be9e | 12331 | case PROCESSOR_OCTEON: |
38a53a0e | 12332 | case PROCESSOR_OCTEON2: |
ab77a036 RS |
12333 | return 2; |
12334 | ||
12335 | case PROCESSOR_SB1: | |
12336 | case PROCESSOR_SB1A: | |
12337 | /* This is actually 4, but we get better performance if we claim 3. | |
12338 | This is partly because of unwanted speculative code motion with the | |
12339 | larger number, and partly because in most common cases we can't | |
12340 | reach the theoretical max of 4. */ | |
12341 | return 3; | |
12342 | ||
58684fa0 MK |
12343 | case PROCESSOR_LOONGSON_2E: |
12344 | case PROCESSOR_LOONGSON_2F: | |
98824c6f | 12345 | case PROCESSOR_LOONGSON_3A: |
58684fa0 MK |
12346 | return 4; |
12347 | ||
ab77a036 RS |
12348 | default: |
12349 | return 1; | |
a38e0142 SL |
12350 | } |
12351 | } | |
12352 | ||
58684fa0 MK |
12353 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */ |
12354 | ||
12355 | static void | |
12356 | mips_ls2_init_dfa_post_cycle_insn (void) | |
12357 | { | |
12358 | start_sequence (); | |
12359 | emit_insn (gen_ls2_alu1_turn_enabled_insn ()); | |
12360 | mips_ls2.alu1_turn_enabled_insn = get_insns (); | |
12361 | end_sequence (); | |
12362 | ||
12363 | start_sequence (); | |
12364 | emit_insn (gen_ls2_alu2_turn_enabled_insn ()); | |
12365 | mips_ls2.alu2_turn_enabled_insn = get_insns (); | |
12366 | end_sequence (); | |
12367 | ||
12368 | start_sequence (); | |
12369 | emit_insn (gen_ls2_falu1_turn_enabled_insn ()); | |
12370 | mips_ls2.falu1_turn_enabled_insn = get_insns (); | |
12371 | end_sequence (); | |
12372 | ||
12373 | start_sequence (); | |
12374 | emit_insn (gen_ls2_falu2_turn_enabled_insn ()); | |
12375 | mips_ls2.falu2_turn_enabled_insn = get_insns (); | |
12376 | end_sequence (); | |
12377 | ||
12378 | mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core"); | |
12379 | mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core"); | |
12380 | mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core"); | |
12381 | mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core"); | |
12382 | } | |
12383 | ||
12384 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook. | |
12385 | Init data used in mips_dfa_post_advance_cycle. */ | |
12386 | ||
12387 | static void | |
12388 | mips_init_dfa_post_cycle_insn (void) | |
12389 | { | |
12390 | if (TUNE_LOONGSON_2EF) | |
12391 | mips_ls2_init_dfa_post_cycle_insn (); | |
12392 | } | |
12393 | ||
12394 | /* Initialize STATE when scheduling for Loongson 2E/2F. | |
12395 | Support round-robin dispatch scheme by enabling only one of | |
12396 | ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions | |
12397 | respectively. */ | |
12398 | ||
12399 | static void | |
12400 | mips_ls2_dfa_post_advance_cycle (state_t state) | |
12401 | { | |
12402 | if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code)) | |
12403 | { | |
12404 | /* Though there are no non-pipelined ALU1 insns, | |
12405 | we can get an instruction of type 'multi' before reload. */ | |
12406 | gcc_assert (mips_ls2.cycle_has_multi_p); | |
12407 | mips_ls2.alu1_turn_p = false; | |
12408 | } | |
12409 | ||
12410 | mips_ls2.cycle_has_multi_p = false; | |
12411 | ||
12412 | if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code)) | |
12413 | /* We have a non-pipelined alu instruction in the core, | |
12414 | adjust round-robin counter. */ | |
12415 | mips_ls2.alu1_turn_p = true; | |
12416 | ||
12417 | if (mips_ls2.alu1_turn_p) | |
12418 | { | |
12419 | if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0) | |
12420 | gcc_unreachable (); | |
12421 | } | |
12422 | else | |
12423 | { | |
12424 | if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0) | |
12425 | gcc_unreachable (); | |
12426 | } | |
12427 | ||
12428 | if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code)) | |
12429 | { | |
12430 | /* There are no non-pipelined FALU1 insns. */ | |
12431 | gcc_unreachable (); | |
12432 | mips_ls2.falu1_turn_p = false; | |
12433 | } | |
12434 | ||
12435 | if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code)) | |
12436 | /* We have a non-pipelined falu instruction in the core, | |
12437 | adjust round-robin counter. */ | |
12438 | mips_ls2.falu1_turn_p = true; | |
12439 | ||
12440 | if (mips_ls2.falu1_turn_p) | |
12441 | { | |
12442 | if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0) | |
12443 | gcc_unreachable (); | |
12444 | } | |
12445 | else | |
12446 | { | |
12447 | if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0) | |
12448 | gcc_unreachable (); | |
12449 | } | |
12450 | } | |
12451 | ||
12452 | /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE. | |
12453 | This hook is being called at the start of each cycle. */ | |
12454 | ||
12455 | static void | |
12456 | mips_dfa_post_advance_cycle (void) | |
12457 | { | |
12458 | if (TUNE_LOONGSON_2EF) | |
12459 | mips_ls2_dfa_post_advance_cycle (curr_state); | |
12460 | } | |
12461 | ||
65239d20 | 12462 | /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should |
ab77a036 | 12463 | be as wide as the scheduling freedom in the DFA. */ |
2bcb2ab3 | 12464 | |
ab77a036 RS |
12465 | static int |
12466 | mips_multipass_dfa_lookahead (void) | |
12467 | { | |
12468 | /* Can schedule up to 4 of the 6 function units in any one cycle. */ | |
12469 | if (TUNE_SB1) | |
12470 | return 4; | |
2bcb2ab3 | 12471 | |
2b18eb32 | 12472 | if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) |
58684fa0 MK |
12473 | return 4; |
12474 | ||
ce00be9e AN |
12475 | if (TUNE_OCTEON) |
12476 | return 2; | |
12477 | ||
ab77a036 RS |
12478 | return 0; |
12479 | } | |
12480 | \f | |
12481 | /* Remove the instruction at index LOWER from ready queue READY and | |
12482 | reinsert it in front of the instruction at index HIGHER. LOWER must | |
12483 | be <= HIGHER. */ | |
2bcb2ab3 | 12484 | |
ab77a036 RS |
12485 | static void |
12486 | mips_promote_ready (rtx *ready, int lower, int higher) | |
2bcb2ab3 | 12487 | { |
ab77a036 RS |
12488 | rtx new_head; |
12489 | int i; | |
2bcb2ab3 | 12490 | |
ab77a036 RS |
12491 | new_head = ready[lower]; |
12492 | for (i = lower; i < higher; i++) | |
12493 | ready[i] = ready[i + 1]; | |
12494 | ready[i] = new_head; | |
12495 | } | |
2bcb2ab3 | 12496 | |
ab77a036 RS |
12497 | /* If the priority of the instruction at POS2 in the ready queue READY |
12498 | is within LIMIT units of that of the instruction at POS1, swap the | |
12499 | instructions if POS2 is not already less than POS1. */ | |
2bcb2ab3 | 12500 | |
ab77a036 RS |
12501 | static void |
12502 | mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit) | |
12503 | { | |
12504 | if (pos1 < pos2 | |
12505 | && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2])) | |
12506 | { | |
12507 | rtx temp; | |
65239d20 | 12508 | |
ab77a036 RS |
12509 | temp = ready[pos1]; |
12510 | ready[pos1] = ready[pos2]; | |
12511 | ready[pos2] = temp; | |
12512 | } | |
12513 | } | |
12514 | \f | |
12515 | /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction | |
12516 | that may clobber hi or lo. */ | |
ab77a036 | 12517 | static rtx mips_macc_chains_last_hilo; |
2bcb2ab3 | 12518 | |
ab77a036 RS |
12519 | /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has |
12520 | been scheduled, updating mips_macc_chains_last_hilo appropriately. */ | |
2bcb2ab3 | 12521 | |
ab77a036 RS |
12522 | static void |
12523 | mips_macc_chains_record (rtx insn) | |
12524 | { | |
12525 | if (get_attr_may_clobber_hilo (insn)) | |
12526 | mips_macc_chains_last_hilo = insn; | |
12527 | } | |
2bcb2ab3 | 12528 | |
ab77a036 RS |
12529 | /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which |
12530 | has NREADY elements, looking for a multiply-add or multiply-subtract | |
12531 | instruction that is cumulative with mips_macc_chains_last_hilo. | |
12532 | If there is one, promote it ahead of anything else that might | |
12533 | clobber hi or lo. */ | |
2bcb2ab3 | 12534 | |
ab77a036 RS |
12535 | static void |
12536 | mips_macc_chains_reorder (rtx *ready, int nready) | |
12537 | { | |
12538 | int i, j; | |
2bcb2ab3 | 12539 | |
ab77a036 RS |
12540 | if (mips_macc_chains_last_hilo != 0) |
12541 | for (i = nready - 1; i >= 0; i--) | |
12542 | if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i])) | |
12543 | { | |
12544 | for (j = nready - 1; j > i; j--) | |
12545 | if (recog_memoized (ready[j]) >= 0 | |
12546 | && get_attr_may_clobber_hilo (ready[j])) | |
12547 | { | |
12548 | mips_promote_ready (ready, i, j); | |
12549 | break; | |
12550 | } | |
12551 | break; | |
12552 | } | |
12553 | } | |
12554 | \f | |
12555 | /* The last instruction to be scheduled. */ | |
ab77a036 | 12556 | static rtx vr4130_last_insn; |
2bcb2ab3 | 12557 | |
ab77a036 RS |
12558 | /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA |
12559 | points to an rtx that is initially an instruction. Nullify the rtx | |
12560 | if the instruction uses the value of register X. */ | |
2bcb2ab3 | 12561 | |
ab77a036 | 12562 | static void |
65239d20 RS |
12563 | vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, |
12564 | void *data) | |
ab77a036 | 12565 | { |
65239d20 RS |
12566 | rtx *insn_ptr; |
12567 | ||
12568 | insn_ptr = (rtx *) data; | |
ab77a036 RS |
12569 | if (REG_P (x) |
12570 | && *insn_ptr != 0 | |
12571 | && reg_referenced_p (x, PATTERN (*insn_ptr))) | |
12572 | *insn_ptr = 0; | |
12573 | } | |
2bcb2ab3 | 12574 | |
ab77a036 RS |
12575 | /* Return true if there is true register dependence between vr4130_last_insn |
12576 | and INSN. */ | |
2bcb2ab3 | 12577 | |
ab77a036 RS |
12578 | static bool |
12579 | vr4130_true_reg_dependence_p (rtx insn) | |
12580 | { | |
12581 | note_stores (PATTERN (vr4130_last_insn), | |
12582 | vr4130_true_reg_dependence_p_1, &insn); | |
12583 | return insn == 0; | |
12584 | } | |
2bcb2ab3 | 12585 | |
ab77a036 RS |
12586 | /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of |
12587 | the ready queue and that INSN2 is the instruction after it, return | |
12588 | true if it is worth promoting INSN2 ahead of INSN1. Look for cases | |
12589 | in which INSN1 and INSN2 can probably issue in parallel, but for | |
12590 | which (INSN2, INSN1) should be less sensitive to instruction | |
12591 | alignment than (INSN1, INSN2). See 4130.md for more details. */ | |
2bcb2ab3 | 12592 | |
ab77a036 RS |
12593 | static bool |
12594 | vr4130_swap_insns_p (rtx insn1, rtx insn2) | |
12595 | { | |
12596 | sd_iterator_def sd_it; | |
12597 | dep_t dep; | |
2bcb2ab3 | 12598 | |
ab77a036 | 12599 | /* Check for the following case: |
2bcb2ab3 | 12600 | |
ab77a036 RS |
12601 | 1) there is some other instruction X with an anti dependence on INSN1; |
12602 | 2) X has a higher priority than INSN2; and | |
12603 | 3) X is an arithmetic instruction (and thus has no unit restrictions). | |
2bcb2ab3 | 12604 | |
ab77a036 RS |
12605 | If INSN1 is the last instruction blocking X, it would better to |
12606 | choose (INSN1, X) over (INSN2, INSN1). */ | |
12607 | FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep) | |
12608 | if (DEP_TYPE (dep) == REG_DEP_ANTI | |
12609 | && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2) | |
12610 | && recog_memoized (DEP_CON (dep)) >= 0 | |
12611 | && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU) | |
12612 | return false; | |
2bcb2ab3 | 12613 | |
ab77a036 RS |
12614 | if (vr4130_last_insn != 0 |
12615 | && recog_memoized (insn1) >= 0 | |
12616 | && recog_memoized (insn2) >= 0) | |
12617 | { | |
12618 | /* See whether INSN1 and INSN2 use different execution units, | |
12619 | or if they are both ALU-type instructions. If so, they can | |
12620 | probably execute in parallel. */ | |
12621 | enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1); | |
12622 | enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2); | |
12623 | if (class1 != class2 || class1 == VR4130_CLASS_ALU) | |
2bcb2ab3 | 12624 | { |
ab77a036 RS |
12625 | /* If only one of the instructions has a dependence on |
12626 | vr4130_last_insn, prefer to schedule the other one first. */ | |
65239d20 RS |
12627 | bool dep1_p = vr4130_true_reg_dependence_p (insn1); |
12628 | bool dep2_p = vr4130_true_reg_dependence_p (insn2); | |
12629 | if (dep1_p != dep2_p) | |
12630 | return dep1_p; | |
2bcb2ab3 | 12631 | |
ab77a036 RS |
12632 | /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn |
12633 | is not an ALU-type instruction and if INSN1 uses the same | |
12634 | execution unit. (Note that if this condition holds, we already | |
12635 | know that INSN2 uses a different execution unit.) */ | |
12636 | if (class1 != VR4130_CLASS_ALU | |
12637 | && recog_memoized (vr4130_last_insn) >= 0 | |
12638 | && class1 == get_attr_vr4130_class (vr4130_last_insn)) | |
12639 | return true; | |
12640 | } | |
12641 | } | |
12642 | return false; | |
12643 | } | |
2bcb2ab3 | 12644 | |
ab77a036 RS |
12645 | /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready |
12646 | queue with at least two instructions. Swap the first two if | |
12647 | vr4130_swap_insns_p says that it could be worthwhile. */ | |
2bcb2ab3 | 12648 | |
ab77a036 RS |
12649 | static void |
12650 | vr4130_reorder (rtx *ready, int nready) | |
12651 | { | |
12652 | if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2])) | |
12653 | mips_promote_ready (ready, nready - 2, nready - 1); | |
12654 | } | |
12655 | \f | |
12656 | /* Record whether last 74k AGEN instruction was a load or store. */ | |
ab77a036 | 12657 | static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN; |
2bcb2ab3 | 12658 | |
ab77a036 RS |
12659 | /* Initialize mips_last_74k_agen_insn from INSN. A null argument |
12660 | resets to TYPE_UNKNOWN state. */ | |
2bcb2ab3 | 12661 | |
ab77a036 RS |
12662 | static void |
12663 | mips_74k_agen_init (rtx insn) | |
12664 | { | |
006b29ab | 12665 | if (!insn || CALL_P (insn) || JUMP_P (insn)) |
ab77a036 | 12666 | mips_last_74k_agen_insn = TYPE_UNKNOWN; |
65239d20 | 12667 | else |
ab77a036 RS |
12668 | { |
12669 | enum attr_type type = get_attr_type (insn); | |
12670 | if (type == TYPE_LOAD || type == TYPE_STORE) | |
12671 | mips_last_74k_agen_insn = type; | |
12672 | } | |
12673 | } | |
2bcb2ab3 | 12674 | |
ab77a036 RS |
12675 | /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple |
12676 | loads to be grouped together, and multiple stores to be grouped | |
12677 | together. Swap things around in the ready queue to make this happen. */ | |
30244df3 | 12678 | |
ab77a036 RS |
12679 | static void |
12680 | mips_74k_agen_reorder (rtx *ready, int nready) | |
12681 | { | |
12682 | int i; | |
12683 | int store_pos, load_pos; | |
30244df3 | 12684 | |
ab77a036 RS |
12685 | store_pos = -1; |
12686 | load_pos = -1; | |
2bcb2ab3 | 12687 | |
ab77a036 RS |
12688 | for (i = nready - 1; i >= 0; i--) |
12689 | { | |
12690 | rtx insn = ready[i]; | |
12691 | if (USEFUL_INSN_P (insn)) | |
12692 | switch (get_attr_type (insn)) | |
12693 | { | |
12694 | case TYPE_STORE: | |
12695 | if (store_pos == -1) | |
12696 | store_pos = i; | |
12697 | break; | |
2bcb2ab3 | 12698 | |
ab77a036 RS |
12699 | case TYPE_LOAD: |
12700 | if (load_pos == -1) | |
12701 | load_pos = i; | |
12702 | break; | |
2bcb2ab3 | 12703 | |
ab77a036 RS |
12704 | default: |
12705 | break; | |
12706 | } | |
12707 | } | |
2bcb2ab3 | 12708 | |
ab77a036 RS |
12709 | if (load_pos == -1 || store_pos == -1) |
12710 | return; | |
2bcb2ab3 | 12711 | |
ab77a036 | 12712 | switch (mips_last_74k_agen_insn) |
76cbf5bf | 12713 | { |
ab77a036 RS |
12714 | case TYPE_UNKNOWN: |
12715 | /* Prefer to schedule loads since they have a higher latency. */ | |
12716 | case TYPE_LOAD: | |
12717 | /* Swap loads to the front of the queue. */ | |
12718 | mips_maybe_swap_ready (ready, load_pos, store_pos, 4); | |
12719 | break; | |
12720 | case TYPE_STORE: | |
12721 | /* Swap stores to the front of the queue. */ | |
12722 | mips_maybe_swap_ready (ready, store_pos, load_pos, 4); | |
12723 | break; | |
12724 | default: | |
12725 | break; | |
76cbf5bf | 12726 | } |
ab77a036 RS |
12727 | } |
12728 | \f | |
12729 | /* Implement TARGET_SCHED_INIT. */ | |
76cbf5bf | 12730 | |
ab77a036 RS |
12731 | static void |
12732 | mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12733 | int max_ready ATTRIBUTE_UNUSED) | |
12734 | { | |
12735 | mips_macc_chains_last_hilo = 0; | |
12736 | vr4130_last_insn = 0; | |
12737 | mips_74k_agen_init (NULL_RTX); | |
58684fa0 MK |
12738 | |
12739 | /* When scheduling for Loongson2, branch instructions go to ALU1, | |
12740 | therefore basic block is most likely to start with round-robin counter | |
12741 | pointed to ALU2. */ | |
12742 | mips_ls2.alu1_turn_p = false; | |
12743 | mips_ls2.falu1_turn_p = true; | |
2bcb2ab3 GK |
12744 | } |
12745 | ||
646e6f41 | 12746 | /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */ |
76cbf5bf | 12747 | |
646e6f41 JZ |
12748 | static void |
12749 | mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12750 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
76cbf5bf | 12751 | { |
ab77a036 RS |
12752 | if (!reload_completed |
12753 | && TUNE_MACC_CHAINS | |
12754 | && *nreadyp > 0) | |
12755 | mips_macc_chains_reorder (ready, *nreadyp); | |
65239d20 | 12756 | |
ab77a036 RS |
12757 | if (reload_completed |
12758 | && TUNE_MIPS4130 | |
12759 | && !TARGET_VR4130_ALIGN | |
12760 | && *nreadyp > 1) | |
12761 | vr4130_reorder (ready, *nreadyp); | |
65239d20 | 12762 | |
ab77a036 RS |
12763 | if (TUNE_74K) |
12764 | mips_74k_agen_reorder (ready, *nreadyp); | |
646e6f41 | 12765 | } |
65239d20 | 12766 | |
646e6f41 JZ |
12767 | /* Implement TARGET_SCHED_REORDER. */ |
12768 | ||
12769 | static int | |
12770 | mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12771 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
12772 | { | |
12773 | mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); | |
ab77a036 RS |
12774 | return mips_issue_rate (); |
12775 | } | |
76cbf5bf | 12776 | |
646e6f41 JZ |
12777 | /* Implement TARGET_SCHED_REORDER2. */ |
12778 | ||
12779 | static int | |
12780 | mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12781 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
12782 | { | |
12783 | mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); | |
12784 | return cached_can_issue_more; | |
12785 | } | |
12786 | ||
58684fa0 MK |
12787 | /* Update round-robin counters for ALU1/2 and FALU1/2. */ |
12788 | ||
12789 | static void | |
12790 | mips_ls2_variable_issue (rtx insn) | |
12791 | { | |
12792 | if (mips_ls2.alu1_turn_p) | |
12793 | { | |
12794 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code)) | |
12795 | mips_ls2.alu1_turn_p = false; | |
12796 | } | |
12797 | else | |
12798 | { | |
12799 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code)) | |
12800 | mips_ls2.alu1_turn_p = true; | |
12801 | } | |
12802 | ||
12803 | if (mips_ls2.falu1_turn_p) | |
12804 | { | |
12805 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code)) | |
12806 | mips_ls2.falu1_turn_p = false; | |
12807 | } | |
12808 | else | |
12809 | { | |
12810 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code)) | |
12811 | mips_ls2.falu1_turn_p = true; | |
12812 | } | |
12813 | ||
12814 | if (recog_memoized (insn) >= 0) | |
12815 | mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI); | |
12816 | } | |
12817 | ||
ab77a036 | 12818 | /* Implement TARGET_SCHED_VARIABLE_ISSUE. */ |
76cbf5bf | 12819 | |
ab77a036 RS |
12820 | static int |
12821 | mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12822 | rtx insn, int more) | |
12823 | { | |
65239d20 RS |
12824 | /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */ |
12825 | if (USEFUL_INSN_P (insn)) | |
f2531eb6 | 12826 | { |
0c433c31 RS |
12827 | if (get_attr_type (insn) != TYPE_GHOST) |
12828 | more--; | |
ab77a036 RS |
12829 | if (!reload_completed && TUNE_MACC_CHAINS) |
12830 | mips_macc_chains_record (insn); | |
12831 | vr4130_last_insn = insn; | |
65239d20 RS |
12832 | if (TUNE_74K) |
12833 | mips_74k_agen_init (insn); | |
58684fa0 MK |
12834 | else if (TUNE_LOONGSON_2EF) |
12835 | mips_ls2_variable_issue (insn); | |
76cbf5bf | 12836 | } |
58684fa0 MK |
12837 | |
12838 | /* Instructions of type 'multi' should all be split before | |
12839 | the second scheduling pass. */ | |
12840 | gcc_assert (!reload_completed | |
12841 | || recog_memoized (insn) < 0 | |
12842 | || get_attr_type (insn) != TYPE_MULTI); | |
12843 | ||
646e6f41 | 12844 | cached_can_issue_more = more; |
ab77a036 | 12845 | return more; |
76cbf5bf | 12846 | } |
ab77a036 RS |
12847 | \f |
12848 | /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY), | |
65239d20 | 12849 | return the first operand of the associated PREF or PREFX insn. */ |
76cbf5bf | 12850 | |
ab77a036 RS |
12851 | rtx |
12852 | mips_prefetch_cookie (rtx write, rtx locality) | |
12853 | { | |
12854 | /* store_streamed / load_streamed. */ | |
12855 | if (INTVAL (locality) <= 0) | |
12856 | return GEN_INT (INTVAL (write) + 4); | |
76cbf5bf | 12857 | |
ab77a036 RS |
12858 | /* store / load. */ |
12859 | if (INTVAL (locality) <= 2) | |
12860 | return write; | |
2bcb2ab3 | 12861 | |
ab77a036 RS |
12862 | /* store_retained / load_retained. */ |
12863 | return GEN_INT (INTVAL (write) + 6); | |
12864 | } | |
12865 | \f | |
fd0eb897 RS |
12866 | /* Flags that indicate when a built-in function is available. |
12867 | ||
12868 | BUILTIN_AVAIL_NON_MIPS16 | |
12869 | The function is available on the current target, but only | |
12870 | in non-MIPS16 mode. */ | |
12871 | #define BUILTIN_AVAIL_NON_MIPS16 1 | |
12872 | ||
12873 | /* Declare an availability predicate for built-in functions that | |
12874 | require non-MIPS16 mode and also require COND to be true. | |
12875 | NAME is the main part of the predicate's name. */ | |
12876 | #define AVAIL_NON_MIPS16(NAME, COND) \ | |
12877 | static unsigned int \ | |
12878 | mips_builtin_avail_##NAME (void) \ | |
12879 | { \ | |
12880 | return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ | |
12881 | } | |
12882 | ||
65239d20 RS |
12883 | /* This structure describes a single built-in function. */ |
12884 | struct mips_builtin_description { | |
ab77a036 RS |
12885 | /* The code of the main .md file instruction. See mips_builtin_type |
12886 | for more information. */ | |
12887 | enum insn_code icode; | |
2bcb2ab3 | 12888 | |
ab77a036 RS |
12889 | /* The floating-point comparison code to use with ICODE, if any. */ |
12890 | enum mips_fp_condition cond; | |
2bcb2ab3 | 12891 | |
65239d20 | 12892 | /* The name of the built-in function. */ |
ab77a036 | 12893 | const char *name; |
2bcb2ab3 | 12894 | |
ab77a036 RS |
12895 | /* Specifies how the function should be expanded. */ |
12896 | enum mips_builtin_type builtin_type; | |
2bcb2ab3 | 12897 | |
ab77a036 RS |
12898 | /* The function's prototype. */ |
12899 | enum mips_function_type function_type; | |
2bcb2ab3 | 12900 | |
fd0eb897 RS |
12901 | /* Whether the function is available. */ |
12902 | unsigned int (*avail) (void); | |
ab77a036 | 12903 | }; |
76cbf5bf | 12904 | |
fd0eb897 RS |
12905 | AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT) |
12906 | AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT) | |
12907 | AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D) | |
12908 | AVAIL_NON_MIPS16 (dsp, TARGET_DSP) | |
12909 | AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) | |
12910 | AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) | |
770da00a | 12911 | AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) |
fd0eb897 | 12912 | AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) |
93581857 | 12913 | AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) |
4d210b07 | 12914 | AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) |
fd0eb897 RS |
12915 | |
12916 | /* Construct a mips_builtin_description from the given arguments. | |
12917 | ||
12918 | INSN is the name of the associated instruction pattern, without the | |
12919 | leading CODE_FOR_mips_. | |
12920 | ||
12921 | CODE is the floating-point condition code associated with the | |
12922 | function. It can be 'f' if the field is not applicable. | |
12923 | ||
12924 | NAME is the name of the function itself, without the leading | |
12925 | "__builtin_mips_". | |
12926 | ||
12927 | BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. | |
12928 | ||
12929 | AVAIL is the name of the availability predicate, without the leading | |
12930 | mips_builtin_avail_. */ | |
12931 | #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \ | |
12932 | FUNCTION_TYPE, AVAIL) \ | |
12933 | { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \ | |
12934 | "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \ | |
12935 | mips_builtin_avail_ ## AVAIL } | |
12936 | ||
12937 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function | |
12938 | mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL | |
12939 | are as for MIPS_BUILTIN. */ | |
12940 | #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
12941 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) | |
206c2d7a | 12942 | |
65239d20 | 12943 | /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which |
fd0eb897 RS |
12944 | are subject to mips_builtin_avail_<AVAIL>. */ |
12945 | #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \ | |
12946 | MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \ | |
12947 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \ | |
12948 | MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \ | |
12949 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL) | |
206c2d7a | 12950 | |
ab77a036 | 12951 | /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. |
fd0eb897 RS |
12952 | The lower and upper forms are subject to mips_builtin_avail_<AVAIL> |
12953 | while the any and all forms are subject to mips_builtin_avail_mips3d. */ | |
12954 | #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \ | |
12955 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \ | |
12956 | MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12957 | mips3d), \ | |
12958 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \ | |
12959 | MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12960 | mips3d), \ | |
12961 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \ | |
12962 | MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12963 | AVAIL), \ | |
12964 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \ | |
12965 | MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12966 | AVAIL) | |
206c2d7a | 12967 | |
ab77a036 | 12968 | /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions |
fd0eb897 | 12969 | are subject to mips_builtin_avail_mips3d. */ |
ab77a036 | 12970 | #define CMP_4S_BUILTINS(INSN, COND) \ |
fd0eb897 RS |
12971 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \ |
12972 | MIPS_BUILTIN_CMP_ANY, \ | |
12973 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \ | |
12974 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \ | |
12975 | MIPS_BUILTIN_CMP_ALL, \ | |
12976 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d) | |
206c2d7a | 12977 | |
ab77a036 | 12978 | /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison |
fd0eb897 RS |
12979 | instruction requires mips_builtin_avail_<AVAIL>. */ |
12980 | #define MOVTF_BUILTINS(INSN, COND, AVAIL) \ | |
12981 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \ | |
12982 | MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
12983 | AVAIL), \ | |
12984 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \ | |
12985 | MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
12986 | AVAIL) | |
2bcb2ab3 | 12987 | |
65239d20 | 12988 | /* Define all the built-in functions related to C.cond.fmt condition COND. */ |
ab77a036 | 12989 | #define CMP_BUILTINS(COND) \ |
fd0eb897 RS |
12990 | MOVTF_BUILTINS (c, COND, paired_single), \ |
12991 | MOVTF_BUILTINS (cabs, COND, mips3d), \ | |
12992 | CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \ | |
12993 | CMP_PS_BUILTINS (c, COND, paired_single), \ | |
12994 | CMP_PS_BUILTINS (cabs, COND, mips3d), \ | |
ab77a036 RS |
12995 | CMP_4S_BUILTINS (c, COND), \ |
12996 | CMP_4S_BUILTINS (cabs, COND) | |
18dbd950 | 12997 | |
fd0eb897 RS |
12998 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET |
12999 | function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE | |
13000 | and AVAIL are as for MIPS_BUILTIN. */ | |
13001 | #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
13002 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ | |
13003 | FUNCTION_TYPE, AVAIL) | |
2bcb2ab3 | 13004 | |
fd0eb897 RS |
13005 | /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP |
13006 | branch instruction. AVAIL is as for MIPS_BUILTIN. */ | |
13007 | #define BPOSGE_BUILTIN(VALUE, AVAIL) \ | |
13008 | MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ | |
13009 | MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) | |
dc884a86 | 13010 | |
93581857 MS |
13011 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> |
13012 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
13013 | builtin_description field. */ | |
13014 | #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \ | |
81f40b79 ILT |
13015 | { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \ |
13016 | "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \ | |
13017 | FUNCTION_TYPE, mips_builtin_avail_loongson } | |
93581857 MS |
13018 | |
13019 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN> | |
13020 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
13021 | builtin_description field. */ | |
13022 | #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \ | |
13023 | LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE) | |
13024 | ||
13025 | /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name. | |
13026 | We use functions of this form when the same insn can be usefully applied | |
13027 | to more than one datatype. */ | |
13028 | #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \ | |
13029 | LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE) | |
13030 | ||
ab77a036 | 13031 | #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 |
ab77a036 RS |
13032 | #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 |
13033 | #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 | |
13034 | #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 | |
13035 | #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3 | |
13036 | #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3 | |
293b77b0 CF |
13037 | #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit |
13038 | #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit | |
dc884a86 | 13039 | |
93581857 MS |
13040 | #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si |
13041 | #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi | |
13042 | #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi | |
13043 | #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3 | |
13044 | #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3 | |
13045 | #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3 | |
13046 | #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3 | |
13047 | #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3 | |
13048 | #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3 | |
13049 | #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3 | |
13050 | #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3 | |
13051 | #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3 | |
13052 | #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3 | |
13053 | #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3 | |
13054 | #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart | |
13055 | #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart | |
a44ecea1 | 13056 | #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3 |
59bdeecb MX |
13057 | #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3 |
13058 | #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3 | |
13059 | #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3 | |
13060 | #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3 | |
13061 | #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3 | |
13062 | #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3 | |
93581857 MS |
13063 | #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3 |
13064 | #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3 | |
13065 | #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3 | |
13066 | #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3 | |
13067 | #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3 | |
13068 | #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3 | |
13069 | #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3 | |
93581857 | 13070 | |
fd0eb897 RS |
13071 | static const struct mips_builtin_description mips_builtins[] = { |
13072 | DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13073 | DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13074 | DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13075 | DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13076 | DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single), | |
13077 | DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single), | |
13078 | DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single), | |
13079 | DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single), | |
13080 | ||
13081 | DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single), | |
13082 | DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13083 | DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13084 | DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13085 | DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13086 | ||
13087 | DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d), | |
13088 | DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d), | |
13089 | DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13090 | DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
13091 | DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
13092 | DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13093 | ||
13094 | DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d), | |
13095 | DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d), | |
13096 | DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13097 | DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
13098 | DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
13099 | DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13100 | ||
13101 | MIPS_FP_CONDITIONS (CMP_BUILTINS), | |
13102 | ||
13103 | /* Built-in functions for the SB-1 processor. */ | |
13104 | DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single), | |
13105 | ||
13106 | /* Built-in functions for the DSP ASE (32-bit and 64-bit). */ | |
13107 | DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13108 | DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13109 | DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
13110 | DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13111 | DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13112 | DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13113 | DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13114 | DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
13115 | DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13116 | DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13117 | DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp), | |
13118 | DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp), | |
13119 | DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp), | |
13120 | DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp), | |
13121 | DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp), | |
13122 | DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp), | |
13123 | DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
13124 | DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
13125 | DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
13126 | DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
13127 | DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp), | |
13128 | DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp), | |
13129 | DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13130 | DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13131 | DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13132 | DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13133 | DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13134 | DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13135 | DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13136 | DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13137 | DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
13138 | DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
13139 | DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
13140 | DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
13141 | DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
13142 | DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
13143 | DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
13144 | DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
13145 | DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
13146 | DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
13147 | DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13148 | DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
13149 | DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
13150 | DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp), | |
13151 | DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp), | |
13152 | DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp), | |
13153 | DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp), | |
13154 | DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
13155 | DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
13156 | DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
13157 | DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
13158 | DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
13159 | DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
13160 | DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
13161 | DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
13162 | DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
13163 | DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13164 | DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13165 | DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13166 | DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp), | |
13167 | DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp), | |
13168 | DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
13169 | DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
13170 | DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
13171 | BPOSGE_BUILTIN (32, dsp), | |
13172 | ||
13173 | /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */ | |
13174 | DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2), | |
13175 | DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13176 | DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13177 | DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
13178 | DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
13179 | DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
13180 | DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
13181 | DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
13182 | DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
13183 | DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
13184 | DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13185 | DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13186 | DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
13187 | DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13188 | DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
13189 | DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2), | |
13190 | DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
13191 | DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
13192 | DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
13193 | DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
13194 | DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
13195 | DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2), | |
13196 | DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13197 | DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13198 | DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
13199 | DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
13200 | DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13201 | DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13202 | DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
13203 | DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
13204 | DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13205 | DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
13206 | DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
13207 | DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
13208 | ||
13209 | /* Built-in functions for the DSP ASE (32-bit only). */ | |
13210 | DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
13211 | DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
13212 | DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
13213 | DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
13214 | DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13215 | DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13216 | DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13217 | DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
13218 | DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
13219 | DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13220 | DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13221 | DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13222 | DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
13223 | DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
13224 | DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
13225 | DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
13226 | DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
13227 | DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
13228 | DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
13229 | DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
13230 | DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
293b77b0 CF |
13231 | DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), |
13232 | DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), | |
13233 | DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
13234 | DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), | |
13235 | DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32), | |
13236 | DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32), | |
fd0eb897 | 13237 | |
770da00a AP |
13238 | /* Built-in functions for the DSP ASE (64-bit only). */ |
13239 | DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64), | |
13240 | ||
fd0eb897 RS |
13241 | /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */ |
13242 | DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
13243 | DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
fd0eb897 | 13244 | DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
fd0eb897 RS |
13245 | DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
13246 | DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
13247 | DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
13248 | DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
13249 | DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
93581857 MS |
13250 | DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
13251 | ||
13252 | /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ | |
13253 | LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), | |
13254 | LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), | |
13255 | LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI), | |
13256 | LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13257 | LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13258 | LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13259 | LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
13260 | LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13261 | LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13262 | LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
13263 | LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI), | |
13264 | LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13265 | LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13266 | LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13267 | LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13268 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI), | |
13269 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13270 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13271 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13272 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI), | |
13273 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
13274 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13275 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13276 | LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13277 | LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13278 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13279 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13280 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13281 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
13282 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13283 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13284 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13285 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13286 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13287 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
13288 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13289 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13290 | LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI), | |
13291 | LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI), | |
13292 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13293 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13294 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13295 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13296 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13297 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13298 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13299 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13300 | LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI), | |
13301 | LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13302 | LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13303 | LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13304 | LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13305 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI), | |
13306 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI), | |
13307 | LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13308 | LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13309 | LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13310 | LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI), | |
13311 | LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13312 | LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI), | |
13313 | LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI), | |
7dab511c RH |
13314 | LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), |
13315 | LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
93581857 MS |
13316 | LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), |
13317 | LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
13318 | LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
13319 | LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
13320 | LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
13321 | LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
13322 | LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
13323 | LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
13324 | LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
13325 | LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
13326 | LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
13327 | LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
13328 | LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13329 | LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13330 | LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13331 | LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
13332 | LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13333 | LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13334 | LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
13335 | LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI), | |
13336 | LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13337 | LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13338 | LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13339 | LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13340 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13341 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13342 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13343 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13344 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
13345 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
13346 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
13347 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
13348 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
13349 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
13350 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
4d210b07 RS |
13351 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), |
13352 | ||
13353 | /* Sundry other built-in functions. */ | |
13354 | DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache) | |
ab77a036 | 13355 | }; |
dc884a86 | 13356 | |
7725086e RS |
13357 | /* Index I is the function declaration for mips_builtins[I], or null if the |
13358 | function isn't defined on this target. */ | |
13359 | static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)]; | |
13360 | ||
41030557 RS |
13361 | /* MODE is a vector mode whose elements have type TYPE. Return the type |
13362 | of the vector itself. */ | |
dc884a86 | 13363 | |
41030557 RS |
13364 | static tree |
13365 | mips_builtin_vector_type (tree type, enum machine_mode mode) | |
dc884a86 | 13366 | { |
93581857 MS |
13367 | static tree types[2 * (int) MAX_MACHINE_MODE]; |
13368 | int mode_index; | |
dc884a86 | 13369 | |
93581857 MS |
13370 | mode_index = (int) mode; |
13371 | ||
13372 | if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type)) | |
13373 | mode_index += MAX_MACHINE_MODE; | |
13374 | ||
13375 | if (types[mode_index] == NULL_TREE) | |
13376 | types[mode_index] = build_vector_type_for_mode (type, mode); | |
13377 | return types[mode_index]; | |
41030557 | 13378 | } |
dc884a86 | 13379 | |
4d210b07 RS |
13380 | /* Return a type for 'const volatile void *'. */ |
13381 | ||
13382 | static tree | |
13383 | mips_build_cvpointer_type (void) | |
13384 | { | |
13385 | static tree cache; | |
13386 | ||
13387 | if (cache == NULL_TREE) | |
13388 | cache = build_pointer_type (build_qualified_type | |
13389 | (void_type_node, | |
13390 | TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)); | |
13391 | return cache; | |
13392 | } | |
13393 | ||
41030557 RS |
13394 | /* Source-level argument types. */ |
13395 | #define MIPS_ATYPE_VOID void_type_node | |
13396 | #define MIPS_ATYPE_INT integer_type_node | |
13397 | #define MIPS_ATYPE_POINTER ptr_type_node | |
4d210b07 | 13398 | #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type () |
dc884a86 | 13399 | |
41030557 | 13400 | /* Standard mode-based argument types. */ |
93581857 | 13401 | #define MIPS_ATYPE_UQI unsigned_intQI_type_node |
41030557 RS |
13402 | #define MIPS_ATYPE_SI intSI_type_node |
13403 | #define MIPS_ATYPE_USI unsigned_intSI_type_node | |
13404 | #define MIPS_ATYPE_DI intDI_type_node | |
93581857 | 13405 | #define MIPS_ATYPE_UDI unsigned_intDI_type_node |
41030557 RS |
13406 | #define MIPS_ATYPE_SF float_type_node |
13407 | #define MIPS_ATYPE_DF double_type_node | |
dc884a86 | 13408 | |
41030557 RS |
13409 | /* Vector argument types. */ |
13410 | #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode) | |
13411 | #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode) | |
93581857 | 13412 | #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode) |
41030557 | 13413 | #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode) |
93581857 MS |
13414 | #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode) |
13415 | #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode) | |
13416 | #define MIPS_ATYPE_UV2SI \ | |
13417 | mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode) | |
13418 | #define MIPS_ATYPE_UV4HI \ | |
13419 | mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode) | |
13420 | #define MIPS_ATYPE_UV8QI \ | |
13421 | mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode) | |
dc884a86 | 13422 | |
41030557 RS |
13423 | /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists |
13424 | their associated MIPS_ATYPEs. */ | |
13425 | #define MIPS_FTYPE_ATYPES1(A, B) \ | |
13426 | MIPS_ATYPE_##A, MIPS_ATYPE_##B | |
dc884a86 | 13427 | |
41030557 RS |
13428 | #define MIPS_FTYPE_ATYPES2(A, B, C) \ |
13429 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C | |
dc884a86 | 13430 | |
41030557 RS |
13431 | #define MIPS_FTYPE_ATYPES3(A, B, C, D) \ |
13432 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D | |
dc884a86 | 13433 | |
41030557 RS |
13434 | #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \ |
13435 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \ | |
13436 | MIPS_ATYPE_##E | |
dc884a86 | 13437 | |
41030557 | 13438 | /* Return the function type associated with function prototype TYPE. */ |
dc884a86 | 13439 | |
41030557 RS |
13440 | static tree |
13441 | mips_build_function_type (enum mips_function_type type) | |
13442 | { | |
13443 | static tree types[(int) MIPS_MAX_FTYPE_MAX]; | |
dc884a86 | 13444 | |
41030557 RS |
13445 | if (types[(int) type] == NULL_TREE) |
13446 | switch (type) | |
13447 | { | |
13448 | #define DEF_MIPS_FTYPE(NUM, ARGS) \ | |
13449 | case MIPS_FTYPE_NAME##NUM ARGS: \ | |
13450 | types[(int) type] \ | |
13451 | = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \ | |
13452 | NULL_TREE); \ | |
13453 | break; | |
13454 | #include "config/mips/mips-ftypes.def" | |
13455 | #undef DEF_MIPS_FTYPE | |
13456 | default: | |
13457 | gcc_unreachable (); | |
13458 | } | |
dc884a86 | 13459 | |
41030557 RS |
13460 | return types[(int) type]; |
13461 | } | |
6f2993e5 | 13462 | |
65239d20 | 13463 | /* Implement TARGET_INIT_BUILTINS. */ |
41030557 RS |
13464 | |
13465 | static void | |
13466 | mips_init_builtins (void) | |
13467 | { | |
65239d20 | 13468 | const struct mips_builtin_description *d; |
fd0eb897 | 13469 | unsigned int i; |
6f2993e5 | 13470 | |
ab77a036 RS |
13471 | /* Iterate through all of the bdesc arrays, initializing all of the |
13472 | builtin functions. */ | |
fd0eb897 | 13473 | for (i = 0; i < ARRAY_SIZE (mips_builtins); i++) |
ab77a036 | 13474 | { |
fd0eb897 RS |
13475 | d = &mips_builtins[i]; |
13476 | if (d->avail ()) | |
7725086e RS |
13477 | mips_builtin_decls[i] |
13478 | = add_builtin_function (d->name, | |
13479 | mips_build_function_type (d->function_type), | |
13480 | i, BUILT_IN_MD, NULL, NULL); | |
ab77a036 RS |
13481 | } |
13482 | } | |
6f2993e5 | 13483 | |
7725086e RS |
13484 | /* Implement TARGET_BUILTIN_DECL. */ |
13485 | ||
13486 | static tree | |
13487 | mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED) | |
13488 | { | |
13489 | if (code >= ARRAY_SIZE (mips_builtins)) | |
13490 | return error_mark_node; | |
13491 | return mips_builtin_decls[code]; | |
13492 | } | |
13493 | ||
b99ce2a8 RS |
13494 | /* Take argument ARGNO from EXP's argument list and convert it into |
13495 | an expand operand. Store the operand in *OP. */ | |
987a3c2b | 13496 | |
b99ce2a8 RS |
13497 | static void |
13498 | mips_prepare_builtin_arg (struct expand_operand *op, tree exp, | |
13499 | unsigned int argno) | |
ab77a036 | 13500 | { |
26b69f64 | 13501 | tree arg; |
ab77a036 | 13502 | rtx value; |
6f2993e5 | 13503 | |
26b69f64 RS |
13504 | arg = CALL_EXPR_ARG (exp, argno); |
13505 | value = expand_normal (arg); | |
b99ce2a8 RS |
13506 | create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg))); |
13507 | } | |
26b69f64 | 13508 | |
b99ce2a8 RS |
13509 | /* Expand instruction ICODE as part of a built-in function sequence. |
13510 | Use the first NOPS elements of OPS as the instruction's operands. | |
13511 | HAS_TARGET_P is true if operand 0 is a target; it is false if the | |
13512 | instruction has no target. | |
26b69f64 | 13513 | |
b99ce2a8 | 13514 | Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */ |
4d210b07 | 13515 | |
b99ce2a8 RS |
13516 | static rtx |
13517 | mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, | |
13518 | struct expand_operand *ops, bool has_target_p) | |
13519 | { | |
13520 | if (!maybe_expand_insn (icode, nops, ops)) | |
13521 | { | |
13522 | error ("invalid argument to built-in function"); | |
13523 | return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx; | |
ab77a036 | 13524 | } |
b99ce2a8 | 13525 | return has_target_p ? ops[0].value : const0_rtx; |
ab77a036 | 13526 | } |
0ac40e7a | 13527 | |
b99ce2a8 RS |
13528 | /* Expand a floating-point comparison for built-in function call EXP. |
13529 | The first NARGS arguments are the values to be compared. ICODE is | |
13530 | the .md pattern that does the comparison and COND is the condition | |
13531 | that is being tested. Return an rtx for the result. */ | |
0ac40e7a | 13532 | |
ab77a036 | 13533 | static rtx |
b99ce2a8 RS |
13534 | mips_expand_builtin_compare_1 (enum insn_code icode, |
13535 | enum mips_fp_condition cond, | |
13536 | tree exp, int nargs) | |
ab77a036 | 13537 | { |
b99ce2a8 RS |
13538 | struct expand_operand ops[MAX_RECOG_OPERANDS]; |
13539 | int opno, argno; | |
6f2993e5 | 13540 | |
b99ce2a8 RS |
13541 | /* The instruction should have a target operand, an operand for each |
13542 | argument, and an operand for COND. */ | |
f04713ee | 13543 | gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args); |
6f2993e5 | 13544 | |
b99ce2a8 RS |
13545 | opno = 0; |
13546 | create_output_operand (&ops[opno++], NULL_RTX, | |
13547 | insn_data[(int) icode].operand[0].mode); | |
13548 | for (argno = 0; argno < nargs; argno++) | |
13549 | mips_prepare_builtin_arg (&ops[opno++], exp, argno); | |
13550 | create_integer_operand (&ops[opno++], (int) cond); | |
13551 | return mips_expand_builtin_insn (icode, opno, ops, true); | |
6f2993e5 RS |
13552 | } |
13553 | ||
65239d20 RS |
13554 | /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function; |
13555 | HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function | |
13556 | and ICODE is the code of the associated .md pattern. TARGET, if nonnull, | |
13557 | suggests a good place to put the result. */ | |
6f2993e5 | 13558 | |
ab77a036 RS |
13559 | static rtx |
13560 | mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, | |
65239d20 | 13561 | bool has_target_p) |
6f2993e5 | 13562 | { |
b99ce2a8 | 13563 | struct expand_operand ops[MAX_RECOG_OPERANDS]; |
65239d20 | 13564 | int opno, argno; |
c15c90bb | 13565 | |
65239d20 RS |
13566 | /* Map any target to operand 0. */ |
13567 | opno = 0; | |
13568 | if (has_target_p) | |
b99ce2a8 | 13569 | create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp))); |
c235ddf2 | 13570 | |
f04713ee RS |
13571 | /* Map the arguments to the other operands. */ |
13572 | gcc_assert (opno + call_expr_nargs (exp) | |
13573 | == insn_data[icode].n_generator_args); | |
b99ce2a8 RS |
13574 | for (argno = 0; argno < call_expr_nargs (exp); argno++) |
13575 | mips_prepare_builtin_arg (&ops[opno++], exp, argno); | |
c15c90bb | 13576 | |
b99ce2a8 | 13577 | return mips_expand_builtin_insn (icode, opno, ops, has_target_p); |
c15c90bb | 13578 | } |
6f2993e5 | 13579 | |
65239d20 RS |
13580 | /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps |
13581 | function; TYPE says which. EXP is the CALL_EXPR that calls the | |
ab77a036 RS |
13582 | function, ICODE is the instruction that should be used to compare |
13583 | the first two arguments, and COND is the condition it should test. | |
13584 | TARGET, if nonnull, suggests a good place to put the result. */ | |
d604bca3 | 13585 | |
ab77a036 RS |
13586 | static rtx |
13587 | mips_expand_builtin_movtf (enum mips_builtin_type type, | |
13588 | enum insn_code icode, enum mips_fp_condition cond, | |
13589 | rtx target, tree exp) | |
13590 | { | |
b99ce2a8 RS |
13591 | struct expand_operand ops[4]; |
13592 | rtx cmp_result; | |
d604bca3 | 13593 | |
b99ce2a8 RS |
13594 | cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2); |
13595 | create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp))); | |
ab77a036 | 13596 | if (type == MIPS_BUILTIN_MOVT) |
d604bca3 | 13597 | { |
b99ce2a8 RS |
13598 | mips_prepare_builtin_arg (&ops[2], exp, 2); |
13599 | mips_prepare_builtin_arg (&ops[1], exp, 3); | |
c1bd2d66 | 13600 | } |
ab77a036 | 13601 | else |
d604bca3 | 13602 | { |
b99ce2a8 RS |
13603 | mips_prepare_builtin_arg (&ops[1], exp, 2); |
13604 | mips_prepare_builtin_arg (&ops[2], exp, 3); | |
c1bd2d66 | 13605 | } |
b99ce2a8 RS |
13606 | create_fixed_operand (&ops[3], cmp_result); |
13607 | return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps, | |
13608 | 4, ops, true); | |
d604bca3 MH |
13609 | } |
13610 | ||
ab77a036 RS |
13611 | /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE |
13612 | into TARGET otherwise. Return TARGET. */ | |
0ff83799 | 13613 | |
ab77a036 RS |
13614 | static rtx |
13615 | mips_builtin_branch_and_move (rtx condition, rtx target, | |
13616 | rtx value_if_true, rtx value_if_false) | |
0ff83799 | 13617 | { |
ab77a036 | 13618 | rtx true_label, done_label; |
0ff83799 | 13619 | |
ab77a036 RS |
13620 | true_label = gen_label_rtx (); |
13621 | done_label = gen_label_rtx (); | |
21c9500d | 13622 | |
ab77a036 RS |
13623 | /* First assume that CONDITION is false. */ |
13624 | mips_emit_move (target, value_if_false); | |
21c9500d | 13625 | |
ab77a036 RS |
13626 | /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */ |
13627 | emit_jump_insn (gen_condjump (condition, true_label)); | |
13628 | emit_jump_insn (gen_jump (done_label)); | |
13629 | emit_barrier (); | |
21c9500d | 13630 | |
ab77a036 RS |
13631 | /* Fix TARGET if CONDITION is true. */ |
13632 | emit_label (true_label); | |
13633 | mips_emit_move (target, value_if_true); | |
0ff83799 | 13634 | |
ab77a036 RS |
13635 | emit_label (done_label); |
13636 | return target; | |
0ff83799 MM |
13637 | } |
13638 | ||
65239d20 RS |
13639 | /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is |
13640 | the CALL_EXPR that calls the function, ICODE is the code of the | |
13641 | comparison instruction, and COND is the condition it should test. | |
13642 | TARGET, if nonnull, suggests a good place to put the boolean result. */ | |
c8520e56 | 13643 | |
ab77a036 RS |
13644 | static rtx |
13645 | mips_expand_builtin_compare (enum mips_builtin_type builtin_type, | |
13646 | enum insn_code icode, enum mips_fp_condition cond, | |
13647 | rtx target, tree exp) | |
c8520e56 | 13648 | { |
b99ce2a8 | 13649 | rtx offset, condition, cmp_result; |
c8520e56 | 13650 | |
ab77a036 RS |
13651 | if (target == 0 || GET_MODE (target) != SImode) |
13652 | target = gen_reg_rtx (SImode); | |
b99ce2a8 RS |
13653 | cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, |
13654 | call_expr_nargs (exp)); | |
0ff83799 | 13655 | |
ab77a036 RS |
13656 | /* If the comparison sets more than one register, we define the result |
13657 | to be 0 if all registers are false and -1 if all registers are true. | |
13658 | The value of the complete result is indeterminate otherwise. */ | |
13659 | switch (builtin_type) | |
a8c1d5f8 | 13660 | { |
ab77a036 RS |
13661 | case MIPS_BUILTIN_CMP_ALL: |
13662 | condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx); | |
13663 | return mips_builtin_branch_and_move (condition, target, | |
13664 | const0_rtx, const1_rtx); | |
13665 | ||
13666 | case MIPS_BUILTIN_CMP_UPPER: | |
13667 | case MIPS_BUILTIN_CMP_LOWER: | |
13668 | offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER); | |
13669 | condition = gen_single_cc (cmp_result, offset); | |
13670 | return mips_builtin_branch_and_move (condition, target, | |
13671 | const1_rtx, const0_rtx); | |
13672 | ||
13673 | default: | |
13674 | condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx); | |
13675 | return mips_builtin_branch_and_move (condition, target, | |
13676 | const1_rtx, const0_rtx); | |
a8c1d5f8 | 13677 | } |
ab77a036 | 13678 | } |
0ff83799 | 13679 | |
65239d20 RS |
13680 | /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET, |
13681 | if nonnull, suggests a good place to put the boolean result. */ | |
0ff83799 | 13682 | |
ab77a036 RS |
13683 | static rtx |
13684 | mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) | |
13685 | { | |
13686 | rtx condition, cmp_result; | |
13687 | int cmp_value; | |
0ff83799 | 13688 | |
ab77a036 RS |
13689 | if (target == 0 || GET_MODE (target) != SImode) |
13690 | target = gen_reg_rtx (SImode); | |
0ff83799 | 13691 | |
ab77a036 RS |
13692 | cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM); |
13693 | ||
13694 | if (builtin_type == MIPS_BUILTIN_BPOSGE32) | |
13695 | cmp_value = 32; | |
a8c1d5f8 | 13696 | else |
ab77a036 RS |
13697 | gcc_assert (0); |
13698 | ||
13699 | condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value)); | |
13700 | return mips_builtin_branch_and_move (condition, target, | |
13701 | const1_rtx, const0_rtx); | |
13702 | } | |
13703 | ||
65239d20 | 13704 | /* Implement TARGET_EXPAND_BUILTIN. */ |
ab77a036 RS |
13705 | |
13706 | static rtx | |
13707 | mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
0767b03f | 13708 | enum machine_mode mode, int ignore) |
ab77a036 | 13709 | { |
ab77a036 | 13710 | tree fndecl; |
fd0eb897 RS |
13711 | unsigned int fcode, avail; |
13712 | const struct mips_builtin_description *d; | |
ab77a036 RS |
13713 | |
13714 | fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
13715 | fcode = DECL_FUNCTION_CODE (fndecl); | |
fd0eb897 RS |
13716 | gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); |
13717 | d = &mips_builtins[fcode]; | |
13718 | avail = d->avail (); | |
13719 | gcc_assert (avail != 0); | |
ab77a036 | 13720 | if (TARGET_MIPS16) |
a8c1d5f8 | 13721 | { |
29d08eba JM |
13722 | error ("built-in function %qE not supported for MIPS16", |
13723 | DECL_NAME (fndecl)); | |
0767b03f | 13724 | return ignore ? const0_rtx : CONST0_RTX (mode); |
a8c1d5f8 | 13725 | } |
fd0eb897 | 13726 | switch (d->builtin_type) |
0ff83799 | 13727 | { |
fd0eb897 RS |
13728 | case MIPS_BUILTIN_DIRECT: |
13729 | return mips_expand_builtin_direct (d->icode, target, exp, true); | |
13730 | ||
13731 | case MIPS_BUILTIN_DIRECT_NO_TARGET: | |
13732 | return mips_expand_builtin_direct (d->icode, target, exp, false); | |
13733 | ||
13734 | case MIPS_BUILTIN_MOVT: | |
13735 | case MIPS_BUILTIN_MOVF: | |
13736 | return mips_expand_builtin_movtf (d->builtin_type, d->icode, | |
13737 | d->cond, target, exp); | |
13738 | ||
13739 | case MIPS_BUILTIN_CMP_ANY: | |
13740 | case MIPS_BUILTIN_CMP_ALL: | |
13741 | case MIPS_BUILTIN_CMP_UPPER: | |
13742 | case MIPS_BUILTIN_CMP_LOWER: | |
13743 | case MIPS_BUILTIN_CMP_SINGLE: | |
13744 | return mips_expand_builtin_compare (d->builtin_type, d->icode, | |
13745 | d->cond, target, exp); | |
13746 | ||
13747 | case MIPS_BUILTIN_BPOSGE32: | |
13748 | return mips_expand_builtin_bposge (d->builtin_type, target); | |
a8c1d5f8 | 13749 | } |
5f5fe6d9 | 13750 | gcc_unreachable (); |
0ff83799 | 13751 | } |
a27fb29b | 13752 | \f |
65239d20 | 13753 | /* An entry in the MIPS16 constant pool. VALUE is the pool constant, |
ab77a036 | 13754 | MODE is its mode, and LABEL is the CODE_LABEL associated with it. */ |
ab77a036 RS |
13755 | struct mips16_constant { |
13756 | struct mips16_constant *next; | |
13757 | rtx value; | |
13758 | rtx label; | |
13759 | enum machine_mode mode; | |
13760 | }; | |
6ba7b547 | 13761 | |
65239d20 | 13762 | /* Information about an incomplete MIPS16 constant pool. FIRST is the |
ab77a036 RS |
13763 | first constant, HIGHEST_ADDRESS is the highest address that the first |
13764 | byte of the pool can have, and INSN_ADDRESS is the current instruction | |
13765 | address. */ | |
ab77a036 RS |
13766 | struct mips16_constant_pool { |
13767 | struct mips16_constant *first; | |
13768 | int highest_address; | |
13769 | int insn_address; | |
13770 | }; | |
6ba7b547 | 13771 | |
ab77a036 RS |
13772 | /* Add constant VALUE to POOL and return its label. MODE is the |
13773 | value's mode (used for CONST_INTs, etc.). */ | |
6ba7b547 | 13774 | |
ab77a036 | 13775 | static rtx |
65239d20 RS |
13776 | mips16_add_constant (struct mips16_constant_pool *pool, |
13777 | rtx value, enum machine_mode mode) | |
ab77a036 RS |
13778 | { |
13779 | struct mips16_constant **p, *c; | |
13780 | bool first_of_size_p; | |
6ba7b547 | 13781 | |
ab77a036 RS |
13782 | /* See whether the constant is already in the pool. If so, return the |
13783 | existing label, otherwise leave P pointing to the place where the | |
13784 | constant should be added. | |
6ba7b547 | 13785 | |
ab77a036 RS |
13786 | Keep the pool sorted in increasing order of mode size so that we can |
13787 | reduce the number of alignments needed. */ | |
13788 | first_of_size_p = true; | |
13789 | for (p = &pool->first; *p != 0; p = &(*p)->next) | |
13790 | { | |
13791 | if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value)) | |
13792 | return (*p)->label; | |
13793 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode)) | |
13794 | break; | |
13795 | if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode)) | |
13796 | first_of_size_p = false; | |
13797 | } | |
6ba7b547 | 13798 | |
ab77a036 RS |
13799 | /* In the worst case, the constant needed by the earliest instruction |
13800 | will end up at the end of the pool. The entire pool must then be | |
13801 | accessible from that instruction. | |
6ba7b547 | 13802 | |
ab77a036 RS |
13803 | When adding the first constant, set the pool's highest address to |
13804 | the address of the first out-of-range byte. Adjust this address | |
13805 | downwards each time a new constant is added. */ | |
13806 | if (pool->first == 0) | |
65239d20 RS |
13807 | /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address |
13808 | of the instruction with the lowest two bits clear. The base PC | |
13809 | value for LDPC has the lowest three bits clear. Assume the worst | |
13810 | case here; namely that the PC-relative instruction occupies the | |
13811 | last 2 bytes in an aligned word. */ | |
ab77a036 RS |
13812 | pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000; |
13813 | pool->highest_address -= GET_MODE_SIZE (mode); | |
13814 | if (first_of_size_p) | |
13815 | /* Take into account the worst possible padding due to alignment. */ | |
13816 | pool->highest_address -= GET_MODE_SIZE (mode) - 1; | |
6ba7b547 | 13817 | |
ab77a036 | 13818 | /* Create a new entry. */ |
65239d20 | 13819 | c = XNEW (struct mips16_constant); |
ab77a036 RS |
13820 | c->value = value; |
13821 | c->mode = mode; | |
13822 | c->label = gen_label_rtx (); | |
13823 | c->next = *p; | |
13824 | *p = c; | |
6ba7b547 | 13825 | |
ab77a036 RS |
13826 | return c->label; |
13827 | } | |
6ba7b547 | 13828 | |
ab77a036 RS |
13829 | /* Output constant VALUE after instruction INSN and return the last |
13830 | instruction emitted. MODE is the mode of the constant. */ | |
6ba7b547 | 13831 | |
ab77a036 | 13832 | static rtx |
65239d20 | 13833 | mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn) |
ab77a036 | 13834 | { |
65239d20 | 13835 | if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode)) |
ab77a036 RS |
13836 | { |
13837 | rtx size = GEN_INT (GET_MODE_SIZE (mode)); | |
13838 | return emit_insn_after (gen_consttable_int (value, size), insn); | |
13839 | } | |
6ba7b547 | 13840 | |
ab77a036 RS |
13841 | if (SCALAR_FLOAT_MODE_P (mode)) |
13842 | return emit_insn_after (gen_consttable_float (value), insn); | |
6ba7b547 | 13843 | |
ab77a036 RS |
13844 | if (VECTOR_MODE_P (mode)) |
13845 | { | |
13846 | int i; | |
6ba7b547 | 13847 | |
ab77a036 | 13848 | for (i = 0; i < CONST_VECTOR_NUNITS (value); i++) |
65239d20 RS |
13849 | insn = mips16_emit_constants_1 (GET_MODE_INNER (mode), |
13850 | CONST_VECTOR_ELT (value, i), insn); | |
ab77a036 RS |
13851 | return insn; |
13852 | } | |
6ba7b547 | 13853 | |
ab77a036 RS |
13854 | gcc_unreachable (); |
13855 | } | |
6ba7b547 | 13856 | |
ab77a036 | 13857 | /* Dump out the constants in CONSTANTS after INSN. */ |
32ad6a47 | 13858 | |
ab77a036 | 13859 | static void |
65239d20 | 13860 | mips16_emit_constants (struct mips16_constant *constants, rtx insn) |
32ad6a47 | 13861 | { |
ab77a036 RS |
13862 | struct mips16_constant *c, *next; |
13863 | int align; | |
46490403 | 13864 | |
ab77a036 RS |
13865 | align = 0; |
13866 | for (c = constants; c != NULL; c = next) | |
32ad6a47 | 13867 | { |
ab77a036 RS |
13868 | /* If necessary, increase the alignment of PC. */ |
13869 | if (align < GET_MODE_SIZE (c->mode)) | |
c9e0ce37 | 13870 | { |
ab77a036 RS |
13871 | int align_log = floor_log2 (GET_MODE_SIZE (c->mode)); |
13872 | insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn); | |
c9e0ce37 | 13873 | } |
ab77a036 | 13874 | align = GET_MODE_SIZE (c->mode); |
a27fb29b | 13875 | |
ab77a036 | 13876 | insn = emit_label_after (c->label, insn); |
65239d20 | 13877 | insn = mips16_emit_constants_1 (c->mode, c->value, insn); |
d07d525a | 13878 | |
ab77a036 RS |
13879 | next = c->next; |
13880 | free (c); | |
13881 | } | |
7dac2f89 | 13882 | |
ab77a036 | 13883 | emit_barrier_after (insn); |
a27fb29b | 13884 | } |
7dac2f89 | 13885 | |
ab77a036 | 13886 | /* Return the length of instruction INSN. */ |
f41a6bf1 | 13887 | |
ab77a036 RS |
13888 | static int |
13889 | mips16_insn_length (rtx insn) | |
13890 | { | |
13891 | if (JUMP_P (insn)) | |
13892 | { | |
13893 | rtx body = PATTERN (insn); | |
13894 | if (GET_CODE (body) == ADDR_VEC) | |
13895 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0); | |
13896 | if (GET_CODE (body) == ADDR_DIFF_VEC) | |
13897 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1); | |
13898 | } | |
13899 | return get_attr_length (insn); | |
13900 | } | |
7dac2f89 | 13901 | |
ab77a036 RS |
13902 | /* If *X is a symbolic constant that refers to the constant pool, add |
13903 | the constant to POOL and rewrite *X to use the constant's label. */ | |
7dac2f89 | 13904 | |
ab77a036 RS |
13905 | static void |
13906 | mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x) | |
a27fb29b | 13907 | { |
ab77a036 | 13908 | rtx base, offset, label; |
7dac2f89 | 13909 | |
ab77a036 RS |
13910 | split_const (*x, &base, &offset); |
13911 | if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base)) | |
13912 | { | |
65239d20 RS |
13913 | label = mips16_add_constant (pool, get_pool_constant (base), |
13914 | get_pool_mode (base)); | |
ab77a036 RS |
13915 | base = gen_rtx_LABEL_REF (Pmode, label); |
13916 | *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE); | |
13917 | } | |
a27fb29b | 13918 | } |
7dac2f89 | 13919 | |
ab77a036 RS |
13920 | /* This structure is used to communicate with mips16_rewrite_pool_refs. |
13921 | INSN is the instruction we're rewriting and POOL points to the current | |
13922 | constant pool. */ | |
13923 | struct mips16_rewrite_pool_refs_info { | |
13924 | rtx insn; | |
13925 | struct mips16_constant_pool *pool; | |
13926 | }; | |
7dac2f89 | 13927 | |
ab77a036 RS |
13928 | /* Rewrite *X so that constant pool references refer to the constant's |
13929 | label instead. DATA points to a mips16_rewrite_pool_refs_info | |
13930 | structure. */ | |
a27fb29b | 13931 | |
ab77a036 RS |
13932 | static int |
13933 | mips16_rewrite_pool_refs (rtx *x, void *data) | |
a27fb29b | 13934 | { |
5ead67f6 KG |
13935 | struct mips16_rewrite_pool_refs_info *info = |
13936 | (struct mips16_rewrite_pool_refs_info *) data; | |
7dac2f89 | 13937 | |
ab77a036 RS |
13938 | if (force_to_mem_operand (*x, Pmode)) |
13939 | { | |
13940 | rtx mem = force_const_mem (GET_MODE (*x), *x); | |
13941 | validate_change (info->insn, x, mem, false); | |
13942 | } | |
a27fb29b | 13943 | |
ab77a036 RS |
13944 | if (MEM_P (*x)) |
13945 | { | |
13946 | mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0)); | |
13947 | return -1; | |
13948 | } | |
a27fb29b | 13949 | |
ddaf8125 RS |
13950 | /* Don't rewrite the __mips16_rdwr symbol. */ |
13951 | if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP) | |
13952 | return -1; | |
13953 | ||
ab77a036 RS |
13954 | if (TARGET_MIPS16_TEXT_LOADS) |
13955 | mips16_rewrite_pool_constant (info->pool, x); | |
a27fb29b | 13956 | |
ab77a036 | 13957 | return GET_CODE (*x) == CONST ? -1 : 0; |
7dac2f89 | 13958 | } |
7c262518 | 13959 | |
b53da244 AN |
13960 | /* Return whether CFG is used in mips_reorg. */ |
13961 | ||
13962 | static bool | |
13963 | mips_cfg_in_reorg (void) | |
13964 | { | |
13965 | return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE | |
13966 | || TARGET_RELAX_PIC_CALLS); | |
13967 | } | |
13968 | ||
ab77a036 | 13969 | /* Build MIPS16 constant pools. */ |
a27fb29b | 13970 | |
ab77a036 RS |
13971 | static void |
13972 | mips16_lay_out_constants (void) | |
a27fb29b | 13973 | { |
ab77a036 RS |
13974 | struct mips16_constant_pool pool; |
13975 | struct mips16_rewrite_pool_refs_info info; | |
13976 | rtx insn, barrier; | |
a27fb29b | 13977 | |
ab77a036 RS |
13978 | if (!TARGET_MIPS16_PCREL_LOADS) |
13979 | return; | |
a27fb29b | 13980 | |
b53da244 AN |
13981 | if (mips_cfg_in_reorg ()) |
13982 | split_all_insns (); | |
13983 | else | |
13984 | split_all_insns_noflow (); | |
ab77a036 RS |
13985 | barrier = 0; |
13986 | memset (&pool, 0, sizeof (pool)); | |
13987 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
13988 | { | |
13989 | /* Rewrite constant pool references in INSN. */ | |
006b29ab | 13990 | if (USEFUL_INSN_P (insn)) |
ab77a036 RS |
13991 | { |
13992 | info.insn = insn; | |
13993 | info.pool = &pool; | |
13994 | for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info); | |
13995 | } | |
dfad12b5 | 13996 | |
ab77a036 | 13997 | pool.insn_address += mips16_insn_length (insn); |
0e5a4ad8 | 13998 | |
ab77a036 RS |
13999 | if (pool.first != NULL) |
14000 | { | |
14001 | /* If there are no natural barriers between the first user of | |
14002 | the pool and the highest acceptable address, we'll need to | |
14003 | create a new instruction to jump around the constant pool. | |
14004 | In the worst case, this instruction will be 4 bytes long. | |
dfad12b5 | 14005 | |
ab77a036 RS |
14006 | If it's too late to do this transformation after INSN, |
14007 | do it immediately before INSN. */ | |
14008 | if (barrier == 0 && pool.insn_address + 4 > pool.highest_address) | |
14009 | { | |
14010 | rtx label, jump; | |
54401342 | 14011 | |
ab77a036 RS |
14012 | label = gen_label_rtx (); |
14013 | ||
14014 | jump = emit_jump_insn_before (gen_jump (label), insn); | |
14015 | JUMP_LABEL (jump) = label; | |
14016 | LABEL_NUSES (label) = 1; | |
14017 | barrier = emit_barrier_after (jump); | |
14018 | ||
14019 | emit_label_after (label, barrier); | |
14020 | pool.insn_address += 4; | |
14021 | } | |
14022 | ||
14023 | /* See whether the constant pool is now out of range of the first | |
14024 | user. If so, output the constants after the previous barrier. | |
14025 | Note that any instructions between BARRIER and INSN (inclusive) | |
14026 | will use negative offsets to refer to the pool. */ | |
14027 | if (pool.insn_address > pool.highest_address) | |
14028 | { | |
65239d20 | 14029 | mips16_emit_constants (pool.first, barrier); |
ab77a036 RS |
14030 | pool.first = NULL; |
14031 | barrier = 0; | |
14032 | } | |
14033 | else if (BARRIER_P (insn)) | |
14034 | barrier = insn; | |
14035 | } | |
14036 | } | |
65239d20 | 14037 | mips16_emit_constants (pool.first, get_last_insn ()); |
0c8da560 | 14038 | } |
50d32cf6 | 14039 | \f |
4d210b07 RS |
14040 | /* Return true if it is worth r10k_simplify_address's while replacing |
14041 | an address with X. We are looking for constants, and for addresses | |
14042 | at a known offset from the incoming stack pointer. */ | |
14043 | ||
14044 | static bool | |
14045 | r10k_simplified_address_p (rtx x) | |
14046 | { | |
14047 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) | |
14048 | x = XEXP (x, 0); | |
14049 | return x == virtual_incoming_args_rtx || CONSTANT_P (x); | |
14050 | } | |
14051 | ||
14052 | /* X is an expression that appears in INSN. Try to use the UD chains | |
14053 | to simplify it, returning the simplified form on success and the | |
14054 | original form otherwise. Replace the incoming value of $sp with | |
14055 | virtual_incoming_args_rtx (which should never occur in X otherwise). */ | |
14056 | ||
14057 | static rtx | |
14058 | r10k_simplify_address (rtx x, rtx insn) | |
14059 | { | |
14060 | rtx newx, op0, op1, set, def_insn, note; | |
57512f53 | 14061 | df_ref use, def; |
4d210b07 RS |
14062 | struct df_link *defs; |
14063 | ||
14064 | newx = NULL_RTX; | |
14065 | if (UNARY_P (x)) | |
14066 | { | |
14067 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
14068 | if (op0 != XEXP (x, 0)) | |
14069 | newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x), | |
14070 | op0, GET_MODE (XEXP (x, 0))); | |
14071 | } | |
14072 | else if (BINARY_P (x)) | |
14073 | { | |
14074 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
14075 | op1 = r10k_simplify_address (XEXP (x, 1), insn); | |
14076 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
14077 | newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); | |
14078 | } | |
14079 | else if (GET_CODE (x) == LO_SUM) | |
14080 | { | |
14081 | /* LO_SUMs can be offset from HIGHs, if we know they won't | |
14082 | overflow. See mips_classify_address for the rationale behind | |
14083 | the lax check. */ | |
14084 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
14085 | if (GET_CODE (op0) == HIGH) | |
14086 | newx = XEXP (x, 1); | |
14087 | } | |
14088 | else if (REG_P (x)) | |
14089 | { | |
14090 | /* Uses are recorded by regno_reg_rtx, not X itself. */ | |
14091 | use = df_find_use (insn, regno_reg_rtx[REGNO (x)]); | |
14092 | gcc_assert (use); | |
14093 | defs = DF_REF_CHAIN (use); | |
14094 | ||
14095 | /* Require a single definition. */ | |
14096 | if (defs && defs->next == NULL) | |
14097 | { | |
14098 | def = defs->ref; | |
14099 | if (DF_REF_IS_ARTIFICIAL (def)) | |
14100 | { | |
14101 | /* Replace the incoming value of $sp with | |
14102 | virtual_incoming_args_rtx. */ | |
14103 | if (x == stack_pointer_rtx | |
14104 | && DF_REF_BB (def) == ENTRY_BLOCK_PTR) | |
14105 | newx = virtual_incoming_args_rtx; | |
14106 | } | |
14107 | else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use), | |
14108 | DF_REF_BB (def))) | |
14109 | { | |
14110 | /* Make sure that DEF_INSN is a single set of REG. */ | |
14111 | def_insn = DF_REF_INSN (def); | |
14112 | if (NONJUMP_INSN_P (def_insn)) | |
14113 | { | |
14114 | set = single_set (def_insn); | |
14115 | if (set && rtx_equal_p (SET_DEST (set), x)) | |
14116 | { | |
14117 | /* Prefer to use notes, since the def-use chains | |
14118 | are often shorter. */ | |
14119 | note = find_reg_equal_equiv_note (def_insn); | |
14120 | if (note) | |
14121 | newx = XEXP (note, 0); | |
14122 | else | |
14123 | newx = SET_SRC (set); | |
14124 | newx = r10k_simplify_address (newx, def_insn); | |
14125 | } | |
14126 | } | |
14127 | } | |
14128 | } | |
14129 | } | |
14130 | if (newx && r10k_simplified_address_p (newx)) | |
14131 | return newx; | |
14132 | return x; | |
14133 | } | |
14134 | ||
14135 | /* Return true if ADDRESS is known to be an uncached address | |
14136 | on R10K systems. */ | |
14137 | ||
14138 | static bool | |
14139 | r10k_uncached_address_p (unsigned HOST_WIDE_INT address) | |
14140 | { | |
14141 | unsigned HOST_WIDE_INT upper; | |
14142 | ||
14143 | /* Check for KSEG1. */ | |
14144 | if (address + 0x60000000 < 0x20000000) | |
14145 | return true; | |
14146 | ||
14147 | /* Check for uncached XKPHYS addresses. */ | |
14148 | if (Pmode == DImode) | |
14149 | { | |
14150 | upper = (address >> 40) & 0xf9ffff; | |
14151 | if (upper == 0x900000 || upper == 0xb80000) | |
14152 | return true; | |
14153 | } | |
14154 | return false; | |
14155 | } | |
14156 | ||
14157 | /* Return true if we can prove that an access to address X in instruction | |
14158 | INSN would be safe from R10K speculation. This X is a general | |
14159 | expression; it might not be a legitimate address. */ | |
14160 | ||
14161 | static bool | |
14162 | r10k_safe_address_p (rtx x, rtx insn) | |
14163 | { | |
14164 | rtx base, offset; | |
14165 | HOST_WIDE_INT offset_val; | |
14166 | ||
14167 | x = r10k_simplify_address (x, insn); | |
14168 | ||
14169 | /* Check for references to the stack frame. It doesn't really matter | |
14170 | how much of the frame has been allocated at INSN; -mr10k-cache-barrier | |
14171 | allows us to assume that accesses to any part of the eventual frame | |
14172 | is safe from speculation at any point in the function. */ | |
14173 | mips_split_plus (x, &base, &offset_val); | |
14174 | if (base == virtual_incoming_args_rtx | |
14175 | && offset_val >= -cfun->machine->frame.total_size | |
14176 | && offset_val < cfun->machine->frame.args_size) | |
14177 | return true; | |
14178 | ||
14179 | /* Check for uncached addresses. */ | |
14180 | if (CONST_INT_P (x)) | |
14181 | return r10k_uncached_address_p (INTVAL (x)); | |
14182 | ||
14183 | /* Check for accesses to a static object. */ | |
14184 | split_const (x, &base, &offset); | |
14185 | return offset_within_block_p (base, INTVAL (offset)); | |
14186 | } | |
14187 | ||
14188 | /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is | |
14189 | an in-range access to an automatic variable, or to an object with | |
14190 | a link-time-constant address. */ | |
14191 | ||
14192 | static bool | |
527210c4 | 14193 | r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset) |
4d210b07 | 14194 | { |
527210c4 | 14195 | if (offset < 0 || offset >= int_size_in_bytes (TREE_TYPE (expr))) |
4d210b07 RS |
14196 | return false; |
14197 | ||
14198 | while (TREE_CODE (expr) == COMPONENT_REF) | |
14199 | { | |
14200 | expr = TREE_OPERAND (expr, 0); | |
14201 | if (expr == NULL_TREE) | |
14202 | return false; | |
14203 | } | |
14204 | ||
14205 | return DECL_P (expr); | |
14206 | } | |
14207 | ||
14208 | /* A for_each_rtx callback for which DATA points to the instruction | |
14209 | containing *X. Stop the search if we find a MEM that is not safe | |
14210 | from R10K speculation. */ | |
14211 | ||
14212 | static int | |
14213 | r10k_needs_protection_p_1 (rtx *loc, void *data) | |
14214 | { | |
14215 | rtx mem; | |
14216 | ||
14217 | mem = *loc; | |
14218 | if (!MEM_P (mem)) | |
14219 | return 0; | |
14220 | ||
527210c4 RS |
14221 | if (MEM_EXPR (mem) |
14222 | && MEM_OFFSET_KNOWN_P (mem) | |
14223 | && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem))) | |
4d210b07 RS |
14224 | return -1; |
14225 | ||
14226 | if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data)) | |
14227 | return -1; | |
14228 | ||
14229 | return 1; | |
14230 | } | |
14231 | ||
14232 | /* A note_stores callback for which DATA points to an instruction pointer. | |
14233 | If *DATA is nonnull, make it null if it X contains a MEM that is not | |
14234 | safe from R10K speculation. */ | |
14235 | ||
14236 | static void | |
14237 | r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED, | |
14238 | void *data) | |
14239 | { | |
14240 | rtx *insn_ptr; | |
14241 | ||
14242 | insn_ptr = (rtx *) data; | |
14243 | if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr)) | |
14244 | *insn_ptr = NULL_RTX; | |
14245 | } | |
14246 | ||
14247 | /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN. | |
14248 | Return nonzero if the call is not to a declared function. */ | |
14249 | ||
14250 | static int | |
14251 | r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
14252 | { | |
14253 | rtx x; | |
14254 | ||
14255 | x = *loc; | |
14256 | if (!MEM_P (x)) | |
14257 | return 0; | |
14258 | ||
14259 | x = XEXP (x, 0); | |
14260 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x)) | |
14261 | return -1; | |
14262 | ||
14263 | return 1; | |
14264 | } | |
14265 | ||
14266 | /* Return true if instruction INSN needs to be protected by an R10K | |
14267 | cache barrier. */ | |
14268 | ||
14269 | static bool | |
14270 | r10k_needs_protection_p (rtx insn) | |
14271 | { | |
14272 | if (CALL_P (insn)) | |
14273 | return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL); | |
14274 | ||
14275 | if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE) | |
14276 | { | |
14277 | note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn); | |
14278 | return insn == NULL_RTX; | |
14279 | } | |
14280 | ||
14281 | return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn); | |
14282 | } | |
14283 | ||
14284 | /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every | |
14285 | edge is unconditional. */ | |
14286 | ||
14287 | static bool | |
14288 | r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs) | |
14289 | { | |
14290 | edge_iterator ei; | |
14291 | edge e; | |
14292 | ||
14293 | FOR_EACH_EDGE (e, ei, bb->preds) | |
14294 | if (!single_succ_p (e->src) | |
14295 | || !TEST_BIT (protected_bbs, e->src->index) | |
14296 | || (e->flags & EDGE_COMPLEX) != 0) | |
14297 | return false; | |
14298 | return true; | |
14299 | } | |
14300 | ||
14301 | /* Implement -mr10k-cache-barrier= for the current function. */ | |
14302 | ||
14303 | static void | |
14304 | r10k_insert_cache_barriers (void) | |
14305 | { | |
14306 | int *rev_post_order; | |
14307 | unsigned int i, n; | |
14308 | basic_block bb; | |
14309 | sbitmap protected_bbs; | |
14310 | rtx insn, end, unprotected_region; | |
14311 | ||
14312 | if (TARGET_MIPS16) | |
14313 | { | |
14314 | sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier"); | |
14315 | return; | |
14316 | } | |
14317 | ||
4d210b07 RS |
14318 | /* Calculate dominators. */ |
14319 | calculate_dominance_info (CDI_DOMINATORS); | |
14320 | ||
14321 | /* Bit X of PROTECTED_BBS is set if the last operation in basic block | |
14322 | X is protected by a cache barrier. */ | |
14323 | protected_bbs = sbitmap_alloc (last_basic_block); | |
14324 | sbitmap_zero (protected_bbs); | |
14325 | ||
14326 | /* Iterate over the basic blocks in reverse post-order. */ | |
14327 | rev_post_order = XNEWVEC (int, last_basic_block); | |
14328 | n = pre_and_rev_post_order_compute (NULL, rev_post_order, false); | |
14329 | for (i = 0; i < n; i++) | |
14330 | { | |
14331 | bb = BASIC_BLOCK (rev_post_order[i]); | |
14332 | ||
14333 | /* If this block is only reached by unconditional edges, and if the | |
14334 | source of every edge is protected, the beginning of the block is | |
14335 | also protected. */ | |
14336 | if (r10k_protected_bb_p (bb, protected_bbs)) | |
14337 | unprotected_region = NULL_RTX; | |
14338 | else | |
14339 | unprotected_region = pc_rtx; | |
14340 | end = NEXT_INSN (BB_END (bb)); | |
14341 | ||
14342 | /* UNPROTECTED_REGION is: | |
14343 | ||
14344 | - null if we are processing a protected region, | |
14345 | - pc_rtx if we are processing an unprotected region but have | |
14346 | not yet found the first instruction in it | |
14347 | - the first instruction in an unprotected region otherwise. */ | |
14348 | for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn)) | |
14349 | { | |
006b29ab | 14350 | if (unprotected_region && USEFUL_INSN_P (insn)) |
4d210b07 RS |
14351 | { |
14352 | if (recog_memoized (insn) == CODE_FOR_mips_cache) | |
14353 | /* This CACHE instruction protects the following code. */ | |
14354 | unprotected_region = NULL_RTX; | |
14355 | else | |
14356 | { | |
14357 | /* See if INSN is the first instruction in this | |
14358 | unprotected region. */ | |
14359 | if (unprotected_region == pc_rtx) | |
14360 | unprotected_region = insn; | |
14361 | ||
14362 | /* See if INSN needs to be protected. If so, | |
14363 | we must insert a cache barrier somewhere between | |
14364 | PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't | |
14365 | clear which position is better performance-wise, | |
14366 | but as a tie-breaker, we assume that it is better | |
14367 | to allow delay slots to be back-filled where | |
14368 | possible, and that it is better not to insert | |
14369 | barriers in the middle of already-scheduled code. | |
14370 | We therefore insert the barrier at the beginning | |
14371 | of the region. */ | |
14372 | if (r10k_needs_protection_p (insn)) | |
14373 | { | |
14374 | emit_insn_before (gen_r10k_cache_barrier (), | |
14375 | unprotected_region); | |
14376 | unprotected_region = NULL_RTX; | |
14377 | } | |
14378 | } | |
14379 | } | |
14380 | ||
14381 | if (CALL_P (insn)) | |
14382 | /* The called function is not required to protect the exit path. | |
14383 | The code that follows a call is therefore unprotected. */ | |
14384 | unprotected_region = pc_rtx; | |
14385 | } | |
14386 | ||
14387 | /* Record whether the end of this block is protected. */ | |
14388 | if (unprotected_region == NULL_RTX) | |
14389 | SET_BIT (protected_bbs, bb->index); | |
14390 | } | |
14391 | XDELETEVEC (rev_post_order); | |
14392 | ||
14393 | sbitmap_free (protected_bbs); | |
14394 | ||
14395 | free_dominance_info (CDI_DOMINATORS); | |
b53da244 AN |
14396 | } |
14397 | \f | |
14398 | /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX | |
951771dc JW |
14399 | otherwise. If INSN has two call rtx, then store the second one in |
14400 | SECOND_CALL. */ | |
4d210b07 | 14401 | |
b53da244 | 14402 | static rtx |
951771dc | 14403 | mips_call_expr_from_insn (rtx insn, rtx *second_call) |
b53da244 AN |
14404 | { |
14405 | rtx x; | |
951771dc | 14406 | rtx x2; |
b53da244 AN |
14407 | |
14408 | if (!CALL_P (insn)) | |
14409 | return NULL_RTX; | |
4d210b07 | 14410 | |
b53da244 AN |
14411 | x = PATTERN (insn); |
14412 | if (GET_CODE (x) == PARALLEL) | |
951771dc JW |
14413 | { |
14414 | /* Calls returning complex values have two CALL rtx. Look for the second | |
14415 | one here, and return it via the SECOND_CALL arg. */ | |
14416 | x2 = XVECEXP (x, 0, 1); | |
14417 | if (GET_CODE (x2) == SET) | |
14418 | x2 = XEXP (x2, 1); | |
14419 | if (GET_CODE (x2) == CALL) | |
14420 | *second_call = x2; | |
14421 | ||
14422 | x = XVECEXP (x, 0, 0); | |
14423 | } | |
b53da244 AN |
14424 | if (GET_CODE (x) == SET) |
14425 | x = XEXP (x, 1); | |
b53da244 | 14426 | gcc_assert (GET_CODE (x) == CALL); |
951771dc | 14427 | |
b53da244 AN |
14428 | return x; |
14429 | } | |
14430 | ||
14431 | /* REG is set in DEF. See if the definition is one of the ways we load a | |
ee3ee488 RS |
14432 | register with a symbol address for a mips_use_pic_fn_addr_reg_p call. |
14433 | If it is, return the symbol reference of the function, otherwise return | |
14434 | NULL_RTX. | |
14435 | ||
14436 | If RECURSE_P is true, use mips_find_pic_call_symbol to interpret | |
14437 | the values of source registers, otherwise treat such registers as | |
14438 | having an unknown value. */ | |
b53da244 AN |
14439 | |
14440 | static rtx | |
ee3ee488 | 14441 | mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p) |
b53da244 AN |
14442 | { |
14443 | rtx def_insn, set; | |
14444 | ||
14445 | if (DF_REF_IS_ARTIFICIAL (def)) | |
14446 | return NULL_RTX; | |
14447 | ||
14448 | def_insn = DF_REF_INSN (def); | |
14449 | set = single_set (def_insn); | |
14450 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
14451 | { | |
14452 | rtx note, src, symbol; | |
14453 | ||
14454 | /* First, look at REG_EQUAL/EQUIV notes. */ | |
14455 | note = find_reg_equal_equiv_note (def_insn); | |
14456 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
14457 | return XEXP (note, 0); | |
14458 | ||
14459 | /* For %call16 references we don't have REG_EQUAL. */ | |
14460 | src = SET_SRC (set); | |
14461 | symbol = mips_strip_unspec_call (src); | |
14462 | if (symbol) | |
14463 | { | |
14464 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
14465 | return symbol; | |
14466 | } | |
14467 | ||
ee3ee488 RS |
14468 | /* Follow at most one simple register copy. Such copies are |
14469 | interesting in cases like: | |
14470 | ||
14471 | for (...) | |
14472 | { | |
14473 | locally_binding_fn (...); | |
14474 | } | |
14475 | ||
14476 | and: | |
14477 | ||
14478 | locally_binding_fn (...); | |
14479 | ... | |
14480 | locally_binding_fn (...); | |
14481 | ||
14482 | where the load of locally_binding_fn can legitimately be | |
14483 | hoisted or shared. However, we do not expect to see complex | |
14484 | chains of copies, so a full worklist solution to the problem | |
14485 | would probably be overkill. */ | |
14486 | if (recurse_p && REG_P (src)) | |
14487 | return mips_find_pic_call_symbol (def_insn, src, false); | |
b53da244 AN |
14488 | } |
14489 | ||
14490 | return NULL_RTX; | |
14491 | } | |
14492 | ||
ee3ee488 RS |
14493 | /* Find the definition of the use of REG in INSN. See if the definition |
14494 | is one of the ways we load a register with a symbol address for a | |
14495 | mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference | |
14496 | of the function, otherwise return NULL_RTX. RECURSE_P is as for | |
14497 | mips_pic_call_symbol_from_set. */ | |
b53da244 AN |
14498 | |
14499 | static rtx | |
ee3ee488 | 14500 | mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p) |
b53da244 AN |
14501 | { |
14502 | df_ref use; | |
14503 | struct df_link *defs; | |
14504 | rtx symbol; | |
14505 | ||
14506 | use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]); | |
14507 | if (!use) | |
14508 | return NULL_RTX; | |
14509 | defs = DF_REF_CHAIN (use); | |
14510 | if (!defs) | |
14511 | return NULL_RTX; | |
ee3ee488 | 14512 | symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); |
b53da244 AN |
14513 | if (!symbol) |
14514 | return NULL_RTX; | |
14515 | ||
14516 | /* If we have more than one definition, they need to be identical. */ | |
14517 | for (defs = defs->next; defs; defs = defs->next) | |
14518 | { | |
14519 | rtx other; | |
14520 | ||
ee3ee488 | 14521 | other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); |
b53da244 AN |
14522 | if (!rtx_equal_p (symbol, other)) |
14523 | return NULL_RTX; | |
14524 | } | |
14525 | ||
14526 | return symbol; | |
14527 | } | |
14528 | ||
14529 | /* Replace the args_size operand of the call expression CALL with the | |
14530 | call-attribute UNSPEC and fill in SYMBOL as the function symbol. */ | |
14531 | ||
14532 | static void | |
14533 | mips_annotate_pic_call_expr (rtx call, rtx symbol) | |
14534 | { | |
14535 | rtx args_size; | |
14536 | ||
14537 | args_size = XEXP (call, 1); | |
14538 | XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size), | |
14539 | gen_rtvec (2, args_size, symbol), | |
14540 | UNSPEC_CALL_ATTR); | |
14541 | } | |
14542 | ||
14543 | /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See | |
14544 | if instead of the arg_size argument it contains the call attributes. If | |
14545 | yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function | |
14546 | symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is | |
14547 | -1. */ | |
14548 | ||
14549 | bool | |
14550 | mips_get_pic_call_symbol (rtx *operands, int args_size_opno) | |
14551 | { | |
14552 | rtx args_size, symbol; | |
14553 | ||
14554 | if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1) | |
14555 | return false; | |
14556 | ||
14557 | args_size = operands[args_size_opno]; | |
14558 | if (GET_CODE (args_size) != UNSPEC) | |
14559 | return false; | |
14560 | gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR); | |
14561 | ||
14562 | symbol = XVECEXP (args_size, 0, 1); | |
14563 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
14564 | ||
14565 | operands[args_size_opno] = symbol; | |
14566 | return true; | |
14567 | } | |
14568 | ||
14569 | /* Use DF to annotate PIC indirect calls with the function symbol they | |
14570 | dispatch to. */ | |
14571 | ||
14572 | static void | |
14573 | mips_annotate_pic_calls (void) | |
14574 | { | |
14575 | basic_block bb; | |
14576 | rtx insn; | |
14577 | ||
14578 | FOR_EACH_BB (bb) | |
14579 | FOR_BB_INSNS (bb, insn) | |
14580 | { | |
951771dc | 14581 | rtx call, reg, symbol, second_call; |
b53da244 | 14582 | |
951771dc JW |
14583 | second_call = 0; |
14584 | call = mips_call_expr_from_insn (insn, &second_call); | |
b53da244 AN |
14585 | if (!call) |
14586 | continue; | |
14587 | gcc_assert (MEM_P (XEXP (call, 0))); | |
14588 | reg = XEXP (XEXP (call, 0), 0); | |
14589 | if (!REG_P (reg)) | |
14590 | continue; | |
14591 | ||
ee3ee488 | 14592 | symbol = mips_find_pic_call_symbol (insn, reg, true); |
b53da244 | 14593 | if (symbol) |
951771dc JW |
14594 | { |
14595 | mips_annotate_pic_call_expr (call, symbol); | |
14596 | if (second_call) | |
14597 | mips_annotate_pic_call_expr (second_call, symbol); | |
14598 | } | |
b53da244 | 14599 | } |
4d210b07 RS |
14600 | } |
14601 | \f | |
ab77a036 RS |
14602 | /* A temporary variable used by for_each_rtx callbacks, etc. */ |
14603 | static rtx mips_sim_insn; | |
39ba1719 | 14604 | |
ab77a036 RS |
14605 | /* A structure representing the state of the processor pipeline. |
14606 | Used by the mips_sim_* family of functions. */ | |
14607 | struct mips_sim { | |
14608 | /* The maximum number of instructions that can be issued in a cycle. | |
14609 | (Caches mips_issue_rate.) */ | |
14610 | unsigned int issue_rate; | |
39ba1719 | 14611 | |
ab77a036 RS |
14612 | /* The current simulation time. */ |
14613 | unsigned int time; | |
39ba1719 | 14614 | |
ab77a036 RS |
14615 | /* How many more instructions can be issued in the current cycle. */ |
14616 | unsigned int insns_left; | |
39ba1719 | 14617 | |
ab77a036 RS |
14618 | /* LAST_SET[X].INSN is the last instruction to set register X. |
14619 | LAST_SET[X].TIME is the time at which that instruction was issued. | |
14620 | INSN is null if no instruction has yet set register X. */ | |
14621 | struct { | |
14622 | rtx insn; | |
14623 | unsigned int time; | |
14624 | } last_set[FIRST_PSEUDO_REGISTER]; | |
39ba1719 | 14625 | |
ab77a036 RS |
14626 | /* The pipeline's current DFA state. */ |
14627 | state_t dfa_state; | |
14628 | }; | |
39ba1719 | 14629 | |
ab77a036 RS |
14630 | /* Reset STATE to the initial simulation state. */ |
14631 | ||
14632 | static void | |
14633 | mips_sim_reset (struct mips_sim *state) | |
14634 | { | |
14635 | state->time = 0; | |
14636 | state->insns_left = state->issue_rate; | |
14637 | memset (&state->last_set, 0, sizeof (state->last_set)); | |
14638 | state_reset (state->dfa_state); | |
39ba1719 | 14639 | } |
39ba1719 | 14640 | |
ab77a036 RS |
14641 | /* Initialize STATE before its first use. DFA_STATE points to an |
14642 | allocated but uninitialized DFA state. */ | |
39ba1719 | 14643 | |
ab77a036 RS |
14644 | static void |
14645 | mips_sim_init (struct mips_sim *state, state_t dfa_state) | |
14646 | { | |
14647 | state->issue_rate = mips_issue_rate (); | |
14648 | state->dfa_state = dfa_state; | |
14649 | mips_sim_reset (state); | |
14650 | } | |
14651 | ||
14652 | /* Advance STATE by one clock cycle. */ | |
39ba1719 RS |
14653 | |
14654 | static void | |
ab77a036 | 14655 | mips_sim_next_cycle (struct mips_sim *state) |
39ba1719 | 14656 | { |
ab77a036 RS |
14657 | state->time++; |
14658 | state->insns_left = state->issue_rate; | |
14659 | state_transition (state->dfa_state, 0); | |
39ba1719 RS |
14660 | } |
14661 | ||
ab77a036 RS |
14662 | /* Advance simulation state STATE until instruction INSN can read |
14663 | register REG. */ | |
39ba1719 RS |
14664 | |
14665 | static void | |
ab77a036 | 14666 | mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg) |
39ba1719 | 14667 | { |
65239d20 | 14668 | unsigned int regno, end_regno; |
39ba1719 | 14669 | |
65239d20 RS |
14670 | end_regno = END_REGNO (reg); |
14671 | for (regno = REGNO (reg); regno < end_regno; regno++) | |
14672 | if (state->last_set[regno].insn != 0) | |
ab77a036 RS |
14673 | { |
14674 | unsigned int t; | |
dc884a86 | 14675 | |
65239d20 RS |
14676 | t = (state->last_set[regno].time |
14677 | + insn_latency (state->last_set[regno].insn, insn)); | |
ab77a036 RS |
14678 | while (state->time < t) |
14679 | mips_sim_next_cycle (state); | |
14680 | } | |
14681 | } | |
dc884a86 | 14682 | |
ab77a036 RS |
14683 | /* A for_each_rtx callback. If *X is a register, advance simulation state |
14684 | DATA until mips_sim_insn can read the register's value. */ | |
dc884a86 | 14685 | |
ab77a036 RS |
14686 | static int |
14687 | mips_sim_wait_regs_2 (rtx *x, void *data) | |
dc884a86 | 14688 | { |
ab77a036 | 14689 | if (REG_P (*x)) |
5ead67f6 | 14690 | mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x); |
ab77a036 | 14691 | return 0; |
dc884a86 RS |
14692 | } |
14693 | ||
ab77a036 | 14694 | /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */ |
dc884a86 | 14695 | |
ab77a036 RS |
14696 | static void |
14697 | mips_sim_wait_regs_1 (rtx *x, void *data) | |
dc884a86 | 14698 | { |
ab77a036 | 14699 | for_each_rtx (x, mips_sim_wait_regs_2, data); |
dc884a86 RS |
14700 | } |
14701 | ||
ab77a036 RS |
14702 | /* Advance simulation state STATE until all of INSN's register |
14703 | dependencies are satisfied. */ | |
dc884a86 | 14704 | |
ab77a036 RS |
14705 | static void |
14706 | mips_sim_wait_regs (struct mips_sim *state, rtx insn) | |
dc884a86 | 14707 | { |
ab77a036 RS |
14708 | mips_sim_insn = insn; |
14709 | note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state); | |
14710 | } | |
dc884a86 | 14711 | |
ab77a036 RS |
14712 | /* Advance simulation state STATE until the units required by |
14713 | instruction INSN are available. */ | |
dc884a86 | 14714 | |
ab77a036 RS |
14715 | static void |
14716 | mips_sim_wait_units (struct mips_sim *state, rtx insn) | |
14717 | { | |
14718 | state_t tmp_state; | |
dc884a86 | 14719 | |
ab77a036 RS |
14720 | tmp_state = alloca (state_size ()); |
14721 | while (state->insns_left == 0 | |
14722 | || (memcpy (tmp_state, state->dfa_state, state_size ()), | |
14723 | state_transition (tmp_state, insn) >= 0)) | |
14724 | mips_sim_next_cycle (state); | |
dc884a86 RS |
14725 | } |
14726 | ||
ab77a036 | 14727 | /* Advance simulation state STATE until INSN is ready to issue. */ |
dc884a86 RS |
14728 | |
14729 | static void | |
ab77a036 | 14730 | mips_sim_wait_insn (struct mips_sim *state, rtx insn) |
dc884a86 | 14731 | { |
ab77a036 RS |
14732 | mips_sim_wait_regs (state, insn); |
14733 | mips_sim_wait_units (state, insn); | |
dc884a86 | 14734 | } |
ab77a036 RS |
14735 | |
14736 | /* mips_sim_insn has just set X. Update the LAST_SET array | |
14737 | in simulation state DATA. */ | |
39ba1719 RS |
14738 | |
14739 | static void | |
ab77a036 | 14740 | mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
39ba1719 | 14741 | { |
ab77a036 | 14742 | struct mips_sim *state; |
39ba1719 | 14743 | |
5ead67f6 | 14744 | state = (struct mips_sim *) data; |
ab77a036 | 14745 | if (REG_P (x)) |
65239d20 RS |
14746 | { |
14747 | unsigned int regno, end_regno; | |
14748 | ||
14749 | end_regno = END_REGNO (x); | |
14750 | for (regno = REGNO (x); regno < end_regno; regno++) | |
14751 | { | |
14752 | state->last_set[regno].insn = mips_sim_insn; | |
14753 | state->last_set[regno].time = state->time; | |
14754 | } | |
14755 | } | |
39ba1719 RS |
14756 | } |
14757 | ||
ab77a036 RS |
14758 | /* Issue instruction INSN in scheduler state STATE. Assume that INSN |
14759 | can issue immediately (i.e., that mips_sim_wait_insn has already | |
14760 | been called). */ | |
39ba1719 | 14761 | |
174bd8ca | 14762 | static void |
ab77a036 | 14763 | mips_sim_issue_insn (struct mips_sim *state, rtx insn) |
174bd8ca | 14764 | { |
ab77a036 RS |
14765 | state_transition (state->dfa_state, insn); |
14766 | state->insns_left--; | |
174bd8ca | 14767 | |
ab77a036 RS |
14768 | mips_sim_insn = insn; |
14769 | note_stores (PATTERN (insn), mips_sim_record_set, state); | |
14770 | } | |
174bd8ca | 14771 | |
ab77a036 | 14772 | /* Simulate issuing a NOP in state STATE. */ |
174bd8ca SL |
14773 | |
14774 | static void | |
ab77a036 | 14775 | mips_sim_issue_nop (struct mips_sim *state) |
174bd8ca | 14776 | { |
ab77a036 RS |
14777 | if (state->insns_left == 0) |
14778 | mips_sim_next_cycle (state); | |
14779 | state->insns_left--; | |
174bd8ca SL |
14780 | } |
14781 | ||
ab77a036 RS |
14782 | /* Update simulation state STATE so that it's ready to accept the instruction |
14783 | after INSN. INSN should be part of the main rtl chain, not a member of a | |
14784 | SEQUENCE. */ | |
174bd8ca SL |
14785 | |
14786 | static void | |
ab77a036 | 14787 | mips_sim_finish_insn (struct mips_sim *state, rtx insn) |
39ba1719 | 14788 | { |
ab77a036 RS |
14789 | /* If INSN is a jump with an implicit delay slot, simulate a nop. */ |
14790 | if (JUMP_P (insn)) | |
14791 | mips_sim_issue_nop (state); | |
174bd8ca | 14792 | |
ab77a036 | 14793 | switch (GET_CODE (SEQ_BEGIN (insn))) |
39ba1719 | 14794 | { |
ab77a036 RS |
14795 | case CODE_LABEL: |
14796 | case CALL_INSN: | |
14797 | /* We can't predict the processor state after a call or label. */ | |
14798 | mips_sim_reset (state); | |
14799 | break; | |
d33289b2 | 14800 | |
ab77a036 RS |
14801 | case JUMP_INSN: |
14802 | /* The delay slots of branch likely instructions are only executed | |
14803 | when the branch is taken. Therefore, if the caller has simulated | |
14804 | the delay slot instruction, STATE does not really reflect the state | |
14805 | of the pipeline for the instruction after the delay slot. Also, | |
14806 | branch likely instructions tend to incur a penalty when not taken, | |
14807 | so there will probably be an extra delay between the branch and | |
14808 | the instruction after the delay slot. */ | |
14809 | if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn))) | |
14810 | mips_sim_reset (state); | |
14811 | break; | |
d33289b2 | 14812 | |
ab77a036 RS |
14813 | default: |
14814 | break; | |
dc884a86 | 14815 | } |
174bd8ca | 14816 | } |
ab77a036 RS |
14817 | \f |
14818 | /* The VR4130 pipeline issues aligned pairs of instructions together, | |
14819 | but it stalls the second instruction if it depends on the first. | |
14820 | In order to cut down the amount of logic required, this dependence | |
14821 | check is not based on a full instruction decode. Instead, any non-SPECIAL | |
14822 | instruction is assumed to modify the register specified by bits 20-16 | |
14823 | (which is usually the "rt" field). | |
174bd8ca | 14824 | |
65239d20 | 14825 | In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an |
ab77a036 RS |
14826 | input, so we can end up with a false dependence between the branch |
14827 | and its delay slot. If this situation occurs in instruction INSN, | |
14828 | try to avoid it by swapping rs and rt. */ | |
174bd8ca SL |
14829 | |
14830 | static void | |
ab77a036 | 14831 | vr4130_avoid_branch_rt_conflict (rtx insn) |
174bd8ca | 14832 | { |
ab77a036 | 14833 | rtx first, second; |
39ba1719 | 14834 | |
ab77a036 RS |
14835 | first = SEQ_BEGIN (insn); |
14836 | second = SEQ_END (insn); | |
14837 | if (JUMP_P (first) | |
14838 | && NONJUMP_INSN_P (second) | |
14839 | && GET_CODE (PATTERN (first)) == SET | |
14840 | && GET_CODE (SET_DEST (PATTERN (first))) == PC | |
14841 | && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE) | |
39ba1719 | 14842 | { |
ab77a036 RS |
14843 | /* Check for the right kind of condition. */ |
14844 | rtx cond = XEXP (SET_SRC (PATTERN (first)), 0); | |
14845 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
14846 | && REG_P (XEXP (cond, 0)) | |
14847 | && REG_P (XEXP (cond, 1)) | |
14848 | && reg_referenced_p (XEXP (cond, 1), PATTERN (second)) | |
14849 | && !reg_referenced_p (XEXP (cond, 0), PATTERN (second))) | |
14850 | { | |
14851 | /* SECOND mentions the rt register but not the rs register. */ | |
14852 | rtx tmp = XEXP (cond, 0); | |
14853 | XEXP (cond, 0) = XEXP (cond, 1); | |
14854 | XEXP (cond, 1) = tmp; | |
14855 | } | |
39ba1719 | 14856 | } |
39ba1719 RS |
14857 | } |
14858 | ||
ab77a036 RS |
14859 | /* Implement -mvr4130-align. Go through each basic block and simulate the |
14860 | processor pipeline. If we find that a pair of instructions could execute | |
65239d20 | 14861 | in parallel, and the first of those instructions is not 8-byte aligned, |
ab77a036 | 14862 | insert a nop to make it aligned. */ |
0c8da560 | 14863 | |
ab77a036 RS |
14864 | static void |
14865 | vr4130_align_insns (void) | |
b875d2ee | 14866 | { |
ab77a036 RS |
14867 | struct mips_sim state; |
14868 | rtx insn, subinsn, last, last2, next; | |
14869 | bool aligned_p; | |
b875d2ee | 14870 | |
ab77a036 | 14871 | dfa_start (); |
50d32cf6 | 14872 | |
ab77a036 RS |
14873 | /* LAST is the last instruction before INSN to have a nonzero length. |
14874 | LAST2 is the last such instruction before LAST. */ | |
14875 | last = 0; | |
14876 | last2 = 0; | |
54401342 | 14877 | |
ab77a036 RS |
14878 | /* ALIGNED_P is true if INSN is known to be at an aligned address. */ |
14879 | aligned_p = true; | |
50d32cf6 | 14880 | |
ab77a036 RS |
14881 | mips_sim_init (&state, alloca (state_size ())); |
14882 | for (insn = get_insns (); insn != 0; insn = next) | |
14883 | { | |
14884 | unsigned int length; | |
50d32cf6 | 14885 | |
ab77a036 | 14886 | next = NEXT_INSN (insn); |
c81d6e2a | 14887 | |
ab77a036 RS |
14888 | /* See the comment above vr4130_avoid_branch_rt_conflict for details. |
14889 | This isn't really related to the alignment pass, but we do it on | |
14890 | the fly to avoid a separate instruction walk. */ | |
14891 | vr4130_avoid_branch_rt_conflict (insn); | |
c81d6e2a | 14892 | |
ab77a036 RS |
14893 | if (USEFUL_INSN_P (insn)) |
14894 | FOR_EACH_SUBINSN (subinsn, insn) | |
14895 | { | |
14896 | mips_sim_wait_insn (&state, subinsn); | |
c81d6e2a | 14897 | |
ab77a036 RS |
14898 | /* If we want this instruction to issue in parallel with the |
14899 | previous one, make sure that the previous instruction is | |
14900 | aligned. There are several reasons why this isn't worthwhile | |
14901 | when the second instruction is a call: | |
5ce6f47b | 14902 | |
ab77a036 RS |
14903 | - Calls are less likely to be performance critical, |
14904 | - There's a good chance that the delay slot can execute | |
14905 | in parallel with the call. | |
14906 | - The return address would then be unaligned. | |
4767c570 | 14907 | |
ab77a036 RS |
14908 | In general, if we're going to insert a nop between instructions |
14909 | X and Y, it's better to insert it immediately after X. That | |
14910 | way, if the nop makes Y aligned, it will also align any labels | |
14911 | between X and Y. */ | |
14912 | if (state.insns_left != state.issue_rate | |
14913 | && !CALL_P (subinsn)) | |
14914 | { | |
14915 | if (subinsn == SEQ_BEGIN (insn) && aligned_p) | |
14916 | { | |
14917 | /* SUBINSN is the first instruction in INSN and INSN is | |
14918 | aligned. We want to align the previous instruction | |
14919 | instead, so insert a nop between LAST2 and LAST. | |
8f2e3902 | 14920 | |
ab77a036 RS |
14921 | Note that LAST could be either a single instruction |
14922 | or a branch with a delay slot. In the latter case, | |
14923 | LAST, like INSN, is already aligned, but the delay | |
14924 | slot must have some extra delay that stops it from | |
14925 | issuing at the same time as the branch. We therefore | |
14926 | insert a nop before the branch in order to align its | |
14927 | delay slot. */ | |
14928 | emit_insn_after (gen_nop (), last2); | |
14929 | aligned_p = false; | |
14930 | } | |
14931 | else if (subinsn != SEQ_BEGIN (insn) && !aligned_p) | |
14932 | { | |
14933 | /* SUBINSN is the delay slot of INSN, but INSN is | |
14934 | currently unaligned. Insert a nop between | |
14935 | LAST and INSN to align it. */ | |
14936 | emit_insn_after (gen_nop (), last); | |
14937 | aligned_p = true; | |
14938 | } | |
14939 | } | |
14940 | mips_sim_issue_insn (&state, subinsn); | |
14941 | } | |
14942 | mips_sim_finish_insn (&state, insn); | |
06a4ab70 | 14943 | |
ab77a036 RS |
14944 | /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ |
14945 | length = get_attr_length (insn); | |
14946 | if (length > 0) | |
14947 | { | |
14948 | /* If the instruction is an asm statement or multi-instruction | |
14949 | mips.md patern, the length is only an estimate. Insert an | |
14950 | 8 byte alignment after it so that the following instructions | |
14951 | can be handled correctly. */ | |
14952 | if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) | |
14953 | && (recog_memoized (insn) < 0 || length >= 8)) | |
14954 | { | |
14955 | next = emit_insn_after (gen_align (GEN_INT (3)), insn); | |
14956 | next = NEXT_INSN (next); | |
14957 | mips_sim_next_cycle (&state); | |
14958 | aligned_p = true; | |
14959 | } | |
14960 | else if (length & 4) | |
14961 | aligned_p = !aligned_p; | |
14962 | last2 = last; | |
14963 | last = insn; | |
14964 | } | |
4ca1f68f | 14965 | |
ab77a036 RS |
14966 | /* See whether INSN is an aligned label. */ |
14967 | if (LABEL_P (insn) && label_to_alignment (insn) >= 3) | |
14968 | aligned_p = true; | |
14969 | } | |
14970 | dfa_finish (); | |
14971 | } | |
14972 | \f | |
a35de342 RS |
14973 | /* This structure records that the current function has a LO_SUM |
14974 | involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is | |
14975 | the largest offset applied to BASE by all such LO_SUMs. */ | |
14976 | struct mips_lo_sum_offset { | |
14977 | rtx base; | |
14978 | HOST_WIDE_INT offset; | |
14979 | }; | |
14980 | ||
14981 | /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ | |
14982 | ||
14983 | static hashval_t | |
14984 | mips_hash_base (rtx base) | |
14985 | { | |
14986 | int do_not_record_p; | |
14987 | ||
14988 | return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); | |
14989 | } | |
14990 | ||
14991 | /* Hash-table callbacks for mips_lo_sum_offsets. */ | |
14992 | ||
14993 | static hashval_t | |
14994 | mips_lo_sum_offset_hash (const void *entry) | |
14995 | { | |
14996 | return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base); | |
14997 | } | |
14998 | ||
14999 | static int | |
15000 | mips_lo_sum_offset_eq (const void *entry, const void *value) | |
15001 | { | |
15002 | return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base, | |
15003 | (const_rtx) value); | |
15004 | } | |
15005 | ||
15006 | /* Look up symbolic constant X in HTAB, which is a hash table of | |
15007 | mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be | |
15008 | paired with a recorded LO_SUM, otherwise record X in the table. */ | |
15009 | ||
15010 | static bool | |
15011 | mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option) | |
15012 | { | |
15013 | rtx base, offset; | |
15014 | void **slot; | |
15015 | struct mips_lo_sum_offset *entry; | |
15016 | ||
15017 | /* Split X into a base and offset. */ | |
15018 | split_const (x, &base, &offset); | |
15019 | if (UNSPEC_ADDRESS_P (base)) | |
15020 | base = UNSPEC_ADDRESS (base); | |
15021 | ||
15022 | /* Look up the base in the hash table. */ | |
15023 | slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option); | |
15024 | if (slot == NULL) | |
15025 | return false; | |
15026 | ||
15027 | entry = (struct mips_lo_sum_offset *) *slot; | |
15028 | if (option == INSERT) | |
15029 | { | |
15030 | if (entry == NULL) | |
15031 | { | |
15032 | entry = XNEW (struct mips_lo_sum_offset); | |
15033 | entry->base = base; | |
15034 | entry->offset = INTVAL (offset); | |
15035 | *slot = entry; | |
15036 | } | |
15037 | else | |
15038 | { | |
15039 | if (INTVAL (offset) > entry->offset) | |
15040 | entry->offset = INTVAL (offset); | |
15041 | } | |
15042 | } | |
15043 | return INTVAL (offset) <= entry->offset; | |
15044 | } | |
15045 | ||
15046 | /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table. | |
15047 | Record every LO_SUM in *LOC. */ | |
15048 | ||
15049 | static int | |
15050 | mips_record_lo_sum (rtx *loc, void *data) | |
15051 | { | |
15052 | if (GET_CODE (*loc) == LO_SUM) | |
15053 | mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT); | |
15054 | return 0; | |
15055 | } | |
15056 | ||
15057 | /* Return true if INSN is a SET of an orphaned high-part relocation. | |
15058 | HTAB is a hash table of mips_lo_sum_offsets that describes all the | |
15059 | LO_SUMs in the current function. */ | |
15060 | ||
15061 | static bool | |
15062 | mips_orphaned_high_part_p (htab_t htab, rtx insn) | |
15063 | { | |
15064 | enum mips_symbol_type type; | |
15065 | rtx x, set; | |
15066 | ||
15067 | set = single_set (insn); | |
15068 | if (set) | |
15069 | { | |
15070 | /* Check for %his. */ | |
15071 | x = SET_SRC (set); | |
15072 | if (GET_CODE (x) == HIGH | |
15073 | && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) | |
15074 | return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); | |
15075 | ||
15076 | /* Check for local %gots (and %got_pages, which is redundant but OK). */ | |
15077 | if (GET_CODE (x) == UNSPEC | |
15078 | && XINT (x, 1) == UNSPEC_LOAD_GOT | |
15079 | && mips_symbolic_constant_p (XVECEXP (x, 0, 1), | |
15080 | SYMBOL_CONTEXT_LEA, &type) | |
15081 | && type == SYMBOL_GOTOFF_PAGE) | |
15082 | return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT); | |
15083 | } | |
15084 | return false; | |
15085 | } | |
15086 | ||
15087 | /* Subroutine of mips_reorg_process_insns. If there is a hazard between | |
15088 | INSN and a previous instruction, avoid it by inserting nops after | |
ab77a036 | 15089 | instruction AFTER. |
308cd611 | 15090 | |
ab77a036 RS |
15091 | *DELAYED_REG and *HILO_DELAY describe the hazards that apply at |
15092 | this point. If *DELAYED_REG is non-null, INSN must wait a cycle | |
15093 | before using the value of that register. *HILO_DELAY counts the | |
15094 | number of instructions since the last hilo hazard (that is, | |
65239d20 | 15095 | the number of instructions since the last MFLO or MFHI). |
4ca1f68f | 15096 | |
ab77a036 RS |
15097 | After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY |
15098 | for the next instruction. | |
4ca1f68f | 15099 | |
ab77a036 | 15100 | LO_REG is an rtx for the LO register, used in dependence checking. */ |
4ca1f68f | 15101 | |
ab77a036 RS |
15102 | static void |
15103 | mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay, | |
15104 | rtx *delayed_reg, rtx lo_reg) | |
15105 | { | |
15106 | rtx pattern, set; | |
dbc90b65 | 15107 | int nops, ninsns; |
06a4ab70 | 15108 | |
ab77a036 | 15109 | pattern = PATTERN (insn); |
4ca1f68f | 15110 | |
ab77a036 RS |
15111 | /* Do not put the whole function in .set noreorder if it contains |
15112 | an asm statement. We don't know whether there will be hazards | |
15113 | between the asm statement and the gcc-generated code. */ | |
15114 | if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0) | |
15115 | cfun->machine->all_noreorder_p = false; | |
4ca1f68f | 15116 | |
ab77a036 RS |
15117 | /* Ignore zero-length instructions (barriers and the like). */ |
15118 | ninsns = get_attr_length (insn) / 4; | |
15119 | if (ninsns == 0) | |
15120 | return; | |
4ca1f68f | 15121 | |
ab77a036 RS |
15122 | /* Work out how many nops are needed. Note that we only care about |
15123 | registers that are explicitly mentioned in the instruction's pattern. | |
15124 | It doesn't matter that calls use the argument registers or that they | |
15125 | clobber hi and lo. */ | |
15126 | if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) | |
15127 | nops = 2 - *hilo_delay; | |
15128 | else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) | |
15129 | nops = 1; | |
15130 | else | |
15131 | nops = 0; | |
4ca1f68f | 15132 | |
ab77a036 RS |
15133 | /* Insert the nops between this instruction and the previous one. |
15134 | Each new nop takes us further from the last hilo hazard. */ | |
15135 | *hilo_delay += nops; | |
15136 | while (nops-- > 0) | |
15137 | emit_insn_after (gen_hazard_nop (), after); | |
4ca1f68f | 15138 | |
ab77a036 RS |
15139 | /* Set up the state for the next instruction. */ |
15140 | *hilo_delay += ninsns; | |
15141 | *delayed_reg = 0; | |
15142 | if (INSN_CODE (insn) >= 0) | |
15143 | switch (get_attr_hazard (insn)) | |
15144 | { | |
15145 | case HAZARD_NONE: | |
15146 | break; | |
21c425ee | 15147 | |
ab77a036 RS |
15148 | case HAZARD_HILO: |
15149 | *hilo_delay = 0; | |
15150 | break; | |
4ca1f68f | 15151 | |
ab77a036 | 15152 | case HAZARD_DELAY: |
dbc90b65 RS |
15153 | set = single_set (insn); |
15154 | gcc_assert (set); | |
ab77a036 RS |
15155 | *delayed_reg = SET_DEST (set); |
15156 | break; | |
15157 | } | |
15158 | } | |
4ca1f68f | 15159 | |
ab77a036 | 15160 | /* Go through the instruction stream and insert nops where necessary. |
a35de342 RS |
15161 | Also delete any high-part relocations whose partnering low parts |
15162 | are now all dead. See if the whole function can then be put into | |
15163 | .set noreorder and .set nomacro. */ | |
06a4ab70 | 15164 | |
ab77a036 | 15165 | static void |
a35de342 | 15166 | mips_reorg_process_insns (void) |
ab77a036 | 15167 | { |
a35de342 RS |
15168 | rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg; |
15169 | int hilo_delay; | |
15170 | htab_t htab; | |
1823bf53 | 15171 | |
ab77a036 RS |
15172 | /* Force all instructions to be split into their final form. */ |
15173 | split_all_insns_noflow (); | |
1823bf53 | 15174 | |
ab77a036 RS |
15175 | /* Recalculate instruction lengths without taking nops into account. */ |
15176 | cfun->machine->ignore_hazard_length_p = true; | |
15177 | shorten_branches (get_insns ()); | |
1823bf53 | 15178 | |
ab77a036 | 15179 | cfun->machine->all_noreorder_p = true; |
118ea793 | 15180 | |
08d0963a RS |
15181 | /* We don't track MIPS16 PC-relative offsets closely enough to make |
15182 | a good job of "set .noreorder" code in MIPS16 mode. */ | |
15183 | if (TARGET_MIPS16) | |
15184 | cfun->machine->all_noreorder_p = false; | |
15185 | ||
a35de342 RS |
15186 | /* Code that doesn't use explicit relocs can't be ".set nomacro". */ |
15187 | if (!TARGET_EXPLICIT_RELOCS) | |
15188 | cfun->machine->all_noreorder_p = false; | |
15189 | ||
ab77a036 RS |
15190 | /* Profiled functions can't be all noreorder because the profiler |
15191 | support uses assembler macros. */ | |
e3b5732b | 15192 | if (crtl->profile) |
ab77a036 | 15193 | cfun->machine->all_noreorder_p = false; |
118ea793 | 15194 | |
0eda4033 CM |
15195 | /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder |
15196 | because we rely on the assembler to work around some errata. */ | |
15197 | if (TARGET_FIX_VR4120 || TARGET_FIX_24K) | |
ab77a036 | 15198 | cfun->machine->all_noreorder_p = false; |
118ea793 | 15199 | |
65239d20 RS |
15200 | /* The same is true for -mfix-vr4130 if we might generate MFLO or |
15201 | MFHI instructions. Note that we avoid using MFLO and MFHI if | |
15202 | the VR4130 MACC and DMACC instructions are available instead; | |
ab77a036 RS |
15203 | see the *mfhilo_{si,di}_macc patterns. */ |
15204 | if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI) | |
15205 | cfun->machine->all_noreorder_p = false; | |
118ea793 | 15206 | |
a35de342 RS |
15207 | htab = htab_create (37, mips_lo_sum_offset_hash, |
15208 | mips_lo_sum_offset_eq, free); | |
15209 | ||
15210 | /* Make a first pass over the instructions, recording all the LO_SUMs. */ | |
15211 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
15212 | FOR_EACH_SUBINSN (subinsn, insn) | |
006b29ab | 15213 | if (USEFUL_INSN_P (subinsn)) |
a35de342 RS |
15214 | for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab); |
15215 | ||
ab77a036 RS |
15216 | last_insn = 0; |
15217 | hilo_delay = 2; | |
15218 | delayed_reg = 0; | |
15219 | lo_reg = gen_rtx_REG (SImode, LO_REGNUM); | |
32041385 | 15220 | |
a35de342 RS |
15221 | /* Make a second pass over the instructions. Delete orphaned |
15222 | high-part relocations or turn them into NOPs. Avoid hazards | |
15223 | by inserting NOPs. */ | |
15224 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
15225 | { | |
15226 | next_insn = NEXT_INSN (insn); | |
006b29ab | 15227 | if (USEFUL_INSN_P (insn)) |
a35de342 RS |
15228 | { |
15229 | if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
15230 | { | |
15231 | /* If we find an orphaned high-part relocation in a delay | |
15232 | slot, it's easier to turn that instruction into a NOP than | |
15233 | to delete it. The delay slot will be a NOP either way. */ | |
15234 | FOR_EACH_SUBINSN (subinsn, insn) | |
15235 | if (INSN_P (subinsn)) | |
15236 | { | |
15237 | if (mips_orphaned_high_part_p (htab, subinsn)) | |
15238 | { | |
15239 | PATTERN (subinsn) = gen_nop (); | |
15240 | INSN_CODE (subinsn) = CODE_FOR_nop; | |
15241 | } | |
15242 | mips_avoid_hazard (last_insn, subinsn, &hilo_delay, | |
15243 | &delayed_reg, lo_reg); | |
15244 | } | |
15245 | last_insn = insn; | |
15246 | } | |
15247 | else | |
15248 | { | |
15249 | /* INSN is a single instruction. Delete it if it's an | |
15250 | orphaned high-part relocation. */ | |
15251 | if (mips_orphaned_high_part_p (htab, insn)) | |
15252 | delete_insn (insn); | |
4d210b07 RS |
15253 | /* Also delete cache barriers if the last instruction |
15254 | was an annulled branch. INSN will not be speculatively | |
15255 | executed. */ | |
15256 | else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier | |
15257 | && last_insn | |
9e187b31 | 15258 | && JUMP_P (SEQ_BEGIN (last_insn)) |
4d210b07 RS |
15259 | && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn))) |
15260 | delete_insn (insn); | |
a35de342 RS |
15261 | else |
15262 | { | |
15263 | mips_avoid_hazard (last_insn, insn, &hilo_delay, | |
15264 | &delayed_reg, lo_reg); | |
15265 | last_insn = insn; | |
15266 | } | |
15267 | } | |
15268 | } | |
15269 | } | |
32041385 | 15270 | |
a35de342 | 15271 | htab_delete (htab); |
ab77a036 RS |
15272 | } |
15273 | ||
0c433c31 RS |
15274 | /* If we are using a GOT, but have not decided to use a global pointer yet, |
15275 | see whether we need one to implement long branches. Convert the ghost | |
15276 | global-pointer instructions into real ones if so. */ | |
15277 | ||
15278 | static bool | |
15279 | mips_expand_ghost_gp_insns (void) | |
15280 | { | |
15281 | rtx insn; | |
15282 | int normal_length; | |
15283 | ||
15284 | /* Quick exit if we already know that we will or won't need a | |
15285 | global pointer. */ | |
15286 | if (!TARGET_USE_GOT | |
15287 | || cfun->machine->global_pointer == INVALID_REGNUM | |
15288 | || mips_must_initialize_gp_p ()) | |
15289 | return false; | |
15290 | ||
15291 | shorten_branches (get_insns ()); | |
15292 | ||
15293 | /* Look for a branch that is longer than normal. The normal length for | |
15294 | non-MIPS16 branches is 8, because the length includes the delay slot. | |
15295 | It is 4 for MIPS16, because MIPS16 branches are extended instructions, | |
15296 | but they have no delay slot. */ | |
15297 | normal_length = (TARGET_MIPS16 ? 4 : 8); | |
15298 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
15299 | if (JUMP_P (insn) | |
15300 | && USEFUL_INSN_P (insn) | |
15301 | && get_attr_length (insn) > normal_length) | |
15302 | break; | |
15303 | ||
15304 | if (insn == NULL_RTX) | |
15305 | return false; | |
15306 | ||
15307 | /* We've now established that we need $gp. */ | |
15308 | cfun->machine->must_initialize_gp_p = true; | |
15309 | split_all_insns_noflow (); | |
15310 | ||
15311 | return true; | |
15312 | } | |
15313 | ||
b53da244 AN |
15314 | /* Subroutine of mips_reorg to manage passes that require DF. */ |
15315 | ||
15316 | static void | |
15317 | mips_df_reorg (void) | |
15318 | { | |
15319 | /* Create def-use chains. */ | |
15320 | df_set_flags (DF_EQ_NOTES); | |
15321 | df_chain_add_problem (DF_UD_CHAIN); | |
15322 | df_analyze (); | |
15323 | ||
15324 | if (TARGET_RELAX_PIC_CALLS) | |
15325 | mips_annotate_pic_calls (); | |
15326 | ||
15327 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE) | |
15328 | r10k_insert_cache_barriers (); | |
15329 | ||
15330 | df_finish_pass (false); | |
15331 | } | |
15332 | ||
ab77a036 RS |
15333 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ |
15334 | ||
15335 | static void | |
15336 | mips_reorg (void) | |
32041385 | 15337 | { |
b53da244 AN |
15338 | /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during |
15339 | insn splitting in mips16_lay_out_constants, DF insn info is only kept up | |
15340 | to date if the CFG is available. */ | |
15341 | if (mips_cfg_in_reorg ()) | |
15342 | compute_bb_for_insn (); | |
ab77a036 | 15343 | mips16_lay_out_constants (); |
b53da244 AN |
15344 | if (mips_cfg_in_reorg ()) |
15345 | { | |
15346 | mips_df_reorg (); | |
15347 | free_bb_for_insn (); | |
15348 | } | |
15349 | ||
c7789bfb | 15350 | if (optimize > 0 && flag_delayed_branch) |
a35de342 RS |
15351 | dbr_schedule (get_insns ()); |
15352 | mips_reorg_process_insns (); | |
08d0963a RS |
15353 | if (!TARGET_MIPS16 |
15354 | && TARGET_EXPLICIT_RELOCS | |
15355 | && TUNE_MIPS4130 | |
15356 | && TARGET_VR4130_ALIGN) | |
a35de342 | 15357 | vr4130_align_insns (); |
0c433c31 RS |
15358 | if (mips_expand_ghost_gp_insns ()) |
15359 | /* The expansion could invalidate some of the VR4130 alignment | |
15360 | optimizations, but this should be an extremely rare case anyhow. */ | |
15361 | mips_reorg_process_insns (); | |
ab77a036 RS |
15362 | } |
15363 | \f | |
15364 | /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text | |
15365 | in order to avoid duplicating too much logic from elsewhere. */ | |
32041385 | 15366 | |
ab77a036 RS |
15367 | static void |
15368 | mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | |
15369 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
15370 | tree function) | |
15371 | { | |
0a2aaacc | 15372 | rtx this_rtx, temp1, temp2, insn, fnaddr; |
ab77a036 RS |
15373 | bool use_sibcall_p; |
15374 | ||
15375 | /* Pretend to be a post-reload pass while generating rtl. */ | |
15376 | reload_completed = 1; | |
15377 | ||
15378 | /* Mark the end of the (empty) prologue. */ | |
15379 | emit_note (NOTE_INSN_PROLOGUE_END); | |
15380 | ||
15381 | /* Determine if we can use a sibcall to call FUNCTION directly. */ | |
15382 | fnaddr = XEXP (DECL_RTL (function), 0); | |
15383 | use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL) | |
15384 | && const_call_insn_operand (fnaddr, Pmode)); | |
15385 | ||
15386 | /* Determine if we need to load FNADDR from the GOT. */ | |
08d0963a RS |
15387 | if (!use_sibcall_p |
15388 | && (mips_got_symbol_type_p | |
15389 | (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA)))) | |
15390 | { | |
15391 | /* Pick a global pointer. Use a call-clobbered register if | |
15392 | TARGET_CALL_SAVED_GP. */ | |
15393 | cfun->machine->global_pointer | |
15394 | = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM; | |
0c433c31 | 15395 | cfun->machine->must_initialize_gp_p = true; |
08d0963a | 15396 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); |
ab77a036 | 15397 | |
08d0963a RS |
15398 | /* Set up the global pointer for n32 or n64 abicalls. */ |
15399 | mips_emit_loadgp (); | |
15400 | } | |
ab77a036 RS |
15401 | |
15402 | /* We need two temporary registers in some cases. */ | |
15403 | temp1 = gen_rtx_REG (Pmode, 2); | |
15404 | temp2 = gen_rtx_REG (Pmode, 3); | |
15405 | ||
15406 | /* Find out which register contains the "this" pointer. */ | |
15407 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
0a2aaacc | 15408 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); |
ab77a036 | 15409 | else |
0a2aaacc | 15410 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); |
ab77a036 | 15411 | |
0a2aaacc | 15412 | /* Add DELTA to THIS_RTX. */ |
ab77a036 RS |
15413 | if (delta != 0) |
15414 | { | |
15415 | rtx offset = GEN_INT (delta); | |
15416 | if (!SMALL_OPERAND (delta)) | |
15417 | { | |
15418 | mips_emit_move (temp1, offset); | |
15419 | offset = temp1; | |
15420 | } | |
0a2aaacc | 15421 | emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); |
ab77a036 RS |
15422 | } |
15423 | ||
0a2aaacc | 15424 | /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ |
ab77a036 RS |
15425 | if (vcall_offset != 0) |
15426 | { | |
15427 | rtx addr; | |
15428 | ||
0a2aaacc KG |
15429 | /* Set TEMP1 to *THIS_RTX. */ |
15430 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); | |
ab77a036 | 15431 | |
0a2aaacc | 15432 | /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ |
ab77a036 RS |
15433 | addr = mips_add_offset (temp2, temp1, vcall_offset); |
15434 | ||
0a2aaacc | 15435 | /* Load the offset and add it to THIS_RTX. */ |
ab77a036 | 15436 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); |
0a2aaacc | 15437 | emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); |
ab77a036 RS |
15438 | } |
15439 | ||
15440 | /* Jump to the target function. Use a sibcall if direct jumps are | |
15441 | allowed, otherwise load the address into a register first. */ | |
15442 | if (use_sibcall_p) | |
15443 | { | |
15444 | insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); | |
15445 | SIBLING_CALL_P (insn) = 1; | |
15446 | } | |
15447 | else | |
15448 | { | |
65239d20 | 15449 | /* This is messy. GAS treats "la $25,foo" as part of a call |
ab77a036 RS |
15450 | sequence and may allow a global "foo" to be lazily bound. |
15451 | The general move patterns therefore reject this combination. | |
15452 | ||
15453 | In this context, lazy binding would actually be OK | |
15454 | for TARGET_CALL_CLOBBERED_GP, but it's still wrong for | |
15455 | TARGET_CALL_SAVED_GP; see mips_load_call_address. | |
15456 | We must therefore load the address via a temporary | |
15457 | register if mips_dangerous_for_la25_p. | |
15458 | ||
08d0963a RS |
15459 | If we jump to the temporary register rather than $25, |
15460 | the assembler can use the move insn to fill the jump's | |
15461 | delay slot. | |
15462 | ||
15463 | We can use the same technique for MIPS16 code, where $25 | |
15464 | is not a valid JR register. */ | |
ab77a036 | 15465 | if (TARGET_USE_PIC_FN_ADDR_REG |
08d0963a | 15466 | && !TARGET_MIPS16 |
ab77a036 RS |
15467 | && !mips_dangerous_for_la25_p (fnaddr)) |
15468 | temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
08d0963a | 15469 | mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr); |
ab77a036 RS |
15470 | |
15471 | if (TARGET_USE_PIC_FN_ADDR_REG | |
15472 | && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM) | |
15473 | mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1); | |
15474 | emit_jump_insn (gen_indirect_jump (temp1)); | |
15475 | } | |
15476 | ||
15477 | /* Run just enough of rest_of_compilation. This sequence was | |
15478 | "borrowed" from alpha.c. */ | |
15479 | insn = get_insns (); | |
15480 | insn_locators_alloc (); | |
15481 | split_all_insns_noflow (); | |
15482 | mips16_lay_out_constants (); | |
15483 | shorten_branches (insn); | |
15484 | final_start_function (insn, file, 1); | |
15485 | final (insn, file, 1); | |
15486 | final_end_function (); | |
15487 | ||
15488 | /* Clean up the vars set above. Note that final_end_function resets | |
15489 | the global pointer for us. */ | |
15490 | reload_completed = 0; | |
15491 | } | |
15492 | \f | |
65239d20 | 15493 | /* The last argument passed to mips_set_mips16_mode, or negative if the |
e32ea2d1 | 15494 | function hasn't been called yet. */ |
60730ade | 15495 | static int was_mips16_p = -1; |
ab77a036 RS |
15496 | |
15497 | /* Set up the target-dependent global state so that it matches the | |
15498 | current function's ISA mode. */ | |
15499 | ||
15500 | static void | |
15501 | mips_set_mips16_mode (int mips16_p) | |
15502 | { | |
e32ea2d1 | 15503 | if (mips16_p == was_mips16_p) |
ab77a036 RS |
15504 | return; |
15505 | ||
15506 | /* Restore base settings of various flags. */ | |
15507 | target_flags = mips_base_target_flags; | |
ab77a036 RS |
15508 | flag_schedule_insns = mips_base_schedule_insns; |
15509 | flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition; | |
15510 | flag_move_loop_invariants = mips_base_move_loop_invariants; | |
15511 | align_loops = mips_base_align_loops; | |
15512 | align_jumps = mips_base_align_jumps; | |
15513 | align_functions = mips_base_align_functions; | |
15514 | ||
15515 | if (mips16_p) | |
15516 | { | |
65239d20 | 15517 | /* Switch to MIPS16 mode. */ |
ab77a036 RS |
15518 | target_flags |= MASK_MIPS16; |
15519 | ||
15520 | /* Don't run the scheduler before reload, since it tends to | |
15521 | increase register pressure. */ | |
15522 | flag_schedule_insns = 0; | |
15523 | ||
65239d20 | 15524 | /* Don't do hot/cold partitioning. mips16_lay_out_constants expects |
ab77a036 RS |
15525 | the whole function to be in a single section. */ |
15526 | flag_reorder_blocks_and_partition = 0; | |
15527 | ||
15528 | /* Don't move loop invariants, because it tends to increase | |
15529 | register pressure. It also introduces an extra move in cases | |
15530 | where the constant is the first operand in a two-operand binary | |
15531 | instruction, or when it forms a register argument to a functon | |
15532 | call. */ | |
15533 | flag_move_loop_invariants = 0; | |
15534 | ||
08d0963a | 15535 | target_flags |= MASK_EXPLICIT_RELOCS; |
ab77a036 | 15536 | |
65239d20 RS |
15537 | /* Experiments suggest we get the best overall section-anchor |
15538 | results from using the range of an unextended LW or SW. Code | |
15539 | that makes heavy use of byte or short accesses can do better | |
15540 | with ranges of 0...31 and 0...63 respectively, but most code is | |
15541 | sensitive to the range of LW and SW instead. */ | |
ab77a036 RS |
15542 | targetm.min_anchor_offset = 0; |
15543 | targetm.max_anchor_offset = 127; | |
15544 | ||
2c5bfdf7 AN |
15545 | targetm.const_anchor = 0; |
15546 | ||
b53da244 AN |
15547 | /* MIPS16 has no BAL instruction. */ |
15548 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
15549 | ||
a2ccf3c2 RS |
15550 | /* The R4000 errata don't apply to any known MIPS16 cores. |
15551 | It's simpler to make the R4000 fixes and MIPS16 mode | |
15552 | mutually exclusive. */ | |
15553 | target_flags &= ~MASK_FIX_R4000; | |
15554 | ||
08d0963a RS |
15555 | if (flag_pic && !TARGET_OLDABI) |
15556 | sorry ("MIPS16 PIC for ABIs other than o32 and o64"); | |
15557 | ||
15558 | if (TARGET_XGOT) | |
15559 | sorry ("MIPS16 -mxgot code"); | |
d375fd5e RS |
15560 | |
15561 | if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI) | |
15562 | sorry ("hard-float MIPS16 code for ABIs other than o32 and o64"); | |
ab77a036 RS |
15563 | } |
15564 | else | |
15565 | { | |
65239d20 | 15566 | /* Switch to normal (non-MIPS16) mode. */ |
ab77a036 RS |
15567 | target_flags &= ~MASK_MIPS16; |
15568 | ||
ab77a036 RS |
15569 | /* Provide default values for align_* for 64-bit targets. */ |
15570 | if (TARGET_64BIT) | |
15571 | { | |
15572 | if (align_loops == 0) | |
15573 | align_loops = 8; | |
15574 | if (align_jumps == 0) | |
15575 | align_jumps = 8; | |
15576 | if (align_functions == 0) | |
15577 | align_functions = 8; | |
15578 | } | |
1823bf53 | 15579 | |
ab77a036 RS |
15580 | targetm.min_anchor_offset = -32768; |
15581 | targetm.max_anchor_offset = 32767; | |
2c5bfdf7 AN |
15582 | |
15583 | targetm.const_anchor = 0x8000; | |
ab77a036 | 15584 | } |
1823bf53 | 15585 | |
65239d20 | 15586 | /* (Re)initialize MIPS target internals for new ISA. */ |
ab77a036 | 15587 | mips_init_relocs (); |
1823bf53 | 15588 | |
5aa62249 RS |
15589 | if (mips16_p) |
15590 | { | |
15591 | if (!mips16_globals) | |
15592 | mips16_globals = save_target_globals (); | |
15593 | else | |
15594 | restore_target_globals (mips16_globals); | |
15595 | } | |
15596 | else | |
15597 | restore_target_globals (&default_target_globals); | |
32041385 | 15598 | |
65239d20 | 15599 | was_mips16_p = mips16_p; |
ab77a036 | 15600 | } |
1823bf53 | 15601 | |
ab77a036 RS |
15602 | /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current |
15603 | function should use the MIPS16 ISA and switch modes accordingly. */ | |
15604 | ||
15605 | static void | |
15606 | mips_set_current_function (tree fndecl) | |
1823bf53 | 15607 | { |
ab77a036 RS |
15608 | mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl)); |
15609 | } | |
15610 | \f | |
15611 | /* Allocate a chunk of memory for per-function machine-dependent data. */ | |
65239d20 | 15612 | |
ab77a036 RS |
15613 | static struct machine_function * |
15614 | mips_init_machine_status (void) | |
15615 | { | |
a9429e29 | 15616 | return ggc_alloc_cleared_machine_function (); |
ab77a036 | 15617 | } |
06a4ab70 | 15618 | |
ab77a036 RS |
15619 | /* Return the processor associated with the given ISA level, or null |
15620 | if the ISA isn't valid. */ | |
ff55fb9c | 15621 | |
ab77a036 RS |
15622 | static const struct mips_cpu_info * |
15623 | mips_cpu_info_from_isa (int isa) | |
ff55fb9c | 15624 | { |
ab77a036 | 15625 | unsigned int i; |
ff55fb9c | 15626 | |
ab77a036 RS |
15627 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
15628 | if (mips_cpu_info_table[i].isa == isa) | |
15629 | return mips_cpu_info_table + i; | |
ff55fb9c | 15630 | |
65239d20 | 15631 | return NULL; |
ff55fb9c RS |
15632 | } |
15633 | ||
d371df6f JM |
15634 | /* Return a mips_cpu_info entry determined by an option valued |
15635 | OPT. */ | |
ff55fb9c | 15636 | |
d371df6f JM |
15637 | static const struct mips_cpu_info * |
15638 | mips_cpu_info_from_opt (int opt) | |
ab77a036 | 15639 | { |
d371df6f JM |
15640 | switch (opt) |
15641 | { | |
15642 | case MIPS_ARCH_OPTION_FROM_ABI: | |
15643 | /* 'from-abi' selects the most compatible architecture for the | |
15644 | given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit | |
15645 | ABIs. For the EABIs, we have to decide whether we're using | |
15646 | the 32-bit or 64-bit version. */ | |
15647 | return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1 | |
15648 | : ABI_NEEDS_64BIT_REGS ? 3 | |
15649 | : (TARGET_64BIT ? 3 : 1)); | |
ab77a036 | 15650 | |
d371df6f JM |
15651 | case MIPS_ARCH_OPTION_NATIVE: |
15652 | gcc_unreachable (); | |
ab77a036 | 15653 | |
d371df6f JM |
15654 | default: |
15655 | return &mips_cpu_info_table[opt]; | |
15656 | } | |
ff55fb9c RS |
15657 | } |
15658 | ||
d371df6f JM |
15659 | /* Return a default mips_cpu_info entry, given that no -march= option |
15660 | was explicitly specified. */ | |
ab77a036 RS |
15661 | |
15662 | static const struct mips_cpu_info * | |
d371df6f | 15663 | mips_default_arch (void) |
06a4ab70 | 15664 | { |
872dab53 | 15665 | #if defined (MIPS_CPU_STRING_DEFAULT) |
ab77a036 | 15666 | unsigned int i; |
ab77a036 | 15667 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
d371df6f | 15668 | if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0) |
ab77a036 | 15669 | return mips_cpu_info_table + i; |
d371df6f | 15670 | gcc_unreachable (); |
872dab53 RS |
15671 | #elif defined (MIPS_ISA_DEFAULT) |
15672 | return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT); | |
d371df6f JM |
15673 | #else |
15674 | /* 'from-abi' makes a good default: you get whatever the ABI | |
15675 | requires. */ | |
15676 | return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI); | |
15677 | #endif | |
ab77a036 RS |
15678 | } |
15679 | ||
ab77a036 RS |
15680 | /* Set up globals to generate code for the ISA or processor |
15681 | described by INFO. */ | |
15682 | ||
15683 | static void | |
15684 | mips_set_architecture (const struct mips_cpu_info *info) | |
15685 | { | |
15686 | if (info != 0) | |
f9e4a411 | 15687 | { |
ab77a036 RS |
15688 | mips_arch_info = info; |
15689 | mips_arch = info->cpu; | |
15690 | mips_isa = info->isa; | |
f9e4a411 | 15691 | } |
ab77a036 | 15692 | } |
f9e4a411 | 15693 | |
ab77a036 RS |
15694 | /* Likewise for tuning. */ |
15695 | ||
15696 | static void | |
15697 | mips_set_tune (const struct mips_cpu_info *info) | |
15698 | { | |
15699 | if (info != 0) | |
1823bf53 | 15700 | { |
ab77a036 RS |
15701 | mips_tune_info = info; |
15702 | mips_tune = info->cpu; | |
1823bf53 | 15703 | } |
ab77a036 | 15704 | } |
ff55fb9c | 15705 | |
525c561d | 15706 | /* Implement TARGET_OPTION_OVERRIDE. */ |
06a4ab70 | 15707 | |
525c561d AS |
15708 | static void |
15709 | mips_option_override (void) | |
06a4ab70 | 15710 | { |
65239d20 | 15711 | int i, start, regno, mode; |
06a4ab70 | 15712 | |
d371df6f JM |
15713 | if (global_options_set.x_mips_isa_option) |
15714 | mips_isa_option_info = &mips_cpu_info_table[mips_isa_option]; | |
15715 | ||
60730ade RS |
15716 | /* Process flags as though we were generating non-MIPS16 code. */ |
15717 | mips_base_mips16 = TARGET_MIPS16; | |
15718 | target_flags &= ~MASK_MIPS16; | |
15719 | ||
ab77a036 RS |
15720 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
15721 | SUBTARGET_OVERRIDE_OPTIONS; | |
15722 | #endif | |
06a4ab70 | 15723 | |
9f946bc1 RS |
15724 | /* -mno-float overrides -mhard-float and -msoft-float. */ |
15725 | if (TARGET_NO_FLOAT) | |
15726 | { | |
15727 | target_flags |= MASK_SOFT_FLOAT_ABI; | |
15728 | target_flags_explicit |= MASK_SOFT_FLOAT_ABI; | |
15729 | } | |
15730 | ||
ac9b0eea RS |
15731 | if (TARGET_FLIP_MIPS16) |
15732 | TARGET_INTERLINK_MIPS16 = 1; | |
15733 | ||
65239d20 | 15734 | /* Set the small data limit. */ |
fa37ed29 | 15735 | mips_small_data_threshold = (global_options_set.x_g_switch_value |
65239d20 RS |
15736 | ? g_switch_value |
15737 | : MIPS_DEFAULT_GVALUE); | |
8f2e3902 | 15738 | |
ab77a036 RS |
15739 | /* The following code determines the architecture and register size. |
15740 | Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()). | |
15741 | The GAS and GCC code should be kept in sync as much as possible. */ | |
06a4ab70 | 15742 | |
d371df6f JM |
15743 | if (global_options_set.x_mips_arch_option) |
15744 | mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option)); | |
06a4ab70 | 15745 | |
65239d20 | 15746 | if (mips_isa_option_info != 0) |
ab77a036 RS |
15747 | { |
15748 | if (mips_arch_info == 0) | |
65239d20 RS |
15749 | mips_set_architecture (mips_isa_option_info); |
15750 | else if (mips_arch_info->isa != mips_isa_option_info->isa) | |
15751 | error ("%<-%s%> conflicts with the other architecture options, " | |
ab77a036 | 15752 | "which specify a %s processor", |
65239d20 | 15753 | mips_isa_option_info->name, |
ab77a036 RS |
15754 | mips_cpu_info_from_isa (mips_arch_info->isa)->name); |
15755 | } | |
06a4ab70 | 15756 | |
ab77a036 | 15757 | if (mips_arch_info == 0) |
d371df6f | 15758 | mips_set_architecture (mips_default_arch ()); |
06a4ab70 | 15759 | |
ab77a036 | 15760 | if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS) |
65239d20 | 15761 | error ("%<-march=%s%> is not compatible with the selected ABI", |
ab77a036 | 15762 | mips_arch_info->name); |
06a4ab70 | 15763 | |
ab77a036 | 15764 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
d371df6f JM |
15765 | if (global_options_set.x_mips_tune_option) |
15766 | mips_set_tune (mips_cpu_info_from_opt (mips_tune_option)); | |
118ea793 | 15767 | |
ab77a036 RS |
15768 | if (mips_tune_info == 0) |
15769 | mips_set_tune (mips_arch_info); | |
118ea793 | 15770 | |
ab77a036 RS |
15771 | if ((target_flags_explicit & MASK_64BIT) != 0) |
15772 | { | |
15773 | /* The user specified the size of the integer registers. Make sure | |
15774 | it agrees with the ABI and ISA. */ | |
15775 | if (TARGET_64BIT && !ISA_HAS_64BIT_REGS) | |
65239d20 | 15776 | error ("%<-mgp64%> used with a 32-bit processor"); |
ab77a036 | 15777 | else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS) |
65239d20 | 15778 | error ("%<-mgp32%> used with a 64-bit ABI"); |
ab77a036 | 15779 | else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS) |
65239d20 | 15780 | error ("%<-mgp64%> used with a 32-bit ABI"); |
ab77a036 RS |
15781 | } |
15782 | else | |
15783 | { | |
15784 | /* Infer the integer register size from the ABI and processor. | |
15785 | Restrict ourselves to 32-bit registers if that's all the | |
15786 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15787 | if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS) | |
15788 | target_flags &= ~MASK_64BIT; | |
15789 | else | |
15790 | target_flags |= MASK_64BIT; | |
118ea793 CF |
15791 | } |
15792 | ||
ab77a036 | 15793 | if ((target_flags_explicit & MASK_FLOAT64) != 0) |
118ea793 | 15794 | { |
65239d20 | 15795 | if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64) |
ab77a036 | 15796 | error ("unsupported combination: %s", "-mfp64 -msingle-float"); |
65239d20 RS |
15797 | else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64) |
15798 | error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float"); | |
15799 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
15800 | { | |
15801 | if (!ISA_HAS_MXHC1) | |
15802 | error ("%<-mgp32%> and %<-mfp64%> can only be combined if" | |
15803 | " the target supports the mfhc1 and mthc1 instructions"); | |
15804 | else if (mips_abi != ABI_32) | |
15805 | error ("%<-mgp32%> and %<-mfp64%> can only be combined when using" | |
15806 | " the o32 ABI"); | |
15807 | } | |
ab77a036 RS |
15808 | } |
15809 | else | |
15810 | { | |
15811 | /* -msingle-float selects 32-bit float registers. Otherwise the | |
15812 | float registers should be the same size as the integer ones. */ | |
15813 | if (TARGET_64BIT && TARGET_DOUBLE_FLOAT) | |
15814 | target_flags |= MASK_FLOAT64; | |
15815 | else | |
15816 | target_flags &= ~MASK_FLOAT64; | |
15817 | } | |
118ea793 | 15818 | |
ab77a036 | 15819 | /* End of code shared with GAS. */ |
118ea793 | 15820 | |
81a478c8 RS |
15821 | /* If a -mlong* option was given, check that it matches the ABI, |
15822 | otherwise infer the -mlong* setting from the other options. */ | |
15823 | if ((target_flags_explicit & MASK_LONG64) != 0) | |
15824 | { | |
15825 | if (TARGET_LONG64) | |
15826 | { | |
15827 | if (mips_abi == ABI_N32) | |
15828 | error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64"); | |
15829 | else if (mips_abi == ABI_32) | |
15830 | error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64"); | |
15831 | else if (mips_abi == ABI_O64 && TARGET_ABICALLS) | |
15832 | /* We have traditionally allowed non-abicalls code to use | |
15833 | an LP64 form of o64. However, it would take a bit more | |
15834 | effort to support the combination of 32-bit GOT entries | |
15835 | and 64-bit pointers, so we treat the abicalls case as | |
15836 | an error. */ | |
15837 | error ("the combination of %qs and %qs is incompatible with %qs", | |
15838 | "-mabi=o64", "-mabicalls", "-mlong64"); | |
15839 | } | |
15840 | else | |
15841 | { | |
15842 | if (mips_abi == ABI_64) | |
15843 | error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32"); | |
15844 | } | |
15845 | } | |
15846 | else | |
ab77a036 RS |
15847 | { |
15848 | if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64) | |
15849 | target_flags |= MASK_LONG64; | |
15850 | else | |
15851 | target_flags &= ~MASK_LONG64; | |
15852 | } | |
118ea793 | 15853 | |
ab77a036 RS |
15854 | if (!TARGET_OLDABI) |
15855 | flag_pcc_struct_return = 0; | |
118ea793 | 15856 | |
65239d20 RS |
15857 | /* Decide which rtx_costs structure to use. */ |
15858 | if (optimize_size) | |
15859 | mips_cost = &mips_rtx_cost_optimize_size; | |
15860 | else | |
15861 | mips_cost = &mips_rtx_cost_data[mips_tune]; | |
15862 | ||
15863 | /* If the user hasn't specified a branch cost, use the processor's | |
15864 | default. */ | |
15865 | if (mips_branch_cost == 0) | |
15866 | mips_branch_cost = mips_cost->branch_cost; | |
15867 | ||
15868 | /* If neither -mbranch-likely nor -mno-branch-likely was given | |
15869 | on the command line, set MASK_BRANCHLIKELY based on the target | |
15870 | architecture and tuning flags. Annulled delay slots are a | |
15871 | size win, so we only consider the processor-specific tuning | |
15872 | for !optimize_size. */ | |
ab77a036 RS |
15873 | if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0) |
15874 | { | |
ab77a036 RS |
15875 | if (ISA_HAS_BRANCHLIKELY |
15876 | && (optimize_size | |
15877 | || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0)) | |
15878 | target_flags |= MASK_BRANCHLIKELY; | |
15879 | else | |
15880 | target_flags &= ~MASK_BRANCHLIKELY; | |
15881 | } | |
15882 | else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) | |
15883 | warning (0, "the %qs architecture does not support branch-likely" | |
15884 | " instructions", mips_arch_info->name); | |
118ea793 | 15885 | |
ab77a036 RS |
15886 | /* The effect of -mabicalls isn't defined for the EABI. */ |
15887 | if (mips_abi == ABI_EABI && TARGET_ABICALLS) | |
15888 | { | |
15889 | error ("unsupported combination: %s", "-mabicalls -mabi=eabi"); | |
15890 | target_flags &= ~MASK_ABICALLS; | |
15891 | } | |
118ea793 | 15892 | |
e21d5757 | 15893 | if (TARGET_ABICALLS_PIC2) |
ab77a036 RS |
15894 | /* We need to set flag_pic for executables as well as DSOs |
15895 | because we may reference symbols that are not defined in | |
15896 | the final executable. (MIPS does not use things like | |
15897 | copy relocs, for example.) | |
118ea793 | 15898 | |
e21d5757 DJ |
15899 | There is a body of code that uses __PIC__ to distinguish |
15900 | between -mabicalls and -mno-abicalls code. The non-__PIC__ | |
15901 | variant is usually appropriate for TARGET_ABICALLS_PIC0, as | |
15902 | long as any indirect jumps use $25. */ | |
ab77a036 | 15903 | flag_pic = 1; |
118ea793 | 15904 | |
ab77a036 RS |
15905 | /* -mvr4130-align is a "speed over size" optimization: it usually produces |
15906 | faster code, but at the expense of more nops. Enable it at -O3 and | |
15907 | above. */ | |
15908 | if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) | |
15909 | target_flags |= MASK_VR4130_ALIGN; | |
118ea793 | 15910 | |
ab77a036 RS |
15911 | /* Prefer a call to memcpy over inline code when optimizing for size, |
15912 | though see MOVE_RATIO in mips.h. */ | |
15913 | if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) | |
15914 | target_flags |= MASK_MEMCPY; | |
118ea793 | 15915 | |
ab77a036 RS |
15916 | /* If we have a nonzero small-data limit, check that the -mgpopt |
15917 | setting is consistent with the other target flags. */ | |
65239d20 | 15918 | if (mips_small_data_threshold > 0) |
ab77a036 RS |
15919 | { |
15920 | if (!TARGET_GPOPT) | |
15921 | { | |
60730ade | 15922 | if (!TARGET_EXPLICIT_RELOCS) |
ab77a036 | 15923 | error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>"); |
118ea793 | 15924 | |
ab77a036 RS |
15925 | TARGET_LOCAL_SDATA = false; |
15926 | TARGET_EXTERN_SDATA = false; | |
15927 | } | |
15928 | else | |
15929 | { | |
15930 | if (TARGET_VXWORKS_RTP) | |
15931 | warning (0, "cannot use small-data accesses for %qs", "-mrtp"); | |
118ea793 | 15932 | |
ab77a036 RS |
15933 | if (TARGET_ABICALLS) |
15934 | warning (0, "cannot use small-data accesses for %qs", | |
15935 | "-mabicalls"); | |
15936 | } | |
15937 | } | |
118ea793 | 15938 | |
ab77a036 RS |
15939 | #ifdef MIPS_TFMODE_FORMAT |
15940 | REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT; | |
15941 | #endif | |
118ea793 | 15942 | |
ab77a036 RS |
15943 | /* Make sure that the user didn't turn off paired single support when |
15944 | MIPS-3D support is requested. */ | |
65239d20 RS |
15945 | if (TARGET_MIPS3D |
15946 | && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT) | |
ab77a036 | 15947 | && !TARGET_PAIRED_SINGLE_FLOAT) |
65239d20 | 15948 | error ("%<-mips3d%> requires %<-mpaired-single%>"); |
118ea793 | 15949 | |
ab77a036 RS |
15950 | /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */ |
15951 | if (TARGET_MIPS3D) | |
15952 | target_flags |= MASK_PAIRED_SINGLE_FLOAT; | |
118ea793 | 15953 | |
ab77a036 RS |
15954 | /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 |
15955 | and TARGET_HARD_FLOAT_ABI are both true. */ | |
15956 | if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) | |
65239d20 RS |
15957 | error ("%qs must be used with %qs", |
15958 | TARGET_MIPS3D ? "-mips3d" : "-mpaired-single", | |
15959 | TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float"); | |
118ea793 | 15960 | |
ab77a036 RS |
15961 | /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is |
15962 | enabled. */ | |
e5a2b69d RS |
15963 | if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE) |
15964 | warning (0, "the %qs architecture does not support paired-single" | |
15965 | " instructions", mips_arch_info->name); | |
118ea793 | 15966 | |
4d210b07 RS |
15967 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE |
15968 | && !TARGET_CACHE_BUILTIN) | |
15969 | { | |
15970 | error ("%qs requires a target that provides the %qs instruction", | |
15971 | "-mr10k-cache-barrier", "cache"); | |
15972 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; | |
15973 | } | |
15974 | ||
ab77a036 RS |
15975 | /* If TARGET_DSPR2, enable MASK_DSP. */ |
15976 | if (TARGET_DSPR2) | |
15977 | target_flags |= MASK_DSP; | |
118ea793 | 15978 | |
082d2ebb RS |
15979 | /* .eh_frame addresses should be the same width as a C pointer. |
15980 | Most MIPS ABIs support only one pointer size, so the assembler | |
15981 | will usually know exactly how big an .eh_frame address is. | |
15982 | ||
15983 | Unfortunately, this is not true of the 64-bit EABI. The ABI was | |
15984 | originally defined to use 64-bit pointers (i.e. it is LP64), and | |
15985 | this is still the default mode. However, we also support an n32-like | |
15986 | ILP32 mode, which is selected by -mlong32. The problem is that the | |
15987 | assembler has traditionally not had an -mlong option, so it has | |
15988 | traditionally not known whether we're using the ILP32 or LP64 form. | |
15989 | ||
15990 | As it happens, gas versions up to and including 2.19 use _32-bit_ | |
15991 | addresses for EABI64 .cfi_* directives. This is wrong for the | |
15992 | default LP64 mode, so we can't use the directives by default. | |
15993 | Moreover, since gas's current behavior is at odds with gcc's | |
15994 | default behavior, it seems unwise to rely on future versions | |
15995 | of gas behaving the same way. We therefore avoid using .cfi | |
15996 | directives for -mlong32 as well. */ | |
15997 | if (mips_abi == ABI_EABI && TARGET_64BIT) | |
15998 | flag_dwarf2_cfi_asm = 0; | |
15999 | ||
49576e25 RS |
16000 | /* .cfi_* directives generate a read-only section, so fall back on |
16001 | manual .eh_frame creation if we need the section to be writable. */ | |
16002 | if (TARGET_WRITABLE_EH_FRAME) | |
16003 | flag_dwarf2_cfi_asm = 0; | |
16004 | ||
07045266 | 16005 | mips_init_print_operand_punct (); |
118ea793 | 16006 | |
ab77a036 RS |
16007 | /* Set up array to map GCC register number to debug register number. |
16008 | Ignore the special purpose register numbers. */ | |
118ea793 | 16009 | |
ab77a036 RS |
16010 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
16011 | { | |
16012 | mips_dbx_regno[i] = INVALID_REGNUM; | |
16013 | if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i)) | |
16014 | mips_dwarf_regno[i] = i; | |
16015 | else | |
16016 | mips_dwarf_regno[i] = INVALID_REGNUM; | |
16017 | } | |
118ea793 | 16018 | |
ab77a036 RS |
16019 | start = GP_DBX_FIRST - GP_REG_FIRST; |
16020 | for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) | |
16021 | mips_dbx_regno[i] = i + start; | |
118ea793 | 16022 | |
ab77a036 RS |
16023 | start = FP_DBX_FIRST - FP_REG_FIRST; |
16024 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
16025 | mips_dbx_regno[i] = i + start; | |
118ea793 | 16026 | |
65239d20 | 16027 | /* Accumulator debug registers use big-endian ordering. */ |
ab77a036 RS |
16028 | mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0; |
16029 | mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1; | |
16030 | mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0; | |
16031 | mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1; | |
16032 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
16033 | { | |
16034 | mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i; | |
16035 | mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1; | |
16036 | } | |
118ea793 | 16037 | |
5f5fe6d9 RS |
16038 | /* Set up mips_hard_regno_mode_ok. */ |
16039 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
16040 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
bbbbb16a ILT |
16041 | mips_hard_regno_mode_ok[mode][regno] |
16042 | = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode); | |
06a4ab70 | 16043 | |
ab77a036 RS |
16044 | /* Function to allocate machine-dependent function status. */ |
16045 | init_machine_status = &mips_init_machine_status; | |
4ca1f68f | 16046 | |
ab77a036 RS |
16047 | /* Default to working around R4000 errata only if the processor |
16048 | was selected explicitly. */ | |
16049 | if ((target_flags_explicit & MASK_FIX_R4000) == 0 | |
d371df6f | 16050 | && strcmp (mips_arch_info->name, "r4000") == 0) |
ab77a036 | 16051 | target_flags |= MASK_FIX_R4000; |
4ca1f68f | 16052 | |
ab77a036 RS |
16053 | /* Default to working around R4400 errata only if the processor |
16054 | was selected explicitly. */ | |
16055 | if ((target_flags_explicit & MASK_FIX_R4400) == 0 | |
d371df6f | 16056 | && strcmp (mips_arch_info->name, "r4400") == 0) |
ab77a036 | 16057 | target_flags |= MASK_FIX_R4400; |
4ca1f68f | 16058 | |
ee9a72e5 JK |
16059 | /* Default to working around R10000 errata only if the processor |
16060 | was selected explicitly. */ | |
16061 | if ((target_flags_explicit & MASK_FIX_R10000) == 0 | |
d371df6f | 16062 | && strcmp (mips_arch_info->name, "r10000") == 0) |
ee9a72e5 JK |
16063 | target_flags |= MASK_FIX_R10000; |
16064 | ||
16065 | /* Make sure that branch-likely instructions available when using | |
16066 | -mfix-r10000. The instructions are not available if either: | |
16067 | ||
16068 | 1. -mno-branch-likely was passed. | |
16069 | 2. The selected ISA does not support branch-likely and | |
16070 | the command line does not include -mbranch-likely. */ | |
16071 | if (TARGET_FIX_R10000 | |
16072 | && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0 | |
16073 | ? !ISA_HAS_BRANCHLIKELY | |
16074 | : !TARGET_BRANCHLIKELY)) | |
16075 | sorry ("%qs requires branch-likely instructions", "-mfix-r10000"); | |
16076 | ||
b96c5923 DD |
16077 | if (TARGET_SYNCI && !ISA_HAS_SYNCI) |
16078 | { | |
16079 | warning (0, "the %qs architecture does not support the synci " | |
16080 | "instruction", mips_arch_info->name); | |
16081 | target_flags &= ~MASK_SYNCI; | |
16082 | } | |
16083 | ||
b53da244 AN |
16084 | /* Only optimize PIC indirect calls if they are actually required. */ |
16085 | if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS) | |
16086 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
16087 | ||
ab77a036 | 16088 | /* Save base state of options. */ |
ab77a036 | 16089 | mips_base_target_flags = target_flags; |
ab77a036 RS |
16090 | mips_base_schedule_insns = flag_schedule_insns; |
16091 | mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition; | |
16092 | mips_base_move_loop_invariants = flag_move_loop_invariants; | |
16093 | mips_base_align_loops = align_loops; | |
16094 | mips_base_align_jumps = align_jumps; | |
16095 | mips_base_align_functions = align_functions; | |
118ea793 | 16096 | |
60730ade RS |
16097 | /* Now select the ISA mode. |
16098 | ||
16099 | Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to | |
16100 | MIPS16 mode afterwards if need be. */ | |
16101 | mips_set_mips16_mode (false); | |
ab77a036 | 16102 | } |
4ca1f68f | 16103 | |
ab77a036 RS |
16104 | /* Swap the register information for registers I and I + 1, which |
16105 | currently have the wrong endianness. Note that the registers' | |
16106 | fixedness and call-clobberedness might have been set on the | |
16107 | command line. */ | |
4ca1f68f | 16108 | |
ab77a036 RS |
16109 | static void |
16110 | mips_swap_registers (unsigned int i) | |
16111 | { | |
16112 | int tmpi; | |
16113 | const char *tmps; | |
4ca1f68f | 16114 | |
ab77a036 RS |
16115 | #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi) |
16116 | #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps) | |
4ca1f68f | 16117 | |
ab77a036 RS |
16118 | SWAP_INT (fixed_regs[i], fixed_regs[i + 1]); |
16119 | SWAP_INT (call_used_regs[i], call_used_regs[i + 1]); | |
16120 | SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]); | |
16121 | SWAP_STRING (reg_names[i], reg_names[i + 1]); | |
16122 | ||
16123 | #undef SWAP_STRING | |
16124 | #undef SWAP_INT | |
06a4ab70 CF |
16125 | } |
16126 | ||
5efd84c5 | 16127 | /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ |
06a4ab70 | 16128 | |
5efd84c5 | 16129 | static void |
ab77a036 | 16130 | mips_conditional_register_usage (void) |
06a4ab70 | 16131 | { |
1e27273f CM |
16132 | |
16133 | if (ISA_HAS_DSP) | |
16134 | { | |
16135 | /* These DSP control register fields are global. */ | |
16136 | global_regs[CCDSP_PO_REGNUM] = 1; | |
16137 | global_regs[CCDSP_SC_REGNUM] = 1; | |
16138 | } | |
006b72bf RS |
16139 | else |
16140 | AND_COMPL_HARD_REG_SET (accessible_reg_set, | |
16141 | reg_class_contents[(int) DSP_ACC_REGS]); | |
06a4ab70 | 16142 | |
ab77a036 RS |
16143 | if (!TARGET_HARD_FLOAT) |
16144 | { | |
006b72bf RS |
16145 | AND_COMPL_HARD_REG_SET (accessible_reg_set, |
16146 | reg_class_contents[(int) FP_REGS]); | |
16147 | AND_COMPL_HARD_REG_SET (accessible_reg_set, | |
16148 | reg_class_contents[(int) ST_REGS]); | |
ab77a036 | 16149 | } |
006b72bf | 16150 | else if (!ISA_HAS_8CC) |
ff55fb9c | 16151 | { |
65239d20 RS |
16152 | /* We only have a single condition-code register. We implement |
16153 | this by fixing all the condition-code registers and generating | |
16154 | RTL that refers directly to ST_REG_FIRST. */ | |
006b72bf RS |
16155 | AND_COMPL_HARD_REG_SET (accessible_reg_set, |
16156 | reg_class_contents[(int) ST_REGS]); | |
16157 | SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM); | |
16158 | fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1; | |
ff55fb9c | 16159 | } |
ab77a036 | 16160 | if (TARGET_MIPS16) |
ff55fb9c | 16161 | { |
a2ccf3c2 RS |
16162 | /* In MIPS16 mode, we permit the $t temporary registers to be used |
16163 | for reload. We prohibit the unused $s registers, since they | |
16164 | are call-saved, and saving them via a MIPS16 register would | |
16165 | probably waste more time than just reloading the value. */ | |
ab77a036 RS |
16166 | fixed_regs[18] = call_used_regs[18] = 1; |
16167 | fixed_regs[19] = call_used_regs[19] = 1; | |
16168 | fixed_regs[20] = call_used_regs[20] = 1; | |
16169 | fixed_regs[21] = call_used_regs[21] = 1; | |
16170 | fixed_regs[22] = call_used_regs[22] = 1; | |
16171 | fixed_regs[23] = call_used_regs[23] = 1; | |
16172 | fixed_regs[26] = call_used_regs[26] = 1; | |
16173 | fixed_regs[27] = call_used_regs[27] = 1; | |
16174 | fixed_regs[30] = call_used_regs[30] = 1; | |
a2ccf3c2 RS |
16175 | |
16176 | /* Do not allow HI and LO to be treated as register operands. | |
16177 | There are no MTHI or MTLO instructions (or any real need | |
16178 | for them) and one-way registers cannot easily be reloaded. */ | |
16179 | AND_COMPL_HARD_REG_SET (operand_reg_set, | |
16180 | reg_class_contents[(int) MD_REGS]); | |
ab77a036 | 16181 | } |
65239d20 | 16182 | /* $f20-$f23 are call-clobbered for n64. */ |
ab77a036 RS |
16183 | if (mips_abi == ABI_64) |
16184 | { | |
16185 | int regno; | |
16186 | for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) | |
16187 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
16188 | } | |
65239d20 RS |
16189 | /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered |
16190 | for n32. */ | |
ab77a036 RS |
16191 | if (mips_abi == ABI_N32) |
16192 | { | |
16193 | int regno; | |
16194 | for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) | |
16195 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
16196 | } | |
16197 | /* Make sure that double-register accumulator values are correctly | |
16198 | ordered for the current endianness. */ | |
16199 | if (TARGET_LITTLE_ENDIAN) | |
16200 | { | |
65239d20 RS |
16201 | unsigned int regno; |
16202 | ||
ab77a036 RS |
16203 | mips_swap_registers (MD_REG_FIRST); |
16204 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2) | |
16205 | mips_swap_registers (regno); | |
ff55fb9c | 16206 | } |
ff55fb9c | 16207 | } |
06a4ab70 | 16208 | |
65239d20 RS |
16209 | /* When generating MIPS16 code, we want to allocate $24 (T_REG) before |
16210 | other registers for instructions for which it is possible. This | |
16211 | encourages the compiler to use CMP in cases where an XOR would | |
16212 | require some register shuffling. */ | |
a8c1d5f8 | 16213 | |
ab77a036 RS |
16214 | void |
16215 | mips_order_regs_for_local_alloc (void) | |
a8c1d5f8 | 16216 | { |
65239d20 | 16217 | int i; |
a8c1d5f8 | 16218 | |
ab77a036 RS |
16219 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
16220 | reg_alloc_order[i] = i; | |
a8c1d5f8 | 16221 | |
ab77a036 RS |
16222 | if (TARGET_MIPS16) |
16223 | { | |
16224 | /* It really doesn't matter where we put register 0, since it is | |
16225 | a fixed register anyhow. */ | |
16226 | reg_alloc_order[0] = 24; | |
16227 | reg_alloc_order[24] = 0; | |
16228 | } | |
a8c1d5f8 | 16229 | } |
e19da24c | 16230 | |
0c433c31 RS |
16231 | /* Implement EH_USES. */ |
16232 | ||
16233 | bool | |
16234 | mips_eh_uses (unsigned int regno) | |
16235 | { | |
16236 | if (reload_completed && !TARGET_ABSOLUTE_JUMPS) | |
16237 | { | |
16238 | /* We need to force certain registers to be live in order to handle | |
16239 | PIC long branches correctly. See mips_must_initialize_gp_p for | |
16240 | details. */ | |
16241 | if (mips_cfun_has_cprestore_slot_p ()) | |
16242 | { | |
16243 | if (regno == CPRESTORE_SLOT_REGNUM) | |
16244 | return true; | |
16245 | } | |
16246 | else | |
16247 | { | |
16248 | if (cfun->machine->global_pointer == regno) | |
16249 | return true; | |
16250 | } | |
16251 | } | |
16252 | ||
16253 | return false; | |
16254 | } | |
16255 | ||
e19da24c CF |
16256 | /* Implement EPILOGUE_USES. */ |
16257 | ||
16258 | bool | |
16259 | mips_epilogue_uses (unsigned int regno) | |
16260 | { | |
16261 | /* Say that the epilogue uses the return address register. Note that | |
16262 | in the case of sibcalls, the values "used by the epilogue" are | |
16263 | considered live at the start of the called function. */ | |
293593b1 | 16264 | if (regno == RETURN_ADDR_REGNUM) |
e19da24c CF |
16265 | return true; |
16266 | ||
16267 | /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM. | |
16268 | See the comment above load_call<mode> for details. */ | |
16269 | if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM) | |
16270 | return true; | |
16271 | ||
16272 | /* An interrupt handler must preserve some registers that are | |
16273 | ordinarily call-clobbered. */ | |
16274 | if (cfun->machine->interrupt_handler_p | |
16275 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
16276 | return true; | |
16277 | ||
16278 | return false; | |
16279 | } | |
1afc5373 CF |
16280 | |
16281 | /* A for_each_rtx callback. Stop the search if *X is an AT register. */ | |
16282 | ||
16283 | static int | |
16284 | mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED) | |
16285 | { | |
47ac44d6 | 16286 | return REG_P (*x) && REGNO (*x) == AT_REGNUM; |
1afc5373 CF |
16287 | } |
16288 | ||
cf5fb4b0 RS |
16289 | /* Return true if INSN needs to be wrapped in ".set noat". |
16290 | INSN has NOPERANDS operands, stored in OPVEC. */ | |
1afc5373 | 16291 | |
cf5fb4b0 RS |
16292 | static bool |
16293 | mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands) | |
1afc5373 CF |
16294 | { |
16295 | int i; | |
16296 | ||
1afc5373 CF |
16297 | if (recog_memoized (insn) >= 0) |
16298 | for (i = 0; i < noperands; i++) | |
16299 | if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL)) | |
cf5fb4b0 RS |
16300 | return true; |
16301 | return false; | |
16302 | } | |
16303 | ||
16304 | /* Implement FINAL_PRESCAN_INSN. */ | |
16305 | ||
16306 | void | |
16307 | mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands) | |
16308 | { | |
16309 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) | |
16310 | mips_push_asm_switch (&mips_noat); | |
1afc5373 CF |
16311 | } |
16312 | ||
16313 | /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */ | |
16314 | ||
0e097268 | 16315 | static void |
cf5fb4b0 RS |
16316 | mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn, |
16317 | rtx *opvec, int noperands) | |
1afc5373 | 16318 | { |
cf5fb4b0 RS |
16319 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) |
16320 | mips_pop_asm_switch (&mips_noat); | |
1afc5373 | 16321 | } |
a3c7bb26 AN |
16322 | |
16323 | /* Return the function that is used to expand the <u>mulsidi3 pattern. | |
16324 | EXT_CODE is the code of the extension used. Return NULL if widening | |
16325 | multiplication shouldn't be used. */ | |
16326 | ||
16327 | mulsidi3_gen_fn | |
16328 | mips_mulsidi3_gen_fn (enum rtx_code ext_code) | |
16329 | { | |
16330 | bool signed_p; | |
16331 | ||
16332 | signed_p = ext_code == SIGN_EXTEND; | |
16333 | if (TARGET_64BIT) | |
16334 | { | |
16335 | /* Don't use widening multiplication with MULT when we have DMUL. Even | |
16336 | with the extension of its input operands DMUL is faster. Note that | |
16337 | the extension is not needed for signed multiplication. In order to | |
16338 | ensure that we always remove the redundant sign-extension in this | |
16339 | case we still expand mulsidi3 for DMUL. */ | |
16340 | if (ISA_HAS_DMUL3) | |
16341 | return signed_p ? gen_mulsidi3_64bit_dmul : NULL; | |
a2ccf3c2 RS |
16342 | if (TARGET_MIPS16) |
16343 | return (signed_p | |
16344 | ? gen_mulsidi3_64bit_mips16 | |
16345 | : gen_umulsidi3_64bit_mips16); | |
a3c7bb26 AN |
16346 | if (TARGET_FIX_R4000) |
16347 | return NULL; | |
16348 | return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit; | |
16349 | } | |
16350 | else | |
16351 | { | |
a2ccf3c2 RS |
16352 | if (TARGET_MIPS16) |
16353 | return (signed_p | |
16354 | ? gen_mulsidi3_32bit_mips16 | |
16355 | : gen_umulsidi3_32bit_mips16); | |
293b77b0 | 16356 | if (TARGET_FIX_R4000 && !ISA_HAS_DSP) |
a3c7bb26 | 16357 | return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000; |
a3c7bb26 AN |
16358 | return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit; |
16359 | } | |
16360 | } | |
a1d29c8c | 16361 | \f |
c640a3bd RS |
16362 | /* Return the size in bytes of the trampoline code, padded to |
16363 | TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target | |
16364 | function address immediately follow. */ | |
a1d29c8c | 16365 | |
c640a3bd RS |
16366 | int |
16367 | mips_trampoline_code_size (void) | |
16368 | { | |
16369 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
16370 | return 4 * 4; | |
16371 | else if (ptr_mode == DImode) | |
16372 | return 8 * 4; | |
16373 | else if (ISA_HAS_LOAD_DELAY) | |
16374 | return 6 * 4; | |
a1d29c8c | 16375 | else |
c640a3bd | 16376 | return 4 * 4; |
a1d29c8c RH |
16377 | } |
16378 | ||
16379 | /* Implement TARGET_TRAMPOLINE_INIT. */ | |
16380 | ||
16381 | static void | |
16382 | mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
16383 | { | |
c640a3bd RS |
16384 | rtx addr, end_addr, high, low, opcode, mem; |
16385 | rtx trampoline[8]; | |
16386 | unsigned int i, j; | |
16387 | HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset; | |
16388 | ||
16389 | /* Work out the offsets of the pointers from the start of the | |
16390 | trampoline code. */ | |
16391 | end_addr_offset = mips_trampoline_code_size (); | |
16392 | static_chain_offset = end_addr_offset; | |
16393 | target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); | |
a1d29c8c | 16394 | |
c640a3bd RS |
16395 | /* Get pointers to the beginning and end of the code block. */ |
16396 | addr = force_reg (Pmode, XEXP (m_tramp, 0)); | |
16397 | end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset)); | |
a1d29c8c | 16398 | |
c640a3bd | 16399 | #define OP(X) gen_int_mode (X, SImode) |
a1d29c8c | 16400 | |
c640a3bd RS |
16401 | /* Build up the code in TRAMPOLINE. */ |
16402 | i = 0; | |
16403 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
16404 | { | |
16405 | /* $25 contains the address of the trampoline. Emit code of the form: | |
16406 | ||
16407 | l[wd] $1, target_function_offset($25) | |
16408 | l[wd] $static_chain, static_chain_offset($25) | |
16409 | jr $1 | |
16410 | move $25,$1. */ | |
16411 | trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM, | |
16412 | target_function_offset, | |
16413 | PIC_FUNCTION_ADDR_REGNUM)); | |
16414 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16415 | static_chain_offset, | |
16416 | PIC_FUNCTION_ADDR_REGNUM)); | |
16417 | trampoline[i++] = OP (MIPS_JR (AT_REGNUM)); | |
16418 | trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM)); | |
16419 | } | |
16420 | else if (ptr_mode == DImode) | |
16421 | { | |
16422 | /* It's too cumbersome to create the full 64-bit address, so let's | |
16423 | instead use: | |
16424 | ||
16425 | move $1, $31 | |
16426 | bal 1f | |
16427 | nop | |
16428 | 1: l[wd] $25, target_function_offset - 12($31) | |
16429 | l[wd] $static_chain, static_chain_offset - 12($31) | |
16430 | jr $25 | |
16431 | move $31, $1 | |
16432 | ||
16433 | where 12 is the offset of "1:" from the start of the code block. */ | |
16434 | trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM)); | |
16435 | trampoline[i++] = OP (MIPS_BAL (1)); | |
16436 | trampoline[i++] = OP (MIPS_NOP); | |
16437 | trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
16438 | target_function_offset - 12, | |
16439 | RETURN_ADDR_REGNUM)); | |
16440 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16441 | static_chain_offset - 12, | |
16442 | RETURN_ADDR_REGNUM)); | |
16443 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16444 | trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM)); | |
16445 | } | |
16446 | else | |
16447 | { | |
16448 | /* If the target has load delays, emit: | |
16449 | ||
16450 | lui $1, %hi(end_addr) | |
16451 | lw $25, %lo(end_addr + ...)($1) | |
16452 | lw $static_chain, %lo(end_addr + ...)($1) | |
16453 | jr $25 | |
16454 | nop | |
16455 | ||
16456 | Otherwise emit: | |
16457 | ||
16458 | lui $1, %hi(end_addr) | |
16459 | lw $25, %lo(end_addr + ...)($1) | |
16460 | jr $25 | |
16461 | lw $static_chain, %lo(end_addr + ...)($1). */ | |
16462 | ||
16463 | /* Split END_ADDR into %hi and %lo values. Trampolines are aligned | |
16464 | to 64 bits, so the %lo value will have the bottom 3 bits clear. */ | |
16465 | high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000), | |
16466 | NULL, false, OPTAB_WIDEN); | |
16467 | high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16), | |
16468 | NULL, false, OPTAB_WIDEN); | |
16469 | low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true); | |
16470 | ||
16471 | /* Emit the LUI. */ | |
16472 | opcode = OP (MIPS_LUI (AT_REGNUM, 0)); | |
16473 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high, | |
16474 | NULL, false, OPTAB_WIDEN); | |
16475 | ||
16476 | /* Emit the load of the target function. */ | |
16477 | opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
16478 | target_function_offset - end_addr_offset, | |
16479 | AT_REGNUM)); | |
16480 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
16481 | NULL, false, OPTAB_WIDEN); | |
16482 | ||
16483 | /* Emit the JR here, if we can. */ | |
16484 | if (!ISA_HAS_LOAD_DELAY) | |
16485 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16486 | ||
16487 | /* Emit the load of the static chain register. */ | |
16488 | opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16489 | static_chain_offset - end_addr_offset, | |
16490 | AT_REGNUM)); | |
16491 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
16492 | NULL, false, OPTAB_WIDEN); | |
16493 | ||
16494 | /* Emit the JR, if we couldn't above. */ | |
16495 | if (ISA_HAS_LOAD_DELAY) | |
16496 | { | |
16497 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16498 | trampoline[i++] = OP (MIPS_NOP); | |
16499 | } | |
16500 | } | |
16501 | ||
16502 | #undef OP | |
16503 | ||
16504 | /* Copy the trampoline code. Leave any padding uninitialized. */ | |
16505 | for (j = 0; j < i; j++) | |
16506 | { | |
16507 | mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode)); | |
16508 | mips_emit_move (mem, trampoline[j]); | |
16509 | } | |
16510 | ||
16511 | /* Set up the static chain pointer field. */ | |
16512 | mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); | |
16513 | mips_emit_move (mem, chain_value); | |
16514 | ||
16515 | /* Set up the target function field. */ | |
16516 | mem = adjust_address (m_tramp, ptr_mode, target_function_offset); | |
16517 | mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); | |
16518 | ||
16519 | /* Flush the code part of the trampoline. */ | |
a1d29c8c RH |
16520 | emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); |
16521 | emit_insn (gen_clear_cache (addr, end_addr)); | |
16522 | } | |
c376dbfb DD |
16523 | |
16524 | /* Implement FUNCTION_PROFILER. */ | |
16525 | ||
16526 | void mips_function_profiler (FILE *file) | |
16527 | { | |
16528 | if (TARGET_MIPS16) | |
16529 | sorry ("mips16 function profiling"); | |
16530 | if (TARGET_LONG_CALLS) | |
16531 | { | |
16532 | /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ | |
16533 | if (Pmode == DImode) | |
16534 | fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]); | |
16535 | else | |
16536 | fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]); | |
16537 | } | |
16538 | mips_push_asm_switch (&mips_noat); | |
16539 | fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n", | |
16540 | reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]); | |
16541 | /* _mcount treats $2 as the static chain register. */ | |
16542 | if (cfun->static_chain_decl != NULL) | |
16543 | fprintf (file, "\tmove\t%s,%s\n", reg_names[2], | |
16544 | reg_names[STATIC_CHAIN_REGNUM]); | |
16545 | if (TARGET_MCOUNT_RA_ADDRESS) | |
16546 | { | |
16547 | /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the | |
16548 | ra save location. */ | |
16549 | if (cfun->machine->frame.ra_fp_offset == 0) | |
16550 | /* ra not saved, pass zero. */ | |
16551 | fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]); | |
16552 | else | |
16553 | fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n", | |
16554 | Pmode == DImode ? "dla" : "la", reg_names[12], | |
16555 | cfun->machine->frame.ra_fp_offset, | |
16556 | reg_names[STACK_POINTER_REGNUM]); | |
16557 | } | |
16558 | if (!TARGET_NEWABI) | |
16559 | fprintf (file, | |
16560 | "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", | |
16561 | TARGET_64BIT ? "dsubu" : "subu", | |
16562 | reg_names[STACK_POINTER_REGNUM], | |
16563 | reg_names[STACK_POINTER_REGNUM], | |
16564 | Pmode == DImode ? 16 : 8); | |
16565 | ||
16566 | if (TARGET_LONG_CALLS) | |
16567 | fprintf (file, "\tjalr\t%s\n", reg_names[3]); | |
16568 | else | |
16569 | fprintf (file, "\tjal\t_mcount\n"); | |
16570 | mips_pop_asm_switch (&mips_noat); | |
16571 | /* _mcount treats $2 as the static chain register. */ | |
16572 | if (cfun->static_chain_decl != NULL) | |
16573 | fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], | |
16574 | reg_names[2]); | |
16575 | } | |
49042313 MX |
16576 | |
16577 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default | |
16578 | behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even | |
1f5f063d | 16579 | when TARGET_LOONGSON_VECTORS is true. */ |
49042313 MX |
16580 | |
16581 | static unsigned HOST_WIDE_INT | |
16582 | mips_shift_truncation_mask (enum machine_mode mode) | |
16583 | { | |
1f5f063d | 16584 | if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) |
49042313 MX |
16585 | return 0; |
16586 | ||
16587 | return GET_MODE_BITSIZE (mode) - 1; | |
16588 | } | |
16589 | ||
e32ea2d1 RS |
16590 | /* Implement TARGET_PREPARE_PCH_SAVE. */ |
16591 | ||
16592 | static void | |
16593 | mips_prepare_pch_save (void) | |
16594 | { | |
16595 | /* We are called in a context where the current MIPS16 vs. non-MIPS16 | |
16596 | setting should be irrelevant. The question then is: which setting | |
16597 | makes most sense at load time? | |
16598 | ||
16599 | The PCH is loaded before the first token is read. We should never | |
16600 | have switched into MIPS16 mode by that point, and thus should not | |
16601 | have populated mips16_globals. Nor can we load the entire contents | |
16602 | of mips16_globals from the PCH file, because mips16_globals contains | |
16603 | a combination of GGC and non-GGC data. | |
16604 | ||
16605 | There is therefore no point in trying save the GGC part of | |
16606 | mips16_globals to the PCH file, or to preserve MIPS16ness across | |
16607 | the PCH save and load. The loading compiler would not have access | |
16608 | to the non-GGC parts of mips16_globals (either from the PCH file, | |
16609 | or from a copy that the loading compiler generated itself) and would | |
16610 | have to call target_reinit anyway. | |
16611 | ||
16612 | It therefore seems best to switch back to non-MIPS16 mode at | |
16613 | save time, and to ensure that mips16_globals remains null after | |
16614 | a PCH load. */ | |
16615 | mips_set_mips16_mode (false); | |
16616 | mips16_globals = 0; | |
16617 | } | |
ab77a036 | 16618 | \f |
7dab511c RH |
16619 | /* Generate or test for an insn that supports a constant permutation. */ |
16620 | ||
16621 | #define MAX_VECT_LEN 8 | |
16622 | ||
16623 | struct expand_vec_perm_d | |
16624 | { | |
16625 | rtx target, op0, op1; | |
16626 | unsigned char perm[MAX_VECT_LEN]; | |
16627 | enum machine_mode vmode; | |
16628 | unsigned char nelt; | |
16629 | bool one_vector_p; | |
16630 | bool testing_p; | |
16631 | }; | |
16632 | ||
16633 | /* Construct (set target (vec_select op0 (parallel perm))) and | |
16634 | return true if that's a valid instruction in the active ISA. */ | |
16635 | ||
16636 | static bool | |
16637 | mips_expand_vselect (rtx target, rtx op0, | |
16638 | const unsigned char *perm, unsigned nelt) | |
16639 | { | |
16640 | rtx rperm[MAX_VECT_LEN], x; | |
16641 | unsigned i; | |
16642 | ||
16643 | for (i = 0; i < nelt; ++i) | |
16644 | rperm[i] = GEN_INT (perm[i]); | |
16645 | ||
16646 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); | |
16647 | x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); | |
16648 | x = gen_rtx_SET (VOIDmode, target, x); | |
16649 | ||
16650 | x = emit_insn (x); | |
16651 | if (recog_memoized (x) < 0) | |
16652 | { | |
16653 | remove_insn (x); | |
16654 | return false; | |
16655 | } | |
16656 | return true; | |
16657 | } | |
16658 | ||
16659 | /* Similar, but generate a vec_concat from op0 and op1 as well. */ | |
16660 | ||
16661 | static bool | |
16662 | mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1, | |
16663 | const unsigned char *perm, unsigned nelt) | |
16664 | { | |
16665 | enum machine_mode v2mode; | |
16666 | rtx x; | |
16667 | ||
16668 | v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0)); | |
16669 | x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); | |
16670 | return mips_expand_vselect (target, x, perm, nelt); | |
16671 | } | |
16672 | ||
16673 | /* Recognize patterns for even-odd extraction. */ | |
16674 | ||
16675 | static bool | |
16676 | mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d) | |
16677 | { | |
16678 | unsigned i, odd, nelt = d->nelt; | |
16679 | rtx t0, t1, t2, t3; | |
16680 | ||
16681 | if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) | |
16682 | return false; | |
16683 | /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */ | |
16684 | if (nelt < 4) | |
16685 | return false; | |
16686 | ||
16687 | odd = d->perm[0]; | |
16688 | if (odd > 1) | |
16689 | return false; | |
16690 | for (i = 1; i < nelt; ++i) | |
16691 | if (d->perm[i] != i * 2 + odd) | |
16692 | return false; | |
16693 | ||
16694 | if (d->testing_p) | |
16695 | return true; | |
16696 | ||
16697 | /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */ | |
16698 | t0 = gen_reg_rtx (d->vmode); | |
16699 | t1 = gen_reg_rtx (d->vmode); | |
16700 | switch (d->vmode) | |
16701 | { | |
16702 | case V4HImode: | |
16703 | emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1)); | |
16704 | emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1)); | |
16705 | if (odd) | |
16706 | emit_insn (gen_loongson_punpckhhw (d->target, t1, t0)); | |
16707 | else | |
16708 | emit_insn (gen_loongson_punpcklhw (d->target, t1, t0)); | |
16709 | break; | |
16710 | ||
16711 | case V8QImode: | |
16712 | t2 = gen_reg_rtx (d->vmode); | |
16713 | t3 = gen_reg_rtx (d->vmode); | |
16714 | emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1)); | |
16715 | emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1)); | |
16716 | emit_insn (gen_loongson_punpckhbh (t2, t1, t0)); | |
16717 | emit_insn (gen_loongson_punpcklbh (t3, t1, t0)); | |
16718 | if (odd) | |
16719 | emit_insn (gen_loongson_punpckhbh (d->target, t3, t2)); | |
16720 | else | |
16721 | emit_insn (gen_loongson_punpcklbh (d->target, t3, t2)); | |
16722 | break; | |
16723 | ||
16724 | default: | |
16725 | gcc_unreachable (); | |
16726 | } | |
16727 | return true; | |
16728 | } | |
16729 | ||
16730 | /* Recognize patterns for the Loongson PSHUFH instruction. */ | |
16731 | ||
16732 | static bool | |
16733 | mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d) | |
16734 | { | |
16735 | unsigned i, mask; | |
16736 | rtx rmask; | |
16737 | ||
16738 | if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) | |
16739 | return false; | |
16740 | if (d->vmode != V4HImode) | |
16741 | return false; | |
16742 | if (d->testing_p) | |
16743 | return true; | |
16744 | ||
16745 | /* Convert the selector into the packed 8-bit form for pshufh. */ | |
16746 | /* Recall that loongson is little-endian only. No big-endian | |
16747 | adjustment required. */ | |
16748 | for (i = mask = 0; i < 4; i++) | |
16749 | mask |= (d->perm[i] & 3) << (i * 2); | |
16750 | rmask = force_reg (SImode, GEN_INT (mask)); | |
16751 | ||
16752 | if (d->one_vector_p) | |
16753 | emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask)); | |
16754 | else | |
16755 | { | |
16756 | rtx t0, t1, x, merge, rmerge[4]; | |
16757 | ||
16758 | t0 = gen_reg_rtx (V4HImode); | |
16759 | t1 = gen_reg_rtx (V4HImode); | |
16760 | emit_insn (gen_loongson_pshufh (t1, d->op1, rmask)); | |
16761 | emit_insn (gen_loongson_pshufh (t0, d->op0, rmask)); | |
16762 | ||
16763 | for (i = 0; i < 4; ++i) | |
16764 | rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx); | |
16765 | merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge)); | |
16766 | merge = force_reg (V4HImode, merge); | |
16767 | ||
16768 | x = gen_rtx_AND (V4HImode, merge, t1); | |
16769 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
16770 | ||
16771 | x = gen_rtx_NOT (V4HImode, merge); | |
16772 | x = gen_rtx_AND (V4HImode, x, t0); | |
16773 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
16774 | ||
16775 | x = gen_rtx_IOR (V4HImode, t0, t1); | |
16776 | emit_insn (gen_rtx_SET (VOIDmode, d->target, x)); | |
16777 | } | |
16778 | ||
16779 | return true; | |
16780 | } | |
16781 | ||
16782 | /* Recognize broadcast patterns for the Loongson. */ | |
16783 | ||
16784 | static bool | |
16785 | mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d) | |
16786 | { | |
16787 | unsigned i, elt; | |
16788 | rtx t0, t1; | |
16789 | ||
16790 | if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) | |
16791 | return false; | |
16792 | /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */ | |
16793 | if (d->vmode != V8QImode) | |
16794 | return false; | |
16795 | if (!d->one_vector_p) | |
16796 | return false; | |
16797 | ||
16798 | elt = d->perm[0]; | |
16799 | for (i = 1; i < 8; ++i) | |
16800 | if (d->perm[i] != elt) | |
16801 | return false; | |
16802 | ||
16803 | if (d->testing_p) | |
16804 | return true; | |
16805 | ||
16806 | /* With one interleave we put two of the desired element adjacent. */ | |
16807 | t0 = gen_reg_rtx (V8QImode); | |
16808 | if (elt < 4) | |
16809 | emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0)); | |
16810 | else | |
16811 | emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0)); | |
16812 | ||
16813 | /* Shuffle that one HImode element into all locations. */ | |
16814 | elt &= 3; | |
16815 | elt *= 0x55; | |
16816 | t1 = gen_reg_rtx (V4HImode); | |
16817 | emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0), | |
16818 | force_reg (SImode, GEN_INT (elt)))); | |
16819 | ||
16820 | emit_move_insn (d->target, gen_lowpart (V8QImode, t1)); | |
16821 | return true; | |
16822 | } | |
16823 | ||
16824 | static bool | |
16825 | mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) | |
16826 | { | |
16827 | unsigned int i, nelt = d->nelt; | |
16828 | unsigned char perm2[MAX_VECT_LEN]; | |
16829 | ||
16830 | if (d->one_vector_p) | |
16831 | { | |
16832 | /* Try interleave with alternating operands. */ | |
16833 | memcpy (perm2, d->perm, sizeof(perm2)); | |
16834 | for (i = 1; i < nelt; i += 2) | |
16835 | perm2[i] += nelt; | |
16836 | if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt)) | |
16837 | return true; | |
16838 | } | |
16839 | else | |
16840 | { | |
16841 | if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, | |
16842 | d->perm, nelt)) | |
16843 | return true; | |
16844 | ||
16845 | /* Try again with swapped operands. */ | |
16846 | for (i = 0; i < nelt; ++i) | |
16847 | perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1); | |
16848 | if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) | |
16849 | return true; | |
16850 | } | |
16851 | ||
16852 | if (mips_expand_vpc_loongson_even_odd (d)) | |
16853 | return true; | |
16854 | if (mips_expand_vpc_loongson_pshufh (d)) | |
16855 | return true; | |
16856 | if (mips_expand_vpc_loongson_bcast (d)) | |
16857 | return true; | |
16858 | return false; | |
16859 | } | |
16860 | ||
16861 | /* Expand a vec_perm_const pattern. */ | |
16862 | ||
16863 | bool | |
16864 | mips_expand_vec_perm_const (rtx operands[4]) | |
16865 | { | |
16866 | struct expand_vec_perm_d d; | |
16867 | int i, nelt, which; | |
16868 | unsigned char orig_perm[MAX_VECT_LEN]; | |
16869 | rtx sel; | |
16870 | bool ok; | |
16871 | ||
16872 | d.target = operands[0]; | |
16873 | d.op0 = operands[1]; | |
16874 | d.op1 = operands[2]; | |
16875 | sel = operands[3]; | |
16876 | ||
16877 | d.vmode = GET_MODE (d.target); | |
16878 | gcc_assert (VECTOR_MODE_P (d.vmode)); | |
16879 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
16880 | d.testing_p = false; | |
16881 | ||
16882 | for (i = which = 0; i < nelt; ++i) | |
16883 | { | |
16884 | rtx e = XVECEXP (sel, 0, i); | |
16885 | int ei = INTVAL (e) & (2 * nelt - 1); | |
16886 | which |= (ei < nelt ? 1 : 2); | |
16887 | orig_perm[i] = ei; | |
16888 | } | |
16889 | memcpy (d.perm, orig_perm, MAX_VECT_LEN); | |
16890 | ||
16891 | switch (which) | |
16892 | { | |
16893 | default: | |
16894 | gcc_unreachable(); | |
16895 | ||
16896 | case 3: | |
16897 | d.one_vector_p = false; | |
16898 | if (!rtx_equal_p (d.op0, d.op1)) | |
16899 | break; | |
16900 | /* FALLTHRU */ | |
16901 | ||
16902 | case 2: | |
16903 | for (i = 0; i < nelt; ++i) | |
16904 | d.perm[i] &= nelt - 1; | |
16905 | d.op0 = d.op1; | |
16906 | d.one_vector_p = true; | |
16907 | break; | |
16908 | ||
16909 | case 1: | |
16910 | d.op1 = d.op0; | |
16911 | d.one_vector_p = true; | |
16912 | break; | |
16913 | } | |
16914 | ||
16915 | ok = mips_expand_vec_perm_const_1 (&d); | |
16916 | ||
16917 | /* If we were given a two-vector permutation which just happened to | |
16918 | have both input vectors equal, we folded this into a one-vector | |
16919 | permutation. There are several loongson patterns that are matched | |
16920 | via direct vec_select+vec_concat expansion, but we do not have | |
16921 | support in mips_expand_vec_perm_const_1 to guess the adjustment | |
16922 | that should be made for a single operand. Just try again with | |
16923 | the original permutation. */ | |
16924 | if (!ok && which == 3) | |
16925 | { | |
16926 | d.op0 = operands[1]; | |
16927 | d.op1 = operands[2]; | |
16928 | d.one_vector_p = false; | |
16929 | memcpy (d.perm, orig_perm, MAX_VECT_LEN); | |
16930 | ok = mips_expand_vec_perm_const_1 (&d); | |
16931 | } | |
16932 | ||
16933 | return ok; | |
16934 | } | |
16935 | ||
16936 | /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ | |
16937 | ||
16938 | static bool | |
16939 | mips_vectorize_vec_perm_const_ok (enum machine_mode vmode, | |
16940 | const unsigned char *sel) | |
16941 | { | |
16942 | struct expand_vec_perm_d d; | |
16943 | unsigned int i, nelt, which; | |
16944 | bool ret; | |
16945 | ||
16946 | d.vmode = vmode; | |
16947 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
16948 | d.testing_p = true; | |
16949 | memcpy (d.perm, sel, nelt); | |
16950 | ||
16951 | /* Categorize the set of elements in the selector. */ | |
16952 | for (i = which = 0; i < nelt; ++i) | |
16953 | { | |
16954 | unsigned char e = d.perm[i]; | |
16955 | gcc_assert (e < 2 * nelt); | |
16956 | which |= (e < nelt ? 1 : 2); | |
16957 | } | |
16958 | ||
16959 | /* For all elements from second vector, fold the elements to first. */ | |
16960 | if (which == 2) | |
16961 | for (i = 0; i < nelt; ++i) | |
16962 | d.perm[i] -= nelt; | |
16963 | ||
16964 | /* Check whether the mask can be applied to the vector type. */ | |
16965 | d.one_vector_p = (which != 3); | |
16966 | ||
16967 | d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); | |
16968 | d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); | |
16969 | if (!d.one_vector_p) | |
16970 | d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); | |
16971 | ||
16972 | start_sequence (); | |
16973 | ret = mips_expand_vec_perm_const_1 (&d); | |
16974 | end_sequence (); | |
16975 | ||
16976 | return ret; | |
16977 | } | |
16978 | ||
16979 | /* Expand an integral vector unpack operation. */ | |
16980 | ||
16981 | void | |
16982 | mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) | |
16983 | { | |
16984 | enum machine_mode imode = GET_MODE (operands[1]); | |
16985 | rtx (*unpack) (rtx, rtx, rtx); | |
16986 | rtx (*cmpgt) (rtx, rtx, rtx); | |
16987 | rtx tmp, dest, zero; | |
16988 | ||
16989 | switch (imode) | |
16990 | { | |
16991 | case V8QImode: | |
16992 | if (high_p) | |
16993 | unpack = gen_loongson_punpckhbh; | |
16994 | else | |
16995 | unpack = gen_loongson_punpcklbh; | |
16996 | cmpgt = gen_loongson_pcmpgtb; | |
16997 | break; | |
16998 | case V4HImode: | |
16999 | if (high_p) | |
17000 | unpack = gen_loongson_punpckhhw; | |
17001 | else | |
17002 | unpack = gen_loongson_punpcklhw; | |
17003 | cmpgt = gen_loongson_pcmpgth; | |
17004 | break; | |
17005 | default: | |
17006 | gcc_unreachable (); | |
17007 | } | |
17008 | ||
17009 | zero = force_reg (imode, CONST0_RTX (imode)); | |
17010 | if (unsigned_p) | |
17011 | tmp = zero; | |
17012 | else | |
17013 | { | |
17014 | tmp = gen_reg_rtx (imode); | |
17015 | emit_insn (cmpgt (tmp, zero, operands[1])); | |
17016 | } | |
17017 | ||
17018 | dest = gen_reg_rtx (imode); | |
17019 | emit_insn (unpack (dest, operands[1], tmp)); | |
17020 | ||
17021 | emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest)); | |
17022 | } | |
17023 | ||
17024 | /* A subroutine of mips_expand_vec_init, match constant vector elements. */ | |
17025 | ||
17026 | static inline bool | |
17027 | mips_constant_elt_p (rtx x) | |
17028 | { | |
17029 | return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE; | |
17030 | } | |
17031 | ||
17032 | /* A subroutine of mips_expand_vec_init, expand via broadcast. */ | |
17033 | ||
17034 | static void | |
17035 | mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt) | |
17036 | { | |
17037 | struct expand_vec_perm_d d; | |
17038 | rtx t1; | |
17039 | bool ok; | |
17040 | ||
17041 | if (elt != const0_rtx) | |
17042 | elt = force_reg (GET_MODE_INNER (vmode), elt); | |
17043 | if (REG_P (elt)) | |
17044 | elt = gen_lowpart (DImode, elt); | |
17045 | ||
17046 | t1 = gen_reg_rtx (vmode); | |
17047 | switch (vmode) | |
17048 | { | |
17049 | case V8QImode: | |
17050 | emit_insn (gen_loongson_vec_init1_v8qi (t1, elt)); | |
17051 | break; | |
17052 | case V4HImode: | |
17053 | emit_insn (gen_loongson_vec_init1_v4hi (t1, elt)); | |
17054 | break; | |
17055 | default: | |
17056 | gcc_unreachable (); | |
17057 | } | |
17058 | ||
17059 | memset (&d, 0, sizeof (d)); | |
17060 | d.target = target; | |
17061 | d.op0 = t1; | |
17062 | d.op1 = t1; | |
17063 | d.vmode = vmode; | |
17064 | d.nelt = GET_MODE_NUNITS (vmode); | |
17065 | d.one_vector_p = true; | |
17066 | ||
17067 | ok = mips_expand_vec_perm_const_1 (&d); | |
17068 | gcc_assert (ok); | |
17069 | } | |
17070 | ||
17071 | /* A subroutine of mips_expand_vec_init, replacing all of the non-constant | |
17072 | elements of VALS with zeros, copy the constant vector to TARGET. */ | |
17073 | ||
17074 | static void | |
17075 | mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt, | |
17076 | rtx target, rtx vals) | |
17077 | { | |
17078 | rtvec vec = shallow_copy_rtvec (XVEC (vals, 0)); | |
17079 | unsigned i; | |
17080 | ||
17081 | for (i = 0; i < nelt; ++i) | |
17082 | { | |
17083 | if (!mips_constant_elt_p (RTVEC_ELT (vec, i))) | |
17084 | RTVEC_ELT (vec, i) = const0_rtx; | |
17085 | } | |
17086 | ||
17087 | emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec)); | |
17088 | } | |
17089 | ||
17090 | ||
17091 | /* A subroutine of mips_expand_vec_init, expand via pinsrh. */ | |
17092 | ||
17093 | static void | |
17094 | mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var) | |
17095 | { | |
17096 | mips_expand_vi_constant (V4HImode, 4, target, vals); | |
17097 | ||
17098 | emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var), | |
17099 | GEN_INT (one_var))); | |
17100 | } | |
17101 | ||
17102 | /* A subroutine of mips_expand_vec_init, expand anything via memory. */ | |
17103 | ||
17104 | static void | |
17105 | mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode, | |
17106 | unsigned nelt, unsigned nvar, rtx target, rtx vals) | |
17107 | { | |
17108 | rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode), 0); | |
17109 | unsigned int i, isize = GET_MODE_SIZE (imode); | |
17110 | ||
17111 | if (nvar < nelt) | |
17112 | mips_expand_vi_constant (vmode, nelt, mem, vals); | |
17113 | ||
17114 | for (i = 0; i < nelt; ++i) | |
17115 | { | |
17116 | rtx x = XVECEXP (vals, 0, i); | |
17117 | if (!mips_constant_elt_p (x)) | |
17118 | emit_move_insn (adjust_address (mem, imode, i * isize), x); | |
17119 | } | |
17120 | ||
17121 | emit_move_insn (target, mem); | |
17122 | } | |
17123 | ||
17124 | /* Expand a vector initialization. */ | |
17125 | ||
17126 | void | |
17127 | mips_expand_vector_init (rtx target, rtx vals) | |
17128 | { | |
17129 | enum machine_mode vmode = GET_MODE (target); | |
17130 | enum machine_mode imode = GET_MODE_INNER (vmode); | |
17131 | unsigned i, nelt = GET_MODE_NUNITS (vmode); | |
17132 | unsigned nvar = 0, one_var = -1u; | |
17133 | bool all_same = true; | |
17134 | rtx x; | |
17135 | ||
17136 | for (i = 0; i < nelt; ++i) | |
17137 | { | |
17138 | x = XVECEXP (vals, 0, i); | |
17139 | if (!mips_constant_elt_p (x)) | |
17140 | nvar++, one_var = i; | |
17141 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
17142 | all_same = false; | |
17143 | } | |
17144 | ||
17145 | /* Load constants from the pool, or whatever's handy. */ | |
17146 | if (nvar == 0) | |
17147 | { | |
17148 | emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0))); | |
17149 | return; | |
17150 | } | |
17151 | ||
17152 | /* For two-part initialization, always use CONCAT. */ | |
17153 | if (nelt == 2) | |
17154 | { | |
17155 | rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0)); | |
17156 | rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1)); | |
17157 | x = gen_rtx_VEC_CONCAT (vmode, op0, op1); | |
17158 | emit_insn (gen_rtx_SET (VOIDmode, target, x)); | |
17159 | return; | |
17160 | } | |
17161 | ||
17162 | /* Loongson is the only cpu with vectors with more elements. */ | |
17163 | gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS); | |
17164 | ||
17165 | /* If all values are identical, broadcast the value. */ | |
17166 | if (all_same) | |
17167 | { | |
17168 | mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0)); | |
17169 | return; | |
17170 | } | |
17171 | ||
17172 | /* If we've only got one non-variable V4HImode, use PINSRH. */ | |
17173 | if (nvar == 1 && vmode == V4HImode) | |
17174 | { | |
17175 | mips_expand_vi_loongson_one_pinsrh (target, vals, one_var); | |
17176 | return; | |
17177 | } | |
17178 | ||
17179 | mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals); | |
17180 | } | |
17181 | ||
17182 | /* Expand a vector reduction. */ | |
17183 | ||
17184 | void | |
17185 | mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx)) | |
17186 | { | |
17187 | enum machine_mode vmode = GET_MODE (in); | |
17188 | unsigned char perm2[2]; | |
17189 | rtx last, next, fold, x; | |
17190 | bool ok; | |
17191 | ||
17192 | last = in; | |
17193 | fold = gen_reg_rtx (vmode); | |
17194 | switch (vmode) | |
17195 | { | |
17196 | case V2SFmode: | |
17197 | /* Use PUL/PLU to produce { L, H } op { H, L }. | |
17198 | By reversing the pair order, rather than a pure interleave high, | |
17199 | we avoid erroneous exceptional conditions that we might otherwise | |
17200 | produce from the computation of H op H. */ | |
17201 | perm2[0] = 1; | |
17202 | perm2[1] = 2; | |
17203 | ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2); | |
17204 | gcc_assert (ok); | |
17205 | break; | |
17206 | ||
17207 | case V2SImode: | |
17208 | /* Use interleave to produce { H, L } op { H, H }. */ | |
17209 | emit_insn (gen_loongson_punpckhwd (fold, last, last)); | |
17210 | break; | |
17211 | ||
17212 | case V4HImode: | |
17213 | /* Perform the first reduction with interleave, | |
17214 | and subsequent reductions with shifts. */ | |
17215 | emit_insn (gen_loongson_punpckhwd_hi (fold, last, last)); | |
17216 | ||
17217 | next = gen_reg_rtx (vmode); | |
17218 | emit_insn (gen (next, last, fold)); | |
17219 | last = next; | |
17220 | ||
17221 | fold = gen_reg_rtx (vmode); | |
17222 | x = force_reg (SImode, GEN_INT (16)); | |
17223 | emit_insn (gen_vec_shr_v4hi (fold, last, x)); | |
17224 | break; | |
17225 | ||
17226 | case V8QImode: | |
17227 | emit_insn (gen_loongson_punpckhwd_qi (fold, last, last)); | |
17228 | ||
17229 | next = gen_reg_rtx (vmode); | |
17230 | emit_insn (gen (next, last, fold)); | |
17231 | last = next; | |
17232 | ||
17233 | fold = gen_reg_rtx (vmode); | |
17234 | x = force_reg (SImode, GEN_INT (16)); | |
17235 | emit_insn (gen_vec_shr_v8qi (fold, last, x)); | |
17236 | ||
17237 | next = gen_reg_rtx (vmode); | |
17238 | emit_insn (gen (next, last, fold)); | |
17239 | last = next; | |
17240 | ||
17241 | fold = gen_reg_rtx (vmode); | |
17242 | x = force_reg (SImode, GEN_INT (8)); | |
17243 | emit_insn (gen_vec_shr_v8qi (fold, last, x)); | |
17244 | break; | |
17245 | ||
17246 | default: | |
17247 | gcc_unreachable (); | |
17248 | } | |
17249 | ||
17250 | emit_insn (gen (target, last, fold)); | |
17251 | } | |
17252 | ||
17253 | /* Expand a vector minimum/maximum. */ | |
17254 | ||
17255 | void | |
17256 | mips_expand_vec_minmax (rtx target, rtx op0, rtx op1, | |
17257 | rtx (*cmp) (rtx, rtx, rtx), bool min_p) | |
17258 | { | |
17259 | enum machine_mode vmode = GET_MODE (target); | |
17260 | rtx tc, t0, t1, x; | |
17261 | ||
17262 | tc = gen_reg_rtx (vmode); | |
17263 | t0 = gen_reg_rtx (vmode); | |
17264 | t1 = gen_reg_rtx (vmode); | |
17265 | ||
17266 | /* op0 > op1 */ | |
17267 | emit_insn (cmp (tc, op0, op1)); | |
17268 | ||
17269 | x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0)); | |
17270 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
17271 | ||
17272 | x = gen_rtx_NOT (vmode, tc); | |
17273 | x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1)); | |
17274 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
17275 | ||
17276 | x = gen_rtx_IOR (vmode, t0, t1); | |
17277 | emit_insn (gen_rtx_SET (VOIDmode, target, x)); | |
17278 | } | |
17279 | \f | |
ab77a036 RS |
17280 | /* Initialize the GCC target structure. */ |
17281 | #undef TARGET_ASM_ALIGNED_HI_OP | |
17282 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
17283 | #undef TARGET_ASM_ALIGNED_SI_OP | |
17284 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
17285 | #undef TARGET_ASM_ALIGNED_DI_OP | |
17286 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
a8c1d5f8 | 17287 | |
525c561d AS |
17288 | #undef TARGET_OPTION_OVERRIDE |
17289 | #define TARGET_OPTION_OVERRIDE mips_option_override | |
17290 | ||
506d7b68 PB |
17291 | #undef TARGET_LEGITIMIZE_ADDRESS |
17292 | #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address | |
17293 | ||
ab77a036 RS |
17294 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
17295 | #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue | |
17296 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
17297 | #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue | |
17298 | #undef TARGET_ASM_SELECT_RTX_SECTION | |
17299 | #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section | |
17300 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION | |
17301 | #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section | |
4ca1f68f | 17302 | |
ab77a036 RS |
17303 | #undef TARGET_SCHED_INIT |
17304 | #define TARGET_SCHED_INIT mips_sched_init | |
17305 | #undef TARGET_SCHED_REORDER | |
17306 | #define TARGET_SCHED_REORDER mips_sched_reorder | |
17307 | #undef TARGET_SCHED_REORDER2 | |
646e6f41 | 17308 | #define TARGET_SCHED_REORDER2 mips_sched_reorder2 |
ab77a036 RS |
17309 | #undef TARGET_SCHED_VARIABLE_ISSUE |
17310 | #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue | |
17311 | #undef TARGET_SCHED_ADJUST_COST | |
17312 | #define TARGET_SCHED_ADJUST_COST mips_adjust_cost | |
17313 | #undef TARGET_SCHED_ISSUE_RATE | |
17314 | #define TARGET_SCHED_ISSUE_RATE mips_issue_rate | |
58684fa0 MK |
17315 | #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN |
17316 | #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn | |
17317 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
17318 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle | |
ab77a036 RS |
17319 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
17320 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
17321 | mips_multipass_dfa_lookahead | |
e472d6bf | 17322 | #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P |
a1c4f19f AP |
17323 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
17324 | mips_small_register_classes_for_mode_p | |
4ca1f68f | 17325 | |
ab77a036 RS |
17326 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
17327 | #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall | |
4ca1f68f | 17328 | |
ab77a036 RS |
17329 | #undef TARGET_INSERT_ATTRIBUTES |
17330 | #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes | |
17331 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
17332 | #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes | |
17333 | #undef TARGET_SET_CURRENT_FUNCTION | |
17334 | #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function | |
06a4ab70 | 17335 | |
ab77a036 RS |
17336 | #undef TARGET_VALID_POINTER_MODE |
17337 | #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode | |
faa832a7 AS |
17338 | #undef TARGET_REGISTER_MOVE_COST |
17339 | #define TARGET_REGISTER_MOVE_COST mips_register_move_cost | |
17340 | #undef TARGET_MEMORY_MOVE_COST | |
17341 | #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost | |
ab77a036 RS |
17342 | #undef TARGET_RTX_COSTS |
17343 | #define TARGET_RTX_COSTS mips_rtx_costs | |
17344 | #undef TARGET_ADDRESS_COST | |
17345 | #define TARGET_ADDRESS_COST mips_address_cost | |
06a4ab70 | 17346 | |
ab77a036 RS |
17347 | #undef TARGET_IN_SMALL_DATA_P |
17348 | #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p | |
118ea793 | 17349 | |
ab77a036 RS |
17350 | #undef TARGET_MACHINE_DEPENDENT_REORG |
17351 | #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg | |
118ea793 | 17352 | |
ef78aed6 AS |
17353 | #undef TARGET_PREFERRED_RELOAD_CLASS |
17354 | #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class | |
17355 | ||
ab77a036 RS |
17356 | #undef TARGET_ASM_FILE_START |
17357 | #define TARGET_ASM_FILE_START mips_file_start | |
17358 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
17359 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
118ea793 | 17360 | |
ab77a036 RS |
17361 | #undef TARGET_INIT_LIBFUNCS |
17362 | #define TARGET_INIT_LIBFUNCS mips_init_libfuncs | |
118ea793 | 17363 | |
ab77a036 RS |
17364 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
17365 | #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list | |
d7bd8aeb JJ |
17366 | #undef TARGET_EXPAND_BUILTIN_VA_START |
17367 | #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start | |
ab77a036 RS |
17368 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
17369 | #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr | |
118ea793 | 17370 | |
cde0f3fd PB |
17371 | #undef TARGET_PROMOTE_FUNCTION_MODE |
17372 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
ab77a036 RS |
17373 | #undef TARGET_PROMOTE_PROTOTYPES |
17374 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
118ea793 | 17375 | |
47be3d6d AS |
17376 | #undef TARGET_FUNCTION_VALUE |
17377 | #define TARGET_FUNCTION_VALUE mips_function_value | |
17378 | #undef TARGET_LIBCALL_VALUE | |
17379 | #define TARGET_LIBCALL_VALUE mips_libcall_value | |
17380 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
17381 | #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p | |
ab77a036 RS |
17382 | #undef TARGET_RETURN_IN_MEMORY |
17383 | #define TARGET_RETURN_IN_MEMORY mips_return_in_memory | |
17384 | #undef TARGET_RETURN_IN_MSB | |
17385 | #define TARGET_RETURN_IN_MSB mips_return_in_msb | |
4dbdb061 | 17386 | |
ab77a036 RS |
17387 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
17388 | #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk | |
17389 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
17390 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true | |
4dbdb061 | 17391 | |
6e9e0126 NF |
17392 | #undef TARGET_PRINT_OPERAND |
17393 | #define TARGET_PRINT_OPERAND mips_print_operand | |
17394 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
17395 | #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address | |
17396 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
17397 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p | |
17398 | ||
ab77a036 RS |
17399 | #undef TARGET_SETUP_INCOMING_VARARGS |
17400 | #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs | |
17401 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
17402 | #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming | |
17403 | #undef TARGET_MUST_PASS_IN_STACK | |
17404 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
17405 | #undef TARGET_PASS_BY_REFERENCE | |
17406 | #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference | |
17407 | #undef TARGET_CALLEE_COPIES | |
17408 | #define TARGET_CALLEE_COPIES mips_callee_copies | |
17409 | #undef TARGET_ARG_PARTIAL_BYTES | |
17410 | #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes | |
c8717ea3 NF |
17411 | #undef TARGET_FUNCTION_ARG |
17412 | #define TARGET_FUNCTION_ARG mips_function_arg | |
17413 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
17414 | #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance | |
c2ed6cf8 NF |
17415 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
17416 | #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary | |
cd3a59b3 | 17417 | |
ab77a036 RS |
17418 | #undef TARGET_MODE_REP_EXTENDED |
17419 | #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended | |
912f2dac | 17420 | |
ab77a036 RS |
17421 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
17422 | #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p | |
912f2dac | 17423 | |
ab77a036 RS |
17424 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
17425 | #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p | |
912f2dac | 17426 | |
cc4b5170 RG |
17427 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
17428 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode | |
26983c22 | 17429 | |
ab77a036 RS |
17430 | #undef TARGET_INIT_BUILTINS |
17431 | #define TARGET_INIT_BUILTINS mips_init_builtins | |
7725086e RS |
17432 | #undef TARGET_BUILTIN_DECL |
17433 | #define TARGET_BUILTIN_DECL mips_builtin_decl | |
ab77a036 RS |
17434 | #undef TARGET_EXPAND_BUILTIN |
17435 | #define TARGET_EXPAND_BUILTIN mips_expand_builtin | |
b12cbf2c | 17436 | |
ab77a036 RS |
17437 | #undef TARGET_HAVE_TLS |
17438 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
b12cbf2c | 17439 | |
ab77a036 RS |
17440 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
17441 | #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem | |
a44380d2 | 17442 | |
1a627b35 RS |
17443 | #undef TARGET_LEGITIMATE_CONSTANT_P |
17444 | #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p | |
17445 | ||
ab77a036 RS |
17446 | #undef TARGET_ENCODE_SECTION_INFO |
17447 | #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info | |
a44380d2 | 17448 | |
ab77a036 RS |
17449 | #undef TARGET_ATTRIBUTE_TABLE |
17450 | #define TARGET_ATTRIBUTE_TABLE mips_attribute_table | |
17451 | /* All our function attributes are related to how out-of-line copies should | |
17452 | be compiled or called. They don't in themselves prevent inlining. */ | |
17453 | #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P | |
17454 | #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true | |
a44380d2 | 17455 | |
ab77a036 RS |
17456 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
17457 | #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry | |
076a5ce6 | 17458 | |
ab77a036 RS |
17459 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P |
17460 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p | |
17461 | #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P | |
17462 | #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p | |
076a5ce6 | 17463 | |
ab77a036 RS |
17464 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
17465 | #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes | |
076a5ce6 | 17466 | |
ab77a036 RS |
17467 | #ifdef HAVE_AS_DTPRELWORD |
17468 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
17469 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel | |
17470 | #endif | |
17471 | #undef TARGET_DWARF_REGISTER_SPAN | |
17472 | #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span | |
076a5ce6 | 17473 | |
1afc5373 CF |
17474 | #undef TARGET_ASM_FINAL_POSTSCAN_INSN |
17475 | #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn | |
17476 | ||
c6c3dba9 PB |
17477 | #undef TARGET_LEGITIMATE_ADDRESS_P |
17478 | #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p | |
17479 | ||
b52b1749 AS |
17480 | #undef TARGET_FRAME_POINTER_REQUIRED |
17481 | #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required | |
17482 | ||
7b5cbb57 AS |
17483 | #undef TARGET_CAN_ELIMINATE |
17484 | #define TARGET_CAN_ELIMINATE mips_can_eliminate | |
17485 | ||
5efd84c5 NF |
17486 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
17487 | #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage | |
17488 | ||
a1d29c8c RH |
17489 | #undef TARGET_TRAMPOLINE_INIT |
17490 | #define TARGET_TRAMPOLINE_INIT mips_trampoline_init | |
17491 | ||
b5f5d41d AS |
17492 | #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME |
17493 | #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename | |
17494 | ||
49042313 MX |
17495 | #undef TARGET_SHIFT_TRUNCATION_MASK |
17496 | #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask | |
17497 | ||
e32ea2d1 RS |
17498 | #undef TARGET_PREPARE_PCH_SAVE |
17499 | #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save | |
17500 | ||
7dab511c RH |
17501 | #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK |
17502 | #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok | |
17503 | ||
ab77a036 | 17504 | struct gcc_target targetm = TARGET_INITIALIZER; |
a44380d2 | 17505 | \f |
e2500fed | 17506 | #include "gt-mips.h" |