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dfad12b5 | 1 | /* Subroutines used for MIPS code generation. |
214be03f | 2 | Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
ef78aed6 AS |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
4 | 2011 | |
6fb5fa3c | 5 | Free Software Foundation, Inc. |
cee98a59 | 6 | Contributed by A. Lichnewsky, lich@inria.inria.fr. |
b2a68403 | 7 | Changes by Michael Meissner, meissner@osf.org. |
85f65093 | 8 | 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and |
147255d8 | 9 | Brendan Eich, brendan@microunity.com. |
cee98a59 | 10 | |
7ec022b2 | 11 | This file is part of GCC. |
cee98a59 | 12 | |
7ec022b2 | 13 | GCC is free software; you can redistribute it and/or modify |
cee98a59 | 14 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
cee98a59 MM |
16 | any later version. |
17 | ||
7ec022b2 | 18 | GCC is distributed in the hope that it will be useful, |
cee98a59 MM |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
24 | along with GCC; see the file COPYING3. If not see |
25 | <http://www.gnu.org/licenses/>. */ | |
cee98a59 MM |
26 | |
27 | #include "config.h" | |
50b2596f | 28 | #include "system.h" |
4977bab6 ZW |
29 | #include "coretypes.h" |
30 | #include "tm.h" | |
cee98a59 MM |
31 | #include "rtl.h" |
32 | #include "regs.h" | |
33 | #include "hard-reg-set.h" | |
cee98a59 MM |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
cee98a59 | 36 | #include "insn-attr.h" |
cee98a59 | 37 | #include "recog.h" |
c5c76735 | 38 | #include "output.h" |
cee98a59 | 39 | #include "tree.h" |
49ad7cfa | 40 | #include "function.h" |
cee98a59 | 41 | #include "expr.h" |
c15c90bb | 42 | #include "optabs.h" |
e2ff10a9 | 43 | #include "libfuncs.h" |
cee98a59 | 44 | #include "flags.h" |
2bcb2ab3 | 45 | #include "reload.h" |
bd9f1972 | 46 | #include "tm_p.h" |
d07d525a | 47 | #include "ggc.h" |
7719ffbf | 48 | #include "gstab.h" |
920ae24b RH |
49 | #include "hashtab.h" |
50 | #include "debug.h" | |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
cafe096b | 53 | #include "integrate.h" |
2743a50a | 54 | #include "langhooks.h" |
b85aed9e | 55 | #include "cfglayout.h" |
dc884a86 | 56 | #include "sched-int.h" |
726a989a | 57 | #include "gimple.h" |
912f2dac | 58 | #include "bitmap.h" |
566dfd71 | 59 | #include "diagnostic.h" |
5aa62249 | 60 | #include "target-globals.h" |
96e45421 | 61 | #include "opts.h" |
cee98a59 | 62 | |
65239d20 | 63 | /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ |
108b61d5 RS |
64 | #define UNSPEC_ADDRESS_P(X) \ |
65 | (GET_CODE (X) == UNSPEC \ | |
66 | && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ | |
67 | && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) | |
68 | ||
69 | /* Extract the symbol or label from UNSPEC wrapper X. */ | |
70 | #define UNSPEC_ADDRESS(X) \ | |
71 | XVECEXP (X, 0, 0) | |
72 | ||
73 | /* Extract the symbol type from UNSPEC wrapper X. */ | |
74 | #define UNSPEC_ADDRESS_TYPE(X) \ | |
75 | ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) | |
76 | ||
be763023 | 77 | /* The maximum distance between the top of the stack frame and the |
e1260576 RS |
78 | value $sp has when we save and restore registers. |
79 | ||
80 | The value for normal-mode code must be a SMALL_OPERAND and must | |
81 | preserve the maximum stack alignment. We therefore use a value | |
82 | of 0x7ff0 in this case. | |
83 | ||
84 | MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by | |
85 | up to 0x7f8 bytes and can usually save or restore all the registers | |
86 | that we need to save or restore. (Note that we can only use these | |
87 | instructions for o32, for which the stack alignment is 8 bytes.) | |
88 | ||
89 | We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and | |
90 | RESTORE are not available. We can then use unextended instructions | |
91 | to save and restore registers, and to allocate and deallocate the top | |
92 | part of the frame. */ | |
93 | #define MIPS_MAX_FIRST_STACK_STEP \ | |
94 | (!TARGET_MIPS16 ? 0x7ff0 \ | |
95 | : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \ | |
96 | : TARGET_64BIT ? 0x100 : 0x400) | |
be763023 | 97 | |
dc884a86 RS |
98 | /* True if INSN is a mips.md pattern or asm statement. */ |
99 | #define USEFUL_INSN_P(INSN) \ | |
006b29ab | 100 | (NONDEBUG_INSN_P (INSN) \ |
dc884a86 RS |
101 | && GET_CODE (PATTERN (INSN)) != USE \ |
102 | && GET_CODE (PATTERN (INSN)) != CLOBBER \ | |
103 | && GET_CODE (PATTERN (INSN)) != ADDR_VEC \ | |
104 | && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC) | |
105 | ||
106 | /* If INSN is a delayed branch sequence, return the first instruction | |
107 | in the sequence, otherwise return INSN itself. */ | |
108 | #define SEQ_BEGIN(INSN) \ | |
109 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
110 | ? XVECEXP (PATTERN (INSN), 0, 0) \ | |
111 | : (INSN)) | |
112 | ||
113 | /* Likewise for the last instruction in a delayed branch sequence. */ | |
114 | #define SEQ_END(INSN) \ | |
115 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
116 | ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \ | |
117 | : (INSN)) | |
118 | ||
119 | /* Execute the following loop body with SUBINSN set to each instruction | |
120 | between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */ | |
121 | #define FOR_EACH_SUBINSN(SUBINSN, INSN) \ | |
122 | for ((SUBINSN) = SEQ_BEGIN (INSN); \ | |
123 | (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \ | |
124 | (SUBINSN) = NEXT_INSN (SUBINSN)) | |
cafe096b | 125 | |
e1260576 RS |
126 | /* True if bit BIT is set in VALUE. */ |
127 | #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) | |
128 | ||
c640a3bd RS |
129 | /* Return the opcode for a ptr_mode load of the form: |
130 | ||
131 | l[wd] DEST, OFFSET(BASE). */ | |
132 | #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \ | |
133 | (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \ | |
134 | | ((BASE) << 21) \ | |
135 | | ((DEST) << 16) \ | |
136 | | (OFFSET)) | |
137 | ||
138 | /* Return the opcode to move register SRC into register DEST. */ | |
139 | #define MIPS_MOVE(DEST, SRC) \ | |
140 | ((TARGET_64BIT ? 0x2d : 0x21) \ | |
141 | | ((DEST) << 11) \ | |
142 | | ((SRC) << 21)) | |
143 | ||
144 | /* Return the opcode for: | |
145 | ||
146 | lui DEST, VALUE. */ | |
147 | #define MIPS_LUI(DEST, VALUE) \ | |
148 | ((0xf << 26) | ((DEST) << 16) | (VALUE)) | |
149 | ||
150 | /* Return the opcode to jump to register DEST. */ | |
151 | #define MIPS_JR(DEST) \ | |
152 | (((DEST) << 21) | 0x8) | |
153 | ||
154 | /* Return the opcode for: | |
155 | ||
156 | bal . + (1 + OFFSET) * 4. */ | |
157 | #define MIPS_BAL(OFFSET) \ | |
158 | ((0x1 << 26) | (0x11 << 16) | (OFFSET)) | |
159 | ||
160 | /* Return the usual opcode for a nop. */ | |
161 | #define MIPS_NOP 0 | |
162 | ||
cafe096b EC |
163 | /* Classifies an address. |
164 | ||
cafe096b EC |
165 | ADDRESS_REG |
166 | A natural register + offset address. The register satisfies | |
167 | mips_valid_base_register_p and the offset is a const_arith_operand. | |
168 | ||
169 | ADDRESS_LO_SUM | |
170 | A LO_SUM rtx. The first operand is a valid base register and | |
171 | the second operand is a symbolic address. | |
172 | ||
173 | ADDRESS_CONST_INT | |
174 | A signed 16-bit constant address. | |
175 | ||
176 | ADDRESS_SYMBOLIC: | |
65239d20 | 177 | A constant symbolic address. */ |
cafe096b | 178 | enum mips_address_type { |
cafe096b EC |
179 | ADDRESS_REG, |
180 | ADDRESS_LO_SUM, | |
181 | ADDRESS_CONST_INT, | |
182 | ADDRESS_SYMBOLIC | |
183 | }; | |
184 | ||
41030557 RS |
185 | /* Macros to create an enumeration identifier for a function prototype. */ |
186 | #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B | |
187 | #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C | |
188 | #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D | |
189 | #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E | |
190 | ||
65239d20 RS |
191 | /* Classifies the prototype of a built-in function. */ |
192 | enum mips_function_type { | |
41030557 RS |
193 | #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST, |
194 | #include "config/mips/mips-ftypes.def" | |
195 | #undef DEF_MIPS_FTYPE | |
4ca1f68f RS |
196 | MIPS_MAX_FTYPE_MAX |
197 | }; | |
198 | ||
65239d20 RS |
199 | /* Specifies how a built-in function should be converted into rtl. */ |
200 | enum mips_builtin_type { | |
201 | /* The function corresponds directly to an .md pattern. The return | |
4ca1f68f RS |
202 | value is mapped to operand 0 and the arguments are mapped to |
203 | operands 1 and above. */ | |
204 | MIPS_BUILTIN_DIRECT, | |
205 | ||
65239d20 | 206 | /* The function corresponds directly to an .md pattern. There is no return |
118ea793 CF |
207 | value and the arguments are mapped to operands 0 and above. */ |
208 | MIPS_BUILTIN_DIRECT_NO_TARGET, | |
209 | ||
65239d20 | 210 | /* The function corresponds to a comparison instruction followed by |
4ca1f68f RS |
211 | a mips_cond_move_tf_ps pattern. The first two arguments are the |
212 | values to compare and the second two arguments are the vector | |
213 | operands for the movt.ps or movf.ps instruction (in assembly order). */ | |
214 | MIPS_BUILTIN_MOVF, | |
215 | MIPS_BUILTIN_MOVT, | |
216 | ||
65239d20 | 217 | /* The function corresponds to a V2SF comparison instruction. Operand 0 |
4ca1f68f RS |
218 | of this instruction is the result of the comparison, which has mode |
219 | CCV2 or CCV4. The function arguments are mapped to operands 1 and | |
220 | above. The function's return value is an SImode boolean that is | |
221 | true under the following conditions: | |
222 | ||
223 | MIPS_BUILTIN_CMP_ANY: one of the registers is true | |
224 | MIPS_BUILTIN_CMP_ALL: all of the registers are true | |
225 | MIPS_BUILTIN_CMP_LOWER: the first register is true | |
226 | MIPS_BUILTIN_CMP_UPPER: the second register is true. */ | |
227 | MIPS_BUILTIN_CMP_ANY, | |
228 | MIPS_BUILTIN_CMP_ALL, | |
229 | MIPS_BUILTIN_CMP_UPPER, | |
230 | MIPS_BUILTIN_CMP_LOWER, | |
231 | ||
232 | /* As above, but the instruction only sets a single $fcc register. */ | |
118ea793 CF |
233 | MIPS_BUILTIN_CMP_SINGLE, |
234 | ||
235 | /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ | |
236 | MIPS_BUILTIN_BPOSGE32 | |
4ca1f68f RS |
237 | }; |
238 | ||
65239d20 | 239 | /* Invoke MACRO (COND) for each C.cond.fmt condition. */ |
308cd611 RS |
240 | #define MIPS_FP_CONDITIONS(MACRO) \ |
241 | MACRO (f), \ | |
242 | MACRO (un), \ | |
243 | MACRO (eq), \ | |
244 | MACRO (ueq), \ | |
245 | MACRO (olt), \ | |
246 | MACRO (ult), \ | |
247 | MACRO (ole), \ | |
248 | MACRO (ule), \ | |
249 | MACRO (sf), \ | |
250 | MACRO (ngle), \ | |
251 | MACRO (seq), \ | |
252 | MACRO (ngl), \ | |
253 | MACRO (lt), \ | |
254 | MACRO (nge), \ | |
255 | MACRO (le), \ | |
256 | MACRO (ngt) | |
257 | ||
258 | /* Enumerates the codes above as MIPS_FP_COND_<X>. */ | |
259 | #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X | |
260 | enum mips_fp_condition { | |
261 | MIPS_FP_CONDITIONS (DECLARE_MIPS_COND) | |
262 | }; | |
263 | ||
264 | /* Index X provides the string representation of MIPS_FP_COND_<X>. */ | |
265 | #define STRINGIFY(X) #X | |
266 | static const char *const mips_fp_conditions[] = { | |
267 | MIPS_FP_CONDITIONS (STRINGIFY) | |
268 | }; | |
269 | ||
16dc5c28 | 270 | /* Information about a function's frame layout. */ |
d1b38208 | 271 | struct GTY(()) mips_frame_info { |
37017f4d RS |
272 | /* The size of the frame in bytes. */ |
273 | HOST_WIDE_INT total_size; | |
274 | ||
275 | /* The number of bytes allocated to variables. */ | |
276 | HOST_WIDE_INT var_size; | |
277 | ||
278 | /* The number of bytes allocated to outgoing function arguments. */ | |
279 | HOST_WIDE_INT args_size; | |
280 | ||
281 | /* The number of bytes allocated to the .cprestore slot, or 0 if there | |
282 | is no such slot. */ | |
283 | HOST_WIDE_INT cprestore_size; | |
284 | ||
37017f4d RS |
285 | /* Bit X is set if the function saves or restores GPR X. */ |
286 | unsigned int mask; | |
287 | ||
288 | /* Likewise FPR X. */ | |
289 | unsigned int fmask; | |
290 | ||
e19da24c CF |
291 | /* Likewise doubleword accumulator X ($acX). */ |
292 | unsigned int acc_mask; | |
293 | ||
294 | /* The number of GPRs, FPRs, doubleword accumulators and COP0 | |
295 | registers saved. */ | |
37017f4d RS |
296 | unsigned int num_gp; |
297 | unsigned int num_fp; | |
e19da24c CF |
298 | unsigned int num_acc; |
299 | unsigned int num_cop0_regs; | |
37017f4d | 300 | |
e19da24c CF |
301 | /* The offset of the topmost GPR, FPR, accumulator and COP0-register |
302 | save slots from the top of the frame, or zero if no such slots are | |
303 | needed. */ | |
37017f4d RS |
304 | HOST_WIDE_INT gp_save_offset; |
305 | HOST_WIDE_INT fp_save_offset; | |
e19da24c CF |
306 | HOST_WIDE_INT acc_save_offset; |
307 | HOST_WIDE_INT cop0_save_offset; | |
37017f4d RS |
308 | |
309 | /* Likewise, but giving offsets from the bottom of the frame. */ | |
310 | HOST_WIDE_INT gp_sp_offset; | |
311 | HOST_WIDE_INT fp_sp_offset; | |
e19da24c CF |
312 | HOST_WIDE_INT acc_sp_offset; |
313 | HOST_WIDE_INT cop0_sp_offset; | |
37017f4d | 314 | |
c376dbfb DD |
315 | /* Similar, but the value passed to _mcount. */ |
316 | HOST_WIDE_INT ra_fp_offset; | |
317 | ||
ba6adec4 | 318 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ |
f374e413 RS |
319 | HOST_WIDE_INT arg_pointer_offset; |
320 | ||
ba6adec4 | 321 | /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ |
f374e413 | 322 | HOST_WIDE_INT hard_frame_pointer_offset; |
b2471838 RS |
323 | }; |
324 | ||
d1b38208 | 325 | struct GTY(()) machine_function { |
65239d20 | 326 | /* The register returned by mips16_gp_pseudo_reg; see there for details. */ |
c8d1b2b7 | 327 | rtx mips16_gp_pseudo_rtx; |
b2471838 | 328 | |
4001cd89 RS |
329 | /* The number of extra stack bytes taken up by register varargs. |
330 | This area is allocated by the callee at the very top of the frame. */ | |
331 | int varargs_size; | |
332 | ||
65239d20 | 333 | /* The current frame information, calculated by mips_compute_frame_info. */ |
b2471838 RS |
334 | struct mips_frame_info frame; |
335 | ||
8d9d9172 RS |
336 | /* The register to use as the function's global pointer, or INVALID_REGNUM |
337 | if the function doesn't need one. */ | |
f833ffd4 | 338 | unsigned int global_pointer; |
6f2993e5 | 339 | |
0c433c31 RS |
340 | /* How many instructions it takes to load a label into $AT, or 0 if |
341 | this property hasn't yet been calculated. */ | |
5a486834 | 342 | unsigned int load_label_num_insns; |
0c433c31 | 343 | |
6f2993e5 RS |
344 | /* True if mips_adjust_insn_length should ignore an instruction's |
345 | hazard attribute. */ | |
346 | bool ignore_hazard_length_p; | |
347 | ||
348 | /* True if the whole function is suitable for .set noreorder and | |
349 | .set nomacro. */ | |
350 | bool all_noreorder_p; | |
108b61d5 | 351 | |
0c433c31 RS |
352 | /* True if the function has "inflexible" and "flexible" references |
353 | to the global pointer. See mips_cfun_has_inflexible_gp_ref_p | |
354 | and mips_cfun_has_flexible_gp_ref_p for details. */ | |
355 | bool has_inflexible_gp_insn_p; | |
356 | bool has_flexible_gp_insn_p; | |
357 | ||
358 | /* True if the function's prologue must load the global pointer | |
359 | value into pic_offset_table_rtx and store the same value in | |
360 | the function's cprestore slot (if any). Even if this value | |
361 | is currently false, we may decide to set it to true later; | |
362 | see mips_must_initialize_gp_p () for details. */ | |
363 | bool must_initialize_gp_p; | |
364 | ||
365 | /* True if the current function must restore $gp after any potential | |
366 | clobber. This value is only meaningful during the first post-epilogue | |
367 | split_insns pass; see mips_must_initialize_gp_p () for details. */ | |
368 | bool must_restore_gp_when_clobbered_p; | |
d6076cee | 369 | |
e19da24c CF |
370 | /* True if this is an interrupt handler. */ |
371 | bool interrupt_handler_p; | |
372 | ||
373 | /* True if this is an interrupt handler that uses shadow registers. */ | |
374 | bool use_shadow_register_set_p; | |
375 | ||
376 | /* True if this is an interrupt handler that should keep interrupts | |
377 | masked. */ | |
378 | bool keep_interrupts_masked_p; | |
379 | ||
380 | /* True if this is an interrupt handler that should use DERET | |
381 | instead of ERET. */ | |
382 | bool use_debug_exception_return_p; | |
c8d1b2b7 AO |
383 | }; |
384 | ||
4d72536e | 385 | /* Information about a single argument. */ |
65239d20 | 386 | struct mips_arg_info { |
4d72536e RS |
387 | /* True if the argument is passed in a floating-point register, or |
388 | would have been if we hadn't run out of registers. */ | |
389 | bool fpr_p; | |
390 | ||
4d72536e RS |
391 | /* The number of words passed in registers, rounded up. */ |
392 | unsigned int reg_words; | |
393 | ||
b11a9d5f RS |
394 | /* For EABI, the offset of the first register from GP_ARG_FIRST or |
395 | FP_ARG_FIRST. For other ABIs, the offset of the first register from | |
396 | the start of the ABI's argument structure (see the CUMULATIVE_ARGS | |
397 | comment for details). | |
398 | ||
399 | The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely | |
4d72536e RS |
400 | on the stack. */ |
401 | unsigned int reg_offset; | |
402 | ||
403 | /* The number of words that must be passed on the stack, rounded up. */ | |
404 | unsigned int stack_words; | |
405 | ||
406 | /* The offset from the start of the stack overflow area of the argument's | |
a0ab749a | 407 | first stack word. Only meaningful when STACK_WORDS is nonzero. */ |
4d72536e RS |
408 | unsigned int stack_offset; |
409 | }; | |
c8d1b2b7 | 410 | |
cafe096b EC |
411 | /* Information about an address described by mips_address_type. |
412 | ||
cafe096b EC |
413 | ADDRESS_CONST_INT |
414 | No fields are used. | |
415 | ||
416 | ADDRESS_REG | |
417 | REG is the base register and OFFSET is the constant offset. | |
418 | ||
419 | ADDRESS_LO_SUM | |
65239d20 RS |
420 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE |
421 | is the type of symbol it references. | |
cafe096b EC |
422 | |
423 | ADDRESS_SYMBOLIC | |
65239d20 RS |
424 | SYMBOL_TYPE is the type of symbol that the address references. */ |
425 | struct mips_address_info { | |
108b61d5 | 426 | enum mips_address_type type; |
cafe096b EC |
427 | rtx reg; |
428 | rtx offset; | |
108b61d5 | 429 | enum mips_symbol_type symbol_type; |
cafe096b EC |
430 | }; |
431 | ||
b259a9a6 RS |
432 | /* One stage in a constant building sequence. These sequences have |
433 | the form: | |
434 | ||
435 | A = VALUE[0] | |
436 | A = A CODE[1] VALUE[1] | |
437 | A = A CODE[2] VALUE[2] | |
438 | ... | |
439 | ||
440 | where A is an accumulator, each CODE[i] is a binary rtl operation | |
65239d20 | 441 | and each VALUE[i] is a constant integer. CODE[0] is undefined. */ |
b259a9a6 RS |
442 | struct mips_integer_op { |
443 | enum rtx_code code; | |
444 | unsigned HOST_WIDE_INT value; | |
445 | }; | |
446 | ||
b259a9a6 RS |
447 | /* The largest number of operations needed to load an integer constant. |
448 | The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. | |
449 | When the lowest bit is clear, we can try, but reject a sequence with | |
450 | an extra SLL at the end. */ | |
451 | #define MIPS_MAX_INTEGER_OPS 7 | |
452 | ||
e1260576 RS |
453 | /* Information about a MIPS16e SAVE or RESTORE instruction. */ |
454 | struct mips16e_save_restore_info { | |
455 | /* The number of argument registers saved by a SAVE instruction. | |
456 | 0 for RESTORE instructions. */ | |
457 | unsigned int nargs; | |
458 | ||
459 | /* Bit X is set if the instruction saves or restores GPR X. */ | |
460 | unsigned int mask; | |
461 | ||
462 | /* The total number of bytes to allocate. */ | |
463 | HOST_WIDE_INT size; | |
464 | }; | |
b259a9a6 | 465 | |
faa832a7 AS |
466 | /* Costs of various operations on the different architectures. */ |
467 | ||
468 | struct mips_rtx_cost_data | |
469 | { | |
470 | unsigned short fp_add; | |
471 | unsigned short fp_mult_sf; | |
472 | unsigned short fp_mult_df; | |
473 | unsigned short fp_div_sf; | |
474 | unsigned short fp_div_df; | |
475 | unsigned short int_mult_si; | |
476 | unsigned short int_mult_di; | |
477 | unsigned short int_div_si; | |
478 | unsigned short int_div_di; | |
479 | unsigned short branch_cost; | |
480 | unsigned short memory_latency; | |
481 | }; | |
482 | ||
cee98a59 MM |
483 | /* Global variables for machine-dependent things. */ |
484 | ||
65239d20 RS |
485 | /* The -G setting, or the configuration's default small-data limit if |
486 | no -G option is given. */ | |
487 | static unsigned int mips_small_data_threshold; | |
cee98a59 | 488 | |
65239d20 RS |
489 | /* The number of file directives written by mips_output_filename. */ |
490 | int num_source_filenames; | |
cee98a59 | 491 | |
65239d20 RS |
492 | /* The name that appeared in the last .file directive written by |
493 | mips_output_filename, or "" if mips_output_filename hasn't | |
494 | written anything yet. */ | |
ab77a036 RS |
495 | const char *current_function_file = ""; |
496 | ||
65239d20 RS |
497 | /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */ |
498 | int sdb_label_count; | |
cee98a59 | 499 | |
65239d20 | 500 | /* Arrays that map GCC register numbers to debugger register numbers. */ |
ab77a036 RS |
501 | int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; |
502 | int mips_dwarf_regno[FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 503 | |
65239d20 | 504 | /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */ |
cf5fb4b0 RS |
505 | struct mips_asm_switch mips_noreorder = { "reorder", 0 }; |
506 | struct mips_asm_switch mips_nomacro = { "macro", 0 }; | |
507 | struct mips_asm_switch mips_noat = { "at", 0 }; | |
cee98a59 | 508 | |
65239d20 RS |
509 | /* True if we're writing out a branch-likely instruction rather than a |
510 | normal branch. */ | |
511 | static bool mips_branch_likely; | |
cee98a59 | 512 | |
65239d20 | 513 | /* The current instruction-set architecture. */ |
24609606 | 514 | enum processor mips_arch; |
a27fb29b | 515 | const struct mips_cpu_info *mips_arch_info; |
7dac2f89 | 516 | |
65239d20 | 517 | /* The processor that we should tune the code for. */ |
24609606 | 518 | enum processor mips_tune; |
a27fb29b | 519 | const struct mips_cpu_info *mips_tune_info; |
7dac2f89 | 520 | |
65239d20 | 521 | /* The ISA level associated with mips_arch. */ |
cee98a59 MM |
522 | int mips_isa; |
523 | ||
65239d20 RS |
524 | /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */ |
525 | static const struct mips_cpu_info *mips_isa_option_info; | |
ab77a036 | 526 | |
65239d20 | 527 | /* Which cost information to use. */ |
faa832a7 | 528 | static const struct mips_rtx_cost_data *mips_cost; |
c1bd2d66 | 529 | |
65239d20 | 530 | /* The ambient target flags, excluding MASK_MIPS16. */ |
f9e4a411 | 531 | static int mips_base_target_flags; |
65239d20 RS |
532 | |
533 | /* True if MIPS16 is the default mode. */ | |
60730ade | 534 | bool mips_base_mips16; |
65239d20 RS |
535 | |
536 | /* The ambient values of other global variables. */ | |
f9e4a411 SL |
537 | static int mips_base_schedule_insns; /* flag_schedule_insns */ |
538 | static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */ | |
8d1d0dee | 539 | static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */ |
f9e4a411 SL |
540 | static int mips_base_align_loops; /* align_loops */ |
541 | static int mips_base_align_jumps; /* align_jumps */ | |
542 | static int mips_base_align_functions; /* align_functions */ | |
f9e4a411 | 543 | |
65239d20 RS |
544 | /* Index [M][R] is true if register R is allowed to hold a value of mode M. */ |
545 | bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 546 | |
65239d20 RS |
547 | /* Index C is true if character C is a valid PRINT_OPERAND punctation |
548 | character. */ | |
6e9e0126 | 549 | static bool mips_print_operand_punct[256]; |
cee98a59 | 550 | |
cafe096b EC |
551 | static GTY (()) int mips_output_filename_first_time = 1; |
552 | ||
108b61d5 | 553 | /* mips_split_p[X] is true if symbols of type X can be split by |
65239d20 | 554 | mips_split_symbol. */ |
ea462dd0 | 555 | bool mips_split_p[NUM_SYMBOL_TYPES]; |
108b61d5 | 556 | |
08d0963a RS |
557 | /* mips_split_hi_p[X] is true if the high parts of symbols of type X |
558 | can be split by mips_split_symbol. */ | |
559 | bool mips_split_hi_p[NUM_SYMBOL_TYPES]; | |
560 | ||
108b61d5 RS |
561 | /* mips_lo_relocs[X] is the relocation to use when a symbol of type X |
562 | appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or | |
563 | if they are matched by a special .md file pattern. */ | |
564 | static const char *mips_lo_relocs[NUM_SYMBOL_TYPES]; | |
565 | ||
566 | /* Likewise for HIGHs. */ | |
567 | static const char *mips_hi_relocs[NUM_SYMBOL_TYPES]; | |
568 | ||
5aa62249 RS |
569 | /* Target state for MIPS16. */ |
570 | struct target_globals *mips16_globals; | |
571 | ||
646e6f41 JZ |
572 | /* Cached value of can_issue_more. This is cached in mips_variable_issue hook |
573 | and returned from mips_sched_reorder2. */ | |
574 | static int cached_can_issue_more; | |
575 | ||
65239d20 RS |
576 | /* Index R is the smallest register class that contains register R. */ |
577 | const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { | |
08d0963a | 578 | LEA_REGS, LEA_REGS, M16_REGS, V1_REG, |
2bcb2ab3 | 579 | M16_REGS, M16_REGS, M16_REGS, M16_REGS, |
cafe096b EC |
580 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, |
581 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
08d0963a | 582 | M16_REGS, M16_REGS, LEA_REGS, LEA_REGS, |
cafe096b EC |
583 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, |
584 | T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, | |
585 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
cee98a59 MM |
586 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
587 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
588 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
589 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
590 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
591 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
592 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
593 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
48156a39 | 594 | MD0_REG, MD1_REG, NO_REGS, ST_REGS, |
b8eb88d0 | 595 | ST_REGS, ST_REGS, ST_REGS, ST_REGS, |
cafe096b | 596 | ST_REGS, ST_REGS, ST_REGS, NO_REGS, |
7314c7dd | 597 | NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS, |
d604bca3 MH |
598 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, |
599 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
600 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
601 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
602 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
603 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
604 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
605 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
606 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
607 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
608 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
609 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
610 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
611 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
612 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
613 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
614 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
615 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
616 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
617 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
618 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
619 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
620 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
118ea793 CF |
621 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, |
622 | DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, | |
623 | DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS, | |
624 | ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS | |
cee98a59 MM |
625 | }; |
626 | ||
65239d20 | 627 | /* The value of TARGET_ATTRIBUTE_TABLE. */ |
6bc7bc14 | 628 | static const struct attribute_spec mips_attribute_table[] = { |
62d784f7 KT |
629 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
630 | om_diagnostic } */ | |
631 | { "long_call", 0, 0, false, true, true, NULL, false }, | |
632 | { "far", 0, 0, false, true, true, NULL, false }, | |
633 | { "near", 0, 0, false, true, true, NULL, false }, | |
65239d20 RS |
634 | /* We would really like to treat "mips16" and "nomips16" as type |
635 | attributes, but GCC doesn't provide the hooks we need to support | |
636 | the right conversion rules. As declaration attributes, they affect | |
637 | code generation but don't carry other semantics. */ | |
62d784f7 KT |
638 | { "mips16", 0, 0, true, false, false, NULL, false }, |
639 | { "nomips16", 0, 0, true, false, false, NULL, false }, | |
e19da24c | 640 | /* Allow functions to be specified as interrupt handlers */ |
62d784f7 KT |
641 | { "interrupt", 0, 0, false, true, true, NULL, false }, |
642 | { "use_shadow_register_set", 0, 0, false, true, true, NULL, false }, | |
643 | { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false }, | |
644 | { "use_debug_exception_return", 0, 0, false, true, true, NULL, false }, | |
645 | { NULL, 0, 0, false, false, false, NULL, false } | |
4dbdb061 | 646 | }; |
672a6f42 | 647 | \f |
d371df6f JM |
648 | /* A table describing all the processors GCC knows about; see |
649 | mips-cpus.def for details. */ | |
65239d20 | 650 | static const struct mips_cpu_info mips_cpu_info_table[] = { |
d371df6f JM |
651 | #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \ |
652 | { NAME, CPU, ISA, FLAGS }, | |
653 | #include "mips-cpus.def" | |
654 | #undef MIPS_CPU | |
a27fb29b | 655 | }; |
c1bd2d66 | 656 | |
65239d20 | 657 | /* Default costs. If these are used for a processor we should look |
ff5c4582 | 658 | up the actual costs. */ |
c1bd2d66 EC |
659 | #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ |
660 | COSTS_N_INSNS (7), /* fp_mult_sf */ \ | |
661 | COSTS_N_INSNS (8), /* fp_mult_df */ \ | |
662 | COSTS_N_INSNS (23), /* fp_div_sf */ \ | |
663 | COSTS_N_INSNS (36), /* fp_div_df */ \ | |
664 | COSTS_N_INSNS (10), /* int_mult_si */ \ | |
665 | COSTS_N_INSNS (10), /* int_mult_di */ \ | |
666 | COSTS_N_INSNS (69), /* int_div_si */ \ | |
667 | COSTS_N_INSNS (69), /* int_div_di */ \ | |
668 | 2, /* branch_cost */ \ | |
669 | 4 /* memory_latency */ | |
670 | ||
65239d20 RS |
671 | /* Floating-point costs for processors without an FPU. Just assume that |
672 | all floating-point libcalls are very expensive. */ | |
c1bd2d66 EC |
673 | #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ |
674 | COSTS_N_INSNS (256), /* fp_mult_sf */ \ | |
675 | COSTS_N_INSNS (256), /* fp_mult_df */ \ | |
676 | COSTS_N_INSNS (256), /* fp_div_sf */ \ | |
677 | COSTS_N_INSNS (256) /* fp_div_df */ | |
678 | ||
65239d20 RS |
679 | /* Costs to use when optimizing for size. */ |
680 | static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { | |
681 | COSTS_N_INSNS (1), /* fp_add */ | |
682 | COSTS_N_INSNS (1), /* fp_mult_sf */ | |
683 | COSTS_N_INSNS (1), /* fp_mult_df */ | |
684 | COSTS_N_INSNS (1), /* fp_div_sf */ | |
685 | COSTS_N_INSNS (1), /* fp_div_df */ | |
686 | COSTS_N_INSNS (1), /* int_mult_si */ | |
687 | COSTS_N_INSNS (1), /* int_mult_di */ | |
688 | COSTS_N_INSNS (1), /* int_div_si */ | |
689 | COSTS_N_INSNS (1), /* int_div_di */ | |
690 | 2, /* branch_cost */ | |
691 | 4 /* memory_latency */ | |
692 | }; | |
693 | ||
694 | /* Costs to use when optimizing for speed, indexed by processor. */ | |
24609606 RS |
695 | static const struct mips_rtx_cost_data |
696 | mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = { | |
65239d20 RS |
697 | { /* R3000 */ |
698 | COSTS_N_INSNS (2), /* fp_add */ | |
699 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
700 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
701 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
702 | COSTS_N_INSNS (19), /* fp_div_df */ | |
703 | COSTS_N_INSNS (12), /* int_mult_si */ | |
704 | COSTS_N_INSNS (12), /* int_mult_di */ | |
705 | COSTS_N_INSNS (35), /* int_div_si */ | |
706 | COSTS_N_INSNS (35), /* int_div_di */ | |
707 | 1, /* branch_cost */ | |
708 | 4 /* memory_latency */ | |
709 | }, | |
710 | { /* 4KC */ | |
711 | SOFT_FP_COSTS, | |
712 | COSTS_N_INSNS (6), /* int_mult_si */ | |
713 | COSTS_N_INSNS (6), /* int_mult_di */ | |
714 | COSTS_N_INSNS (36), /* int_div_si */ | |
715 | COSTS_N_INSNS (36), /* int_div_di */ | |
716 | 1, /* branch_cost */ | |
717 | 4 /* memory_latency */ | |
718 | }, | |
719 | { /* 4KP */ | |
720 | SOFT_FP_COSTS, | |
721 | COSTS_N_INSNS (36), /* int_mult_si */ | |
722 | COSTS_N_INSNS (36), /* int_mult_di */ | |
723 | COSTS_N_INSNS (37), /* int_div_si */ | |
724 | COSTS_N_INSNS (37), /* int_div_di */ | |
725 | 1, /* branch_cost */ | |
726 | 4 /* memory_latency */ | |
727 | }, | |
728 | { /* 5KC */ | |
729 | SOFT_FP_COSTS, | |
730 | COSTS_N_INSNS (4), /* int_mult_si */ | |
731 | COSTS_N_INSNS (11), /* int_mult_di */ | |
732 | COSTS_N_INSNS (36), /* int_div_si */ | |
733 | COSTS_N_INSNS (68), /* int_div_di */ | |
734 | 1, /* branch_cost */ | |
735 | 4 /* memory_latency */ | |
736 | }, | |
737 | { /* 5KF */ | |
738 | COSTS_N_INSNS (4), /* fp_add */ | |
739 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
740 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
741 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
742 | COSTS_N_INSNS (32), /* fp_div_df */ | |
743 | COSTS_N_INSNS (4), /* int_mult_si */ | |
744 | COSTS_N_INSNS (11), /* int_mult_di */ | |
745 | COSTS_N_INSNS (36), /* int_div_si */ | |
746 | COSTS_N_INSNS (68), /* int_div_di */ | |
747 | 1, /* branch_cost */ | |
748 | 4 /* memory_latency */ | |
749 | }, | |
750 | { /* 20KC */ | |
751 | COSTS_N_INSNS (4), /* fp_add */ | |
752 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
753 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
754 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
755 | COSTS_N_INSNS (32), /* fp_div_df */ | |
756 | COSTS_N_INSNS (4), /* int_mult_si */ | |
757 | COSTS_N_INSNS (7), /* int_mult_di */ | |
758 | COSTS_N_INSNS (42), /* int_div_si */ | |
759 | COSTS_N_INSNS (72), /* int_div_di */ | |
760 | 1, /* branch_cost */ | |
761 | 4 /* memory_latency */ | |
762 | }, | |
763 | { /* 24KC */ | |
764 | SOFT_FP_COSTS, | |
765 | COSTS_N_INSNS (5), /* int_mult_si */ | |
766 | COSTS_N_INSNS (5), /* int_mult_di */ | |
767 | COSTS_N_INSNS (41), /* int_div_si */ | |
768 | COSTS_N_INSNS (41), /* int_div_di */ | |
769 | 1, /* branch_cost */ | |
770 | 4 /* memory_latency */ | |
771 | }, | |
772 | { /* 24KF2_1 */ | |
773 | COSTS_N_INSNS (8), /* fp_add */ | |
774 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
775 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
776 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
777 | COSTS_N_INSNS (64), /* fp_div_df */ | |
778 | COSTS_N_INSNS (5), /* int_mult_si */ | |
779 | COSTS_N_INSNS (5), /* int_mult_di */ | |
780 | COSTS_N_INSNS (41), /* int_div_si */ | |
781 | COSTS_N_INSNS (41), /* int_div_di */ | |
782 | 1, /* branch_cost */ | |
783 | 4 /* memory_latency */ | |
784 | }, | |
785 | { /* 24KF1_1 */ | |
786 | COSTS_N_INSNS (4), /* fp_add */ | |
787 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
788 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
789 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
790 | COSTS_N_INSNS (32), /* fp_div_df */ | |
791 | COSTS_N_INSNS (5), /* int_mult_si */ | |
792 | COSTS_N_INSNS (5), /* int_mult_di */ | |
793 | COSTS_N_INSNS (41), /* int_div_si */ | |
794 | COSTS_N_INSNS (41), /* int_div_di */ | |
795 | 1, /* branch_cost */ | |
796 | 4 /* memory_latency */ | |
797 | }, | |
798 | { /* 74KC */ | |
799 | SOFT_FP_COSTS, | |
800 | COSTS_N_INSNS (5), /* int_mult_si */ | |
801 | COSTS_N_INSNS (5), /* int_mult_di */ | |
802 | COSTS_N_INSNS (41), /* int_div_si */ | |
803 | COSTS_N_INSNS (41), /* int_div_di */ | |
804 | 1, /* branch_cost */ | |
805 | 4 /* memory_latency */ | |
806 | }, | |
807 | { /* 74KF2_1 */ | |
808 | COSTS_N_INSNS (8), /* fp_add */ | |
809 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
810 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
811 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
812 | COSTS_N_INSNS (64), /* fp_div_df */ | |
813 | COSTS_N_INSNS (5), /* int_mult_si */ | |
814 | COSTS_N_INSNS (5), /* int_mult_di */ | |
815 | COSTS_N_INSNS (41), /* int_div_si */ | |
816 | COSTS_N_INSNS (41), /* int_div_di */ | |
817 | 1, /* branch_cost */ | |
818 | 4 /* memory_latency */ | |
819 | }, | |
820 | { /* 74KF1_1 */ | |
821 | COSTS_N_INSNS (4), /* fp_add */ | |
822 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
823 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
824 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
825 | COSTS_N_INSNS (32), /* fp_div_df */ | |
826 | COSTS_N_INSNS (5), /* int_mult_si */ | |
827 | COSTS_N_INSNS (5), /* int_mult_di */ | |
828 | COSTS_N_INSNS (41), /* int_div_si */ | |
829 | COSTS_N_INSNS (41), /* int_div_di */ | |
830 | 1, /* branch_cost */ | |
831 | 4 /* memory_latency */ | |
832 | }, | |
833 | { /* 74KF3_2 */ | |
834 | COSTS_N_INSNS (6), /* fp_add */ | |
835 | COSTS_N_INSNS (6), /* fp_mult_sf */ | |
836 | COSTS_N_INSNS (7), /* fp_mult_df */ | |
837 | COSTS_N_INSNS (25), /* fp_div_sf */ | |
838 | COSTS_N_INSNS (48), /* fp_div_df */ | |
839 | COSTS_N_INSNS (5), /* int_mult_si */ | |
840 | COSTS_N_INSNS (5), /* int_mult_di */ | |
841 | COSTS_N_INSNS (41), /* int_div_si */ | |
842 | COSTS_N_INSNS (41), /* int_div_di */ | |
843 | 1, /* branch_cost */ | |
844 | 4 /* memory_latency */ | |
845 | }, | |
33db2060 MS |
846 | { /* Loongson-2E */ |
847 | DEFAULT_COSTS | |
848 | }, | |
849 | { /* Loongson-2F */ | |
850 | DEFAULT_COSTS | |
851 | }, | |
98824c6f MS |
852 | { /* Loongson-3A */ |
853 | DEFAULT_COSTS | |
854 | }, | |
65239d20 RS |
855 | { /* M4k */ |
856 | DEFAULT_COSTS | |
d97e6aca AN |
857 | }, |
858 | /* Octeon */ | |
859 | { | |
860 | SOFT_FP_COSTS, | |
861 | COSTS_N_INSNS (5), /* int_mult_si */ | |
862 | COSTS_N_INSNS (5), /* int_mult_di */ | |
863 | COSTS_N_INSNS (72), /* int_div_si */ | |
864 | COSTS_N_INSNS (72), /* int_div_di */ | |
865 | 1, /* branch_cost */ | |
866 | 4 /* memory_latency */ | |
65239d20 RS |
867 | }, |
868 | { /* R3900 */ | |
869 | COSTS_N_INSNS (2), /* fp_add */ | |
870 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
871 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
872 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
873 | COSTS_N_INSNS (19), /* fp_div_df */ | |
874 | COSTS_N_INSNS (2), /* int_mult_si */ | |
875 | COSTS_N_INSNS (2), /* int_mult_di */ | |
876 | COSTS_N_INSNS (35), /* int_div_si */ | |
877 | COSTS_N_INSNS (35), /* int_div_di */ | |
878 | 1, /* branch_cost */ | |
879 | 4 /* memory_latency */ | |
880 | }, | |
881 | { /* R6000 */ | |
882 | COSTS_N_INSNS (3), /* fp_add */ | |
883 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
884 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
885 | COSTS_N_INSNS (15), /* fp_div_sf */ | |
886 | COSTS_N_INSNS (16), /* fp_div_df */ | |
887 | COSTS_N_INSNS (17), /* int_mult_si */ | |
888 | COSTS_N_INSNS (17), /* int_mult_di */ | |
889 | COSTS_N_INSNS (38), /* int_div_si */ | |
890 | COSTS_N_INSNS (38), /* int_div_di */ | |
891 | 2, /* branch_cost */ | |
892 | 6 /* memory_latency */ | |
893 | }, | |
894 | { /* R4000 */ | |
895 | COSTS_N_INSNS (6), /* fp_add */ | |
896 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
897 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
898 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
899 | COSTS_N_INSNS (36), /* fp_div_df */ | |
900 | COSTS_N_INSNS (10), /* int_mult_si */ | |
901 | COSTS_N_INSNS (10), /* int_mult_di */ | |
902 | COSTS_N_INSNS (69), /* int_div_si */ | |
903 | COSTS_N_INSNS (69), /* int_div_di */ | |
904 | 2, /* branch_cost */ | |
905 | 6 /* memory_latency */ | |
906 | }, | |
907 | { /* R4100 */ | |
908 | DEFAULT_COSTS | |
909 | }, | |
910 | { /* R4111 */ | |
911 | DEFAULT_COSTS | |
912 | }, | |
913 | { /* R4120 */ | |
914 | DEFAULT_COSTS | |
915 | }, | |
916 | { /* R4130 */ | |
917 | /* The only costs that appear to be updated here are | |
918 | integer multiplication. */ | |
919 | SOFT_FP_COSTS, | |
920 | COSTS_N_INSNS (4), /* int_mult_si */ | |
921 | COSTS_N_INSNS (6), /* int_mult_di */ | |
922 | COSTS_N_INSNS (69), /* int_div_si */ | |
923 | COSTS_N_INSNS (69), /* int_div_di */ | |
924 | 1, /* branch_cost */ | |
925 | 4 /* memory_latency */ | |
926 | }, | |
927 | { /* R4300 */ | |
928 | DEFAULT_COSTS | |
929 | }, | |
930 | { /* R4600 */ | |
931 | DEFAULT_COSTS | |
932 | }, | |
933 | { /* R4650 */ | |
934 | DEFAULT_COSTS | |
935 | }, | |
936 | { /* R5000 */ | |
937 | COSTS_N_INSNS (6), /* fp_add */ | |
938 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
939 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
940 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
941 | COSTS_N_INSNS (36), /* fp_div_df */ | |
942 | COSTS_N_INSNS (5), /* int_mult_si */ | |
943 | COSTS_N_INSNS (5), /* int_mult_di */ | |
944 | COSTS_N_INSNS (36), /* int_div_si */ | |
945 | COSTS_N_INSNS (36), /* int_div_di */ | |
946 | 1, /* branch_cost */ | |
947 | 4 /* memory_latency */ | |
948 | }, | |
949 | { /* R5400 */ | |
950 | COSTS_N_INSNS (6), /* fp_add */ | |
951 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
952 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
953 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
954 | COSTS_N_INSNS (59), /* fp_div_df */ | |
955 | COSTS_N_INSNS (3), /* int_mult_si */ | |
956 | COSTS_N_INSNS (4), /* int_mult_di */ | |
957 | COSTS_N_INSNS (42), /* int_div_si */ | |
958 | COSTS_N_INSNS (74), /* int_div_di */ | |
959 | 1, /* branch_cost */ | |
960 | 4 /* memory_latency */ | |
961 | }, | |
962 | { /* R5500 */ | |
963 | COSTS_N_INSNS (6), /* fp_add */ | |
964 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
965 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
966 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
967 | COSTS_N_INSNS (59), /* fp_div_df */ | |
968 | COSTS_N_INSNS (5), /* int_mult_si */ | |
969 | COSTS_N_INSNS (9), /* int_mult_di */ | |
970 | COSTS_N_INSNS (42), /* int_div_si */ | |
971 | COSTS_N_INSNS (74), /* int_div_di */ | |
972 | 1, /* branch_cost */ | |
973 | 4 /* memory_latency */ | |
974 | }, | |
975 | { /* R7000 */ | |
976 | /* The only costs that are changed here are | |
977 | integer multiplication. */ | |
978 | COSTS_N_INSNS (6), /* fp_add */ | |
979 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
980 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
981 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
982 | COSTS_N_INSNS (36), /* fp_div_df */ | |
983 | COSTS_N_INSNS (5), /* int_mult_si */ | |
984 | COSTS_N_INSNS (9), /* int_mult_di */ | |
985 | COSTS_N_INSNS (69), /* int_div_si */ | |
986 | COSTS_N_INSNS (69), /* int_div_di */ | |
987 | 1, /* branch_cost */ | |
988 | 4 /* memory_latency */ | |
989 | }, | |
990 | { /* R8000 */ | |
991 | DEFAULT_COSTS | |
992 | }, | |
993 | { /* R9000 */ | |
994 | /* The only costs that are changed here are | |
995 | integer multiplication. */ | |
996 | COSTS_N_INSNS (6), /* fp_add */ | |
997 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
998 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
999 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1000 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1001 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1002 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1003 | COSTS_N_INSNS (69), /* int_div_si */ | |
1004 | COSTS_N_INSNS (69), /* int_div_di */ | |
1005 | 1, /* branch_cost */ | |
1006 | 4 /* memory_latency */ | |
1007 | }, | |
7a3446ec JK |
1008 | { /* R1x000 */ |
1009 | COSTS_N_INSNS (2), /* fp_add */ | |
1010 | COSTS_N_INSNS (2), /* fp_mult_sf */ | |
1011 | COSTS_N_INSNS (2), /* fp_mult_df */ | |
1012 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
1013 | COSTS_N_INSNS (19), /* fp_div_df */ | |
1014 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1015 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1016 | COSTS_N_INSNS (34), /* int_div_si */ | |
1017 | COSTS_N_INSNS (66), /* int_div_di */ | |
1018 | 1, /* branch_cost */ | |
1019 | 4 /* memory_latency */ | |
1020 | }, | |
65239d20 RS |
1021 | { /* SB1 */ |
1022 | /* These costs are the same as the SB-1A below. */ | |
1023 | COSTS_N_INSNS (4), /* fp_add */ | |
1024 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1025 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1026 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1027 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1028 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1029 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1030 | COSTS_N_INSNS (36), /* int_div_si */ | |
1031 | COSTS_N_INSNS (68), /* int_div_di */ | |
1032 | 1, /* branch_cost */ | |
1033 | 4 /* memory_latency */ | |
1034 | }, | |
1035 | { /* SB1-A */ | |
1036 | /* These costs are the same as the SB-1 above. */ | |
1037 | COSTS_N_INSNS (4), /* fp_add */ | |
1038 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1039 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1040 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1041 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1042 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1043 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1044 | COSTS_N_INSNS (36), /* int_div_si */ | |
1045 | COSTS_N_INSNS (68), /* int_div_di */ | |
1046 | 1, /* branch_cost */ | |
1047 | 4 /* memory_latency */ | |
1048 | }, | |
1049 | { /* SR71000 */ | |
1050 | DEFAULT_COSTS | |
1051 | }, | |
d0ae31b0 | 1052 | { /* XLR */ |
0051ef59 | 1053 | SOFT_FP_COSTS, |
d0ae31b0 SM |
1054 | COSTS_N_INSNS (8), /* int_mult_si */ |
1055 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1056 | COSTS_N_INSNS (72), /* int_div_si */ | |
1057 | COSTS_N_INSNS (72), /* int_div_di */ | |
1058 | 1, /* branch_cost */ | |
1059 | 4 /* memory_latency */ | |
1060 | } | |
65239d20 | 1061 | }; |
a27fb29b | 1062 | \f |
ee3ee488 | 1063 | static rtx mips_find_pic_call_symbol (rtx, rtx, bool); |
faa832a7 AS |
1064 | static int mips_register_move_cost (enum machine_mode, reg_class_t, |
1065 | reg_class_t); | |
c2ed6cf8 | 1066 | static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree); |
b53da244 | 1067 | \f |
65239d20 | 1068 | /* This hash table keeps track of implicit "mips16" and "nomips16" attributes |
ab77a036 | 1069 | for -mflip_mips16. It maps decl names onto a boolean mode setting. */ |
d1b38208 | 1070 | struct GTY (()) mflip_mips16_entry { |
ab77a036 RS |
1071 | const char *name; |
1072 | bool mips16_p; | |
1073 | }; | |
1074 | static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab; | |
4dbdb061 | 1075 | |
ab77a036 | 1076 | /* Hash table callbacks for mflip_mips16_htab. */ |
4dbdb061 | 1077 | |
ab77a036 RS |
1078 | static hashval_t |
1079 | mflip_mips16_htab_hash (const void *entry) | |
1080 | { | |
1081 | return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name); | |
1082 | } | |
912f2dac | 1083 | |
ab77a036 RS |
1084 | static int |
1085 | mflip_mips16_htab_eq (const void *entry, const void *name) | |
1086 | { | |
1087 | return strcmp (((const struct mflip_mips16_entry *) entry)->name, | |
1088 | (const char *) name) == 0; | |
1089 | } | |
ea462dd0 | 1090 | |
65239d20 RS |
1091 | /* True if -mflip-mips16 should next add an attribute for the default MIPS16 |
1092 | mode, false if it should next add an attribute for the opposite mode. */ | |
1093 | static GTY(()) bool mips16_flipper; | |
cd3a59b3 | 1094 | |
ab77a036 RS |
1095 | /* DECL is a function that needs a default "mips16" or "nomips16" attribute |
1096 | for -mflip-mips16. Return true if it should use "mips16" and false if | |
1097 | it should use "nomips16". */ | |
a44380d2 | 1098 | |
ab77a036 RS |
1099 | static bool |
1100 | mflip_mips16_use_mips16_p (tree decl) | |
1101 | { | |
1102 | struct mflip_mips16_entry *entry; | |
1103 | const char *name; | |
1104 | hashval_t hash; | |
1105 | void **slot; | |
076a5ce6 | 1106 | |
ab77a036 RS |
1107 | /* Use the opposite of the command-line setting for anonymous decls. */ |
1108 | if (!DECL_NAME (decl)) | |
1109 | return !mips_base_mips16; | |
cd3a59b3 | 1110 | |
ab77a036 RS |
1111 | if (!mflip_mips16_htab) |
1112 | mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash, | |
1113 | mflip_mips16_htab_eq, NULL); | |
cd3a59b3 | 1114 | |
ab77a036 RS |
1115 | name = IDENTIFIER_POINTER (DECL_NAME (decl)); |
1116 | hash = htab_hash_string (name); | |
1117 | slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT); | |
1118 | entry = (struct mflip_mips16_entry *) *slot; | |
1119 | if (!entry) | |
1120 | { | |
1121 | mips16_flipper = !mips16_flipper; | |
a9429e29 | 1122 | entry = ggc_alloc_mflip_mips16_entry (); |
ab77a036 RS |
1123 | entry->name = name; |
1124 | entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16; | |
1125 | *slot = entry; | |
1126 | } | |
1127 | return entry->mips16_p; | |
1128 | } | |
1129 | \f | |
cd3a59b3 SL |
1130 | /* Predicates to test for presence of "near" and "far"/"long_call" |
1131 | attributes on the given TYPE. */ | |
1132 | ||
1133 | static bool | |
3101faab | 1134 | mips_near_type_p (const_tree type) |
cd3a59b3 SL |
1135 | { |
1136 | return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; | |
1137 | } | |
1138 | ||
1139 | static bool | |
3101faab | 1140 | mips_far_type_p (const_tree type) |
cd3a59b3 SL |
1141 | { |
1142 | return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL | |
1143 | || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); | |
1144 | } | |
1145 | ||
65239d20 | 1146 | /* Similar predicates for "mips16"/"nomips16" function attributes. */ |
f9e4a411 SL |
1147 | |
1148 | static bool | |
9a6dfb47 | 1149 | mips_mips16_decl_p (const_tree decl) |
f9e4a411 | 1150 | { |
9a6dfb47 | 1151 | return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL; |
f9e4a411 SL |
1152 | } |
1153 | ||
1154 | static bool | |
9a6dfb47 | 1155 | mips_nomips16_decl_p (const_tree decl) |
f9e4a411 | 1156 | { |
9a6dfb47 | 1157 | return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL; |
f9e4a411 | 1158 | } |
cd3a59b3 | 1159 | |
e19da24c CF |
1160 | /* Check if the interrupt attribute is set for a function. */ |
1161 | ||
1162 | static bool | |
1163 | mips_interrupt_type_p (tree type) | |
1164 | { | |
1165 | return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; | |
1166 | } | |
1167 | ||
1168 | /* Check if the attribute to use shadow register set is set for a function. */ | |
1169 | ||
1170 | static bool | |
1171 | mips_use_shadow_register_set_p (tree type) | |
1172 | { | |
1173 | return lookup_attribute ("use_shadow_register_set", | |
1174 | TYPE_ATTRIBUTES (type)) != NULL; | |
1175 | } | |
1176 | ||
1177 | /* Check if the attribute to keep interrupts masked is set for a function. */ | |
1178 | ||
1179 | static bool | |
1180 | mips_keep_interrupts_masked_p (tree type) | |
1181 | { | |
1182 | return lookup_attribute ("keep_interrupts_masked", | |
1183 | TYPE_ATTRIBUTES (type)) != NULL; | |
1184 | } | |
1185 | ||
1186 | /* Check if the attribute to use debug exception return is set for | |
1187 | a function. */ | |
1188 | ||
1189 | static bool | |
1190 | mips_use_debug_exception_return_p (tree type) | |
1191 | { | |
1192 | return lookup_attribute ("use_debug_exception_return", | |
1193 | TYPE_ATTRIBUTES (type)) != NULL; | |
1194 | } | |
1195 | ||
ab77a036 RS |
1196 | /* Return true if function DECL is a MIPS16 function. Return the ambient |
1197 | setting if DECL is null. */ | |
cd3a59b3 | 1198 | |
ab77a036 RS |
1199 | static bool |
1200 | mips_use_mips16_mode_p (tree decl) | |
cd3a59b3 | 1201 | { |
ab77a036 RS |
1202 | if (decl) |
1203 | { | |
1204 | /* Nested functions must use the same frame pointer as their | |
1205 | parent and must therefore use the same ISA mode. */ | |
1206 | tree parent = decl_function_context (decl); | |
1207 | if (parent) | |
1208 | decl = parent; | |
1209 | if (mips_mips16_decl_p (decl)) | |
1210 | return true; | |
1211 | if (mips_nomips16_decl_p (decl)) | |
1212 | return false; | |
1213 | } | |
1214 | return mips_base_mips16; | |
1215 | } | |
1216 | ||
65239d20 | 1217 | /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ |
ab77a036 RS |
1218 | |
1219 | static int | |
1220 | mips_comp_type_attributes (const_tree type1, const_tree type2) | |
1221 | { | |
cd3a59b3 SL |
1222 | /* Disallow mixed near/far attributes. */ |
1223 | if (mips_far_type_p (type1) && mips_near_type_p (type2)) | |
1224 | return 0; | |
1225 | if (mips_near_type_p (type1) && mips_far_type_p (type2)) | |
1226 | return 0; | |
cd3a59b3 SL |
1227 | return 1; |
1228 | } | |
ab77a036 RS |
1229 | |
1230 | /* Implement TARGET_INSERT_ATTRIBUTES. */ | |
1231 | ||
1232 | static void | |
1233 | mips_insert_attributes (tree decl, tree *attributes) | |
1234 | { | |
1235 | const char *name; | |
1236 | bool mips16_p, nomips16_p; | |
1237 | ||
1238 | /* Check for "mips16" and "nomips16" attributes. */ | |
1239 | mips16_p = lookup_attribute ("mips16", *attributes) != NULL; | |
1240 | nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL; | |
1241 | if (TREE_CODE (decl) != FUNCTION_DECL) | |
1242 | { | |
1243 | if (mips16_p) | |
1244 | error ("%qs attribute only applies to functions", "mips16"); | |
1245 | if (nomips16_p) | |
1246 | error ("%qs attribute only applies to functions", "nomips16"); | |
1247 | } | |
1248 | else | |
1249 | { | |
1250 | mips16_p |= mips_mips16_decl_p (decl); | |
1251 | nomips16_p |= mips_nomips16_decl_p (decl); | |
1252 | if (mips16_p || nomips16_p) | |
1253 | { | |
65239d20 | 1254 | /* DECL cannot be simultaneously "mips16" and "nomips16". */ |
ab77a036 | 1255 | if (mips16_p && nomips16_p) |
29d08eba | 1256 | error ("%qE cannot have both %<mips16%> and " |
ab77a036 | 1257 | "%<nomips16%> attributes", |
29d08eba | 1258 | DECL_NAME (decl)); |
ab77a036 RS |
1259 | } |
1260 | else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl)) | |
1261 | { | |
1262 | /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a | |
1263 | "mips16" attribute, arbitrarily pick one. We must pick the same | |
1264 | setting for duplicate declarations of a function. */ | |
1265 | name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16"; | |
1266 | *attributes = tree_cons (get_identifier (name), NULL, *attributes); | |
1267 | } | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ | |
1272 | ||
1273 | static tree | |
1274 | mips_merge_decl_attributes (tree olddecl, tree newdecl) | |
1275 | { | |
1276 | /* The decls' "mips16" and "nomips16" attributes must match exactly. */ | |
1277 | if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl)) | |
29d08eba JM |
1278 | error ("%qE redeclared with conflicting %qs attributes", |
1279 | DECL_NAME (newdecl), "mips16"); | |
ab77a036 | 1280 | if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl)) |
29d08eba JM |
1281 | error ("%qE redeclared with conflicting %qs attributes", |
1282 | DECL_NAME (newdecl), "nomips16"); | |
ab77a036 RS |
1283 | |
1284 | return merge_attributes (DECL_ATTRIBUTES (olddecl), | |
1285 | DECL_ATTRIBUTES (newdecl)); | |
1286 | } | |
cee98a59 | 1287 | \f |
e1260576 RS |
1288 | /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR |
1289 | and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */ | |
1290 | ||
1291 | static void | |
1292 | mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr) | |
1293 | { | |
47ac44d6 | 1294 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
e1260576 RS |
1295 | { |
1296 | *base_ptr = XEXP (x, 0); | |
1297 | *offset_ptr = INTVAL (XEXP (x, 1)); | |
1298 | } | |
1299 | else | |
1300 | { | |
1301 | *base_ptr = x; | |
1302 | *offset_ptr = 0; | |
1303 | } | |
1304 | } | |
1305 | \f | |
ab77a036 RS |
1306 | static unsigned int mips_build_integer (struct mips_integer_op *, |
1307 | unsigned HOST_WIDE_INT); | |
1308 | ||
65239d20 | 1309 | /* A subroutine of mips_build_integer, with the same interface. |
ab77a036 RS |
1310 | Assume that the final action in the sequence should be a left shift. */ |
1311 | ||
1312 | static unsigned int | |
1313 | mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value) | |
1314 | { | |
1315 | unsigned int i, shift; | |
1316 | ||
1317 | /* Shift VALUE right until its lowest bit is set. Shift arithmetically | |
1318 | since signed numbers are easier to load than unsigned ones. */ | |
1319 | shift = 0; | |
1320 | while ((value & 1) == 0) | |
1321 | value /= 2, shift++; | |
1322 | ||
1323 | i = mips_build_integer (codes, value); | |
1324 | codes[i].code = ASHIFT; | |
1325 | codes[i].value = shift; | |
1326 | return i + 1; | |
1327 | } | |
1328 | ||
ab77a036 RS |
1329 | /* As for mips_build_shift, but assume that the final action will be |
1330 | an IOR or PLUS operation. */ | |
1331 | ||
1332 | static unsigned int | |
1333 | mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) | |
1334 | { | |
1335 | unsigned HOST_WIDE_INT high; | |
1336 | unsigned int i; | |
1337 | ||
1338 | high = value & ~(unsigned HOST_WIDE_INT) 0xffff; | |
1339 | if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000) | |
1340 | { | |
65239d20 RS |
1341 | /* The constant is too complex to load with a simple LUI/ORI pair, |
1342 | so we want to give the recursive call as many trailing zeros as | |
1343 | possible. In this case, we know bit 16 is set and that the | |
1344 | low 16 bits form a negative number. If we subtract that number | |
1345 | from VALUE, we will clear at least the lowest 17 bits, maybe more. */ | |
ab77a036 RS |
1346 | i = mips_build_integer (codes, CONST_HIGH_PART (value)); |
1347 | codes[i].code = PLUS; | |
1348 | codes[i].value = CONST_LOW_PART (value); | |
1349 | } | |
1350 | else | |
1351 | { | |
65239d20 RS |
1352 | /* Either this is a simple LUI/ORI pair, or clearing the lowest 16 |
1353 | bits gives a value with at least 17 trailing zeros. */ | |
ab77a036 RS |
1354 | i = mips_build_integer (codes, high); |
1355 | codes[i].code = IOR; | |
1356 | codes[i].value = value & 0xffff; | |
1357 | } | |
1358 | return i + 1; | |
1359 | } | |
1360 | ||
ab77a036 RS |
1361 | /* Fill CODES with a sequence of rtl operations to load VALUE. |
1362 | Return the number of operations needed. */ | |
1363 | ||
1364 | static unsigned int | |
1365 | mips_build_integer (struct mips_integer_op *codes, | |
1366 | unsigned HOST_WIDE_INT value) | |
1367 | { | |
1368 | if (SMALL_OPERAND (value) | |
1369 | || SMALL_OPERAND_UNSIGNED (value) | |
1370 | || LUI_OPERAND (value)) | |
1371 | { | |
1372 | /* The value can be loaded with a single instruction. */ | |
1373 | codes[0].code = UNKNOWN; | |
1374 | codes[0].value = value; | |
1375 | return 1; | |
1376 | } | |
1377 | else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value))) | |
1378 | { | |
1379 | /* Either the constant is a simple LUI/ORI combination or its | |
1380 | lowest bit is set. We don't want to shift in this case. */ | |
1381 | return mips_build_lower (codes, value); | |
1382 | } | |
1383 | else if ((value & 0xffff) == 0) | |
1384 | { | |
1385 | /* The constant will need at least three actions. The lowest | |
1386 | 16 bits are clear, so the final action will be a shift. */ | |
1387 | return mips_build_shift (codes, value); | |
1388 | } | |
1389 | else | |
1390 | { | |
1391 | /* The final action could be a shift, add or inclusive OR. | |
1392 | Rather than use a complex condition to select the best | |
1393 | approach, try both mips_build_shift and mips_build_lower | |
1394 | and pick the one that gives the shortest sequence. | |
1395 | Note that this case is only used once per constant. */ | |
1396 | struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS]; | |
1397 | unsigned int cost, alt_cost; | |
1398 | ||
1399 | cost = mips_build_shift (codes, value); | |
1400 | alt_cost = mips_build_lower (alt_codes, value); | |
1401 | if (alt_cost < cost) | |
1402 | { | |
1403 | memcpy (codes, alt_codes, alt_cost * sizeof (codes[0])); | |
1404 | cost = alt_cost; | |
1405 | } | |
1406 | return cost; | |
1407 | } | |
1408 | } | |
1409 | \f | |
1a627b35 RS |
1410 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
1411 | ||
1412 | static bool | |
1413 | mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
1414 | { | |
1415 | return mips_const_insns (x) > 0; | |
1416 | } | |
1417 | \f | |
08d0963a RS |
1418 | /* Return true if symbols of type TYPE require a GOT access. */ |
1419 | ||
1420 | static bool | |
1421 | mips_got_symbol_type_p (enum mips_symbol_type type) | |
1422 | { | |
1423 | switch (type) | |
1424 | { | |
1425 | case SYMBOL_GOT_PAGE_OFST: | |
1426 | case SYMBOL_GOT_DISP: | |
1427 | return true; | |
1428 | ||
1429 | default: | |
1430 | return false; | |
1431 | } | |
1432 | } | |
1433 | ||
ab77a036 RS |
1434 | /* Return true if X is a thread-local symbol. */ |
1435 | ||
1436 | static bool | |
65239d20 | 1437 | mips_tls_symbol_p (rtx x) |
ab77a036 RS |
1438 | { |
1439 | return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
1440 | } | |
1441 | ||
08e7ceb3 RS |
1442 | /* Return true if SYMBOL_REF X is associated with a global symbol |
1443 | (in the STB_GLOBAL sense). */ | |
1444 | ||
1445 | static bool | |
3101faab | 1446 | mips_global_symbol_p (const_rtx x) |
08e7ceb3 | 1447 | { |
65239d20 | 1448 | const_tree decl = SYMBOL_REF_DECL (x); |
08e7ceb3 | 1449 | |
08e7ceb3 | 1450 | if (!decl) |
08d0963a | 1451 | return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x); |
08e7ceb3 RS |
1452 | |
1453 | /* Weakref symbols are not TREE_PUBLIC, but their targets are global | |
1454 | or weak symbols. Relocations in the object file will be against | |
1455 | the target symbol, so it's that symbol's binding that matters here. */ | |
1456 | return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl)); | |
1457 | } | |
1458 | ||
08d0963a RS |
1459 | /* Return true if function X is a libgcc MIPS16 stub function. */ |
1460 | ||
1461 | static bool | |
1462 | mips16_stub_function_p (const_rtx x) | |
1463 | { | |
1464 | return (GET_CODE (x) == SYMBOL_REF | |
1465 | && strncmp (XSTR (x, 0), "__mips16_", 9) == 0); | |
1466 | } | |
1467 | ||
1468 | /* Return true if function X is a locally-defined and locally-binding | |
1469 | MIPS16 function. */ | |
1470 | ||
1471 | static bool | |
1472 | mips16_local_function_p (const_rtx x) | |
1473 | { | |
1474 | return (GET_CODE (x) == SYMBOL_REF | |
1475 | && SYMBOL_REF_LOCAL_P (x) | |
1476 | && !SYMBOL_REF_EXTERNAL_P (x) | |
1477 | && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x))); | |
1478 | } | |
1479 | ||
08e7ceb3 RS |
1480 | /* Return true if SYMBOL_REF X binds locally. */ |
1481 | ||
1482 | static bool | |
3101faab | 1483 | mips_symbol_binds_local_p (const_rtx x) |
08e7ceb3 RS |
1484 | { |
1485 | return (SYMBOL_REF_DECL (x) | |
1486 | ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) | |
1487 | : SYMBOL_REF_LOCAL_P (x)); | |
1488 | } | |
1489 | ||
a318179e RS |
1490 | /* Return true if rtx constants of mode MODE should be put into a small |
1491 | data section. */ | |
1492 | ||
1493 | static bool | |
1494 | mips_rtx_constant_in_small_data_p (enum machine_mode mode) | |
1495 | { | |
1496 | return (!TARGET_EMBEDDED_DATA | |
1497 | && TARGET_LOCAL_SDATA | |
65239d20 | 1498 | && GET_MODE_SIZE (mode) <= mips_small_data_threshold); |
a318179e RS |
1499 | } |
1500 | ||
ab77a036 RS |
1501 | /* Return true if X should not be moved directly into register $25. |
1502 | We need this because many versions of GAS will treat "la $25,foo" as | |
1503 | part of a call sequence and so allow a global "foo" to be lazily bound. */ | |
1504 | ||
1505 | bool | |
1506 | mips_dangerous_for_la25_p (rtx x) | |
1507 | { | |
1508 | return (!TARGET_EXPLICIT_RELOCS | |
1509 | && TARGET_USE_GOT | |
1510 | && GET_CODE (x) == SYMBOL_REF | |
1511 | && mips_global_symbol_p (x)); | |
1512 | } | |
1513 | ||
08d0963a RS |
1514 | /* Return true if calls to X might need $25 to be valid on entry. */ |
1515 | ||
1516 | bool | |
1517 | mips_use_pic_fn_addr_reg_p (const_rtx x) | |
1518 | { | |
1519 | if (!TARGET_USE_PIC_FN_ADDR_REG) | |
1520 | return false; | |
1521 | ||
1522 | /* MIPS16 stub functions are guaranteed not to use $25. */ | |
1523 | if (mips16_stub_function_p (x)) | |
1524 | return false; | |
1525 | ||
e21d5757 DJ |
1526 | if (GET_CODE (x) == SYMBOL_REF) |
1527 | { | |
1528 | /* If PLTs and copy relocations are available, the static linker | |
1529 | will make sure that $25 is valid on entry to the target function. */ | |
1530 | if (TARGET_ABICALLS_PIC0) | |
1531 | return false; | |
1532 | ||
1533 | /* Locally-defined functions use absolute accesses to set up | |
1534 | the global pointer. */ | |
1535 | if (TARGET_ABSOLUTE_ABICALLS | |
1536 | && mips_symbol_binds_local_p (x) | |
1537 | && !SYMBOL_REF_EXTERNAL_P (x)) | |
1538 | return false; | |
1539 | } | |
08d0963a RS |
1540 | |
1541 | return true; | |
1542 | } | |
1543 | ||
280fcbfa RS |
1544 | /* Return the method that should be used to access SYMBOL_REF or |
1545 | LABEL_REF X in context CONTEXT. */ | |
cafe096b EC |
1546 | |
1547 | static enum mips_symbol_type | |
3101faab | 1548 | mips_classify_symbol (const_rtx x, enum mips_symbol_context context) |
cee98a59 | 1549 | { |
8cb6400c RS |
1550 | if (TARGET_RTP_PIC) |
1551 | return SYMBOL_GOT_DISP; | |
1552 | ||
cafe096b | 1553 | if (GET_CODE (x) == LABEL_REF) |
76cbf5bf | 1554 | { |
4377fad9 RS |
1555 | /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16 |
1556 | code and if we know that the label is in the current function's | |
1557 | text section. LABEL_REFs are used for jump tables as well as | |
1558 | text labels, so we must check whether jump tables live in the | |
1559 | text section. */ | |
1560 | if (TARGET_MIPS16_SHORT_JUMP_TABLES | |
1561 | && !LABEL_REF_NONLOCAL_P (x)) | |
67da85da | 1562 | return SYMBOL_PC_RELATIVE; |
65239d20 | 1563 | |
d9870b7e | 1564 | if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) |
08e7ceb3 | 1565 | return SYMBOL_GOT_PAGE_OFST; |
65239d20 | 1566 | |
67da85da | 1567 | return SYMBOL_ABSOLUTE; |
76cbf5bf | 1568 | } |
cee98a59 | 1569 | |
7ad769fe | 1570 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
2bcb2ab3 | 1571 | |
69229b81 DJ |
1572 | if (SYMBOL_REF_TLS_MODEL (x)) |
1573 | return SYMBOL_TLS; | |
1574 | ||
cafe096b EC |
1575 | if (CONSTANT_POOL_ADDRESS_P (x)) |
1576 | { | |
c93c5160 RS |
1577 | if (TARGET_MIPS16_TEXT_LOADS) |
1578 | return SYMBOL_PC_RELATIVE; | |
1579 | ||
1580 | if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM) | |
67da85da | 1581 | return SYMBOL_PC_RELATIVE; |
cee98a59 | 1582 | |
a318179e | 1583 | if (mips_rtx_constant_in_small_data_p (get_pool_mode (x))) |
67da85da | 1584 | return SYMBOL_GP_RELATIVE; |
cafe096b EC |
1585 | } |
1586 | ||
3ac25120 RS |
1587 | /* Do not use small-data accesses for weak symbols; they may end up |
1588 | being zero. */ | |
65239d20 | 1589 | if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x)) |
67da85da | 1590 | return SYMBOL_GP_RELATIVE; |
b8898790 | 1591 | |
e06e2776 RS |
1592 | /* Don't use GOT accesses for locally-binding symbols when -mno-shared |
1593 | is in effect. */ | |
e21d5757 | 1594 | if (TARGET_ABICALLS_PIC2 |
e06e2776 | 1595 | && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))) |
f6149877 | 1596 | { |
08e7ceb3 RS |
1597 | /* There are three cases to consider: |
1598 | ||
1599 | - o32 PIC (either with or without explicit relocs) | |
1600 | - n32/n64 PIC without explicit relocs | |
1601 | - n32/n64 PIC with explicit relocs | |
1602 | ||
1603 | In the first case, both local and global accesses will use an | |
1604 | R_MIPS_GOT16 relocation. We must correctly predict which of | |
1605 | the two semantics (local or global) the assembler and linker | |
1606 | will apply. The choice depends on the symbol's binding rather | |
1607 | than its visibility. | |
f6149877 | 1608 | |
08e7ceb3 RS |
1609 | In the second case, the assembler will not use R_MIPS_GOT16 |
1610 | relocations, but it chooses between local and global accesses | |
1611 | in the same way as for o32 PIC. | |
1612 | ||
1613 | In the third case we have more freedom since both forms of | |
1614 | access will work for any kind of symbol. However, there seems | |
1615 | little point in doing things differently. */ | |
1616 | if (mips_global_symbol_p (x)) | |
1617 | return SYMBOL_GOT_DISP; | |
1618 | ||
1619 | return SYMBOL_GOT_PAGE_OFST; | |
f6149877 | 1620 | } |
cafe096b | 1621 | |
c93c5160 | 1622 | if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL) |
e06e2776 | 1623 | return SYMBOL_FORCE_TO_MEM; |
65239d20 | 1624 | |
67da85da | 1625 | return SYMBOL_ABSOLUTE; |
cee98a59 MM |
1626 | } |
1627 | ||
65239d20 RS |
1628 | /* Classify the base of symbolic expression X, given that X appears in |
1629 | context CONTEXT. */ | |
6d992de0 RS |
1630 | |
1631 | static enum mips_symbol_type | |
1632 | mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context) | |
1633 | { | |
1634 | rtx offset; | |
1635 | ||
1636 | split_const (x, &x, &offset); | |
1637 | if (UNSPEC_ADDRESS_P (x)) | |
1638 | return UNSPEC_ADDRESS_TYPE (x); | |
1639 | ||
1640 | return mips_classify_symbol (x, context); | |
1641 | } | |
1642 | ||
6de36441 | 1643 | /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN |
65239d20 | 1644 | is the alignment in bytes of SYMBOL_REF X. */ |
8b5fb3a3 DD |
1645 | |
1646 | static bool | |
1647 | mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset) | |
1648 | { | |
65239d20 | 1649 | HOST_WIDE_INT align; |
8b5fb3a3 | 1650 | |
65239d20 RS |
1651 | align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1; |
1652 | return IN_RANGE (offset, 0, align - 1); | |
8b5fb3a3 DD |
1653 | } |
1654 | ||
280fcbfa RS |
1655 | /* Return true if X is a symbolic constant that can be used in context |
1656 | CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ | |
108b61d5 | 1657 | |
96a30b18 | 1658 | bool |
280fcbfa RS |
1659 | mips_symbolic_constant_p (rtx x, enum mips_symbol_context context, |
1660 | enum mips_symbol_type *symbol_type) | |
108b61d5 | 1661 | { |
7ffb5e78 | 1662 | rtx offset; |
108b61d5 | 1663 | |
7ffb5e78 | 1664 | split_const (x, &x, &offset); |
108b61d5 | 1665 | if (UNSPEC_ADDRESS_P (x)) |
8b5fb3a3 DD |
1666 | { |
1667 | *symbol_type = UNSPEC_ADDRESS_TYPE (x); | |
1668 | x = UNSPEC_ADDRESS (x); | |
1669 | } | |
108b61d5 | 1670 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) |
69229b81 | 1671 | { |
280fcbfa | 1672 | *symbol_type = mips_classify_symbol (x, context); |
69229b81 DJ |
1673 | if (*symbol_type == SYMBOL_TLS) |
1674 | return false; | |
1675 | } | |
108b61d5 RS |
1676 | else |
1677 | return false; | |
1678 | ||
7ffb5e78 | 1679 | if (offset == const0_rtx) |
108b61d5 RS |
1680 | return true; |
1681 | ||
1682 | /* Check whether a nonzero offset is valid for the underlying | |
1683 | relocations. */ | |
1684 | switch (*symbol_type) | |
1685 | { | |
67da85da | 1686 | case SYMBOL_ABSOLUTE: |
e06e2776 | 1687 | case SYMBOL_FORCE_TO_MEM: |
c93c5160 | 1688 | case SYMBOL_32_HIGH: |
e245bd81 RS |
1689 | case SYMBOL_64_HIGH: |
1690 | case SYMBOL_64_MID: | |
1691 | case SYMBOL_64_LOW: | |
62973ffe RS |
1692 | /* If the target has 64-bit pointers and the object file only |
1693 | supports 32-bit symbols, the values of those symbols will be | |
1694 | sign-extended. In this case we can't allow an arbitrary offset | |
1695 | in case the 32-bit value X + OFFSET has a different sign from X. */ | |
1696 | if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS) | |
7ffb5e78 | 1697 | return offset_within_block_p (x, INTVAL (offset)); |
62973ffe RS |
1698 | |
1699 | /* In other cases the relocations can handle any offset. */ | |
108b61d5 RS |
1700 | return true; |
1701 | ||
67da85da | 1702 | case SYMBOL_PC_RELATIVE: |
76cbf5bf RS |
1703 | /* Allow constant pool references to be converted to LABEL+CONSTANT. |
1704 | In this case, we no longer have access to the underlying constant, | |
1705 | but the original symbol-based access was known to be valid. */ | |
1706 | if (GET_CODE (x) == LABEL_REF) | |
1707 | return true; | |
1708 | ||
1709 | /* Fall through. */ | |
1710 | ||
67da85da | 1711 | case SYMBOL_GP_RELATIVE: |
62973ffe | 1712 | /* Make sure that the offset refers to something within the |
7ffb5e78 | 1713 | same object block. This should guarantee that the final |
62973ffe | 1714 | PC- or GP-relative offset is within the 16-bit limit. */ |
7ffb5e78 | 1715 | return offset_within_block_p (x, INTVAL (offset)); |
108b61d5 | 1716 | |
08e7ceb3 | 1717 | case SYMBOL_GOT_PAGE_OFST: |
108b61d5 | 1718 | case SYMBOL_GOTOFF_PAGE: |
08e7ceb3 RS |
1719 | /* If the symbol is global, the GOT entry will contain the symbol's |
1720 | address, and we will apply a 16-bit offset after loading it. | |
1721 | If the symbol is local, the linker should provide enough local | |
1722 | GOT entries for a 16-bit offset, but larger offsets may lead | |
1723 | to GOT overflow. */ | |
7ffb5e78 | 1724 | return SMALL_INT (offset); |
108b61d5 | 1725 | |
8b5fb3a3 DD |
1726 | case SYMBOL_TPREL: |
1727 | case SYMBOL_DTPREL: | |
1728 | /* There is no carry between the HI and LO REL relocations, so the | |
1729 | offset is only valid if we know it won't lead to such a carry. */ | |
1730 | return mips_offset_within_alignment_p (x, INTVAL (offset)); | |
1731 | ||
08e7ceb3 RS |
1732 | case SYMBOL_GOT_DISP: |
1733 | case SYMBOL_GOTOFF_DISP: | |
108b61d5 RS |
1734 | case SYMBOL_GOTOFF_CALL: |
1735 | case SYMBOL_GOTOFF_LOADGP: | |
69229b81 DJ |
1736 | case SYMBOL_TLSGD: |
1737 | case SYMBOL_TLSLDM: | |
69229b81 DJ |
1738 | case SYMBOL_GOTTPREL: |
1739 | case SYMBOL_TLS: | |
8cb6400c | 1740 | case SYMBOL_HALF: |
108b61d5 RS |
1741 | return false; |
1742 | } | |
7ad769fe | 1743 | gcc_unreachable (); |
108b61d5 | 1744 | } |
ab77a036 RS |
1745 | \f |
1746 | /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a | |
1747 | single instruction. We rely on the fact that, in the worst case, | |
1748 | all instructions involved in a MIPS16 address calculation are usually | |
1749 | extended ones. */ | |
108b61d5 | 1750 | |
ab77a036 RS |
1751 | static int |
1752 | mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode) | |
cee98a59 | 1753 | { |
ab77a036 | 1754 | switch (type) |
bcbc6b7f | 1755 | { |
ab77a036 RS |
1756 | case SYMBOL_ABSOLUTE: |
1757 | /* When using 64-bit symbols, we need 5 preparatory instructions, | |
1758 | such as: | |
bcbc6b7f | 1759 | |
ab77a036 RS |
1760 | lui $at,%highest(symbol) |
1761 | daddiu $at,$at,%higher(symbol) | |
1762 | dsll $at,$at,16 | |
1763 | daddiu $at,$at,%hi(symbol) | |
1764 | dsll $at,$at,16 | |
bcbc6b7f | 1765 | |
ab77a036 | 1766 | The final address is then $at + %lo(symbol). With 32-bit |
65239d20 RS |
1767 | symbols we just need a preparatory LUI for normal mode and |
1768 | a preparatory LI and SLL for MIPS16. */ | |
ab77a036 | 1769 | return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; |
bcbc6b7f | 1770 | |
ab77a036 RS |
1771 | case SYMBOL_GP_RELATIVE: |
1772 | /* Treat GP-relative accesses as taking a single instruction on | |
1773 | MIPS16 too; the copy of $gp can often be shared. */ | |
1774 | return 1; | |
b8eb88d0 | 1775 | |
67da85da | 1776 | case SYMBOL_PC_RELATIVE: |
65239d20 RS |
1777 | /* PC-relative constants can be only be used with ADDIUPC, |
1778 | DADDIUPC, LWPC and LDPC. */ | |
fbb96ac5 RS |
1779 | if (mode == MAX_MACHINE_MODE |
1780 | || GET_MODE_SIZE (mode) == 4 | |
1781 | || GET_MODE_SIZE (mode) == 8) | |
1782 | return 1; | |
1783 | ||
65239d20 | 1784 | /* The constant must be loaded using ADDIUPC or DADDIUPC first. */ |
fbb96ac5 | 1785 | return 0; |
b8eb88d0 | 1786 | |
e06e2776 | 1787 | case SYMBOL_FORCE_TO_MEM: |
206c2d7a RS |
1788 | /* LEAs will be converted into constant-pool references by |
1789 | mips_reorg. */ | |
1790 | if (mode == MAX_MACHINE_MODE) | |
1791 | return 1; | |
1792 | ||
65239d20 | 1793 | /* The constant must be loaded and then dereferenced. */ |
e06e2776 RS |
1794 | return 0; |
1795 | ||
08e7ceb3 | 1796 | case SYMBOL_GOT_DISP: |
fbb96ac5 RS |
1797 | /* The constant will have to be loaded from the GOT before it |
1798 | is used in an address. */ | |
1799 | if (mode != MAX_MACHINE_MODE) | |
1800 | return 0; | |
1801 | ||
1802 | /* Fall through. */ | |
1803 | ||
1804 | case SYMBOL_GOT_PAGE_OFST: | |
65239d20 RS |
1805 | /* Unless -funit-at-a-time is in effect, we can't be sure whether the |
1806 | local/global classification is accurate. The worst cases are: | |
2bcb2ab3 | 1807 | |
f6149877 RS |
1808 | (1) For local symbols when generating o32 or o64 code. The assembler |
1809 | will use: | |
108b61d5 | 1810 | |
f6149877 RS |
1811 | lw $at,%got(symbol) |
1812 | nop | |
108b61d5 | 1813 | |
f6149877 | 1814 | ...and the final address will be $at + %lo(symbol). |
108b61d5 | 1815 | |
f6149877 RS |
1816 | (2) For global symbols when -mxgot. The assembler will use: |
1817 | ||
1818 | lui $at,%got_hi(symbol) | |
1819 | (d)addu $at,$at,$gp | |
1820 | ||
1821 | ...and the final address will be $at + %got_lo(symbol). */ | |
1822 | return 3; | |
108b61d5 RS |
1823 | |
1824 | case SYMBOL_GOTOFF_PAGE: | |
08e7ceb3 | 1825 | case SYMBOL_GOTOFF_DISP: |
108b61d5 RS |
1826 | case SYMBOL_GOTOFF_CALL: |
1827 | case SYMBOL_GOTOFF_LOADGP: | |
c93c5160 | 1828 | case SYMBOL_32_HIGH: |
e245bd81 RS |
1829 | case SYMBOL_64_HIGH: |
1830 | case SYMBOL_64_MID: | |
1831 | case SYMBOL_64_LOW: | |
69229b81 DJ |
1832 | case SYMBOL_TLSGD: |
1833 | case SYMBOL_TLSLDM: | |
1834 | case SYMBOL_DTPREL: | |
1835 | case SYMBOL_GOTTPREL: | |
1836 | case SYMBOL_TPREL: | |
fbb96ac5 RS |
1837 | case SYMBOL_HALF: |
1838 | /* A 16-bit constant formed by a single relocation, or a 32-bit | |
1839 | constant formed from a high 16-bit relocation and a low 16-bit | |
65239d20 RS |
1840 | relocation. Use mips_split_p to determine which. 32-bit |
1841 | constants need an "lui; addiu" sequence for normal mode and | |
1842 | an "li; sll; addiu" sequence for MIPS16 mode. */ | |
c93c5160 | 1843 | return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2; |
69229b81 DJ |
1844 | |
1845 | case SYMBOL_TLS: | |
1846 | /* We don't treat a bare TLS symbol as a constant. */ | |
1847 | return 0; | |
2bcb2ab3 | 1848 | } |
7ad769fe | 1849 | gcc_unreachable (); |
cafe096b | 1850 | } |
2bcb2ab3 | 1851 | |
fbb96ac5 RS |
1852 | /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed |
1853 | to load symbols of type TYPE into a register. Return 0 if the given | |
1854 | type of symbol cannot be used as an immediate operand. | |
1855 | ||
1856 | Otherwise, return the number of instructions needed to load or store | |
1857 | values of mode MODE to or from addresses of type TYPE. Return 0 if | |
1858 | the given type of symbol is not valid in addresses. | |
1859 | ||
1860 | In both cases, treat extended MIPS16 instructions as two instructions. */ | |
1861 | ||
1862 | static int | |
1863 | mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode) | |
1864 | { | |
1865 | return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1); | |
1866 | } | |
65239d20 RS |
1867 | \f |
1868 | /* A for_each_rtx callback. Stop the search if *X references a | |
1869 | thread-local symbol. */ | |
96a30b18 | 1870 | |
ab77a036 RS |
1871 | static int |
1872 | mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
96a30b18 | 1873 | { |
65239d20 | 1874 | return mips_tls_symbol_p (*x); |
96a30b18 | 1875 | } |
2bcb2ab3 | 1876 | |
65239d20 | 1877 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
cee98a59 | 1878 | |
cafe096b | 1879 | static bool |
1a627b35 | 1880 | mips_cannot_force_const_mem (enum machine_mode mode, rtx x) |
cee98a59 | 1881 | { |
08d0963a | 1882 | enum mips_symbol_type type; |
ab77a036 RS |
1883 | rtx base, offset; |
1884 | ||
08d0963a RS |
1885 | /* There is no assembler syntax for expressing an address-sized |
1886 | high part. */ | |
1887 | if (GET_CODE (x) == HIGH) | |
1888 | return true; | |
1889 | ||
1890 | /* As an optimization, reject constants that mips_legitimize_move | |
1891 | can expand inline. | |
1892 | ||
1893 | Suppose we have a multi-instruction sequence that loads constant C | |
1894 | into register R. If R does not get allocated a hard register, and | |
1895 | R is used in an operand that allows both registers and memory | |
1896 | references, reload will consider forcing C into memory and using | |
1897 | one of the instruction's memory alternatives. Returning false | |
1898 | here will force it to use an input reload instead. */ | |
1a627b35 | 1899 | if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x)) |
08d0963a | 1900 | return true; |
ab77a036 | 1901 | |
08d0963a RS |
1902 | split_const (x, &base, &offset); |
1903 | if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type) | |
1904 | && type != SYMBOL_FORCE_TO_MEM) | |
1905 | { | |
1906 | /* The same optimization as for CONST_INT. */ | |
1907 | if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0) | |
ab77a036 RS |
1908 | return true; |
1909 | ||
08d0963a RS |
1910 | /* If MIPS16 constant pools live in the text section, they should |
1911 | not refer to anything that might need run-time relocation. */ | |
1912 | if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type)) | |
ab77a036 | 1913 | return true; |
cafe096b | 1914 | } |
ab77a036 | 1915 | |
65239d20 RS |
1916 | /* TLS symbols must be computed by mips_legitimize_move. */ |
1917 | if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL)) | |
ab77a036 RS |
1918 | return true; |
1919 | ||
cafe096b EC |
1920 | return false; |
1921 | } | |
cee98a59 | 1922 | |
ab77a036 RS |
1923 | /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for |
1924 | constants when we're using a per-function constant pool. */ | |
cee98a59 | 1925 | |
ab77a036 RS |
1926 | static bool |
1927 | mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1928 | const_rtx x ATTRIBUTE_UNUSED) | |
1929 | { | |
1930 | return !TARGET_MIPS16_PCREL_LOADS; | |
1931 | } | |
1932 | \f | |
65239d20 RS |
1933 | /* Return true if register REGNO is a valid base register for mode MODE. |
1934 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
cee98a59 | 1935 | |
cafe096b | 1936 | int |
65239d20 RS |
1937 | mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, |
1938 | bool strict_p) | |
cafe096b | 1939 | { |
ab77a036 RS |
1940 | if (!HARD_REGISTER_NUM_P (regno)) |
1941 | { | |
65239d20 | 1942 | if (!strict_p) |
ab77a036 RS |
1943 | return true; |
1944 | regno = reg_renumber[regno]; | |
1945 | } | |
cafe096b | 1946 | |
ab77a036 RS |
1947 | /* These fake registers will be eliminated to either the stack or |
1948 | hard frame pointer, both of which are usually valid base registers. | |
1949 | Reload deals with the cases where the eliminated form isn't valid. */ | |
1950 | if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) | |
1951 | return true; | |
1952 | ||
65239d20 | 1953 | /* In MIPS16 mode, the stack pointer can only address word and doubleword |
ab77a036 RS |
1954 | values, nothing smaller. There are two problems here: |
1955 | ||
1956 | (a) Instantiating virtual registers can introduce new uses of the | |
1957 | stack pointer. If these virtual registers are valid addresses, | |
1958 | the stack pointer should be too. | |
1959 | ||
1960 | (b) Most uses of the stack pointer are not made explicit until | |
1961 | FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated. | |
1962 | We don't know until that stage whether we'll be eliminating to the | |
1963 | stack pointer (which needs the restriction) or the hard frame | |
1964 | pointer (which doesn't). | |
1965 | ||
1966 | All in all, it seems more consistent to only enforce this restriction | |
1967 | during and after reload. */ | |
1968 | if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) | |
65239d20 | 1969 | return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; |
ab77a036 RS |
1970 | |
1971 | return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); | |
1972 | } | |
1973 | ||
65239d20 RS |
1974 | /* Return true if X is a valid base register for mode MODE. |
1975 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
ab77a036 RS |
1976 | |
1977 | static bool | |
65239d20 | 1978 | mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p) |
ab77a036 | 1979 | { |
65239d20 | 1980 | if (!strict_p && GET_CODE (x) == SUBREG) |
ab77a036 RS |
1981 | x = SUBREG_REG (x); |
1982 | ||
1983 | return (REG_P (x) | |
65239d20 | 1984 | && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); |
ab77a036 RS |
1985 | } |
1986 | ||
fa21a761 RS |
1987 | /* Return true if, for every base register BASE_REG, (plus BASE_REG X) |
1988 | can address a value of mode MODE. */ | |
1989 | ||
1990 | static bool | |
1991 | mips_valid_offset_p (rtx x, enum machine_mode mode) | |
1992 | { | |
1993 | /* Check that X is a signed 16-bit number. */ | |
1994 | if (!const_arith_operand (x, Pmode)) | |
1995 | return false; | |
1996 | ||
1997 | /* We may need to split multiword moves, so make sure that every word | |
1998 | is accessible. */ | |
1999 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2000 | && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) | |
2001 | return false; | |
2002 | ||
2003 | return true; | |
2004 | } | |
2005 | ||
2006 | /* Return true if a LO_SUM can address a value of mode MODE when the | |
2007 | LO_SUM symbol has type SYMBOL_TYPE. */ | |
2008 | ||
2009 | static bool | |
2010 | mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode) | |
2011 | { | |
2012 | /* Check that symbols of type SYMBOL_TYPE can be used to access values | |
2013 | of mode MODE. */ | |
2014 | if (mips_symbol_insns (symbol_type, mode) == 0) | |
2015 | return false; | |
2016 | ||
2017 | /* Check that there is a known low-part relocation. */ | |
2018 | if (mips_lo_relocs[symbol_type] == NULL) | |
2019 | return false; | |
2020 | ||
2021 | /* We may need to split multiword moves, so make sure that each word | |
2022 | can be accessed without inducing a carry. This is mainly needed | |
2023 | for o64, which has historically only guaranteed 64-bit alignment | |
2024 | for 128-bit types. */ | |
2025 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2026 | && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) | |
2027 | return false; | |
2028 | ||
2029 | return true; | |
2030 | } | |
2031 | ||
ab77a036 | 2032 | /* Return true if X is a valid address for machine mode MODE. If it is, |
65239d20 RS |
2033 | fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in |
2034 | effect. */ | |
ab77a036 RS |
2035 | |
2036 | static bool | |
2037 | mips_classify_address (struct mips_address_info *info, rtx x, | |
65239d20 | 2038 | enum machine_mode mode, bool strict_p) |
ab77a036 RS |
2039 | { |
2040 | switch (GET_CODE (x)) | |
2041 | { | |
2042 | case REG: | |
2043 | case SUBREG: | |
2044 | info->type = ADDRESS_REG; | |
2045 | info->reg = x; | |
2046 | info->offset = const0_rtx; | |
65239d20 | 2047 | return mips_valid_base_register_p (info->reg, mode, strict_p); |
ab77a036 RS |
2048 | |
2049 | case PLUS: | |
2050 | info->type = ADDRESS_REG; | |
2051 | info->reg = XEXP (x, 0); | |
2052 | info->offset = XEXP (x, 1); | |
65239d20 | 2053 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2054 | && mips_valid_offset_p (info->offset, mode)); |
ab77a036 RS |
2055 | |
2056 | case LO_SUM: | |
2057 | info->type = ADDRESS_LO_SUM; | |
2058 | info->reg = XEXP (x, 0); | |
2059 | info->offset = XEXP (x, 1); | |
2060 | /* We have to trust the creator of the LO_SUM to do something vaguely | |
2061 | sane. Target-independent code that creates a LO_SUM should also | |
2062 | create and verify the matching HIGH. Target-independent code that | |
2063 | adds an offset to a LO_SUM must prove that the offset will not | |
2064 | induce a carry. Failure to do either of these things would be | |
2065 | a bug, and we are not required to check for it here. The MIPS | |
2066 | backend itself should only create LO_SUMs for valid symbolic | |
2067 | constants, with the high part being either a HIGH or a copy | |
2068 | of _gp. */ | |
2069 | info->symbol_type | |
2070 | = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM); | |
65239d20 | 2071 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2072 | && mips_valid_lo_sum_p (info->symbol_type, mode)); |
ab77a036 RS |
2073 | |
2074 | case CONST_INT: | |
2075 | /* Small-integer addresses don't occur very often, but they | |
2076 | are legitimate if $0 is a valid base register. */ | |
2077 | info->type = ADDRESS_CONST_INT; | |
2078 | return !TARGET_MIPS16 && SMALL_INT (x); | |
2079 | ||
2080 | case CONST: | |
2081 | case LABEL_REF: | |
2082 | case SYMBOL_REF: | |
2083 | info->type = ADDRESS_SYMBOLIC; | |
2084 | return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM, | |
2085 | &info->symbol_type) | |
2086 | && mips_symbol_insns (info->symbol_type, mode) > 0 | |
2087 | && !mips_split_p[info->symbol_type]); | |
2088 | ||
2089 | default: | |
2090 | return false; | |
2091 | } | |
2092 | } | |
2093 | ||
c6c3dba9 | 2094 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ |
ab77a036 | 2095 | |
c6c3dba9 | 2096 | static bool |
65239d20 | 2097 | mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) |
ab77a036 RS |
2098 | { |
2099 | struct mips_address_info addr; | |
2100 | ||
65239d20 | 2101 | return mips_classify_address (&addr, x, mode, strict_p); |
ab77a036 RS |
2102 | } |
2103 | ||
2104 | /* Return true if X is a legitimate $sp-based address for mode MDOE. */ | |
2105 | ||
2106 | bool | |
2107 | mips_stack_address_p (rtx x, enum machine_mode mode) | |
2108 | { | |
2109 | struct mips_address_info addr; | |
2110 | ||
2111 | return (mips_classify_address (&addr, x, mode, false) | |
2112 | && addr.type == ADDRESS_REG | |
2113 | && addr.reg == stack_pointer_rtx); | |
2114 | } | |
2115 | ||
65239d20 RS |
2116 | /* Return true if ADDR matches the pattern for the LWXS load scaled indexed |
2117 | address instruction. Note that such addresses are not considered | |
331d9186 | 2118 | legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use |
65239d20 | 2119 | is so restricted. */ |
ab77a036 RS |
2120 | |
2121 | static bool | |
2122 | mips_lwxs_address_p (rtx addr) | |
2123 | { | |
2124 | if (ISA_HAS_LWXS | |
2125 | && GET_CODE (addr) == PLUS | |
2126 | && REG_P (XEXP (addr, 1))) | |
2127 | { | |
2128 | rtx offset = XEXP (addr, 0); | |
2129 | if (GET_CODE (offset) == MULT | |
2130 | && REG_P (XEXP (offset, 0)) | |
47ac44d6 | 2131 | && CONST_INT_P (XEXP (offset, 1)) |
ab77a036 RS |
2132 | && INTVAL (XEXP (offset, 1)) == 4) |
2133 | return true; | |
2134 | } | |
2135 | return false; | |
2136 | } | |
65239d20 RS |
2137 | \f |
2138 | /* Return true if a value at OFFSET bytes from base register BASE can be | |
2139 | accessed using an unextended MIPS16 instruction. MODE is the mode of | |
2140 | the value. | |
ab77a036 RS |
2141 | |
2142 | Usually the offset in an unextended instruction is a 5-bit field. | |
65239d20 RS |
2143 | The offset is unsigned and shifted left once for LH and SH, twice |
2144 | for LW and SW, and so on. An exception is LWSP and SWSP, which have | |
2145 | an 8-bit immediate field that's shifted left twice. */ | |
ab77a036 RS |
2146 | |
2147 | static bool | |
65239d20 RS |
2148 | mips16_unextended_reference_p (enum machine_mode mode, rtx base, |
2149 | unsigned HOST_WIDE_INT offset) | |
ab77a036 | 2150 | { |
65239d20 | 2151 | if (offset % GET_MODE_SIZE (mode) == 0) |
ab77a036 RS |
2152 | { |
2153 | if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) | |
65239d20 RS |
2154 | return offset < 256U * GET_MODE_SIZE (mode); |
2155 | return offset < 32U * GET_MODE_SIZE (mode); | |
ab77a036 RS |
2156 | } |
2157 | return false; | |
2158 | } | |
2159 | ||
ab77a036 | 2160 | /* Return the number of instructions needed to load or store a value |
65239d20 RS |
2161 | of mode MODE at address X. Return 0 if X isn't valid for MODE. |
2162 | Assume that multiword moves may need to be split into word moves | |
2163 | if MIGHT_SPLIT_P, otherwise assume that a single load or store is | |
2164 | enough. | |
ab77a036 | 2165 | |
65239d20 | 2166 | For MIPS16 code, count extended instructions as two instructions. */ |
ab77a036 RS |
2167 | |
2168 | int | |
2169 | mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p) | |
2170 | { | |
2171 | struct mips_address_info addr; | |
2172 | int factor; | |
2173 | ||
2174 | /* BLKmode is used for single unaligned loads and stores and should | |
2175 | not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty | |
2176 | meaningless, so we have to single it out as a special case one way | |
2177 | or the other.) */ | |
5955b0a3 | 2178 | if (mode != BLKmode && might_split_p) |
656f37ee | 2179 | factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
5955b0a3 RS |
2180 | else |
2181 | factor = 1; | |
656f37ee | 2182 | |
108b61d5 RS |
2183 | if (mips_classify_address (&addr, x, mode, false)) |
2184 | switch (addr.type) | |
2185 | { | |
2186 | case ADDRESS_REG: | |
2187 | if (TARGET_MIPS16 | |
65239d20 RS |
2188 | && !mips16_unextended_reference_p (mode, addr.reg, |
2189 | UINTVAL (addr.offset))) | |
108b61d5 RS |
2190 | return factor * 2; |
2191 | return factor; | |
cafe096b | 2192 | |
108b61d5 | 2193 | case ADDRESS_LO_SUM: |
65239d20 | 2194 | return TARGET_MIPS16 ? factor * 2 : factor; |
4fef83a7 | 2195 | |
108b61d5 RS |
2196 | case ADDRESS_CONST_INT: |
2197 | return factor; | |
cafe096b | 2198 | |
108b61d5 | 2199 | case ADDRESS_SYMBOLIC: |
fbb96ac5 | 2200 | return factor * mips_symbol_insns (addr.symbol_type, mode); |
108b61d5 RS |
2201 | } |
2202 | return 0; | |
cafe096b EC |
2203 | } |
2204 | ||
65239d20 RS |
2205 | /* Return the number of instructions needed to load constant X. |
2206 | Return 0 if X isn't a valid constant. */ | |
cafe096b EC |
2207 | |
2208 | int | |
b4966b1b | 2209 | mips_const_insns (rtx x) |
cafe096b | 2210 | { |
b259a9a6 | 2211 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; |
108b61d5 | 2212 | enum mips_symbol_type symbol_type; |
7ffb5e78 | 2213 | rtx offset; |
cafe096b EC |
2214 | |
2215 | switch (GET_CODE (x)) | |
2216 | { | |
cafe096b | 2217 | case HIGH: |
c93c5160 RS |
2218 | if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA, |
2219 | &symbol_type) | |
108b61d5 RS |
2220 | || !mips_split_p[symbol_type]) |
2221 | return 0; | |
2222 | ||
65239d20 RS |
2223 | /* This is simply an LUI for normal mode. It is an extended |
2224 | LI followed by an extended SLL for MIPS16. */ | |
c93c5160 | 2225 | return TARGET_MIPS16 ? 4 : 1; |
cee98a59 MM |
2226 | |
2227 | case CONST_INT: | |
2bcb2ab3 | 2228 | if (TARGET_MIPS16) |
cafe096b EC |
2229 | /* Unsigned 8-bit constants can be loaded using an unextended |
2230 | LI instruction. Unsigned 16-bit constants can be loaded | |
2231 | using an extended LI. Negative constants must be loaded | |
2232 | using LI and then negated. */ | |
65239d20 | 2233 | return (IN_RANGE (INTVAL (x), 0, 255) ? 1 |
cafe096b | 2234 | : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 |
65239d20 | 2235 | : IN_RANGE (-INTVAL (x), 0, 255) ? 2 |
cafe096b EC |
2236 | : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 |
2237 | : 0); | |
2238 | ||
b259a9a6 | 2239 | return mips_build_integer (codes, INTVAL (x)); |
cee98a59 | 2240 | |
cafe096b | 2241 | case CONST_DOUBLE: |
06a4ab70 | 2242 | case CONST_VECTOR: |
65239d20 RS |
2243 | /* Allow zeros for normal mode, where we can use $0. */ |
2244 | return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; | |
cee98a59 | 2245 | |
108b61d5 RS |
2246 | case CONST: |
2247 | if (CONST_GP_P (x)) | |
2248 | return 1; | |
2249 | ||
2250 | /* See if we can refer to X directly. */ | |
280fcbfa | 2251 | if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type)) |
fbb96ac5 | 2252 | return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE); |
108b61d5 RS |
2253 | |
2254 | /* Otherwise try splitting the constant into a base and offset. | |
08d0963a RS |
2255 | If the offset is a 16-bit value, we can load the base address |
2256 | into a register and then use (D)ADDIU to add in the offset. | |
2257 | If the offset is larger, we can load the base and offset | |
2258 | into separate registers and add them together with (D)ADDU. | |
2259 | However, the latter is only possible before reload; during | |
2260 | and after reload, we must have the option of forcing the | |
2261 | constant into the pool instead. */ | |
7ffb5e78 | 2262 | split_const (x, &x, &offset); |
108b61d5 | 2263 | if (offset != 0) |
cafe096b | 2264 | { |
108b61d5 RS |
2265 | int n = mips_const_insns (x); |
2266 | if (n != 0) | |
2267 | { | |
7ffb5e78 | 2268 | if (SMALL_INT (offset)) |
108b61d5 | 2269 | return n + 1; |
fbbf66e7 | 2270 | else if (!targetm.cannot_force_const_mem (GET_MODE (x), x)) |
7ffb5e78 | 2271 | return n + 1 + mips_build_integer (codes, INTVAL (offset)); |
108b61d5 RS |
2272 | } |
2273 | } | |
2274 | return 0; | |
cee98a59 | 2275 | |
108b61d5 RS |
2276 | case SYMBOL_REF: |
2277 | case LABEL_REF: | |
fbb96ac5 RS |
2278 | return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA), |
2279 | MAX_MACHINE_MODE); | |
cee98a59 | 2280 | |
108b61d5 RS |
2281 | default: |
2282 | return 0; | |
cafe096b EC |
2283 | } |
2284 | } | |
cee98a59 | 2285 | |
c5cb5d18 RS |
2286 | /* X is a doubleword constant that can be handled by splitting it into |
2287 | two words and loading each word separately. Return the number of | |
2288 | instructions required to do this. */ | |
2289 | ||
2290 | int | |
2291 | mips_split_const_insns (rtx x) | |
2292 | { | |
2293 | unsigned int low, high; | |
2294 | ||
2295 | low = mips_const_insns (mips_subword (x, false)); | |
2296 | high = mips_const_insns (mips_subword (x, true)); | |
2297 | gcc_assert (low > 0 && high > 0); | |
2298 | return low + high; | |
2299 | } | |
2300 | ||
5955b0a3 RS |
2301 | /* Return the number of instructions needed to implement INSN, |
2302 | given that it loads from or stores to MEM. Count extended | |
65239d20 | 2303 | MIPS16 instructions as two instructions. */ |
f5963e61 | 2304 | |
cafe096b | 2305 | int |
5955b0a3 | 2306 | mips_load_store_insns (rtx mem, rtx insn) |
cafe096b | 2307 | { |
5955b0a3 RS |
2308 | enum machine_mode mode; |
2309 | bool might_split_p; | |
2310 | rtx set; | |
2311 | ||
2312 | gcc_assert (MEM_P (mem)); | |
2313 | mode = GET_MODE (mem); | |
2314 | ||
2315 | /* Try to prove that INSN does not need to be split. */ | |
2316 | might_split_p = true; | |
2317 | if (GET_MODE_BITSIZE (mode) == 64) | |
2318 | { | |
2319 | set = single_set (insn); | |
2320 | if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) | |
2321 | might_split_p = false; | |
2322 | } | |
2323 | ||
2324 | return mips_address_insns (XEXP (mem, 0), mode, might_split_p); | |
cafe096b | 2325 | } |
2bcb2ab3 | 2326 | |
46490403 MR |
2327 | /* Return the number of instructions needed for an integer division. */ |
2328 | ||
2329 | int | |
2330 | mips_idiv_insns (void) | |
2331 | { | |
2332 | int count; | |
2333 | ||
2334 | count = 1; | |
2335 | if (TARGET_CHECK_ZERO_DIV) | |
9f0df97a DD |
2336 | { |
2337 | if (GENERATE_DIVIDE_TRAPS) | |
2338 | count++; | |
2339 | else | |
2340 | count += 2; | |
2341 | } | |
66083422 | 2342 | |
6ba7b547 | 2343 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) |
46490403 MR |
2344 | count++; |
2345 | return count; | |
2346 | } | |
50d32cf6 | 2347 | \f |
51e7252a RS |
2348 | /* Emit a move from SRC to DEST. Assume that the move expanders can |
2349 | handle all moves if !can_create_pseudo_p (). The distinction is | |
2350 | important because, unlike emit_move_insn, the move expanders know | |
2351 | how to force Pmode objects into the constant pool even when the | |
2352 | constant pool address is not itself legitimate. */ | |
2353 | ||
2354 | rtx | |
2355 | mips_emit_move (rtx dest, rtx src) | |
2356 | { | |
2357 | return (can_create_pseudo_p () | |
2358 | ? emit_move_insn (dest, src) | |
2359 | : emit_move_insn_1 (dest, src)); | |
2360 | } | |
108b61d5 | 2361 | |
d48a3196 CF |
2362 | /* Emit an instruction of the form (set TARGET (CODE OP0)). */ |
2363 | ||
2364 | static void | |
2365 | mips_emit_unary (enum rtx_code code, rtx target, rtx op0) | |
2366 | { | |
2367 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2368 | gen_rtx_fmt_e (code, GET_MODE (op0), op0))); | |
2369 | } | |
2370 | ||
2371 | /* Compute (CODE OP0) and store the result in a new register of mode MODE. | |
2372 | Return that new register. */ | |
2373 | ||
2374 | static rtx | |
2375 | mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0) | |
2376 | { | |
2377 | rtx reg; | |
2378 | ||
2379 | reg = gen_reg_rtx (mode); | |
2380 | mips_emit_unary (code, reg, op0); | |
2381 | return reg; | |
2382 | } | |
2383 | ||
ab77a036 RS |
2384 | /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ |
2385 | ||
2386 | static void | |
2387 | mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) | |
2388 | { | |
2389 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2390 | gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); | |
2391 | } | |
2392 | ||
49bce30a RS |
2393 | /* Compute (CODE OP0 OP1) and store the result in a new register |
2394 | of mode MODE. Return that new register. */ | |
2395 | ||
2396 | static rtx | |
2397 | mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1) | |
2398 | { | |
2399 | rtx reg; | |
2400 | ||
2401 | reg = gen_reg_rtx (mode); | |
2402 | mips_emit_binary (code, reg, op0, op1); | |
2403 | return reg; | |
2404 | } | |
2405 | ||
65239d20 | 2406 | /* Copy VALUE to a register and return that register. If new pseudos |
108b61d5 RS |
2407 | are allowed, copy it into a new register, otherwise use DEST. */ |
2408 | ||
2409 | static rtx | |
2410 | mips_force_temporary (rtx dest, rtx value) | |
2411 | { | |
b3a13419 | 2412 | if (can_create_pseudo_p ()) |
108b61d5 RS |
2413 | return force_reg (Pmode, value); |
2414 | else | |
2415 | { | |
65239d20 | 2416 | mips_emit_move (dest, value); |
108b61d5 RS |
2417 | return dest; |
2418 | } | |
cafe096b | 2419 | } |
dbc90b65 RS |
2420 | |
2421 | /* Emit a call sequence with call pattern PATTERN and return the call | |
2422 | instruction itself (which is not necessarily the last instruction | |
08d0963a RS |
2423 | emitted). ORIG_ADDR is the original, unlegitimized address, |
2424 | ADDR is the legitimized form, and LAZY_P is true if the call | |
2425 | address is lazily-bound. */ | |
dbc90b65 RS |
2426 | |
2427 | static rtx | |
08d0963a | 2428 | mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p) |
dbc90b65 | 2429 | { |
08d0963a | 2430 | rtx insn, reg; |
dbc90b65 RS |
2431 | |
2432 | insn = emit_call_insn (pattern); | |
2433 | ||
08d0963a RS |
2434 | if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr)) |
2435 | { | |
2436 | /* MIPS16 JALRs only take MIPS16 registers. If the target | |
2437 | function requires $25 to be valid on entry, we must copy it | |
2438 | there separately. The move instruction can be put in the | |
2439 | call's delay slot. */ | |
2440 | reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
2441 | emit_insn_before (gen_move_insn (reg, addr), insn); | |
2442 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
2443 | } | |
2444 | ||
dbc90b65 | 2445 | if (lazy_p) |
08d0963a | 2446 | /* Lazy-binding stubs require $gp to be valid on entry. */ |
dbc90b65 RS |
2447 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2448 | ||
2449 | if (TARGET_USE_GOT) | |
2450 | { | |
2451 | /* See the comment above load_call<mode> for details. */ | |
2452 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2453 | gen_rtx_REG (Pmode, GOT_VERSION_REGNUM)); | |
2454 | emit_insn (gen_update_got_version ()); | |
2455 | } | |
2456 | return insn; | |
2457 | } | |
65239d20 | 2458 | \f |
7462a715 RS |
2459 | /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, |
2460 | then add CONST_INT OFFSET to the result. */ | |
2461 | ||
2462 | static rtx | |
2463 | mips_unspec_address_offset (rtx base, rtx offset, | |
2464 | enum mips_symbol_type symbol_type) | |
2465 | { | |
2466 | base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), | |
2467 | UNSPEC_ADDRESS_FIRST + symbol_type); | |
2468 | if (offset != const0_rtx) | |
2469 | base = gen_rtx_PLUS (Pmode, base, offset); | |
2470 | return gen_rtx_CONST (Pmode, base); | |
2471 | } | |
2472 | ||
2473 | /* Return an UNSPEC address with underlying address ADDRESS and symbol | |
2474 | type SYMBOL_TYPE. */ | |
2475 | ||
2476 | rtx | |
2477 | mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) | |
2478 | { | |
2479 | rtx base, offset; | |
2480 | ||
2481 | split_const (address, &base, &offset); | |
2482 | return mips_unspec_address_offset (base, offset, symbol_type); | |
2483 | } | |
2484 | ||
b53da244 AN |
2485 | /* If OP is an UNSPEC address, return the address to which it refers, |
2486 | otherwise return OP itself. */ | |
2487 | ||
2488 | static rtx | |
2489 | mips_strip_unspec_address (rtx op) | |
2490 | { | |
2491 | rtx base, offset; | |
2492 | ||
2493 | split_const (op, &base, &offset); | |
2494 | if (UNSPEC_ADDRESS_P (base)) | |
2495 | op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset)); | |
2496 | return op; | |
2497 | } | |
2498 | ||
7462a715 RS |
2499 | /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the |
2500 | high part to BASE and return the result. Just return BASE otherwise. | |
2501 | TEMP is as for mips_force_temporary. | |
2502 | ||
2503 | The returned expression can be used as the first operand to a LO_SUM. */ | |
2504 | ||
2505 | static rtx | |
2506 | mips_unspec_offset_high (rtx temp, rtx base, rtx addr, | |
2507 | enum mips_symbol_type symbol_type) | |
2508 | { | |
2509 | if (mips_split_p[symbol_type]) | |
2510 | { | |
2511 | addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); | |
2512 | addr = mips_force_temporary (temp, addr); | |
2513 | base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base)); | |
2514 | } | |
2515 | return base; | |
2516 | } | |
2517 | \f | |
5ca3d30c RS |
2518 | /* Return an instruction that copies $gp into register REG. We want |
2519 | GCC to treat the register's value as constant, so that its value | |
2520 | can be rematerialized on demand. */ | |
2521 | ||
2522 | static rtx | |
2523 | gen_load_const_gp (rtx reg) | |
2524 | { | |
2525 | return (Pmode == SImode | |
2526 | ? gen_load_const_gp_si (reg) | |
2527 | : gen_load_const_gp_di (reg)); | |
2528 | } | |
2529 | ||
65239d20 RS |
2530 | /* Return a pseudo register that contains the value of $gp throughout |
2531 | the current function. Such registers are needed by MIPS16 functions, | |
2532 | for which $gp itself is not a valid base register or addition operand. */ | |
ab77a036 RS |
2533 | |
2534 | static rtx | |
2535 | mips16_gp_pseudo_reg (void) | |
2536 | { | |
2537 | if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) | |
ab77a036 | 2538 | { |
08d0963a RS |
2539 | rtx insn, scan; |
2540 | ||
8a7a250d RS |
2541 | cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); |
2542 | ||
08d0963a RS |
2543 | push_topmost_sequence (); |
2544 | ||
2545 | scan = get_insns (); | |
2546 | while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan))) | |
2547 | scan = NEXT_INSN (scan); | |
ab77a036 | 2548 | |
ab77a036 | 2549 | insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); |
08d0963a | 2550 | emit_insn_after (insn, scan); |
ab77a036 | 2551 | |
ab77a036 | 2552 | pop_topmost_sequence (); |
ab77a036 RS |
2553 | } |
2554 | ||
2555 | return cfun->machine->mips16_gp_pseudo_rtx; | |
2556 | } | |
cafe096b | 2557 | |
08d0963a RS |
2558 | /* Return a base register that holds pic_offset_table_rtx. |
2559 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2560 | ||
2561 | rtx | |
2562 | mips_pic_base_register (rtx temp) | |
2563 | { | |
2564 | if (!TARGET_MIPS16) | |
2565 | return pic_offset_table_rtx; | |
2566 | ||
8a7a250d | 2567 | if (currently_expanding_to_rtl) |
08d0963a RS |
2568 | return mips16_gp_pseudo_reg (); |
2569 | ||
8a7a250d RS |
2570 | if (can_create_pseudo_p ()) |
2571 | temp = gen_reg_rtx (Pmode); | |
2572 | ||
08d0963a RS |
2573 | if (TARGET_USE_GOT) |
2574 | /* The first post-reload split exposes all references to $gp | |
2575 | (both uses and definitions). All references must remain | |
2576 | explicit after that point. | |
2577 | ||
2578 | It is safe to introduce uses of $gp at any time, so for | |
2579 | simplicity, we do that before the split too. */ | |
2580 | mips_emit_move (temp, pic_offset_table_rtx); | |
2581 | else | |
2582 | emit_insn (gen_load_const_gp (temp)); | |
2583 | return temp; | |
2584 | } | |
2585 | ||
b53da244 AN |
2586 | /* Return the RHS of a load_call<mode> insn. */ |
2587 | ||
2588 | static rtx | |
2589 | mips_unspec_call (rtx reg, rtx symbol) | |
2590 | { | |
2591 | rtvec vec; | |
2592 | ||
2593 | vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM)); | |
2594 | return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL); | |
2595 | } | |
2596 | ||
2597 | /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol | |
2598 | reference. Return NULL_RTX otherwise. */ | |
2599 | ||
2600 | static rtx | |
2601 | mips_strip_unspec_call (rtx src) | |
2602 | { | |
2603 | if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL) | |
2604 | return mips_strip_unspec_address (XVECEXP (src, 0, 1)); | |
2605 | return NULL_RTX; | |
2606 | } | |
2607 | ||
08d0963a RS |
2608 | /* Create and return a GOT reference of type TYPE for address ADDR. |
2609 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2610 | ||
2611 | rtx | |
2612 | mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type) | |
2613 | { | |
2614 | rtx base, high, lo_sum_symbol; | |
2615 | ||
2616 | base = mips_pic_base_register (temp); | |
2617 | ||
2618 | /* If we used the temporary register to load $gp, we can't use | |
2619 | it for the high part as well. */ | |
2620 | if (temp != NULL && reg_overlap_mentioned_p (base, temp)) | |
2621 | temp = NULL; | |
2622 | ||
2623 | high = mips_unspec_offset_high (temp, base, addr, type); | |
2624 | lo_sum_symbol = mips_unspec_address (addr, type); | |
2625 | ||
2626 | if (type == SYMBOL_GOTOFF_CALL) | |
b53da244 | 2627 | return mips_unspec_call (high, lo_sum_symbol); |
08d0963a RS |
2628 | else |
2629 | return (Pmode == SImode | |
2630 | ? gen_unspec_gotsi (high, lo_sum_symbol) | |
2631 | : gen_unspec_gotdi (high, lo_sum_symbol)); | |
2632 | } | |
2633 | ||
390ea488 RS |
2634 | /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise |
2635 | it appears in a MEM of that mode. Return true if ADDR is a legitimate | |
08d0963a RS |
2636 | constant in that context and can be split into high and low parts. |
2637 | If so, and if LOW_OUT is nonnull, emit the high part and store the | |
2638 | low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. | |
cafe096b | 2639 | |
390ea488 | 2640 | TEMP is as for mips_force_temporary and is used to load the high |
08d0963a RS |
2641 | part into a register. |
2642 | ||
2643 | When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be | |
2644 | a legitimize SET_SRC for an .md pattern, otherwise the low part | |
2645 | is guaranteed to be a legitimate address for mode MODE. */ | |
390ea488 RS |
2646 | |
2647 | bool | |
08d0963a | 2648 | mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out) |
cafe096b | 2649 | { |
390ea488 RS |
2650 | enum mips_symbol_context context; |
2651 | enum mips_symbol_type symbol_type; | |
108b61d5 | 2652 | rtx high; |
cafe096b | 2653 | |
390ea488 RS |
2654 | context = (mode == MAX_MACHINE_MODE |
2655 | ? SYMBOL_CONTEXT_LEA | |
2656 | : SYMBOL_CONTEXT_MEM); | |
08d0963a | 2657 | if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA) |
1732457d | 2658 | { |
08d0963a RS |
2659 | addr = XEXP (addr, 0); |
2660 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
2661 | && mips_symbol_insns (symbol_type, mode) > 0 | |
2662 | && mips_split_hi_p[symbol_type]) | |
390ea488 | 2663 | { |
08d0963a RS |
2664 | if (low_out) |
2665 | switch (symbol_type) | |
2666 | { | |
2667 | case SYMBOL_GOT_PAGE_OFST: | |
2668 | /* The high part of a page/ofst pair is loaded from the GOT. */ | |
2669 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE); | |
2670 | break; | |
2671 | ||
2672 | default: | |
2673 | gcc_unreachable (); | |
2674 | } | |
2675 | return true; | |
390ea488 | 2676 | } |
08d0963a RS |
2677 | } |
2678 | else | |
2679 | { | |
2680 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
2681 | && mips_symbol_insns (symbol_type, mode) > 0 | |
2682 | && mips_split_p[symbol_type]) | |
390ea488 | 2683 | { |
08d0963a RS |
2684 | if (low_out) |
2685 | switch (symbol_type) | |
2686 | { | |
2687 | case SYMBOL_GOT_DISP: | |
2688 | /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */ | |
2689 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP); | |
2690 | break; | |
2691 | ||
2692 | case SYMBOL_GP_RELATIVE: | |
2693 | high = mips_pic_base_register (temp); | |
2694 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
2695 | break; | |
2696 | ||
2697 | default: | |
2698 | high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); | |
2699 | high = mips_force_temporary (temp, high); | |
2700 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
2701 | break; | |
2702 | } | |
2703 | return true; | |
390ea488 | 2704 | } |
1732457d | 2705 | } |
08d0963a | 2706 | return false; |
cafe096b EC |
2707 | } |
2708 | ||
b73ce23b RS |
2709 | /* Return a legitimate address for REG + OFFSET. TEMP is as for |
2710 | mips_force_temporary; it is only needed when OFFSET is not a | |
2711 | SMALL_OPERAND. */ | |
cafe096b | 2712 | |
108b61d5 | 2713 | static rtx |
b73ce23b | 2714 | mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) |
cafe096b | 2715 | { |
108b61d5 | 2716 | if (!SMALL_OPERAND (offset)) |
b73ce23b RS |
2717 | { |
2718 | rtx high; | |
65239d20 | 2719 | |
b73ce23b RS |
2720 | if (TARGET_MIPS16) |
2721 | { | |
2722 | /* Load the full offset into a register so that we can use | |
2723 | an unextended instruction for the address itself. */ | |
2724 | high = GEN_INT (offset); | |
2725 | offset = 0; | |
2726 | } | |
2727 | else | |
2728 | { | |
6d8f135b JW |
2729 | /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. |
2730 | The addition inside the macro CONST_HIGH_PART may cause an | |
2731 | overflow, so we need to force a sign-extension check. */ | |
2732 | high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); | |
b73ce23b RS |
2733 | offset = CONST_LOW_PART (offset); |
2734 | } | |
2735 | high = mips_force_temporary (temp, high); | |
2736 | reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); | |
2737 | } | |
2738 | return plus_constant (reg, offset); | |
cafe096b | 2739 | } |
65239d20 RS |
2740 | \f |
2741 | /* The __tls_get_attr symbol. */ | |
69229b81 DJ |
2742 | static GTY(()) rtx mips_tls_symbol; |
2743 | ||
65239d20 RS |
2744 | /* Return an instruction sequence that calls __tls_get_addr. SYM is |
2745 | the TLS symbol we are referencing and TYPE is the symbol type to use | |
2746 | (either global dynamic or local dynamic). V0 is an RTX for the | |
2747 | return value location. */ | |
2748 | ||
69229b81 DJ |
2749 | static rtx |
2750 | mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0) | |
2751 | { | |
dbc90b65 | 2752 | rtx insn, loc, a0; |
69229b81 DJ |
2753 | |
2754 | a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); | |
2755 | ||
2756 | if (!mips_tls_symbol) | |
2757 | mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2758 | ||
2759 | loc = mips_unspec_address (sym, type); | |
2760 | ||
2761 | start_sequence (); | |
2762 | ||
2763 | emit_insn (gen_rtx_SET (Pmode, a0, | |
2764 | gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); | |
08d0963a RS |
2765 | insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol, |
2766 | const0_rtx, NULL_RTX, false); | |
becfd6e5 | 2767 | RTL_CONST_CALL_P (insn) = 1; |
69229b81 DJ |
2768 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); |
2769 | insn = get_insns (); | |
2770 | ||
2771 | end_sequence (); | |
2772 | ||
2773 | return insn; | |
2774 | } | |
2775 | ||
256f27f1 RS |
2776 | /* Return a pseudo register that contains the current thread pointer. */ |
2777 | ||
2778 | static rtx | |
2779 | mips_get_tp (void) | |
2780 | { | |
2781 | rtx tp; | |
2782 | ||
2783 | tp = gen_reg_rtx (Pmode); | |
2784 | if (Pmode == DImode) | |
2785 | emit_insn (gen_tls_get_tp_di (tp)); | |
2786 | else | |
2787 | emit_insn (gen_tls_get_tp_si (tp)); | |
2788 | return tp; | |
2789 | } | |
2790 | ||
65239d20 RS |
2791 | /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return |
2792 | its address. The return value will be both a valid address and a valid | |
2793 | SET_SRC (either a REG or a LO_SUM). */ | |
69229b81 DJ |
2794 | |
2795 | static rtx | |
2796 | mips_legitimize_tls_address (rtx loc) | |
2797 | { | |
256f27f1 | 2798 | rtx dest, insn, v0, tp, tmp1, tmp2, eqv; |
69229b81 DJ |
2799 | enum tls_model model; |
2800 | ||
edede024 SL |
2801 | if (TARGET_MIPS16) |
2802 | { | |
2803 | sorry ("MIPS16 TLS"); | |
2804 | return gen_reg_rtx (Pmode); | |
2805 | } | |
2806 | ||
69229b81 | 2807 | model = SYMBOL_REF_TLS_MODEL (loc); |
4afa41f1 RS |
2808 | /* Only TARGET_ABICALLS code can have more than one module; other |
2809 | code must be be static and should not use a GOT. All TLS models | |
2810 | reduce to local exec in this situation. */ | |
2811 | if (!TARGET_ABICALLS) | |
2812 | model = TLS_MODEL_LOCAL_EXEC; | |
69229b81 DJ |
2813 | |
2814 | switch (model) | |
2815 | { | |
2816 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
65239d20 | 2817 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
2818 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0); |
2819 | dest = gen_reg_rtx (Pmode); | |
2820 | emit_libcall_block (insn, dest, v0, loc); | |
2821 | break; | |
2822 | ||
2823 | case TLS_MODEL_LOCAL_DYNAMIC: | |
65239d20 | 2824 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
2825 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0); |
2826 | tmp1 = gen_reg_rtx (Pmode); | |
2827 | ||
2828 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2829 | share the LDM result with other LD model accesses. */ | |
2830 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2831 | UNSPEC_TLS_LDM); | |
2832 | emit_libcall_block (insn, tmp1, v0, eqv); | |
2833 | ||
2834 | tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL); | |
2835 | dest = gen_rtx_LO_SUM (Pmode, tmp2, | |
2836 | mips_unspec_address (loc, SYMBOL_DTPREL)); | |
2837 | break; | |
2838 | ||
2839 | case TLS_MODEL_INITIAL_EXEC: | |
256f27f1 | 2840 | tp = mips_get_tp (); |
69229b81 DJ |
2841 | tmp1 = gen_reg_rtx (Pmode); |
2842 | tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); | |
2843 | if (Pmode == DImode) | |
256f27f1 | 2844 | emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 2845 | else |
256f27f1 | 2846 | emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 2847 | dest = gen_reg_rtx (Pmode); |
256f27f1 | 2848 | emit_insn (gen_add3_insn (dest, tmp1, tp)); |
69229b81 DJ |
2849 | break; |
2850 | ||
2851 | case TLS_MODEL_LOCAL_EXEC: | |
256f27f1 RS |
2852 | tp = mips_get_tp (); |
2853 | tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL); | |
69229b81 DJ |
2854 | dest = gen_rtx_LO_SUM (Pmode, tmp1, |
2855 | mips_unspec_address (loc, SYMBOL_TPREL)); | |
2856 | break; | |
2857 | ||
2858 | default: | |
107a4b41 | 2859 | gcc_unreachable (); |
69229b81 | 2860 | } |
69229b81 DJ |
2861 | return dest; |
2862 | } | |
65239d20 | 2863 | \f |
fa21a761 RS |
2864 | /* If X is not a valid address for mode MODE, force it into a register. */ |
2865 | ||
2866 | static rtx | |
2867 | mips_force_address (rtx x, enum machine_mode mode) | |
2868 | { | |
2869 | if (!mips_legitimate_address_p (mode, x, false)) | |
2870 | x = force_reg (Pmode, x); | |
2871 | return x; | |
2872 | } | |
2873 | ||
506d7b68 | 2874 | /* This function is used to implement LEGITIMIZE_ADDRESS. If X can |
cafe096b | 2875 | be legitimized in a way that the generic machinery might not expect, |
506d7b68 | 2876 | return a new address, otherwise return NULL. MODE is the mode of |
cafe096b | 2877 | the memory being accessed. */ |
910628b8 | 2878 | |
506d7b68 PB |
2879 | static rtx |
2880 | mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
2881 | enum machine_mode mode) | |
7dac2f89 | 2882 | { |
fa21a761 | 2883 | rtx base, addr; |
65239d20 RS |
2884 | HOST_WIDE_INT offset; |
2885 | ||
506d7b68 PB |
2886 | if (mips_tls_symbol_p (x)) |
2887 | return mips_legitimize_tls_address (x); | |
69229b81 | 2888 | |
108b61d5 | 2889 | /* See if the address can split into a high part and a LO_SUM. */ |
506d7b68 PB |
2890 | if (mips_split_symbol (NULL, x, mode, &addr)) |
2891 | return mips_force_address (addr, mode); | |
910628b8 | 2892 | |
65239d20 | 2893 | /* Handle BASE + OFFSET using mips_add_offset. */ |
506d7b68 | 2894 | mips_split_plus (x, &base, &offset); |
65239d20 | 2895 | if (offset != 0) |
cafe096b | 2896 | { |
65239d20 RS |
2897 | if (!mips_valid_base_register_p (base, mode, false)) |
2898 | base = copy_to_mode_reg (Pmode, base); | |
fa21a761 | 2899 | addr = mips_add_offset (NULL, base, offset); |
506d7b68 | 2900 | return mips_force_address (addr, mode); |
cafe096b | 2901 | } |
506d7b68 PB |
2902 | |
2903 | return x; | |
50c0000c | 2904 | } |
c94c9817 | 2905 | |
65239d20 | 2906 | /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */ |
b259a9a6 | 2907 | |
ea462dd0 | 2908 | void |
65239d20 | 2909 | mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) |
b259a9a6 RS |
2910 | { |
2911 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; | |
2912 | enum machine_mode mode; | |
65239d20 | 2913 | unsigned int i, num_ops; |
b259a9a6 RS |
2914 | rtx x; |
2915 | ||
2916 | mode = GET_MODE (dest); | |
65239d20 | 2917 | num_ops = mips_build_integer (codes, value); |
b259a9a6 RS |
2918 | |
2919 | /* Apply each binary operation to X. Invariant: X is a legitimate | |
2920 | source operand for a SET pattern. */ | |
2921 | x = GEN_INT (codes[0].value); | |
65239d20 | 2922 | for (i = 1; i < num_ops; i++) |
b259a9a6 | 2923 | { |
b3a13419 | 2924 | if (!can_create_pseudo_p ()) |
ea462dd0 RS |
2925 | { |
2926 | emit_insn (gen_rtx_SET (VOIDmode, temp, x)); | |
2927 | x = temp; | |
2928 | } | |
b259a9a6 RS |
2929 | else |
2930 | x = force_reg (mode, x); | |
2931 | x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); | |
2932 | } | |
2933 | ||
2934 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
2935 | } | |
2936 | ||
cafe096b EC |
2937 | /* Subroutine of mips_legitimize_move. Move constant SRC into register |
2938 | DEST given that SRC satisfies immediate_operand but doesn't satisfy | |
2939 | move_operand. */ | |
2940 | ||
2941 | static void | |
b4966b1b | 2942 | mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src) |
c94c9817 | 2943 | { |
7ffb5e78 | 2944 | rtx base, offset; |
cafe096b | 2945 | |
ea462dd0 RS |
2946 | /* Split moves of big integers into smaller pieces. */ |
2947 | if (splittable_const_int_operand (src, mode)) | |
b259a9a6 | 2948 | { |
ea462dd0 | 2949 | mips_move_integer (dest, dest, INTVAL (src)); |
b259a9a6 RS |
2950 | return; |
2951 | } | |
2952 | ||
ea462dd0 | 2953 | /* Split moves of symbolic constants into high/low pairs. */ |
390ea488 | 2954 | if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) |
69229b81 | 2955 | { |
390ea488 | 2956 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); |
69229b81 DJ |
2957 | return; |
2958 | } | |
2959 | ||
65239d20 RS |
2960 | /* Generate the appropriate access sequences for TLS symbols. */ |
2961 | if (mips_tls_symbol_p (src)) | |
cafe096b | 2962 | { |
51e7252a | 2963 | mips_emit_move (dest, mips_legitimize_tls_address (src)); |
cafe096b EC |
2964 | return; |
2965 | } | |
2966 | ||
edede024 SL |
2967 | /* If we have (const (plus symbol offset)), and that expression cannot |
2968 | be forced into memory, load the symbol first and add in the offset. | |
2969 | In non-MIPS16 mode, prefer to do this even if the constant _can_ be | |
2970 | forced into memory, as it usually produces better code. */ | |
7ffb5e78 | 2971 | split_const (src, &base, &offset); |
edede024 | 2972 | if (offset != const0_rtx |
fbbf66e7 | 2973 | && (targetm.cannot_force_const_mem (mode, src) |
edede024 | 2974 | || (!TARGET_MIPS16 && can_create_pseudo_p ()))) |
cafe096b | 2975 | { |
108b61d5 | 2976 | base = mips_force_temporary (dest, base); |
65239d20 | 2977 | mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset))); |
cafe096b EC |
2978 | return; |
2979 | } | |
2980 | ||
2981 | src = force_const_mem (mode, src); | |
2982 | ||
2983 | /* When using explicit relocs, constant pool references are sometimes | |
108b61d5 | 2984 | not legitimate addresses. */ |
390ea488 | 2985 | mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); |
51e7252a | 2986 | mips_emit_move (dest, src); |
c94c9817 MM |
2987 | } |
2988 | ||
65239d20 | 2989 | /* If (set DEST SRC) is not a valid move instruction, emit an equivalent |
cafe096b EC |
2990 | sequence that is valid. */ |
2991 | ||
2992 | bool | |
b4966b1b | 2993 | mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src) |
c94c9817 | 2994 | { |
cafe096b | 2995 | if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) |
7dac2f89 | 2996 | { |
51e7252a | 2997 | mips_emit_move (dest, force_reg (mode, src)); |
cafe096b | 2998 | return true; |
7dac2f89 EC |
2999 | } |
3000 | ||
fc31c7ca | 3001 | /* We need to deal with constants that would be legitimate |
65239d20 | 3002 | immediate_operands but aren't legitimate move_operands. */ |
fc31c7ca | 3003 | if (CONSTANT_P (src) && !move_operand (src, mode)) |
cafe096b EC |
3004 | { |
3005 | mips_legitimize_const_move (mode, dest, src); | |
3006 | set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); | |
3007 | return true; | |
3008 | } | |
3009 | return false; | |
3010 | } | |
cee98a59 | 3011 | \f |
65239d20 RS |
3012 | /* Return true if value X in context CONTEXT is a small-data address |
3013 | that can be rewritten as a LO_SUM. */ | |
ab77a036 RS |
3014 | |
3015 | static bool | |
3016 | mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context) | |
3017 | { | |
3018 | enum mips_symbol_type symbol_type; | |
3019 | ||
08d0963a RS |
3020 | return (mips_lo_relocs[SYMBOL_GP_RELATIVE] |
3021 | && !mips_split_p[SYMBOL_GP_RELATIVE] | |
ab77a036 RS |
3022 | && mips_symbolic_constant_p (x, context, &symbol_type) |
3023 | && symbol_type == SYMBOL_GP_RELATIVE); | |
3024 | } | |
3025 | ||
ab77a036 RS |
3026 | /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the |
3027 | containing MEM, or null if none. */ | |
3028 | ||
3029 | static int | |
3030 | mips_small_data_pattern_1 (rtx *loc, void *data) | |
3031 | { | |
3032 | enum mips_symbol_context context; | |
3033 | ||
3034 | if (GET_CODE (*loc) == LO_SUM) | |
3035 | return -1; | |
3036 | ||
3037 | if (MEM_P (*loc)) | |
3038 | { | |
3039 | if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc)) | |
3040 | return 1; | |
3041 | return -1; | |
3042 | } | |
3043 | ||
3044 | context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA; | |
3045 | return mips_rewrite_small_data_p (*loc, context); | |
3046 | } | |
3047 | ||
3048 | /* Return true if OP refers to small data symbols directly, not through | |
3049 | a LO_SUM. */ | |
3050 | ||
3051 | bool | |
3052 | mips_small_data_pattern_p (rtx op) | |
3053 | { | |
65239d20 | 3054 | return for_each_rtx (&op, mips_small_data_pattern_1, NULL); |
ab77a036 | 3055 | } |
65239d20 | 3056 | |
ab77a036 RS |
3057 | /* A for_each_rtx callback, used by mips_rewrite_small_data. |
3058 | DATA is the containing MEM, or null if none. */ | |
3059 | ||
3060 | static int | |
3061 | mips_rewrite_small_data_1 (rtx *loc, void *data) | |
3062 | { | |
3063 | enum mips_symbol_context context; | |
3064 | ||
3065 | if (MEM_P (*loc)) | |
3066 | { | |
3067 | for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc); | |
3068 | return -1; | |
3069 | } | |
3070 | ||
3071 | context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA; | |
3072 | if (mips_rewrite_small_data_p (*loc, context)) | |
3073 | *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc); | |
3074 | ||
3075 | if (GET_CODE (*loc) == LO_SUM) | |
3076 | return -1; | |
3077 | ||
3078 | return 0; | |
3079 | } | |
3080 | ||
65239d20 RS |
3081 | /* Rewrite instruction pattern PATTERN so that it refers to small data |
3082 | using explicit relocations. */ | |
ab77a036 RS |
3083 | |
3084 | rtx | |
65239d20 | 3085 | mips_rewrite_small_data (rtx pattern) |
ab77a036 | 3086 | { |
65239d20 RS |
3087 | pattern = copy_insn (pattern); |
3088 | for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL); | |
3089 | return pattern; | |
ab77a036 RS |
3090 | } |
3091 | \f | |
65239d20 RS |
3092 | /* We need a lot of little routines to check the range of MIPS16 immediate |
3093 | operands. */ | |
2bcb2ab3 GK |
3094 | |
3095 | static int | |
b4966b1b | 3096 | m16_check_op (rtx op, int low, int high, int mask) |
2bcb2ab3 | 3097 | { |
47ac44d6 | 3098 | return (CONST_INT_P (op) |
65239d20 | 3099 | && IN_RANGE (INTVAL (op), low, high) |
2bcb2ab3 GK |
3100 | && (INTVAL (op) & mask) == 0); |
3101 | } | |
3102 | ||
3103 | int | |
b4966b1b | 3104 | m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3105 | { |
3106 | return m16_check_op (op, 0x1, 0x8, 0); | |
3107 | } | |
3108 | ||
3109 | int | |
b4966b1b | 3110 | m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3111 | { |
65239d20 | 3112 | return m16_check_op (op, -0x8, 0x7, 0); |
2bcb2ab3 GK |
3113 | } |
3114 | ||
3115 | int | |
b4966b1b | 3116 | m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3117 | { |
65239d20 | 3118 | return m16_check_op (op, -0x7, 0x8, 0); |
2bcb2ab3 GK |
3119 | } |
3120 | ||
3121 | int | |
b4966b1b | 3122 | m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3123 | { |
65239d20 | 3124 | return m16_check_op (op, -0x10, 0xf, 0); |
2bcb2ab3 GK |
3125 | } |
3126 | ||
3127 | int | |
b4966b1b | 3128 | m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3129 | { |
65239d20 | 3130 | return m16_check_op (op, -0xf, 0x10, 0); |
2bcb2ab3 GK |
3131 | } |
3132 | ||
3133 | int | |
b4966b1b | 3134 | m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3135 | { |
65239d20 | 3136 | return m16_check_op (op, -0x10 << 2, 0xf << 2, 3); |
2bcb2ab3 GK |
3137 | } |
3138 | ||
3139 | int | |
b4966b1b | 3140 | m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3141 | { |
65239d20 | 3142 | return m16_check_op (op, -0xf << 2, 0x10 << 2, 3); |
2bcb2ab3 GK |
3143 | } |
3144 | ||
3145 | int | |
b4966b1b | 3146 | m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3147 | { |
65239d20 | 3148 | return m16_check_op (op, -0x80, 0x7f, 0); |
2bcb2ab3 GK |
3149 | } |
3150 | ||
3151 | int | |
b4966b1b | 3152 | m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3153 | { |
65239d20 | 3154 | return m16_check_op (op, -0x7f, 0x80, 0); |
2bcb2ab3 GK |
3155 | } |
3156 | ||
3157 | int | |
b4966b1b | 3158 | m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3159 | { |
3160 | return m16_check_op (op, 0x0, 0xff, 0); | |
3161 | } | |
3162 | ||
3163 | int | |
b4966b1b | 3164 | m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3165 | { |
65239d20 | 3166 | return m16_check_op (op, -0xff, 0x0, 0); |
2bcb2ab3 GK |
3167 | } |
3168 | ||
3169 | int | |
b4966b1b | 3170 | m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3171 | { |
65239d20 | 3172 | return m16_check_op (op, -0x1, 0xfe, 0); |
2bcb2ab3 GK |
3173 | } |
3174 | ||
3175 | int | |
b4966b1b | 3176 | m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3177 | { |
3178 | return m16_check_op (op, 0x0, 0xff << 2, 3); | |
3179 | } | |
3180 | ||
3181 | int | |
b4966b1b | 3182 | m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3183 | { |
65239d20 | 3184 | return m16_check_op (op, -0xff << 2, 0x0, 3); |
2bcb2ab3 GK |
3185 | } |
3186 | ||
3187 | int | |
b4966b1b | 3188 | m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3189 | { |
65239d20 | 3190 | return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7); |
2bcb2ab3 GK |
3191 | } |
3192 | ||
3193 | int | |
b4966b1b | 3194 | m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3195 | { |
65239d20 | 3196 | return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7); |
2bcb2ab3 | 3197 | } |
cee98a59 | 3198 | \f |
8144a1a8 RS |
3199 | /* The cost of loading values from the constant pool. It should be |
3200 | larger than the cost of any constant we want to synthesize inline. */ | |
8144a1a8 RS |
3201 | #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8) |
3202 | ||
3203 | /* Return the cost of X when used as an operand to the MIPS16 instruction | |
3204 | that implements CODE. Return -1 if there is no such instruction, or if | |
3205 | X is not a valid immediate operand for it. */ | |
3206 | ||
3207 | static int | |
3208 | mips16_constant_cost (int code, HOST_WIDE_INT x) | |
3209 | { | |
3210 | switch (code) | |
3211 | { | |
3212 | case ASHIFT: | |
3213 | case ASHIFTRT: | |
3214 | case LSHIFTRT: | |
3215 | /* Shifts by between 1 and 8 bits (inclusive) are unextended, | |
3216 | other shifts are extended. The shift patterns truncate the shift | |
3217 | count to the right size, so there are no out-of-range values. */ | |
3218 | if (IN_RANGE (x, 1, 8)) | |
3219 | return 0; | |
3220 | return COSTS_N_INSNS (1); | |
3221 | ||
3222 | case PLUS: | |
3223 | if (IN_RANGE (x, -128, 127)) | |
3224 | return 0; | |
3225 | if (SMALL_OPERAND (x)) | |
3226 | return COSTS_N_INSNS (1); | |
3227 | return -1; | |
3228 | ||
3229 | case LEU: | |
3230 | /* Like LE, but reject the always-true case. */ | |
3231 | if (x == -1) | |
3232 | return -1; | |
3233 | case LE: | |
3234 | /* We add 1 to the immediate and use SLT. */ | |
3235 | x += 1; | |
3236 | case XOR: | |
3237 | /* We can use CMPI for an xor with an unsigned 16-bit X. */ | |
3238 | case LT: | |
3239 | case LTU: | |
3240 | if (IN_RANGE (x, 0, 255)) | |
3241 | return 0; | |
3242 | if (SMALL_OPERAND_UNSIGNED (x)) | |
3243 | return COSTS_N_INSNS (1); | |
3244 | return -1; | |
3245 | ||
3246 | case EQ: | |
3247 | case NE: | |
3248 | /* Equality comparisons with 0 are cheap. */ | |
3249 | if (x == 0) | |
3250 | return 0; | |
3251 | return -1; | |
3252 | ||
3253 | default: | |
3254 | return -1; | |
3255 | } | |
3256 | } | |
3257 | ||
3258 | /* Return true if there is a non-MIPS16 instruction that implements CODE | |
3259 | and if that instruction accepts X as an immediate operand. */ | |
3260 | ||
3261 | static int | |
3262 | mips_immediate_operand_p (int code, HOST_WIDE_INT x) | |
3263 | { | |
3264 | switch (code) | |
3265 | { | |
3266 | case ASHIFT: | |
3267 | case ASHIFTRT: | |
3268 | case LSHIFTRT: | |
3269 | /* All shift counts are truncated to a valid constant. */ | |
3270 | return true; | |
3271 | ||
3272 | case ROTATE: | |
3273 | case ROTATERT: | |
3274 | /* Likewise rotates, if the target supports rotates at all. */ | |
3275 | return ISA_HAS_ROR; | |
3276 | ||
3277 | case AND: | |
3278 | case IOR: | |
3279 | case XOR: | |
3280 | /* These instructions take 16-bit unsigned immediates. */ | |
3281 | return SMALL_OPERAND_UNSIGNED (x); | |
3282 | ||
3283 | case PLUS: | |
3284 | case LT: | |
3285 | case LTU: | |
3286 | /* These instructions take 16-bit signed immediates. */ | |
3287 | return SMALL_OPERAND (x); | |
3288 | ||
3289 | case EQ: | |
3290 | case NE: | |
3291 | case GT: | |
3292 | case GTU: | |
3293 | /* The "immediate" forms of these instructions are really | |
3294 | implemented as comparisons with register 0. */ | |
3295 | return x == 0; | |
3296 | ||
3297 | case GE: | |
3298 | case GEU: | |
3299 | /* Likewise, meaning that the only valid immediate operand is 1. */ | |
3300 | return x == 1; | |
3301 | ||
3302 | case LE: | |
3303 | /* We add 1 to the immediate and use SLT. */ | |
3304 | return SMALL_OPERAND (x + 1); | |
3305 | ||
3306 | case LEU: | |
3307 | /* Likewise SLTU, but reject the always-true case. */ | |
3308 | return SMALL_OPERAND (x + 1) && x + 1 != 0; | |
3309 | ||
3310 | case SIGN_EXTRACT: | |
3311 | case ZERO_EXTRACT: | |
3312 | /* The bit position and size are immediate operands. */ | |
3313 | return ISA_HAS_EXT_INS; | |
3314 | ||
3315 | default: | |
3316 | /* By default assume that $0 can be used for 0. */ | |
3317 | return x == 0; | |
3318 | } | |
3319 | } | |
3320 | ||
3321 | /* Return the cost of binary operation X, given that the instruction | |
3322 | sequence for a word-sized or smaller operation has cost SINGLE_COST | |
53d66977 AN |
3323 | and that the sequence of a double-word operation has cost DOUBLE_COST. |
3324 | If SPEED is true, optimize for speed otherwise optimize for size. */ | |
8144a1a8 RS |
3325 | |
3326 | static int | |
53d66977 | 3327 | mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) |
8144a1a8 RS |
3328 | { |
3329 | int cost; | |
3330 | ||
3331 | if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) | |
3332 | cost = double_cost; | |
3333 | else | |
3334 | cost = single_cost; | |
3335 | return (cost | |
5e8f01f4 | 3336 | + set_src_cost (XEXP (x, 0), speed) |
68f932c4 | 3337 | + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed)); |
8144a1a8 RS |
3338 | } |
3339 | ||
3340 | /* Return the cost of floating-point multiplications of mode MODE. */ | |
3341 | ||
3342 | static int | |
3343 | mips_fp_mult_cost (enum machine_mode mode) | |
3344 | { | |
3345 | return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; | |
3346 | } | |
3347 | ||
3348 | /* Return the cost of floating-point divisions of mode MODE. */ | |
3349 | ||
3350 | static int | |
3351 | mips_fp_div_cost (enum machine_mode mode) | |
3352 | { | |
3353 | return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; | |
3354 | } | |
3355 | ||
3356 | /* Return the cost of sign-extending OP to mode MODE, not including the | |
3357 | cost of OP itself. */ | |
3358 | ||
3359 | static int | |
3360 | mips_sign_extend_cost (enum machine_mode mode, rtx op) | |
3361 | { | |
3362 | if (MEM_P (op)) | |
3363 | /* Extended loads are as cheap as unextended ones. */ | |
3364 | return 0; | |
3365 | ||
3366 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3367 | /* A sign extension from SImode to DImode in 64-bit mode is free. */ | |
3368 | return 0; | |
3369 | ||
3370 | if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E) | |
3371 | /* We can use SEB or SEH. */ | |
3372 | return COSTS_N_INSNS (1); | |
3373 | ||
3374 | /* We need to use a shift left and a shift right. */ | |
3375 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3376 | } | |
3377 | ||
3378 | /* Return the cost of zero-extending OP to mode MODE, not including the | |
3379 | cost of OP itself. */ | |
3380 | ||
3381 | static int | |
3382 | mips_zero_extend_cost (enum machine_mode mode, rtx op) | |
3383 | { | |
3384 | if (MEM_P (op)) | |
3385 | /* Extended loads are as cheap as unextended ones. */ | |
3386 | return 0; | |
3387 | ||
3388 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3389 | /* We need a shift left by 32 bits and a shift right by 32 bits. */ | |
3390 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3391 | ||
3392 | if (GENERATE_MIPS16E) | |
3393 | /* We can use ZEB or ZEH. */ | |
3394 | return COSTS_N_INSNS (1); | |
3395 | ||
3396 | if (TARGET_MIPS16) | |
3397 | /* We need to load 0xff or 0xffff into a register and use AND. */ | |
3398 | return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3); | |
3399 | ||
3400 | /* We can use ANDI. */ | |
3401 | return COSTS_N_INSNS (1); | |
3402 | } | |
3403 | ||
3404 | /* Implement TARGET_RTX_COSTS. */ | |
3405 | ||
cafe096b | 3406 | static bool |
68f932c4 RS |
3407 | mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
3408 | int *total, bool speed) | |
cafe096b EC |
3409 | { |
3410 | enum machine_mode mode = GET_MODE (x); | |
c1bd2d66 | 3411 | bool float_mode_p = FLOAT_MODE_P (mode); |
8144a1a8 RS |
3412 | int cost; |
3413 | rtx addr; | |
3414 | ||
3415 | /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't | |
3416 | appear in the instruction stream, and the cost of a comparison is | |
3417 | really the cost of the branch or scc condition. At the time of | |
65239d20 | 3418 | writing, GCC only uses an explicit outer COMPARE code when optabs |
8144a1a8 RS |
3419 | is testing whether a constant is expensive enough to force into a |
3420 | register. We want optabs to pass such constants through the MIPS | |
3421 | expanders instead, so make all constants very cheap here. */ | |
3422 | if (outer_code == COMPARE) | |
3423 | { | |
3424 | gcc_assert (CONSTANT_P (x)); | |
3425 | *total = 0; | |
3426 | return true; | |
3427 | } | |
c1bd2d66 | 3428 | |
cafe096b EC |
3429 | switch (code) |
3430 | { | |
3431 | case CONST_INT: | |
8144a1a8 RS |
3432 | /* Treat *clear_upper32-style ANDs as having zero cost in the |
3433 | second operand. The cost is entirely in the first operand. | |
3434 | ||
3435 | ??? This is needed because we would otherwise try to CSE | |
3436 | the constant operand. Although that's the right thing for | |
3437 | instructions that continue to be a register operation throughout | |
3438 | compilation, it is disastrous for instructions that could | |
3439 | later be converted into a memory operation. */ | |
3440 | if (TARGET_64BIT | |
3441 | && outer_code == AND | |
3442 | && UINTVAL (x) == 0xffffffff) | |
3443 | { | |
3444 | *total = 0; | |
3445 | return true; | |
3446 | } | |
cafe096b | 3447 | |
8144a1a8 RS |
3448 | if (TARGET_MIPS16) |
3449 | { | |
3450 | cost = mips16_constant_cost (outer_code, INTVAL (x)); | |
3451 | if (cost >= 0) | |
c1bd2d66 | 3452 | { |
8144a1a8 | 3453 | *total = cost; |
c1bd2d66 EC |
3454 | return true; |
3455 | } | |
8144a1a8 RS |
3456 | } |
3457 | else | |
3458 | { | |
3459 | /* When not optimizing for size, we care more about the cost | |
3460 | of hot code, and hot code is often in a loop. If a constant | |
3461 | operand needs to be forced into a register, we will often be | |
3462 | able to hoist the constant load out of the loop, so the load | |
3463 | should not contribute to the cost. */ | |
53d66977 | 3464 | if (speed || mips_immediate_operand_p (outer_code, INTVAL (x))) |
c1bd2d66 EC |
3465 | { |
3466 | *total = 0; | |
3467 | return true; | |
3468 | } | |
3469 | } | |
8144a1a8 | 3470 | /* Fall through. */ |
cafe096b EC |
3471 | |
3472 | case CONST: | |
3473 | case SYMBOL_REF: | |
3474 | case LABEL_REF: | |
3475 | case CONST_DOUBLE: | |
206c2d7a RS |
3476 | if (force_to_mem_operand (x, VOIDmode)) |
3477 | { | |
3478 | *total = COSTS_N_INSNS (1); | |
3479 | return true; | |
3480 | } | |
8144a1a8 RS |
3481 | cost = mips_const_insns (x); |
3482 | if (cost > 0) | |
108b61d5 | 3483 | { |
8144a1a8 RS |
3484 | /* If the constant is likely to be stored in a GPR, SETs of |
3485 | single-insn constants are as cheap as register sets; we | |
3486 | never want to CSE them. | |
3487 | ||
3488 | Don't reduce the cost of storing a floating-point zero in | |
3489 | FPRs. If we have a zero in an FPR for other reasons, we | |
3490 | can get better cfg-cleanup and delayed-branch results by | |
3491 | using it consistently, rather than using $0 sometimes and | |
3492 | an FPR at other times. Also, moves between floating-point | |
3493 | registers are sometimes cheaper than (D)MTC1 $0. */ | |
3494 | if (cost == 1 | |
3495 | && outer_code == SET | |
3496 | && !(float_mode_p && TARGET_HARD_FLOAT)) | |
3497 | cost = 0; | |
3498 | /* When non-MIPS16 code loads a constant N>1 times, we rarely | |
3499 | want to CSE the constant itself. It is usually better to | |
3500 | have N copies of the last operation in the sequence and one | |
3501 | shared copy of the other operations. (Note that this is | |
3502 | not true for MIPS16 code, where the final operation in the | |
3503 | sequence is often an extended instruction.) | |
3504 | ||
3505 | Also, if we have a CONST_INT, we don't know whether it is | |
3506 | for a word or doubleword operation, so we cannot rely on | |
3507 | the result of mips_build_integer. */ | |
3508 | else if (!TARGET_MIPS16 | |
3509 | && (outer_code == SET || mode == VOIDmode)) | |
3510 | cost = 1; | |
3511 | *total = COSTS_N_INSNS (cost); | |
108b61d5 RS |
3512 | return true; |
3513 | } | |
8144a1a8 RS |
3514 | /* The value will need to be fetched from the constant pool. */ |
3515 | *total = CONSTANT_POOL_COST; | |
3516 | return true; | |
3517 | ||
3518 | case MEM: | |
3519 | /* If the address is legitimate, return the number of | |
3520 | instructions it needs. */ | |
3521 | addr = XEXP (x, 0); | |
3522 | cost = mips_address_insns (addr, mode, true); | |
3523 | if (cost > 0) | |
108b61d5 | 3524 | { |
8144a1a8 | 3525 | *total = COSTS_N_INSNS (cost + 1); |
108b61d5 RS |
3526 | return true; |
3527 | } | |
8144a1a8 RS |
3528 | /* Check for a scaled indexed address. */ |
3529 | if (mips_lwxs_address_p (addr)) | |
3530 | { | |
3531 | *total = COSTS_N_INSNS (2); | |
3532 | return true; | |
3533 | } | |
3534 | /* Otherwise use the default handling. */ | |
3535 | return false; | |
cafe096b EC |
3536 | |
3537 | case FFS: | |
3538 | *total = COSTS_N_INSNS (6); | |
8144a1a8 | 3539 | return false; |
cafe096b EC |
3540 | |
3541 | case NOT: | |
8144a1a8 RS |
3542 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); |
3543 | return false; | |
cafe096b EC |
3544 | |
3545 | case AND: | |
8144a1a8 RS |
3546 | /* Check for a *clear_upper32 pattern and treat it like a zero |
3547 | extension. See the pattern's comment for details. */ | |
3548 | if (TARGET_64BIT | |
3549 | && mode == DImode | |
3550 | && CONST_INT_P (XEXP (x, 1)) | |
3551 | && UINTVAL (XEXP (x, 1)) == 0xffffffff) | |
3552 | { | |
3553 | *total = (mips_zero_extend_cost (mode, XEXP (x, 0)) | |
5e8f01f4 | 3554 | + set_src_cost (XEXP (x, 0), speed)); |
8144a1a8 RS |
3555 | return true; |
3556 | } | |
3557 | /* Fall through. */ | |
3558 | ||
cafe096b EC |
3559 | case IOR: |
3560 | case XOR: | |
8144a1a8 | 3561 | /* Double-word operations use two single-word operations. */ |
53d66977 AN |
3562 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2), |
3563 | speed); | |
8144a1a8 | 3564 | return true; |
cafe096b EC |
3565 | |
3566 | case ASHIFT: | |
3567 | case ASHIFTRT: | |
3568 | case LSHIFTRT: | |
8144a1a8 RS |
3569 | case ROTATE: |
3570 | case ROTATERT: | |
3571 | if (CONSTANT_P (XEXP (x, 1))) | |
53d66977 AN |
3572 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3573 | speed); | |
8144a1a8 | 3574 | else |
53d66977 AN |
3575 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12), |
3576 | speed); | |
8144a1a8 | 3577 | return true; |
cafe096b EC |
3578 | |
3579 | case ABS: | |
c1bd2d66 | 3580 | if (float_mode_p) |
8144a1a8 | 3581 | *total = mips_cost->fp_add; |
cafe096b EC |
3582 | else |
3583 | *total = COSTS_N_INSNS (4); | |
8144a1a8 | 3584 | return false; |
cafe096b EC |
3585 | |
3586 | case LO_SUM: | |
8144a1a8 RS |
3587 | /* Low-part immediates need an extended MIPS16 instruction. */ |
3588 | *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1) | |
5e8f01f4 | 3589 | + set_src_cost (XEXP (x, 0), speed)); |
8144a1a8 RS |
3590 | return true; |
3591 | ||
3592 | case LT: | |
3593 | case LTU: | |
3594 | case LE: | |
3595 | case LEU: | |
3596 | case GT: | |
3597 | case GTU: | |
3598 | case GE: | |
3599 | case GEU: | |
3600 | case EQ: | |
3601 | case NE: | |
3602 | case UNORDERED: | |
3603 | case LTGT: | |
3604 | /* Branch comparisons have VOIDmode, so use the first operand's | |
3605 | mode instead. */ | |
3606 | mode = GET_MODE (XEXP (x, 0)); | |
3607 | if (FLOAT_MODE_P (mode)) | |
3608 | { | |
3609 | *total = mips_cost->fp_add; | |
3610 | return false; | |
3611 | } | |
53d66977 AN |
3612 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3613 | speed); | |
cafe096b EC |
3614 | return true; |
3615 | ||
cafe096b | 3616 | case MINUS: |
8144a1a8 | 3617 | if (float_mode_p |
b51469a5 | 3618 | && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) |
8144a1a8 RS |
3619 | && TARGET_FUSED_MADD |
3620 | && !HONOR_NANS (mode) | |
3621 | && !HONOR_SIGNED_ZEROS (mode)) | |
3622 | { | |
3623 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
3624 | associated patterns. */ | |
3625 | rtx op0 = XEXP (x, 0); | |
3626 | rtx op1 = XEXP (x, 1); | |
3627 | if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) | |
3628 | { | |
3629 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
3630 | + set_src_cost (XEXP (XEXP (op0, 0), 0), speed) |
3631 | + set_src_cost (XEXP (op0, 1), speed) | |
3632 | + set_src_cost (op1, speed)); | |
8144a1a8 RS |
3633 | return true; |
3634 | } | |
3635 | if (GET_CODE (op1) == MULT) | |
3636 | { | |
3637 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
3638 | + set_src_cost (op0, speed) |
3639 | + set_src_cost (XEXP (op1, 0), speed) | |
3640 | + set_src_cost (XEXP (op1, 1), speed)); | |
8144a1a8 RS |
3641 | return true; |
3642 | } | |
3643 | } | |
3644 | /* Fall through. */ | |
3645 | ||
3646 | case PLUS: | |
c1bd2d66 EC |
3647 | if (float_mode_p) |
3648 | { | |
65239d20 RS |
3649 | /* If this is part of a MADD or MSUB, treat the PLUS as |
3650 | being free. */ | |
8144a1a8 RS |
3651 | if (ISA_HAS_FP4 |
3652 | && TARGET_FUSED_MADD | |
3653 | && GET_CODE (XEXP (x, 0)) == MULT) | |
3654 | *total = 0; | |
3655 | else | |
3656 | *total = mips_cost->fp_add; | |
3657 | return false; | |
c1bd2d66 EC |
3658 | } |
3659 | ||
8144a1a8 RS |
3660 | /* Double-word operations require three single-word operations and |
3661 | an SLTU. The MIPS16 version then needs to move the result of | |
3662 | the SLTU from $24 to a MIPS16 register. */ | |
3663 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), | |
53d66977 AN |
3664 | COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4), |
3665 | speed); | |
8144a1a8 | 3666 | return true; |
cafe096b EC |
3667 | |
3668 | case NEG: | |
8144a1a8 | 3669 | if (float_mode_p |
b51469a5 | 3670 | && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) |
8144a1a8 RS |
3671 | && TARGET_FUSED_MADD |
3672 | && !HONOR_NANS (mode) | |
3673 | && HONOR_SIGNED_ZEROS (mode)) | |
3674 | { | |
3675 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
3676 | associated patterns. */ | |
3677 | rtx op = XEXP (x, 0); | |
3678 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) | |
3679 | && GET_CODE (XEXP (op, 0)) == MULT) | |
3680 | { | |
3681 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
3682 | + set_src_cost (XEXP (XEXP (op, 0), 0), speed) |
3683 | + set_src_cost (XEXP (XEXP (op, 0), 1), speed) | |
3684 | + set_src_cost (XEXP (op, 1), speed)); | |
8144a1a8 RS |
3685 | return true; |
3686 | } | |
3687 | } | |
3688 | ||
3689 | if (float_mode_p) | |
3690 | *total = mips_cost->fp_add; | |
3691 | else | |
3692 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); | |
cafe096b EC |
3693 | return false; |
3694 | ||
3695 | case MULT: | |
8144a1a8 RS |
3696 | if (float_mode_p) |
3697 | *total = mips_fp_mult_cost (mode); | |
3698 | else if (mode == DImode && !TARGET_64BIT) | |
3699 | /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions, | |
3700 | where the mulsidi3 always includes an MFHI and an MFLO. */ | |
53d66977 AN |
3701 | *total = (speed |
3702 | ? mips_cost->int_mult_si * 3 + 6 | |
3703 | : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)); | |
3704 | else if (!speed) | |
8144a1a8 RS |
3705 | *total = (ISA_HAS_MUL3 ? 1 : 2); |
3706 | else if (mode == DImode) | |
c1bd2d66 | 3707 | *total = mips_cost->int_mult_di; |
8144a1a8 RS |
3708 | else |
3709 | *total = mips_cost->int_mult_si; | |
3710 | return false; | |
cafe096b EC |
3711 | |
3712 | case DIV: | |
8144a1a8 | 3713 | /* Check for a reciprocal. */ |
a1569a0e RS |
3714 | if (float_mode_p |
3715 | && ISA_HAS_FP4 | |
3716 | && flag_unsafe_math_optimizations | |
3717 | && XEXP (x, 0) == CONST1_RTX (mode)) | |
8144a1a8 | 3718 | { |
a1569a0e RS |
3719 | if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) |
3720 | /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the | |
3721 | division as being free. */ | |
5e8f01f4 | 3722 | *total = set_src_cost (XEXP (x, 1), speed); |
a1569a0e | 3723 | else |
bbbbb16a | 3724 | *total = (mips_fp_div_cost (mode) |
5e8f01f4 | 3725 | + set_src_cost (XEXP (x, 1), speed)); |
a1569a0e | 3726 | return true; |
8144a1a8 RS |
3727 | } |
3728 | /* Fall through. */ | |
3729 | ||
3730 | case SQRT: | |
cafe096b | 3731 | case MOD: |
c1bd2d66 EC |
3732 | if (float_mode_p) |
3733 | { | |
8144a1a8 RS |
3734 | *total = mips_fp_div_cost (mode); |
3735 | return false; | |
c1bd2d66 | 3736 | } |
031a26c5 | 3737 | /* Fall through. */ |
cafe096b EC |
3738 | |
3739 | case UDIV: | |
3740 | case UMOD: | |
53d66977 | 3741 | if (!speed) |
8144a1a8 RS |
3742 | { |
3743 | /* It is our responsibility to make division by a power of 2 | |
3744 | as cheap as 2 register additions if we want the division | |
3745 | expanders to be used for such operations; see the setting | |
3746 | of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16 | |
3747 | should always produce shorter code than using | |
3748 | expand_sdiv2_pow2. */ | |
3749 | if (TARGET_MIPS16 | |
3750 | && CONST_INT_P (XEXP (x, 1)) | |
3751 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
3752 | { | |
5e8f01f4 | 3753 | *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed); |
8144a1a8 RS |
3754 | return true; |
3755 | } | |
3756 | *total = COSTS_N_INSNS (mips_idiv_insns ()); | |
3757 | } | |
3758 | else if (mode == DImode) | |
c1bd2d66 | 3759 | *total = mips_cost->int_div_di; |
cafe096b | 3760 | else |
c1bd2d66 | 3761 | *total = mips_cost->int_div_si; |
8144a1a8 | 3762 | return false; |
cafe096b EC |
3763 | |
3764 | case SIGN_EXTEND: | |
8144a1a8 RS |
3765 | *total = mips_sign_extend_cost (mode, XEXP (x, 0)); |
3766 | return false; | |
cafe096b EC |
3767 | |
3768 | case ZERO_EXTEND: | |
8144a1a8 RS |
3769 | *total = mips_zero_extend_cost (mode, XEXP (x, 0)); |
3770 | return false; | |
cafe096b | 3771 | |
c1bd2d66 EC |
3772 | case FLOAT: |
3773 | case UNSIGNED_FLOAT: | |
3774 | case FIX: | |
3775 | case FLOAT_EXTEND: | |
3776 | case FLOAT_TRUNCATE: | |
c1bd2d66 | 3777 | *total = mips_cost->fp_add; |
8144a1a8 | 3778 | return false; |
c1bd2d66 | 3779 | |
cafe096b EC |
3780 | default: |
3781 | return false; | |
3782 | } | |
3783 | } | |
3784 | ||
65239d20 | 3785 | /* Implement TARGET_ADDRESS_COST. */ |
cafe096b EC |
3786 | |
3787 | static int | |
f40751dd | 3788 | mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED) |
cafe096b | 3789 | { |
5955b0a3 | 3790 | return mips_address_insns (addr, SImode, false); |
cafe096b | 3791 | } |
cee98a59 | 3792 | \f |
6f5a62e9 RS |
3793 | /* Information about a single instruction in a multi-instruction |
3794 | asm sequence. */ | |
3795 | struct mips_multi_member { | |
3796 | /* True if this is a label, false if it is code. */ | |
3797 | bool is_label_p; | |
3798 | ||
3799 | /* The output_asm_insn format of the instruction. */ | |
3800 | const char *format; | |
3801 | ||
3802 | /* The operands to the instruction. */ | |
3803 | rtx operands[MAX_RECOG_OPERANDS]; | |
3804 | }; | |
3805 | typedef struct mips_multi_member mips_multi_member; | |
3806 | ||
3807 | /* Vector definitions for the above. */ | |
3808 | DEF_VEC_O(mips_multi_member); | |
3809 | DEF_VEC_ALLOC_O(mips_multi_member, heap); | |
3810 | ||
3811 | /* The instructions that make up the current multi-insn sequence. */ | |
3812 | static VEC (mips_multi_member, heap) *mips_multi_members; | |
3813 | ||
3814 | /* How many instructions (as opposed to labels) are in the current | |
3815 | multi-insn sequence. */ | |
3816 | static unsigned int mips_multi_num_insns; | |
3817 | ||
3818 | /* Start a new multi-insn sequence. */ | |
3819 | ||
3820 | static void | |
3821 | mips_multi_start (void) | |
3822 | { | |
3823 | VEC_truncate (mips_multi_member, mips_multi_members, 0); | |
3824 | mips_multi_num_insns = 0; | |
3825 | } | |
3826 | ||
3827 | /* Add a new, uninitialized member to the current multi-insn sequence. */ | |
3828 | ||
3829 | static struct mips_multi_member * | |
3830 | mips_multi_add (void) | |
3831 | { | |
3832 | return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0); | |
3833 | } | |
3834 | ||
3835 | /* Add a normal insn with the given asm format to the current multi-insn | |
3836 | sequence. The other arguments are a null-terminated list of operands. */ | |
3837 | ||
3838 | static void | |
3839 | mips_multi_add_insn (const char *format, ...) | |
3840 | { | |
3841 | struct mips_multi_member *member; | |
3842 | va_list ap; | |
3843 | unsigned int i; | |
3844 | rtx op; | |
3845 | ||
3846 | member = mips_multi_add (); | |
3847 | member->is_label_p = false; | |
3848 | member->format = format; | |
3849 | va_start (ap, format); | |
3850 | i = 0; | |
3851 | while ((op = va_arg (ap, rtx))) | |
3852 | member->operands[i++] = op; | |
3853 | va_end (ap); | |
3854 | mips_multi_num_insns++; | |
3855 | } | |
3856 | ||
3857 | /* Add the given label definition to the current multi-insn sequence. | |
3858 | The definition should include the colon. */ | |
3859 | ||
3860 | static void | |
3861 | mips_multi_add_label (const char *label) | |
3862 | { | |
3863 | struct mips_multi_member *member; | |
3864 | ||
3865 | member = mips_multi_add (); | |
3866 | member->is_label_p = true; | |
3867 | member->format = label; | |
3868 | } | |
3869 | ||
3870 | /* Return the index of the last member of the current multi-insn sequence. */ | |
3871 | ||
3872 | static unsigned int | |
3873 | mips_multi_last_index (void) | |
3874 | { | |
3875 | return VEC_length (mips_multi_member, mips_multi_members) - 1; | |
3876 | } | |
3877 | ||
3878 | /* Add a copy of an existing instruction to the current multi-insn | |
3879 | sequence. I is the index of the instruction that should be copied. */ | |
3880 | ||
3881 | static void | |
3882 | mips_multi_copy_insn (unsigned int i) | |
3883 | { | |
3884 | struct mips_multi_member *member; | |
3885 | ||
3886 | member = mips_multi_add (); | |
3887 | memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i), | |
3888 | sizeof (*member)); | |
3889 | gcc_assert (!member->is_label_p); | |
3890 | } | |
3891 | ||
3892 | /* Change the operand of an existing instruction in the current | |
3893 | multi-insn sequence. I is the index of the instruction, | |
3894 | OP is the index of the operand, and X is the new value. */ | |
3895 | ||
3896 | static void | |
3897 | mips_multi_set_operand (unsigned int i, unsigned int op, rtx x) | |
3898 | { | |
3899 | VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x; | |
3900 | } | |
3901 | ||
3902 | /* Write out the asm code for the current multi-insn sequence. */ | |
3903 | ||
3904 | static void | |
3905 | mips_multi_write (void) | |
3906 | { | |
3907 | struct mips_multi_member *member; | |
3908 | unsigned int i; | |
3909 | ||
ac47786e | 3910 | FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member) |
6f5a62e9 RS |
3911 | if (member->is_label_p) |
3912 | fprintf (asm_out_file, "%s\n", member->format); | |
3913 | else | |
3914 | output_asm_insn (member->format, member->operands); | |
3915 | } | |
3916 | \f | |
5b0f0db6 RS |
3917 | /* Return one word of double-word value OP, taking into account the fixed |
3918 | endianness of certain registers. HIGH_P is true to select the high part, | |
3919 | false to select the low part. */ | |
92544bdf | 3920 | |
5b0f0db6 | 3921 | rtx |
65239d20 | 3922 | mips_subword (rtx op, bool high_p) |
5b0f0db6 | 3923 | { |
0064fbe9 | 3924 | unsigned int byte, offset; |
5b0f0db6 | 3925 | enum machine_mode mode; |
cee98a59 | 3926 | |
5b0f0db6 RS |
3927 | mode = GET_MODE (op); |
3928 | if (mode == VOIDmode) | |
21dfc6dc | 3929 | mode = TARGET_64BIT ? TImode : DImode; |
cee98a59 | 3930 | |
5b0f0db6 RS |
3931 | if (TARGET_BIG_ENDIAN ? !high_p : high_p) |
3932 | byte = UNITS_PER_WORD; | |
3933 | else | |
3934 | byte = 0; | |
cee98a59 | 3935 | |
48156a39 | 3936 | if (FP_REG_RTX_P (op)) |
0064fbe9 RS |
3937 | { |
3938 | /* Paired FPRs are always ordered little-endian. */ | |
3939 | offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0); | |
3940 | return gen_rtx_REG (word_mode, REGNO (op) + offset); | |
3941 | } | |
cee98a59 | 3942 | |
66083422 | 3943 | if (MEM_P (op)) |
108b61d5 | 3944 | return mips_rewrite_small_data (adjust_address (op, word_mode, byte)); |
b8eb88d0 | 3945 | |
5b0f0db6 RS |
3946 | return simplify_gen_subreg (word_mode, op, mode, byte); |
3947 | } | |
cee98a59 | 3948 | |
5b0f0db6 | 3949 | /* Return true if a 64-bit move from SRC to DEST should be split into two. */ |
cee98a59 | 3950 | |
5b0f0db6 | 3951 | bool |
b4966b1b | 3952 | mips_split_64bit_move_p (rtx dest, rtx src) |
5b0f0db6 RS |
3953 | { |
3954 | if (TARGET_64BIT) | |
3955 | return false; | |
cee98a59 | 3956 | |
65239d20 RS |
3957 | /* FPR-to-FPR moves can be done in a single instruction, if they're |
3958 | allowed at all. */ | |
5b0f0db6 RS |
3959 | if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) |
3960 | return false; | |
cee98a59 | 3961 | |
f457938f RS |
3962 | /* Check for floating-point loads and stores. */ |
3963 | if (ISA_HAS_LDC1_SDC1) | |
5b0f0db6 | 3964 | { |
66083422 | 3965 | if (FP_REG_RTX_P (dest) && MEM_P (src)) |
5b0f0db6 | 3966 | return false; |
66083422 | 3967 | if (FP_REG_RTX_P (src) && MEM_P (dest)) |
5b0f0db6 RS |
3968 | return false; |
3969 | } | |
3970 | return true; | |
3971 | } | |
b8eb88d0 | 3972 | |
0064fbe9 RS |
3973 | /* Split a doubleword move from SRC to DEST. On 32-bit targets, |
3974 | this function handles 64-bit moves for which mips_split_64bit_move_p | |
3975 | holds. For 64-bit targets, this function handles 128-bit moves. */ | |
cee98a59 | 3976 | |
5b0f0db6 | 3977 | void |
0064fbe9 | 3978 | mips_split_doubleword_move (rtx dest, rtx src) |
5b0f0db6 | 3979 | { |
21dfc6dc RS |
3980 | rtx low_dest; |
3981 | ||
0064fbe9 | 3982 | if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) |
5b0f0db6 | 3983 | { |
0064fbe9 RS |
3984 | if (!TARGET_64BIT && GET_MODE (dest) == DImode) |
3985 | emit_insn (gen_move_doubleword_fprdi (dest, src)); | |
3986 | else if (!TARGET_64BIT && GET_MODE (dest) == DFmode) | |
3987 | emit_insn (gen_move_doubleword_fprdf (dest, src)); | |
e5a2b69d RS |
3988 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode) |
3989 | emit_insn (gen_move_doubleword_fprv2sf (dest, src)); | |
93581857 MS |
3990 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode) |
3991 | emit_insn (gen_move_doubleword_fprv2si (dest, src)); | |
3992 | else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode) | |
3993 | emit_insn (gen_move_doubleword_fprv4hi (dest, src)); | |
3994 | else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode) | |
3995 | emit_insn (gen_move_doubleword_fprv8qi (dest, src)); | |
0064fbe9 RS |
3996 | else if (TARGET_64BIT && GET_MODE (dest) == TFmode) |
3997 | emit_insn (gen_move_doubleword_fprtf (dest, src)); | |
6f428062 | 3998 | else |
0064fbe9 | 3999 | gcc_unreachable (); |
5b0f0db6 | 4000 | } |
21dfc6dc RS |
4001 | else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) |
4002 | { | |
4003 | low_dest = mips_subword (dest, false); | |
4004 | mips_emit_move (low_dest, mips_subword (src, false)); | |
4005 | if (TARGET_64BIT) | |
4006 | emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); | |
4007 | else | |
4008 | emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); | |
4009 | } | |
4010 | else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) | |
4011 | { | |
4012 | mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); | |
4013 | if (TARGET_64BIT) | |
4014 | emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); | |
4015 | else | |
4016 | emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); | |
4017 | } | |
5b0f0db6 RS |
4018 | else |
4019 | { | |
4020 | /* The operation can be split into two normal moves. Decide in | |
4021 | which order to do them. */ | |
65239d20 | 4022 | low_dest = mips_subword (dest, false); |
66083422 | 4023 | if (REG_P (low_dest) |
5b0f0db6 | 4024 | && reg_overlap_mentioned_p (low_dest, src)) |
cee98a59 | 4025 | { |
65239d20 RS |
4026 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); |
4027 | mips_emit_move (low_dest, mips_subword (src, false)); | |
cee98a59 | 4028 | } |
5b0f0db6 | 4029 | else |
cee98a59 | 4030 | { |
65239d20 RS |
4031 | mips_emit_move (low_dest, mips_subword (src, false)); |
4032 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); | |
cee98a59 | 4033 | } |
5b0f0db6 RS |
4034 | } |
4035 | } | |
4036 | \f | |
4037 | /* Return the appropriate instructions to move SRC into DEST. Assume | |
4038 | that SRC is operand 1 and DEST is operand 0. */ | |
cee98a59 | 4039 | |
5b0f0db6 | 4040 | const char * |
b4966b1b | 4041 | mips_output_move (rtx dest, rtx src) |
5b0f0db6 RS |
4042 | { |
4043 | enum rtx_code dest_code, src_code; | |
65239d20 | 4044 | enum machine_mode mode; |
c93c5160 | 4045 | enum mips_symbol_type symbol_type; |
5b0f0db6 | 4046 | bool dbl_p; |
cee98a59 | 4047 | |
5b0f0db6 RS |
4048 | dest_code = GET_CODE (dest); |
4049 | src_code = GET_CODE (src); | |
65239d20 RS |
4050 | mode = GET_MODE (dest); |
4051 | dbl_p = (GET_MODE_SIZE (mode) == 8); | |
cee98a59 | 4052 | |
5b0f0db6 RS |
4053 | if (dbl_p && mips_split_64bit_move_p (dest, src)) |
4054 | return "#"; | |
910628b8 | 4055 | |
5b0f0db6 | 4056 | if ((src_code == REG && GP_REG_P (REGNO (src))) |
65239d20 | 4057 | || (!TARGET_MIPS16 && src == CONST0_RTX (mode))) |
5b0f0db6 RS |
4058 | { |
4059 | if (dest_code == REG) | |
910628b8 | 4060 | { |
5b0f0db6 | 4061 | if (GP_REG_P (REGNO (dest))) |
245115a4 | 4062 | return "move\t%0,%z1"; |
cafe096b | 4063 | |
21dfc6dc RS |
4064 | /* Moves to HI are handled by special .md insns. */ |
4065 | if (REGNO (dest) == LO_REGNUM) | |
4066 | return "mtlo\t%z1"; | |
cafe096b | 4067 | |
118ea793 CF |
4068 | if (DSP_ACC_REG_P (REGNO (dest))) |
4069 | { | |
4070 | static char retval[] = "mt__\t%z1,%q0"; | |
65239d20 | 4071 | |
118ea793 CF |
4072 | retval[2] = reg_names[REGNO (dest)][4]; |
4073 | retval[3] = reg_names[REGNO (dest)][5]; | |
4074 | return retval; | |
4075 | } | |
4076 | ||
5b0f0db6 | 4077 | if (FP_REG_P (REGNO (dest))) |
65239d20 | 4078 | return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0"; |
cafe096b | 4079 | |
5b0f0db6 RS |
4080 | if (ALL_COP_REG_P (REGNO (dest))) |
4081 | { | |
4082 | static char retval[] = "dmtc_\t%z1,%0"; | |
cafe096b | 4083 | |
5b0f0db6 | 4084 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); |
65239d20 | 4085 | return dbl_p ? retval : retval + 1; |
5b0f0db6 RS |
4086 | } |
4087 | } | |
4088 | if (dest_code == MEM) | |
21dfc6dc RS |
4089 | switch (GET_MODE_SIZE (mode)) |
4090 | { | |
4091 | case 1: return "sb\t%z1,%0"; | |
4092 | case 2: return "sh\t%z1,%0"; | |
4093 | case 4: return "sw\t%z1,%0"; | |
4094 | case 8: return "sd\t%z1,%0"; | |
4095 | } | |
cee98a59 | 4096 | } |
5b0f0db6 | 4097 | if (dest_code == REG && GP_REG_P (REGNO (dest))) |
cee98a59 | 4098 | { |
5b0f0db6 | 4099 | if (src_code == REG) |
cee98a59 | 4100 | { |
21dfc6dc RS |
4101 | /* Moves from HI are handled by special .md insns. */ |
4102 | if (REGNO (src) == LO_REGNUM) | |
4103 | { | |
4104 | /* When generating VR4120 or VR4130 code, we use MACC and | |
4105 | DMACC instead of MFLO. This avoids both the normal | |
4106 | MIPS III HI/LO hazards and the errata related to | |
4107 | -mfix-vr4130. */ | |
4108 | if (ISA_HAS_MACCHI) | |
4109 | return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; | |
4110 | return "mflo\t%0"; | |
4111 | } | |
65239d20 | 4112 | |
118ea793 CF |
4113 | if (DSP_ACC_REG_P (REGNO (src))) |
4114 | { | |
4115 | static char retval[] = "mf__\t%0,%q1"; | |
65239d20 | 4116 | |
118ea793 CF |
4117 | retval[2] = reg_names[REGNO (src)][4]; |
4118 | retval[3] = reg_names[REGNO (src)][5]; | |
4119 | return retval; | |
4120 | } | |
4121 | ||
5b0f0db6 | 4122 | if (FP_REG_P (REGNO (src))) |
65239d20 | 4123 | return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1"; |
cee98a59 | 4124 | |
5b0f0db6 | 4125 | if (ALL_COP_REG_P (REGNO (src))) |
d604bca3 | 4126 | { |
5b0f0db6 | 4127 | static char retval[] = "dmfc_\t%0,%1"; |
d604bca3 | 4128 | |
5b0f0db6 | 4129 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); |
65239d20 | 4130 | return dbl_p ? retval : retval + 1; |
d604bca3 | 4131 | } |
65239d20 RS |
4132 | |
4133 | if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC) | |
4134 | return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1"; | |
cee98a59 MM |
4135 | } |
4136 | ||
5b0f0db6 | 4137 | if (src_code == MEM) |
21dfc6dc RS |
4138 | switch (GET_MODE_SIZE (mode)) |
4139 | { | |
4140 | case 1: return "lbu\t%0,%1"; | |
4141 | case 2: return "lhu\t%0,%1"; | |
4142 | case 4: return "lw\t%0,%1"; | |
4143 | case 8: return "ld\t%0,%1"; | |
4144 | } | |
cee98a59 | 4145 | |
5b0f0db6 | 4146 | if (src_code == CONST_INT) |
cee98a59 | 4147 | { |
65239d20 RS |
4148 | /* Don't use the X format for the operand itself, because that |
4149 | will give out-of-range numbers for 64-bit hosts and 32-bit | |
4150 | targets. */ | |
5b0f0db6 RS |
4151 | if (!TARGET_MIPS16) |
4152 | return "li\t%0,%1\t\t\t# %X1"; | |
4153 | ||
65239d20 | 4154 | if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) |
5b0f0db6 RS |
4155 | return "li\t%0,%1"; |
4156 | ||
65239d20 | 4157 | if (SMALL_OPERAND_UNSIGNED (-INTVAL (src))) |
bb732af8 | 4158 | return "#"; |
cee98a59 MM |
4159 | } |
4160 | ||
5b0f0db6 | 4161 | if (src_code == HIGH) |
c93c5160 | 4162 | return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; |
5b0f0db6 | 4163 | |
108b61d5 RS |
4164 | if (CONST_GP_P (src)) |
4165 | return "move\t%0,%1"; | |
7dac2f89 | 4166 | |
c93c5160 RS |
4167 | if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type) |
4168 | && mips_lo_relocs[symbol_type] != 0) | |
4169 | { | |
4170 | /* A signed 16-bit constant formed by applying a relocation | |
4171 | operator to a symbolic address. */ | |
4172 | gcc_assert (!mips_split_p[symbol_type]); | |
4173 | return "li\t%0,%R1"; | |
4174 | } | |
4175 | ||
108b61d5 | 4176 | if (symbolic_operand (src, VOIDmode)) |
c93c5160 RS |
4177 | { |
4178 | gcc_assert (TARGET_MIPS16 | |
4179 | ? TARGET_MIPS16_TEXT_LOADS | |
4180 | : !TARGET_EXPLICIT_RELOCS); | |
65239d20 | 4181 | return dbl_p ? "dla\t%0,%1" : "la\t%0,%1"; |
c93c5160 | 4182 | } |
cee98a59 | 4183 | } |
5b0f0db6 RS |
4184 | if (src_code == REG && FP_REG_P (REGNO (src))) |
4185 | { | |
4186 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
06a4ab70 CF |
4187 | { |
4188 | if (GET_MODE (dest) == V2SFmode) | |
4189 | return "mov.ps\t%0,%1"; | |
4190 | else | |
65239d20 | 4191 | return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1"; |
06a4ab70 | 4192 | } |
cee98a59 | 4193 | |
5b0f0db6 | 4194 | if (dest_code == MEM) |
65239d20 | 4195 | return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0"; |
5b0f0db6 RS |
4196 | } |
4197 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
cee98a59 | 4198 | { |
5b0f0db6 | 4199 | if (src_code == MEM) |
65239d20 | 4200 | return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1"; |
cee98a59 | 4201 | } |
5b0f0db6 RS |
4202 | if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM) |
4203 | { | |
4204 | static char retval[] = "l_c_\t%0,%1"; | |
cee98a59 | 4205 | |
5b0f0db6 RS |
4206 | retval[1] = (dbl_p ? 'd' : 'w'); |
4207 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); | |
4208 | return retval; | |
4209 | } | |
4210 | if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src))) | |
4211 | { | |
4212 | static char retval[] = "s_c_\t%1,%0"; | |
cee98a59 | 4213 | |
5b0f0db6 RS |
4214 | retval[1] = (dbl_p ? 'd' : 'w'); |
4215 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); | |
4216 | return retval; | |
4217 | } | |
7ad769fe | 4218 | gcc_unreachable (); |
cee98a59 | 4219 | } |
b2471838 | 4220 | \f |
65239d20 RS |
4221 | /* Return true if CMP1 is a suitable second operand for integer ordering |
4222 | test CODE. See also the *sCC patterns in mips.md. */ | |
34b650b3 | 4223 | |
a012718f | 4224 | static bool |
65239d20 | 4225 | mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) |
a012718f RS |
4226 | { |
4227 | switch (code) | |
34b650b3 | 4228 | { |
a012718f RS |
4229 | case GT: |
4230 | case GTU: | |
4231 | return reg_or_0_operand (cmp1, VOIDmode); | |
34b650b3 | 4232 | |
a012718f RS |
4233 | case GE: |
4234 | case GEU: | |
4235 | return !TARGET_MIPS16 && cmp1 == const1_rtx; | |
34b650b3 | 4236 | |
a012718f RS |
4237 | case LT: |
4238 | case LTU: | |
4239 | return arith_operand (cmp1, VOIDmode); | |
34b650b3 | 4240 | |
a012718f RS |
4241 | case LE: |
4242 | return sle_operand (cmp1, VOIDmode); | |
34b650b3 | 4243 | |
a012718f RS |
4244 | case LEU: |
4245 | return sleu_operand (cmp1, VOIDmode); | |
34b650b3 | 4246 | |
a012718f | 4247 | default: |
7ad769fe | 4248 | gcc_unreachable (); |
34b650b3 | 4249 | } |
a012718f | 4250 | } |
34b650b3 | 4251 | |
65239d20 RS |
4252 | /* Return true if *CMP1 (of mode MODE) is a valid second operand for |
4253 | integer ordering test *CODE, or if an equivalent combination can | |
4254 | be formed by adjusting *CODE and *CMP1. When returning true, update | |
4255 | *CODE and *CMP1 with the chosen code and operand, otherwise leave | |
4256 | them alone. */ | |
ecd48505 EC |
4257 | |
4258 | static bool | |
65239d20 RS |
4259 | mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, |
4260 | enum machine_mode mode) | |
ecd48505 | 4261 | { |
213ce6f2 | 4262 | HOST_WIDE_INT plus_one; |
ecd48505 | 4263 | |
65239d20 | 4264 | if (mips_int_order_operand_ok_p (*code, *cmp1)) |
213ce6f2 | 4265 | return true; |
d8934cf1 | 4266 | |
47ac44d6 | 4267 | if (CONST_INT_P (*cmp1)) |
213ce6f2 RS |
4268 | switch (*code) |
4269 | { | |
4270 | case LE: | |
4271 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4272 | if (INTVAL (*cmp1) < plus_one) | |
4273 | { | |
4274 | *code = LT; | |
4275 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4276 | return true; | |
4277 | } | |
4278 | break; | |
4279 | ||
4280 | case LEU: | |
4281 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4282 | if (plus_one != 0) | |
4283 | { | |
4284 | *code = LTU; | |
4285 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4286 | return true; | |
4287 | } | |
4288 | break; | |
4289 | ||
4290 | default: | |
4291 | break; | |
4292 | } | |
ecd48505 | 4293 | return false; |
ecd48505 EC |
4294 | } |
4295 | ||
65239d20 | 4296 | /* Compare CMP0 and CMP1 using ordering test CODE and store the result |
5fb79e4c AN |
4297 | in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR |
4298 | is nonnull, it's OK to set TARGET to the inverse of the result and | |
4299 | flip *INVERT_PTR instead. */ | |
f5963e61 | 4300 | |
a012718f | 4301 | static void |
65239d20 | 4302 | mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, |
a012718f RS |
4303 | rtx target, rtx cmp0, rtx cmp1) |
4304 | { | |
65239d20 RS |
4305 | enum machine_mode mode; |
4306 | ||
213ce6f2 RS |
4307 | /* First see if there is a MIPS instruction that can do this operation. |
4308 | If not, try doing the same for the inverse operation. If that also | |
4309 | fails, force CMP1 into a register and try again. */ | |
5fb79e4c | 4310 | mode = GET_MODE (cmp0); |
65239d20 | 4311 | if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) |
ecd48505 | 4312 | mips_emit_binary (code, target, cmp0, cmp1); |
bbdb5552 MM |
4313 | else |
4314 | { | |
a012718f | 4315 | enum rtx_code inv_code = reverse_condition (code); |
65239d20 | 4316 | if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode)) |
a012718f | 4317 | { |
65239d20 RS |
4318 | cmp1 = force_reg (mode, cmp1); |
4319 | mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); | |
a012718f RS |
4320 | } |
4321 | else if (invert_ptr == 0) | |
2bcb2ab3 | 4322 | { |
49bce30a RS |
4323 | rtx inv_target; |
4324 | ||
4325 | inv_target = mips_force_binary (GET_MODE (target), | |
4326 | inv_code, cmp0, cmp1); | |
a012718f | 4327 | mips_emit_binary (XOR, target, inv_target, const1_rtx); |
2bcb2ab3 GK |
4328 | } |
4329 | else | |
4330 | { | |
a012718f RS |
4331 | *invert_ptr = !*invert_ptr; |
4332 | mips_emit_binary (inv_code, target, cmp0, cmp1); | |
2bcb2ab3 | 4333 | } |
34b650b3 | 4334 | } |
a012718f | 4335 | } |
34b650b3 | 4336 | |
a012718f RS |
4337 | /* Return a register that is zero iff CMP0 and CMP1 are equal. |
4338 | The register will have the same mode as CMP0. */ | |
34b650b3 | 4339 | |
a012718f RS |
4340 | static rtx |
4341 | mips_zero_if_equal (rtx cmp0, rtx cmp1) | |
4342 | { | |
4343 | if (cmp1 == const0_rtx) | |
4344 | return cmp0; | |
2bcb2ab3 | 4345 | |
f1286257 RS |
4346 | if (uns_arith_operand (cmp1, VOIDmode)) |
4347 | return expand_binop (GET_MODE (cmp0), xor_optab, | |
4348 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); | |
4349 | ||
4350 | return expand_binop (GET_MODE (cmp0), sub_optab, | |
a012718f RS |
4351 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); |
4352 | } | |
4353 | ||
ec4fc7ed | 4354 | /* Convert *CODE into a code that can be used in a floating-point |
65239d20 | 4355 | scc instruction (C.cond.fmt). Return true if the values of |
ec4fc7ed RS |
4356 | the condition code registers will be inverted, with 0 indicating |
4357 | that the condition holds. */ | |
4358 | ||
4359 | static bool | |
65239d20 | 4360 | mips_reversed_fp_cond (enum rtx_code *code) |
ec4fc7ed RS |
4361 | { |
4362 | switch (*code) | |
4363 | { | |
4364 | case NE: | |
4365 | case LTGT: | |
4366 | case ORDERED: | |
4367 | *code = reverse_condition_maybe_unordered (*code); | |
4368 | return true; | |
4369 | ||
4370 | default: | |
4371 | return false; | |
4372 | } | |
4373 | } | |
4374 | ||
bb592806 | 4375 | /* Convert a comparison into something that can be used in a branch or |
f90b7a5a PB |
4376 | conditional move. On entry, *OP0 and *OP1 are the values being |
4377 | compared and *CODE is the code used to compare them. | |
bb592806 RS |
4378 | |
4379 | Update *CODE, *OP0 and *OP1 so that they describe the final comparison. | |
65239d20 | 4380 | If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible, |
bb592806 RS |
4381 | otherwise any standard branch condition can be used. The standard branch |
4382 | conditions are: | |
4383 | ||
65239d20 | 4384 | - EQ or NE between two registers. |
bb592806 RS |
4385 | - any comparison between a register and zero. */ |
4386 | ||
4387 | static void | |
4388 | mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) | |
4389 | { | |
f90b7a5a PB |
4390 | rtx cmp_op0 = *op0; |
4391 | rtx cmp_op1 = *op1; | |
4392 | ||
4393 | if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) | |
bb592806 | 4394 | { |
f90b7a5a PB |
4395 | if (!need_eq_ne_p && *op1 == const0_rtx) |
4396 | ; | |
bb592806 RS |
4397 | else if (*code == EQ || *code == NE) |
4398 | { | |
4399 | if (need_eq_ne_p) | |
4400 | { | |
f90b7a5a | 4401 | *op0 = mips_zero_if_equal (cmp_op0, cmp_op1); |
bb592806 RS |
4402 | *op1 = const0_rtx; |
4403 | } | |
4404 | else | |
f90b7a5a | 4405 | *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); |
bb592806 RS |
4406 | } |
4407 | else | |
4408 | { | |
4409 | /* The comparison needs a separate scc instruction. Store the | |
4410 | result of the scc in *OP0 and compare it against zero. */ | |
4411 | bool invert = false; | |
f90b7a5a PB |
4412 | *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); |
4413 | mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1); | |
bb592806 | 4414 | *code = (invert ? EQ : NE); |
65239d20 | 4415 | *op1 = const0_rtx; |
bb592806 RS |
4416 | } |
4417 | } | |
f90b7a5a | 4418 | else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0))) |
9fc777ad CF |
4419 | { |
4420 | *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM); | |
f90b7a5a | 4421 | mips_emit_binary (*code, *op0, cmp_op0, cmp_op1); |
9fc777ad CF |
4422 | *code = NE; |
4423 | *op1 = const0_rtx; | |
4424 | } | |
bb592806 RS |
4425 | else |
4426 | { | |
4427 | enum rtx_code cmp_code; | |
4428 | ||
65239d20 | 4429 | /* Floating-point tests use a separate C.cond.fmt comparison to |
bb592806 RS |
4430 | set a condition code register. The branch or conditional move |
4431 | will then compare that register against zero. | |
4432 | ||
4433 | Set CMP_CODE to the code of the comparison instruction and | |
4434 | *CODE to the code that the branch or move should use. */ | |
ec4fc7ed | 4435 | cmp_code = *code; |
65239d20 | 4436 | *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; |
bb592806 RS |
4437 | *op0 = (ISA_HAS_8CC |
4438 | ? gen_reg_rtx (CCmode) | |
4439 | : gen_rtx_REG (CCmode, FPSW_REGNUM)); | |
4440 | *op1 = const0_rtx; | |
f90b7a5a | 4441 | mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); |
bb592806 RS |
4442 | } |
4443 | } | |
4444 | \f | |
f90b7a5a PB |
4445 | /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] |
4446 | and OPERAND[3]. Store the result in OPERANDS[0]. | |
a012718f | 4447 | |
f90b7a5a PB |
4448 | On 64-bit targets, the mode of the comparison and target will always be |
4449 | SImode, thus possibly narrower than that of the comparison's operands. */ | |
34b650b3 | 4450 | |
f90b7a5a PB |
4451 | void |
4452 | mips_expand_scc (rtx operands[]) | |
a012718f | 4453 | { |
f90b7a5a PB |
4454 | rtx target = operands[0]; |
4455 | enum rtx_code code = GET_CODE (operands[1]); | |
4456 | rtx op0 = operands[2]; | |
4457 | rtx op1 = operands[3]; | |
4458 | ||
4459 | gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); | |
a012718f | 4460 | |
a012718f RS |
4461 | if (code == EQ || code == NE) |
4462 | { | |
5299815b | 4463 | if (ISA_HAS_SEQ_SNE |
f90b7a5a PB |
4464 | && reg_imm10_operand (op1, GET_MODE (op1))) |
4465 | mips_emit_binary (code, target, op0, op1); | |
5299815b AN |
4466 | else |
4467 | { | |
f90b7a5a | 4468 | rtx zie = mips_zero_if_equal (op0, op1); |
5299815b AN |
4469 | mips_emit_binary (code, target, zie, const0_rtx); |
4470 | } | |
a012718f RS |
4471 | } |
4472 | else | |
f90b7a5a | 4473 | mips_emit_int_order_test (code, 0, target, op0, op1); |
34b650b3 | 4474 | } |
8ab907e8 | 4475 | |
f90b7a5a PB |
4476 | /* Compare OPERANDS[1] with OPERANDS[2] using comparison code |
4477 | CODE and jump to OPERANDS[3] if the condition holds. */ | |
cee98a59 MM |
4478 | |
4479 | void | |
f90b7a5a | 4480 | mips_expand_conditional_branch (rtx *operands) |
cee98a59 | 4481 | { |
f90b7a5a PB |
4482 | enum rtx_code code = GET_CODE (operands[0]); |
4483 | rtx op0 = operands[1]; | |
4484 | rtx op1 = operands[2]; | |
4485 | rtx condition; | |
f5963e61 | 4486 | |
bb592806 | 4487 | mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16); |
a8c1d5f8 | 4488 | condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
f90b7a5a | 4489 | emit_jump_insn (gen_condjump (condition, operands[3])); |
b8eb88d0 | 4490 | } |
34b650b3 | 4491 | |
ec4fc7ed RS |
4492 | /* Implement: |
4493 | ||
4494 | (set temp (COND:CCV2 CMP_OP0 CMP_OP1)) | |
4495 | (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */ | |
4496 | ||
4497 | void | |
4498 | mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src, | |
4499 | enum rtx_code cond, rtx cmp_op0, rtx cmp_op1) | |
4500 | { | |
4501 | rtx cmp_result; | |
4502 | bool reversed_p; | |
4503 | ||
65239d20 | 4504 | reversed_p = mips_reversed_fp_cond (&cond); |
ec4fc7ed RS |
4505 | cmp_result = gen_reg_rtx (CCV2mode); |
4506 | emit_insn (gen_scc_ps (cmp_result, | |
4507 | gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1))); | |
4508 | if (reversed_p) | |
4509 | emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src, | |
4510 | cmp_result)); | |
4511 | else | |
4512 | emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src, | |
4513 | cmp_result)); | |
4514 | } | |
4515 | ||
f90b7a5a PB |
4516 | /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] |
4517 | if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */ | |
cee98a59 | 4518 | |
b8eb88d0 | 4519 | void |
65239d20 | 4520 | mips_expand_conditional_move (rtx *operands) |
b8eb88d0 | 4521 | { |
f90b7a5a PB |
4522 | rtx cond; |
4523 | enum rtx_code code = GET_CODE (operands[1]); | |
4524 | rtx op0 = XEXP (operands[1], 0); | |
4525 | rtx op1 = XEXP (operands[1], 1); | |
c5c76735 | 4526 | |
bb592806 | 4527 | mips_emit_compare (&code, &op0, &op1, true); |
f90b7a5a | 4528 | cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); |
bb592806 | 4529 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
65239d20 | 4530 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond, |
c5c76735 | 4531 | operands[2], operands[3]))); |
b8eb88d0 | 4532 | } |
a0b6cdee | 4533 | |
f90b7a5a | 4534 | /* Perform the comparison in COMPARISON, then trap if the condition holds. */ |
a0b6cdee GM |
4535 | |
4536 | void | |
f90b7a5a | 4537 | mips_expand_conditional_trap (rtx comparison) |
a0b6cdee GM |
4538 | { |
4539 | rtx op0, op1; | |
65239d20 | 4540 | enum machine_mode mode; |
f90b7a5a | 4541 | enum rtx_code code; |
a0b6cdee | 4542 | |
65239d20 RS |
4543 | /* MIPS conditional trap instructions don't have GT or LE flavors, |
4544 | so we must swap the operands and convert to LT and GE respectively. */ | |
f90b7a5a | 4545 | code = GET_CODE (comparison); |
65239d20 | 4546 | switch (code) |
a0b6cdee | 4547 | { |
65239d20 RS |
4548 | case GT: |
4549 | case LE: | |
4550 | case GTU: | |
4551 | case LEU: | |
4552 | code = swap_condition (code); | |
f90b7a5a PB |
4553 | op0 = XEXP (comparison, 1); |
4554 | op1 = XEXP (comparison, 0); | |
65239d20 RS |
4555 | break; |
4556 | ||
4557 | default: | |
f90b7a5a PB |
4558 | op0 = XEXP (comparison, 0); |
4559 | op1 = XEXP (comparison, 1); | |
65239d20 | 4560 | break; |
a0b6cdee | 4561 | } |
65239d20 | 4562 | |
f90b7a5a | 4563 | mode = GET_MODE (XEXP (comparison, 0)); |
886ce862 RS |
4564 | op0 = force_reg (mode, op0); |
4565 | if (!arith_operand (op1, mode)) | |
a0b6cdee GM |
4566 | op1 = force_reg (mode, op1); |
4567 | ||
4568 | emit_insn (gen_rtx_TRAP_IF (VOIDmode, | |
65239d20 RS |
4569 | gen_rtx_fmt_ee (code, mode, op0, op1), |
4570 | const0_rtx)); | |
a0b6cdee | 4571 | } |
cee98a59 | 4572 | \f |
65239d20 | 4573 | /* Initialize *CUM for a call to a function of type FNTYPE. */ |
ab77a036 RS |
4574 | |
4575 | void | |
65239d20 | 4576 | mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype) |
9a6dfb47 | 4577 | { |
65239d20 RS |
4578 | memset (cum, 0, sizeof (*cum)); |
4579 | cum->prototype = (fntype && prototype_p (fntype)); | |
4580 | cum->gp_reg_found = (cum->prototype && stdarg_p (fntype)); | |
9a6dfb47 RS |
4581 | } |
4582 | ||
ab77a036 RS |
4583 | /* Fill INFO with information about a single argument. CUM is the |
4584 | cumulative state for earlier arguments. MODE is the mode of this | |
4585 | argument and TYPE is its type (if known). NAMED is true if this | |
4586 | is a named (fixed) argument rather than a variable one. */ | |
4587 | ||
4588 | static void | |
65239d20 | 4589 | mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum, |
c8717ea3 | 4590 | enum machine_mode mode, const_tree type, bool named) |
08e7ceb3 | 4591 | { |
ab77a036 RS |
4592 | bool doubleword_aligned_p; |
4593 | unsigned int num_bytes, num_words, max_regs; | |
08e7ceb3 | 4594 | |
ab77a036 RS |
4595 | /* Work out the size of the argument. */ |
4596 | num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
4597 | num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
b85aed9e | 4598 | |
ab77a036 RS |
4599 | /* Decide whether it should go in a floating-point register, assuming |
4600 | one is free. Later code checks for availability. | |
b85aed9e | 4601 | |
ab77a036 RS |
4602 | The checks against UNITS_PER_FPVALUE handle the soft-float and |
4603 | single-float cases. */ | |
4604 | switch (mips_abi) | |
e8b7a137 | 4605 | { |
ab77a036 RS |
4606 | case ABI_EABI: |
4607 | /* The EABI conventions have traditionally been defined in terms | |
4608 | of TYPE_MODE, regardless of the actual type. */ | |
4609 | info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4610 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4611 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); | |
4612 | break; | |
b85aed9e | 4613 | |
ab77a036 RS |
4614 | case ABI_32: |
4615 | case ABI_O64: | |
4616 | /* Only leading floating-point scalars are passed in | |
4617 | floating-point registers. We also handle vector floats the same | |
4618 | say, which is OK because they are not covered by the standard ABI. */ | |
4619 | info->fpr_p = (!cum->gp_reg_found | |
4620 | && cum->arg_number < 2 | |
65239d20 RS |
4621 | && (type == 0 |
4622 | || SCALAR_FLOAT_TYPE_P (type) | |
ab77a036 RS |
4623 | || VECTOR_FLOAT_TYPE_P (type)) |
4624 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4625 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4626 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); | |
4627 | break; | |
cafe096b | 4628 | |
ab77a036 RS |
4629 | case ABI_N32: |
4630 | case ABI_64: | |
65239d20 RS |
4631 | /* Scalar, complex and vector floating-point types are passed in |
4632 | floating-point registers, as long as this is a named rather | |
4633 | than a variable argument. */ | |
ab77a036 RS |
4634 | info->fpr_p = (named |
4635 | && (type == 0 || FLOAT_TYPE_P (type)) | |
4636 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4637 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4638 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4639 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); | |
3c53850d | 4640 | |
ab77a036 RS |
4641 | /* ??? According to the ABI documentation, the real and imaginary |
4642 | parts of complex floats should be passed in individual registers. | |
4643 | The real and imaginary parts of stack arguments are supposed | |
4644 | to be contiguous and there should be an extra word of padding | |
4645 | at the end. | |
cafe096b | 4646 | |
ab77a036 RS |
4647 | This has two problems. First, it makes it impossible to use a |
4648 | single "void *" va_list type, since register and stack arguments | |
4649 | are passed differently. (At the time of writing, MIPSpro cannot | |
4650 | handle complex float varargs correctly.) Second, it's unclear | |
4651 | what should happen when there is only one register free. | |
3c53850d | 4652 | |
ab77a036 RS |
4653 | For now, we assume that named complex floats should go into FPRs |
4654 | if there are two FPRs free, otherwise they should be passed in the | |
4655 | same way as a struct containing two floats. */ | |
4656 | if (info->fpr_p | |
4657 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4658 | && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) | |
4659 | { | |
4660 | if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) | |
4661 | info->fpr_p = false; | |
4662 | else | |
4663 | num_words = 2; | |
4664 | } | |
4665 | break; | |
cafe096b | 4666 | |
ab77a036 RS |
4667 | default: |
4668 | gcc_unreachable (); | |
cafe096b | 4669 | } |
3c53850d | 4670 | |
ab77a036 | 4671 | /* See whether the argument has doubleword alignment. */ |
c2ed6cf8 NF |
4672 | doubleword_aligned_p = (mips_function_arg_boundary (mode, type) |
4673 | > BITS_PER_WORD); | |
3c53850d | 4674 | |
ab77a036 RS |
4675 | /* Set REG_OFFSET to the register count we're interested in. |
4676 | The EABI allocates the floating-point registers separately, | |
4677 | but the other ABIs allocate them like integer registers. */ | |
4678 | info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p | |
4679 | ? cum->num_fprs | |
4680 | : cum->num_gprs); | |
cafe096b | 4681 | |
ab77a036 RS |
4682 | /* Advance to an even register if the argument is doubleword-aligned. */ |
4683 | if (doubleword_aligned_p) | |
4684 | info->reg_offset += info->reg_offset & 1; | |
cafe096b | 4685 | |
ab77a036 RS |
4686 | /* Work out the offset of a stack argument. */ |
4687 | info->stack_offset = cum->stack_words; | |
4688 | if (doubleword_aligned_p) | |
4689 | info->stack_offset += info->stack_offset & 1; | |
cafe096b | 4690 | |
ab77a036 | 4691 | max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; |
f9e4a411 | 4692 | |
ab77a036 RS |
4693 | /* Partition the argument between registers and stack. */ |
4694 | info->reg_words = MIN (num_words, max_regs); | |
4695 | info->stack_words = num_words - info->reg_words; | |
4696 | } | |
f9e4a411 | 4697 | |
65239d20 RS |
4698 | /* INFO describes a register argument that has the normal format for the |
4699 | argument's mode. Return the register it uses, assuming that FPRs are | |
4700 | available if HARD_FLOAT_P. */ | |
1ec3b87b | 4701 | |
ab77a036 RS |
4702 | static unsigned int |
4703 | mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p) | |
4704 | { | |
4705 | if (!info->fpr_p || !hard_float_p) | |
4706 | return GP_ARG_FIRST + info->reg_offset; | |
4707 | else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0) | |
4708 | /* In o32, the second argument is always passed in $f14 | |
4709 | for TARGET_DOUBLE_FLOAT, regardless of whether the | |
4710 | first argument was a word or doubleword. */ | |
4711 | return FP_ARG_FIRST + 2; | |
4712 | else | |
4713 | return FP_ARG_FIRST + info->reg_offset; | |
cafe096b | 4714 | } |
d12b8c85 | 4715 | |
65239d20 RS |
4716 | /* Implement TARGET_STRICT_ARGUMENT_NAMING. */ |
4717 | ||
ab77a036 | 4718 | static bool |
d5cc9181 | 4719 | mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) |
ab77a036 RS |
4720 | { |
4721 | return !TARGET_OLDABI; | |
4722 | } | |
d12b8c85 | 4723 | |
c8717ea3 | 4724 | /* Implement TARGET_FUNCTION_ARG. */ |
d12b8c85 | 4725 | |
c8717ea3 | 4726 | static rtx |
d5cc9181 | 4727 | mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
c8717ea3 | 4728 | const_tree type, bool named) |
d12b8c85 | 4729 | { |
d5cc9181 | 4730 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
ab77a036 | 4731 | struct mips_arg_info info; |
d12b8c85 | 4732 | |
ab77a036 | 4733 | /* We will be called with a mode of VOIDmode after the last argument |
65239d20 RS |
4734 | has been seen. Whatever we return will be passed to the call expander. |
4735 | If we need a MIPS16 fp_code, return a REG with the code stored as | |
4736 | the mode. */ | |
ab77a036 RS |
4737 | if (mode == VOIDmode) |
4738 | { | |
4739 | if (TARGET_MIPS16 && cum->fp_code != 0) | |
4740 | return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0); | |
ab77a036 | 4741 | else |
65239d20 | 4742 | return NULL; |
ab77a036 | 4743 | } |
d12b8c85 | 4744 | |
65239d20 | 4745 | mips_get_arg_info (&info, cum, mode, type, named); |
b2471838 | 4746 | |
ab77a036 RS |
4747 | /* Return straight away if the whole argument is passed on the stack. */ |
4748 | if (info.reg_offset == MAX_ARGS_IN_REGISTERS) | |
65239d20 | 4749 | return NULL; |
b2471838 | 4750 | |
65239d20 RS |
4751 | /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure |
4752 | contains a double in its entirety, then that 64-bit chunk is passed | |
4753 | in a floating-point register. */ | |
4754 | if (TARGET_NEWABI | |
4755 | && TARGET_HARD_FLOAT | |
4756 | && named | |
4757 | && type != 0 | |
ab77a036 | 4758 | && TREE_CODE (type) == RECORD_TYPE |
ab77a036 | 4759 | && TYPE_SIZE_UNIT (type) |
65239d20 | 4760 | && host_integerp (TYPE_SIZE_UNIT (type), 1)) |
ab77a036 | 4761 | { |
ab77a036 | 4762 | tree field; |
b2471838 | 4763 | |
ab77a036 | 4764 | /* First check to see if there is any such field. */ |
910ad8de | 4765 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
ab77a036 | 4766 | if (TREE_CODE (field) == FIELD_DECL |
65239d20 | 4767 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
4768 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD |
4769 | && host_integerp (bit_position (field), 0) | |
4770 | && int_bit_position (field) % BITS_PER_WORD == 0) | |
4771 | break; | |
cee98a59 | 4772 | |
ab77a036 RS |
4773 | if (field != 0) |
4774 | { | |
4775 | /* Now handle the special case by returning a PARALLEL | |
4776 | indicating where each 64-bit chunk goes. INFO.REG_WORDS | |
4777 | chunks are passed in registers. */ | |
4778 | unsigned int i; | |
4779 | HOST_WIDE_INT bitpos; | |
4780 | rtx ret; | |
730cf822 | 4781 | |
ab77a036 RS |
4782 | /* assign_parms checks the mode of ENTRY_PARM, so we must |
4783 | use the actual mode here. */ | |
4784 | ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); | |
cee98a59 | 4785 | |
ab77a036 RS |
4786 | bitpos = 0; |
4787 | field = TYPE_FIELDS (type); | |
4788 | for (i = 0; i < info.reg_words; i++) | |
4789 | { | |
4790 | rtx reg; | |
cee98a59 | 4791 | |
910ad8de | 4792 | for (; field; field = DECL_CHAIN (field)) |
ab77a036 RS |
4793 | if (TREE_CODE (field) == FIELD_DECL |
4794 | && int_bit_position (field) >= bitpos) | |
4795 | break; | |
cee98a59 | 4796 | |
ab77a036 RS |
4797 | if (field |
4798 | && int_bit_position (field) == bitpos | |
65239d20 | 4799 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
4800 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) |
4801 | reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); | |
4802 | else | |
4803 | reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); | |
4804 | ||
4805 | XVECEXP (ret, 0, i) | |
4806 | = gen_rtx_EXPR_LIST (VOIDmode, reg, | |
4807 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4808 | ||
4809 | bitpos += BITS_PER_WORD; | |
4810 | } | |
4811 | return ret; | |
4812 | } | |
4813 | } | |
4814 | ||
4815 | /* Handle the n32/n64 conventions for passing complex floating-point | |
4816 | arguments in FPR pairs. The real part goes in the lower register | |
4817 | and the imaginary part goes in the upper register. */ | |
4818 | if (TARGET_NEWABI | |
4819 | && info.fpr_p | |
4820 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
cee98a59 | 4821 | { |
ab77a036 RS |
4822 | rtx real, imag; |
4823 | enum machine_mode inner; | |
65239d20 | 4824 | unsigned int regno; |
ab77a036 RS |
4825 | |
4826 | inner = GET_MODE_INNER (mode); | |
65239d20 | 4827 | regno = FP_ARG_FIRST + info.reg_offset; |
ab77a036 RS |
4828 | if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) |
4829 | { | |
4830 | /* Real part in registers, imaginary part on stack. */ | |
4831 | gcc_assert (info.stack_words == info.reg_words); | |
65239d20 | 4832 | return gen_rtx_REG (inner, regno); |
ab77a036 | 4833 | } |
e0ec4c3b RS |
4834 | else |
4835 | { | |
ab77a036 RS |
4836 | gcc_assert (info.stack_words == 0); |
4837 | real = gen_rtx_EXPR_LIST (VOIDmode, | |
65239d20 | 4838 | gen_rtx_REG (inner, regno), |
ab77a036 RS |
4839 | const0_rtx); |
4840 | imag = gen_rtx_EXPR_LIST (VOIDmode, | |
4841 | gen_rtx_REG (inner, | |
65239d20 | 4842 | regno + info.reg_words / 2), |
ab77a036 RS |
4843 | GEN_INT (GET_MODE_SIZE (inner))); |
4844 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); | |
e0ec4c3b | 4845 | } |
730cf822 | 4846 | } |
f5963e61 | 4847 | |
ab77a036 | 4848 | return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); |
cee98a59 | 4849 | } |
cee98a59 | 4850 | |
c8717ea3 | 4851 | /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ |
cee98a59 | 4852 | |
c8717ea3 | 4853 | static void |
d5cc9181 | 4854 | mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
c8717ea3 | 4855 | const_tree type, bool named) |
842eb20e | 4856 | { |
d5cc9181 | 4857 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
ab77a036 | 4858 | struct mips_arg_info info; |
842eb20e | 4859 | |
65239d20 | 4860 | mips_get_arg_info (&info, cum, mode, type, named); |
842eb20e | 4861 | |
ab77a036 RS |
4862 | if (!info.fpr_p) |
4863 | cum->gp_reg_found = true; | |
910628b8 | 4864 | |
65239d20 RS |
4865 | /* See the comment above the CUMULATIVE_ARGS structure in mips.h for |
4866 | an explanation of what this code does. It assumes that we're using | |
4867 | either the o32 or the o64 ABI, both of which pass at most 2 arguments | |
4868 | in FPRs. */ | |
ab77a036 RS |
4869 | if (cum->arg_number < 2 && info.fpr_p) |
4870 | cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2); | |
910628b8 | 4871 | |
65239d20 RS |
4872 | /* Advance the register count. This has the effect of setting |
4873 | num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned | |
4874 | argument required us to skip the final GPR and pass the whole | |
4875 | argument on the stack. */ | |
ab77a036 RS |
4876 | if (mips_abi != ABI_EABI || !info.fpr_p) |
4877 | cum->num_gprs = info.reg_offset + info.reg_words; | |
4878 | else if (info.reg_words > 0) | |
4879 | cum->num_fprs += MAX_FPRS_PER_FMT; | |
910628b8 | 4880 | |
65239d20 | 4881 | /* Advance the stack word count. */ |
ab77a036 RS |
4882 | if (info.stack_words > 0) |
4883 | cum->stack_words = info.stack_offset + info.stack_words; | |
842eb20e | 4884 | |
ab77a036 RS |
4885 | cum->arg_number++; |
4886 | } | |
842eb20e | 4887 | |
ab77a036 | 4888 | /* Implement TARGET_ARG_PARTIAL_BYTES. */ |
842eb20e | 4889 | |
ab77a036 | 4890 | static int |
d5cc9181 | 4891 | mips_arg_partial_bytes (cumulative_args_t cum, |
ab77a036 RS |
4892 | enum machine_mode mode, tree type, bool named) |
4893 | { | |
4894 | struct mips_arg_info info; | |
f5963e61 | 4895 | |
d5cc9181 | 4896 | mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named); |
ab77a036 RS |
4897 | return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; |
4898 | } | |
147255d8 | 4899 | |
c2ed6cf8 NF |
4900 | /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at |
4901 | least PARM_BOUNDARY bits of alignment, but will be given anything up | |
ab77a036 | 4902 | to STACK_BOUNDARY bits if the type requires it. */ |
f5963e61 | 4903 | |
c2ed6cf8 | 4904 | static unsigned int |
c8717ea3 | 4905 | mips_function_arg_boundary (enum machine_mode mode, const_tree type) |
ab77a036 RS |
4906 | { |
4907 | unsigned int alignment; | |
4908 | ||
4909 | alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
4910 | if (alignment < PARM_BOUNDARY) | |
4911 | alignment = PARM_BOUNDARY; | |
4912 | if (alignment > STACK_BOUNDARY) | |
4913 | alignment = STACK_BOUNDARY; | |
4914 | return alignment; | |
730cf822 | 4915 | } |
df770e04 | 4916 | |
ab77a036 RS |
4917 | /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return |
4918 | upward rather than downward. In other words, return true if the | |
4919 | first byte of the stack slot has useful data, false if the last | |
4920 | byte does. */ | |
df770e04 | 4921 | |
ab77a036 RS |
4922 | bool |
4923 | mips_pad_arg_upward (enum machine_mode mode, const_tree type) | |
df770e04 | 4924 | { |
ab77a036 RS |
4925 | /* On little-endian targets, the first byte of every stack argument |
4926 | is passed in the first byte of the stack slot. */ | |
4927 | if (!BYTES_BIG_ENDIAN) | |
4928 | return true; | |
df770e04 | 4929 | |
ab77a036 RS |
4930 | /* Otherwise, integral types are padded downward: the last byte of a |
4931 | stack argument is passed in the last byte of the stack slot. */ | |
4932 | if (type != 0 | |
4933 | ? (INTEGRAL_TYPE_P (type) | |
4934 | || POINTER_TYPE_P (type) | |
4935 | || FIXED_POINT_TYPE_P (type)) | |
65239d20 | 4936 | : (SCALAR_INT_MODE_P (mode) |
ab77a036 RS |
4937 | || ALL_SCALAR_FIXED_POINT_MODE_P (mode))) |
4938 | return false; | |
df770e04 | 4939 | |
ab77a036 RS |
4940 | /* Big-endian o64 pads floating-point arguments downward. */ |
4941 | if (mips_abi == ABI_O64) | |
4942 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4943 | return false; | |
df770e04 | 4944 | |
ab77a036 RS |
4945 | /* Other types are padded upward for o32, o64, n32 and n64. */ |
4946 | if (mips_abi != ABI_EABI) | |
4947 | return true; | |
df770e04 | 4948 | |
ab77a036 RS |
4949 | /* Arguments smaller than a stack slot are padded downward. */ |
4950 | if (mode != BLKmode) | |
65239d20 | 4951 | return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY; |
ab77a036 | 4952 | else |
65239d20 | 4953 | return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT); |
ab77a036 | 4954 | } |
df770e04 | 4955 | |
ab77a036 RS |
4956 | /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN |
4957 | if the least significant byte of the register has useful data. Return | |
4958 | the opposite if the most significant byte does. */ | |
0cebb05d | 4959 | |
730cf822 | 4960 | bool |
ab77a036 | 4961 | mips_pad_reg_upward (enum machine_mode mode, tree type) |
730cf822 | 4962 | { |
ab77a036 RS |
4963 | /* No shifting is required for floating-point arguments. */ |
4964 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4965 | return !BYTES_BIG_ENDIAN; | |
4966 | ||
4967 | /* Otherwise, apply the same padding to register arguments as we do | |
4968 | to stack arguments. */ | |
4969 | return mips_pad_arg_upward (mode, type); | |
842eb20e | 4970 | } |
cee98a59 | 4971 | |
ab77a036 | 4972 | /* Return nonzero when an argument must be passed by reference. */ |
cee98a59 | 4973 | |
ab77a036 | 4974 | static bool |
d5cc9181 | 4975 | mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ab77a036 RS |
4976 | enum machine_mode mode, const_tree type, |
4977 | bool named ATTRIBUTE_UNUSED) | |
4978 | { | |
4979 | if (mips_abi == ABI_EABI) | |
4980 | { | |
4981 | int size; | |
cee98a59 | 4982 | |
ab77a036 RS |
4983 | /* ??? How should SCmode be handled? */ |
4984 | if (mode == DImode || mode == DFmode | |
4985 | || mode == DQmode || mode == UDQmode | |
4986 | || mode == DAmode || mode == UDAmode) | |
4987 | return 0; | |
cee98a59 | 4988 | |
ab77a036 RS |
4989 | size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); |
4990 | return size == -1 || size > UNITS_PER_WORD; | |
4991 | } | |
4992 | else | |
cee98a59 | 4993 | { |
ab77a036 RS |
4994 | /* If we have a variable-sized parameter, we have no choice. */ |
4995 | return targetm.calls.must_pass_in_stack (mode, type); | |
cee98a59 | 4996 | } |
cee98a59 MM |
4997 | } |
4998 | ||
65239d20 RS |
4999 | /* Implement TARGET_CALLEE_COPIES. */ |
5000 | ||
ab77a036 | 5001 | static bool |
d5cc9181 | 5002 | mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ab77a036 RS |
5003 | enum machine_mode mode ATTRIBUTE_UNUSED, |
5004 | const_tree type ATTRIBUTE_UNUSED, bool named) | |
5005 | { | |
5006 | return mips_abi == ABI_EABI && named; | |
5007 | } | |
5008 | \f | |
5009 | /* See whether VALTYPE is a record whose fields should be returned in | |
5010 | floating-point registers. If so, return the number of fields and | |
5011 | list them in FIELDS (which should have two elements). Return 0 | |
5012 | otherwise. | |
b4966b1b | 5013 | |
ab77a036 RS |
5014 | For n32 & n64, a structure with one or two fields is returned in |
5015 | floating-point registers as long as every field has a floating-point | |
5016 | type. */ | |
b4966b1b | 5017 | |
ab77a036 RS |
5018 | static int |
5019 | mips_fpr_return_fields (const_tree valtype, tree *fields) | |
4d72536e | 5020 | { |
ab77a036 RS |
5021 | tree field; |
5022 | int i; | |
4d72536e | 5023 | |
ab77a036 RS |
5024 | if (!TARGET_NEWABI) |
5025 | return 0; | |
4d72536e | 5026 | |
ab77a036 RS |
5027 | if (TREE_CODE (valtype) != RECORD_TYPE) |
5028 | return 0; | |
4d72536e | 5029 | |
ab77a036 | 5030 | i = 0; |
910ad8de | 5031 | for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field)) |
ae043003 | 5032 | { |
ab77a036 RS |
5033 | if (TREE_CODE (field) != FIELD_DECL) |
5034 | continue; | |
ae043003 | 5035 | |
a3d97724 | 5036 | if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) |
ab77a036 | 5037 | return 0; |
ae043003 | 5038 | |
ab77a036 RS |
5039 | if (i == 2) |
5040 | return 0; | |
ae043003 | 5041 | |
ab77a036 RS |
5042 | fields[i++] = field; |
5043 | } | |
5044 | return i; | |
5045 | } | |
ae043003 | 5046 | |
ab77a036 RS |
5047 | /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return |
5048 | a value in the most significant part of $2/$3 if: | |
ae043003 | 5049 | |
ab77a036 | 5050 | - the target is big-endian; |
ae043003 | 5051 | |
ab77a036 RS |
5052 | - the value has a structure or union type (we generalize this to |
5053 | cover aggregates from other languages too); and | |
4d72536e | 5054 | |
ab77a036 | 5055 | - the structure is not returned in floating-point registers. */ |
4d72536e | 5056 | |
ab77a036 RS |
5057 | static bool |
5058 | mips_return_in_msb (const_tree valtype) | |
5059 | { | |
5060 | tree fields[2]; | |
4d72536e | 5061 | |
ab77a036 RS |
5062 | return (TARGET_NEWABI |
5063 | && TARGET_BIG_ENDIAN | |
5064 | && AGGREGATE_TYPE_P (valtype) | |
5065 | && mips_fpr_return_fields (valtype, fields) == 0); | |
4d72536e RS |
5066 | } |
5067 | ||
ab77a036 RS |
5068 | /* Return true if the function return value MODE will get returned in a |
5069 | floating-point register. */ | |
a38e0142 | 5070 | |
ab77a036 RS |
5071 | static bool |
5072 | mips_return_mode_in_fpr_p (enum machine_mode mode) | |
a38e0142 | 5073 | { |
ab77a036 RS |
5074 | return ((GET_MODE_CLASS (mode) == MODE_FLOAT |
5075 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT | |
5076 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5077 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); | |
a38e0142 SL |
5078 | } |
5079 | ||
fd0d4c1f RS |
5080 | /* Return the representation of an FPR return register when the |
5081 | value being returned in FP_RETURN has mode VALUE_MODE and the | |
5082 | return type itself has mode TYPE_MODE. On NewABI targets, | |
5083 | the two modes may be different for structures like: | |
5084 | ||
5085 | struct __attribute__((packed)) foo { float f; } | |
5086 | ||
5087 | where we return the SFmode value of "f" in FP_RETURN, but where | |
5088 | the structure itself has mode BLKmode. */ | |
5089 | ||
5090 | static rtx | |
5091 | mips_return_fpr_single (enum machine_mode type_mode, | |
5092 | enum machine_mode value_mode) | |
5093 | { | |
5094 | rtx x; | |
5095 | ||
5096 | x = gen_rtx_REG (value_mode, FP_RETURN); | |
5097 | if (type_mode != value_mode) | |
5098 | { | |
5099 | x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); | |
5100 | x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); | |
5101 | } | |
5102 | return x; | |
5103 | } | |
5104 | ||
ab77a036 RS |
5105 | /* Return a composite value in a pair of floating-point registers. |
5106 | MODE1 and OFFSET1 are the mode and byte offset for the first value, | |
5107 | likewise MODE2 and OFFSET2 for the second. MODE is the mode of the | |
5108 | complete value. | |
cee98a59 | 5109 | |
ab77a036 RS |
5110 | For n32 & n64, $f0 always holds the first value and $f2 the second. |
5111 | Otherwise the values are packed together as closely as possible. */ | |
cee98a59 | 5112 | |
ab77a036 RS |
5113 | static rtx |
5114 | mips_return_fpr_pair (enum machine_mode mode, | |
5115 | enum machine_mode mode1, HOST_WIDE_INT offset1, | |
5116 | enum machine_mode mode2, HOST_WIDE_INT offset2) | |
5117 | { | |
5118 | int inc; | |
cee98a59 | 5119 | |
ab77a036 RS |
5120 | inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT); |
5121 | return gen_rtx_PARALLEL | |
5122 | (mode, | |
5123 | gen_rtvec (2, | |
5124 | gen_rtx_EXPR_LIST (VOIDmode, | |
5125 | gen_rtx_REG (mode1, FP_RETURN), | |
5126 | GEN_INT (offset1)), | |
5127 | gen_rtx_EXPR_LIST (VOIDmode, | |
5128 | gen_rtx_REG (mode2, FP_RETURN + inc), | |
5129 | GEN_INT (offset2)))); | |
cee98a59 | 5130 | |
cee98a59 MM |
5131 | } |
5132 | ||
47be3d6d AS |
5133 | /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE. |
5134 | For normal calls, VALTYPE is the return type and MODE is VOIDmode. | |
5135 | For libcalls, VALTYPE is null and MODE is the mode of the return value. */ | |
cee98a59 | 5136 | |
47be3d6d AS |
5137 | static rtx |
5138 | mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type, | |
5139 | enum machine_mode mode) | |
ab77a036 RS |
5140 | { |
5141 | if (valtype) | |
cee98a59 | 5142 | { |
ab77a036 | 5143 | tree fields[2]; |
65239d20 | 5144 | int unsigned_p; |
47be3d6d AS |
5145 | const_tree func; |
5146 | ||
5147 | if (fn_decl_or_type && DECL_P (fn_decl_or_type)) | |
5148 | func = fn_decl_or_type; | |
5149 | else | |
5150 | func = NULL; | |
cee98a59 | 5151 | |
ab77a036 | 5152 | mode = TYPE_MODE (valtype); |
65239d20 | 5153 | unsigned_p = TYPE_UNSIGNED (valtype); |
4d72536e | 5154 | |
cde0f3fd PB |
5155 | /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, |
5156 | return values, promote the mode here too. */ | |
5157 | mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); | |
0e5a4ad8 | 5158 | |
ab77a036 RS |
5159 | /* Handle structures whose fields are returned in $f0/$f2. */ |
5160 | switch (mips_fpr_return_fields (valtype, fields)) | |
a20b7b05 | 5161 | { |
ab77a036 | 5162 | case 1: |
fd0d4c1f RS |
5163 | return mips_return_fpr_single (mode, |
5164 | TYPE_MODE (TREE_TYPE (fields[0]))); | |
4d72536e | 5165 | |
ab77a036 RS |
5166 | case 2: |
5167 | return mips_return_fpr_pair (mode, | |
5168 | TYPE_MODE (TREE_TYPE (fields[0])), | |
5169 | int_byte_position (fields[0]), | |
5170 | TYPE_MODE (TREE_TYPE (fields[1])), | |
5171 | int_byte_position (fields[1])); | |
5172 | } | |
4d72536e | 5173 | |
ab77a036 RS |
5174 | /* If a value is passed in the most significant part of a register, see |
5175 | whether we have to round the mode up to a whole number of words. */ | |
5176 | if (mips_return_in_msb (valtype)) | |
5177 | { | |
5178 | HOST_WIDE_INT size = int_size_in_bytes (valtype); | |
5179 | if (size % UNITS_PER_WORD != 0) | |
a20b7b05 | 5180 | { |
ab77a036 RS |
5181 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; |
5182 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4d72536e | 5183 | } |
3f1f8d8c | 5184 | } |
ab77a036 RS |
5185 | |
5186 | /* For EABI, the class of return register depends entirely on MODE. | |
5187 | For example, "struct { some_type x; }" and "union { some_type x; }" | |
5188 | are returned in the same way as a bare "some_type" would be. | |
5189 | Other ABIs only use FPRs for scalar, complex or vector types. */ | |
5190 | if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype)) | |
5191 | return gen_rtx_REG (mode, GP_RETURN); | |
3f1f8d8c MM |
5192 | } |
5193 | ||
ab77a036 | 5194 | if (!TARGET_MIPS16) |
ae043003 | 5195 | { |
ab77a036 RS |
5196 | /* Handle long doubles for n32 & n64. */ |
5197 | if (mode == TFmode) | |
5198 | return mips_return_fpr_pair (mode, | |
5199 | DImode, 0, | |
5200 | DImode, GET_MODE_SIZE (mode) / 2); | |
ae043003 | 5201 | |
ab77a036 | 5202 | if (mips_return_mode_in_fpr_p (mode)) |
0882b52e | 5203 | { |
ab77a036 RS |
5204 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
5205 | return mips_return_fpr_pair (mode, | |
5206 | GET_MODE_INNER (mode), 0, | |
5207 | GET_MODE_INNER (mode), | |
5208 | GET_MODE_SIZE (mode) / 2); | |
5209 | else | |
5210 | return gen_rtx_REG (mode, FP_RETURN); | |
0882b52e | 5211 | } |
ae043003 RS |
5212 | } |
5213 | ||
ab77a036 | 5214 | return gen_rtx_REG (mode, GP_RETURN); |
cee98a59 MM |
5215 | } |
5216 | ||
47be3d6d AS |
5217 | /* Implement TARGET_FUNCTION_VALUE. */ |
5218 | ||
5219 | static rtx | |
5220 | mips_function_value (const_tree valtype, const_tree fn_decl_or_type, | |
5221 | bool outgoing ATTRIBUTE_UNUSED) | |
5222 | { | |
5223 | return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode); | |
5224 | } | |
5225 | ||
5226 | /* Implement TARGET_LIBCALL_VALUE. */ | |
5227 | ||
5228 | static rtx | |
5229 | mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) | |
5230 | { | |
5231 | return mips_function_value_1 (NULL_TREE, NULL_TREE, mode); | |
5232 | } | |
5233 | ||
5234 | /* Implement TARGET_FUNCTION_VALUE_REGNO_P. | |
5235 | ||
5236 | On the MIPS, R2 R3 and F0 F2 are the only register thus used. | |
5237 | Currently, R2 and F0 are only implemented here (C has no complex type). */ | |
5238 | ||
5239 | static bool | |
5240 | mips_function_value_regno_p (const unsigned int regno) | |
5241 | { | |
5242 | if (regno == GP_RETURN | |
5243 | || regno == FP_RETURN | |
5244 | || (LONG_DOUBLE_TYPE_SIZE == 128 | |
5245 | && FP_RETURN != GP_RETURN | |
5246 | && regno == FP_RETURN + 2)) | |
5247 | return true; | |
5248 | ||
5249 | return false; | |
5250 | } | |
5251 | ||
65239d20 RS |
5252 | /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs, |
5253 | all BLKmode objects are returned in memory. Under the n32, n64 | |
5254 | and embedded ABIs, small structures are returned in a register. | |
ab77a036 RS |
5255 | Objects with varying size must still be returned in memory, of |
5256 | course. */ | |
b4966b1b | 5257 | |
ab77a036 RS |
5258 | static bool |
5259 | mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) | |
648bb159 | 5260 | { |
65239d20 RS |
5261 | return (TARGET_OLDABI |
5262 | ? TYPE_MODE (type) == BLKmode | |
5263 | : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD)); | |
648bb159 | 5264 | } |
4d72536e | 5265 | \f |
65239d20 RS |
5266 | /* Implement TARGET_SETUP_INCOMING_VARARGS. */ |
5267 | ||
0c8da560 | 5268 | static void |
d5cc9181 | 5269 | mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode, |
4001cd89 RS |
5270 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5271 | int no_rtl) | |
4d72536e RS |
5272 | { |
5273 | CUMULATIVE_ARGS local_cum; | |
5274 | int gp_saved, fp_saved; | |
cee98a59 | 5275 | |
4d72536e RS |
5276 | /* The caller has advanced CUM up to, but not beyond, the last named |
5277 | argument. Advance a local copy of CUM past the last "real" named | |
6c535c69 | 5278 | argument, to find out how many registers are left over. */ |
d5cc9181 JR |
5279 | local_cum = *get_cumulative_args (cum); |
5280 | mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, | |
5281 | true); | |
4d72536e RS |
5282 | |
5283 | /* Found out how many registers we need to save. */ | |
bb63e5a0 | 5284 | gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; |
4d72536e | 5285 | fp_saved = (EABI_FLOAT_VARARGS_P |
bb63e5a0 | 5286 | ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs |
4d72536e | 5287 | : 0); |
cee98a59 | 5288 | |
4d72536e | 5289 | if (!no_rtl) |
cee98a59 | 5290 | { |
4d72536e RS |
5291 | if (gp_saved > 0) |
5292 | { | |
5293 | rtx ptr, mem; | |
5294 | ||
4001cd89 RS |
5295 | ptr = plus_constant (virtual_incoming_args_rtx, |
5296 | REG_PARM_STACK_SPACE (cfun->decl) | |
5297 | - gp_saved * UNITS_PER_WORD); | |
8d0e1e43 | 5298 | mem = gen_frame_mem (BLKmode, ptr); |
520d96c6 | 5299 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
4d72536e | 5300 | |
520d96c6 RS |
5301 | move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, |
5302 | mem, gp_saved); | |
4d72536e RS |
5303 | } |
5304 | if (fp_saved > 0) | |
5305 | { | |
5306 | /* We can't use move_block_from_reg, because it will use | |
031a26c5 | 5307 | the wrong mode. */ |
4d72536e RS |
5308 | enum machine_mode mode; |
5309 | int off, i; | |
cee98a59 | 5310 | |
4d72536e | 5311 | /* Set OFF to the offset from virtual_incoming_args_rtx of |
71cc389b | 5312 | the first float register. The FP save area lies below |
4d72536e | 5313 | the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */ |
65239d20 | 5314 | off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE; |
4d72536e | 5315 | off -= fp_saved * UNITS_PER_FPREG; |
cee98a59 | 5316 | |
4d72536e RS |
5317 | mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; |
5318 | ||
e8ab09c1 SL |
5319 | for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; |
5320 | i += MAX_FPRS_PER_FMT) | |
4d72536e | 5321 | { |
520d96c6 RS |
5322 | rtx ptr, mem; |
5323 | ||
5324 | ptr = plus_constant (virtual_incoming_args_rtx, off); | |
8d0e1e43 | 5325 | mem = gen_frame_mem (mode, ptr); |
520d96c6 | 5326 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
51e7252a | 5327 | mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i)); |
8a381273 | 5328 | off += UNITS_PER_HWFPVALUE; |
4d72536e RS |
5329 | } |
5330 | } | |
5331 | } | |
4001cd89 RS |
5332 | if (REG_PARM_STACK_SPACE (cfun->decl) == 0) |
5333 | cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD | |
5334 | + fp_saved * UNITS_PER_FPREG); | |
cee98a59 | 5335 | } |
4d72536e | 5336 | |
65239d20 | 5337 | /* Implement TARGET_BUILTIN_VA_LIST. */ |
4fe12442 | 5338 | |
c35d187f RH |
5339 | static tree |
5340 | mips_build_builtin_va_list (void) | |
5d3f2bd5 | 5341 | { |
4d72536e | 5342 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5343 | { |
65239d20 RS |
5344 | /* We keep 3 pointers, and two offsets. |
5345 | ||
5346 | Two pointers are to the overflow area, which starts at the CFA. | |
5347 | One of these is constant, for addressing into the GPR save area | |
5348 | below it. The other is advanced up the stack through the | |
5349 | overflow region. | |
5350 | ||
5351 | The third pointer is to the bottom of the GPR save area. | |
5352 | Since the FPR save area is just below it, we can address | |
5353 | FPR slots off this pointer. | |
5354 | ||
5355 | We also keep two one-byte offsets, which are to be subtracted | |
5356 | from the constant pointers to yield addresses in the GPR and | |
5357 | FPR save areas. These are downcounted as float or non-float | |
5358 | arguments are used, and when they get to zero, the argument | |
5359 | must be obtained from the overflow region. */ | |
7a0ec607 CD |
5360 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record; |
5361 | tree array, index; | |
5d3f2bd5 | 5362 | |
65239d20 | 5363 | record = lang_hooks.types.make_type (RECORD_TYPE); |
5d3f2bd5 | 5364 | |
4c4bde29 AH |
5365 | f_ovfl = build_decl (BUILTINS_LOCATION, |
5366 | FIELD_DECL, get_identifier ("__overflow_argptr"), | |
65239d20 | 5367 | ptr_type_node); |
4c4bde29 AH |
5368 | f_gtop = build_decl (BUILTINS_LOCATION, |
5369 | FIELD_DECL, get_identifier ("__gpr_top"), | |
65239d20 | 5370 | ptr_type_node); |
4c4bde29 AH |
5371 | f_ftop = build_decl (BUILTINS_LOCATION, |
5372 | FIELD_DECL, get_identifier ("__fpr_top"), | |
65239d20 | 5373 | ptr_type_node); |
4c4bde29 AH |
5374 | f_goff = build_decl (BUILTINS_LOCATION, |
5375 | FIELD_DECL, get_identifier ("__gpr_offset"), | |
65239d20 | 5376 | unsigned_char_type_node); |
4c4bde29 AH |
5377 | f_foff = build_decl (BUILTINS_LOCATION, |
5378 | FIELD_DECL, get_identifier ("__fpr_offset"), | |
65239d20 | 5379 | unsigned_char_type_node); |
7a0ec607 CD |
5380 | /* Explicitly pad to the size of a pointer, so that -Wpadded won't |
5381 | warn on every user file. */ | |
7d60be94 | 5382 | index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1); |
7a0ec607 CD |
5383 | array = build_array_type (unsigned_char_type_node, |
5384 | build_index_type (index)); | |
4c4bde29 AH |
5385 | f_res = build_decl (BUILTINS_LOCATION, |
5386 | FIELD_DECL, get_identifier ("__reserved"), array); | |
5d3f2bd5 | 5387 | |
4fe12442 DL |
5388 | DECL_FIELD_CONTEXT (f_ovfl) = record; |
5389 | DECL_FIELD_CONTEXT (f_gtop) = record; | |
5390 | DECL_FIELD_CONTEXT (f_ftop) = record; | |
5391 | DECL_FIELD_CONTEXT (f_goff) = record; | |
5392 | DECL_FIELD_CONTEXT (f_foff) = record; | |
7a0ec607 | 5393 | DECL_FIELD_CONTEXT (f_res) = record; |
5d3f2bd5 | 5394 | |
4fe12442 | 5395 | TYPE_FIELDS (record) = f_ovfl; |
910ad8de NF |
5396 | DECL_CHAIN (f_ovfl) = f_gtop; |
5397 | DECL_CHAIN (f_gtop) = f_ftop; | |
5398 | DECL_CHAIN (f_ftop) = f_goff; | |
5399 | DECL_CHAIN (f_goff) = f_foff; | |
5400 | DECL_CHAIN (f_foff) = f_res; | |
5d3f2bd5 | 5401 | |
4fe12442 | 5402 | layout_type (record); |
5d3f2bd5 RH |
5403 | return record; |
5404 | } | |
9aaa1ee8 | 5405 | else if (TARGET_IRIX6) |
4f1cad00 RH |
5406 | /* On IRIX 6, this type is 'char *'. */ |
5407 | return build_pointer_type (char_type_node); | |
5d3f2bd5 | 5408 | else |
4f1cad00 RH |
5409 | /* Otherwise, we use 'void *'. */ |
5410 | return ptr_type_node; | |
5d3f2bd5 RH |
5411 | } |
5412 | ||
d7bd8aeb | 5413 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ |
5d3f2bd5 | 5414 | |
d7bd8aeb | 5415 | static void |
b4966b1b | 5416 | mips_va_start (tree valist, rtx nextarg) |
5d3f2bd5 | 5417 | { |
4001cd89 | 5418 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5419 | { |
4001cd89 RS |
5420 | const CUMULATIVE_ARGS *cum; |
5421 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; | |
5422 | tree ovfl, gtop, ftop, goff, foff; | |
5423 | tree t; | |
4fe12442 | 5424 | int gpr_save_area_size; |
4001cd89 RS |
5425 | int fpr_save_area_size; |
5426 | int fpr_offset; | |
4fe12442 | 5427 | |
38173d38 | 5428 | cum = &crtl->args.info; |
4d72536e | 5429 | gpr_save_area_size |
bb63e5a0 | 5430 | = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD; |
4001cd89 RS |
5431 | fpr_save_area_size |
5432 | = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG; | |
4d72536e | 5433 | |
4001cd89 | 5434 | f_ovfl = TYPE_FIELDS (va_list_type_node); |
910ad8de NF |
5435 | f_gtop = DECL_CHAIN (f_ovfl); |
5436 | f_ftop = DECL_CHAIN (f_gtop); | |
5437 | f_goff = DECL_CHAIN (f_ftop); | |
5438 | f_foff = DECL_CHAIN (f_goff); | |
4001cd89 | 5439 | |
47a25a46 RG |
5440 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5441 | NULL_TREE); | |
5442 | gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, | |
5443 | NULL_TREE); | |
5444 | ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, | |
5445 | NULL_TREE); | |
5446 | goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, | |
5447 | NULL_TREE); | |
5448 | foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, | |
5449 | NULL_TREE); | |
4001cd89 RS |
5450 | |
5451 | /* Emit code to initialize OVFL, which points to the next varargs | |
5452 | stack argument. CUM->STACK_WORDS gives the number of stack | |
5453 | words used by named arguments. */ | |
5454 | t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); | |
5455 | if (cum->stack_words > 0) | |
5d49b6a7 | 5456 | t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD); |
726a989a | 5457 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); |
4001cd89 RS |
5458 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5459 | ||
5460 | /* Emit code to initialize GTOP, the top of the GPR save area. */ | |
5461 | t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); | |
726a989a | 5462 | t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); |
4001cd89 RS |
5463 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5464 | ||
5465 | /* Emit code to initialize FTOP, the top of the FPR save area. | |
5466 | This address is gpr_save_area_bytes below GTOP, rounded | |
5467 | down to the next fp-aligned boundary. */ | |
5468 | t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); | |
5469 | fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1; | |
65239d20 | 5470 | fpr_offset &= -UNITS_PER_FPVALUE; |
4001cd89 | 5471 | if (fpr_offset) |
5d49b6a7 | 5472 | t = fold_build_pointer_plus_hwi (t, -fpr_offset); |
726a989a | 5473 | t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t); |
4001cd89 RS |
5474 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5475 | ||
5476 | /* Emit code to initialize GOFF, the offset from GTOP of the | |
5477 | next GPR argument. */ | |
726a989a | 5478 | t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff, |
e0681eaa | 5479 | build_int_cst (TREE_TYPE (goff), gpr_save_area_size)); |
4001cd89 RS |
5480 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5481 | ||
5482 | /* Likewise emit code to initialize FOFF, the offset from FTOP | |
5483 | of the next FPR argument. */ | |
726a989a | 5484 | t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff, |
e0681eaa | 5485 | build_int_cst (TREE_TYPE (foff), fpr_save_area_size)); |
4001cd89 | 5486 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5d3f2bd5 RH |
5487 | } |
5488 | else | |
4001cd89 RS |
5489 | { |
5490 | nextarg = plus_constant (nextarg, -cfun->machine->varargs_size); | |
5491 | std_expand_builtin_va_start (valist, nextarg); | |
5492 | } | |
5d3f2bd5 | 5493 | } |
65239d20 RS |
5494 | |
5495 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ | |
5d3f2bd5 | 5496 | |
0310e537 | 5497 | static tree |
726a989a RB |
5498 | mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
5499 | gimple_seq *post_p) | |
5d3f2bd5 | 5500 | { |
0310e537 | 5501 | tree addr; |
65239d20 | 5502 | bool indirect_p; |
0310e537 | 5503 | |
65239d20 RS |
5504 | indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
5505 | if (indirect_p) | |
0310e537 | 5506 | type = build_pointer_type (type); |
5d3f2bd5 | 5507 | |
65239d20 | 5508 | if (!EABI_FLOAT_VARARGS_P) |
0310e537 RH |
5509 | addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
5510 | else | |
5d3f2bd5 | 5511 | { |
0310e537 RH |
5512 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; |
5513 | tree ovfl, top, off, align; | |
65239d20 | 5514 | HOST_WIDE_INT size, rsize, osize; |
0310e537 RH |
5515 | tree t, u; |
5516 | ||
5517 | f_ovfl = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
5518 | f_gtop = DECL_CHAIN (f_ovfl); |
5519 | f_ftop = DECL_CHAIN (f_gtop); | |
5520 | f_goff = DECL_CHAIN (f_ftop); | |
5521 | f_foff = DECL_CHAIN (f_goff); | |
0310e537 | 5522 | |
65239d20 | 5523 | /* Let: |
0310e537 | 5524 | |
65239d20 | 5525 | TOP be the top of the GPR or FPR save area; |
0310e537 RH |
5526 | OFF be the offset from TOP of the next register; |
5527 | ADDR_RTX be the address of the argument; | |
65239d20 | 5528 | SIZE be the number of bytes in the argument type; |
0310e537 | 5529 | RSIZE be the number of bytes used to store the argument |
65239d20 | 5530 | when it's in the register save area; and |
0310e537 | 5531 | OSIZE be the number of bytes used to store it when it's |
65239d20 | 5532 | in the stack overflow area. |
0310e537 RH |
5533 | |
5534 | The code we want is: | |
5535 | ||
5536 | 1: off &= -rsize; // round down | |
5537 | 2: if (off != 0) | |
5538 | 3: { | |
65239d20 RS |
5539 | 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0); |
5540 | 5: off -= rsize; | |
0310e537 RH |
5541 | 6: } |
5542 | 7: else | |
5543 | 8: { | |
65239d20 RS |
5544 | 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize; |
5545 | 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0); | |
5546 | 11: ovfl += osize; | |
5547 | 14: } | |
0310e537 RH |
5548 | |
5549 | [1] and [9] can sometimes be optimized away. */ | |
5550 | ||
47a25a46 RG |
5551 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5552 | NULL_TREE); | |
65239d20 | 5553 | size = int_size_in_bytes (type); |
0310e537 RH |
5554 | |
5555 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT | |
5556 | && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE) | |
5d3f2bd5 | 5557 | { |
6d8d5435 RS |
5558 | top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), |
5559 | unshare_expr (valist), f_ftop, NULL_TREE); | |
5560 | off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), | |
5561 | unshare_expr (valist), f_foff, NULL_TREE); | |
0310e537 | 5562 | |
65239d20 RS |
5563 | /* When va_start saves FPR arguments to the stack, each slot |
5564 | takes up UNITS_PER_HWFPVALUE bytes, regardless of the | |
5565 | argument's precision. */ | |
0310e537 RH |
5566 | rsize = UNITS_PER_HWFPVALUE; |
5567 | ||
5568 | /* Overflow arguments are padded to UNITS_PER_WORD bytes | |
5569 | (= PARM_BOUNDARY bits). This can be different from RSIZE | |
5570 | in two cases: | |
5571 | ||
5572 | (1) On 32-bit targets when TYPE is a structure such as: | |
5573 | ||
5574 | struct s { float f; }; | |
5575 | ||
5576 | Such structures are passed in paired FPRs, so RSIZE | |
5577 | will be 8 bytes. However, the structure only takes | |
5578 | up 4 bytes of memory, so OSIZE will only be 4. | |
5579 | ||
5580 | (2) In combinations such as -mgp64 -msingle-float | |
65239d20 RS |
5581 | -fshort-double. Doubles passed in registers will then take |
5582 | up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the | |
5583 | stack take up UNITS_PER_WORD bytes. */ | |
0310e537 | 5584 | osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD); |
5d3f2bd5 | 5585 | } |
4d72536e RS |
5586 | else |
5587 | { | |
6d8d5435 RS |
5588 | top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), |
5589 | unshare_expr (valist), f_gtop, NULL_TREE); | |
5590 | off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), | |
5591 | unshare_expr (valist), f_goff, NULL_TREE); | |
65239d20 | 5592 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; |
0310e537 | 5593 | if (rsize > UNITS_PER_WORD) |
4fe12442 | 5594 | { |
0310e537 | 5595 | /* [1] Emit code for: off &= -rsize. */ |
6d8d5435 | 5596 | t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off), |
3179cf8c | 5597 | build_int_cst (TREE_TYPE (off), -rsize)); |
6d8d5435 | 5598 | gimplify_assign (unshare_expr (off), t, pre_p); |
4d72536e | 5599 | } |
0310e537 RH |
5600 | osize = rsize; |
5601 | } | |
a85cd407 | 5602 | |
0310e537 | 5603 | /* [2] Emit code to branch if off == 0. */ |
47a25a46 RG |
5604 | t = build2 (NE_EXPR, boolean_type_node, off, |
5605 | build_int_cst (TREE_TYPE (off), 0)); | |
5606 | addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); | |
0310e537 RH |
5607 | |
5608 | /* [5] Emit code for: off -= rsize. We do this as a form of | |
65239d20 | 5609 | post-decrement not available to C. */ |
7d60be94 | 5610 | t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize)); |
47a25a46 | 5611 | t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t); |
65239d20 RS |
5612 | |
5613 | /* [4] Emit code for: | |
5614 | addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */ | |
0310e537 | 5615 | t = fold_convert (sizetype, t); |
5be014d5 | 5616 | t = fold_build1 (NEGATE_EXPR, sizetype, t); |
5d49b6a7 | 5617 | t = fold_build_pointer_plus (top, t); |
0310e537 | 5618 | if (BYTES_BIG_ENDIAN && rsize > size) |
5d49b6a7 | 5619 | t = fold_build_pointer_plus_hwi (t, rsize - size); |
0310e537 | 5620 | COND_EXPR_THEN (addr) = t; |
a85cd407 | 5621 | |
0310e537 RH |
5622 | if (osize > UNITS_PER_WORD) |
5623 | { | |
65239d20 | 5624 | /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */ |
5d49b6a7 RG |
5625 | t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1); |
5626 | u = build_int_cst (TREE_TYPE (t), -osize); | |
5be014d5 | 5627 | t = build2 (BIT_AND_EXPR, sizetype, t, u); |
6d8d5435 RS |
5628 | align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), |
5629 | unshare_expr (ovfl), t); | |
4d72536e | 5630 | } |
0310e537 RH |
5631 | else |
5632 | align = NULL; | |
5633 | ||
65239d20 RS |
5634 | /* [10, 11] Emit code for: |
5635 | addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0) | |
5636 | ovfl += osize. */ | |
5637 | u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize)); | |
47a25a46 | 5638 | t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u); |
0310e537 | 5639 | if (BYTES_BIG_ENDIAN && osize > size) |
5d49b6a7 | 5640 | t = fold_build_pointer_plus_hwi (t, osize - size); |
5d3f2bd5 | 5641 | |
65239d20 | 5642 | /* String [9] and [10, 11] together. */ |
0310e537 | 5643 | if (align) |
47a25a46 | 5644 | t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t); |
0310e537 | 5645 | COND_EXPR_ELSE (addr) = t; |
5d3f2bd5 | 5646 | |
0310e537 | 5647 | addr = fold_convert (build_pointer_type (type), addr); |
d6e9821f | 5648 | addr = build_va_arg_indirect_ref (addr); |
0310e537 | 5649 | } |
e72ed4a7 | 5650 | |
65239d20 | 5651 | if (indirect_p) |
d6e9821f | 5652 | addr = build_va_arg_indirect_ref (addr); |
5d3f2bd5 | 5653 | |
0310e537 | 5654 | return addr; |
5d3f2bd5 RH |
5655 | } |
5656 | \f | |
b2b61607 RS |
5657 | /* Start a definition of function NAME. MIPS16_P indicates whether the |
5658 | function contains MIPS16 code. */ | |
5659 | ||
5660 | static void | |
5661 | mips_start_function_definition (const char *name, bool mips16_p) | |
5662 | { | |
5663 | if (mips16_p) | |
5664 | fprintf (asm_out_file, "\t.set\tmips16\n"); | |
5665 | else | |
5666 | fprintf (asm_out_file, "\t.set\tnomips16\n"); | |
5667 | ||
5668 | if (!flag_inhibit_size_directive) | |
5669 | { | |
5670 | fputs ("\t.ent\t", asm_out_file); | |
5671 | assemble_name (asm_out_file, name); | |
5672 | fputs ("\n", asm_out_file); | |
5673 | } | |
5674 | ||
5675 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function"); | |
5676 | ||
5677 | /* Start the definition proper. */ | |
5678 | assemble_name (asm_out_file, name); | |
5679 | fputs (":\n", asm_out_file); | |
5680 | } | |
5681 | ||
5682 | /* End a function definition started by mips_start_function_definition. */ | |
5683 | ||
5684 | static void | |
5685 | mips_end_function_definition (const char *name) | |
5686 | { | |
5687 | if (!flag_inhibit_size_directive) | |
5688 | { | |
5689 | fputs ("\t.end\t", asm_out_file); | |
5690 | assemble_name (asm_out_file, name); | |
5691 | fputs ("\n", asm_out_file); | |
5692 | } | |
5693 | } | |
5694 | \f | |
7462a715 RS |
5695 | /* Return true if calls to X can use R_MIPS_CALL* relocations. */ |
5696 | ||
5697 | static bool | |
5698 | mips_ok_for_lazy_binding_p (rtx x) | |
5699 | { | |
5700 | return (TARGET_USE_GOT | |
5701 | && GET_CODE (x) == SYMBOL_REF | |
08d0963a | 5702 | && !SYMBOL_REF_BIND_NOW_P (x) |
7462a715 RS |
5703 | && !mips_symbol_binds_local_p (x)); |
5704 | } | |
5705 | ||
08d0963a RS |
5706 | /* Load function address ADDR into register DEST. TYPE is as for |
5707 | mips_expand_call. Return true if we used an explicit lazy-binding | |
5708 | sequence. */ | |
7462a715 RS |
5709 | |
5710 | static bool | |
08d0963a | 5711 | mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr) |
7462a715 RS |
5712 | { |
5713 | /* If we're generating PIC, and this call is to a global function, | |
5714 | try to allow its address to be resolved lazily. This isn't | |
5715 | possible for sibcalls when $gp is call-saved because the value | |
5716 | of $gp on entry to the stub would be our caller's gp, not ours. */ | |
5717 | if (TARGET_EXPLICIT_RELOCS | |
08d0963a | 5718 | && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP) |
7462a715 RS |
5719 | && mips_ok_for_lazy_binding_p (addr)) |
5720 | { | |
08d0963a RS |
5721 | addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL); |
5722 | emit_insn (gen_rtx_SET (VOIDmode, dest, addr)); | |
7462a715 RS |
5723 | return true; |
5724 | } | |
5725 | else | |
5726 | { | |
5727 | mips_emit_move (dest, addr); | |
5728 | return false; | |
5729 | } | |
5730 | } | |
5731 | \f | |
08d0963a RS |
5732 | /* Each locally-defined hard-float MIPS16 function has a local symbol |
5733 | associated with it. This hash table maps the function symbol (FUNC) | |
5734 | to the local symbol (LOCAL). */ | |
d1b38208 | 5735 | struct GTY(()) mips16_local_alias { |
08d0963a RS |
5736 | rtx func; |
5737 | rtx local; | |
5738 | }; | |
5739 | static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases; | |
5740 | ||
5741 | /* Hash table callbacks for mips16_local_aliases. */ | |
5742 | ||
5743 | static hashval_t | |
5744 | mips16_local_aliases_hash (const void *entry) | |
5745 | { | |
5746 | const struct mips16_local_alias *alias; | |
5747 | ||
5748 | alias = (const struct mips16_local_alias *) entry; | |
5749 | return htab_hash_string (XSTR (alias->func, 0)); | |
5750 | } | |
5751 | ||
5752 | static int | |
5753 | mips16_local_aliases_eq (const void *entry1, const void *entry2) | |
5754 | { | |
5755 | const struct mips16_local_alias *alias1, *alias2; | |
5756 | ||
5757 | alias1 = (const struct mips16_local_alias *) entry1; | |
5758 | alias2 = (const struct mips16_local_alias *) entry2; | |
5759 | return rtx_equal_p (alias1->func, alias2->func); | |
5760 | } | |
5761 | ||
5762 | /* FUNC is the symbol for a locally-defined hard-float MIPS16 function. | |
5763 | Return a local alias for it, creating a new one if necessary. */ | |
5764 | ||
5765 | static rtx | |
5766 | mips16_local_alias (rtx func) | |
5767 | { | |
5768 | struct mips16_local_alias *alias, tmp_alias; | |
5769 | void **slot; | |
5770 | ||
5771 | /* Create the hash table if this is the first call. */ | |
5772 | if (mips16_local_aliases == NULL) | |
5773 | mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash, | |
5774 | mips16_local_aliases_eq, NULL); | |
5775 | ||
5776 | /* Look up the function symbol, creating a new entry if need be. */ | |
5777 | tmp_alias.func = func; | |
5778 | slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT); | |
5779 | gcc_assert (slot != NULL); | |
5780 | ||
5781 | alias = (struct mips16_local_alias *) *slot; | |
5782 | if (alias == NULL) | |
5783 | { | |
5784 | const char *func_name, *local_name; | |
5785 | rtx local; | |
5786 | ||
5787 | /* Create a new SYMBOL_REF for the local symbol. The choice of | |
5788 | __fn_local_* is based on the __fn_stub_* names that we've | |
5789 | traditionally used for the non-MIPS16 stub. */ | |
5790 | func_name = targetm.strip_name_encoding (XSTR (func, 0)); | |
5791 | local_name = ACONCAT (("__fn_local_", func_name, NULL)); | |
5792 | local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name)); | |
5793 | SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL; | |
5794 | ||
5795 | /* Create a new structure to represent the mapping. */ | |
a9429e29 | 5796 | alias = ggc_alloc_mips16_local_alias (); |
08d0963a RS |
5797 | alias->func = func; |
5798 | alias->local = local; | |
5799 | *slot = alias; | |
5800 | } | |
5801 | return alias->local; | |
5802 | } | |
5803 | \f | |
65239d20 RS |
5804 | /* A chained list of functions for which mips16_build_call_stub has already |
5805 | generated a stub. NAME is the name of the function and FP_RET_P is true | |
5806 | if the function returns a value in floating-point registers. */ | |
5807 | struct mips16_stub { | |
ab77a036 RS |
5808 | struct mips16_stub *next; |
5809 | char *name; | |
65239d20 | 5810 | bool fp_ret_p; |
ab77a036 | 5811 | }; |
ab77a036 | 5812 | static struct mips16_stub *mips16_stubs; |
b4966b1b | 5813 | |
08d0963a RS |
5814 | /* Return a SYMBOL_REF for a MIPS16 function called NAME. */ |
5815 | ||
5816 | static rtx | |
5817 | mips16_stub_function (const char *name) | |
5818 | { | |
5819 | rtx x; | |
5820 | ||
5821 | x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
5822 | SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION); | |
5823 | return x; | |
5824 | } | |
5825 | ||
65239d20 RS |
5826 | /* Return the two-character string that identifies floating-point |
5827 | return mode MODE in the name of a MIPS16 function stub. */ | |
b4966b1b | 5828 | |
ab77a036 RS |
5829 | static const char * |
5830 | mips16_call_stub_mode_suffix (enum machine_mode mode) | |
5831 | { | |
5832 | if (mode == SFmode) | |
5833 | return "sf"; | |
5834 | else if (mode == DFmode) | |
5835 | return "df"; | |
5836 | else if (mode == SCmode) | |
5837 | return "sc"; | |
5838 | else if (mode == DCmode) | |
5839 | return "dc"; | |
5840 | else if (mode == V2SFmode) | |
5841 | return "df"; | |
5842 | else | |
5843 | gcc_unreachable (); | |
5844 | } | |
b4966b1b | 5845 | |
5b372d33 RS |
5846 | /* Write instructions to move a 32-bit value between general register |
5847 | GPREG and floating-point register FPREG. DIRECTION is 't' to move | |
5848 | from GPREG to FPREG and 'f' to move in the opposite direction. */ | |
5849 | ||
5850 | static void | |
5851 | mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
5852 | { | |
5853 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5854 | reg_names[gpreg], reg_names[fpreg]); | |
5855 | } | |
5856 | ||
5857 | /* Likewise for 64-bit values. */ | |
5858 | ||
5859 | static void | |
5860 | mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
5861 | { | |
5862 | if (TARGET_64BIT) | |
5863 | fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction, | |
5864 | reg_names[gpreg], reg_names[fpreg]); | |
5865 | else if (TARGET_FLOAT64) | |
5866 | { | |
5867 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5868 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
5869 | fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction, | |
5870 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]); | |
5871 | } | |
5872 | else | |
5873 | { | |
5874 | /* Move the least-significant word. */ | |
5875 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5876 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
5877 | /* ...then the most significant word. */ | |
5878 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5879 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]); | |
5880 | } | |
5881 | } | |
5882 | ||
5883 | /* Write out code to move floating-point arguments into or out of | |
23fdf75c | 5884 | general registers. FP_CODE is the code describing which arguments |
5b372d33 RS |
5885 | are present (see the comment above the definition of CUMULATIVE_ARGS |
5886 | in mips.h). DIRECTION is as for mips_output_32bit_xfer. */ | |
b4966b1b | 5887 | |
ab77a036 | 5888 | static void |
5b372d33 | 5889 | mips_output_args_xfer (int fp_code, char direction) |
ab77a036 | 5890 | { |
5b372d33 | 5891 | unsigned int gparg, fparg, f; |
ab77a036 | 5892 | CUMULATIVE_ARGS cum; |
b4966b1b | 5893 | |
65239d20 | 5894 | /* This code only works for o32 and o64. */ |
ab77a036 | 5895 | gcc_assert (TARGET_OLDABI); |
b4966b1b | 5896 | |
65239d20 | 5897 | mips_init_cumulative_args (&cum, NULL); |
b4966b1b | 5898 | |
ab77a036 RS |
5899 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
5900 | { | |
5901 | enum machine_mode mode; | |
5902 | struct mips_arg_info info; | |
b4966b1b | 5903 | |
ab77a036 RS |
5904 | if ((f & 3) == 1) |
5905 | mode = SFmode; | |
5906 | else if ((f & 3) == 2) | |
5907 | mode = DFmode; | |
5908 | else | |
5909 | gcc_unreachable (); | |
b4966b1b | 5910 | |
65239d20 | 5911 | mips_get_arg_info (&info, &cum, mode, NULL, true); |
ab77a036 RS |
5912 | gparg = mips_arg_regno (&info, false); |
5913 | fparg = mips_arg_regno (&info, true); | |
b4966b1b | 5914 | |
ab77a036 | 5915 | if (mode == SFmode) |
5b372d33 | 5916 | mips_output_32bit_xfer (direction, gparg, fparg); |
ab77a036 | 5917 | else |
5b372d33 | 5918 | mips_output_64bit_xfer (direction, gparg, fparg); |
b4966b1b | 5919 | |
d5cc9181 | 5920 | mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true); |
b4966b1b | 5921 | } |
b4966b1b RS |
5922 | } |
5923 | ||
65239d20 RS |
5924 | /* Write a MIPS16 stub for the current function. This stub is used |
5925 | for functions which take arguments in the floating-point registers. | |
5926 | It is normal-mode code that moves the floating-point arguments | |
5927 | into the general registers and then jumps to the MIPS16 code. */ | |
b4966b1b | 5928 | |
ab77a036 | 5929 | static void |
65239d20 | 5930 | mips16_build_function_stub (void) |
b4966b1b | 5931 | { |
08d0963a | 5932 | const char *fnname, *alias_name, *separator; |
ab77a036 | 5933 | char *secname, *stubname; |
65239d20 | 5934 | tree stubdecl; |
ab77a036 | 5935 | unsigned int f; |
08d0963a | 5936 | rtx symbol, alias; |
b4966b1b | 5937 | |
65239d20 | 5938 | /* Create the name of the stub, and its unique section. */ |
08d0963a RS |
5939 | symbol = XEXP (DECL_RTL (current_function_decl), 0); |
5940 | alias = mips16_local_alias (symbol); | |
5941 | ||
5942 | fnname = targetm.strip_name_encoding (XSTR (symbol, 0)); | |
5943 | alias_name = targetm.strip_name_encoding (XSTR (alias, 0)); | |
65239d20 RS |
5944 | secname = ACONCAT ((".mips16.fn.", fnname, NULL)); |
5945 | stubname = ACONCAT (("__fn_stub_", fnname, NULL)); | |
5946 | ||
5947 | /* Build a decl for the stub. */ | |
4c4bde29 AH |
5948 | stubdecl = build_decl (BUILTINS_LOCATION, |
5949 | FUNCTION_DECL, get_identifier (stubname), | |
b861891b | 5950 | build_function_type_list (void_type_node, NULL_TREE)); |
ab77a036 | 5951 | DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); |
4c4bde29 AH |
5952 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
5953 | RESULT_DECL, NULL_TREE, void_type_node); | |
b4966b1b | 5954 | |
65239d20 | 5955 | /* Output a comment. */ |
23fdf75c RS |
5956 | fprintf (asm_out_file, "\t# Stub function for %s (", |
5957 | current_function_name ()); | |
65239d20 | 5958 | separator = ""; |
38173d38 | 5959 | for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2) |
b4966b1b | 5960 | { |
65239d20 | 5961 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 5962 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 5963 | separator = ", "; |
b4966b1b | 5964 | } |
23fdf75c | 5965 | fprintf (asm_out_file, ")\n"); |
9226543b | 5966 | |
b2b61607 RS |
5967 | /* Start the function definition. */ |
5968 | assemble_start_function (stubdecl, stubname); | |
5969 | mips_start_function_definition (stubname, false); | |
e689b870 | 5970 | |
e21d5757 DJ |
5971 | /* If generating pic2 code, either set up the global pointer or |
5972 | switch to pic0. */ | |
5973 | if (TARGET_ABICALLS_PIC2) | |
08d0963a | 5974 | { |
e21d5757 DJ |
5975 | if (TARGET_ABSOLUTE_ABICALLS) |
5976 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
5977 | else | |
5978 | { | |
5979 | output_asm_insn ("%(.cpload\t%^%)", NULL); | |
5980 | /* Emit an R_MIPS_NONE relocation to tell the linker what the | |
5981 | target function is. Use a local GOT access when loading the | |
5982 | symbol, to cut down on the number of unnecessary GOT entries | |
5983 | for stubs that aren't needed. */ | |
5984 | output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol); | |
5985 | symbol = alias; | |
5986 | } | |
08d0963a RS |
5987 | } |
5988 | ||
e21d5757 | 5989 | /* Load the address of the MIPS16 function into $25. Do this first so |
6a68a258 RS |
5990 | that targets with coprocessor interlocks can use an MFC1 to fill the |
5991 | delay slot. */ | |
e21d5757 | 5992 | output_asm_insn ("la\t%^,%0", &symbol); |
e689b870 | 5993 | |
65239d20 | 5994 | /* Move the arguments from floating-point registers to general registers. */ |
38173d38 | 5995 | mips_output_args_xfer (crtl->args.info.fp_code, 'f'); |
e689b870 | 5996 | |
65239d20 | 5997 | /* Jump to the MIPS16 function. */ |
e21d5757 | 5998 | output_asm_insn ("jr\t%^", NULL); |
d8934cf1 | 5999 | |
e21d5757 | 6000 | if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS) |
08d0963a RS |
6001 | fprintf (asm_out_file, "\t.option\tpic2\n"); |
6002 | ||
b2b61607 | 6003 | mips_end_function_definition (stubname); |
e689b870 | 6004 | |
08d0963a RS |
6005 | /* If the linker needs to create a dynamic symbol for the target |
6006 | function, it will associate the symbol with the stub (which, | |
6007 | unlike the target function, follows the proper calling conventions). | |
6008 | It is therefore useful to have a local alias for the target function, | |
6009 | so that it can still be identified as MIPS16 code. As an optimization, | |
6010 | this symbol can also be used for indirect MIPS16 references from | |
6011 | within this file. */ | |
6012 | ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname); | |
6013 | ||
ab77a036 | 6014 | switch_to_section (function_section (current_function_decl)); |
e689b870 DU |
6015 | } |
6016 | ||
5f5fe6d9 RS |
6017 | /* The current function is a MIPS16 function that returns a value in an FPR. |
6018 | Copy the return value from its soft-float to its hard-float location. | |
6019 | libgcc2 has special non-MIPS16 helper functions for each case. */ | |
6020 | ||
6021 | static void | |
6022 | mips16_copy_fpr_return_value (void) | |
6023 | { | |
08d0963a RS |
6024 | rtx fn, insn, retval; |
6025 | tree return_type; | |
5f5fe6d9 | 6026 | enum machine_mode return_mode; |
08d0963a | 6027 | const char *name; |
5f5fe6d9 RS |
6028 | |
6029 | return_type = DECL_RESULT (current_function_decl); | |
6030 | return_mode = DECL_MODE (return_type); | |
6031 | ||
08d0963a RS |
6032 | name = ACONCAT (("__mips16_ret_", |
6033 | mips16_call_stub_mode_suffix (return_mode), | |
6034 | NULL)); | |
6035 | fn = mips16_stub_function (name); | |
6036 | ||
6037 | /* The function takes arguments in $2 (and possibly $3), so calls | |
6038 | to it cannot be lazily bound. */ | |
6039 | SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW; | |
6040 | ||
6041 | /* Model the call as something that takes the GPR return value as | |
6042 | argument and returns an "updated" value. */ | |
6043 | retval = gen_rtx_REG (return_mode, GP_RETURN); | |
6044 | insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn, | |
6045 | const0_rtx, NULL_RTX, false); | |
6046 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval); | |
5f5fe6d9 RS |
6047 | } |
6048 | ||
08d0963a | 6049 | /* Consider building a stub for a MIPS16 call to function *FN_PTR. |
65239d20 RS |
6050 | RETVAL is the location of the return value, or null if this is |
6051 | a "call" rather than a "call_value". ARGS_SIZE is the size of the | |
6052 | arguments and FP_CODE is the code built by mips_function_arg; | |
b53da244 | 6053 | see the comment before the fp_code field in CUMULATIVE_ARGS for details. |
d33289b2 | 6054 | |
08d0963a RS |
6055 | There are three alternatives: |
6056 | ||
6057 | - If a stub was needed, emit the call and return the call insn itself. | |
6058 | ||
6059 | - If we can avoid using a stub by redirecting the call, set *FN_PTR | |
6060 | to the new target and return null. | |
6061 | ||
6062 | - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR | |
6063 | unmodified. | |
f9e4a411 | 6064 | |
65239d20 RS |
6065 | A stub is needed for calls to functions that, in normal mode, |
6066 | receive arguments in FPRs or return values in FPRs. The stub | |
6067 | copies the arguments from their soft-float positions to their | |
6068 | hard-float positions, calls the real function, then copies the | |
6069 | return value from its hard-float position to its soft-float | |
6070 | position. | |
f9e4a411 | 6071 | |
08d0963a RS |
6072 | We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub. |
6073 | If *FN_PTR turns out to be to a non-MIPS16 function, the linker | |
6074 | automatically redirects the JAL to the stub, otherwise the JAL | |
6075 | continues to call FN directly. */ | |
65239d20 | 6076 | |
dbc90b65 | 6077 | static rtx |
08d0963a | 6078 | mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code) |
f9e4a411 | 6079 | { |
ab77a036 | 6080 | const char *fnname; |
65239d20 | 6081 | bool fp_ret_p; |
ab77a036 | 6082 | struct mips16_stub *l; |
08d0963a | 6083 | rtx insn, fn; |
f9e4a411 | 6084 | |
65239d20 | 6085 | /* We don't need to do anything if we aren't in MIPS16 mode, or if |
ab77a036 RS |
6086 | we were invoked with the -msoft-float option. */ |
6087 | if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI) | |
dbc90b65 | 6088 | return NULL_RTX; |
f9e4a411 | 6089 | |
65239d20 | 6090 | /* Figure out whether the value might come back in a floating-point |
ab77a036 | 6091 | register. */ |
65239d20 | 6092 | fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval)); |
f9e4a411 | 6093 | |
65239d20 RS |
6094 | /* We don't need to do anything if there were no floating-point |
6095 | arguments and the value will not be returned in a floating-point | |
ab77a036 | 6096 | register. */ |
65239d20 | 6097 | if (fp_code == 0 && !fp_ret_p) |
dbc90b65 | 6098 | return NULL_RTX; |
f9e4a411 | 6099 | |
ab77a036 | 6100 | /* We don't need to do anything if this is a call to a special |
65239d20 | 6101 | MIPS16 support function. */ |
08d0963a RS |
6102 | fn = *fn_ptr; |
6103 | if (mips16_stub_function_p (fn)) | |
dbc90b65 | 6104 | return NULL_RTX; |
f9e4a411 | 6105 | |
ab77a036 RS |
6106 | /* This code will only work for o32 and o64 abis. The other ABI's |
6107 | require more sophisticated support. */ | |
6108 | gcc_assert (TARGET_OLDABI); | |
f9e4a411 | 6109 | |
65239d20 RS |
6110 | /* If we're calling via a function pointer, use one of the magic |
6111 | libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination. | |
6112 | Each stub expects the function address to arrive in register $2. */ | |
08d0963a RS |
6113 | if (GET_CODE (fn) != SYMBOL_REF |
6114 | || !call_insn_operand (fn, VOIDmode)) | |
f9e4a411 | 6115 | { |
ab77a036 | 6116 | char buf[30]; |
08d0963a RS |
6117 | rtx stub_fn, insn, addr; |
6118 | bool lazy_p; | |
6119 | ||
6120 | /* If this is a locally-defined and locally-binding function, | |
6121 | avoid the stub by calling the local alias directly. */ | |
6122 | if (mips16_local_function_p (fn)) | |
6123 | { | |
6124 | *fn_ptr = mips16_local_alias (fn); | |
6125 | return NULL_RTX; | |
6126 | } | |
f9e4a411 | 6127 | |
65239d20 RS |
6128 | /* Create a SYMBOL_REF for the libgcc.a function. */ |
6129 | if (fp_ret_p) | |
ab77a036 RS |
6130 | sprintf (buf, "__mips16_call_stub_%s_%d", |
6131 | mips16_call_stub_mode_suffix (GET_MODE (retval)), | |
6132 | fp_code); | |
f9e4a411 | 6133 | else |
65239d20 | 6134 | sprintf (buf, "__mips16_call_stub_%d", fp_code); |
08d0963a RS |
6135 | stub_fn = mips16_stub_function (buf); |
6136 | ||
6137 | /* The function uses $2 as an argument, so calls to it | |
6138 | cannot be lazily bound. */ | |
6139 | SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW; | |
f9e4a411 | 6140 | |
65239d20 | 6141 | /* Load the target function into $2. */ |
08d0963a RS |
6142 | addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); |
6143 | lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn); | |
f9e4a411 | 6144 | |
65239d20 | 6145 | /* Emit the call. */ |
08d0963a RS |
6146 | insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn, |
6147 | args_size, NULL_RTX, lazy_p); | |
f9e4a411 | 6148 | |
65239d20 | 6149 | /* Tell GCC that this call does indeed use the value of $2. */ |
08d0963a | 6150 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr); |
f9e4a411 | 6151 | |
65239d20 | 6152 | /* If we are handling a floating-point return value, we need to |
ab77a036 RS |
6153 | save $18 in the function prologue. Putting a note on the |
6154 | call will mean that df_regs_ever_live_p ($18) will be true if the | |
6155 | call is not eliminated, and we can check that in the prologue | |
6156 | code. */ | |
65239d20 | 6157 | if (fp_ret_p) |
ab77a036 RS |
6158 | CALL_INSN_FUNCTION_USAGE (insn) = |
6159 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6160 | gen_rtx_CLOBBER (VOIDmode, |
6161 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6162 | CALL_INSN_FUNCTION_USAGE (insn)); |
f9e4a411 | 6163 | |
dbc90b65 | 6164 | return insn; |
ab77a036 | 6165 | } |
f9e4a411 | 6166 | |
ab77a036 RS |
6167 | /* We know the function we are going to call. If we have already |
6168 | built a stub, we don't need to do anything further. */ | |
ab77a036 RS |
6169 | fnname = targetm.strip_name_encoding (XSTR (fn, 0)); |
6170 | for (l = mips16_stubs; l != NULL; l = l->next) | |
6171 | if (strcmp (l->name, fnname) == 0) | |
6172 | break; | |
d33289b2 | 6173 | |
ab77a036 | 6174 | if (l == NULL) |
f9e4a411 | 6175 | { |
65239d20 RS |
6176 | const char *separator; |
6177 | char *secname, *stubname; | |
6178 | tree stubid, stubdecl; | |
6179 | unsigned int f; | |
8d1d0dee | 6180 | |
65239d20 | 6181 | /* If the function does not return in FPRs, the special stub |
ab77a036 | 6182 | section is named |
65239d20 RS |
6183 | .mips16.call.FNNAME |
6184 | ||
6185 | If the function does return in FPRs, the stub section is named | |
ab77a036 | 6186 | .mips16.call.fp.FNNAME |
f9e4a411 | 6187 | |
65239d20 RS |
6188 | Build a decl for the stub. */ |
6189 | secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "", | |
6190 | fnname, NULL)); | |
6191 | stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "", | |
6192 | fnname, NULL)); | |
ab77a036 | 6193 | stubid = get_identifier (stubname); |
4c4bde29 AH |
6194 | stubdecl = build_decl (BUILTINS_LOCATION, |
6195 | FUNCTION_DECL, stubid, | |
b861891b NF |
6196 | build_function_type_list (void_type_node, |
6197 | NULL_TREE)); | |
ab77a036 | 6198 | DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); |
4c4bde29 AH |
6199 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6200 | RESULT_DECL, NULL_TREE, | |
65239d20 | 6201 | void_type_node); |
9a6dfb47 | 6202 | |
65239d20 | 6203 | /* Output a comment. */ |
ab77a036 | 6204 | fprintf (asm_out_file, "\t# Stub function to call %s%s (", |
65239d20 | 6205 | (fp_ret_p |
ab77a036 RS |
6206 | ? (GET_MODE (retval) == SFmode ? "float " : "double ") |
6207 | : ""), | |
6208 | fnname); | |
65239d20 | 6209 | separator = ""; |
ab77a036 RS |
6210 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
6211 | { | |
65239d20 | 6212 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6213 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6214 | separator = ", "; |
ab77a036 RS |
6215 | } |
6216 | fprintf (asm_out_file, ")\n"); | |
f9e4a411 | 6217 | |
b2b61607 | 6218 | /* Start the function definition. */ |
ab77a036 | 6219 | assemble_start_function (stubdecl, stubname); |
b2b61607 | 6220 | mips_start_function_definition (stubname, false); |
8ce4afa3 | 6221 | |
65239d20 | 6222 | if (!fp_ret_p) |
ab77a036 | 6223 | { |
e21d5757 | 6224 | /* Load the address of the MIPS16 function into $25. Do this |
6a68a258 RS |
6225 | first so that targets with coprocessor interlocks can use |
6226 | an MFC1 to fill the delay slot. */ | |
08d0963a RS |
6227 | if (TARGET_EXPLICIT_RELOCS) |
6228 | { | |
6229 | output_asm_insn ("lui\t%^,%%hi(%0)", &fn); | |
6230 | output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn); | |
6231 | } | |
6232 | else | |
6233 | output_asm_insn ("la\t%^,%0", &fn); | |
6a68a258 RS |
6234 | } |
6235 | ||
65239d20 RS |
6236 | /* Move the arguments from general registers to floating-point |
6237 | registers. */ | |
6a68a258 RS |
6238 | mips_output_args_xfer (fp_code, 't'); |
6239 | ||
65239d20 | 6240 | if (!fp_ret_p) |
6a68a258 RS |
6241 | { |
6242 | /* Jump to the previously-loaded address. */ | |
08d0963a | 6243 | output_asm_insn ("jr\t%^", NULL); |
ab77a036 RS |
6244 | } |
6245 | else | |
6246 | { | |
65239d20 RS |
6247 | /* Save the return address in $18 and call the non-MIPS16 function. |
6248 | The stub's caller knows that $18 might be clobbered, even though | |
6249 | $18 is usually a call-saved register. */ | |
ab77a036 | 6250 | fprintf (asm_out_file, "\tmove\t%s,%s\n", |
293593b1 | 6251 | reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]); |
b53da244 | 6252 | output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn); |
65239d20 RS |
6253 | |
6254 | /* Move the result from floating-point registers to | |
6255 | general registers. */ | |
ab77a036 RS |
6256 | switch (GET_MODE (retval)) |
6257 | { | |
6258 | case SCmode: | |
93f63c68 RS |
6259 | mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN, |
6260 | TARGET_BIG_ENDIAN | |
6261 | ? FP_REG_FIRST + MAX_FPRS_PER_FMT | |
6262 | : FP_REG_FIRST); | |
6263 | mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN, | |
6264 | TARGET_LITTLE_ENDIAN | |
6265 | ? FP_REG_FIRST + MAX_FPRS_PER_FMT | |
6266 | : FP_REG_FIRST); | |
ab77a036 RS |
6267 | if (GET_MODE (retval) == SCmode && TARGET_64BIT) |
6268 | { | |
6269 | /* On 64-bit targets, complex floats are returned in | |
6270 | a single GPR, such that "sd" on a suitably-aligned | |
6271 | target would store the value correctly. */ | |
93f63c68 RS |
6272 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", |
6273 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN], | |
6274 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); | |
ab77a036 | 6275 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", |
5b372d33 RS |
6276 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN], |
6277 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]); | |
93f63c68 RS |
6278 | fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n", |
6279 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN], | |
6280 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); | |
ab77a036 | 6281 | fprintf (asm_out_file, "\tor\t%s,%s,%s\n", |
5b372d33 RS |
6282 | reg_names[GP_RETURN], |
6283 | reg_names[GP_RETURN], | |
6284 | reg_names[GP_RETURN + 1]); | |
ab77a036 RS |
6285 | } |
6286 | break; | |
f9e4a411 | 6287 | |
93f63c68 RS |
6288 | case SFmode: |
6289 | mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST); | |
6290 | break; | |
6291 | ||
ab77a036 | 6292 | case DCmode: |
5b372d33 RS |
6293 | mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD), |
6294 | FP_REG_FIRST + MAX_FPRS_PER_FMT); | |
ab77a036 RS |
6295 | /* Fall though. */ |
6296 | case DFmode: | |
6297 | case V2SFmode: | |
5b372d33 | 6298 | mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST); |
ab77a036 | 6299 | break; |
9a6dfb47 | 6300 | |
ab77a036 RS |
6301 | default: |
6302 | gcc_unreachable (); | |
6303 | } | |
65239d20 | 6304 | fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]); |
ab77a036 | 6305 | } |
9a6dfb47 | 6306 | |
ab77a036 RS |
6307 | #ifdef ASM_DECLARE_FUNCTION_SIZE |
6308 | ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); | |
6309 | #endif | |
9a6dfb47 | 6310 | |
b2b61607 | 6311 | mips_end_function_definition (stubname); |
9a6dfb47 | 6312 | |
ab77a036 | 6313 | /* Record this stub. */ |
65239d20 | 6314 | l = XNEW (struct mips16_stub); |
ab77a036 | 6315 | l->name = xstrdup (fnname); |
65239d20 | 6316 | l->fp_ret_p = fp_ret_p; |
ab77a036 RS |
6317 | l->next = mips16_stubs; |
6318 | mips16_stubs = l; | |
6319 | } | |
9a6dfb47 | 6320 | |
65239d20 | 6321 | /* If we expect a floating-point return value, but we've built a |
ab77a036 | 6322 | stub which does not expect one, then we're in trouble. We can't |
65239d20 | 6323 | use the existing stub, because it won't handle the floating-point |
ab77a036 RS |
6324 | value. We can't build a new stub, because the linker won't know |
6325 | which stub to use for the various calls in this object file. | |
6326 | Fortunately, this case is illegal, since it means that a function | |
6327 | was declared in two different ways in a single compilation. */ | |
65239d20 | 6328 | if (fp_ret_p && !l->fp_ret_p) |
ab77a036 | 6329 | error ("cannot handle inconsistent calls to %qs", fnname); |
9a6dfb47 | 6330 | |
ab77a036 | 6331 | if (retval == NULL_RTX) |
65239d20 | 6332 | insn = gen_call_internal_direct (fn, args_size); |
ab77a036 | 6333 | else |
65239d20 | 6334 | insn = gen_call_value_internal_direct (retval, fn, args_size); |
08d0963a | 6335 | insn = mips_emit_call_insn (insn, fn, fn, false); |
9a6dfb47 | 6336 | |
65239d20 RS |
6337 | /* If we are calling a stub which handles a floating-point return |
6338 | value, we need to arrange to save $18 in the prologue. We do this | |
6339 | by marking the function call as using the register. The prologue | |
6340 | will later see that it is used, and emit code to save it. */ | |
6341 | if (fp_ret_p) | |
ab77a036 RS |
6342 | CALL_INSN_FUNCTION_USAGE (insn) = |
6343 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6344 | gen_rtx_CLOBBER (VOIDmode, |
6345 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6346 | CALL_INSN_FUNCTION_USAGE (insn)); |
9a6dfb47 | 6347 | |
dbc90b65 | 6348 | return insn; |
9a6dfb47 | 6349 | } |
ab77a036 | 6350 | \f |
08d0963a RS |
6351 | /* Expand a call of type TYPE. RESULT is where the result will go (null |
6352 | for "call"s and "sibcall"s), ADDR is the address of the function, | |
6353 | ARGS_SIZE is the size of the arguments and AUX is the value passed | |
6354 | to us by mips_function_arg. LAZY_P is true if this call already | |
6355 | involves a lazily-bound function address (such as when calling | |
6356 | functions through a MIPS16 hard-float stub). | |
f9e4a411 | 6357 | |
dbc90b65 RS |
6358 | Return the call itself. */ |
6359 | ||
6360 | rtx | |
08d0963a RS |
6361 | mips_expand_call (enum mips_call_type type, rtx result, rtx addr, |
6362 | rtx args_size, rtx aux, bool lazy_p) | |
f9e4a411 | 6363 | { |
ab77a036 | 6364 | rtx orig_addr, pattern, insn; |
08d0963a | 6365 | int fp_code; |
d522e7a2 | 6366 | |
08d0963a RS |
6367 | fp_code = aux == 0 ? 0 : (int) GET_MODE (aux); |
6368 | insn = mips16_build_call_stub (result, &addr, args_size, fp_code); | |
6369 | if (insn) | |
6370 | { | |
6371 | gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL); | |
6372 | return insn; | |
6373 | } | |
6374 | ; | |
ab77a036 | 6375 | orig_addr = addr; |
ab77a036 | 6376 | if (!call_insn_operand (addr, VOIDmode)) |
d522e7a2 | 6377 | { |
08d0963a RS |
6378 | if (type == MIPS_CALL_EPILOGUE) |
6379 | addr = MIPS_EPILOGUE_TEMP (Pmode); | |
6380 | else | |
6381 | addr = gen_reg_rtx (Pmode); | |
6382 | lazy_p |= mips_load_call_address (type, addr, orig_addr); | |
ab77a036 | 6383 | } |
d522e7a2 | 6384 | |
08d0963a | 6385 | if (result == 0) |
65239d20 | 6386 | { |
08d0963a | 6387 | rtx (*fn) (rtx, rtx); |
d522e7a2 | 6388 | |
0c433c31 | 6389 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6390 | fn = gen_sibcall_internal; |
6391 | else | |
6392 | fn = gen_call_internal; | |
6393 | ||
6394 | pattern = fn (addr, args_size); | |
6395 | } | |
ab77a036 RS |
6396 | else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) |
6397 | { | |
fd0d4c1f | 6398 | /* Handle return values created by mips_return_fpr_pair. */ |
08d0963a | 6399 | rtx (*fn) (rtx, rtx, rtx, rtx); |
ab77a036 | 6400 | rtx reg1, reg2; |
d522e7a2 | 6401 | |
0c433c31 | 6402 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6403 | fn = gen_sibcall_value_multiple_internal; |
6404 | else | |
6405 | fn = gen_call_value_multiple_internal; | |
6406 | ||
ab77a036 RS |
6407 | reg1 = XEXP (XVECEXP (result, 0, 0), 0); |
6408 | reg2 = XEXP (XVECEXP (result, 0, 1), 0); | |
08d0963a | 6409 | pattern = fn (reg1, addr, args_size, reg2); |
ab77a036 RS |
6410 | } |
6411 | else | |
fd0d4c1f | 6412 | { |
08d0963a RS |
6413 | rtx (*fn) (rtx, rtx, rtx); |
6414 | ||
0c433c31 | 6415 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6416 | fn = gen_sibcall_value_internal; |
6417 | else | |
6418 | fn = gen_call_value_internal; | |
6419 | ||
fd0d4c1f RS |
6420 | /* Handle return values created by mips_return_fpr_single. */ |
6421 | if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) | |
6422 | result = XEXP (XVECEXP (result, 0, 0), 0); | |
08d0963a | 6423 | pattern = fn (result, addr, args_size); |
fd0d4c1f | 6424 | } |
d522e7a2 | 6425 | |
08d0963a RS |
6426 | return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p); |
6427 | } | |
6428 | ||
6429 | /* Split call instruction INSN into a $gp-clobbering call and | |
6430 | (where necessary) an instruction to restore $gp from its save slot. | |
6431 | CALL_PATTERN is the pattern of the new call. */ | |
6432 | ||
6433 | void | |
6434 | mips_split_call (rtx insn, rtx call_pattern) | |
6435 | { | |
82220036 | 6436 | emit_call_insn (call_pattern); |
08d0963a RS |
6437 | if (!find_reg_note (insn, REG_NORETURN, 0)) |
6438 | /* Pick a temporary register that is suitable for both MIPS16 and | |
6439 | non-MIPS16 code. $4 and $5 are used for returning complex double | |
6440 | values in soft-float code, so $6 is the first suitable candidate. */ | |
0c433c31 | 6441 | mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2)); |
d522e7a2 | 6442 | } |
a27fb29b | 6443 | |
ab77a036 RS |
6444 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ |
6445 | ||
6446 | static bool | |
6447 | mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) | |
cee98a59 | 6448 | { |
ab77a036 RS |
6449 | if (!TARGET_SIBCALLS) |
6450 | return false; | |
cee98a59 | 6451 | |
e19da24c CF |
6452 | /* Interrupt handlers need special epilogue code and therefore can't |
6453 | use sibcalls. */ | |
6454 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
6455 | return false; | |
6456 | ||
ab77a036 RS |
6457 | /* We can't do a sibcall if the called function is a MIPS16 function |
6458 | because there is no direct "jx" instruction equivalent to "jalx" to | |
9be10a79 RS |
6459 | switch the ISA mode. We only care about cases where the sibling |
6460 | and normal calls would both be direct. */ | |
cf900097 RS |
6461 | if (decl |
6462 | && mips_use_mips16_mode_p (decl) | |
9be10a79 | 6463 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)) |
ab77a036 | 6464 | return false; |
d1138d8e | 6465 | |
0b6e1647 RS |
6466 | /* When -minterlink-mips16 is in effect, assume that non-locally-binding |
6467 | functions could be MIPS16 ones unless an attribute explicitly tells | |
6468 | us otherwise. */ | |
ab77a036 RS |
6469 | if (TARGET_INTERLINK_MIPS16 |
6470 | && decl | |
dd748704 | 6471 | && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl)) |
ab77a036 RS |
6472 | && !mips_nomips16_decl_p (decl) |
6473 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)) | |
6474 | return false; | |
cee98a59 | 6475 | |
ab77a036 RS |
6476 | /* Otherwise OK. */ |
6477 | return true; | |
6478 | } | |
6479 | \f | |
6480 | /* Emit code to move general operand SRC into condition-code | |
65239d20 | 6481 | register DEST given that SCRATCH is a scratch TFmode FPR. |
ab77a036 | 6482 | The sequence is: |
147255d8 | 6483 | |
ab77a036 RS |
6484 | FP1 = SRC |
6485 | FP2 = 0.0f | |
6486 | DEST = FP2 < FP1 | |
5ae590d7 | 6487 | |
65239d20 | 6488 | where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */ |
f5963e61 | 6489 | |
ab77a036 | 6490 | void |
65239d20 | 6491 | mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch) |
ab77a036 RS |
6492 | { |
6493 | rtx fp1, fp2; | |
ade6c319 | 6494 | |
ab77a036 RS |
6495 | /* Change the source to SFmode. */ |
6496 | if (MEM_P (src)) | |
6497 | src = adjust_address (src, SFmode, 0); | |
6498 | else if (REG_P (src) || GET_CODE (src) == SUBREG) | |
6499 | src = gen_rtx_REG (SFmode, true_regnum (src)); | |
1bd9166e | 6500 | |
ab77a036 RS |
6501 | fp1 = gen_rtx_REG (SFmode, REGNO (scratch)); |
6502 | fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT); | |
f1d5187e | 6503 | |
ab77a036 RS |
6504 | mips_emit_move (copy_rtx (fp1), src); |
6505 | mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode)); | |
6506 | emit_insn (gen_slt_sf (dest, fp2, fp1)); | |
6507 | } | |
6508 | \f | |
6509 | /* Emit straight-line code to move LENGTH bytes from SRC to DEST. | |
6510 | Assume that the areas do not overlap. */ | |
7dac2f89 | 6511 | |
ab77a036 RS |
6512 | static void |
6513 | mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) | |
6514 | { | |
6515 | HOST_WIDE_INT offset, delta; | |
6516 | unsigned HOST_WIDE_INT bits; | |
6517 | int i; | |
6518 | enum machine_mode mode; | |
6519 | rtx *regs; | |
6520 | ||
6521 | /* Work out how many bits to move at a time. If both operands have | |
6522 | half-word alignment, it is usually better to move in half words. | |
6523 | For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr | |
6524 | and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr. | |
6525 | Otherwise move word-sized chunks. */ | |
6526 | if (MEM_ALIGN (src) == BITS_PER_WORD / 2 | |
6527 | && MEM_ALIGN (dest) == BITS_PER_WORD / 2) | |
6528 | bits = BITS_PER_WORD / 2; | |
d81ecf52 | 6529 | else |
ab77a036 | 6530 | bits = BITS_PER_WORD; |
c1bd2d66 | 6531 | |
ab77a036 RS |
6532 | mode = mode_for_size (bits, MODE_INT, 0); |
6533 | delta = bits / BITS_PER_UNIT; | |
a05bea76 | 6534 | |
ab77a036 | 6535 | /* Allocate a buffer for the temporary registers. */ |
5ead67f6 | 6536 | regs = XALLOCAVEC (rtx, length / delta); |
ab77a036 RS |
6537 | |
6538 | /* Load as many BITS-sized chunks as possible. Use a normal load if | |
6539 | the source has enough alignment, otherwise use left/right pairs. */ | |
6540 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
cee98a59 | 6541 | { |
ab77a036 RS |
6542 | regs[i] = gen_reg_rtx (mode); |
6543 | if (MEM_ALIGN (src) >= bits) | |
6544 | mips_emit_move (regs[i], adjust_address (src, mode, offset)); | |
7dac2f89 | 6545 | else |
ab77a036 RS |
6546 | { |
6547 | rtx part = adjust_address (src, BLKmode, offset); | |
65239d20 | 6548 | if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0)) |
ab77a036 RS |
6549 | gcc_unreachable (); |
6550 | } | |
a27fb29b | 6551 | } |
cee98a59 | 6552 | |
ab77a036 RS |
6553 | /* Copy the chunks to the destination. */ |
6554 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
6555 | if (MEM_ALIGN (dest) >= bits) | |
6556 | mips_emit_move (adjust_address (dest, mode, offset), regs[i]); | |
6557 | else | |
6558 | { | |
6559 | rtx part = adjust_address (dest, BLKmode, offset); | |
65239d20 | 6560 | if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0)) |
ab77a036 RS |
6561 | gcc_unreachable (); |
6562 | } | |
6563 | ||
6564 | /* Mop up any left-over bytes. */ | |
6565 | if (offset < length) | |
a27fb29b | 6566 | { |
ab77a036 RS |
6567 | src = adjust_address (src, BLKmode, offset); |
6568 | dest = adjust_address (dest, BLKmode, offset); | |
6569 | move_by_pieces (dest, src, length - offset, | |
6570 | MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); | |
cee98a59 | 6571 | } |
ab77a036 | 6572 | } |
f8151871 | 6573 | |
ab77a036 RS |
6574 | /* Helper function for doing a loop-based block operation on memory |
6575 | reference MEM. Each iteration of the loop will operate on LENGTH | |
6576 | bytes of MEM. | |
cee98a59 | 6577 | |
ab77a036 RS |
6578 | Create a new base register for use within the loop and point it to |
6579 | the start of MEM. Create a new memory reference that uses this | |
6580 | register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ | |
33563487 | 6581 | |
ab77a036 RS |
6582 | static void |
6583 | mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, | |
6584 | rtx *loop_reg, rtx *loop_mem) | |
6585 | { | |
6586 | *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); | |
af34e51e | 6587 | |
ab77a036 RS |
6588 | /* Although the new mem does not refer to a known location, |
6589 | it does keep up to LENGTH bytes of alignment. */ | |
6590 | *loop_mem = change_address (mem, BLKmode, *loop_reg); | |
6591 | set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); | |
6592 | } | |
142ee136 | 6593 | |
a1c6b246 RS |
6594 | /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER |
6595 | bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that | |
6596 | the memory regions do not overlap. */ | |
d9870b7e | 6597 | |
ab77a036 | 6598 | static void |
a1c6b246 RS |
6599 | mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, |
6600 | HOST_WIDE_INT bytes_per_iter) | |
ab77a036 | 6601 | { |
f90b7a5a | 6602 | rtx label, src_reg, dest_reg, final_src, test; |
ab77a036 | 6603 | HOST_WIDE_INT leftover; |
8cb6400c | 6604 | |
a1c6b246 | 6605 | leftover = length % bytes_per_iter; |
ab77a036 | 6606 | length -= leftover; |
dc884a86 | 6607 | |
ab77a036 | 6608 | /* Create registers and memory references for use within the loop. */ |
a1c6b246 RS |
6609 | mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); |
6610 | mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); | |
cfa31150 | 6611 | |
ab77a036 RS |
6612 | /* Calculate the value that SRC_REG should have after the last iteration |
6613 | of the loop. */ | |
6614 | final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), | |
6615 | 0, 0, OPTAB_WIDEN); | |
6616 | ||
6617 | /* Emit the start of the loop. */ | |
6618 | label = gen_label_rtx (); | |
6619 | emit_label (label); | |
6620 | ||
6621 | /* Emit the loop body. */ | |
a1c6b246 | 6622 | mips_block_move_straight (dest, src, bytes_per_iter); |
ab77a036 RS |
6623 | |
6624 | /* Move on to the next block. */ | |
a1c6b246 RS |
6625 | mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter)); |
6626 | mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter)); | |
ab77a036 RS |
6627 | |
6628 | /* Emit the loop condition. */ | |
f90b7a5a | 6629 | test = gen_rtx_NE (VOIDmode, src_reg, final_src); |
ab77a036 | 6630 | if (Pmode == DImode) |
f90b7a5a | 6631 | emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); |
ab77a036 | 6632 | else |
f90b7a5a | 6633 | emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); |
ab77a036 RS |
6634 | |
6635 | /* Mop up any left-over bytes. */ | |
6636 | if (leftover) | |
6637 | mips_block_move_straight (dest, src, leftover); | |
6638 | } | |
6639 | ||
65239d20 RS |
6640 | /* Expand a movmemsi instruction, which copies LENGTH bytes from |
6641 | memory reference SRC to memory reference DEST. */ | |
ab77a036 RS |
6642 | |
6643 | bool | |
6644 | mips_expand_block_move (rtx dest, rtx src, rtx length) | |
6645 | { | |
47ac44d6 | 6646 | if (CONST_INT_P (length)) |
a318179e | 6647 | { |
a1c6b246 | 6648 | if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT) |
a318179e | 6649 | { |
ab77a036 RS |
6650 | mips_block_move_straight (dest, src, INTVAL (length)); |
6651 | return true; | |
a318179e | 6652 | } |
ab77a036 | 6653 | else if (optimize) |
a318179e | 6654 | { |
a1c6b246 RS |
6655 | mips_block_move_loop (dest, src, INTVAL (length), |
6656 | MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); | |
ab77a036 | 6657 | return true; |
a318179e RS |
6658 | } |
6659 | } | |
ab77a036 RS |
6660 | return false; |
6661 | } | |
6662 | \f | |
ab77a036 | 6663 | /* Expand a loop of synci insns for the address range [BEGIN, END). */ |
cafe096b | 6664 | |
ab77a036 RS |
6665 | void |
6666 | mips_expand_synci_loop (rtx begin, rtx end) | |
6667 | { | |
d48a3196 CF |
6668 | rtx inc, label, end_label, cmp_result, mask, length; |
6669 | ||
6670 | /* Create end_label. */ | |
6671 | end_label = gen_label_rtx (); | |
6672 | ||
6673 | /* Check if begin equals end. */ | |
6674 | cmp_result = gen_rtx_EQ (VOIDmode, begin, end); | |
6675 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
06a4ab70 | 6676 | |
65239d20 | 6677 | /* Load INC with the cache line size (rdhwr INC,$1). */ |
9d50ba21 AN |
6678 | inc = gen_reg_rtx (Pmode); |
6679 | emit_insn (Pmode == SImode | |
6680 | ? gen_rdhwr_synci_step_si (inc) | |
6681 | : gen_rdhwr_synci_step_di (inc)); | |
06a4ab70 | 6682 | |
d48a3196 CF |
6683 | /* Check if inc is 0. */ |
6684 | cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx); | |
6685 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
6686 | ||
6687 | /* Calculate mask. */ | |
6688 | mask = mips_force_unary (Pmode, NEG, inc); | |
6689 | ||
6690 | /* Mask out begin by mask. */ | |
6691 | begin = mips_force_binary (Pmode, AND, begin, mask); | |
6692 | ||
6693 | /* Calculate length. */ | |
6694 | length = mips_force_binary (Pmode, MINUS, end, begin); | |
6695 | ||
ab77a036 RS |
6696 | /* Loop back to here. */ |
6697 | label = gen_label_rtx (); | |
6698 | emit_label (label); | |
06a4ab70 | 6699 | |
ab77a036 | 6700 | emit_insn (gen_synci (begin)); |
06a4ab70 | 6701 | |
d48a3196 CF |
6702 | /* Update length. */ |
6703 | mips_emit_binary (MINUS, length, length, inc); | |
32041385 | 6704 | |
d48a3196 | 6705 | /* Update begin. */ |
ab77a036 | 6706 | mips_emit_binary (PLUS, begin, begin, inc); |
cee98a59 | 6707 | |
d48a3196 CF |
6708 | /* Check if length is greater than 0. */ |
6709 | cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx); | |
ab77a036 | 6710 | emit_jump_insn (gen_condjump (cmp_result, label)); |
d48a3196 CF |
6711 | |
6712 | emit_label (end_label); | |
ab77a036 RS |
6713 | } |
6714 | \f | |
06d19617 DD |
6715 | /* Expand a QI or HI mode atomic memory operation. |
6716 | ||
6717 | GENERATOR contains a pointer to the gen_* function that generates | |
6718 | the SI mode underlying atomic operation using masks that we | |
6719 | calculate. | |
6720 | ||
6721 | RESULT is the return register for the operation. Its value is NULL | |
6722 | if unused. | |
6723 | ||
6724 | MEM is the location of the atomic access. | |
6725 | ||
6726 | OLDVAL is the first operand for the operation. | |
6727 | ||
6728 | NEWVAL is the optional second operand for the operation. Its value | |
6729 | is NULL if unused. */ | |
49bce30a RS |
6730 | |
6731 | void | |
06d19617 DD |
6732 | mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator, |
6733 | rtx result, rtx mem, rtx oldval, rtx newval) | |
49bce30a RS |
6734 | { |
6735 | rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask; | |
06d19617 DD |
6736 | rtx unshifted_mask_reg, mask, inverted_mask, si_op; |
6737 | rtx res = NULL; | |
977502ff DD |
6738 | enum machine_mode mode; |
6739 | ||
6740 | mode = GET_MODE (mem); | |
49bce30a RS |
6741 | |
6742 | /* Compute the address of the containing SImode value. */ | |
6743 | orig_addr = force_reg (Pmode, XEXP (mem, 0)); | |
6744 | memsi_addr = mips_force_binary (Pmode, AND, orig_addr, | |
6745 | force_reg (Pmode, GEN_INT (-4))); | |
6746 | ||
6747 | /* Create a memory reference for it. */ | |
6748 | memsi = gen_rtx_MEM (SImode, memsi_addr); | |
6749 | set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); | |
6750 | MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); | |
6751 | ||
6752 | /* Work out the byte offset of the QImode or HImode value, | |
6753 | counting from the least significant byte. */ | |
6754 | shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3)); | |
6755 | if (TARGET_BIG_ENDIAN) | |
977502ff | 6756 | mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2)); |
49bce30a RS |
6757 | |
6758 | /* Multiply by eight to convert the shift value from bytes to bits. */ | |
6759 | mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3)); | |
6760 | ||
6761 | /* Make the final shift an SImode value, so that it can be used in | |
6762 | SImode operations. */ | |
6763 | shiftsi = force_reg (SImode, gen_lowpart (SImode, shift)); | |
6764 | ||
6765 | /* Set MASK to an inclusive mask of the QImode or HImode value. */ | |
977502ff DD |
6766 | unshifted_mask = GEN_INT (GET_MODE_MASK (mode)); |
6767 | unshifted_mask_reg = force_reg (SImode, unshifted_mask); | |
6768 | mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi); | |
49bce30a RS |
6769 | |
6770 | /* Compute the equivalent exclusive mask. */ | |
6771 | inverted_mask = gen_reg_rtx (SImode); | |
6772 | emit_insn (gen_rtx_SET (VOIDmode, inverted_mask, | |
6773 | gen_rtx_NOT (SImode, mask))); | |
6774 | ||
6775 | /* Shift the old value into place. */ | |
977502ff DD |
6776 | if (oldval != const0_rtx) |
6777 | { | |
6778 | oldval = convert_modes (SImode, mode, oldval, true); | |
6779 | oldval = force_reg (SImode, oldval); | |
6780 | oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi); | |
6781 | } | |
49bce30a RS |
6782 | |
6783 | /* Do the same for the new value. */ | |
06d19617 | 6784 | if (newval && newval != const0_rtx) |
977502ff DD |
6785 | { |
6786 | newval = convert_modes (SImode, mode, newval, true); | |
6787 | newval = force_reg (SImode, newval); | |
6788 | newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi); | |
6789 | } | |
49bce30a RS |
6790 | |
6791 | /* Do the SImode atomic access. */ | |
06d19617 DD |
6792 | if (result) |
6793 | res = gen_reg_rtx (SImode); | |
6794 | if (newval) | |
6795 | si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval); | |
6796 | else if (result) | |
6797 | si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval); | |
6798 | else | |
6799 | si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval); | |
6800 | ||
6801 | emit_insn (si_op); | |
6802 | ||
6803 | if (result) | |
6804 | { | |
6805 | /* Shift and convert the result. */ | |
6806 | mips_emit_binary (AND, res, res, mask); | |
6807 | mips_emit_binary (LSHIFTRT, res, res, shiftsi); | |
6808 | mips_emit_move (result, gen_lowpart (GET_MODE (result), res)); | |
6809 | } | |
49bce30a RS |
6810 | } |
6811 | ||
ab77a036 RS |
6812 | /* Return true if it is possible to use left/right accesses for a |
6813 | bitfield of WIDTH bits starting BITPOS bits into *OP. When | |
6814 | returning true, update *OP, *LEFT and *RIGHT as follows: | |
cee98a59 | 6815 | |
ab77a036 | 6816 | *OP is a BLKmode reference to the whole field. |
cee98a59 | 6817 | |
ab77a036 RS |
6818 | *LEFT is a QImode reference to the first byte if big endian or |
6819 | the last byte if little endian. This address can be used in the | |
65239d20 | 6820 | left-side instructions (LWL, SWL, LDL, SDL). |
cee98a59 | 6821 | |
ab77a036 RS |
6822 | *RIGHT is a QImode reference to the opposite end of the field and |
6823 | can be used in the patterning right-side instruction. */ | |
cee98a59 | 6824 | |
ab77a036 | 6825 | static bool |
65239d20 | 6826 | mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos, |
ab77a036 RS |
6827 | rtx *left, rtx *right) |
6828 | { | |
6829 | rtx first, last; | |
77d4f3a4 | 6830 | |
ab77a036 RS |
6831 | /* Check that the operand really is a MEM. Not all the extv and |
6832 | extzv predicates are checked. */ | |
6833 | if (!MEM_P (*op)) | |
6834 | return false; | |
cee98a59 | 6835 | |
ab77a036 RS |
6836 | /* Check that the size is valid. */ |
6837 | if (width != 32 && (!TARGET_64BIT || width != 64)) | |
6838 | return false; | |
cee98a59 | 6839 | |
ab77a036 RS |
6840 | /* We can only access byte-aligned values. Since we are always passed |
6841 | a reference to the first byte of the field, it is not necessary to | |
6842 | do anything with BITPOS after this check. */ | |
6843 | if (bitpos % BITS_PER_UNIT != 0) | |
6844 | return false; | |
34b650b3 | 6845 | |
ab77a036 RS |
6846 | /* Reject aligned bitfields: we want to use a normal load or store |
6847 | instead of a left/right pair. */ | |
6848 | if (MEM_ALIGN (*op) >= width) | |
6849 | return false; | |
06a4ab70 | 6850 | |
ab77a036 RS |
6851 | /* Adjust *OP to refer to the whole field. This also has the effect |
6852 | of legitimizing *OP's address for BLKmode, possibly simplifying it. */ | |
6853 | *op = adjust_address (*op, BLKmode, 0); | |
f5541398 | 6854 | set_mem_size (*op, width / BITS_PER_UNIT); |
06a4ab70 | 6855 | |
ab77a036 RS |
6856 | /* Get references to both ends of the field. We deliberately don't |
6857 | use the original QImode *OP for FIRST since the new BLKmode one | |
6858 | might have a simpler address. */ | |
6859 | first = adjust_address (*op, QImode, 0); | |
6860 | last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1); | |
cee98a59 | 6861 | |
ab77a036 | 6862 | /* Allocate to LEFT and RIGHT according to endianness. LEFT should |
65239d20 | 6863 | correspond to the MSB and RIGHT to the LSB. */ |
ab77a036 RS |
6864 | if (TARGET_BIG_ENDIAN) |
6865 | *left = first, *right = last; | |
6866 | else | |
6867 | *left = last, *right = first; | |
cee98a59 | 6868 | |
ab77a036 RS |
6869 | return true; |
6870 | } | |
cee98a59 | 6871 | |
65239d20 RS |
6872 | /* Try to use left/right loads to expand an "extv" or "extzv" pattern. |
6873 | DEST, SRC, WIDTH and BITPOS are the operands passed to the expander; | |
6874 | the operation is the equivalent of: | |
6875 | ||
6876 | (set DEST (*_extract SRC WIDTH BITPOS)) | |
cee98a59 | 6877 | |
65239d20 | 6878 | Return true on success. */ |
cee98a59 | 6879 | |
ab77a036 | 6880 | bool |
65239d20 RS |
6881 | mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width, |
6882 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
6883 | { |
6884 | rtx left, right, temp; | |
6885 | ||
65239d20 RS |
6886 | /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will |
6887 | be a paradoxical word_mode subreg. This is the only case in which | |
ab77a036 RS |
6888 | we allow the destination to be larger than the source. */ |
6889 | if (GET_CODE (dest) == SUBREG | |
6890 | && GET_MODE (dest) == DImode | |
ab77a036 RS |
6891 | && GET_MODE (SUBREG_REG (dest)) == SImode) |
6892 | dest = SUBREG_REG (dest); | |
6893 | ||
6894 | /* After the above adjustment, the destination must be the same | |
6895 | width as the source. */ | |
6896 | if (GET_MODE_BITSIZE (GET_MODE (dest)) != width) | |
6897 | return false; | |
6898 | ||
6899 | if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right)) | |
6900 | return false; | |
6901 | ||
6902 | temp = gen_reg_rtx (GET_MODE (dest)); | |
6903 | if (GET_MODE (dest) == DImode) | |
6904 | { | |
6905 | emit_insn (gen_mov_ldl (temp, src, left)); | |
6906 | emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp)); | |
6907 | } | |
6908 | else | |
6909 | { | |
6910 | emit_insn (gen_mov_lwl (temp, src, left)); | |
6911 | emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); | |
cee98a59 | 6912 | } |
ab77a036 RS |
6913 | return true; |
6914 | } | |
bfed8dac | 6915 | |
65239d20 RS |
6916 | /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH, |
6917 | BITPOS and SRC are the operands passed to the expander; the operation | |
6918 | is the equivalent of: | |
6919 | ||
6920 | (set (zero_extract DEST WIDTH BITPOS) SRC) | |
efa3896a | 6921 | |
65239d20 | 6922 | Return true on success. */ |
cafe096b | 6923 | |
ab77a036 | 6924 | bool |
65239d20 RS |
6925 | mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, |
6926 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
6927 | { |
6928 | rtx left, right; | |
6929 | enum machine_mode mode; | |
6ba7b547 | 6930 | |
ab77a036 RS |
6931 | if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right)) |
6932 | return false; | |
f9e4a411 | 6933 | |
ab77a036 RS |
6934 | mode = mode_for_size (width, MODE_INT, 0); |
6935 | src = gen_lowpart (mode, src); | |
ab77a036 RS |
6936 | if (mode == DImode) |
6937 | { | |
6938 | emit_insn (gen_mov_sdl (dest, src, left)); | |
6939 | emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); | |
6940 | } | |
6941 | else | |
6942 | { | |
6943 | emit_insn (gen_mov_swl (dest, src, left)); | |
6944 | emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); | |
6945 | } | |
6946 | return true; | |
c8d1b2b7 AO |
6947 | } |
6948 | ||
ab77a036 | 6949 | /* Return true if X is a MEM with the same size as MODE. */ |
48156a39 | 6950 | |
ab77a036 RS |
6951 | bool |
6952 | mips_mem_fits_mode_p (enum machine_mode mode, rtx x) | |
48156a39 | 6953 | { |
f5541398 RS |
6954 | return (MEM_P (x) |
6955 | && MEM_SIZE_KNOWN_P (x) | |
6956 | && MEM_SIZE (x) == GET_MODE_SIZE (mode)); | |
48156a39 NS |
6957 | } |
6958 | ||
65239d20 | 6959 | /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the |
ab77a036 RS |
6960 | source of an "ext" instruction or the destination of an "ins" |
6961 | instruction. OP must be a register operand and the following | |
6962 | conditions must hold: | |
ac8ab9fe | 6963 | |
65239d20 RS |
6964 | 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op)) |
6965 | 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
6966 | 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
ab77a036 RS |
6967 | |
6968 | Also reject lengths equal to a word as they are better handled | |
6969 | by the move patterns. */ | |
6970 | ||
6971 | bool | |
65239d20 | 6972 | mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) |
ac8ab9fe | 6973 | { |
ab77a036 RS |
6974 | if (!ISA_HAS_EXT_INS |
6975 | || !register_operand (op, VOIDmode) | |
6976 | || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) | |
6977 | return false; | |
ac8ab9fe | 6978 | |
65239d20 RS |
6979 | if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1)) |
6980 | return false; | |
ac8ab9fe | 6981 | |
65239d20 | 6982 | if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op))) |
ab77a036 RS |
6983 | return false; |
6984 | ||
6985 | return true; | |
ac8ab9fe | 6986 | } |
49912bcd AN |
6987 | |
6988 | /* Check if MASK and SHIFT are valid in mask-low-and-shift-left | |
6989 | operation if MAXLEN is the maxium length of consecutive bits that | |
6990 | can make up MASK. MODE is the mode of the operation. See | |
6991 | mask_low_and_shift_len for the actual definition. */ | |
6992 | ||
6993 | bool | |
6994 | mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen) | |
6995 | { | |
6996 | return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen); | |
6997 | } | |
6998 | ||
b2c9d70f AN |
6999 | /* Return true iff OP1 and OP2 are valid operands together for the |
7000 | *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider, | |
7001 | see the table in the comment before the pattern. */ | |
7002 | ||
7003 | bool | |
7004 | and_operands_ok (enum machine_mode mode, rtx op1, rtx op2) | |
7005 | { | |
7006 | return (memory_operand (op1, mode) | |
7007 | ? and_load_operand (op2, mode) | |
7008 | : and_reg_operand (op2, mode)); | |
7009 | } | |
7010 | ||
49912bcd AN |
7011 | /* The canonical form of a mask-low-and-shift-left operation is |
7012 | (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits | |
7013 | cleared. Thus we need to shift MASK to the right before checking if it | |
7014 | is a valid mask value. MODE is the mode of the operation. If true | |
7015 | return the length of the mask, otherwise return -1. */ | |
7016 | ||
7017 | int | |
7018 | mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift) | |
7019 | { | |
7020 | HOST_WIDE_INT shval; | |
7021 | ||
7022 | shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1); | |
7023 | return exact_log2 ((UINTVAL (mask) >> shval) + 1); | |
7024 | } | |
ab77a036 | 7025 | \f |
65239d20 | 7026 | /* Return true if -msplit-addresses is selected and should be honored. |
ac8ab9fe | 7027 | |
65239d20 RS |
7028 | -msplit-addresses is a half-way house between explicit relocations |
7029 | and the traditional assembler macros. It can split absolute 32-bit | |
7030 | symbolic constants into a high/lo_sum pair but uses macros for other | |
7031 | sorts of access. | |
ab77a036 RS |
7032 | |
7033 | Like explicit relocation support for REL targets, it relies | |
7034 | on GNU extensions in the assembler and the linker. | |
7035 | ||
7036 | Although this code should work for -O0, it has traditionally | |
7037 | been treated as an optimization. */ | |
7038 | ||
65239d20 RS |
7039 | static bool |
7040 | mips_split_addresses_p (void) | |
c8d1b2b7 | 7041 | { |
65239d20 RS |
7042 | return (TARGET_SPLIT_ADDRESSES |
7043 | && optimize | |
7044 | && !TARGET_MIPS16 | |
7045 | && !flag_pic | |
7046 | && !ABI_HAS_64BIT_SYMBOLS); | |
cee98a59 MM |
7047 | } |
7048 | ||
65239d20 | 7049 | /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */ |
2bcb2ab3 | 7050 | |
ab77a036 RS |
7051 | static void |
7052 | mips_init_relocs (void) | |
2bcb2ab3 | 7053 | { |
ab77a036 | 7054 | memset (mips_split_p, '\0', sizeof (mips_split_p)); |
08d0963a | 7055 | memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p)); |
ab77a036 RS |
7056 | memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs)); |
7057 | memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs)); | |
2bcb2ab3 | 7058 | |
ab77a036 RS |
7059 | if (ABI_HAS_64BIT_SYMBOLS) |
7060 | { | |
7061 | if (TARGET_EXPLICIT_RELOCS) | |
7062 | { | |
7063 | mips_split_p[SYMBOL_64_HIGH] = true; | |
7064 | mips_hi_relocs[SYMBOL_64_HIGH] = "%highest("; | |
7065 | mips_lo_relocs[SYMBOL_64_HIGH] = "%higher("; | |
7066 | ||
7067 | mips_split_p[SYMBOL_64_MID] = true; | |
7068 | mips_hi_relocs[SYMBOL_64_MID] = "%higher("; | |
7069 | mips_lo_relocs[SYMBOL_64_MID] = "%hi("; | |
7070 | ||
7071 | mips_split_p[SYMBOL_64_LOW] = true; | |
7072 | mips_hi_relocs[SYMBOL_64_LOW] = "%hi("; | |
7073 | mips_lo_relocs[SYMBOL_64_LOW] = "%lo("; | |
7074 | ||
7075 | mips_split_p[SYMBOL_ABSOLUTE] = true; | |
7076 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7077 | } | |
7078 | } | |
7079 | else | |
7080 | { | |
65239d20 | 7081 | if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16) |
ab77a036 RS |
7082 | { |
7083 | mips_split_p[SYMBOL_ABSOLUTE] = true; | |
7084 | mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; | |
7085 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7086 | ||
7087 | mips_lo_relocs[SYMBOL_32_HIGH] = "%hi("; | |
7088 | } | |
7089 | } | |
2bcb2ab3 GK |
7090 | |
7091 | if (TARGET_MIPS16) | |
7092 | { | |
ab77a036 RS |
7093 | /* The high part is provided by a pseudo copy of $gp. */ |
7094 | mips_split_p[SYMBOL_GP_RELATIVE] = true; | |
7095 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel("; | |
2bcb2ab3 | 7096 | } |
08d0963a RS |
7097 | else if (TARGET_EXPLICIT_RELOCS) |
7098 | /* Small data constants are kept whole until after reload, | |
7099 | then lowered by mips_rewrite_small_data. */ | |
7100 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel("; | |
2bcb2ab3 | 7101 | |
ab77a036 RS |
7102 | if (TARGET_EXPLICIT_RELOCS) |
7103 | { | |
ab77a036 RS |
7104 | mips_split_p[SYMBOL_GOT_PAGE_OFST] = true; |
7105 | if (TARGET_NEWABI) | |
7106 | { | |
7107 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page("; | |
7108 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst("; | |
7109 | } | |
7110 | else | |
7111 | { | |
7112 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got("; | |
7113 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo("; | |
7114 | } | |
08d0963a RS |
7115 | if (TARGET_MIPS16) |
7116 | /* Expose the use of $28 as soon as possible. */ | |
7117 | mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true; | |
cee98a59 | 7118 | |
ab77a036 RS |
7119 | if (TARGET_XGOT) |
7120 | { | |
7121 | /* The HIGH and LO_SUM are matched by special .md patterns. */ | |
7122 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
cee98a59 | 7123 | |
ab77a036 RS |
7124 | mips_split_p[SYMBOL_GOTOFF_DISP] = true; |
7125 | mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi("; | |
7126 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo("; | |
c831afd5 | 7127 | |
ab77a036 RS |
7128 | mips_split_p[SYMBOL_GOTOFF_CALL] = true; |
7129 | mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi("; | |
7130 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo("; | |
7131 | } | |
7132 | else | |
7133 | { | |
7134 | if (TARGET_NEWABI) | |
7135 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp("; | |
7136 | else | |
7137 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got("; | |
7138 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16("; | |
08d0963a RS |
7139 | if (TARGET_MIPS16) |
7140 | /* Expose the use of $28 as soon as possible. */ | |
7141 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
ab77a036 RS |
7142 | } |
7143 | } | |
a50f2a09 | 7144 | |
ab77a036 RS |
7145 | if (TARGET_NEWABI) |
7146 | { | |
7147 | mips_split_p[SYMBOL_GOTOFF_LOADGP] = true; | |
7148 | mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel("; | |
7149 | mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel("; | |
c831afd5 | 7150 | } |
f5963e61 | 7151 | |
ab77a036 RS |
7152 | mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd("; |
7153 | mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm("; | |
65239d20 RS |
7154 | |
7155 | mips_split_p[SYMBOL_DTPREL] = true; | |
ab77a036 RS |
7156 | mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi("; |
7157 | mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo("; | |
65239d20 | 7158 | |
ab77a036 | 7159 | mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel("; |
65239d20 RS |
7160 | |
7161 | mips_split_p[SYMBOL_TPREL] = true; | |
ab77a036 RS |
7162 | mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi("; |
7163 | mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo("; | |
cee98a59 | 7164 | |
ab77a036 | 7165 | mips_lo_relocs[SYMBOL_HALF] = "%half("; |
cee98a59 | 7166 | } |
ab77a036 | 7167 | |
ab77a036 RS |
7168 | /* Print symbolic operand OP, which is part of a HIGH or LO_SUM |
7169 | in context CONTEXT. RELOCS is the array of relocations to use. */ | |
7170 | ||
7171 | static void | |
65239d20 RS |
7172 | mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context, |
7173 | const char **relocs) | |
ab77a036 RS |
7174 | { |
7175 | enum mips_symbol_type symbol_type; | |
7176 | const char *p; | |
7177 | ||
7178 | symbol_type = mips_classify_symbolic_expression (op, context); | |
65239d20 | 7179 | gcc_assert (relocs[symbol_type]); |
ab77a036 RS |
7180 | |
7181 | fputs (relocs[symbol_type], file); | |
7182 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7183 | for (p = relocs[symbol_type]; *p != 0; p++) | |
7184 | if (*p == '(') | |
7185 | fputc (')', file); | |
7186 | } | |
7187 | ||
cf5fb4b0 RS |
7188 | /* Start a new block with the given asm switch enabled. If we need |
7189 | to print a directive, emit PREFIX before it and SUFFIX after it. */ | |
7190 | ||
7191 | static void | |
7192 | mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7193 | const char *prefix, const char *suffix) | |
7194 | { | |
7195 | if (asm_switch->nesting_level == 0) | |
7196 | fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix); | |
7197 | asm_switch->nesting_level++; | |
7198 | } | |
7199 | ||
7200 | /* Likewise, but end a block. */ | |
7201 | ||
7202 | static void | |
7203 | mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7204 | const char *prefix, const char *suffix) | |
7205 | { | |
7206 | gcc_assert (asm_switch->nesting_level); | |
7207 | asm_switch->nesting_level--; | |
7208 | if (asm_switch->nesting_level == 0) | |
7209 | fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix); | |
7210 | } | |
7211 | ||
7212 | /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1 | |
7213 | that either print a complete line or print nothing. */ | |
7214 | ||
7215 | void | |
7216 | mips_push_asm_switch (struct mips_asm_switch *asm_switch) | |
7217 | { | |
7218 | mips_push_asm_switch_1 (asm_switch, "\t", "\n"); | |
7219 | } | |
7220 | ||
7221 | void | |
7222 | mips_pop_asm_switch (struct mips_asm_switch *asm_switch) | |
7223 | { | |
7224 | mips_pop_asm_switch_1 (asm_switch, "\t", "\n"); | |
7225 | } | |
7226 | ||
07045266 | 7227 | /* Print the text for PRINT_OPERAND punctation character CH to FILE. |
dfad12b5 RS |
7228 | The punctuation characters are: |
7229 | ||
07045266 RS |
7230 | '(' Start a nested ".set noreorder" block. |
7231 | ')' End a nested ".set noreorder" block. | |
7232 | '[' Start a nested ".set noat" block. | |
7233 | ']' End a nested ".set noat" block. | |
7234 | '<' Start a nested ".set nomacro" block. | |
7235 | '>' End a nested ".set nomacro" block. | |
7236 | '*' Behave like %(%< if generating a delayed-branch sequence. | |
7237 | '#' Print a nop if in a ".set noreorder" block. | |
7238 | '/' Like '#', but do nothing within a delayed-branch sequence. | |
7239 | '?' Print "l" if mips_branch_likely is true | |
ee9a72e5 | 7240 | '~' Print a nop if mips_branch_likely is true |
ffa9d0b1 | 7241 | '.' Print the name of the register with a hard-wired zero (zero or $0). |
07045266 | 7242 | '@' Print the name of the assembler temporary register (at or $1). |
2bcb2ab3 | 7243 | '^' Print the name of the pic call-through register (t9 or $25). |
f833ffd4 | 7244 | '+' Print the name of the gp register (usually gp or $28). |
07045266 | 7245 | '$' Print the name of the stack pointer register (sp or $29). |
cee98a59 | 7246 | |
07045266 | 7247 | See also mips_init_print_operand_pucnt. */ |
cee98a59 | 7248 | |
07045266 RS |
7249 | static void |
7250 | mips_print_operand_punctuation (FILE *file, int ch) | |
7251 | { | |
7252 | switch (ch) | |
cee98a59 | 7253 | { |
07045266 | 7254 | case '(': |
cf5fb4b0 | 7255 | mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t"); |
07045266 | 7256 | break; |
cee98a59 | 7257 | |
07045266 | 7258 | case ')': |
cf5fb4b0 | 7259 | mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", ""); |
07045266 | 7260 | break; |
cee98a59 | 7261 | |
07045266 | 7262 | case '[': |
cf5fb4b0 | 7263 | mips_push_asm_switch_1 (&mips_noat, "", "\n\t"); |
07045266 | 7264 | break; |
ffa9d0b1 | 7265 | |
07045266 | 7266 | case ']': |
cf5fb4b0 | 7267 | mips_pop_asm_switch_1 (&mips_noat, "\n\t", ""); |
07045266 | 7268 | break; |
cee98a59 | 7269 | |
07045266 | 7270 | case '<': |
cf5fb4b0 | 7271 | mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t"); |
07045266 | 7272 | break; |
2bcb2ab3 | 7273 | |
07045266 | 7274 | case '>': |
cf5fb4b0 | 7275 | mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", ""); |
07045266 | 7276 | break; |
2bcb2ab3 | 7277 | |
07045266 RS |
7278 | case '*': |
7279 | if (final_sequence != 0) | |
7280 | { | |
7281 | mips_print_operand_punctuation (file, '('); | |
7282 | mips_print_operand_punctuation (file, '<'); | |
7283 | } | |
7284 | break; | |
cee98a59 | 7285 | |
07045266 | 7286 | case '#': |
cf5fb4b0 | 7287 | if (mips_noreorder.nesting_level > 0) |
07045266 RS |
7288 | fputs ("\n\tnop", file); |
7289 | break; | |
cee98a59 | 7290 | |
07045266 RS |
7291 | case '/': |
7292 | /* Print an extra newline so that the delayed insn is separated | |
7293 | from the following ones. This looks neater and is consistent | |
7294 | with non-nop delayed sequences. */ | |
cf5fb4b0 | 7295 | if (mips_noreorder.nesting_level > 0 && final_sequence == 0) |
07045266 RS |
7296 | fputs ("\n\tnop\n", file); |
7297 | break; | |
cee98a59 | 7298 | |
07045266 RS |
7299 | case '?': |
7300 | if (mips_branch_likely) | |
7301 | putc ('l', file); | |
7302 | break; | |
cee98a59 | 7303 | |
ee9a72e5 JK |
7304 | case '~': |
7305 | if (mips_branch_likely) | |
7306 | fputs ("\n\tnop", file); | |
7307 | break; | |
7308 | ||
07045266 RS |
7309 | case '.': |
7310 | fputs (reg_names[GP_REG_FIRST + 0], file); | |
7311 | break; | |
cee98a59 | 7312 | |
07045266 | 7313 | case '@': |
293593b1 | 7314 | fputs (reg_names[AT_REGNUM], file); |
07045266 | 7315 | break; |
6f2993e5 | 7316 | |
07045266 RS |
7317 | case '^': |
7318 | fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file); | |
7319 | break; | |
cee98a59 | 7320 | |
07045266 RS |
7321 | case '+': |
7322 | fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); | |
7323 | break; | |
cee98a59 | 7324 | |
07045266 RS |
7325 | case '$': |
7326 | fputs (reg_names[STACK_POINTER_REGNUM], file); | |
7327 | break; | |
cee98a59 | 7328 | |
07045266 RS |
7329 | default: |
7330 | gcc_unreachable (); | |
7331 | break; | |
7332 | } | |
7333 | } | |
cee98a59 | 7334 | |
07045266 | 7335 | /* Initialize mips_print_operand_punct. */ |
cee98a59 | 7336 | |
07045266 RS |
7337 | static void |
7338 | mips_init_print_operand_punct (void) | |
7339 | { | |
7340 | const char *p; | |
cee98a59 | 7341 | |
6f5a62e9 | 7342 | for (p = "()[]<>*#/?~.@^+$"; *p; p++) |
07045266 RS |
7343 | mips_print_operand_punct[(unsigned char) *p] = true; |
7344 | } | |
cee98a59 | 7345 | |
07045266 RS |
7346 | /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction |
7347 | associated with condition CODE. Print the condition part of the | |
7348 | opcode to FILE. */ | |
cee98a59 | 7349 | |
07045266 RS |
7350 | static void |
7351 | mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter) | |
7352 | { | |
7353 | switch (code) | |
7354 | { | |
7355 | case EQ: | |
7356 | case NE: | |
7357 | case GT: | |
7358 | case GE: | |
7359 | case LT: | |
7360 | case LE: | |
7361 | case GTU: | |
7362 | case GEU: | |
7363 | case LTU: | |
7364 | case LEU: | |
7365 | /* Conveniently, the MIPS names for these conditions are the same | |
7366 | as their RTL equivalents. */ | |
7367 | fputs (GET_RTX_NAME (code), file); | |
7368 | break; | |
cee98a59 | 7369 | |
07045266 RS |
7370 | default: |
7371 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
7372 | break; | |
7373 | } | |
7374 | } | |
cee98a59 | 7375 | |
07045266 | 7376 | /* Likewise floating-point branches. */ |
f5963e61 | 7377 | |
07045266 RS |
7378 | static void |
7379 | mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter) | |
7380 | { | |
7381 | switch (code) | |
7382 | { | |
7383 | case EQ: | |
7384 | fputs ("c1f", file); | |
7385 | break; | |
efa3896a | 7386 | |
07045266 RS |
7387 | case NE: |
7388 | fputs ("c1t", file); | |
7389 | break; | |
66471b47 | 7390 | |
07045266 RS |
7391 | default: |
7392 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
7393 | break; | |
7394 | } | |
7395 | } | |
66471b47 | 7396 | |
6e9e0126 NF |
7397 | /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
7398 | ||
7399 | static bool | |
7400 | mips_print_operand_punct_valid_p (unsigned char code) | |
7401 | { | |
7402 | return mips_print_operand_punct[code]; | |
7403 | } | |
7404 | ||
7405 | /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are: | |
f5963e61 | 7406 | |
07045266 RS |
7407 | 'X' Print CONST_INT OP in hexadecimal format. |
7408 | 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format. | |
7409 | 'd' Print CONST_INT OP in decimal. | |
49912bcd | 7410 | 'm' Print one less than CONST_INT OP in decimal. |
07045266 RS |
7411 | 'h' Print the high-part relocation associated with OP, after stripping |
7412 | any outermost HIGH. | |
7413 | 'R' Print the low-part relocation associated with OP. | |
7414 | 'C' Print the integer branch condition for comparison OP. | |
7415 | 'N' Print the inverse of the integer branch condition for comparison OP. | |
7416 | 'F' Print the FPU branch condition for comparison OP. | |
7417 | 'W' Print the inverse of the FPU branch condition for comparison OP. | |
7418 | 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...), | |
7419 | 'z' for (eq:?I ...), 'n' for (ne:?I ...). | |
7420 | 't' Like 'T', but with the EQ/NE cases reversed | |
7421 | 'Y' Print mips_fp_conditions[INTVAL (OP)] | |
7422 | 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing. | |
7423 | 'q' Print a DSP accumulator register. | |
7424 | 'D' Print the second part of a double-word register or memory operand. | |
7425 | 'L' Print the low-order register in a double-word register operand. | |
7426 | 'M' Print high-order register in a double-word register operand. | |
7427 | 'z' Print $0 if OP is zero, otherwise print OP normally. */ | |
7428 | ||
6e9e0126 | 7429 | static void |
65239d20 | 7430 | mips_print_operand (FILE *file, rtx op, int letter) |
07045266 RS |
7431 | { |
7432 | enum rtx_code code; | |
cee98a59 | 7433 | |
6e9e0126 | 7434 | if (mips_print_operand_punct_valid_p (letter)) |
cee98a59 | 7435 | { |
07045266 | 7436 | mips_print_operand_punctuation (file, letter); |
cee98a59 MM |
7437 | return; |
7438 | } | |
7439 | ||
07045266 | 7440 | gcc_assert (op); |
cee98a59 | 7441 | code = GET_CODE (op); |
2a0b0bf5 | 7442 | |
07045266 RS |
7443 | switch (letter) |
7444 | { | |
7445 | case 'X': | |
47ac44d6 | 7446 | if (CONST_INT_P (op)) |
07045266 RS |
7447 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); |
7448 | else | |
7449 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7450 | break; | |
cee98a59 | 7451 | |
07045266 | 7452 | case 'x': |
47ac44d6 | 7453 | if (CONST_INT_P (op)) |
07045266 RS |
7454 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff); |
7455 | else | |
7456 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7457 | break; | |
0ff83799 | 7458 | |
07045266 | 7459 | case 'd': |
47ac44d6 | 7460 | if (CONST_INT_P (op)) |
07045266 RS |
7461 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op)); |
7462 | else | |
7463 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7464 | break; | |
0ff83799 | 7465 | |
49912bcd | 7466 | case 'm': |
47ac44d6 | 7467 | if (CONST_INT_P (op)) |
49912bcd AN |
7468 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1); |
7469 | else | |
7470 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7471 | break; | |
7472 | ||
07045266 RS |
7473 | case 'h': |
7474 | if (code == HIGH) | |
108b61d5 | 7475 | op = XEXP (op, 0); |
65239d20 | 7476 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs); |
07045266 RS |
7477 | break; |
7478 | ||
7479 | case 'R': | |
65239d20 | 7480 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs); |
07045266 | 7481 | break; |
108b61d5 | 7482 | |
07045266 RS |
7483 | case 'C': |
7484 | mips_print_int_branch_condition (file, code, letter); | |
7485 | break; | |
108b61d5 | 7486 | |
07045266 RS |
7487 | case 'N': |
7488 | mips_print_int_branch_condition (file, reverse_condition (code), letter); | |
7489 | break; | |
7490 | ||
7491 | case 'F': | |
7492 | mips_print_float_branch_condition (file, code, letter); | |
7493 | break; | |
7494 | ||
7495 | case 'W': | |
7496 | mips_print_float_branch_condition (file, reverse_condition (code), | |
7497 | letter); | |
7498 | break; | |
7499 | ||
7500 | case 'T': | |
7501 | case 't': | |
7502 | { | |
7503 | int truth = (code == NE) == (letter == 'T'); | |
7504 | fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); | |
7505 | } | |
7506 | break; | |
7507 | ||
7508 | case 'Y': | |
7509 | if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions)) | |
7510 | fputs (mips_fp_conditions[UINTVAL (op)], file); | |
308cd611 | 7511 | else |
07045266 RS |
7512 | output_operand_lossage ("'%%%c' is not a valid operand prefix", |
7513 | letter); | |
7514 | break; | |
06a4ab70 | 7515 | |
07045266 | 7516 | case 'Z': |
308cd611 RS |
7517 | if (ISA_HAS_8CC) |
7518 | { | |
65239d20 | 7519 | mips_print_operand (file, op, 0); |
308cd611 RS |
7520 | fputc (',', file); |
7521 | } | |
07045266 | 7522 | break; |
118ea793 | 7523 | |
07045266 RS |
7524 | case 'q': |
7525 | if (code == REG && MD_REG_P (REGNO (op))) | |
118ea793 | 7526 | fprintf (file, "$ac0"); |
07045266 RS |
7527 | else if (code == REG && DSP_ACC_REG_P (REGNO (op))) |
7528 | fprintf (file, "$ac%c", reg_names[REGNO (op)][3]); | |
51c6b247 | 7529 | else |
07045266 RS |
7530 | output_operand_lossage ("invalid use of '%%%c'", letter); |
7531 | break; | |
cee98a59 | 7532 | |
07045266 RS |
7533 | default: |
7534 | switch (code) | |
7535 | { | |
7536 | case REG: | |
7537 | { | |
7538 | unsigned int regno = REGNO (op); | |
7539 | if ((letter == 'M' && TARGET_LITTLE_ENDIAN) | |
7540 | || (letter == 'L' && TARGET_BIG_ENDIAN) | |
7541 | || letter == 'D') | |
7542 | regno++; | |
b0907a6c AN |
7543 | else if (letter && letter != 'z' && letter != 'M' && letter != 'L') |
7544 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
e19da24c CF |
7545 | /* We need to print $0 .. $31 for COP0 registers. */ |
7546 | if (COP0_REG_P (regno)) | |
7547 | fprintf (file, "$%s", ®_names[regno][4]); | |
7548 | else | |
7549 | fprintf (file, "%s", reg_names[regno]); | |
07045266 RS |
7550 | } |
7551 | break; | |
cee98a59 | 7552 | |
07045266 RS |
7553 | case MEM: |
7554 | if (letter == 'D') | |
7555 | output_address (plus_constant (XEXP (op, 0), 4)); | |
b0907a6c AN |
7556 | else if (letter && letter != 'z') |
7557 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
7558 | else |
7559 | output_address (XEXP (op, 0)); | |
7560 | break; | |
cee98a59 | 7561 | |
07045266 RS |
7562 | default: |
7563 | if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) | |
7564 | fputs (reg_names[GP_REG_FIRST], file); | |
b0907a6c AN |
7565 | else if (letter && letter != 'z') |
7566 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
7567 | else if (CONST_GP_P (op)) |
7568 | fputs (reg_names[GLOBAL_POINTER_REGNUM], file); | |
7569 | else | |
7570 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7571 | break; | |
7572 | } | |
b3c90666 | 7573 | } |
108b61d5 | 7574 | } |
07045266 | 7575 | |
6e9e0126 | 7576 | /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ |
cee98a59 | 7577 | |
6e9e0126 | 7578 | static void |
65239d20 | 7579 | mips_print_operand_address (FILE *file, rtx x) |
cafe096b EC |
7580 | { |
7581 | struct mips_address_info addr; | |
cee98a59 | 7582 | |
108b61d5 RS |
7583 | if (mips_classify_address (&addr, x, word_mode, true)) |
7584 | switch (addr.type) | |
7585 | { | |
7586 | case ADDRESS_REG: | |
65239d20 | 7587 | mips_print_operand (file, addr.offset, 0); |
108b61d5 RS |
7588 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
7589 | return; | |
7590 | ||
7591 | case ADDRESS_LO_SUM: | |
65239d20 RS |
7592 | mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM, |
7593 | mips_lo_relocs); | |
108b61d5 RS |
7594 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
7595 | return; | |
7596 | ||
7597 | case ADDRESS_CONST_INT: | |
4767c570 | 7598 | output_addr_const (file, x); |
65239d20 | 7599 | fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); |
4767c570 RS |
7600 | return; |
7601 | ||
108b61d5 | 7602 | case ADDRESS_SYMBOLIC: |
c93c5160 | 7603 | output_addr_const (file, mips_strip_unspec_address (x)); |
108b61d5 RS |
7604 | return; |
7605 | } | |
7ad769fe | 7606 | gcc_unreachable (); |
cee98a59 | 7607 | } |
301d03af | 7608 | \f |
65239d20 | 7609 | /* Implement TARGET_ENCODE_SECTION_INFO. */ |
ab77a036 RS |
7610 | |
7611 | static void | |
7612 | mips_encode_section_info (tree decl, rtx rtl, int first) | |
7613 | { | |
7614 | default_encode_section_info (decl, rtl, first); | |
7615 | ||
7616 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
7617 | { | |
7618 | rtx symbol = XEXP (rtl, 0); | |
7619 | tree type = TREE_TYPE (decl); | |
7620 | ||
65239d20 | 7621 | /* Encode whether the symbol is short or long. */ |
ab77a036 RS |
7622 | if ((TARGET_LONG_CALLS && !mips_near_type_p (type)) |
7623 | || mips_far_type_p (type)) | |
7624 | SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; | |
7625 | } | |
7626 | } | |
7627 | ||
7628 | /* Implement TARGET_SELECT_RTX_SECTION. */ | |
7629 | ||
7630 | static section * | |
7631 | mips_select_rtx_section (enum machine_mode mode, rtx x, | |
7632 | unsigned HOST_WIDE_INT align) | |
7633 | { | |
7634 | /* ??? Consider using mergeable small data sections. */ | |
7635 | if (mips_rtx_constant_in_small_data_p (mode)) | |
7636 | return get_named_section (NULL, ".sdata", 0); | |
7637 | ||
7638 | return default_elf_select_rtx_section (mode, x, align); | |
7639 | } | |
7640 | ||
7641 | /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. | |
7642 | ||
7643 | The complication here is that, with the combination TARGET_ABICALLS | |
e21d5757 DJ |
7644 | && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use |
7645 | absolute addresses, and should therefore not be included in the | |
7646 | read-only part of a DSO. Handle such cases by selecting a normal | |
7647 | data section instead of a read-only one. The logic apes that in | |
7648 | default_function_rodata_section. */ | |
ab77a036 RS |
7649 | |
7650 | static section * | |
7651 | mips_function_rodata_section (tree decl) | |
7652 | { | |
e21d5757 | 7653 | if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD) |
ab77a036 RS |
7654 | return default_function_rodata_section (decl); |
7655 | ||
7656 | if (decl && DECL_SECTION_NAME (decl)) | |
7657 | { | |
7658 | const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
7659 | if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0) | |
7660 | { | |
7661 | char *rname = ASTRDUP (name); | |
7662 | rname[14] = 'd'; | |
7663 | return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl); | |
7664 | } | |
65239d20 RS |
7665 | else if (flag_function_sections |
7666 | && flag_data_sections | |
ab77a036 RS |
7667 | && strncmp (name, ".text.", 6) == 0) |
7668 | { | |
7669 | char *rname = ASTRDUP (name); | |
7670 | memcpy (rname + 1, "data", 4); | |
7671 | return get_section (rname, SECTION_WRITE, decl); | |
7672 | } | |
7673 | } | |
7674 | return data_section; | |
7675 | } | |
7676 | ||
65239d20 | 7677 | /* Implement TARGET_IN_SMALL_DATA_P. */ |
ab77a036 RS |
7678 | |
7679 | static bool | |
7680 | mips_in_small_data_p (const_tree decl) | |
7681 | { | |
65239d20 | 7682 | unsigned HOST_WIDE_INT size; |
ab77a036 RS |
7683 | |
7684 | if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL) | |
7685 | return false; | |
7686 | ||
65239d20 RS |
7687 | /* We don't yet generate small-data references for -mabicalls |
7688 | or VxWorks RTP code. See the related -G handling in | |
525c561d | 7689 | mips_option_override. */ |
ab77a036 RS |
7690 | if (TARGET_ABICALLS || TARGET_VXWORKS_RTP) |
7691 | return false; | |
7692 | ||
7693 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) | |
7694 | { | |
7695 | const char *name; | |
7696 | ||
7697 | /* Reject anything that isn't in a known small-data section. */ | |
7698 | name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
7699 | if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) | |
7700 | return false; | |
7701 | ||
7702 | /* If a symbol is defined externally, the assembler will use the | |
7703 | usual -G rules when deciding how to implement macros. */ | |
7704 | if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl)) | |
7705 | return true; | |
7706 | } | |
7707 | else if (TARGET_EMBEDDED_DATA) | |
7708 | { | |
7709 | /* Don't put constants into the small data section: we want them | |
7710 | to be in ROM rather than RAM. */ | |
7711 | if (TREE_CODE (decl) != VAR_DECL) | |
7712 | return false; | |
7713 | ||
7714 | if (TREE_READONLY (decl) | |
7715 | && !TREE_SIDE_EFFECTS (decl) | |
7716 | && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl)))) | |
7717 | return false; | |
7718 | } | |
7719 | ||
7720 | /* Enforce -mlocal-sdata. */ | |
7721 | if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl)) | |
7722 | return false; | |
7723 | ||
7724 | /* Enforce -mextern-sdata. */ | |
7725 | if (!TARGET_EXTERN_SDATA && DECL_P (decl)) | |
7726 | { | |
7727 | if (DECL_EXTERNAL (decl)) | |
7728 | return false; | |
7729 | if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL) | |
7730 | return false; | |
7731 | } | |
7732 | ||
2a4430a6 RS |
7733 | /* We have traditionally not treated zero-sized objects as small data, |
7734 | so this is now effectively part of the ABI. */ | |
ab77a036 | 7735 | size = int_size_in_bytes (TREE_TYPE (decl)); |
2a4430a6 | 7736 | return size > 0 && size <= mips_small_data_threshold; |
ab77a036 RS |
7737 | } |
7738 | ||
7739 | /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use | |
7740 | anchors for small data: the GP register acts as an anchor in that | |
7741 | case. We also don't want to use them for PC-relative accesses, | |
7742 | where the PC acts as an anchor. */ | |
7743 | ||
7744 | static bool | |
7745 | mips_use_anchors_for_symbol_p (const_rtx symbol) | |
7746 | { | |
7747 | switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM)) | |
7748 | { | |
7749 | case SYMBOL_PC_RELATIVE: | |
7750 | case SYMBOL_GP_RELATIVE: | |
7751 | return false; | |
7752 | ||
7753 | default: | |
7754 | return default_use_anchors_for_symbol_p (symbol); | |
7755 | } | |
7756 | } | |
7757 | \f | |
7758 | /* The MIPS debug format wants all automatic variables and arguments | |
7759 | to be in terms of the virtual frame pointer (stack pointer before | |
7760 | any adjustment in the function), while the MIPS 3.0 linker wants | |
7761 | the frame pointer to be the stack pointer after the initial | |
7762 | adjustment. So, we do the adjustment here. The arg pointer (which | |
7763 | is eliminated) points to the virtual frame pointer, while the frame | |
7764 | pointer (which may be eliminated) points to the stack pointer after | |
7765 | the initial adjustments. */ | |
7766 | ||
7767 | HOST_WIDE_INT | |
7768 | mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) | |
7769 | { | |
7770 | rtx offset2 = const0_rtx; | |
7771 | rtx reg = eliminate_constant_term (addr, &offset2); | |
7772 | ||
7773 | if (offset == 0) | |
7774 | offset = INTVAL (offset2); | |
7775 | ||
65239d20 RS |
7776 | if (reg == stack_pointer_rtx |
7777 | || reg == frame_pointer_rtx | |
ab77a036 RS |
7778 | || reg == hard_frame_pointer_rtx) |
7779 | { | |
f374e413 RS |
7780 | offset -= cfun->machine->frame.total_size; |
7781 | if (reg == hard_frame_pointer_rtx) | |
7782 | offset += cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
7783 | } |
7784 | ||
7785 | /* sdbout_parms does not want this to crash for unrecognized cases. */ | |
7786 | #if 0 | |
7787 | else if (reg != arg_pointer_rtx) | |
7788 | fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer", | |
7789 | addr); | |
7790 | #endif | |
7791 | ||
7792 | return offset; | |
7793 | } | |
7794 | \f | |
65239d20 | 7795 | /* Implement ASM_OUTPUT_EXTERNAL. */ |
cee98a59 | 7796 | |
f8fdb503 L |
7797 | void |
7798 | mips_output_external (FILE *file, tree decl, const char *name) | |
5619cc87 | 7799 | { |
f8fdb503 | 7800 | default_elf_asm_output_external (file, decl, name); |
5619cc87 | 7801 | |
f8fdb503 L |
7802 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
7803 | set in order to avoid putting out names that are never really | |
7804 | used. */ | |
7805 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
6773a41c | 7806 | { |
f8fdb503 L |
7807 | if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl)) |
7808 | { | |
65239d20 RS |
7809 | /* When using assembler macros, emit .extern directives for |
7810 | all small-data externs so that the assembler knows how | |
7811 | big they are. | |
7812 | ||
7813 | In most cases it would be safe (though pointless) to emit | |
7814 | .externs for other symbols too. One exception is when an | |
7815 | object is within the -G limit but declared by the user to | |
7816 | be in a section other than .sbss or .sdata. */ | |
f8fdb503 L |
7817 | fputs ("\t.extern\t", file); |
7818 | assemble_name (file, name); | |
7819 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n", | |
7820 | int_size_in_bytes (TREE_TYPE (decl))); | |
7821 | } | |
6773a41c | 7822 | } |
cee98a59 | 7823 | } |
65239d20 | 7824 | |
b5f5d41d | 7825 | /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */ |
cee98a59 | 7826 | |
b5f5d41d | 7827 | static void |
b4966b1b | 7828 | mips_output_filename (FILE *stream, const char *name) |
cee98a59 | 7829 | { |
8b0397a6 DJ |
7830 | /* If we are emitting DWARF-2, let dwarf2out handle the ".file" |
7831 | directives. */ | |
7832 | if (write_symbols == DWARF2_DEBUG) | |
7833 | return; | |
cafe096b | 7834 | else if (mips_output_filename_first_time) |
cee98a59 | 7835 | { |
cafe096b | 7836 | mips_output_filename_first_time = 0; |
82563d35 | 7837 | num_source_filenames += 1; |
cee98a59 | 7838 | current_function_file = name; |
3e487b21 ZW |
7839 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
7840 | output_quoted_string (stream, name); | |
7841 | putc ('\n', stream); | |
cee98a59 | 7842 | } |
3e487b21 ZW |
7843 | /* If we are emitting stabs, let dbxout.c handle this (except for |
7844 | the mips_output_filename_first_time case). */ | |
2bacb292 | 7845 | else if (write_symbols == DBX_DEBUG) |
3e487b21 | 7846 | return; |
cee98a59 | 7847 | else if (name != current_function_file |
d82783b6 | 7848 | && strcmp (name, current_function_file) != 0) |
cee98a59 | 7849 | { |
82563d35 | 7850 | num_source_filenames += 1; |
d82783b6 | 7851 | current_function_file = name; |
3e487b21 ZW |
7852 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
7853 | output_quoted_string (stream, name); | |
7854 | putc ('\n', stream); | |
cee98a59 MM |
7855 | } |
7856 | } | |
ab77a036 | 7857 | |
65239d20 | 7858 | /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
ab77a036 | 7859 | |
9a4a025a | 7860 | static void ATTRIBUTE_UNUSED |
ab77a036 RS |
7861 | mips_output_dwarf_dtprel (FILE *file, int size, rtx x) |
7862 | { | |
7863 | switch (size) | |
7864 | { | |
7865 | case 4: | |
7866 | fputs ("\t.dtprelword\t", file); | |
7867 | break; | |
7868 | ||
7869 | case 8: | |
7870 | fputs ("\t.dtpreldword\t", file); | |
7871 | break; | |
7872 | ||
7873 | default: | |
7874 | gcc_unreachable (); | |
7875 | } | |
7876 | output_addr_const (file, x); | |
7877 | fputs ("+0x8000", file); | |
7878 | } | |
7879 | ||
7880 | /* Implement TARGET_DWARF_REGISTER_SPAN. */ | |
7881 | ||
7882 | static rtx | |
7883 | mips_dwarf_register_span (rtx reg) | |
7884 | { | |
7885 | rtx high, low; | |
7886 | enum machine_mode mode; | |
7887 | ||
7888 | /* By default, GCC maps increasing register numbers to increasing | |
7889 | memory locations, but paired FPRs are always little-endian, | |
7890 | regardless of the prevailing endianness. */ | |
7891 | mode = GET_MODE (reg); | |
7892 | if (FP_REG_P (REGNO (reg)) | |
7893 | && TARGET_BIG_ENDIAN | |
7894 | && MAX_FPRS_PER_FMT > 1 | |
7895 | && GET_MODE_SIZE (mode) > UNITS_PER_FPREG) | |
7896 | { | |
7897 | gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE); | |
7898 | high = mips_subword (reg, true); | |
7899 | low = mips_subword (reg, false); | |
7900 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low)); | |
7901 | } | |
7902 | ||
7903 | return NULL_RTX; | |
7904 | } | |
65239d20 RS |
7905 | |
7906 | /* Implement ASM_OUTPUT_ASCII. */ | |
b3276c7a | 7907 | |
7dac2f89 | 7908 | void |
65239d20 | 7909 | mips_output_ascii (FILE *stream, const char *string, size_t len) |
b3276c7a GK |
7910 | { |
7911 | size_t i; | |
65239d20 | 7912 | int cur_pos; |
b3276c7a | 7913 | |
65239d20 RS |
7914 | cur_pos = 17; |
7915 | fprintf (stream, "\t.ascii\t\""); | |
7dac2f89 EC |
7916 | for (i = 0; i < len; i++) |
7917 | { | |
65239d20 | 7918 | int c; |
7dac2f89 | 7919 | |
65239d20 | 7920 | c = (unsigned char) string[i]; |
c5ff069d | 7921 | if (ISPRINT (c)) |
7dac2f89 | 7922 | { |
c5ff069d | 7923 | if (c == '\\' || c == '\"') |
7dac2f89 | 7924 | { |
c5ff069d | 7925 | putc ('\\', stream); |
7dac2f89 EC |
7926 | cur_pos++; |
7927 | } | |
c5ff069d ZW |
7928 | putc (c, stream); |
7929 | cur_pos++; | |
7930 | } | |
7931 | else | |
7932 | { | |
7933 | fprintf (stream, "\\%03o", c); | |
7934 | cur_pos += 4; | |
7dac2f89 EC |
7935 | } |
7936 | ||
7937 | if (cur_pos > 72 && i+1 < len) | |
7938 | { | |
7939 | cur_pos = 17; | |
65239d20 | 7940 | fprintf (stream, "\"\n\t.ascii\t\""); |
7dac2f89 EC |
7941 | } |
7942 | } | |
7943 | fprintf (stream, "\"\n"); | |
b3276c7a | 7944 | } |
65239d20 | 7945 | |
ab77a036 | 7946 | /* Emit either a label, .comm, or .lcomm directive. When using assembler |
65239d20 RS |
7947 | macros, mark the symbol as written so that mips_asm_output_external |
7948 | won't emit an .extern for it. STREAM is the output file, NAME is the | |
7949 | name of the symbol, INIT_STRING is the string that should be written | |
7950 | before the symbol and FINAL_STRING is the string that should be | |
7951 | written after it. FINAL_STRING is a printf format that consumes the | |
7952 | remaining arguments. */ | |
35f5add9 RS |
7953 | |
7954 | void | |
ab77a036 RS |
7955 | mips_declare_object (FILE *stream, const char *name, const char *init_string, |
7956 | const char *final_string, ...) | |
35f5add9 | 7957 | { |
ab77a036 | 7958 | va_list ap; |
35f5add9 | 7959 | |
ab77a036 RS |
7960 | fputs (init_string, stream); |
7961 | assemble_name (stream, name); | |
7962 | va_start (ap, final_string); | |
7963 | vfprintf (stream, final_string, ap); | |
7964 | va_end (ap); | |
7965 | ||
7966 | if (!TARGET_EXPLICIT_RELOCS) | |
7967 | { | |
7968 | tree name_tree = get_identifier (name); | |
7969 | TREE_ASM_WRITTEN (name_tree) = 1; | |
35f5add9 | 7970 | } |
48b2e0a7 RS |
7971 | } |
7972 | ||
7973 | /* Declare a common object of SIZE bytes using asm directive INIT_STRING. | |
7974 | NAME is the name of the object and ALIGN is the required alignment | |
7975 | in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third | |
7976 | alignment argument. */ | |
7977 | ||
7978 | void | |
7979 | mips_declare_common_object (FILE *stream, const char *name, | |
7980 | const char *init_string, | |
7981 | unsigned HOST_WIDE_INT size, | |
7982 | unsigned int align, bool takes_alignment_p) | |
7983 | { | |
7984 | if (!takes_alignment_p) | |
35f5add9 | 7985 | { |
35f5add9 RS |
7986 | size += (align / BITS_PER_UNIT) - 1; |
7987 | size -= size % (align / BITS_PER_UNIT); | |
48b2e0a7 | 7988 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
7989 | "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size); |
7990 | } | |
7991 | else | |
48b2e0a7 | 7992 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
7993 | "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n", |
7994 | size, align / BITS_PER_UNIT); | |
7995 | } | |
7996 | ||
ab77a036 RS |
7997 | /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the |
7998 | elfos.h version, but we also need to handle -muninit-const-in-rodata. */ | |
9987501f MM |
7999 | |
8000 | void | |
ab77a036 RS |
8001 | mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name, |
8002 | unsigned HOST_WIDE_INT size, | |
8003 | unsigned int align) | |
9987501f | 8004 | { |
ab77a036 RS |
8005 | /* If the target wants uninitialized const declarations in |
8006 | .rdata then don't put them in .comm. */ | |
65239d20 RS |
8007 | if (TARGET_EMBEDDED_DATA |
8008 | && TARGET_UNINIT_CONST_IN_RODATA | |
8009 | && TREE_CODE (decl) == VAR_DECL | |
8010 | && TREE_READONLY (decl) | |
ab77a036 | 8011 | && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) |
9987501f | 8012 | { |
ab77a036 RS |
8013 | if (TREE_PUBLIC (decl) && DECL_NAME (decl)) |
8014 | targetm.asm_out.globalize_label (stream, name); | |
8015 | ||
8016 | switch_to_section (readonly_data_section); | |
8017 | ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); | |
8018 | mips_declare_object (stream, name, "", | |
8019 | ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", | |
8020 | size); | |
9987501f | 8021 | } |
ab77a036 RS |
8022 | else |
8023 | mips_declare_common_object (stream, name, "\n\t.comm\t", | |
8024 | size, align, true); | |
9987501f | 8025 | } |
c1115ccd RS |
8026 | |
8027 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8028 | extern int size_directive_output; | |
8029 | ||
8030 | /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF | |
65239d20 | 8031 | definitions except that it uses mips_declare_object to emit the label. */ |
c1115ccd RS |
8032 | |
8033 | void | |
b4966b1b RS |
8034 | mips_declare_object_name (FILE *stream, const char *name, |
8035 | tree decl ATTRIBUTE_UNUSED) | |
c1115ccd RS |
8036 | { |
8037 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
82563d35 | 8038 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); |
c1115ccd RS |
8039 | #endif |
8040 | ||
82563d35 RS |
8041 | size_directive_output = 0; |
8042 | if (!flag_inhibit_size_directive && DECL_SIZE (decl)) | |
8043 | { | |
8044 | HOST_WIDE_INT size; | |
c1115ccd | 8045 | |
82563d35 RS |
8046 | size_directive_output = 1; |
8047 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8048 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
c1115ccd RS |
8049 | } |
8050 | ||
99a3237a | 8051 | mips_declare_object (stream, name, "", ":\n"); |
c1115ccd RS |
8052 | } |
8053 | ||
8054 | /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */ | |
8055 | ||
8056 | void | |
b4966b1b | 8057 | mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end) |
c1115ccd RS |
8058 | { |
8059 | const char *name; | |
8060 | ||
8061 | name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
82563d35 | 8062 | if (!flag_inhibit_size_directive |
c1115ccd | 8063 | && DECL_SIZE (decl) != 0 |
65239d20 RS |
8064 | && !at_end |
8065 | && top_level | |
c1115ccd RS |
8066 | && DECL_INITIAL (decl) == error_mark_node |
8067 | && !size_directive_output) | |
8068 | { | |
8069 | HOST_WIDE_INT size; | |
8070 | ||
8071 | size_directive_output = 1; | |
8072 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8073 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8074 | } | |
8075 | } | |
8076 | #endif | |
dbe9742d | 8077 | \f |
5f5fe6d9 RS |
8078 | /* Return the FOO in the name of the ".mdebug.FOO" section associated |
8079 | with the current ABI. */ | |
8080 | ||
8081 | static const char * | |
8082 | mips_mdebug_abi_name (void) | |
8083 | { | |
8084 | switch (mips_abi) | |
8085 | { | |
8086 | case ABI_32: | |
8087 | return "abi32"; | |
8088 | case ABI_O64: | |
8089 | return "abiO64"; | |
8090 | case ABI_N32: | |
8091 | return "abiN32"; | |
8092 | case ABI_64: | |
63553059 | 8093 | return "abi64"; |
5f5fe6d9 RS |
8094 | case ABI_EABI: |
8095 | return TARGET_64BIT ? "eabi64" : "eabi32"; | |
8096 | default: | |
8097 | gcc_unreachable (); | |
8098 | } | |
8099 | } | |
8100 | ||
ab77a036 | 8101 | /* Implement TARGET_ASM_FILE_START. */ |
108b61d5 | 8102 | |
ab77a036 RS |
8103 | static void |
8104 | mips_file_start (void) | |
108b61d5 | 8105 | { |
ab77a036 | 8106 | default_file_start (); |
108b61d5 | 8107 | |
65239d20 RS |
8108 | /* Generate a special section to describe the ABI switches used to |
8109 | produce the resultant binary. This is unnecessary on IRIX and | |
8110 | causes unwanted warnings from the native linker. */ | |
9aaa1ee8 | 8111 | if (!TARGET_IRIX6) |
ab77a036 | 8112 | { |
65239d20 RS |
8113 | /* Record the ABI itself. Modern versions of binutils encode |
8114 | this information in the ELF header flags, but GDB needs the | |
8115 | information in order to correctly debug binaries produced by | |
8116 | older binutils. See the function mips_gdbarch_init in | |
8117 | gdb/mips-tdep.c. */ | |
ab77a036 | 8118 | fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n", |
5f5fe6d9 | 8119 | mips_mdebug_abi_name ()); |
280fcbfa | 8120 | |
ab77a036 RS |
8121 | /* There is no ELF header flag to distinguish long32 forms of the |
8122 | EABI from long64 forms. Emit a special section to help tools | |
8123 | such as GDB. Do the same for o64, which is sometimes used with | |
8124 | -mlong64. */ | |
8125 | if (mips_abi == ABI_EABI || mips_abi == ABI_O64) | |
8126 | fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n" | |
8127 | "\t.previous\n", TARGET_LONG64 ? 64 : 32); | |
108b61d5 | 8128 | |
ab77a036 | 8129 | #ifdef HAVE_AS_GNU_ATTRIBUTE |
9f946bc1 RS |
8130 | { |
8131 | int attr; | |
8132 | ||
8133 | /* No floating-point operations, -mno-float. */ | |
8134 | if (TARGET_NO_FLOAT) | |
8135 | attr = 0; | |
8136 | /* Soft-float code, -msoft-float. */ | |
8137 | else if (!TARGET_HARD_FLOAT_ABI) | |
8138 | attr = 3; | |
8139 | /* Single-float code, -msingle-float. */ | |
8140 | else if (!TARGET_DOUBLE_FLOAT) | |
8141 | attr = 2; | |
8142 | /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */ | |
8143 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
8144 | attr = 4; | |
8145 | /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */ | |
8146 | else | |
8147 | attr = 1; | |
8148 | ||
8149 | fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr); | |
8150 | } | |
ab77a036 | 8151 | #endif |
280fcbfa RS |
8152 | } |
8153 | ||
65239d20 | 8154 | /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */ |
ab77a036 | 8155 | if (TARGET_ABICALLS) |
e21d5757 DJ |
8156 | { |
8157 | fprintf (asm_out_file, "\t.abicalls\n"); | |
8158 | if (TARGET_ABICALLS_PIC0) | |
8159 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
8160 | } | |
108b61d5 | 8161 | |
ab77a036 RS |
8162 | if (flag_verbose_asm) |
8163 | fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", | |
8164 | ASM_COMMENT_START, | |
65239d20 | 8165 | mips_small_data_threshold, mips_arch_info->name, mips_isa); |
108b61d5 RS |
8166 | } |
8167 | \f | |
65239d20 | 8168 | /* Make the last instruction frame-related and note that it performs |
ab77a036 | 8169 | the operation described by FRAME_PATTERN. */ |
108b61d5 | 8170 | |
ab77a036 RS |
8171 | static void |
8172 | mips_set_frame_expr (rtx frame_pattern) | |
108b61d5 | 8173 | { |
ab77a036 | 8174 | rtx insn; |
280fcbfa | 8175 | |
ab77a036 RS |
8176 | insn = get_last_insn (); |
8177 | RTX_FRAME_RELATED_P (insn) = 1; | |
8178 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8179 | frame_pattern, | |
8180 | REG_NOTES (insn)); | |
8181 | } | |
280fcbfa | 8182 | |
ab77a036 RS |
8183 | /* Return a frame-related rtx that stores REG at MEM. |
8184 | REG must be a single register. */ | |
108b61d5 | 8185 | |
ab77a036 RS |
8186 | static rtx |
8187 | mips_frame_set (rtx mem, rtx reg) | |
8188 | { | |
8189 | rtx set; | |
108b61d5 | 8190 | |
ab77a036 RS |
8191 | set = gen_rtx_SET (VOIDmode, mem, reg); |
8192 | RTX_FRAME_RELATED_P (set) = 1; | |
a38e0142 | 8193 | |
ab77a036 | 8194 | return set; |
a38e0142 | 8195 | } |
ab77a036 RS |
8196 | \f |
8197 | /* If a MIPS16e SAVE or RESTORE instruction saves or restores register | |
8198 | mips16e_s2_s8_regs[X], it must also save the registers in indexes | |
8199 | X + 1 onwards. Likewise mips16e_a0_a3_regs. */ | |
8200 | static const unsigned char mips16e_s2_s8_regs[] = { | |
8201 | 30, 23, 22, 21, 20, 19, 18 | |
8202 | }; | |
8203 | static const unsigned char mips16e_a0_a3_regs[] = { | |
8204 | 4, 5, 6, 7 | |
8205 | }; | |
a38e0142 | 8206 | |
ab77a036 RS |
8207 | /* A list of the registers that can be saved by the MIPS16e SAVE instruction, |
8208 | ordered from the uppermost in memory to the lowest in memory. */ | |
8209 | static const unsigned char mips16e_save_restore_regs[] = { | |
8210 | 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4 | |
8211 | }; | |
f833ffd4 | 8212 | |
e1260576 RS |
8213 | /* Return the index of the lowest X in the range [0, SIZE) for which |
8214 | bit REGS[X] is set in MASK. Return SIZE if there is no such X. */ | |
8215 | ||
8216 | static unsigned int | |
8217 | mips16e_find_first_register (unsigned int mask, const unsigned char *regs, | |
8218 | unsigned int size) | |
8219 | { | |
8220 | unsigned int i; | |
8221 | ||
8222 | for (i = 0; i < size; i++) | |
8223 | if (BITSET_P (mask, regs[i])) | |
8224 | break; | |
8225 | ||
8226 | return i; | |
8227 | } | |
8228 | ||
37017f4d RS |
8229 | /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR |
8230 | is the number of set bits. If *MASK_PTR contains REGS[X] for some X | |
8231 | in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same | |
8232 | is true for all indexes (X, SIZE). */ | |
e1260576 RS |
8233 | |
8234 | static void | |
8235 | mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs, | |
37017f4d | 8236 | unsigned int size, unsigned int *num_regs_ptr) |
e1260576 RS |
8237 | { |
8238 | unsigned int i; | |
8239 | ||
8240 | i = mips16e_find_first_register (*mask_ptr, regs, size); | |
8241 | for (i++; i < size; i++) | |
8242 | if (!BITSET_P (*mask_ptr, regs[i])) | |
8243 | { | |
37017f4d | 8244 | *num_regs_ptr += 1; |
e1260576 RS |
8245 | *mask_ptr |= 1 << regs[i]; |
8246 | } | |
8247 | } | |
f833ffd4 | 8248 | |
ab77a036 RS |
8249 | /* Return a simplified form of X using the register values in REG_VALUES. |
8250 | REG_VALUES[R] is the last value assigned to hard register R, or null | |
8251 | if R has not been modified. | |
cee98a59 | 8252 | |
ab77a036 | 8253 | This function is rather limited, but is good enough for our purposes. */ |
cee98a59 | 8254 | |
ab77a036 RS |
8255 | static rtx |
8256 | mips16e_collect_propagate_value (rtx x, rtx *reg_values) | |
cee98a59 | 8257 | { |
ab77a036 | 8258 | x = avoid_constant_pool_reference (x); |
cee98a59 | 8259 | |
ab77a036 | 8260 | if (UNARY_P (x)) |
9e800206 | 8261 | { |
65239d20 | 8262 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
ab77a036 RS |
8263 | return simplify_gen_unary (GET_CODE (x), GET_MODE (x), |
8264 | x0, GET_MODE (XEXP (x, 0))); | |
9e800206 RH |
8265 | } |
8266 | ||
ab77a036 | 8267 | if (ARITHMETIC_P (x)) |
e1260576 | 8268 | { |
65239d20 RS |
8269 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
8270 | rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values); | |
ab77a036 | 8271 | return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1); |
e1260576 RS |
8272 | } |
8273 | ||
ab77a036 RS |
8274 | if (REG_P (x) |
8275 | && reg_values[REGNO (x)] | |
8276 | && !rtx_unstable_p (reg_values[REGNO (x)])) | |
8277 | return reg_values[REGNO (x)]; | |
cee98a59 | 8278 | |
ab77a036 RS |
8279 | return x; |
8280 | } | |
33563487 | 8281 | |
ab77a036 RS |
8282 | /* Return true if (set DEST SRC) stores an argument register into its |
8283 | caller-allocated save slot, storing the number of that argument | |
8284 | register in *REGNO_PTR if so. REG_VALUES is as for | |
8285 | mips16e_collect_propagate_value. */ | |
cee98a59 | 8286 | |
ab77a036 RS |
8287 | static bool |
8288 | mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values, | |
8289 | unsigned int *regno_ptr) | |
8290 | { | |
8291 | unsigned int argno, regno; | |
8292 | HOST_WIDE_INT offset, required_offset; | |
8293 | rtx addr, base; | |
2bcb2ab3 | 8294 | |
ab77a036 RS |
8295 | /* Check that this is a word-mode store. */ |
8296 | if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode) | |
8297 | return false; | |
258d81a8 | 8298 | |
ab77a036 RS |
8299 | /* Check that the register being saved is an unmodified argument |
8300 | register. */ | |
8301 | regno = REGNO (src); | |
65239d20 | 8302 | if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno]) |
ab77a036 RS |
8303 | return false; |
8304 | argno = regno - GP_ARG_FIRST; | |
e88fb323 | 8305 | |
65239d20 RS |
8306 | /* Check whether the address is an appropriate stack-pointer or |
8307 | frame-pointer access. */ | |
ab77a036 RS |
8308 | addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values); |
8309 | mips_split_plus (addr, &base, &offset); | |
8310 | required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD; | |
8311 | if (base == hard_frame_pointer_rtx) | |
f374e413 | 8312 | required_offset -= cfun->machine->frame.hard_frame_pointer_offset; |
ab77a036 RS |
8313 | else if (base != stack_pointer_rtx) |
8314 | return false; | |
8315 | if (offset != required_offset) | |
8316 | return false; | |
cee98a59 | 8317 | |
ab77a036 RS |
8318 | *regno_ptr = regno; |
8319 | return true; | |
cee98a59 | 8320 | } |
b2471838 | 8321 | |
ab77a036 RS |
8322 | /* A subroutine of mips_expand_prologue, called only when generating |
8323 | MIPS16e SAVE instructions. Search the start of the function for any | |
8324 | instructions that save argument registers into their caller-allocated | |
8325 | save slots. Delete such instructions and return a value N such that | |
8326 | saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted | |
8327 | instructions redundant. */ | |
b2471838 | 8328 | |
ab77a036 RS |
8329 | static unsigned int |
8330 | mips16e_collect_argument_saves (void) | |
8331 | { | |
8332 | rtx reg_values[FIRST_PSEUDO_REGISTER]; | |
8333 | rtx insn, next, set, dest, src; | |
8334 | unsigned int nargs, regno; | |
84879759 | 8335 | |
ab77a036 RS |
8336 | push_topmost_sequence (); |
8337 | nargs = 0; | |
8338 | memset (reg_values, 0, sizeof (reg_values)); | |
8339 | for (insn = get_insns (); insn; insn = next) | |
b2471838 | 8340 | { |
ab77a036 | 8341 | next = NEXT_INSN (insn); |
006b29ab | 8342 | if (NOTE_P (insn) || DEBUG_INSN_P (insn)) |
ab77a036 | 8343 | continue; |
b2471838 | 8344 | |
ab77a036 RS |
8345 | if (!INSN_P (insn)) |
8346 | break; | |
b2471838 | 8347 | |
ab77a036 RS |
8348 | set = PATTERN (insn); |
8349 | if (GET_CODE (set) != SET) | |
8350 | break; | |
8351 | ||
8352 | dest = SET_DEST (set); | |
8353 | src = SET_SRC (set); | |
8354 | if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no)) | |
8355 | { | |
8356 | if (!BITSET_P (cfun->machine->frame.mask, regno)) | |
8357 | { | |
8358 | delete_insn (insn); | |
8359 | nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1); | |
8360 | } | |
8361 | } | |
8362 | else if (REG_P (dest) && GET_MODE (dest) == word_mode) | |
8363 | reg_values[REGNO (dest)] | |
8364 | = mips16e_collect_propagate_value (src, reg_values); | |
8365 | else | |
8366 | break; | |
b2471838 | 8367 | } |
ab77a036 | 8368 | pop_topmost_sequence (); |
b2471838 | 8369 | |
ab77a036 RS |
8370 | return nargs; |
8371 | } | |
b2471838 | 8372 | |
ab77a036 RS |
8373 | /* Return a move between register REGNO and memory location SP + OFFSET. |
8374 | Make the move a load if RESTORE_P, otherwise make it a frame-related | |
8375 | store. */ | |
67070ffe | 8376 | |
ab77a036 RS |
8377 | static rtx |
8378 | mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset, | |
8379 | unsigned int regno) | |
67070ffe | 8380 | { |
ab77a036 | 8381 | rtx reg, mem; |
1cbfdb1f | 8382 | |
ab77a036 RS |
8383 | mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset)); |
8384 | reg = gen_rtx_REG (SImode, regno); | |
8385 | return (restore_p | |
8386 | ? gen_rtx_SET (VOIDmode, reg, mem) | |
8387 | : mips_frame_set (mem, reg)); | |
1cbfdb1f RS |
8388 | } |
8389 | ||
ab77a036 RS |
8390 | /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which. |
8391 | The instruction must: | |
1cbfdb1f | 8392 | |
ab77a036 RS |
8393 | - Allocate or deallocate SIZE bytes in total; SIZE is known |
8394 | to be nonzero. | |
cee98a59 | 8395 | |
ab77a036 RS |
8396 | - Save or restore as many registers in *MASK_PTR as possible. |
8397 | The instruction saves the first registers at the top of the | |
8398 | allocated area, with the other registers below it. | |
cee98a59 | 8399 | |
ab77a036 | 8400 | - Save NARGS argument registers above the allocated area. |
b85aed9e | 8401 | |
ab77a036 | 8402 | (NARGS is always zero if RESTORE_P.) |
b85aed9e | 8403 | |
ab77a036 RS |
8404 | The SAVE and RESTORE instructions cannot save and restore all general |
8405 | registers, so there may be some registers left over for the caller to | |
8406 | handle. Destructively modify *MASK_PTR so that it contains the registers | |
8407 | that still need to be saved or restored. The caller can save these | |
8408 | registers in the memory immediately below *OFFSET_PTR, which is a | |
8409 | byte offset from the bottom of the allocated stack area. */ | |
d9870b7e | 8410 | |
ab77a036 RS |
8411 | static rtx |
8412 | mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr, | |
8413 | HOST_WIDE_INT *offset_ptr, unsigned int nargs, | |
8414 | HOST_WIDE_INT size) | |
d9870b7e | 8415 | { |
ab77a036 RS |
8416 | rtx pattern, set; |
8417 | HOST_WIDE_INT offset, top_offset; | |
8418 | unsigned int i, regno; | |
8419 | int n; | |
8cb6400c | 8420 | |
ddc4af9c | 8421 | gcc_assert (cfun->machine->frame.num_fp == 0); |
d9870b7e | 8422 | |
ab77a036 RS |
8423 | /* Calculate the number of elements in the PARALLEL. We need one element |
8424 | for the stack adjustment, one for each argument register save, and one | |
8425 | for each additional register move. */ | |
8426 | n = 1 + nargs; | |
8427 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
8428 | if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i])) | |
8429 | n++; | |
d9870b7e | 8430 | |
ab77a036 RS |
8431 | /* Create the final PARALLEL. */ |
8432 | pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n)); | |
8433 | n = 0; | |
d9870b7e | 8434 | |
ab77a036 RS |
8435 | /* Add the stack pointer adjustment. */ |
8436 | set = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8437 | plus_constant (stack_pointer_rtx, | |
8438 | restore_p ? size : -size)); | |
8439 | RTX_FRAME_RELATED_P (set) = 1; | |
8440 | XVECEXP (pattern, 0, n++) = set; | |
d9870b7e | 8441 | |
ab77a036 RS |
8442 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
8443 | top_offset = restore_p ? size : 0; | |
b85aed9e | 8444 | |
ab77a036 RS |
8445 | /* Save the arguments. */ |
8446 | for (i = 0; i < nargs; i++) | |
8447 | { | |
6e75e6e3 | 8448 | offset = top_offset + i * UNITS_PER_WORD; |
ab77a036 RS |
8449 | set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i); |
8450 | XVECEXP (pattern, 0, n++) = set; | |
8451 | } | |
d9870b7e | 8452 | |
ab77a036 RS |
8453 | /* Then fill in the other register moves. */ |
8454 | offset = top_offset; | |
8455 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
b85aed9e | 8456 | { |
ab77a036 RS |
8457 | regno = mips16e_save_restore_regs[i]; |
8458 | if (BITSET_P (*mask_ptr, regno)) | |
d9870b7e | 8459 | { |
ab77a036 RS |
8460 | offset -= UNITS_PER_WORD; |
8461 | set = mips16e_save_restore_reg (restore_p, offset, regno); | |
8462 | XVECEXP (pattern, 0, n++) = set; | |
8463 | *mask_ptr &= ~(1 << regno); | |
d9870b7e | 8464 | } |
ab77a036 | 8465 | } |
b85aed9e | 8466 | |
ab77a036 | 8467 | /* Tell the caller what offset it should use for the remaining registers. */ |
b87bc4e8 | 8468 | *offset_ptr = size + (offset - top_offset); |
d9870b7e | 8469 | |
ab77a036 | 8470 | gcc_assert (n == XVECLEN (pattern, 0)); |
8cb6400c | 8471 | |
ab77a036 | 8472 | return pattern; |
b85aed9e RS |
8473 | } |
8474 | ||
ab77a036 RS |
8475 | /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack |
8476 | pointer. Return true if PATTERN matches the kind of instruction | |
8477 | generated by mips16e_build_save_restore. If INFO is nonnull, | |
8478 | initialize it when returning true. */ | |
cee98a59 | 8479 | |
ab77a036 RS |
8480 | bool |
8481 | mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust, | |
8482 | struct mips16e_save_restore_info *info) | |
cee98a59 | 8483 | { |
37017f4d RS |
8484 | unsigned int i, nargs, mask, extra; |
8485 | HOST_WIDE_INT top_offset, save_offset, offset; | |
ab77a036 RS |
8486 | rtx set, reg, mem, base; |
8487 | int n; | |
cee98a59 | 8488 | |
ab77a036 RS |
8489 | if (!GENERATE_MIPS16E_SAVE_RESTORE) |
8490 | return false; | |
2bcb2ab3 | 8491 | |
ab77a036 RS |
8492 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
8493 | top_offset = adjust > 0 ? adjust : 0; | |
f9e4a411 | 8494 | |
ab77a036 | 8495 | /* Interpret all other members of the PARALLEL. */ |
6e75e6e3 | 8496 | save_offset = top_offset - UNITS_PER_WORD; |
ab77a036 RS |
8497 | mask = 0; |
8498 | nargs = 0; | |
8499 | i = 0; | |
8500 | for (n = 1; n < XVECLEN (pattern, 0); n++) | |
e9a25f70 | 8501 | { |
ab77a036 RS |
8502 | /* Check that we have a SET. */ |
8503 | set = XVECEXP (pattern, 0, n); | |
8504 | if (GET_CODE (set) != SET) | |
8505 | return false; | |
3c7404d3 | 8506 | |
ab77a036 RS |
8507 | /* Check that the SET is a load (if restoring) or a store |
8508 | (if saving). */ | |
8509 | mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set); | |
8510 | if (!MEM_P (mem)) | |
8511 | return false; | |
3c7404d3 | 8512 | |
ab77a036 RS |
8513 | /* Check that the address is the sum of the stack pointer and a |
8514 | possibly-zero constant offset. */ | |
8515 | mips_split_plus (XEXP (mem, 0), &base, &offset); | |
8516 | if (base != stack_pointer_rtx) | |
8517 | return false; | |
82563d35 | 8518 | |
ab77a036 RS |
8519 | /* Check that SET's other operand is a register. */ |
8520 | reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set); | |
8521 | if (!REG_P (reg)) | |
8522 | return false; | |
e9a25f70 | 8523 | |
ab77a036 | 8524 | /* Check for argument saves. */ |
6e75e6e3 | 8525 | if (offset == top_offset + nargs * UNITS_PER_WORD |
ab77a036 RS |
8526 | && REGNO (reg) == GP_ARG_FIRST + nargs) |
8527 | nargs++; | |
8528 | else if (offset == save_offset) | |
8529 | { | |
8530 | while (mips16e_save_restore_regs[i++] != REGNO (reg)) | |
8531 | if (i == ARRAY_SIZE (mips16e_save_restore_regs)) | |
8532 | return false; | |
a50f2a09 | 8533 | |
ab77a036 | 8534 | mask |= 1 << REGNO (reg); |
6e75e6e3 | 8535 | save_offset -= UNITS_PER_WORD; |
ab77a036 RS |
8536 | } |
8537 | else | |
8538 | return false; | |
e9a25f70 | 8539 | } |
ffa9d0b1 | 8540 | |
ab77a036 RS |
8541 | /* Check that the restrictions on register ranges are met. */ |
8542 | extra = 0; | |
8543 | mips16e_mask_registers (&mask, mips16e_s2_s8_regs, | |
8544 | ARRAY_SIZE (mips16e_s2_s8_regs), &extra); | |
8545 | mips16e_mask_registers (&mask, mips16e_a0_a3_regs, | |
8546 | ARRAY_SIZE (mips16e_a0_a3_regs), &extra); | |
8547 | if (extra != 0) | |
8548 | return false; | |
8549 | ||
8550 | /* Make sure that the topmost argument register is not saved twice. | |
8551 | The checks above ensure that the same is then true for the other | |
8552 | argument registers. */ | |
8553 | if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1)) | |
8554 | return false; | |
8555 | ||
8556 | /* Pass back information, if requested. */ | |
8557 | if (info) | |
6f2993e5 | 8558 | { |
ab77a036 RS |
8559 | info->nargs = nargs; |
8560 | info->mask = mask; | |
8561 | info->size = (adjust > 0 ? adjust : -adjust); | |
6f2993e5 | 8562 | } |
b85aed9e | 8563 | |
ab77a036 | 8564 | return true; |
f833ffd4 | 8565 | } |
be763023 | 8566 | |
ab77a036 RS |
8567 | /* Add a MIPS16e SAVE or RESTORE register-range argument to string S |
8568 | for the register range [MIN_REG, MAX_REG]. Return a pointer to | |
8569 | the null terminator. */ | |
be763023 | 8570 | |
ab77a036 RS |
8571 | static char * |
8572 | mips16e_add_register_range (char *s, unsigned int min_reg, | |
8573 | unsigned int max_reg) | |
8574 | { | |
8575 | if (min_reg != max_reg) | |
8576 | s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]); | |
8577 | else | |
8578 | s += sprintf (s, ",%s", reg_names[min_reg]); | |
8579 | return s; | |
be763023 RS |
8580 | } |
8581 | ||
ab77a036 RS |
8582 | /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction. |
8583 | PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */ | |
be763023 | 8584 | |
ab77a036 RS |
8585 | const char * |
8586 | mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust) | |
be763023 | 8587 | { |
ab77a036 | 8588 | static char buffer[300]; |
1de2bc2a | 8589 | |
ab77a036 RS |
8590 | struct mips16e_save_restore_info info; |
8591 | unsigned int i, end; | |
8592 | char *s; | |
1de2bc2a | 8593 | |
ab77a036 RS |
8594 | /* Parse the pattern. */ |
8595 | if (!mips16e_save_restore_pattern_p (pattern, adjust, &info)) | |
8596 | gcc_unreachable (); | |
be763023 | 8597 | |
ab77a036 RS |
8598 | /* Add the mnemonic. */ |
8599 | s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t"); | |
8600 | s += strlen (s); | |
be763023 | 8601 | |
ab77a036 RS |
8602 | /* Save the arguments. */ |
8603 | if (info.nargs > 1) | |
8604 | s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST], | |
8605 | reg_names[GP_ARG_FIRST + info.nargs - 1]); | |
8606 | else if (info.nargs == 1) | |
8607 | s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]); | |
be763023 | 8608 | |
ab77a036 RS |
8609 | /* Emit the amount of stack space to allocate or deallocate. */ |
8610 | s += sprintf (s, "%d", (int) info.size); | |
be763023 | 8611 | |
ab77a036 RS |
8612 | /* Save or restore $16. */ |
8613 | if (BITSET_P (info.mask, 16)) | |
8614 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]); | |
936b1317 | 8615 | |
ab77a036 RS |
8616 | /* Save or restore $17. */ |
8617 | if (BITSET_P (info.mask, 17)) | |
8618 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]); | |
be763023 | 8619 | |
ab77a036 RS |
8620 | /* Save or restore registers in the range $s2...$s8, which |
8621 | mips16e_s2_s8_regs lists in decreasing order. Note that this | |
8622 | is a software register range; the hardware registers are not | |
8623 | numbered consecutively. */ | |
8624 | end = ARRAY_SIZE (mips16e_s2_s8_regs); | |
8625 | i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end); | |
8626 | if (i < end) | |
8627 | s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1], | |
8628 | mips16e_s2_s8_regs[i]); | |
be763023 | 8629 | |
ab77a036 RS |
8630 | /* Save or restore registers in the range $a0...$a3. */ |
8631 | end = ARRAY_SIZE (mips16e_a0_a3_regs); | |
8632 | i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end); | |
8633 | if (i < end) | |
8634 | s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i], | |
8635 | mips16e_a0_a3_regs[end - 1]); | |
e1260576 | 8636 | |
ab77a036 | 8637 | /* Save or restore $31. */ |
293593b1 RS |
8638 | if (BITSET_P (info.mask, RETURN_ADDR_REGNUM)) |
8639 | s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]); | |
e1260576 | 8640 | |
ab77a036 | 8641 | return buffer; |
e1260576 | 8642 | } |
ab77a036 | 8643 | \f |
0c433c31 RS |
8644 | /* Return true if the current function returns its value in a floating-point |
8645 | register in MIPS16 mode. */ | |
e1260576 | 8646 | |
ab77a036 | 8647 | static bool |
0c433c31 | 8648 | mips16_cfun_returns_in_fpr_p (void) |
ab77a036 | 8649 | { |
0c433c31 RS |
8650 | tree return_type = DECL_RESULT (current_function_decl); |
8651 | return (TARGET_MIPS16 | |
8652 | && TARGET_HARD_FLOAT_ABI | |
8653 | && !aggregate_value_p (return_type, current_function_decl) | |
8654 | && mips_return_mode_in_fpr_p (DECL_MODE (return_type))); | |
8655 | } | |
e1260576 | 8656 | |
0c433c31 RS |
8657 | /* Return true if predicate PRED is true for at least one instruction. |
8658 | Cache the result in *CACHE, and assume that the result is true | |
8659 | if *CACHE is already true. */ | |
8660 | ||
8661 | static bool | |
8662 | mips_find_gp_ref (bool *cache, bool (*pred) (rtx)) | |
8663 | { | |
8664 | rtx insn; | |
8665 | ||
8666 | if (!*cache) | |
8667 | { | |
ab77a036 RS |
8668 | push_topmost_sequence (); |
8669 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
0c433c31 | 8670 | if (USEFUL_INSN_P (insn) && pred (insn)) |
65239d20 | 8671 | { |
0c433c31 | 8672 | *cache = true; |
65239d20 RS |
8673 | break; |
8674 | } | |
ab77a036 | 8675 | pop_topmost_sequence (); |
ab77a036 | 8676 | } |
0c433c31 | 8677 | return *cache; |
ab77a036 | 8678 | } |
e1260576 | 8679 | |
0c433c31 RS |
8680 | /* Return true if INSN refers to the global pointer in an "inflexible" way. |
8681 | See mips_cfun_has_inflexible_gp_ref_p for details. */ | |
7462a715 RS |
8682 | |
8683 | static bool | |
0c433c31 | 8684 | mips_insn_has_inflexible_gp_ref_p (rtx insn) |
7462a715 | 8685 | { |
0c433c31 RS |
8686 | /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE |
8687 | indicate that the target could be a traditional MIPS | |
8688 | lazily-binding stub. */ | |
8689 | return find_reg_fusage (insn, USE, pic_offset_table_rtx); | |
8690 | } | |
8691 | ||
8692 | /* Return true if the current function refers to the global pointer | |
8693 | in a way that forces $28 to be valid. This means that we can't | |
8694 | change the choice of global pointer, even for NewABI code. | |
8695 | ||
8696 | One example of this (and one which needs several checks) is that | |
8697 | $28 must be valid when calling traditional MIPS lazy-binding stubs. | |
8698 | (This restriction does not apply to PLTs.) */ | |
8699 | ||
8700 | static bool | |
8701 | mips_cfun_has_inflexible_gp_ref_p (void) | |
8702 | { | |
8703 | /* If the function has a nonlocal goto, $28 must hold the correct | |
8704 | global pointer for the target function. That is, the target | |
8705 | of the goto implicitly uses $28. */ | |
8706 | if (crtl->has_nonlocal_goto) | |
8707 | return true; | |
8708 | ||
8709 | if (TARGET_ABICALLS_PIC2) | |
8710 | { | |
8711 | /* Symbolic accesses implicitly use the global pointer unless | |
8712 | -mexplicit-relocs is in effect. JAL macros to symbolic addresses | |
8713 | might go to traditional MIPS lazy-binding stubs. */ | |
8714 | if (!TARGET_EXPLICIT_RELOCS) | |
8715 | return true; | |
8716 | ||
8717 | /* FUNCTION_PROFILER includes a JAL to _mcount, which again | |
8718 | can be lazily-bound. */ | |
8719 | if (crtl->profile) | |
8720 | return true; | |
8721 | ||
8722 | /* MIPS16 functions that return in FPRs need to call an | |
8723 | external libgcc routine. This call is only made explict | |
8724 | during mips_expand_epilogue, and it too might be lazily bound. */ | |
8725 | if (mips16_cfun_returns_in_fpr_p ()) | |
8726 | return true; | |
8727 | } | |
8728 | ||
8729 | return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p, | |
8730 | mips_insn_has_inflexible_gp_ref_p); | |
8731 | } | |
8732 | ||
8733 | /* Return true if INSN refers to the global pointer in a "flexible" way. | |
8734 | See mips_cfun_has_flexible_gp_ref_p for details. */ | |
8735 | ||
8736 | static bool | |
8737 | mips_insn_has_flexible_gp_ref_p (rtx insn) | |
8738 | { | |
8739 | return (get_attr_got (insn) != GOT_UNSET | |
8740 | || mips_small_data_pattern_p (PATTERN (insn)) | |
8741 | || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn))); | |
8742 | } | |
8743 | ||
8744 | /* Return true if the current function references the global pointer, | |
8745 | but if those references do not inherently require the global pointer | |
8746 | to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */ | |
8747 | ||
8748 | static bool | |
8749 | mips_cfun_has_flexible_gp_ref_p (void) | |
8750 | { | |
8751 | /* Reload can sometimes introduce constant pool references | |
8752 | into a function that otherwise didn't need them. For example, | |
8753 | suppose we have an instruction like: | |
8754 | ||
8755 | (set (reg:DF R1) (float:DF (reg:SI R2))) | |
8756 | ||
8757 | If R2 turns out to be a constant such as 1, the instruction may | |
8758 | have a REG_EQUAL note saying that R1 == 1.0. Reload then has | |
8759 | the option of using this constant if R2 doesn't get allocated | |
8760 | to a register. | |
8761 | ||
8762 | In cases like these, reload will have added the constant to the | |
8763 | pool but no instruction will yet refer to it. */ | |
8764 | if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool) | |
8765 | return true; | |
8766 | ||
8767 | return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p, | |
8768 | mips_insn_has_flexible_gp_ref_p); | |
7462a715 RS |
8769 | } |
8770 | ||
ab77a036 | 8771 | /* Return the register that should be used as the global pointer |
8d9d9172 RS |
8772 | within this function. Return INVALID_REGNUM if the function |
8773 | doesn't need a global pointer. */ | |
e1260576 | 8774 | |
ab77a036 RS |
8775 | static unsigned int |
8776 | mips_global_pointer (void) | |
e1260576 | 8777 | { |
ab77a036 | 8778 | unsigned int regno; |
e1260576 | 8779 | |
ab77a036 RS |
8780 | /* $gp is always available unless we're using a GOT. */ |
8781 | if (!TARGET_USE_GOT) | |
8782 | return GLOBAL_POINTER_REGNUM; | |
e1260576 | 8783 | |
0c433c31 RS |
8784 | /* If there are inflexible references to $gp, we must use the |
8785 | standard register. */ | |
8786 | if (mips_cfun_has_inflexible_gp_ref_p ()) | |
ab77a036 | 8787 | return GLOBAL_POINTER_REGNUM; |
e1260576 | 8788 | |
0c433c31 RS |
8789 | /* If there are no current references to $gp, then the only uses |
8790 | we can introduce later are those involved in long branches. */ | |
8791 | if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ()) | |
8792 | return INVALID_REGNUM; | |
e21d5757 | 8793 | |
0c433c31 RS |
8794 | /* If the global pointer is call-saved, try to use a call-clobbered |
8795 | alternative. */ | |
ab77a036 RS |
8796 | if (TARGET_CALL_SAVED_GP && current_function_is_leaf) |
8797 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) | |
8798 | if (!df_regs_ever_live_p (regno) | |
8799 | && call_really_used_regs[regno] | |
8800 | && !fixed_regs[regno] | |
8801 | && regno != PIC_FUNCTION_ADDR_REGNUM) | |
8802 | return regno; | |
e1260576 | 8803 | |
ab77a036 | 8804 | return GLOBAL_POINTER_REGNUM; |
e1260576 RS |
8805 | } |
8806 | ||
293593b1 | 8807 | /* Return true if the current function's prologue must load the global |
0c433c31 RS |
8808 | pointer value into pic_offset_table_rtx and store the same value in |
8809 | the function's cprestore slot (if any). | |
8810 | ||
8811 | One problem we have to deal with is that, when emitting GOT-based | |
8812 | position independent code, long-branch sequences will need to load | |
8813 | the address of the branch target from the GOT. We don't know until | |
8814 | the very end of compilation whether (and where) the function needs | |
8815 | long branches, so we must ensure that _any_ branch can access the | |
8816 | global pointer in some form. However, we do not want to pessimize | |
8817 | the usual case in which all branches are short. | |
8818 | ||
8819 | We handle this as follows: | |
8820 | ||
8821 | (1) During reload, we set cfun->machine->global_pointer to | |
8822 | INVALID_REGNUM if we _know_ that the current function | |
8823 | doesn't need a global pointer. This is only valid if | |
8824 | long branches don't need the GOT. | |
8825 | ||
8826 | Otherwise, we assume that we might need a global pointer | |
8827 | and pick an appropriate register. | |
8828 | ||
8829 | (2) If cfun->machine->global_pointer != INVALID_REGNUM, | |
8830 | we ensure that the global pointer is available at every | |
8831 | block boundary bar entry and exit. We do this in one of two ways: | |
8832 | ||
8833 | - If the function has a cprestore slot, we ensure that this | |
8834 | slot is valid at every branch. However, as explained in | |
8835 | point (6) below, there is no guarantee that pic_offset_table_rtx | |
8836 | itself is valid if new uses of the global pointer are introduced | |
8837 | after the first post-epilogue split. | |
8838 | ||
8839 | We guarantee that the cprestore slot is valid by loading it | |
8840 | into a fake register, CPRESTORE_SLOT_REGNUM. We then make | |
8841 | this register live at every block boundary bar function entry | |
8842 | and exit. It is then invalid to move the load (and thus the | |
8843 | preceding store) across a block boundary. | |
8844 | ||
8845 | - If the function has no cprestore slot, we guarantee that | |
8846 | pic_offset_table_rtx itself is valid at every branch. | |
8847 | ||
8848 | See mips_eh_uses for the handling of the register liveness. | |
8849 | ||
8850 | (3) During prologue and epilogue generation, we emit "ghost" | |
8851 | placeholder instructions to manipulate the global pointer. | |
8852 | ||
8853 | (4) During prologue generation, we set cfun->machine->must_initialize_gp_p | |
8854 | and cfun->machine->must_restore_gp_when_clobbered_p if we already know | |
8855 | that the function needs a global pointer. (There is no need to set | |
8856 | them earlier than this, and doing it as late as possible leads to | |
8857 | fewer false positives.) | |
8858 | ||
8859 | (5) If cfun->machine->must_initialize_gp_p is true during a | |
8860 | split_insns pass, we split the ghost instructions into real | |
8861 | instructions. These split instructions can then be optimized in | |
8862 | the usual way. Otherwise, we keep the ghost instructions intact, | |
8863 | and optimize for the case where they aren't needed. We still | |
8864 | have the option of splitting them later, if we need to introduce | |
8865 | new uses of the global pointer. | |
8866 | ||
8867 | For example, the scheduler ignores a ghost instruction that | |
8868 | stores $28 to the stack, but it handles the split form of | |
8869 | the ghost instruction as an ordinary store. | |
8870 | ||
8871 | (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p | |
8872 | is true during the first post-epilogue split_insns pass, we split | |
8873 | calls and restore_gp patterns into instructions that explicitly | |
8874 | load pic_offset_table_rtx from the cprestore slot. Otherwise, | |
8875 | we split these patterns into instructions that _don't_ load from | |
8876 | the cprestore slot. | |
8877 | ||
8878 | If cfun->machine->must_restore_gp_when_clobbered_p is true at the | |
8879 | time of the split, then any instructions that exist at that time | |
8880 | can make free use of pic_offset_table_rtx. However, if we want | |
8881 | to introduce new uses of the global pointer after the split, | |
8882 | we must explicitly load the value from the cprestore slot, since | |
8883 | pic_offset_table_rtx itself might not be valid at a given point | |
8884 | in the function. | |
8885 | ||
8886 | The idea is that we want to be able to delete redundant | |
8887 | loads from the cprestore slot in the usual case where no | |
8888 | long branches are needed. | |
8889 | ||
8890 | (7) If cfun->machine->must_initialize_gp_p is still false at the end | |
8891 | of md_reorg, we decide whether the global pointer is needed for | |
8892 | long branches. If so, we set cfun->machine->must_initialize_gp_p | |
8893 | to true and split the ghost instructions into real instructions | |
8894 | at that stage. | |
8895 | ||
8896 | Note that the ghost instructions must have a zero length for three reasons: | |
8897 | ||
8898 | - Giving the length of the underlying $gp sequence might cause | |
8899 | us to use long branches in cases where they aren't really needed. | |
8900 | ||
8901 | - They would perturb things like alignment calculations. | |
8902 | ||
8903 | - More importantly, the hazard detection in md_reorg relies on | |
8904 | empty instructions having a zero length. | |
8905 | ||
8906 | If we find a long branch and split the ghost instructions at the | |
8907 | end of md_reorg, the split could introduce more long branches. | |
8908 | That isn't a problem though, because we still do the split before | |
8909 | the final shorten_branches pass. | |
8910 | ||
8911 | This is extremely ugly, but it seems like the best compromise between | |
8912 | correctness and efficiency. */ | |
8913 | ||
8914 | bool | |
8915 | mips_must_initialize_gp_p (void) | |
8916 | { | |
8917 | return cfun->machine->must_initialize_gp_p; | |
8918 | } | |
8919 | ||
e19da24c CF |
8920 | /* Return true if REGNO is a register that is ordinarily call-clobbered |
8921 | but must nevertheless be preserved by an interrupt handler. */ | |
8922 | ||
8923 | static bool | |
8924 | mips_interrupt_extra_call_saved_reg_p (unsigned int regno) | |
8925 | { | |
8926 | if (MD_REG_P (regno)) | |
8927 | return true; | |
8928 | ||
8929 | if (TARGET_DSP && DSP_ACC_REG_P (regno)) | |
8930 | return true; | |
8931 | ||
8932 | if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p) | |
8933 | { | |
8934 | /* $0 is hard-wired. */ | |
8935 | if (regno == GP_REG_FIRST) | |
8936 | return false; | |
8937 | ||
8938 | /* The interrupt handler can treat kernel registers as | |
8939 | scratch registers. */ | |
8940 | if (KERNEL_REG_P (regno)) | |
8941 | return false; | |
8942 | ||
8943 | /* The function will return the stack pointer to its original value | |
8944 | anyway. */ | |
8945 | if (regno == STACK_POINTER_REGNUM) | |
8946 | return false; | |
8947 | ||
8948 | /* Otherwise, return true for registers that aren't ordinarily | |
8949 | call-clobbered. */ | |
8950 | return call_really_used_regs[regno]; | |
8951 | } | |
8952 | ||
8953 | return false; | |
8954 | } | |
8955 | ||
7cc003b5 RS |
8956 | /* Return true if the current function should treat register REGNO |
8957 | as call-saved. */ | |
e1260576 | 8958 | |
ab77a036 | 8959 | static bool |
7cc003b5 RS |
8960 | mips_cfun_call_saved_reg_p (unsigned int regno) |
8961 | { | |
b14ee6c9 RS |
8962 | /* If the user makes an ordinarily-call-saved register global, |
8963 | that register is no longer call-saved. */ | |
8964 | if (global_regs[regno]) | |
8965 | return false; | |
8966 | ||
e19da24c CF |
8967 | /* Interrupt handlers need to save extra registers. */ |
8968 | if (cfun->machine->interrupt_handler_p | |
8969 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
8970 | return true; | |
8971 | ||
7cc003b5 RS |
8972 | /* call_insns preserve $28 unless they explicitly say otherwise, |
8973 | so call_really_used_regs[] treats $28 as call-saved. However, | |
8974 | we want the ABI property rather than the default call_insn | |
8975 | property here. */ | |
8976 | return (regno == GLOBAL_POINTER_REGNUM | |
8977 | ? TARGET_CALL_SAVED_GP | |
8978 | : !call_really_used_regs[regno]); | |
8979 | } | |
8980 | ||
8981 | /* Return true if the function body might clobber register REGNO. | |
8982 | We know that REGNO is call-saved. */ | |
8983 | ||
8984 | static bool | |
8985 | mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno) | |
ab77a036 | 8986 | { |
7cc003b5 RS |
8987 | /* Some functions should be treated as clobbering all call-saved |
8988 | registers. */ | |
8989 | if (crtl->saves_all_registers) | |
4817c43b | 8990 | return true; |
e1260576 | 8991 | |
7cc003b5 RS |
8992 | /* DF handles cases where a register is explicitly referenced in |
8993 | the rtl. Incoming values are passed in call-clobbered registers, | |
8994 | so we can assume that any live call-saved register is set within | |
8995 | the function. */ | |
8996 | if (df_regs_ever_live_p (regno)) | |
ab77a036 | 8997 | return true; |
e1260576 | 8998 | |
7cc003b5 RS |
8999 | /* Check for registers that are clobbered by FUNCTION_PROFILER. |
9000 | These clobbers are not explicit in the rtl. */ | |
9001 | if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno)) | |
9002 | return true; | |
9003 | ||
9004 | /* If we're using a call-saved global pointer, the function's | |
9005 | prologue will need to set it up. */ | |
9006 | if (cfun->machine->global_pointer == regno) | |
ab77a036 | 9007 | return true; |
106b3d40 | 9008 | |
7cc003b5 RS |
9009 | /* The function's prologue will need to set the frame pointer if |
9010 | frame_pointer_needed. */ | |
ab77a036 RS |
9011 | if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) |
9012 | return true; | |
e1260576 | 9013 | |
7cc003b5 RS |
9014 | /* If a MIPS16 function returns a value in FPRs, its epilogue |
9015 | will need to call an external libgcc routine. This yet-to-be | |
9016 | generated call_insn will clobber $31. */ | |
293593b1 | 9017 | if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ()) |
ab77a036 | 9018 | return true; |
e1260576 | 9019 | |
e19da24c CF |
9020 | /* If REGNO is ordinarily call-clobbered, we must assume that any |
9021 | called function could modify it. */ | |
9022 | if (cfun->machine->interrupt_handler_p | |
9023 | && !current_function_is_leaf | |
9024 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
9025 | return true; | |
9026 | ||
7cc003b5 RS |
9027 | return false; |
9028 | } | |
9029 | ||
9030 | /* Return true if the current function must save register REGNO. */ | |
9031 | ||
9032 | static bool | |
9033 | mips_save_reg_p (unsigned int regno) | |
9034 | { | |
9035 | if (mips_cfun_call_saved_reg_p (regno)) | |
9036 | { | |
9037 | if (mips_cfun_might_clobber_call_saved_reg_p (regno)) | |
9038 | return true; | |
9039 | ||
9040 | /* Save both registers in an FPR pair if either one is used. This is | |
9041 | needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd | |
9042 | register to be used without the even register. */ | |
9043 | if (FP_REG_P (regno) | |
9044 | && MAX_FPRS_PER_FMT == 2 | |
9045 | && mips_cfun_might_clobber_call_saved_reg_p (regno + 1)) | |
9046 | return true; | |
9047 | } | |
9048 | ||
9049 | /* We need to save the incoming return address if __builtin_eh_return | |
9050 | is being used to set a different return address. */ | |
293593b1 | 9051 | if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) |
ab77a036 | 9052 | return true; |
e1260576 | 9053 | |
ab77a036 | 9054 | return false; |
e1260576 RS |
9055 | } |
9056 | ||
16dc5c28 | 9057 | /* Populate the current function's mips_frame_info structure. |
e1260576 | 9058 | |
ab77a036 | 9059 | MIPS stack frames look like: |
e1260576 | 9060 | |
37017f4d RS |
9061 | +-------------------------------+ |
9062 | | | | |
9063 | | incoming stack arguments | | |
9064 | | | | |
9065 | +-------------------------------+ | |
9066 | | | | |
9067 | | caller-allocated save area | | |
9068 | A | for register arguments | | |
9069 | | | | |
9070 | +-------------------------------+ <-- incoming stack pointer | |
9071 | | | | |
9072 | | callee-allocated save area | | |
9073 | B | for arguments that are | | |
9074 | | split between registers and | | |
9075 | | the stack | | |
9076 | | | | |
9077 | +-------------------------------+ <-- arg_pointer_rtx | |
9078 | | | | |
9079 | C | callee-allocated save area | | |
9080 | | for register varargs | | |
9081 | | | | |
e19da24c CF |
9082 | +-------------------------------+ <-- frame_pointer_rtx |
9083 | | | + cop0_sp_offset | |
9084 | | COP0 reg save area | + UNITS_PER_WORD | |
9085 | | | | |
9086 | +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset | |
9087 | | | + UNITS_PER_WORD | |
9088 | | accumulator save area | | |
9089 | | | | |
ba6adec4 | 9090 | +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset |
37017f4d RS |
9091 | | | + UNITS_PER_HWFPVALUE |
9092 | | FPR save area | | |
9093 | | | | |
ba6adec4 | 9094 | +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset |
37017f4d RS |
9095 | | | + UNITS_PER_WORD |
9096 | | GPR save area | | |
9097 | | | | |
ba6adec4 AN |
9098 | +-------------------------------+ <-- frame_pointer_rtx with |
9099 | | | \ -fstack-protector | |
37017f4d RS |
9100 | | local variables | | var_size |
9101 | | | / | |
9102 | +-------------------------------+ | |
9103 | | | \ | |
9104 | | $gp save area | | cprestore_size | |
9105 | | | / | |
9106 | P +-------------------------------+ <-- hard_frame_pointer_rtx for | |
ba6adec4 AN |
9107 | | | \ MIPS16 code |
9108 | | outgoing stack arguments | | | |
9109 | | | | | |
9110 | +-------------------------------+ | args_size | |
9111 | | | | | |
9112 | | caller-allocated save area | | | |
9113 | | for register arguments | | | |
9114 | | | / | |
37017f4d | 9115 | +-------------------------------+ <-- stack_pointer_rtx |
ba6adec4 AN |
9116 | frame_pointer_rtx without |
9117 | -fstack-protector | |
37017f4d RS |
9118 | hard_frame_pointer_rtx for |
9119 | non-MIPS16 code. | |
9120 | ||
9121 | At least two of A, B and C will be empty. | |
9122 | ||
9123 | Dynamic stack allocations such as alloca insert data at point P. | |
9124 | They decrease stack_pointer_rtx but leave frame_pointer_rtx and | |
9125 | hard_frame_pointer_rtx unchanged. */ | |
e1260576 | 9126 | |
16dc5c28 RS |
9127 | static void |
9128 | mips_compute_frame_info (void) | |
ab77a036 | 9129 | { |
37017f4d | 9130 | struct mips_frame_info *frame; |
16dc5c28 | 9131 | HOST_WIDE_INT offset, size; |
37017f4d | 9132 | unsigned int regno, i; |
e1260576 | 9133 | |
e19da24c CF |
9134 | /* Set this function's interrupt properties. */ |
9135 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
9136 | { | |
9137 | if (!ISA_MIPS32R2) | |
9138 | error ("the %<interrupt%> attribute requires a MIPS32r2 processor"); | |
9139 | else if (TARGET_HARD_FLOAT) | |
9140 | error ("the %<interrupt%> attribute requires %<-msoft-float%>"); | |
9141 | else if (TARGET_MIPS16) | |
9142 | error ("interrupt handlers cannot be MIPS16 functions"); | |
9143 | else | |
9144 | { | |
9145 | cfun->machine->interrupt_handler_p = true; | |
9146 | cfun->machine->use_shadow_register_set_p = | |
9147 | mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl)); | |
9148 | cfun->machine->keep_interrupts_masked_p = | |
9149 | mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl)); | |
9150 | cfun->machine->use_debug_exception_return_p = | |
9151 | mips_use_debug_exception_return_p (TREE_TYPE | |
9152 | (current_function_decl)); | |
9153 | } | |
9154 | } | |
9155 | ||
37017f4d RS |
9156 | frame = &cfun->machine->frame; |
9157 | memset (frame, 0, sizeof (*frame)); | |
16dc5c28 | 9158 | size = get_frame_size (); |
e1260576 | 9159 | |
37017f4d | 9160 | cfun->machine->global_pointer = mips_global_pointer (); |
e1260576 | 9161 | |
ba6adec4 AN |
9162 | /* The first two blocks contain the outgoing argument area and the $gp save |
9163 | slot. This area isn't needed in leaf functions, but if the | |
9164 | target-independent frame size is nonzero, we have already committed to | |
9165 | allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */ | |
9166 | if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf) | |
37017f4d RS |
9167 | { |
9168 | /* The MIPS 3.0 linker does not like functions that dynamically | |
9169 | allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it | |
9170 | looks like we are trying to create a second frame pointer to the | |
9171 | function, so allocate some stack space to make it happy. */ | |
e3b5732b | 9172 | if (cfun->calls_alloca) |
37017f4d RS |
9173 | frame->args_size = REG_PARM_STACK_SPACE (cfun->decl); |
9174 | else | |
9175 | frame->args_size = 0; | |
9176 | frame->cprestore_size = 0; | |
9177 | } | |
9178 | else | |
9179 | { | |
38173d38 | 9180 | frame->args_size = crtl->outgoing_args_size; |
ba6adec4 | 9181 | frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE; |
37017f4d RS |
9182 | } |
9183 | offset = frame->args_size + frame->cprestore_size; | |
e1260576 | 9184 | |
37017f4d RS |
9185 | /* Move above the local variables. */ |
9186 | frame->var_size = MIPS_STACK_ALIGN (size); | |
9187 | offset += frame->var_size; | |
e1260576 | 9188 | |
37017f4d | 9189 | /* Find out which GPRs we need to save. */ |
ab77a036 RS |
9190 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) |
9191 | if (mips_save_reg_p (regno)) | |
9192 | { | |
37017f4d RS |
9193 | frame->num_gp++; |
9194 | frame->mask |= 1 << (regno - GP_REG_FIRST); | |
ab77a036 | 9195 | } |
e1260576 | 9196 | |
37017f4d RS |
9197 | /* If this function calls eh_return, we must also save and restore the |
9198 | EH data registers. */ | |
e3b5732b | 9199 | if (crtl->calls_eh_return) |
37017f4d RS |
9200 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) |
9201 | { | |
9202 | frame->num_gp++; | |
9203 | frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); | |
9204 | } | |
e1260576 | 9205 | |
ab77a036 RS |
9206 | /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers: |
9207 | $a3-$a0 and $s2-$s8. If we save one register in the range, we must | |
9208 | save all later registers too. */ | |
9209 | if (GENERATE_MIPS16E_SAVE_RESTORE) | |
9210 | { | |
37017f4d RS |
9211 | mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs, |
9212 | ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp); | |
9213 | mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs, | |
9214 | ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp); | |
9215 | } | |
9216 | ||
9217 | /* Move above the GPR save area. */ | |
9218 | if (frame->num_gp > 0) | |
9219 | { | |
ddc4af9c | 9220 | offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD); |
37017f4d | 9221 | frame->gp_sp_offset = offset - UNITS_PER_WORD; |
ab77a036 | 9222 | } |
e1260576 | 9223 | |
37017f4d | 9224 | /* Find out which FPRs we need to save. This loop must iterate over |
e19da24c | 9225 | the same space as its companion in mips_for_each_saved_gpr_and_fpr. */ |
ab77a036 | 9226 | if (TARGET_HARD_FLOAT) |
37017f4d | 9227 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT) |
ab77a036 RS |
9228 | if (mips_save_reg_p (regno)) |
9229 | { | |
37017f4d RS |
9230 | frame->num_fp += MAX_FPRS_PER_FMT; |
9231 | frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST); | |
ab77a036 | 9232 | } |
e1260576 | 9233 | |
37017f4d RS |
9234 | /* Move above the FPR save area. */ |
9235 | if (frame->num_fp > 0) | |
e1260576 | 9236 | { |
ddc4af9c | 9237 | offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG); |
37017f4d | 9238 | frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; |
e1260576 RS |
9239 | } |
9240 | ||
e19da24c CF |
9241 | /* Add in space for the interrupt context information. */ |
9242 | if (cfun->machine->interrupt_handler_p) | |
9243 | { | |
9244 | /* Check HI/LO. */ | |
9245 | if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM)) | |
9246 | { | |
9247 | frame->num_acc++; | |
9248 | frame->acc_mask |= (1 << 0); | |
9249 | } | |
9250 | ||
9251 | /* Check accumulators 1, 2, 3. */ | |
9252 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
9253 | if (mips_save_reg_p (i) || mips_save_reg_p (i + 1)) | |
9254 | { | |
9255 | frame->num_acc++; | |
9256 | frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1); | |
9257 | } | |
9258 | ||
9259 | /* All interrupt context functions need space to preserve STATUS. */ | |
9260 | frame->num_cop0_regs++; | |
9261 | ||
9262 | /* If we don't keep interrupts masked, we need to save EPC. */ | |
9263 | if (!cfun->machine->keep_interrupts_masked_p) | |
9264 | frame->num_cop0_regs++; | |
9265 | } | |
9266 | ||
9267 | /* Move above the accumulator save area. */ | |
9268 | if (frame->num_acc > 0) | |
9269 | { | |
9270 | /* Each accumulator needs 2 words. */ | |
9271 | offset += frame->num_acc * 2 * UNITS_PER_WORD; | |
9272 | frame->acc_sp_offset = offset - UNITS_PER_WORD; | |
9273 | } | |
9274 | ||
9275 | /* Move above the COP0 register save area. */ | |
9276 | if (frame->num_cop0_regs > 0) | |
9277 | { | |
9278 | offset += frame->num_cop0_regs * UNITS_PER_WORD; | |
9279 | frame->cop0_sp_offset = offset - UNITS_PER_WORD; | |
9280 | } | |
9281 | ||
37017f4d RS |
9282 | /* Move above the callee-allocated varargs save area. */ |
9283 | offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size); | |
f374e413 | 9284 | frame->arg_pointer_offset = offset; |
e1260576 | 9285 | |
37017f4d | 9286 | /* Move above the callee-allocated area for pretend stack arguments. */ |
38173d38 | 9287 | offset += crtl->args.pretend_args_size; |
37017f4d RS |
9288 | frame->total_size = offset; |
9289 | ||
9290 | /* Work out the offsets of the save areas from the top of the frame. */ | |
9291 | if (frame->gp_sp_offset > 0) | |
9292 | frame->gp_save_offset = frame->gp_sp_offset - offset; | |
9293 | if (frame->fp_sp_offset > 0) | |
9294 | frame->fp_save_offset = frame->fp_sp_offset - offset; | |
e19da24c CF |
9295 | if (frame->acc_sp_offset > 0) |
9296 | frame->acc_save_offset = frame->acc_sp_offset - offset; | |
9297 | if (frame->num_cop0_regs > 0) | |
9298 | frame->cop0_save_offset = frame->cop0_sp_offset - offset; | |
ab77a036 | 9299 | |
f374e413 RS |
9300 | /* MIPS16 code offsets the frame pointer by the size of the outgoing |
9301 | arguments. This tends to increase the chances of using unextended | |
9302 | instructions for local variables and incoming arguments. */ | |
9303 | if (TARGET_MIPS16) | |
9304 | frame->hard_frame_pointer_offset = frame->args_size; | |
e1260576 RS |
9305 | } |
9306 | ||
ab77a036 RS |
9307 | /* Return the style of GP load sequence that is being used for the |
9308 | current function. */ | |
e1260576 | 9309 | |
ab77a036 RS |
9310 | enum mips_loadgp_style |
9311 | mips_current_loadgp_style (void) | |
e1260576 | 9312 | { |
8d9d9172 | 9313 | if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM) |
ab77a036 | 9314 | return LOADGP_NONE; |
e1260576 | 9315 | |
ab77a036 RS |
9316 | if (TARGET_RTP_PIC) |
9317 | return LOADGP_RTP; | |
e1260576 | 9318 | |
ab77a036 RS |
9319 | if (TARGET_ABSOLUTE_ABICALLS) |
9320 | return LOADGP_ABSOLUTE; | |
e1260576 | 9321 | |
ab77a036 RS |
9322 | return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; |
9323 | } | |
65239d20 | 9324 | |
b52b1749 | 9325 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
29c4d304 | 9326 | |
b52b1749 | 9327 | static bool |
29c4d304 RS |
9328 | mips_frame_pointer_required (void) |
9329 | { | |
9330 | /* If the function contains dynamic stack allocations, we need to | |
9331 | use the frame pointer to access the static parts of the frame. */ | |
e3b5732b | 9332 | if (cfun->calls_alloca) |
29c4d304 RS |
9333 | return true; |
9334 | ||
9335 | /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise, | |
9336 | reload may be unable to compute the address of a local variable, | |
9337 | since there is no way to add a large constant to the stack pointer | |
9338 | without using a second temporary register. */ | |
9339 | if (TARGET_MIPS16) | |
9340 | { | |
16dc5c28 | 9341 | mips_compute_frame_info (); |
29c4d304 RS |
9342 | if (!SMALL_OPERAND (cfun->machine->frame.total_size)) |
9343 | return true; | |
9344 | } | |
9345 | ||
9346 | return false; | |
9347 | } | |
9348 | ||
7b5cbb57 AS |
9349 | /* Make sure that we're not trying to eliminate to the wrong hard frame |
9350 | pointer. */ | |
9351 | ||
9352 | static bool | |
9353 | mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
9354 | { | |
9355 | return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); | |
9356 | } | |
9357 | ||
65239d20 RS |
9358 | /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer |
9359 | or argument pointer. TO is either the stack pointer or hard frame | |
9360 | pointer. */ | |
e1260576 | 9361 | |
ab77a036 RS |
9362 | HOST_WIDE_INT |
9363 | mips_initial_elimination_offset (int from, int to) | |
9364 | { | |
9365 | HOST_WIDE_INT offset; | |
9366 | ||
16dc5c28 | 9367 | mips_compute_frame_info (); |
ab77a036 | 9368 | |
ba6adec4 | 9369 | /* Set OFFSET to the offset from the end-of-prologue stack pointer. */ |
ab77a036 RS |
9370 | switch (from) |
9371 | { | |
9372 | case FRAME_POINTER_REGNUM: | |
ba6adec4 AN |
9373 | if (FRAME_GROWS_DOWNWARD) |
9374 | offset = (cfun->machine->frame.args_size | |
9375 | + cfun->machine->frame.cprestore_size | |
9376 | + cfun->machine->frame.var_size); | |
9377 | else | |
9378 | offset = 0; | |
ab77a036 RS |
9379 | break; |
9380 | ||
9381 | case ARG_POINTER_REGNUM: | |
f374e413 | 9382 | offset = cfun->machine->frame.arg_pointer_offset; |
ab77a036 RS |
9383 | break; |
9384 | ||
9385 | default: | |
9386 | gcc_unreachable (); | |
9387 | } | |
9388 | ||
f374e413 RS |
9389 | if (to == HARD_FRAME_POINTER_REGNUM) |
9390 | offset -= cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
9391 | |
9392 | return offset; | |
e1260576 | 9393 | } |
ab77a036 | 9394 | \f |
dbc90b65 | 9395 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */ |
e1260576 | 9396 | |
ab77a036 RS |
9397 | static void |
9398 | mips_extra_live_on_entry (bitmap regs) | |
9399 | { | |
dbc90b65 RS |
9400 | if (TARGET_USE_GOT) |
9401 | { | |
9402 | /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up | |
9403 | the global pointer. */ | |
9404 | if (!TARGET_ABSOLUTE_ABICALLS) | |
9405 | bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM); | |
9406 | ||
08d0963a RS |
9407 | /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of |
9408 | the global pointer. */ | |
9409 | if (TARGET_MIPS16) | |
9410 | bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM); | |
9411 | ||
dbc90b65 RS |
9412 | /* See the comment above load_call<mode> for details. */ |
9413 | bitmap_set_bit (regs, GOT_VERSION_REGNUM); | |
9414 | } | |
ab77a036 | 9415 | } |
e1260576 | 9416 | |
65239d20 RS |
9417 | /* Implement RETURN_ADDR_RTX. We do not support moving back to a |
9418 | previous frame. */ | |
ab77a036 RS |
9419 | |
9420 | rtx | |
9421 | mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) | |
e1260576 | 9422 | { |
ab77a036 RS |
9423 | if (count != 0) |
9424 | return const0_rtx; | |
e1260576 | 9425 | |
293593b1 | 9426 | return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); |
ab77a036 | 9427 | } |
e1260576 | 9428 | |
ab77a036 RS |
9429 | /* Emit code to change the current function's return address to |
9430 | ADDRESS. SCRATCH is available as a scratch register, if needed. | |
9431 | ADDRESS and SCRATCH are both word-mode GPRs. */ | |
e1260576 | 9432 | |
ab77a036 RS |
9433 | void |
9434 | mips_set_return_address (rtx address, rtx scratch) | |
9435 | { | |
9436 | rtx slot_address; | |
e1260576 | 9437 | |
293593b1 | 9438 | gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); |
ab77a036 RS |
9439 | slot_address = mips_add_offset (scratch, stack_pointer_rtx, |
9440 | cfun->machine->frame.gp_sp_offset); | |
8d0e1e43 | 9441 | mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); |
e1260576 | 9442 | } |
be763023 | 9443 | |
0c433c31 | 9444 | /* Return true if the current function has a cprestore slot. */ |
0fb5ac6f | 9445 | |
0c433c31 RS |
9446 | bool |
9447 | mips_cfun_has_cprestore_slot_p (void) | |
9448 | { | |
9449 | return (cfun->machine->global_pointer != INVALID_REGNUM | |
9450 | && cfun->machine->frame.cprestore_size > 0); | |
9451 | } | |
9452 | ||
9453 | /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the | |
9454 | cprestore slot. LOAD_P is true if the caller wants to load from | |
9455 | the cprestore slot; it is false if the caller wants to store to | |
9456 | the slot. */ | |
9457 | ||
9458 | static void | |
9459 | mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset, | |
9460 | bool load_p) | |
0fb5ac6f | 9461 | { |
08d0963a | 9462 | const struct mips_frame_info *frame; |
0fb5ac6f | 9463 | |
08d0963a | 9464 | frame = &cfun->machine->frame; |
0c433c31 RS |
9465 | /* .cprestore always uses the stack pointer instead of the frame pointer. |
9466 | We have a free choice for direct stores for non-MIPS16 functions, | |
9467 | and for MIPS16 functions whose cprestore slot is in range of the | |
9468 | stack pointer. Using the stack pointer would sometimes give more | |
9469 | (early) scheduling freedom, but using the frame pointer would | |
9470 | sometimes give more (late) scheduling freedom. It's hard to | |
9471 | predict which applies to a given function, so let's keep things | |
9472 | simple. | |
9473 | ||
9474 | Loads must always use the frame pointer in functions that call | |
9475 | alloca, and there's little benefit to using the stack pointer | |
9476 | otherwise. */ | |
9477 | if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p)) | |
9478 | { | |
9479 | *base = hard_frame_pointer_rtx; | |
9480 | *offset = frame->args_size - frame->hard_frame_pointer_offset; | |
08d0963a RS |
9481 | } |
9482 | else | |
9483 | { | |
0c433c31 RS |
9484 | *base = stack_pointer_rtx; |
9485 | *offset = frame->args_size; | |
08d0963a | 9486 | } |
0c433c31 RS |
9487 | } |
9488 | ||
9489 | /* Return true if X is the load or store address of the cprestore slot; | |
9490 | LOAD_P says which. */ | |
9491 | ||
9492 | bool | |
9493 | mips_cprestore_address_p (rtx x, bool load_p) | |
9494 | { | |
9495 | rtx given_base, required_base; | |
9496 | HOST_WIDE_INT given_offset, required_offset; | |
9497 | ||
9498 | mips_split_plus (x, &given_base, &given_offset); | |
9499 | mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p); | |
9500 | return given_base == required_base && given_offset == required_offset; | |
9501 | } | |
9502 | ||
9503 | /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are | |
9504 | going to load from it, false if we are going to store to it. | |
9505 | Use TEMP as a temporary register if need be. */ | |
9506 | ||
9507 | static rtx | |
9508 | mips_cprestore_slot (rtx temp, bool load_p) | |
9509 | { | |
9510 | rtx base; | |
9511 | HOST_WIDE_INT offset; | |
9512 | ||
9513 | mips_get_cprestore_base_and_offset (&base, &offset, load_p); | |
08d0963a RS |
9514 | return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset)); |
9515 | } | |
9516 | ||
0c433c31 RS |
9517 | /* Emit instructions to save global pointer value GP into cprestore |
9518 | slot MEM. OFFSET is the offset that MEM applies to the base register. | |
9519 | ||
9520 | MEM may not be a legitimate address. If it isn't, TEMP is a | |
9521 | temporary register that can be used, otherwise it is a SCRATCH. */ | |
9522 | ||
9523 | void | |
9524 | mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp) | |
9525 | { | |
9526 | if (TARGET_CPRESTORE_DIRECTIVE) | |
9527 | { | |
9528 | gcc_assert (gp == pic_offset_table_rtx); | |
9529 | emit_insn (gen_cprestore (mem, offset)); | |
9530 | } | |
9531 | else | |
9532 | mips_emit_move (mips_cprestore_slot (temp, false), gp); | |
9533 | } | |
9534 | ||
08d0963a | 9535 | /* Restore $gp from its save slot, using TEMP as a temporary base register |
0c433c31 RS |
9536 | if need be. This function is for o32 and o64 abicalls only. |
9537 | ||
9538 | See mips_must_initialize_gp_p for details about how we manage the | |
9539 | global pointer. */ | |
08d0963a RS |
9540 | |
9541 | void | |
0c433c31 | 9542 | mips_restore_gp_from_cprestore_slot (rtx temp) |
08d0963a | 9543 | { |
0c433c31 | 9544 | gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed); |
f833ffd4 | 9545 | |
0c433c31 | 9546 | if (!cfun->machine->must_restore_gp_when_clobbered_p) |
c870c233 RS |
9547 | { |
9548 | emit_note (NOTE_INSN_DELETED); | |
9549 | return; | |
9550 | } | |
e21d5757 | 9551 | |
08d0963a RS |
9552 | if (TARGET_MIPS16) |
9553 | { | |
0c433c31 | 9554 | mips_emit_move (temp, mips_cprestore_slot (temp, true)); |
08d0963a RS |
9555 | mips_emit_move (pic_offset_table_rtx, temp); |
9556 | } | |
9557 | else | |
0c433c31 | 9558 | mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true)); |
ab77a036 RS |
9559 | if (!TARGET_EXPLICIT_RELOCS) |
9560 | emit_insn (gen_blockage ()); | |
9561 | } | |
9562 | \f | |
9563 | /* A function to save or store a register. The first argument is the | |
9564 | register and the second is the stack slot. */ | |
9565 | typedef void (*mips_save_restore_fn) (rtx, rtx); | |
cee98a59 | 9566 | |
ab77a036 RS |
9567 | /* Use FN to save or restore register REGNO. MODE is the register's |
9568 | mode and OFFSET is the offset of its save slot from the current | |
9569 | stack pointer. */ | |
e1260576 | 9570 | |
ab77a036 RS |
9571 | static void |
9572 | mips_save_restore_reg (enum machine_mode mode, int regno, | |
9573 | HOST_WIDE_INT offset, mips_save_restore_fn fn) | |
9574 | { | |
9575 | rtx mem; | |
e1260576 | 9576 | |
ab77a036 | 9577 | mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset)); |
ab77a036 RS |
9578 | fn (gen_rtx_REG (mode, regno), mem); |
9579 | } | |
e1260576 | 9580 | |
e19da24c CF |
9581 | /* Call FN for each accumlator that is saved by the current function. |
9582 | SP_OFFSET is the offset of the current stack pointer from the start | |
9583 | of the frame. */ | |
9584 | ||
9585 | static void | |
9586 | mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn) | |
9587 | { | |
9588 | HOST_WIDE_INT offset; | |
9589 | int regno; | |
9590 | ||
9591 | offset = cfun->machine->frame.acc_sp_offset - sp_offset; | |
9592 | if (BITSET_P (cfun->machine->frame.acc_mask, 0)) | |
9593 | { | |
9594 | mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn); | |
9595 | offset -= UNITS_PER_WORD; | |
9596 | mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn); | |
9597 | offset -= UNITS_PER_WORD; | |
9598 | } | |
9599 | ||
9600 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) | |
9601 | if (BITSET_P (cfun->machine->frame.acc_mask, | |
9602 | ((regno - DSP_ACC_REG_FIRST) / 2) + 1)) | |
9603 | { | |
9604 | mips_save_restore_reg (word_mode, regno, offset, fn); | |
9605 | offset -= UNITS_PER_WORD; | |
9606 | } | |
9607 | } | |
9608 | ||
ab77a036 RS |
9609 | /* Call FN for each register that is saved by the current function. |
9610 | SP_OFFSET is the offset of the current stack pointer from the start | |
9611 | of the frame. */ | |
a94dbf2c | 9612 | |
ab77a036 | 9613 | static void |
e19da24c CF |
9614 | mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, |
9615 | mips_save_restore_fn fn) | |
ab77a036 RS |
9616 | { |
9617 | enum machine_mode fpr_mode; | |
9618 | HOST_WIDE_INT offset; | |
9619 | int regno; | |
2bcb2ab3 | 9620 | |
ab77a036 RS |
9621 | /* Save registers starting from high to low. The debuggers prefer at least |
9622 | the return register be stored at func+4, and also it allows us not to | |
9623 | need a nop in the epilogue if at least one register is reloaded in | |
9624 | addition to return address. */ | |
9625 | offset = cfun->machine->frame.gp_sp_offset - sp_offset; | |
9626 | for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) | |
9627 | if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) | |
9628 | { | |
c376dbfb DD |
9629 | /* Record the ra offset for use by mips_function_profiler. */ |
9630 | if (regno == RETURN_ADDR_REGNUM) | |
9631 | cfun->machine->frame.ra_fp_offset = offset + sp_offset; | |
6e75e6e3 RS |
9632 | mips_save_restore_reg (word_mode, regno, offset, fn); |
9633 | offset -= UNITS_PER_WORD; | |
ab77a036 RS |
9634 | } |
9635 | ||
9636 | /* This loop must iterate over the same space as its companion in | |
16dc5c28 | 9637 | mips_compute_frame_info. */ |
ab77a036 RS |
9638 | offset = cfun->machine->frame.fp_sp_offset - sp_offset; |
9639 | fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); | |
65239d20 | 9640 | for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; |
ab77a036 RS |
9641 | regno >= FP_REG_FIRST; |
9642 | regno -= MAX_FPRS_PER_FMT) | |
9643 | if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) | |
9644 | { | |
9645 | mips_save_restore_reg (fpr_mode, regno, offset, fn); | |
9646 | offset -= GET_MODE_SIZE (fpr_mode); | |
9647 | } | |
9648 | } | |
0c433c31 RS |
9649 | |
9650 | /* Return true if a move between register REGNO and its save slot (MEM) | |
9651 | can be done in a single move. LOAD_P is true if we are loading | |
9652 | from the slot, false if we are storing to it. */ | |
9653 | ||
9654 | static bool | |
9655 | mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p) | |
9656 | { | |
9657 | /* There is a specific MIPS16 instruction for saving $31 to the stack. */ | |
293593b1 | 9658 | if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM) |
0c433c31 RS |
9659 | return false; |
9660 | ||
9661 | return mips_secondary_reload_class (REGNO_REG_CLASS (regno), | |
9662 | GET_MODE (mem), mem, load_p) == NO_REGS; | |
9663 | } | |
9664 | ||
9665 | /* Emit a move from SRC to DEST, given that one of them is a register | |
9666 | save slot and that the other is a register. TEMP is a temporary | |
9667 | GPR of the same mode that is available if need be. */ | |
9668 | ||
9669 | void | |
9670 | mips_emit_save_slot_move (rtx dest, rtx src, rtx temp) | |
9671 | { | |
9672 | unsigned int regno; | |
9673 | rtx mem; | |
9674 | ||
9675 | if (REG_P (src)) | |
9676 | { | |
9677 | regno = REGNO (src); | |
9678 | mem = dest; | |
9679 | } | |
9680 | else | |
9681 | { | |
9682 | regno = REGNO (dest); | |
9683 | mem = src; | |
9684 | } | |
9685 | ||
9686 | if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ()) | |
9687 | { | |
9688 | /* We don't yet know whether we'll need this instruction or not. | |
9689 | Postpone the decision by emitting a ghost move. This move | |
9690 | is specifically not frame-related; only the split version is. */ | |
9691 | if (TARGET_64BIT) | |
9692 | emit_insn (gen_move_gpdi (dest, src)); | |
9693 | else | |
9694 | emit_insn (gen_move_gpsi (dest, src)); | |
9695 | return; | |
9696 | } | |
9697 | ||
9698 | if (regno == HI_REGNUM) | |
9699 | { | |
9700 | if (REG_P (dest)) | |
9701 | { | |
9702 | mips_emit_move (temp, src); | |
9703 | if (TARGET_64BIT) | |
9704 | emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST), | |
9705 | temp, gen_rtx_REG (DImode, LO_REGNUM))); | |
9706 | else | |
9707 | emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST), | |
9708 | temp, gen_rtx_REG (SImode, LO_REGNUM))); | |
9709 | } | |
9710 | else | |
9711 | { | |
9712 | if (TARGET_64BIT) | |
9713 | emit_insn (gen_mfhidi_ti (temp, | |
9714 | gen_rtx_REG (TImode, MD_REG_FIRST))); | |
9715 | else | |
9716 | emit_insn (gen_mfhisi_di (temp, | |
9717 | gen_rtx_REG (DImode, MD_REG_FIRST))); | |
9718 | mips_emit_move (dest, temp); | |
9719 | } | |
9720 | } | |
9721 | else if (mips_direct_save_slot_move_p (regno, mem, mem == src)) | |
9722 | mips_emit_move (dest, src); | |
9723 | else | |
9724 | { | |
9725 | gcc_assert (!reg_overlap_mentioned_p (dest, temp)); | |
9726 | mips_emit_move (temp, src); | |
9727 | mips_emit_move (dest, temp); | |
9728 | } | |
9729 | if (MEM_P (dest)) | |
9730 | mips_set_frame_expr (mips_frame_set (dest, src)); | |
9731 | } | |
ab77a036 RS |
9732 | \f |
9733 | /* If we're generating n32 or n64 abicalls, and the current function | |
9734 | does not use $28 as its global pointer, emit a cplocal directive. | |
9735 | Use pic_offset_table_rtx as the argument to the directive. */ | |
9736 | ||
9737 | static void | |
9738 | mips_output_cplocal (void) | |
9739 | { | |
9740 | if (!TARGET_EXPLICIT_RELOCS | |
0c433c31 | 9741 | && mips_must_initialize_gp_p () |
ab77a036 RS |
9742 | && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM) |
9743 | output_asm_insn (".cplocal %+", 0); | |
9744 | } | |
9745 | ||
65239d20 | 9746 | /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */ |
ab77a036 RS |
9747 | |
9748 | static void | |
9749 | mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9750 | { | |
9751 | const char *fnname; | |
ab77a036 RS |
9752 | |
9753 | #ifdef SDB_DEBUGGING_INFO | |
9754 | if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) | |
9755 | SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); | |
9756 | #endif | |
9757 | ||
65239d20 RS |
9758 | /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle |
9759 | floating-point arguments. */ | |
ab77a036 RS |
9760 | if (TARGET_MIPS16 |
9761 | && TARGET_HARD_FLOAT_ABI | |
38173d38 | 9762 | && crtl->args.info.fp_code != 0) |
65239d20 | 9763 | mips16_build_function_stub (); |
ab77a036 | 9764 | |
b2b61607 RS |
9765 | /* Get the function name the same way that toplev.c does before calling |
9766 | assemble_start_function. This is needed so that the name used here | |
9767 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
9768 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
9769 | mips_start_function_definition (fnname, TARGET_MIPS16); | |
f833ffd4 | 9770 | |
65239d20 | 9771 | /* Output MIPS-specific frame information. */ |
ab77a036 RS |
9772 | if (!flag_inhibit_size_directive) |
9773 | { | |
65239d20 RS |
9774 | const struct mips_frame_info *frame; |
9775 | ||
9776 | frame = &cfun->machine->frame; | |
9777 | ||
9778 | /* .frame FRAMEREG, FRAMESIZE, RETREG. */ | |
ab77a036 RS |
9779 | fprintf (file, |
9780 | "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t" | |
65239d20 RS |
9781 | "# vars= " HOST_WIDE_INT_PRINT_DEC |
9782 | ", regs= %d/%d" | |
ab77a036 RS |
9783 | ", args= " HOST_WIDE_INT_PRINT_DEC |
9784 | ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", | |
65239d20 RS |
9785 | reg_names[frame_pointer_needed |
9786 | ? HARD_FRAME_POINTER_REGNUM | |
9787 | : STACK_POINTER_REGNUM], | |
f374e413 | 9788 | (frame_pointer_needed |
65239d20 RS |
9789 | ? frame->total_size - frame->hard_frame_pointer_offset |
9790 | : frame->total_size), | |
293593b1 | 9791 | reg_names[RETURN_ADDR_REGNUM], |
65239d20 RS |
9792 | frame->var_size, |
9793 | frame->num_gp, frame->num_fp, | |
9794 | frame->args_size, | |
9795 | frame->cprestore_size); | |
be763023 | 9796 | |
65239d20 | 9797 | /* .mask MASK, OFFSET. */ |
ab77a036 | 9798 | fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", |
65239d20 | 9799 | frame->mask, frame->gp_save_offset); |
d8d5b1e1 | 9800 | |
65239d20 RS |
9801 | /* .fmask MASK, OFFSET. */ |
9802 | fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", | |
9803 | frame->fmask, frame->fp_save_offset); | |
ab77a036 RS |
9804 | } |
9805 | ||
65239d20 RS |
9806 | /* Handle the initialization of $gp for SVR4 PIC, if applicable. |
9807 | Also emit the ".set noreorder; .set nomacro" sequence for functions | |
9808 | that need it. */ | |
0c433c31 RS |
9809 | if (mips_must_initialize_gp_p () |
9810 | && mips_current_loadgp_style () == LOADGP_OLDABI) | |
ab77a036 | 9811 | { |
08d0963a RS |
9812 | if (TARGET_MIPS16) |
9813 | { | |
9814 | /* This is a fixed-form sequence. The position of the | |
9815 | first two instructions is important because of the | |
9816 | way _gp_disp is defined. */ | |
9817 | output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); | |
9818 | output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); | |
9819 | output_asm_insn ("sll\t$2,16", 0); | |
9820 | output_asm_insn ("addu\t$2,$3", 0); | |
9821 | } | |
ab77a036 | 9822 | else |
cf5fb4b0 RS |
9823 | { |
9824 | /* .cpload must be in a .set noreorder but not a | |
9825 | .set nomacro block. */ | |
9826 | mips_push_asm_switch (&mips_noreorder); | |
9827 | output_asm_insn (".cpload\t%^", 0); | |
9828 | if (!cfun->machine->all_noreorder_p) | |
9829 | mips_pop_asm_switch (&mips_noreorder); | |
9830 | else | |
9831 | mips_push_asm_switch (&mips_nomacro); | |
9832 | } | |
ab77a036 RS |
9833 | } |
9834 | else if (cfun->machine->all_noreorder_p) | |
cf5fb4b0 RS |
9835 | { |
9836 | mips_push_asm_switch (&mips_noreorder); | |
9837 | mips_push_asm_switch (&mips_nomacro); | |
9838 | } | |
ab77a036 RS |
9839 | |
9840 | /* Tell the assembler which register we're using as the global | |
9841 | pointer. This is needed for thunks, since they can use either | |
9842 | explicit relocs or assembler macros. */ | |
9843 | mips_output_cplocal (); | |
cee98a59 | 9844 | } |
ab77a036 | 9845 | |
65239d20 | 9846 | /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */ |
b5e9dd03 | 9847 | |
08c148a8 | 9848 | static void |
b4966b1b RS |
9849 | mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
9850 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
cee98a59 | 9851 | { |
b2b61607 RS |
9852 | const char *fnname; |
9853 | ||
b85aed9e | 9854 | /* Reinstate the normal $gp. */ |
6fb5fa3c | 9855 | SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM); |
b85aed9e RS |
9856 | mips_output_cplocal (); |
9857 | ||
6f2993e5 RS |
9858 | if (cfun->machine->all_noreorder_p) |
9859 | { | |
cf5fb4b0 RS |
9860 | mips_pop_asm_switch (&mips_nomacro); |
9861 | mips_pop_asm_switch (&mips_noreorder); | |
6f2993e5 RS |
9862 | } |
9863 | ||
b2b61607 RS |
9864 | /* Get the function name the same way that toplev.c does before calling |
9865 | assemble_start_function. This is needed so that the name used here | |
9866 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
9867 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
9868 | mips_end_function_definition (fnname); | |
cee98a59 | 9869 | } |
0fb5ac6f | 9870 | \f |
ab77a036 | 9871 | /* Save register REG to MEM. Make the instruction frame-related. */ |
be763023 RS |
9872 | |
9873 | static void | |
ab77a036 | 9874 | mips_save_reg (rtx reg, rtx mem) |
be763023 | 9875 | { |
ab77a036 | 9876 | if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) |
be763023 | 9877 | { |
ab77a036 RS |
9878 | rtx x1, x2; |
9879 | ||
9880 | if (mips_split_64bit_move_p (mem, reg)) | |
9881 | mips_split_doubleword_move (mem, reg); | |
9882 | else | |
9883 | mips_emit_move (mem, reg); | |
9884 | ||
65239d20 RS |
9885 | x1 = mips_frame_set (mips_subword (mem, false), |
9886 | mips_subword (reg, false)); | |
9887 | x2 = mips_frame_set (mips_subword (mem, true), | |
9888 | mips_subword (reg, true)); | |
ab77a036 | 9889 | mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2))); |
be763023 RS |
9890 | } |
9891 | else | |
0c433c31 | 9892 | mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg))); |
be763023 RS |
9893 | } |
9894 | ||
ab77a036 | 9895 | /* The __gnu_local_gp symbol. */ |
be763023 | 9896 | |
ab77a036 | 9897 | static GTY(()) rtx mips_gnu_local_gp; |
0fb5ac6f | 9898 | |
ab77a036 RS |
9899 | /* If we're generating n32 or n64 abicalls, emit instructions |
9900 | to set up the global pointer. */ | |
0fb5ac6f | 9901 | |
ab77a036 RS |
9902 | static void |
9903 | mips_emit_loadgp (void) | |
9904 | { | |
5557aad2 | 9905 | rtx addr, offset, incoming_address, base, index, pic_reg; |
d33289b2 | 9906 | |
08d0963a | 9907 | pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; |
ab77a036 | 9908 | switch (mips_current_loadgp_style ()) |
a38e0142 | 9909 | { |
ab77a036 RS |
9910 | case LOADGP_ABSOLUTE: |
9911 | if (mips_gnu_local_gp == NULL) | |
9912 | { | |
9913 | mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); | |
9914 | SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; | |
9915 | } | |
5557aad2 RS |
9916 | emit_insn (Pmode == SImode |
9917 | ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp) | |
9918 | : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp)); | |
ab77a036 | 9919 | break; |
a38e0142 | 9920 | |
08d0963a RS |
9921 | case LOADGP_OLDABI: |
9922 | /* Added by mips_output_function_prologue. */ | |
9923 | break; | |
9924 | ||
ab77a036 RS |
9925 | case LOADGP_NEWABI: |
9926 | addr = XEXP (DECL_RTL (current_function_decl), 0); | |
9927 | offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP); | |
9928 | incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
5557aad2 RS |
9929 | emit_insn (Pmode == SImode |
9930 | ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address) | |
9931 | : gen_loadgp_newabi_di (pic_reg, offset, incoming_address)); | |
ab77a036 | 9932 | break; |
a38e0142 | 9933 | |
ab77a036 RS |
9934 | case LOADGP_RTP: |
9935 | base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE)); | |
9936 | index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX)); | |
5557aad2 RS |
9937 | emit_insn (Pmode == SImode |
9938 | ? gen_loadgp_rtp_si (pic_reg, base, index) | |
9939 | : gen_loadgp_rtp_di (pic_reg, base, index)); | |
ab77a036 RS |
9940 | break; |
9941 | ||
9942 | default: | |
de9f679d | 9943 | return; |
ab77a036 | 9944 | } |
08d0963a RS |
9945 | |
9946 | if (TARGET_MIPS16) | |
9947 | emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg)); | |
9948 | ||
de9f679d RS |
9949 | /* Emit a blockage if there are implicit uses of the GP register. |
9950 | This includes profiled functions, because FUNCTION_PROFILE uses | |
9951 | a jal macro. */ | |
9952 | if (!TARGET_EXPLICIT_RELOCS || crtl->profile) | |
9953 | emit_insn (gen_loadgp_blockage ()); | |
ab77a036 RS |
9954 | } |
9955 | ||
e19da24c CF |
9956 | /* A for_each_rtx callback. Stop the search if *X is a kernel register. */ |
9957 | ||
9958 | static int | |
9959 | mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED) | |
9960 | { | |
47ac44d6 | 9961 | return REG_P (*x) && KERNEL_REG_P (REGNO (*x)); |
e19da24c CF |
9962 | } |
9963 | ||
65239d20 | 9964 | /* Expand the "prologue" pattern. */ |
ab77a036 RS |
9965 | |
9966 | void | |
9967 | mips_expand_prologue (void) | |
9968 | { | |
65239d20 | 9969 | const struct mips_frame_info *frame; |
ab77a036 RS |
9970 | HOST_WIDE_INT size; |
9971 | unsigned int nargs; | |
9972 | rtx insn; | |
9973 | ||
8d9d9172 | 9974 | if (cfun->machine->global_pointer != INVALID_REGNUM) |
0c433c31 RS |
9975 | { |
9976 | /* Check whether an insn uses pic_offset_table_rtx, either explicitly | |
9977 | or implicitly. If so, we can commit to using a global pointer | |
9978 | straight away, otherwise we need to defer the decision. */ | |
9979 | if (mips_cfun_has_inflexible_gp_ref_p () | |
9980 | || mips_cfun_has_flexible_gp_ref_p ()) | |
9981 | { | |
9982 | cfun->machine->must_initialize_gp_p = true; | |
9983 | cfun->machine->must_restore_gp_when_clobbered_p = true; | |
9984 | } | |
9985 | ||
9986 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); | |
9987 | } | |
ab77a036 | 9988 | |
65239d20 RS |
9989 | frame = &cfun->machine->frame; |
9990 | size = frame->total_size; | |
ab77a036 | 9991 | |
a11e0df4 | 9992 | if (flag_stack_usage_info) |
d3c12306 EB |
9993 | current_function_static_stack_size = size; |
9994 | ||
ab77a036 RS |
9995 | /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP |
9996 | bytes beforehand; this is enough to cover the register save area | |
9997 | without going out of range. */ | |
e19da24c CF |
9998 | if (((frame->mask | frame->fmask | frame->acc_mask) != 0) |
9999 | || frame->num_cop0_regs > 0) | |
ab77a036 RS |
10000 | { |
10001 | HOST_WIDE_INT step1; | |
10002 | ||
10003 | step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); | |
ab77a036 RS |
10004 | if (GENERATE_MIPS16E_SAVE_RESTORE) |
10005 | { | |
10006 | HOST_WIDE_INT offset; | |
10007 | unsigned int mask, regno; | |
10008 | ||
10009 | /* Try to merge argument stores into the save instruction. */ | |
10010 | nargs = mips16e_collect_argument_saves (); | |
10011 | ||
10012 | /* Build the save instruction. */ | |
65239d20 | 10013 | mask = frame->mask; |
ab77a036 RS |
10014 | insn = mips16e_build_save_restore (false, &mask, &offset, |
10015 | nargs, step1); | |
10016 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
10017 | size -= step1; | |
10018 | ||
10019 | /* Check if we need to save other registers. */ | |
10020 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
10021 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
10022 | { | |
6e75e6e3 RS |
10023 | offset -= UNITS_PER_WORD; |
10024 | mips_save_restore_reg (word_mode, regno, | |
10025 | offset, mips_save_reg); | |
ab77a036 RS |
10026 | } |
10027 | } | |
10028 | else | |
10029 | { | |
e19da24c CF |
10030 | if (cfun->machine->interrupt_handler_p) |
10031 | { | |
10032 | HOST_WIDE_INT offset; | |
10033 | rtx mem; | |
10034 | ||
10035 | /* If this interrupt is using a shadow register set, we need to | |
10036 | get the stack pointer from the previous register set. */ | |
10037 | if (cfun->machine->use_shadow_register_set_p) | |
10038 | emit_insn (gen_mips_rdpgpr (stack_pointer_rtx, | |
10039 | stack_pointer_rtx)); | |
10040 | ||
10041 | if (!cfun->machine->keep_interrupts_masked_p) | |
10042 | { | |
10043 | /* Move from COP0 Cause to K0. */ | |
10044 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM), | |
10045 | gen_rtx_REG (SImode, | |
10046 | COP0_CAUSE_REG_NUM))); | |
10047 | /* Move from COP0 EPC to K1. */ | |
10048 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
10049 | gen_rtx_REG (SImode, | |
10050 | COP0_EPC_REG_NUM))); | |
10051 | } | |
10052 | ||
10053 | /* Allocate the first part of the frame. */ | |
10054 | insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, | |
10055 | GEN_INT (-step1)); | |
10056 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
10057 | size -= step1; | |
10058 | ||
10059 | /* Start at the uppermost location for saving. */ | |
10060 | offset = frame->cop0_sp_offset - size; | |
10061 | if (!cfun->machine->keep_interrupts_masked_p) | |
10062 | { | |
10063 | /* Push EPC into its stack slot. */ | |
10064 | mem = gen_frame_mem (word_mode, | |
10065 | plus_constant (stack_pointer_rtx, | |
10066 | offset)); | |
10067 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
10068 | offset -= UNITS_PER_WORD; | |
10069 | } | |
10070 | ||
10071 | /* Move from COP0 Status to K1. */ | |
10072 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
10073 | gen_rtx_REG (SImode, | |
10074 | COP0_STATUS_REG_NUM))); | |
10075 | ||
10076 | /* Right justify the RIPL in k0. */ | |
10077 | if (!cfun->machine->keep_interrupts_masked_p) | |
10078 | emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), | |
10079 | gen_rtx_REG (SImode, K0_REG_NUM), | |
10080 | GEN_INT (CAUSE_IPL))); | |
10081 | ||
10082 | /* Push Status into its stack slot. */ | |
10083 | mem = gen_frame_mem (word_mode, | |
10084 | plus_constant (stack_pointer_rtx, offset)); | |
10085 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
10086 | offset -= UNITS_PER_WORD; | |
10087 | ||
10088 | /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ | |
10089 | if (!cfun->machine->keep_interrupts_masked_p) | |
10090 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10091 | GEN_INT (6), | |
10092 | GEN_INT (SR_IPL), | |
10093 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10094 | ||
10095 | if (!cfun->machine->keep_interrupts_masked_p) | |
10096 | /* Enable interrupts by clearing the KSU ERL and EXL bits. | |
10097 | IE is already the correct value, so we don't have to do | |
10098 | anything explicit. */ | |
10099 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10100 | GEN_INT (4), | |
10101 | GEN_INT (SR_EXL), | |
10102 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
10103 | else | |
10104 | /* Disable interrupts by clearing the KSU, ERL, EXL, | |
10105 | and IE bits. */ | |
10106 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10107 | GEN_INT (5), | |
10108 | GEN_INT (SR_IE), | |
10109 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
10110 | } | |
10111 | else | |
10112 | { | |
10113 | insn = gen_add3_insn (stack_pointer_rtx, | |
10114 | stack_pointer_rtx, | |
10115 | GEN_INT (-step1)); | |
10116 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
10117 | size -= step1; | |
10118 | } | |
10119 | mips_for_each_saved_acc (size, mips_save_reg); | |
10120 | mips_for_each_saved_gpr_and_fpr (size, mips_save_reg); | |
ab77a036 RS |
10121 | } |
10122 | } | |
10123 | ||
10124 | /* Allocate the rest of the frame. */ | |
10125 | if (size > 0) | |
10126 | { | |
10127 | if (SMALL_OPERAND (-size)) | |
10128 | RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10129 | stack_pointer_rtx, | |
10130 | GEN_INT (-size)))) = 1; | |
10131 | else | |
10132 | { | |
10133 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size)); | |
10134 | if (TARGET_MIPS16) | |
10135 | { | |
10136 | /* There are no instructions to add or subtract registers | |
10137 | from the stack pointer, so use the frame pointer as a | |
10138 | temporary. We should always be using a frame pointer | |
10139 | in this case anyway. */ | |
10140 | gcc_assert (frame_pointer_needed); | |
10141 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
10142 | emit_insn (gen_sub3_insn (hard_frame_pointer_rtx, | |
10143 | hard_frame_pointer_rtx, | |
10144 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10145 | mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx); | |
10146 | } | |
10147 | else | |
10148 | emit_insn (gen_sub3_insn (stack_pointer_rtx, | |
10149 | stack_pointer_rtx, | |
10150 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10151 | ||
10152 | /* Describe the combined effect of the previous instructions. */ | |
10153 | mips_set_frame_expr | |
10154 | (gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
10155 | plus_constant (stack_pointer_rtx, -size))); | |
10156 | } | |
10157 | } | |
10158 | ||
f374e413 | 10159 | /* Set up the frame pointer, if we're using one. */ |
ab77a036 RS |
10160 | if (frame_pointer_needed) |
10161 | { | |
f374e413 RS |
10162 | HOST_WIDE_INT offset; |
10163 | ||
65239d20 | 10164 | offset = frame->hard_frame_pointer_offset; |
f374e413 | 10165 | if (offset == 0) |
ab77a036 | 10166 | { |
f374e413 RS |
10167 | insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); |
10168 | RTX_FRAME_RELATED_P (insn) = 1; | |
10169 | } | |
10170 | else if (SMALL_OPERAND (offset)) | |
10171 | { | |
10172 | insn = gen_add3_insn (hard_frame_pointer_rtx, | |
10173 | stack_pointer_rtx, GEN_INT (offset)); | |
10174 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
ab77a036 RS |
10175 | } |
10176 | else | |
f374e413 RS |
10177 | { |
10178 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset)); | |
10179 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
10180 | emit_insn (gen_add3_insn (hard_frame_pointer_rtx, | |
10181 | hard_frame_pointer_rtx, | |
10182 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10183 | mips_set_frame_expr | |
10184 | (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, | |
10185 | plus_constant (stack_pointer_rtx, offset))); | |
10186 | } | |
ab77a036 RS |
10187 | } |
10188 | ||
10189 | mips_emit_loadgp (); | |
10190 | ||
65239d20 | 10191 | /* Initialize the $gp save slot. */ |
0c433c31 | 10192 | if (mips_cfun_has_cprestore_slot_p ()) |
08d0963a | 10193 | { |
0c433c31 RS |
10194 | rtx base, mem, gp, temp; |
10195 | HOST_WIDE_INT offset; | |
10196 | ||
10197 | mips_get_cprestore_base_and_offset (&base, &offset, false); | |
10198 | mem = gen_frame_mem (Pmode, plus_constant (base, offset)); | |
10199 | gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; | |
10200 | temp = (SMALL_OPERAND (offset) | |
10201 | ? gen_rtx_SCRATCH (Pmode) | |
10202 | : MIPS_PROLOGUE_TEMP (Pmode)); | |
10203 | emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp)); | |
10204 | ||
10205 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
10206 | mem = gen_frame_mem (Pmode, plus_constant (base, offset)); | |
10207 | emit_insn (gen_use_cprestore (mem)); | |
08d0963a | 10208 | } |
ab77a036 | 10209 | |
e19da24c CF |
10210 | /* We need to search back to the last use of K0 or K1. */ |
10211 | if (cfun->machine->interrupt_handler_p) | |
10212 | { | |
10213 | for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn)) | |
10214 | if (INSN_P (insn) | |
10215 | && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL)) | |
10216 | break; | |
10217 | /* Emit a move from K1 to COP0 Status after insn. */ | |
10218 | gcc_assert (insn != NULL_RTX); | |
10219 | emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
10220 | gen_rtx_REG (SImode, K1_REG_NUM)), | |
10221 | insn); | |
10222 | } | |
10223 | ||
ab77a036 RS |
10224 | /* If we are profiling, make sure no instructions are scheduled before |
10225 | the call to mcount. */ | |
e3b5732b | 10226 | if (crtl->profile) |
ab77a036 RS |
10227 | emit_insn (gen_blockage ()); |
10228 | } | |
10229 | \f | |
10230 | /* Emit instructions to restore register REG from slot MEM. */ | |
10231 | ||
10232 | static void | |
10233 | mips_restore_reg (rtx reg, rtx mem) | |
10234 | { | |
65239d20 | 10235 | /* There's no MIPS16 instruction to load $31 directly. Load into |
ab77a036 | 10236 | $7 instead and adjust the return insn appropriately. */ |
293593b1 | 10237 | if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM) |
65239d20 | 10238 | reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7); |
ab77a036 | 10239 | |
0c433c31 | 10240 | mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg))); |
ab77a036 RS |
10241 | } |
10242 | ||
2f7e2abb RS |
10243 | /* Emit any instructions needed before a return. */ |
10244 | ||
10245 | void | |
10246 | mips_expand_before_return (void) | |
10247 | { | |
10248 | /* When using a call-clobbered gp, we start out with unified call | |
10249 | insns that include instructions to restore the gp. We then split | |
10250 | these unified calls after reload. These split calls explicitly | |
10251 | clobber gp, so there is no need to define | |
10252 | PIC_OFFSET_TABLE_REG_CALL_CLOBBERED. | |
10253 | ||
10254 | For consistency, we should also insert an explicit clobber of $28 | |
10255 | before return insns, so that the post-reload optimizers know that | |
10256 | the register is not live on exit. */ | |
10257 | if (TARGET_CALL_CLOBBERED_GP) | |
10258 | emit_clobber (pic_offset_table_rtx); | |
10259 | } | |
10260 | ||
65239d20 RS |
10261 | /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P |
10262 | says which. */ | |
ab77a036 RS |
10263 | |
10264 | void | |
65239d20 | 10265 | mips_expand_epilogue (bool sibcall_p) |
ab77a036 | 10266 | { |
65239d20 | 10267 | const struct mips_frame_info *frame; |
ab77a036 | 10268 | HOST_WIDE_INT step1, step2; |
e19da24c | 10269 | rtx base, target, insn; |
ab77a036 RS |
10270 | |
10271 | if (!sibcall_p && mips_can_use_return_insn ()) | |
10272 | { | |
10273 | emit_jump_insn (gen_return ()); | |
10274 | return; | |
10275 | } | |
10276 | ||
65239d20 | 10277 | /* In MIPS16 mode, if the return value should go into a floating-point |
ab77a036 RS |
10278 | register, we need to call a helper routine to copy it over. */ |
10279 | if (mips16_cfun_returns_in_fpr_p ()) | |
5f5fe6d9 | 10280 | mips16_copy_fpr_return_value (); |
1f2d8f51 | 10281 | |
be763023 RS |
10282 | /* Split the frame into two. STEP1 is the amount of stack we should |
10283 | deallocate before restoring the registers. STEP2 is the amount we | |
10284 | should deallocate afterwards. | |
10285 | ||
10286 | Start off by assuming that no registers need to be restored. */ | |
65239d20 RS |
10287 | frame = &cfun->machine->frame; |
10288 | step1 = frame->total_size; | |
be763023 RS |
10289 | step2 = 0; |
10290 | ||
f374e413 | 10291 | /* Work out which register holds the frame address. */ |
be763023 RS |
10292 | if (!frame_pointer_needed) |
10293 | base = stack_pointer_rtx; | |
10294 | else | |
0fb5ac6f | 10295 | { |
be763023 | 10296 | base = hard_frame_pointer_rtx; |
65239d20 | 10297 | step1 -= frame->hard_frame_pointer_offset; |
0fb5ac6f MM |
10298 | } |
10299 | ||
be763023 RS |
10300 | /* If we need to restore registers, deallocate as much stack as |
10301 | possible in the second step without going out of range. */ | |
e19da24c CF |
10302 | if ((frame->mask | frame->fmask | frame->acc_mask) != 0 |
10303 | || frame->num_cop0_regs > 0) | |
0fb5ac6f | 10304 | { |
be763023 RS |
10305 | step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP); |
10306 | step1 -= step2; | |
10307 | } | |
f5963e61 | 10308 | |
be763023 RS |
10309 | /* Set TARGET to BASE + STEP1. */ |
10310 | target = base; | |
10311 | if (step1 > 0) | |
10312 | { | |
10313 | rtx adjust; | |
2bcb2ab3 | 10314 | |
be763023 RS |
10315 | /* Get an rtx for STEP1 that we can add to BASE. */ |
10316 | adjust = GEN_INT (step1); | |
10317 | if (!SMALL_OPERAND (step1)) | |
9e800206 | 10318 | { |
51e7252a | 10319 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust); |
be763023 | 10320 | adjust = MIPS_EPILOGUE_TEMP (Pmode); |
9e800206 RH |
10321 | } |
10322 | ||
be763023 RS |
10323 | /* Normal mode code can copy the result straight into $sp. */ |
10324 | if (!TARGET_MIPS16) | |
10325 | target = stack_pointer_rtx; | |
9e800206 | 10326 | |
be763023 RS |
10327 | emit_insn (gen_add3_insn (target, base, adjust)); |
10328 | } | |
282cb01b | 10329 | |
be763023 RS |
10330 | /* Copy TARGET into the stack pointer. */ |
10331 | if (target != stack_pointer_rtx) | |
51e7252a | 10332 | mips_emit_move (stack_pointer_rtx, target); |
282cb01b | 10333 | |
14976818 RS |
10334 | /* If we're using addressing macros, $gp is implicitly used by all |
10335 | SYMBOL_REFs. We must emit a blockage insn before restoring $gp | |
10336 | from the stack. */ | |
10337 | if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS) | |
be763023 | 10338 | emit_insn (gen_blockage ()); |
282cb01b | 10339 | |
65239d20 | 10340 | if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0) |
e1260576 RS |
10341 | { |
10342 | unsigned int regno, mask; | |
10343 | HOST_WIDE_INT offset; | |
10344 | rtx restore; | |
10345 | ||
10346 | /* Generate the restore instruction. */ | |
65239d20 | 10347 | mask = frame->mask; |
e1260576 RS |
10348 | restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2); |
10349 | ||
10350 | /* Restore any other registers manually. */ | |
10351 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
10352 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
10353 | { | |
6e75e6e3 RS |
10354 | offset -= UNITS_PER_WORD; |
10355 | mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg); | |
e1260576 | 10356 | } |
be763023 | 10357 | |
e1260576 RS |
10358 | /* Restore the remaining registers and deallocate the final bit |
10359 | of the frame. */ | |
10360 | emit_insn (restore); | |
10361 | } | |
10362 | else | |
10363 | { | |
10364 | /* Restore the registers. */ | |
e19da24c CF |
10365 | mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg); |
10366 | mips_for_each_saved_gpr_and_fpr (frame->total_size - step2, | |
10367 | mips_restore_reg); | |
e1260576 | 10368 | |
e19da24c CF |
10369 | if (cfun->machine->interrupt_handler_p) |
10370 | { | |
10371 | HOST_WIDE_INT offset; | |
10372 | rtx mem; | |
10373 | ||
10374 | offset = frame->cop0_sp_offset - (frame->total_size - step2); | |
10375 | if (!cfun->machine->keep_interrupts_masked_p) | |
10376 | { | |
10377 | /* Restore the original EPC. */ | |
10378 | mem = gen_frame_mem (word_mode, | |
10379 | plus_constant (stack_pointer_rtx, offset)); | |
10380 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); | |
10381 | offset -= UNITS_PER_WORD; | |
10382 | ||
10383 | /* Move to COP0 EPC. */ | |
10384 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM), | |
10385 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10386 | } | |
10387 | ||
10388 | /* Restore the original Status. */ | |
10389 | mem = gen_frame_mem (word_mode, | |
10390 | plus_constant (stack_pointer_rtx, offset)); | |
10391 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); | |
10392 | offset -= UNITS_PER_WORD; | |
10393 | ||
10394 | /* If we don't use shoadow register set, we need to update SP. */ | |
10395 | if (!cfun->machine->use_shadow_register_set_p && step2 > 0) | |
10396 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10397 | stack_pointer_rtx, | |
10398 | GEN_INT (step2))); | |
10399 | ||
10400 | /* Move to COP0 Status. */ | |
10401 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
10402 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10403 | } | |
10404 | else | |
10405 | { | |
10406 | /* Deallocate the final bit of the frame. */ | |
10407 | if (step2 > 0) | |
10408 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10409 | stack_pointer_rtx, | |
10410 | GEN_INT (step2))); | |
10411 | } | |
e1260576 | 10412 | } |
91e01231 | 10413 | |
71cc389b | 10414 | /* Add in the __builtin_eh_return stack adjustment. We need to |
65239d20 | 10415 | use a temporary in MIPS16 code. */ |
e3b5732b | 10416 | if (crtl->calls_eh_return) |
be763023 RS |
10417 | { |
10418 | if (TARGET_MIPS16) | |
10419 | { | |
51e7252a | 10420 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx); |
be763023 RS |
10421 | emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode), |
10422 | MIPS_EPILOGUE_TEMP (Pmode), | |
10423 | EH_RETURN_STACKADJ_RTX)); | |
51e7252a | 10424 | mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode)); |
9e800206 | 10425 | } |
be763023 RS |
10426 | else |
10427 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10428 | stack_pointer_rtx, | |
10429 | EH_RETURN_STACKADJ_RTX)); | |
0fb5ac6f | 10430 | } |
be763023 | 10431 | |
cafe096b EC |
10432 | if (!sibcall_p) |
10433 | { | |
2f7e2abb | 10434 | mips_expand_before_return (); |
e19da24c CF |
10435 | if (cfun->machine->interrupt_handler_p) |
10436 | { | |
10437 | /* Interrupt handlers generate eret or deret. */ | |
10438 | if (cfun->machine->use_debug_exception_return_p) | |
10439 | emit_jump_insn (gen_mips_deret ()); | |
10440 | else | |
10441 | emit_jump_insn (gen_mips_eret ()); | |
10442 | } | |
10443 | else | |
10444 | { | |
10445 | unsigned int regno; | |
10446 | ||
10447 | /* When generating MIPS16 code, the normal | |
10448 | mips_for_each_saved_gpr_and_fpr path will restore the return | |
10449 | address into $7 rather than $31. */ | |
10450 | if (TARGET_MIPS16 | |
10451 | && !GENERATE_MIPS16E_SAVE_RESTORE | |
293593b1 | 10452 | && BITSET_P (frame->mask, RETURN_ADDR_REGNUM)) |
e19da24c CF |
10453 | regno = GP_REG_FIRST + 7; |
10454 | else | |
293593b1 | 10455 | regno = RETURN_ADDR_REGNUM; |
e19da24c CF |
10456 | emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno))); |
10457 | } | |
10458 | } | |
10459 | ||
10460 | /* Search from the beginning to the first use of K0 or K1. */ | |
10461 | if (cfun->machine->interrupt_handler_p | |
10462 | && !cfun->machine->keep_interrupts_masked_p) | |
10463 | { | |
10464 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
10465 | if (INSN_P (insn) | |
10466 | && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL)) | |
10467 | break; | |
10468 | gcc_assert (insn != NULL_RTX); | |
10469 | /* Insert disable interrupts before the first use of K0 or K1. */ | |
10470 | emit_insn_before (gen_mips_di (), insn); | |
10471 | emit_insn_before (gen_mips_ehb (), insn); | |
cafe096b | 10472 | } |
cee98a59 | 10473 | } |
cee98a59 | 10474 | \f |
f5963e61 | 10475 | /* Return nonzero if this function is known to have a null epilogue. |
cee98a59 MM |
10476 | This allows the optimizer to omit jumps to jumps if no stack |
10477 | was created. */ | |
10478 | ||
65239d20 | 10479 | bool |
b4966b1b | 10480 | mips_can_use_return_insn (void) |
cee98a59 | 10481 | { |
e19da24c CF |
10482 | /* Interrupt handlers need to go through the epilogue. */ |
10483 | if (cfun->machine->interrupt_handler_p) | |
10484 | return false; | |
10485 | ||
65239d20 RS |
10486 | if (!reload_completed) |
10487 | return false; | |
cee98a59 | 10488 | |
e3b5732b | 10489 | if (crtl->profile) |
65239d20 | 10490 | return false; |
1f2d8f51 | 10491 | |
65239d20 RS |
10492 | /* In MIPS16 mode, a function that returns a floating-point value |
10493 | needs to arrange to copy the return value into the floating-point | |
2bcb2ab3 | 10494 | registers. */ |
a38e0142 | 10495 | if (mips16_cfun_returns_in_fpr_p ()) |
65239d20 | 10496 | return false; |
2bcb2ab3 | 10497 | |
16dc5c28 | 10498 | return cfun->machine->frame.total_size == 0; |
cee98a59 | 10499 | } |
9753d4e4 | 10500 | \f |
5f5fe6d9 RS |
10501 | /* Return true if register REGNO can store a value of mode MODE. |
10502 | The result of this function is cached in mips_hard_regno_mode_ok. */ | |
10503 | ||
10504 | static bool | |
10505 | mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode) | |
10506 | { | |
10507 | unsigned int size; | |
0a2aaacc | 10508 | enum mode_class mclass; |
5f5fe6d9 RS |
10509 | |
10510 | if (mode == CCV2mode) | |
10511 | return (ISA_HAS_8CC | |
10512 | && ST_REG_P (regno) | |
10513 | && (regno - ST_REG_FIRST) % 2 == 0); | |
10514 | ||
10515 | if (mode == CCV4mode) | |
10516 | return (ISA_HAS_8CC | |
10517 | && ST_REG_P (regno) | |
10518 | && (regno - ST_REG_FIRST) % 4 == 0); | |
10519 | ||
10520 | if (mode == CCmode) | |
10521 | { | |
10522 | if (!ISA_HAS_8CC) | |
10523 | return regno == FPSW_REGNUM; | |
10524 | ||
10525 | return (ST_REG_P (regno) | |
10526 | || GP_REG_P (regno) | |
10527 | || FP_REG_P (regno)); | |
10528 | } | |
10529 | ||
10530 | size = GET_MODE_SIZE (mode); | |
0a2aaacc | 10531 | mclass = GET_MODE_CLASS (mode); |
5f5fe6d9 RS |
10532 | |
10533 | if (GP_REG_P (regno)) | |
10534 | return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; | |
10535 | ||
10536 | if (FP_REG_P (regno) | |
10537 | && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0 | |
10538 | || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG))) | |
10539 | { | |
10540 | /* Allow TFmode for CCmode reloads. */ | |
10541 | if (mode == TFmode && ISA_HAS_8CC) | |
10542 | return true; | |
10543 | ||
93581857 MS |
10544 | /* Allow 64-bit vector modes for Loongson-2E/2F. */ |
10545 | if (TARGET_LOONGSON_VECTORS | |
10546 | && (mode == V2SImode | |
10547 | || mode == V4HImode | |
10548 | || mode == V8QImode | |
10549 | || mode == DImode)) | |
10550 | return true; | |
10551 | ||
0a2aaacc KG |
10552 | if (mclass == MODE_FLOAT |
10553 | || mclass == MODE_COMPLEX_FLOAT | |
10554 | || mclass == MODE_VECTOR_FLOAT) | |
5f5fe6d9 RS |
10555 | return size <= UNITS_PER_FPVALUE; |
10556 | ||
10557 | /* Allow integer modes that fit into a single register. We need | |
10558 | to put integers into FPRs when using instructions like CVT | |
10559 | and TRUNC. There's no point allowing sizes smaller than a word, | |
10560 | because the FPU has no appropriate load/store instructions. */ | |
0a2aaacc | 10561 | if (mclass == MODE_INT) |
5f5fe6d9 RS |
10562 | return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG; |
10563 | } | |
10564 | ||
10565 | if (ACC_REG_P (regno) | |
10566 | && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) | |
10567 | { | |
21dfc6dc RS |
10568 | if (MD_REG_P (regno)) |
10569 | { | |
10570 | /* After a multiplication or division, clobbering HI makes | |
10571 | the value of LO unpredictable, and vice versa. This means | |
10572 | that, for all interesting cases, HI and LO are effectively | |
10573 | a single register. | |
10574 | ||
10575 | We model this by requiring that any value that uses HI | |
10576 | also uses LO. */ | |
10577 | if (size <= UNITS_PER_WORD * 2) | |
10578 | return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); | |
10579 | } | |
10580 | else | |
10581 | { | |
10582 | /* DSP accumulators do not have the same restrictions as | |
10583 | HI and LO, so we can treat them as normal doubleword | |
10584 | registers. */ | |
10585 | if (size <= UNITS_PER_WORD) | |
10586 | return true; | |
5f5fe6d9 | 10587 | |
21dfc6dc RS |
10588 | if (size <= UNITS_PER_WORD * 2 |
10589 | && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) | |
10590 | return true; | |
10591 | } | |
5f5fe6d9 RS |
10592 | } |
10593 | ||
10594 | if (ALL_COP_REG_P (regno)) | |
0a2aaacc | 10595 | return mclass == MODE_INT && size <= UNITS_PER_WORD; |
5f5fe6d9 | 10596 | |
dbc90b65 RS |
10597 | if (regno == GOT_VERSION_REGNUM) |
10598 | return mode == SImode; | |
10599 | ||
5f5fe6d9 RS |
10600 | return false; |
10601 | } | |
10602 | ||
c862c910 | 10603 | /* Implement HARD_REGNO_NREGS. */ |
b85aed9e | 10604 | |
ab77a036 RS |
10605 | unsigned int |
10606 | mips_hard_regno_nregs (int regno, enum machine_mode mode) | |
b85aed9e | 10607 | { |
ab77a036 | 10608 | if (ST_REG_P (regno)) |
c862c910 RS |
10609 | /* The size of FP status registers is always 4, because they only hold |
10610 | CCmode values, and CCmode is always considered to be 4 bytes wide. */ | |
10611 | return (GET_MODE_SIZE (mode) + 3) / 4; | |
b85aed9e | 10612 | |
c862c910 RS |
10613 | if (FP_REG_P (regno)) |
10614 | return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; | |
e440de0e | 10615 | |
c862c910 RS |
10616 | /* All other registers are word-sized. */ |
10617 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
10618 | } | |
6fb5fa3c | 10619 | |
c862c910 RS |
10620 | /* Implement CLASS_MAX_NREGS, taking the maximum of the cases |
10621 | in mips_hard_regno_nregs. */ | |
f5678792 | 10622 | |
ab77a036 | 10623 | int |
0a2aaacc | 10624 | mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode) |
ab77a036 | 10625 | { |
c862c910 RS |
10626 | int size; |
10627 | HARD_REG_SET left; | |
10628 | ||
10629 | size = 0x8000; | |
0a2aaacc | 10630 | COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); |
c862c910 RS |
10631 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) |
10632 | { | |
10633 | size = MIN (size, 4); | |
10634 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); | |
10635 | } | |
10636 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) | |
10637 | { | |
10638 | size = MIN (size, UNITS_PER_FPREG); | |
10639 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); | |
10640 | } | |
10641 | if (!hard_reg_set_empty_p (left)) | |
10642 | size = MIN (size, UNITS_PER_WORD); | |
10643 | return (GET_MODE_SIZE (mode) + size - 1) / size; | |
ab77a036 | 10644 | } |
b85aed9e | 10645 | |
65239d20 | 10646 | /* Implement CANNOT_CHANGE_MODE_CLASS. */ |
b85aed9e | 10647 | |
ab77a036 RS |
10648 | bool |
10649 | mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED, | |
10650 | enum machine_mode to ATTRIBUTE_UNUSED, | |
0a2aaacc | 10651 | enum reg_class rclass) |
ab77a036 | 10652 | { |
dd5a833e MS |
10653 | /* There are several problems with changing the modes of values in |
10654 | floating-point registers: | |
b85aed9e | 10655 | |
ab77a036 | 10656 | - When a multi-word value is stored in paired floating-point |
dd5a833e MS |
10657 | registers, the first register always holds the low word. We |
10658 | therefore can't allow FPRs to change between single-word and | |
10659 | multi-word modes on big-endian targets. | |
b85aed9e | 10660 | |
dd5a833e MS |
10661 | - GCC assumes that each word of a multiword register can be |
10662 | accessed individually using SUBREGs. This is not true for | |
10663 | floating-point registers if they are bigger than a word. | |
b85aed9e | 10664 | |
ab77a036 | 10665 | - Loading a 32-bit value into a 64-bit floating-point register |
dd5a833e MS |
10666 | will not sign-extend the value, despite what LOAD_EXTEND_OP |
10667 | says. We can't allow FPRs to change from SImode to a wider | |
10668 | mode on 64-bit targets. | |
b85aed9e | 10669 | |
dd5a833e MS |
10670 | - If the FPU has already interpreted a value in one format, we |
10671 | must not ask it to treat the value as having a different | |
10672 | format. | |
b85aed9e | 10673 | |
43029c10 | 10674 | We therefore disallow all mode changes involving FPRs. */ |
0a2aaacc | 10675 | return reg_classes_intersect_p (FP_REGS, rclass); |
ab77a036 | 10676 | } |
b85aed9e | 10677 | |
42db504c SB |
10678 | /* Implement target hook small_register_classes_for_mode_p. */ |
10679 | ||
10680 | static bool | |
10681 | mips_small_register_classes_for_mode_p (enum machine_mode mode | |
10682 | ATTRIBUTE_UNUSED) | |
10683 | { | |
10684 | return TARGET_MIPS16; | |
10685 | } | |
10686 | ||
ab77a036 | 10687 | /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */ |
b85aed9e | 10688 | |
ab77a036 RS |
10689 | static bool |
10690 | mips_mode_ok_for_mov_fmt_p (enum machine_mode mode) | |
10691 | { | |
10692 | switch (mode) | |
b85aed9e | 10693 | { |
ab77a036 RS |
10694 | case SFmode: |
10695 | return TARGET_HARD_FLOAT; | |
b85aed9e | 10696 | |
ab77a036 RS |
10697 | case DFmode: |
10698 | return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT; | |
b85aed9e | 10699 | |
ab77a036 RS |
10700 | case V2SFmode: |
10701 | return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT; | |
b85aed9e | 10702 | |
ab77a036 RS |
10703 | default: |
10704 | return false; | |
b85aed9e | 10705 | } |
b85aed9e | 10706 | } |
9753d4e4 | 10707 | |
e5a2b69d RS |
10708 | /* Implement MODES_TIEABLE_P. */ |
10709 | ||
10710 | bool | |
10711 | mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
10712 | { | |
10713 | /* FPRs allow no mode punning, so it's not worth tying modes if we'd | |
10714 | prefer to put one of them in FPRs. */ | |
10715 | return (mode1 == mode2 | |
10716 | || (!mips_mode_ok_for_mov_fmt_p (mode1) | |
10717 | && !mips_mode_ok_for_mov_fmt_p (mode2))); | |
10718 | } | |
10719 | ||
ef78aed6 | 10720 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
7dac2f89 | 10721 | |
ef78aed6 AS |
10722 | static reg_class_t |
10723 | mips_preferred_reload_class (rtx x, reg_class_t rclass) | |
ab77a036 | 10724 | { |
0a2aaacc | 10725 | if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass)) |
ab77a036 | 10726 | return LEA_REGS; |
9753d4e4 | 10727 | |
0a2aaacc | 10728 | if (reg_class_subset_p (FP_REGS, rclass) |
ab77a036 RS |
10729 | && mips_mode_ok_for_mov_fmt_p (GET_MODE (x))) |
10730 | return FP_REGS; | |
94b9aa66 | 10731 | |
0a2aaacc KG |
10732 | if (reg_class_subset_p (GR_REGS, rclass)) |
10733 | rclass = GR_REGS; | |
94b9aa66 | 10734 | |
0a2aaacc KG |
10735 | if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass)) |
10736 | rclass = M16_REGS; | |
d6b5193b | 10737 | |
0a2aaacc | 10738 | return rclass; |
94b9aa66 RS |
10739 | } |
10740 | ||
aea8cb37 RS |
10741 | /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. |
10742 | Return a "canonical" class to represent it in later calculations. */ | |
91455597 | 10743 | |
faa832a7 AS |
10744 | static reg_class_t |
10745 | mips_canonicalize_move_class (reg_class_t rclass) | |
ab77a036 | 10746 | { |
aea8cb37 RS |
10747 | /* All moves involving accumulator registers have the same cost. */ |
10748 | if (reg_class_subset_p (rclass, ACC_REGS)) | |
10749 | rclass = ACC_REGS; | |
10750 | ||
10751 | /* Likewise promote subclasses of general registers to the most | |
10752 | interesting containing class. */ | |
10753 | if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS)) | |
10754 | rclass = M16_REGS; | |
10755 | else if (reg_class_subset_p (rclass, GENERAL_REGS)) | |
10756 | rclass = GENERAL_REGS; | |
10757 | ||
10758 | return rclass; | |
10759 | } | |
10760 | ||
10761 | /* Return the cost of moving a value of mode MODE from a register of | |
10762 | class FROM to a GPR. Return 0 for classes that are unions of other | |
10763 | classes handled by this function. */ | |
10764 | ||
10765 | static int | |
10766 | mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
faa832a7 | 10767 | reg_class_t from) |
aea8cb37 RS |
10768 | { |
10769 | switch (from) | |
9753d4e4 | 10770 | { |
aea8cb37 RS |
10771 | case GENERAL_REGS: |
10772 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
10773 | return 2; | |
10774 | ||
10775 | case ACC_REGS: | |
10776 | /* MFLO and MFHI. */ | |
10777 | return 6; | |
10778 | ||
10779 | case FP_REGS: | |
10780 | /* MFC1, etc. */ | |
10781 | return 4; | |
10782 | ||
10783 | case ST_REGS: | |
10784 | /* LUI followed by MOVF. */ | |
10785 | return 4; | |
10786 | ||
10787 | case COP0_REGS: | |
10788 | case COP2_REGS: | |
10789 | case COP3_REGS: | |
10790 | /* This choice of value is historical. */ | |
10791 | return 5; | |
10792 | ||
10793 | default: | |
10794 | return 0; | |
9753d4e4 | 10795 | } |
aea8cb37 RS |
10796 | } |
10797 | ||
10798 | /* Return the cost of moving a value of mode MODE from a GPR to a | |
10799 | register of class TO. Return 0 for classes that are unions of | |
10800 | other classes handled by this function. */ | |
10801 | ||
10802 | static int | |
faa832a7 | 10803 | mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to) |
aea8cb37 RS |
10804 | { |
10805 | switch (to) | |
9753d4e4 | 10806 | { |
aea8cb37 RS |
10807 | case GENERAL_REGS: |
10808 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
10809 | return 2; | |
10810 | ||
10811 | case ACC_REGS: | |
10812 | /* MTLO and MTHI. */ | |
10813 | return 6; | |
10814 | ||
10815 | case FP_REGS: | |
10816 | /* MTC1, etc. */ | |
10817 | return 4; | |
10818 | ||
10819 | case ST_REGS: | |
10820 | /* A secondary reload through an FPR scratch. */ | |
10821 | return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS) | |
10822 | + mips_register_move_cost (mode, FP_REGS, ST_REGS)); | |
10823 | ||
10824 | case COP0_REGS: | |
10825 | case COP2_REGS: | |
10826 | case COP3_REGS: | |
10827 | /* This choice of value is historical. */ | |
10828 | return 5; | |
10829 | ||
10830 | default: | |
10831 | return 0; | |
9753d4e4 | 10832 | } |
aea8cb37 RS |
10833 | } |
10834 | ||
faa832a7 | 10835 | /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the |
aea8cb37 RS |
10836 | maximum of the move costs for subclasses; regclass will work out |
10837 | the maximum for us. */ | |
10838 | ||
faa832a7 | 10839 | static int |
aea8cb37 | 10840 | mips_register_move_cost (enum machine_mode mode, |
faa832a7 | 10841 | reg_class_t from, reg_class_t to) |
aea8cb37 | 10842 | { |
faa832a7 | 10843 | reg_class_t dregs; |
aea8cb37 RS |
10844 | int cost1, cost2; |
10845 | ||
10846 | from = mips_canonicalize_move_class (from); | |
10847 | to = mips_canonicalize_move_class (to); | |
10848 | ||
10849 | /* Handle moves that can be done without using general-purpose registers. */ | |
10850 | if (from == FP_REGS) | |
a318179e | 10851 | { |
aea8cb37 RS |
10852 | if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode)) |
10853 | /* MOV.FMT. */ | |
ab77a036 | 10854 | return 4; |
aea8cb37 RS |
10855 | if (to == ST_REGS) |
10856 | /* The sequence generated by mips_expand_fcc_reload. */ | |
10857 | return 8; | |
ab77a036 | 10858 | } |
aea8cb37 RS |
10859 | |
10860 | /* Handle cases in which only one class deviates from the ideal. */ | |
10861 | dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS; | |
10862 | if (from == dregs) | |
10863 | return mips_move_from_gpr_cost (mode, to); | |
10864 | if (to == dregs) | |
10865 | return mips_move_to_gpr_cost (mode, from); | |
10866 | ||
10867 | /* Handles cases that require a GPR temporary. */ | |
10868 | cost1 = mips_move_to_gpr_cost (mode, from); | |
10869 | if (cost1 != 0) | |
ab77a036 | 10870 | { |
aea8cb37 RS |
10871 | cost2 = mips_move_from_gpr_cost (mode, to); |
10872 | if (cost2 != 0) | |
10873 | return cost1 + cost2; | |
a318179e RS |
10874 | } |
10875 | ||
aea8cb37 | 10876 | return 0; |
9753d4e4 | 10877 | } |
ea462dd0 | 10878 | |
faa832a7 AS |
10879 | /* Implement TARGET_MEMORY_MOVE_COST. */ |
10880 | ||
10881 | static int | |
10882 | mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) | |
10883 | { | |
10884 | return (mips_cost->memory_latency | |
10885 | + memory_move_secondary_cost (mode, rclass, in)); | |
10886 | } | |
10887 | ||
65239d20 | 10888 | /* Return the register class required for a secondary register when |
0a2aaacc | 10889 | copying between one of the registers in RCLASS and value X, which |
65239d20 RS |
10890 | has mode MODE. X is the source of the move if IN_P, otherwise it |
10891 | is the destination. Return NO_REGS if no secondary register is | |
10892 | needed. */ | |
ea462dd0 | 10893 | |
ab77a036 | 10894 | enum reg_class |
0a2aaacc | 10895 | mips_secondary_reload_class (enum reg_class rclass, |
65239d20 | 10896 | enum machine_mode mode, rtx x, bool in_p) |
ea462dd0 | 10897 | { |
ab77a036 | 10898 | int regno; |
ea462dd0 | 10899 | |
ab77a036 RS |
10900 | /* If X is a constant that cannot be loaded into $25, it must be loaded |
10901 | into some other GPR. No other register class allows a direct move. */ | |
10902 | if (mips_dangerous_for_la25_p (x)) | |
0a2aaacc | 10903 | return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS; |
c988af2b | 10904 | |
ab77a036 RS |
10905 | regno = true_regnum (x); |
10906 | if (TARGET_MIPS16) | |
10907 | { | |
10908 | /* In MIPS16 mode, every move must involve a member of M16_REGS. */ | |
0a2aaacc | 10909 | if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno)) |
ab77a036 | 10910 | return M16_REGS; |
c988af2b | 10911 | |
ab77a036 RS |
10912 | return NO_REGS; |
10913 | } | |
c988af2b | 10914 | |
ab77a036 RS |
10915 | /* Copying from accumulator registers to anywhere other than a general |
10916 | register requires a temporary general register. */ | |
0a2aaacc | 10917 | if (reg_class_subset_p (rclass, ACC_REGS)) |
ab77a036 RS |
10918 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; |
10919 | if (ACC_REG_P (regno)) | |
0a2aaacc | 10920 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
c988af2b | 10921 | |
ab77a036 | 10922 | /* We can only copy a value to a condition code register from a |
65239d20 RS |
10923 | floating-point register, and even then we require a scratch |
10924 | floating-point register. We can only copy a value out of a | |
10925 | condition-code register into a general register. */ | |
0a2aaacc | 10926 | if (reg_class_subset_p (rclass, ST_REGS)) |
c988af2b | 10927 | { |
ab77a036 RS |
10928 | if (in_p) |
10929 | return FP_REGS; | |
10930 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; | |
10931 | } | |
10932 | if (ST_REG_P (regno)) | |
10933 | { | |
10934 | if (!in_p) | |
10935 | return FP_REGS; | |
0a2aaacc | 10936 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 | 10937 | } |
c988af2b | 10938 | |
0a2aaacc | 10939 | if (reg_class_subset_p (rclass, FP_REGS)) |
ab77a036 RS |
10940 | { |
10941 | if (MEM_P (x) | |
10942 | && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)) | |
10943 | /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use | |
10944 | pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */ | |
10945 | return NO_REGS; | |
c988af2b | 10946 | |
ab77a036 RS |
10947 | if (GP_REG_P (regno) || x == CONST0_RTX (mode)) |
10948 | /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */ | |
10949 | return NO_REGS; | |
c988af2b | 10950 | |
fbbf66e7 | 10951 | if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x)) |
ab77a036 RS |
10952 | /* We can force the constant to memory and use lwc1 |
10953 | and ldc1. As above, we will use pairs of lwc1s if | |
10954 | ldc1 is not supported. */ | |
10955 | return NO_REGS; | |
10956 | ||
10957 | if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode)) | |
10958 | /* In this case we can use mov.fmt. */ | |
10959 | return NO_REGS; | |
10960 | ||
10961 | /* Otherwise, we need to reload through an integer register. */ | |
10962 | return GR_REGS; | |
c988af2b | 10963 | } |
ab77a036 | 10964 | if (FP_REG_P (regno)) |
0a2aaacc | 10965 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 RS |
10966 | |
10967 | return NO_REGS; | |
c988af2b RS |
10968 | } |
10969 | ||
65239d20 | 10970 | /* Implement TARGET_MODE_REP_EXTENDED. */ |
c988af2b | 10971 | |
ab77a036 RS |
10972 | static int |
10973 | mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep) | |
10974 | { | |
65239d20 | 10975 | /* On 64-bit targets, SImode register values are sign-extended to DImode. */ |
ab77a036 RS |
10976 | if (TARGET_64BIT && mode == SImode && mode_rep == DImode) |
10977 | return SIGN_EXTEND; | |
c988af2b | 10978 | |
ab77a036 RS |
10979 | return UNKNOWN; |
10980 | } | |
65239d20 RS |
10981 | \f |
10982 | /* Implement TARGET_VALID_POINTER_MODE. */ | |
c988af2b | 10983 | |
ab77a036 RS |
10984 | static bool |
10985 | mips_valid_pointer_mode (enum machine_mode mode) | |
10986 | { | |
65239d20 | 10987 | return mode == SImode || (TARGET_64BIT && mode == DImode); |
ab77a036 | 10988 | } |
c988af2b | 10989 | |
65239d20 | 10990 | /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */ |
c988af2b RS |
10991 | |
10992 | static bool | |
ab77a036 | 10993 | mips_vector_mode_supported_p (enum machine_mode mode) |
c988af2b | 10994 | { |
ab77a036 RS |
10995 | switch (mode) |
10996 | { | |
10997 | case V2SFmode: | |
10998 | return TARGET_PAIRED_SINGLE_FLOAT; | |
c988af2b | 10999 | |
ab77a036 RS |
11000 | case V2HImode: |
11001 | case V4QImode: | |
11002 | case V2HQmode: | |
11003 | case V2UHQmode: | |
11004 | case V2HAmode: | |
11005 | case V2UHAmode: | |
11006 | case V4QQmode: | |
11007 | case V4UQQmode: | |
11008 | return TARGET_DSP; | |
c988af2b | 11009 | |
93581857 MS |
11010 | case V2SImode: |
11011 | case V4HImode: | |
11012 | case V8QImode: | |
11013 | return TARGET_LOONGSON_VECTORS; | |
11014 | ||
ab77a036 RS |
11015 | default: |
11016 | return false; | |
11017 | } | |
11018 | } | |
c988af2b | 11019 | |
ab77a036 | 11020 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ |
c988af2b | 11021 | |
ab77a036 RS |
11022 | static bool |
11023 | mips_scalar_mode_supported_p (enum machine_mode mode) | |
c988af2b | 11024 | { |
ab77a036 RS |
11025 | if (ALL_FIXED_POINT_MODE_P (mode) |
11026 | && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) | |
11027 | return true; | |
c988af2b | 11028 | |
ab77a036 | 11029 | return default_scalar_mode_supported_p (mode); |
c988af2b | 11030 | } |
65239d20 | 11031 | \f |
cc4b5170 | 11032 | /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ |
26983c22 | 11033 | |
cc4b5170 RG |
11034 | static enum machine_mode |
11035 | mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED) | |
26983c22 | 11036 | { |
cc4b5170 RG |
11037 | if (TARGET_PAIRED_SINGLE_FLOAT |
11038 | && mode == SFmode) | |
11039 | return V2SFmode; | |
11040 | return word_mode; | |
26983c22 L |
11041 | } |
11042 | ||
65239d20 | 11043 | /* Implement TARGET_INIT_LIBFUNCS. */ |
c988af2b | 11044 | |
ab77a036 RS |
11045 | static void |
11046 | mips_init_libfuncs (void) | |
33563487 | 11047 | { |
ab77a036 | 11048 | if (TARGET_FIX_VR4120) |
c6e6f5c1 | 11049 | { |
65239d20 RS |
11050 | /* Register the special divsi3 and modsi3 functions needed to work |
11051 | around VR4120 division errata. */ | |
ab77a036 RS |
11052 | set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); |
11053 | set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); | |
33563487 JW |
11054 | } |
11055 | ||
ab77a036 | 11056 | if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI) |
a38e0142 | 11057 | { |
65239d20 | 11058 | /* Register the MIPS16 -mhard-float stubs. */ |
ab77a036 RS |
11059 | set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3"); |
11060 | set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3"); | |
11061 | set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3"); | |
11062 | set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3"); | |
c988af2b | 11063 | |
ab77a036 RS |
11064 | set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2"); |
11065 | set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2"); | |
11066 | set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2"); | |
11067 | set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2"); | |
11068 | set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2"); | |
11069 | set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2"); | |
11070 | set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2"); | |
c988af2b | 11071 | |
ab77a036 RS |
11072 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi"); |
11073 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf"); | |
11074 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf"); | |
293a36eb | 11075 | |
ab77a036 RS |
11076 | if (TARGET_DOUBLE_FLOAT) |
11077 | { | |
11078 | set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3"); | |
11079 | set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3"); | |
11080 | set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3"); | |
11081 | set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3"); | |
293a36eb | 11082 | |
ab77a036 RS |
11083 | set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2"); |
11084 | set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2"); | |
11085 | set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2"); | |
11086 | set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2"); | |
11087 | set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2"); | |
11088 | set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2"); | |
11089 | set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2"); | |
293a36eb | 11090 | |
65239d20 RS |
11091 | set_conv_libfunc (sext_optab, DFmode, SFmode, |
11092 | "__mips16_extendsfdf2"); | |
11093 | set_conv_libfunc (trunc_optab, SFmode, DFmode, | |
11094 | "__mips16_truncdfsf2"); | |
11095 | set_conv_libfunc (sfix_optab, SImode, DFmode, | |
11096 | "__mips16_fix_truncdfsi"); | |
11097 | set_conv_libfunc (sfloat_optab, DFmode, SImode, | |
11098 | "__mips16_floatsidf"); | |
11099 | set_conv_libfunc (ufloat_optab, DFmode, SImode, | |
11100 | "__mips16_floatunsidf"); | |
ab77a036 | 11101 | } |
0310e537 | 11102 | } |
e2ff10a9 RS |
11103 | |
11104 | /* The MIPS16 ISA does not have an encoding for "sync", so we rely | |
11105 | on an external non-MIPS16 routine to implement __sync_synchronize. */ | |
11106 | if (TARGET_MIPS16) | |
11107 | synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); | |
6cdd5672 RH |
11108 | } |
11109 | ||
0c433c31 RS |
11110 | /* Build up a multi-insn sequence that loads label TARGET into $AT. */ |
11111 | ||
11112 | static void | |
11113 | mips_process_load_label (rtx target) | |
11114 | { | |
11115 | rtx base, gp, intop; | |
11116 | HOST_WIDE_INT offset; | |
11117 | ||
11118 | mips_multi_start (); | |
11119 | switch (mips_abi) | |
11120 | { | |
11121 | case ABI_N32: | |
11122 | mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0); | |
11123 | mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
11124 | break; | |
11125 | ||
11126 | case ABI_64: | |
11127 | mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0); | |
11128 | mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
11129 | break; | |
11130 | ||
11131 | default: | |
11132 | gp = pic_offset_table_rtx; | |
11133 | if (mips_cfun_has_cprestore_slot_p ()) | |
11134 | { | |
11135 | gp = gen_rtx_REG (Pmode, AT_REGNUM); | |
11136 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
11137 | if (!SMALL_OPERAND (offset)) | |
11138 | { | |
11139 | intop = GEN_INT (CONST_HIGH_PART (offset)); | |
11140 | mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0); | |
11141 | mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0); | |
11142 | ||
11143 | base = gp; | |
11144 | offset = CONST_LOW_PART (offset); | |
11145 | } | |
11146 | intop = GEN_INT (offset); | |
11147 | if (ISA_HAS_LOAD_DELAY) | |
11148 | mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0); | |
11149 | else | |
11150 | mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0); | |
11151 | } | |
11152 | if (ISA_HAS_LOAD_DELAY) | |
11153 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0); | |
11154 | else | |
11155 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0); | |
11156 | mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0); | |
11157 | break; | |
11158 | } | |
11159 | } | |
11160 | ||
11161 | /* Return the number of instructions needed to load a label into $AT. */ | |
11162 | ||
11163 | static unsigned int | |
5a486834 | 11164 | mips_load_label_num_insns (void) |
0c433c31 | 11165 | { |
5a486834 | 11166 | if (cfun->machine->load_label_num_insns == 0) |
0c433c31 RS |
11167 | { |
11168 | mips_process_load_label (pc_rtx); | |
5a486834 | 11169 | cfun->machine->load_label_num_insns = mips_multi_num_insns; |
0c433c31 | 11170 | } |
5a486834 | 11171 | return cfun->machine->load_label_num_insns; |
0c433c31 RS |
11172 | } |
11173 | ||
11174 | /* Emit an asm sequence to start a noat block and load the address | |
11175 | of a label into $1. */ | |
11176 | ||
11177 | void | |
11178 | mips_output_load_label (rtx target) | |
11179 | { | |
11180 | mips_push_asm_switch (&mips_noat); | |
11181 | if (TARGET_EXPLICIT_RELOCS) | |
11182 | { | |
11183 | mips_process_load_label (target); | |
11184 | mips_multi_write (); | |
11185 | } | |
11186 | else | |
11187 | { | |
11188 | if (Pmode == DImode) | |
11189 | output_asm_insn ("dla\t%@,%0", &target); | |
11190 | else | |
11191 | output_asm_insn ("la\t%@,%0", &target); | |
11192 | } | |
11193 | } | |
11194 | ||
ab77a036 RS |
11195 | /* Return the length of INSN. LENGTH is the initial length computed by |
11196 | attributes in the machine-description file. */ | |
97ab1175 | 11197 | |
ab77a036 RS |
11198 | int |
11199 | mips_adjust_insn_length (rtx insn, int length) | |
cff9f8d5 | 11200 | { |
0c433c31 RS |
11201 | /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length |
11202 | of a PIC long-branch sequence. Substitute the correct value. */ | |
11203 | if (length == MAX_PIC_BRANCH_LENGTH | |
11204 | && INSN_CODE (insn) >= 0 | |
11205 | && get_attr_type (insn) == TYPE_BRANCH) | |
11206 | { | |
11207 | /* Add the branch-over instruction and its delay slot, if this | |
11208 | is a conditional branch. */ | |
11209 | length = simplejump_p (insn) ? 0 : 8; | |
11210 | ||
11211 | /* Load the label into $AT and jump to it. Ignore the delay | |
11212 | slot of the jump. */ | |
5a486834 | 11213 | length += 4 * mips_load_label_num_insns() + 4; |
0c433c31 RS |
11214 | } |
11215 | ||
ab77a036 RS |
11216 | /* A unconditional jump has an unfilled delay slot if it is not part |
11217 | of a sequence. A conditional jump normally has a delay slot, but | |
11218 | does not on MIPS16. */ | |
11219 | if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn))) | |
11220 | length += 4; | |
6f428062 | 11221 | |
ab77a036 RS |
11222 | /* See how many nops might be needed to avoid hardware hazards. */ |
11223 | if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0) | |
11224 | switch (get_attr_hazard (insn)) | |
11225 | { | |
11226 | case HAZARD_NONE: | |
11227 | break; | |
6f428062 | 11228 | |
ab77a036 RS |
11229 | case HAZARD_DELAY: |
11230 | length += 4; | |
11231 | break; | |
6f428062 | 11232 | |
ab77a036 RS |
11233 | case HAZARD_HILO: |
11234 | length += 8; | |
11235 | break; | |
11236 | } | |
3d30741b | 11237 | |
65239d20 RS |
11238 | /* In order to make it easier to share MIPS16 and non-MIPS16 patterns, |
11239 | the .md file length attributes are 4-based for both modes. | |
11240 | Adjust the MIPS16 ones here. */ | |
ab77a036 RS |
11241 | if (TARGET_MIPS16) |
11242 | length /= 2; | |
3d30741b | 11243 | |
ab77a036 | 11244 | return length; |
cff9f8d5 AH |
11245 | } |
11246 | ||
ab77a036 | 11247 | /* Return the assembly code for INSN, which has the operands given by |
0c433c31 RS |
11248 | OPERANDS, and which branches to OPERANDS[0] if some condition is true. |
11249 | BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0] | |
ab77a036 RS |
11250 | is in range of a direct branch. BRANCH_IF_FALSE is an inverted |
11251 | version of BRANCH_IF_TRUE. */ | |
a6008bd8 | 11252 | |
ab77a036 RS |
11253 | const char * |
11254 | mips_output_conditional_branch (rtx insn, rtx *operands, | |
11255 | const char *branch_if_true, | |
11256 | const char *branch_if_false) | |
a6008bd8 | 11257 | { |
ab77a036 RS |
11258 | unsigned int length; |
11259 | rtx taken, not_taken; | |
a6008bd8 | 11260 | |
0c433c31 | 11261 | gcc_assert (LABEL_P (operands[0])); |
4cba945d | 11262 | |
ab77a036 RS |
11263 | length = get_attr_length (insn); |
11264 | if (length <= 8) | |
11265 | { | |
11266 | /* Just a simple conditional branch. */ | |
11267 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
11268 | return branch_if_true; | |
11269 | } | |
a6008bd8 | 11270 | |
ab77a036 RS |
11271 | /* Generate a reversed branch around a direct jump. This fallback does |
11272 | not use branch-likely instructions. */ | |
11273 | mips_branch_likely = false; | |
11274 | not_taken = gen_label_rtx (); | |
0c433c31 | 11275 | taken = operands[0]; |
2bcb2ab3 | 11276 | |
ab77a036 | 11277 | /* Generate the reversed branch to NOT_TAKEN. */ |
0c433c31 | 11278 | operands[0] = not_taken; |
ab77a036 | 11279 | output_asm_insn (branch_if_false, operands); |
3d30741b | 11280 | |
ab77a036 RS |
11281 | /* If INSN has a delay slot, we must provide delay slots for both the |
11282 | branch to NOT_TAKEN and the conditional jump. We must also ensure | |
11283 | that INSN's delay slot is executed in the appropriate cases. */ | |
11284 | if (final_sequence) | |
a6008bd8 | 11285 | { |
ab77a036 RS |
11286 | /* This first delay slot will always be executed, so use INSN's |
11287 | delay slot if is not annulled. */ | |
11288 | if (!INSN_ANNULLED_BRANCH_P (insn)) | |
11289 | { | |
11290 | final_scan_insn (XVECEXP (final_sequence, 0, 1), | |
11291 | asm_out_file, optimize, 1, NULL); | |
11292 | INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; | |
11293 | } | |
11294 | else | |
11295 | output_asm_insn ("nop", 0); | |
11296 | fprintf (asm_out_file, "\n"); | |
a6008bd8 | 11297 | } |
cafe096b | 11298 | |
ab77a036 | 11299 | /* Output the unconditional branch to TAKEN. */ |
0c433c31 RS |
11300 | if (TARGET_ABSOLUTE_JUMPS) |
11301 | output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken); | |
ab77a036 | 11302 | else |
b8eb88d0 | 11303 | { |
0c433c31 | 11304 | mips_output_load_label (taken); |
ab77a036 | 11305 | output_asm_insn ("jr\t%@%]%/", 0); |
b8eb88d0 ILT |
11306 | } |
11307 | ||
ab77a036 RS |
11308 | /* Now deal with its delay slot; see above. */ |
11309 | if (final_sequence) | |
8214bf98 | 11310 | { |
ab77a036 RS |
11311 | /* This delay slot will only be executed if the branch is taken. |
11312 | Use INSN's delay slot if is annulled. */ | |
11313 | if (INSN_ANNULLED_BRANCH_P (insn)) | |
11314 | { | |
11315 | final_scan_insn (XVECEXP (final_sequence, 0, 1), | |
11316 | asm_out_file, optimize, 1, NULL); | |
11317 | INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; | |
11318 | } | |
11319 | else | |
11320 | output_asm_insn ("nop", 0); | |
11321 | fprintf (asm_out_file, "\n"); | |
2bcb2ab3 GK |
11322 | } |
11323 | ||
ab77a036 | 11324 | /* Output NOT_TAKEN. */ |
65239d20 RS |
11325 | targetm.asm_out.internal_label (asm_out_file, "L", |
11326 | CODE_LABEL_NUMBER (not_taken)); | |
ab77a036 | 11327 | return ""; |
46299de9 | 11328 | } |
d604bca3 | 11329 | |
0c433c31 | 11330 | /* Return the assembly code for INSN, which branches to OPERANDS[0] |
65239d20 | 11331 | if some ordering condition is true. The condition is given by |
0c433c31 RS |
11332 | OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of |
11333 | OPERANDS[1]. OPERANDS[2] is the comparison's first operand; | |
ab77a036 | 11334 | its second is always zero. */ |
4977bab6 | 11335 | |
ab77a036 RS |
11336 | const char * |
11337 | mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p) | |
4977bab6 | 11338 | { |
ab77a036 | 11339 | const char *branch[2]; |
62d9f2e9 | 11340 | |
0c433c31 | 11341 | /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true. |
ab77a036 | 11342 | Make BRANCH[0] branch on the inverse condition. */ |
0c433c31 | 11343 | switch (GET_CODE (operands[1])) |
118ea793 | 11344 | { |
ab77a036 RS |
11345 | /* These cases are equivalent to comparisons against zero. */ |
11346 | case LEU: | |
11347 | inverted_p = !inverted_p; | |
11348 | /* Fall through. */ | |
11349 | case GTU: | |
0c433c31 RS |
11350 | branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0"); |
11351 | branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0"); | |
ab77a036 | 11352 | break; |
118ea793 | 11353 | |
ab77a036 RS |
11354 | /* These cases are always true or always false. */ |
11355 | case LTU: | |
11356 | inverted_p = !inverted_p; | |
11357 | /* Fall through. */ | |
11358 | case GEU: | |
0c433c31 RS |
11359 | branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0"); |
11360 | branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0"); | |
ab77a036 | 11361 | break; |
118ea793 CF |
11362 | |
11363 | default: | |
0c433c31 RS |
11364 | branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0"); |
11365 | branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0"); | |
ab77a036 | 11366 | break; |
118ea793 | 11367 | } |
ab77a036 | 11368 | return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); |
06a4ab70 | 11369 | } |
ab77a036 | 11370 | \f |
6f5a62e9 RS |
11371 | /* Start a block of code that needs access to the LL, SC and SYNC |
11372 | instructions. */ | |
11373 | ||
11374 | static void | |
11375 | mips_start_ll_sc_sync_block (void) | |
11376 | { | |
11377 | if (!ISA_HAS_LL_SC) | |
11378 | { | |
11379 | output_asm_insn (".set\tpush", 0); | |
11380 | output_asm_insn (".set\tmips2", 0); | |
11381 | } | |
11382 | } | |
11383 | ||
11384 | /* End a block started by mips_start_ll_sc_sync_block. */ | |
11385 | ||
11386 | static void | |
11387 | mips_end_ll_sc_sync_block (void) | |
11388 | { | |
11389 | if (!ISA_HAS_LL_SC) | |
11390 | output_asm_insn (".set\tpop", 0); | |
11391 | } | |
11392 | ||
11393 | /* Output and/or return the asm template for a sync instruction. */ | |
ee9a72e5 JK |
11394 | |
11395 | const char * | |
6f5a62e9 | 11396 | mips_output_sync (void) |
ee9a72e5 | 11397 | { |
6f5a62e9 RS |
11398 | mips_start_ll_sc_sync_block (); |
11399 | output_asm_insn ("sync", 0); | |
11400 | mips_end_ll_sc_sync_block (); | |
11401 | return ""; | |
11402 | } | |
40a4a37b | 11403 | |
6f5a62e9 RS |
11404 | /* Return the asm template associated with sync_insn1 value TYPE. |
11405 | IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */ | |
068ca03a | 11406 | |
6f5a62e9 RS |
11407 | static const char * |
11408 | mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p) | |
11409 | { | |
11410 | switch (type) | |
11411 | { | |
11412 | case SYNC_INSN1_MOVE: | |
11413 | return "move\t%0,%z2"; | |
11414 | case SYNC_INSN1_LI: | |
11415 | return "li\t%0,%2"; | |
11416 | case SYNC_INSN1_ADDU: | |
11417 | return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2"; | |
11418 | case SYNC_INSN1_ADDIU: | |
11419 | return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2"; | |
11420 | case SYNC_INSN1_SUBU: | |
11421 | return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2"; | |
11422 | case SYNC_INSN1_AND: | |
11423 | return "and\t%0,%1,%z2"; | |
11424 | case SYNC_INSN1_ANDI: | |
11425 | return "andi\t%0,%1,%2"; | |
11426 | case SYNC_INSN1_OR: | |
11427 | return "or\t%0,%1,%z2"; | |
11428 | case SYNC_INSN1_ORI: | |
11429 | return "ori\t%0,%1,%2"; | |
11430 | case SYNC_INSN1_XOR: | |
11431 | return "xor\t%0,%1,%z2"; | |
11432 | case SYNC_INSN1_XORI: | |
11433 | return "xori\t%0,%1,%2"; | |
11434 | } | |
11435 | gcc_unreachable (); | |
11436 | } | |
11437 | ||
11438 | /* Return the asm template associated with sync_insn2 value TYPE. */ | |
11439 | ||
11440 | static const char * | |
11441 | mips_sync_insn2_template (enum attr_sync_insn2 type) | |
11442 | { | |
11443 | switch (type) | |
11444 | { | |
11445 | case SYNC_INSN2_NOP: | |
11446 | gcc_unreachable (); | |
11447 | case SYNC_INSN2_AND: | |
11448 | return "and\t%0,%1,%z2"; | |
11449 | case SYNC_INSN2_XOR: | |
11450 | return "xor\t%0,%1,%z2"; | |
11451 | case SYNC_INSN2_NOT: | |
11452 | return "nor\t%0,%1,%."; | |
11453 | } | |
11454 | gcc_unreachable (); | |
11455 | } | |
11456 | ||
11457 | /* OPERANDS are the operands to a sync loop instruction and INDEX is | |
11458 | the value of the one of the sync_* attributes. Return the operand | |
11459 | referred to by the attribute, or DEFAULT_VALUE if the insn doesn't | |
11460 | have the associated attribute. */ | |
11461 | ||
11462 | static rtx | |
11463 | mips_get_sync_operand (rtx *operands, int index, rtx default_value) | |
11464 | { | |
11465 | if (index > 0) | |
11466 | default_value = operands[index - 1]; | |
11467 | return default_value; | |
11468 | } | |
11469 | ||
11470 | /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn | |
11471 | sequence for it. */ | |
11472 | ||
11473 | static void | |
11474 | mips_process_sync_loop (rtx insn, rtx *operands) | |
11475 | { | |
11476 | rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask; | |
11477 | rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3; | |
11478 | unsigned int tmp3_insn; | |
11479 | enum attr_sync_insn1 insn1; | |
11480 | enum attr_sync_insn2 insn2; | |
11481 | bool is_64bit_p; | |
11482 | ||
11483 | /* Read an operand from the sync_WHAT attribute and store it in | |
11484 | variable WHAT. DEFAULT is the default value if no attribute | |
11485 | is specified. */ | |
11486 | #define READ_OPERAND(WHAT, DEFAULT) \ | |
11487 | WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \ | |
11488 | DEFAULT) | |
11489 | ||
11490 | /* Read the memory. */ | |
11491 | READ_OPERAND (mem, 0); | |
11492 | gcc_assert (mem); | |
11493 | is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64); | |
11494 | ||
11495 | /* Read the other attributes. */ | |
11496 | at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM); | |
11497 | READ_OPERAND (oldval, at); | |
11498 | READ_OPERAND (newval, at); | |
11499 | READ_OPERAND (inclusive_mask, 0); | |
11500 | READ_OPERAND (exclusive_mask, 0); | |
11501 | READ_OPERAND (required_oldval, 0); | |
11502 | READ_OPERAND (insn1_op2, 0); | |
11503 | insn1 = get_attr_sync_insn1 (insn); | |
11504 | insn2 = get_attr_sync_insn2 (insn); | |
11505 | ||
11506 | mips_multi_start (); | |
11507 | ||
11508 | /* Output the release side of the memory barrier. */ | |
11509 | if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES) | |
916e9b31 DD |
11510 | { |
11511 | if (required_oldval == 0 && TARGET_OCTEON) | |
11512 | { | |
11513 | /* Octeon doesn't reorder reads, so a full barrier can be | |
11514 | created by using SYNCW to order writes combined with the | |
11515 | write from the following SC. When the SC successfully | |
11516 | completes, we know that all preceding writes are also | |
11517 | committed to the coherent memory system. It is possible | |
11518 | for a single SYNCW to fail, but a pair of them will never | |
11519 | fail, so we use two. */ | |
11520 | mips_multi_add_insn ("syncw", NULL); | |
11521 | mips_multi_add_insn ("syncw", NULL); | |
11522 | } | |
11523 | else | |
11524 | mips_multi_add_insn ("sync", NULL); | |
11525 | } | |
6f5a62e9 RS |
11526 | |
11527 | /* Output the branch-back label. */ | |
11528 | mips_multi_add_label ("1:"); | |
11529 | ||
11530 | /* OLDVAL = *MEM. */ | |
11531 | mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1", | |
11532 | oldval, mem, NULL); | |
11533 | ||
11534 | /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */ | |
11535 | if (required_oldval) | |
11536 | { | |
11537 | if (inclusive_mask == 0) | |
11538 | tmp1 = oldval; | |
11539 | else | |
11540 | { | |
11541 | gcc_assert (oldval != at); | |
11542 | mips_multi_add_insn ("and\t%0,%1,%2", | |
11543 | at, oldval, inclusive_mask, NULL); | |
11544 | tmp1 = at; | |
11545 | } | |
11546 | mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL); | |
11547 | } | |
11548 | ||
11549 | /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */ | |
11550 | if (exclusive_mask == 0) | |
11551 | tmp1 = const0_rtx; | |
11552 | else | |
11553 | { | |
11554 | gcc_assert (oldval != at); | |
11555 | mips_multi_add_insn ("and\t%0,%1,%z2", | |
11556 | at, oldval, exclusive_mask, NULL); | |
11557 | tmp1 = at; | |
11558 | } | |
11559 | ||
11560 | /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2). | |
11561 | ||
11562 | We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit | |
11563 | at least one instruction in that case. */ | |
11564 | if (insn1 == SYNC_INSN1_MOVE | |
11565 | && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP)) | |
11566 | tmp2 = insn1_op2; | |
11567 | else | |
068ca03a | 11568 | { |
6f5a62e9 RS |
11569 | mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p), |
11570 | newval, oldval, insn1_op2, NULL); | |
11571 | tmp2 = newval; | |
068ca03a | 11572 | } |
6f5a62e9 RS |
11573 | |
11574 | /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */ | |
11575 | if (insn2 == SYNC_INSN2_NOP) | |
11576 | tmp3 = tmp2; | |
11577 | else | |
11578 | { | |
11579 | mips_multi_add_insn (mips_sync_insn2_template (insn2), | |
11580 | newval, tmp2, inclusive_mask, NULL); | |
11581 | tmp3 = newval; | |
11582 | } | |
11583 | tmp3_insn = mips_multi_last_index (); | |
11584 | ||
11585 | /* $AT = $TMP1 | $TMP3. */ | |
11586 | if (tmp1 == const0_rtx || tmp3 == const0_rtx) | |
11587 | { | |
11588 | mips_multi_set_operand (tmp3_insn, 0, at); | |
11589 | tmp3 = at; | |
11590 | } | |
11591 | else | |
11592 | { | |
11593 | gcc_assert (tmp1 != tmp3); | |
11594 | mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL); | |
11595 | } | |
11596 | ||
11597 | /* if (!commit (*MEM = $AT)) goto 1. | |
11598 | ||
11599 | This will sometimes be a delayed branch; see the write code below | |
11600 | for details. */ | |
11601 | mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); | |
11602 | mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); | |
11603 | ||
11604 | /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ | |
11605 | if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) | |
11606 | { | |
11607 | mips_multi_copy_insn (tmp3_insn); | |
11608 | mips_multi_set_operand (mips_multi_last_index (), 0, newval); | |
11609 | } | |
11610 | else | |
11611 | mips_multi_add_insn ("nop", NULL); | |
11612 | ||
11613 | /* Output the acquire side of the memory barrier. */ | |
11614 | if (TARGET_SYNC_AFTER_SC) | |
11615 | mips_multi_add_insn ("sync", NULL); | |
11616 | ||
11617 | /* Output the exit label, if needed. */ | |
11618 | if (required_oldval) | |
11619 | mips_multi_add_label ("2:"); | |
11620 | ||
11621 | #undef READ_OPERAND | |
11622 | } | |
11623 | ||
11624 | /* Output and/or return the asm template for sync loop INSN, which has | |
11625 | the operands given by OPERANDS. */ | |
11626 | ||
11627 | const char * | |
11628 | mips_output_sync_loop (rtx insn, rtx *operands) | |
11629 | { | |
11630 | mips_process_sync_loop (insn, operands); | |
11631 | ||
11632 | /* Use branch-likely instructions to work around the LL/SC R10000 | |
11633 | errata. */ | |
11634 | mips_branch_likely = TARGET_FIX_R10000; | |
11635 | ||
11636 | mips_push_asm_switch (&mips_noreorder); | |
11637 | mips_push_asm_switch (&mips_nomacro); | |
11638 | mips_push_asm_switch (&mips_noat); | |
11639 | mips_start_ll_sc_sync_block (); | |
11640 | ||
11641 | mips_multi_write (); | |
11642 | ||
11643 | mips_end_ll_sc_sync_block (); | |
11644 | mips_pop_asm_switch (&mips_noat); | |
11645 | mips_pop_asm_switch (&mips_nomacro); | |
11646 | mips_pop_asm_switch (&mips_noreorder); | |
11647 | ||
11648 | return ""; | |
11649 | } | |
11650 | ||
11651 | /* Return the number of individual instructions in sync loop INSN, | |
11652 | which has the operands given by OPERANDS. */ | |
11653 | ||
11654 | unsigned int | |
11655 | mips_sync_loop_insns (rtx insn, rtx *operands) | |
11656 | { | |
11657 | mips_process_sync_loop (insn, operands); | |
11658 | return mips_multi_num_insns; | |
ee9a72e5 JK |
11659 | } |
11660 | \f | |
65239d20 RS |
11661 | /* Return the assembly code for DIV or DDIV instruction DIVISION, which has |
11662 | the operands given by OPERANDS. Add in a divide-by-zero check if needed. | |
9fc777ad | 11663 | |
ab77a036 RS |
11664 | When working around R4000 and R4400 errata, we need to make sure that |
11665 | the division is not immediately followed by a shift[1][2]. We also | |
11666 | need to stop the division from being put into a branch delay slot[3]. | |
11667 | The easiest way to avoid both problems is to add a nop after the | |
11668 | division. When a divide-by-zero check is needed, this nop can be | |
11669 | used to fill the branch delay slot. | |
9fc777ad | 11670 | |
ab77a036 RS |
11671 | [1] If a double-word or a variable shift executes immediately |
11672 | after starting an integer division, the shift may give an | |
11673 | incorrect result. See quotations of errata #16 and #28 from | |
11674 | "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" | |
11675 | in mips.md for details. | |
9fc777ad | 11676 | |
ab77a036 RS |
11677 | [2] A similar bug to [1] exists for all revisions of the |
11678 | R4000 and the R4400 when run in an MC configuration. | |
11679 | From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0": | |
d34053ed | 11680 | |
ab77a036 | 11681 | "19. In this following sequence: |
2bcb2ab3 | 11682 | |
ab77a036 RS |
11683 | ddiv (or ddivu or div or divu) |
11684 | dsll32 (or dsrl32, dsra32) | |
d6076cee | 11685 | |
ab77a036 RS |
11686 | if an MPT stall occurs, while the divide is slipping the cpu |
11687 | pipeline, then the following double shift would end up with an | |
11688 | incorrect result. | |
2bcb2ab3 | 11689 | |
ab77a036 RS |
11690 | Workaround: The compiler needs to avoid generating any |
11691 | sequence with divide followed by extended double shift." | |
2bcb2ab3 | 11692 | |
ab77a036 RS |
11693 | This erratum is also present in "MIPS R4400MC Errata, Processor |
11694 | Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0 | |
11695 | & 3.0" as errata #10 and #4, respectively. | |
2bcb2ab3 | 11696 | |
ab77a036 RS |
11697 | [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" |
11698 | (also valid for MIPS R4000MC processors): | |
2bcb2ab3 | 11699 | |
ab77a036 | 11700 | "52. R4000SC: This bug does not apply for the R4000PC. |
2bcb2ab3 | 11701 | |
ab77a036 | 11702 | There are two flavors of this bug: |
2bcb2ab3 | 11703 | |
ab77a036 RS |
11704 | 1) If the instruction just after divide takes an RF exception |
11705 | (tlb-refill, tlb-invalid) and gets an instruction cache | |
11706 | miss (both primary and secondary) and the line which is | |
11707 | currently in secondary cache at this index had the first | |
11708 | data word, where the bits 5..2 are set, then R4000 would | |
11709 | get a wrong result for the div. | |
a38e0142 | 11710 | |
ab77a036 RS |
11711 | ##1 |
11712 | nop | |
11713 | div r8, r9 | |
11714 | ------------------- # end-of page. -tlb-refill | |
11715 | nop | |
11716 | ##2 | |
11717 | nop | |
11718 | div r8, r9 | |
11719 | ------------------- # end-of page. -tlb-invalid | |
11720 | nop | |
a38e0142 | 11721 | |
ab77a036 RS |
11722 | 2) If the divide is in the taken branch delay slot, where the |
11723 | target takes RF exception and gets an I-cache miss for the | |
11724 | exception vector or where I-cache miss occurs for the | |
11725 | target address, under the above mentioned scenarios, the | |
11726 | div would get wrong results. | |
a38e0142 | 11727 | |
ab77a036 RS |
11728 | ##1 |
11729 | j r2 # to next page mapped or unmapped | |
11730 | div r8,r9 # this bug would be there as long | |
11731 | # as there is an ICache miss and | |
11732 | nop # the "data pattern" is present | |
2bcb2ab3 | 11733 | |
ab77a036 RS |
11734 | ##2 |
11735 | beq r0, r0, NextPage # to Next page | |
11736 | div r8,r9 | |
11737 | nop | |
a38e0142 | 11738 | |
ab77a036 RS |
11739 | This bug is present for div, divu, ddiv, and ddivu |
11740 | instructions. | |
a38e0142 | 11741 | |
ab77a036 RS |
11742 | Workaround: For item 1), OS could make sure that the next page |
11743 | after the divide instruction is also mapped. For item 2), the | |
11744 | compiler could make sure that the divide instruction is not in | |
11745 | the branch delay slot." | |
2bcb2ab3 | 11746 | |
ab77a036 RS |
11747 | These processors have PRId values of 0x00004220 and 0x00004300 for |
11748 | the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */ | |
2bcb2ab3 | 11749 | |
ab77a036 RS |
11750 | const char * |
11751 | mips_output_division (const char *division, rtx *operands) | |
2bcb2ab3 | 11752 | { |
ab77a036 | 11753 | const char *s; |
2bcb2ab3 | 11754 | |
ab77a036 RS |
11755 | s = division; |
11756 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) | |
2bcb2ab3 | 11757 | { |
ab77a036 RS |
11758 | output_asm_insn (s, operands); |
11759 | s = "nop"; | |
2bcb2ab3 | 11760 | } |
ab77a036 | 11761 | if (TARGET_CHECK_ZERO_DIV) |
3c7404d3 | 11762 | { |
ab77a036 RS |
11763 | if (TARGET_MIPS16) |
11764 | { | |
11765 | output_asm_insn (s, operands); | |
11766 | s = "bnez\t%2,1f\n\tbreak\t7\n1:"; | |
11767 | } | |
11768 | else if (GENERATE_DIVIDE_TRAPS) | |
67e67979 DU |
11769 | { |
11770 | /* Avoid long replay penalty on load miss by putting the trap before | |
11771 | the divide. */ | |
11772 | if (TUNE_74K) | |
11773 | output_asm_insn ("teq\t%2,%.,7", operands); | |
11774 | else | |
11775 | { | |
11776 | output_asm_insn (s, operands); | |
11777 | s = "teq\t%2,%.,7"; | |
11778 | } | |
11779 | } | |
ab77a036 RS |
11780 | else |
11781 | { | |
11782 | output_asm_insn ("%(bne\t%2,%.,1f", operands); | |
11783 | output_asm_insn (s, operands); | |
11784 | s = "break\t7%)\n1:"; | |
11785 | } | |
3c7404d3 | 11786 | } |
ab77a036 RS |
11787 | return s; |
11788 | } | |
11789 | \f | |
65239d20 RS |
11790 | /* Return true if IN_INSN is a multiply-add or multiply-subtract |
11791 | instruction and if OUT_INSN assigns to the accumulator operand. */ | |
2bcb2ab3 | 11792 | |
ab77a036 | 11793 | bool |
65239d20 | 11794 | mips_linked_madd_p (rtx out_insn, rtx in_insn) |
ab77a036 RS |
11795 | { |
11796 | rtx x; | |
2bcb2ab3 | 11797 | |
65239d20 | 11798 | x = single_set (in_insn); |
ab77a036 RS |
11799 | if (x == 0) |
11800 | return false; | |
2bcb2ab3 | 11801 | |
ab77a036 | 11802 | x = SET_SRC (x); |
2bcb2ab3 | 11803 | |
ab77a036 RS |
11804 | if (GET_CODE (x) == PLUS |
11805 | && GET_CODE (XEXP (x, 0)) == MULT | |
65239d20 | 11806 | && reg_set_p (XEXP (x, 1), out_insn)) |
ab77a036 | 11807 | return true; |
2bcb2ab3 | 11808 | |
ab77a036 RS |
11809 | if (GET_CODE (x) == MINUS |
11810 | && GET_CODE (XEXP (x, 1)) == MULT | |
65239d20 | 11811 | && reg_set_p (XEXP (x, 0), out_insn)) |
ab77a036 | 11812 | return true; |
2bcb2ab3 | 11813 | |
ab77a036 | 11814 | return false; |
2bcb2ab3 GK |
11815 | } |
11816 | ||
65239d20 RS |
11817 | /* True if the dependency between OUT_INSN and IN_INSN is on the store |
11818 | data rather than the address. We need this because the cprestore | |
11819 | pattern is type "store", but is defined using an UNSPEC_VOLATILE, | |
11820 | which causes the default routine to abort. We just return false | |
11821 | for that case. */ | |
2bcb2ab3 | 11822 | |
65239d20 | 11823 | bool |
ab77a036 | 11824 | mips_store_data_bypass_p (rtx out_insn, rtx in_insn) |
2bcb2ab3 | 11825 | { |
ab77a036 RS |
11826 | if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) |
11827 | return false; | |
2bcb2ab3 | 11828 | |
65239d20 | 11829 | return !store_data_bypass_p (out_insn, in_insn); |
ab77a036 RS |
11830 | } |
11831 | \f | |
58684fa0 MK |
11832 | |
11833 | /* Variables and flags used in scheduler hooks when tuning for | |
11834 | Loongson 2E/2F. */ | |
11835 | static struct | |
11836 | { | |
11837 | /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch | |
11838 | strategy. */ | |
11839 | ||
11840 | /* If true, then next ALU1/2 instruction will go to ALU1. */ | |
11841 | bool alu1_turn_p; | |
11842 | ||
11843 | /* If true, then next FALU1/2 unstruction will go to FALU1. */ | |
11844 | bool falu1_turn_p; | |
11845 | ||
11846 | /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */ | |
11847 | int alu1_core_unit_code; | |
11848 | int alu2_core_unit_code; | |
11849 | int falu1_core_unit_code; | |
11850 | int falu2_core_unit_code; | |
11851 | ||
11852 | /* True if current cycle has a multi instruction. | |
11853 | This flag is used in mips_ls2_dfa_post_advance_cycle. */ | |
11854 | bool cycle_has_multi_p; | |
11855 | ||
11856 | /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units. | |
11857 | These are used in mips_ls2_dfa_post_advance_cycle to initialize | |
11858 | DFA state. | |
11859 | E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2 | |
11860 | instruction to go ALU1. */ | |
11861 | rtx alu1_turn_enabled_insn; | |
11862 | rtx alu2_turn_enabled_insn; | |
11863 | rtx falu1_turn_enabled_insn; | |
11864 | rtx falu2_turn_enabled_insn; | |
11865 | } mips_ls2; | |
11866 | ||
ab77a036 RS |
11867 | /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output |
11868 | dependencies have no cost, except on the 20Kc where output-dependence | |
11869 | is treated like input-dependence. */ | |
2bcb2ab3 | 11870 | |
ab77a036 RS |
11871 | static int |
11872 | mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, | |
11873 | rtx dep ATTRIBUTE_UNUSED, int cost) | |
11874 | { | |
11875 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT | |
11876 | && TUNE_20KC) | |
11877 | return cost; | |
11878 | if (REG_NOTE_KIND (link) != 0) | |
11879 | return 0; | |
11880 | return cost; | |
11881 | } | |
a38e0142 | 11882 | |
ab77a036 RS |
11883 | /* Return the number of instructions that can be issued per cycle. */ |
11884 | ||
11885 | static int | |
11886 | mips_issue_rate (void) | |
a38e0142 | 11887 | { |
ab77a036 | 11888 | switch (mips_tune) |
a38e0142 | 11889 | { |
ab77a036 RS |
11890 | case PROCESSOR_74KC: |
11891 | case PROCESSOR_74KF2_1: | |
11892 | case PROCESSOR_74KF1_1: | |
11893 | case PROCESSOR_74KF3_2: | |
11894 | /* The 74k is not strictly quad-issue cpu, but can be seen as one | |
11895 | by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns, | |
65239d20 RS |
11896 | but in reality only a maximum of 3 insns can be issued as |
11897 | floating-point loads and stores also require a slot in the | |
11898 | AGEN pipe. */ | |
7a3446ec JK |
11899 | case PROCESSOR_R10000: |
11900 | /* All R10K Processors are quad-issue (being the first MIPS | |
11901 | processors to support this feature). */ | |
11902 | return 4; | |
ab77a036 RS |
11903 | |
11904 | case PROCESSOR_20KC: | |
11905 | case PROCESSOR_R4130: | |
11906 | case PROCESSOR_R5400: | |
11907 | case PROCESSOR_R5500: | |
11908 | case PROCESSOR_R7000: | |
11909 | case PROCESSOR_R9000: | |
ce00be9e | 11910 | case PROCESSOR_OCTEON: |
ab77a036 RS |
11911 | return 2; |
11912 | ||
11913 | case PROCESSOR_SB1: | |
11914 | case PROCESSOR_SB1A: | |
11915 | /* This is actually 4, but we get better performance if we claim 3. | |
11916 | This is partly because of unwanted speculative code motion with the | |
11917 | larger number, and partly because in most common cases we can't | |
11918 | reach the theoretical max of 4. */ | |
11919 | return 3; | |
11920 | ||
58684fa0 MK |
11921 | case PROCESSOR_LOONGSON_2E: |
11922 | case PROCESSOR_LOONGSON_2F: | |
98824c6f | 11923 | case PROCESSOR_LOONGSON_3A: |
58684fa0 MK |
11924 | return 4; |
11925 | ||
ab77a036 RS |
11926 | default: |
11927 | return 1; | |
a38e0142 SL |
11928 | } |
11929 | } | |
11930 | ||
58684fa0 MK |
11931 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */ |
11932 | ||
11933 | static void | |
11934 | mips_ls2_init_dfa_post_cycle_insn (void) | |
11935 | { | |
11936 | start_sequence (); | |
11937 | emit_insn (gen_ls2_alu1_turn_enabled_insn ()); | |
11938 | mips_ls2.alu1_turn_enabled_insn = get_insns (); | |
11939 | end_sequence (); | |
11940 | ||
11941 | start_sequence (); | |
11942 | emit_insn (gen_ls2_alu2_turn_enabled_insn ()); | |
11943 | mips_ls2.alu2_turn_enabled_insn = get_insns (); | |
11944 | end_sequence (); | |
11945 | ||
11946 | start_sequence (); | |
11947 | emit_insn (gen_ls2_falu1_turn_enabled_insn ()); | |
11948 | mips_ls2.falu1_turn_enabled_insn = get_insns (); | |
11949 | end_sequence (); | |
11950 | ||
11951 | start_sequence (); | |
11952 | emit_insn (gen_ls2_falu2_turn_enabled_insn ()); | |
11953 | mips_ls2.falu2_turn_enabled_insn = get_insns (); | |
11954 | end_sequence (); | |
11955 | ||
11956 | mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core"); | |
11957 | mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core"); | |
11958 | mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core"); | |
11959 | mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core"); | |
11960 | } | |
11961 | ||
11962 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook. | |
11963 | Init data used in mips_dfa_post_advance_cycle. */ | |
11964 | ||
11965 | static void | |
11966 | mips_init_dfa_post_cycle_insn (void) | |
11967 | { | |
11968 | if (TUNE_LOONGSON_2EF) | |
11969 | mips_ls2_init_dfa_post_cycle_insn (); | |
11970 | } | |
11971 | ||
11972 | /* Initialize STATE when scheduling for Loongson 2E/2F. | |
11973 | Support round-robin dispatch scheme by enabling only one of | |
11974 | ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions | |
11975 | respectively. */ | |
11976 | ||
11977 | static void | |
11978 | mips_ls2_dfa_post_advance_cycle (state_t state) | |
11979 | { | |
11980 | if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code)) | |
11981 | { | |
11982 | /* Though there are no non-pipelined ALU1 insns, | |
11983 | we can get an instruction of type 'multi' before reload. */ | |
11984 | gcc_assert (mips_ls2.cycle_has_multi_p); | |
11985 | mips_ls2.alu1_turn_p = false; | |
11986 | } | |
11987 | ||
11988 | mips_ls2.cycle_has_multi_p = false; | |
11989 | ||
11990 | if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code)) | |
11991 | /* We have a non-pipelined alu instruction in the core, | |
11992 | adjust round-robin counter. */ | |
11993 | mips_ls2.alu1_turn_p = true; | |
11994 | ||
11995 | if (mips_ls2.alu1_turn_p) | |
11996 | { | |
11997 | if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0) | |
11998 | gcc_unreachable (); | |
11999 | } | |
12000 | else | |
12001 | { | |
12002 | if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0) | |
12003 | gcc_unreachable (); | |
12004 | } | |
12005 | ||
12006 | if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code)) | |
12007 | { | |
12008 | /* There are no non-pipelined FALU1 insns. */ | |
12009 | gcc_unreachable (); | |
12010 | mips_ls2.falu1_turn_p = false; | |
12011 | } | |
12012 | ||
12013 | if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code)) | |
12014 | /* We have a non-pipelined falu instruction in the core, | |
12015 | adjust round-robin counter. */ | |
12016 | mips_ls2.falu1_turn_p = true; | |
12017 | ||
12018 | if (mips_ls2.falu1_turn_p) | |
12019 | { | |
12020 | if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0) | |
12021 | gcc_unreachable (); | |
12022 | } | |
12023 | else | |
12024 | { | |
12025 | if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0) | |
12026 | gcc_unreachable (); | |
12027 | } | |
12028 | } | |
12029 | ||
12030 | /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE. | |
12031 | This hook is being called at the start of each cycle. */ | |
12032 | ||
12033 | static void | |
12034 | mips_dfa_post_advance_cycle (void) | |
12035 | { | |
12036 | if (TUNE_LOONGSON_2EF) | |
12037 | mips_ls2_dfa_post_advance_cycle (curr_state); | |
12038 | } | |
12039 | ||
65239d20 | 12040 | /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should |
ab77a036 | 12041 | be as wide as the scheduling freedom in the DFA. */ |
2bcb2ab3 | 12042 | |
ab77a036 RS |
12043 | static int |
12044 | mips_multipass_dfa_lookahead (void) | |
12045 | { | |
12046 | /* Can schedule up to 4 of the 6 function units in any one cycle. */ | |
12047 | if (TUNE_SB1) | |
12048 | return 4; | |
2bcb2ab3 | 12049 | |
2b18eb32 | 12050 | if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) |
58684fa0 MK |
12051 | return 4; |
12052 | ||
ce00be9e AN |
12053 | if (TUNE_OCTEON) |
12054 | return 2; | |
12055 | ||
ab77a036 RS |
12056 | return 0; |
12057 | } | |
12058 | \f | |
12059 | /* Remove the instruction at index LOWER from ready queue READY and | |
12060 | reinsert it in front of the instruction at index HIGHER. LOWER must | |
12061 | be <= HIGHER. */ | |
2bcb2ab3 | 12062 | |
ab77a036 RS |
12063 | static void |
12064 | mips_promote_ready (rtx *ready, int lower, int higher) | |
2bcb2ab3 | 12065 | { |
ab77a036 RS |
12066 | rtx new_head; |
12067 | int i; | |
2bcb2ab3 | 12068 | |
ab77a036 RS |
12069 | new_head = ready[lower]; |
12070 | for (i = lower; i < higher; i++) | |
12071 | ready[i] = ready[i + 1]; | |
12072 | ready[i] = new_head; | |
12073 | } | |
2bcb2ab3 | 12074 | |
ab77a036 RS |
12075 | /* If the priority of the instruction at POS2 in the ready queue READY |
12076 | is within LIMIT units of that of the instruction at POS1, swap the | |
12077 | instructions if POS2 is not already less than POS1. */ | |
2bcb2ab3 | 12078 | |
ab77a036 RS |
12079 | static void |
12080 | mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit) | |
12081 | { | |
12082 | if (pos1 < pos2 | |
12083 | && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2])) | |
12084 | { | |
12085 | rtx temp; | |
65239d20 | 12086 | |
ab77a036 RS |
12087 | temp = ready[pos1]; |
12088 | ready[pos1] = ready[pos2]; | |
12089 | ready[pos2] = temp; | |
12090 | } | |
12091 | } | |
12092 | \f | |
12093 | /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction | |
12094 | that may clobber hi or lo. */ | |
ab77a036 | 12095 | static rtx mips_macc_chains_last_hilo; |
2bcb2ab3 | 12096 | |
ab77a036 RS |
12097 | /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has |
12098 | been scheduled, updating mips_macc_chains_last_hilo appropriately. */ | |
2bcb2ab3 | 12099 | |
ab77a036 RS |
12100 | static void |
12101 | mips_macc_chains_record (rtx insn) | |
12102 | { | |
12103 | if (get_attr_may_clobber_hilo (insn)) | |
12104 | mips_macc_chains_last_hilo = insn; | |
12105 | } | |
2bcb2ab3 | 12106 | |
ab77a036 RS |
12107 | /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which |
12108 | has NREADY elements, looking for a multiply-add or multiply-subtract | |
12109 | instruction that is cumulative with mips_macc_chains_last_hilo. | |
12110 | If there is one, promote it ahead of anything else that might | |
12111 | clobber hi or lo. */ | |
2bcb2ab3 | 12112 | |
ab77a036 RS |
12113 | static void |
12114 | mips_macc_chains_reorder (rtx *ready, int nready) | |
12115 | { | |
12116 | int i, j; | |
2bcb2ab3 | 12117 | |
ab77a036 RS |
12118 | if (mips_macc_chains_last_hilo != 0) |
12119 | for (i = nready - 1; i >= 0; i--) | |
12120 | if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i])) | |
12121 | { | |
12122 | for (j = nready - 1; j > i; j--) | |
12123 | if (recog_memoized (ready[j]) >= 0 | |
12124 | && get_attr_may_clobber_hilo (ready[j])) | |
12125 | { | |
12126 | mips_promote_ready (ready, i, j); | |
12127 | break; | |
12128 | } | |
12129 | break; | |
12130 | } | |
12131 | } | |
12132 | \f | |
12133 | /* The last instruction to be scheduled. */ | |
ab77a036 | 12134 | static rtx vr4130_last_insn; |
2bcb2ab3 | 12135 | |
ab77a036 RS |
12136 | /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA |
12137 | points to an rtx that is initially an instruction. Nullify the rtx | |
12138 | if the instruction uses the value of register X. */ | |
2bcb2ab3 | 12139 | |
ab77a036 | 12140 | static void |
65239d20 RS |
12141 | vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, |
12142 | void *data) | |
ab77a036 | 12143 | { |
65239d20 RS |
12144 | rtx *insn_ptr; |
12145 | ||
12146 | insn_ptr = (rtx *) data; | |
ab77a036 RS |
12147 | if (REG_P (x) |
12148 | && *insn_ptr != 0 | |
12149 | && reg_referenced_p (x, PATTERN (*insn_ptr))) | |
12150 | *insn_ptr = 0; | |
12151 | } | |
2bcb2ab3 | 12152 | |
ab77a036 RS |
12153 | /* Return true if there is true register dependence between vr4130_last_insn |
12154 | and INSN. */ | |
2bcb2ab3 | 12155 | |
ab77a036 RS |
12156 | static bool |
12157 | vr4130_true_reg_dependence_p (rtx insn) | |
12158 | { | |
12159 | note_stores (PATTERN (vr4130_last_insn), | |
12160 | vr4130_true_reg_dependence_p_1, &insn); | |
12161 | return insn == 0; | |
12162 | } | |
2bcb2ab3 | 12163 | |
ab77a036 RS |
12164 | /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of |
12165 | the ready queue and that INSN2 is the instruction after it, return | |
12166 | true if it is worth promoting INSN2 ahead of INSN1. Look for cases | |
12167 | in which INSN1 and INSN2 can probably issue in parallel, but for | |
12168 | which (INSN2, INSN1) should be less sensitive to instruction | |
12169 | alignment than (INSN1, INSN2). See 4130.md for more details. */ | |
2bcb2ab3 | 12170 | |
ab77a036 RS |
12171 | static bool |
12172 | vr4130_swap_insns_p (rtx insn1, rtx insn2) | |
12173 | { | |
12174 | sd_iterator_def sd_it; | |
12175 | dep_t dep; | |
2bcb2ab3 | 12176 | |
ab77a036 | 12177 | /* Check for the following case: |
2bcb2ab3 | 12178 | |
ab77a036 RS |
12179 | 1) there is some other instruction X with an anti dependence on INSN1; |
12180 | 2) X has a higher priority than INSN2; and | |
12181 | 3) X is an arithmetic instruction (and thus has no unit restrictions). | |
2bcb2ab3 | 12182 | |
ab77a036 RS |
12183 | If INSN1 is the last instruction blocking X, it would better to |
12184 | choose (INSN1, X) over (INSN2, INSN1). */ | |
12185 | FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep) | |
12186 | if (DEP_TYPE (dep) == REG_DEP_ANTI | |
12187 | && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2) | |
12188 | && recog_memoized (DEP_CON (dep)) >= 0 | |
12189 | && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU) | |
12190 | return false; | |
2bcb2ab3 | 12191 | |
ab77a036 RS |
12192 | if (vr4130_last_insn != 0 |
12193 | && recog_memoized (insn1) >= 0 | |
12194 | && recog_memoized (insn2) >= 0) | |
12195 | { | |
12196 | /* See whether INSN1 and INSN2 use different execution units, | |
12197 | or if they are both ALU-type instructions. If so, they can | |
12198 | probably execute in parallel. */ | |
12199 | enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1); | |
12200 | enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2); | |
12201 | if (class1 != class2 || class1 == VR4130_CLASS_ALU) | |
2bcb2ab3 | 12202 | { |
ab77a036 RS |
12203 | /* If only one of the instructions has a dependence on |
12204 | vr4130_last_insn, prefer to schedule the other one first. */ | |
65239d20 RS |
12205 | bool dep1_p = vr4130_true_reg_dependence_p (insn1); |
12206 | bool dep2_p = vr4130_true_reg_dependence_p (insn2); | |
12207 | if (dep1_p != dep2_p) | |
12208 | return dep1_p; | |
2bcb2ab3 | 12209 | |
ab77a036 RS |
12210 | /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn |
12211 | is not an ALU-type instruction and if INSN1 uses the same | |
12212 | execution unit. (Note that if this condition holds, we already | |
12213 | know that INSN2 uses a different execution unit.) */ | |
12214 | if (class1 != VR4130_CLASS_ALU | |
12215 | && recog_memoized (vr4130_last_insn) >= 0 | |
12216 | && class1 == get_attr_vr4130_class (vr4130_last_insn)) | |
12217 | return true; | |
12218 | } | |
12219 | } | |
12220 | return false; | |
12221 | } | |
2bcb2ab3 | 12222 | |
ab77a036 RS |
12223 | /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready |
12224 | queue with at least two instructions. Swap the first two if | |
12225 | vr4130_swap_insns_p says that it could be worthwhile. */ | |
2bcb2ab3 | 12226 | |
ab77a036 RS |
12227 | static void |
12228 | vr4130_reorder (rtx *ready, int nready) | |
12229 | { | |
12230 | if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2])) | |
12231 | mips_promote_ready (ready, nready - 2, nready - 1); | |
12232 | } | |
12233 | \f | |
12234 | /* Record whether last 74k AGEN instruction was a load or store. */ | |
ab77a036 | 12235 | static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN; |
2bcb2ab3 | 12236 | |
ab77a036 RS |
12237 | /* Initialize mips_last_74k_agen_insn from INSN. A null argument |
12238 | resets to TYPE_UNKNOWN state. */ | |
2bcb2ab3 | 12239 | |
ab77a036 RS |
12240 | static void |
12241 | mips_74k_agen_init (rtx insn) | |
12242 | { | |
006b29ab | 12243 | if (!insn || CALL_P (insn) || JUMP_P (insn)) |
ab77a036 | 12244 | mips_last_74k_agen_insn = TYPE_UNKNOWN; |
65239d20 | 12245 | else |
ab77a036 RS |
12246 | { |
12247 | enum attr_type type = get_attr_type (insn); | |
12248 | if (type == TYPE_LOAD || type == TYPE_STORE) | |
12249 | mips_last_74k_agen_insn = type; | |
12250 | } | |
12251 | } | |
2bcb2ab3 | 12252 | |
ab77a036 RS |
12253 | /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple |
12254 | loads to be grouped together, and multiple stores to be grouped | |
12255 | together. Swap things around in the ready queue to make this happen. */ | |
30244df3 | 12256 | |
ab77a036 RS |
12257 | static void |
12258 | mips_74k_agen_reorder (rtx *ready, int nready) | |
12259 | { | |
12260 | int i; | |
12261 | int store_pos, load_pos; | |
30244df3 | 12262 | |
ab77a036 RS |
12263 | store_pos = -1; |
12264 | load_pos = -1; | |
2bcb2ab3 | 12265 | |
ab77a036 RS |
12266 | for (i = nready - 1; i >= 0; i--) |
12267 | { | |
12268 | rtx insn = ready[i]; | |
12269 | if (USEFUL_INSN_P (insn)) | |
12270 | switch (get_attr_type (insn)) | |
12271 | { | |
12272 | case TYPE_STORE: | |
12273 | if (store_pos == -1) | |
12274 | store_pos = i; | |
12275 | break; | |
2bcb2ab3 | 12276 | |
ab77a036 RS |
12277 | case TYPE_LOAD: |
12278 | if (load_pos == -1) | |
12279 | load_pos = i; | |
12280 | break; | |
2bcb2ab3 | 12281 | |
ab77a036 RS |
12282 | default: |
12283 | break; | |
12284 | } | |
12285 | } | |
2bcb2ab3 | 12286 | |
ab77a036 RS |
12287 | if (load_pos == -1 || store_pos == -1) |
12288 | return; | |
2bcb2ab3 | 12289 | |
ab77a036 | 12290 | switch (mips_last_74k_agen_insn) |
76cbf5bf | 12291 | { |
ab77a036 RS |
12292 | case TYPE_UNKNOWN: |
12293 | /* Prefer to schedule loads since they have a higher latency. */ | |
12294 | case TYPE_LOAD: | |
12295 | /* Swap loads to the front of the queue. */ | |
12296 | mips_maybe_swap_ready (ready, load_pos, store_pos, 4); | |
12297 | break; | |
12298 | case TYPE_STORE: | |
12299 | /* Swap stores to the front of the queue. */ | |
12300 | mips_maybe_swap_ready (ready, store_pos, load_pos, 4); | |
12301 | break; | |
12302 | default: | |
12303 | break; | |
76cbf5bf | 12304 | } |
ab77a036 RS |
12305 | } |
12306 | \f | |
12307 | /* Implement TARGET_SCHED_INIT. */ | |
76cbf5bf | 12308 | |
ab77a036 RS |
12309 | static void |
12310 | mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12311 | int max_ready ATTRIBUTE_UNUSED) | |
12312 | { | |
12313 | mips_macc_chains_last_hilo = 0; | |
12314 | vr4130_last_insn = 0; | |
12315 | mips_74k_agen_init (NULL_RTX); | |
58684fa0 MK |
12316 | |
12317 | /* When scheduling for Loongson2, branch instructions go to ALU1, | |
12318 | therefore basic block is most likely to start with round-robin counter | |
12319 | pointed to ALU2. */ | |
12320 | mips_ls2.alu1_turn_p = false; | |
12321 | mips_ls2.falu1_turn_p = true; | |
2bcb2ab3 GK |
12322 | } |
12323 | ||
646e6f41 | 12324 | /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */ |
76cbf5bf | 12325 | |
646e6f41 JZ |
12326 | static void |
12327 | mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12328 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
76cbf5bf | 12329 | { |
ab77a036 RS |
12330 | if (!reload_completed |
12331 | && TUNE_MACC_CHAINS | |
12332 | && *nreadyp > 0) | |
12333 | mips_macc_chains_reorder (ready, *nreadyp); | |
65239d20 | 12334 | |
ab77a036 RS |
12335 | if (reload_completed |
12336 | && TUNE_MIPS4130 | |
12337 | && !TARGET_VR4130_ALIGN | |
12338 | && *nreadyp > 1) | |
12339 | vr4130_reorder (ready, *nreadyp); | |
65239d20 | 12340 | |
ab77a036 RS |
12341 | if (TUNE_74K) |
12342 | mips_74k_agen_reorder (ready, *nreadyp); | |
646e6f41 | 12343 | } |
65239d20 | 12344 | |
646e6f41 JZ |
12345 | /* Implement TARGET_SCHED_REORDER. */ |
12346 | ||
12347 | static int | |
12348 | mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12349 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
12350 | { | |
12351 | mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); | |
ab77a036 RS |
12352 | return mips_issue_rate (); |
12353 | } | |
76cbf5bf | 12354 | |
646e6f41 JZ |
12355 | /* Implement TARGET_SCHED_REORDER2. */ |
12356 | ||
12357 | static int | |
12358 | mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12359 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
12360 | { | |
12361 | mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); | |
12362 | return cached_can_issue_more; | |
12363 | } | |
12364 | ||
58684fa0 MK |
12365 | /* Update round-robin counters for ALU1/2 and FALU1/2. */ |
12366 | ||
12367 | static void | |
12368 | mips_ls2_variable_issue (rtx insn) | |
12369 | { | |
12370 | if (mips_ls2.alu1_turn_p) | |
12371 | { | |
12372 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code)) | |
12373 | mips_ls2.alu1_turn_p = false; | |
12374 | } | |
12375 | else | |
12376 | { | |
12377 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code)) | |
12378 | mips_ls2.alu1_turn_p = true; | |
12379 | } | |
12380 | ||
12381 | if (mips_ls2.falu1_turn_p) | |
12382 | { | |
12383 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code)) | |
12384 | mips_ls2.falu1_turn_p = false; | |
12385 | } | |
12386 | else | |
12387 | { | |
12388 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code)) | |
12389 | mips_ls2.falu1_turn_p = true; | |
12390 | } | |
12391 | ||
12392 | if (recog_memoized (insn) >= 0) | |
12393 | mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI); | |
12394 | } | |
12395 | ||
ab77a036 | 12396 | /* Implement TARGET_SCHED_VARIABLE_ISSUE. */ |
76cbf5bf | 12397 | |
ab77a036 RS |
12398 | static int |
12399 | mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12400 | rtx insn, int more) | |
12401 | { | |
65239d20 RS |
12402 | /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */ |
12403 | if (USEFUL_INSN_P (insn)) | |
f2531eb6 | 12404 | { |
0c433c31 RS |
12405 | if (get_attr_type (insn) != TYPE_GHOST) |
12406 | more--; | |
ab77a036 RS |
12407 | if (!reload_completed && TUNE_MACC_CHAINS) |
12408 | mips_macc_chains_record (insn); | |
12409 | vr4130_last_insn = insn; | |
65239d20 RS |
12410 | if (TUNE_74K) |
12411 | mips_74k_agen_init (insn); | |
58684fa0 MK |
12412 | else if (TUNE_LOONGSON_2EF) |
12413 | mips_ls2_variable_issue (insn); | |
76cbf5bf | 12414 | } |
58684fa0 MK |
12415 | |
12416 | /* Instructions of type 'multi' should all be split before | |
12417 | the second scheduling pass. */ | |
12418 | gcc_assert (!reload_completed | |
12419 | || recog_memoized (insn) < 0 | |
12420 | || get_attr_type (insn) != TYPE_MULTI); | |
12421 | ||
646e6f41 | 12422 | cached_can_issue_more = more; |
ab77a036 | 12423 | return more; |
76cbf5bf | 12424 | } |
ab77a036 RS |
12425 | \f |
12426 | /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY), | |
65239d20 | 12427 | return the first operand of the associated PREF or PREFX insn. */ |
76cbf5bf | 12428 | |
ab77a036 RS |
12429 | rtx |
12430 | mips_prefetch_cookie (rtx write, rtx locality) | |
12431 | { | |
12432 | /* store_streamed / load_streamed. */ | |
12433 | if (INTVAL (locality) <= 0) | |
12434 | return GEN_INT (INTVAL (write) + 4); | |
76cbf5bf | 12435 | |
ab77a036 RS |
12436 | /* store / load. */ |
12437 | if (INTVAL (locality) <= 2) | |
12438 | return write; | |
2bcb2ab3 | 12439 | |
ab77a036 RS |
12440 | /* store_retained / load_retained. */ |
12441 | return GEN_INT (INTVAL (write) + 6); | |
12442 | } | |
12443 | \f | |
fd0eb897 RS |
12444 | /* Flags that indicate when a built-in function is available. |
12445 | ||
12446 | BUILTIN_AVAIL_NON_MIPS16 | |
12447 | The function is available on the current target, but only | |
12448 | in non-MIPS16 mode. */ | |
12449 | #define BUILTIN_AVAIL_NON_MIPS16 1 | |
12450 | ||
12451 | /* Declare an availability predicate for built-in functions that | |
12452 | require non-MIPS16 mode and also require COND to be true. | |
12453 | NAME is the main part of the predicate's name. */ | |
12454 | #define AVAIL_NON_MIPS16(NAME, COND) \ | |
12455 | static unsigned int \ | |
12456 | mips_builtin_avail_##NAME (void) \ | |
12457 | { \ | |
12458 | return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ | |
12459 | } | |
12460 | ||
65239d20 RS |
12461 | /* This structure describes a single built-in function. */ |
12462 | struct mips_builtin_description { | |
ab77a036 RS |
12463 | /* The code of the main .md file instruction. See mips_builtin_type |
12464 | for more information. */ | |
12465 | enum insn_code icode; | |
2bcb2ab3 | 12466 | |
ab77a036 RS |
12467 | /* The floating-point comparison code to use with ICODE, if any. */ |
12468 | enum mips_fp_condition cond; | |
2bcb2ab3 | 12469 | |
65239d20 | 12470 | /* The name of the built-in function. */ |
ab77a036 | 12471 | const char *name; |
2bcb2ab3 | 12472 | |
ab77a036 RS |
12473 | /* Specifies how the function should be expanded. */ |
12474 | enum mips_builtin_type builtin_type; | |
2bcb2ab3 | 12475 | |
ab77a036 RS |
12476 | /* The function's prototype. */ |
12477 | enum mips_function_type function_type; | |
2bcb2ab3 | 12478 | |
fd0eb897 RS |
12479 | /* Whether the function is available. */ |
12480 | unsigned int (*avail) (void); | |
ab77a036 | 12481 | }; |
76cbf5bf | 12482 | |
fd0eb897 RS |
12483 | AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT) |
12484 | AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT) | |
12485 | AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D) | |
12486 | AVAIL_NON_MIPS16 (dsp, TARGET_DSP) | |
12487 | AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) | |
12488 | AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) | |
12489 | AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) | |
93581857 | 12490 | AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) |
4d210b07 | 12491 | AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) |
fd0eb897 RS |
12492 | |
12493 | /* Construct a mips_builtin_description from the given arguments. | |
12494 | ||
12495 | INSN is the name of the associated instruction pattern, without the | |
12496 | leading CODE_FOR_mips_. | |
12497 | ||
12498 | CODE is the floating-point condition code associated with the | |
12499 | function. It can be 'f' if the field is not applicable. | |
12500 | ||
12501 | NAME is the name of the function itself, without the leading | |
12502 | "__builtin_mips_". | |
12503 | ||
12504 | BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. | |
12505 | ||
12506 | AVAIL is the name of the availability predicate, without the leading | |
12507 | mips_builtin_avail_. */ | |
12508 | #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \ | |
12509 | FUNCTION_TYPE, AVAIL) \ | |
12510 | { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \ | |
12511 | "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \ | |
12512 | mips_builtin_avail_ ## AVAIL } | |
12513 | ||
12514 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function | |
12515 | mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL | |
12516 | are as for MIPS_BUILTIN. */ | |
12517 | #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
12518 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) | |
206c2d7a | 12519 | |
65239d20 | 12520 | /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which |
fd0eb897 RS |
12521 | are subject to mips_builtin_avail_<AVAIL>. */ |
12522 | #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \ | |
12523 | MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \ | |
12524 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \ | |
12525 | MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \ | |
12526 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL) | |
206c2d7a | 12527 | |
ab77a036 | 12528 | /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. |
fd0eb897 RS |
12529 | The lower and upper forms are subject to mips_builtin_avail_<AVAIL> |
12530 | while the any and all forms are subject to mips_builtin_avail_mips3d. */ | |
12531 | #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \ | |
12532 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \ | |
12533 | MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12534 | mips3d), \ | |
12535 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \ | |
12536 | MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12537 | mips3d), \ | |
12538 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \ | |
12539 | MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12540 | AVAIL), \ | |
12541 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \ | |
12542 | MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12543 | AVAIL) | |
206c2d7a | 12544 | |
ab77a036 | 12545 | /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions |
fd0eb897 | 12546 | are subject to mips_builtin_avail_mips3d. */ |
ab77a036 | 12547 | #define CMP_4S_BUILTINS(INSN, COND) \ |
fd0eb897 RS |
12548 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \ |
12549 | MIPS_BUILTIN_CMP_ANY, \ | |
12550 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \ | |
12551 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \ | |
12552 | MIPS_BUILTIN_CMP_ALL, \ | |
12553 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d) | |
206c2d7a | 12554 | |
ab77a036 | 12555 | /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison |
fd0eb897 RS |
12556 | instruction requires mips_builtin_avail_<AVAIL>. */ |
12557 | #define MOVTF_BUILTINS(INSN, COND, AVAIL) \ | |
12558 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \ | |
12559 | MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
12560 | AVAIL), \ | |
12561 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \ | |
12562 | MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
12563 | AVAIL) | |
2bcb2ab3 | 12564 | |
65239d20 | 12565 | /* Define all the built-in functions related to C.cond.fmt condition COND. */ |
ab77a036 | 12566 | #define CMP_BUILTINS(COND) \ |
fd0eb897 RS |
12567 | MOVTF_BUILTINS (c, COND, paired_single), \ |
12568 | MOVTF_BUILTINS (cabs, COND, mips3d), \ | |
12569 | CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \ | |
12570 | CMP_PS_BUILTINS (c, COND, paired_single), \ | |
12571 | CMP_PS_BUILTINS (cabs, COND, mips3d), \ | |
ab77a036 RS |
12572 | CMP_4S_BUILTINS (c, COND), \ |
12573 | CMP_4S_BUILTINS (cabs, COND) | |
18dbd950 | 12574 | |
fd0eb897 RS |
12575 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET |
12576 | function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE | |
12577 | and AVAIL are as for MIPS_BUILTIN. */ | |
12578 | #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
12579 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ | |
12580 | FUNCTION_TYPE, AVAIL) | |
2bcb2ab3 | 12581 | |
fd0eb897 RS |
12582 | /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP |
12583 | branch instruction. AVAIL is as for MIPS_BUILTIN. */ | |
12584 | #define BPOSGE_BUILTIN(VALUE, AVAIL) \ | |
12585 | MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ | |
12586 | MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) | |
dc884a86 | 12587 | |
93581857 MS |
12588 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> |
12589 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
12590 | builtin_description field. */ | |
12591 | #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \ | |
81f40b79 ILT |
12592 | { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \ |
12593 | "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \ | |
12594 | FUNCTION_TYPE, mips_builtin_avail_loongson } | |
93581857 MS |
12595 | |
12596 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN> | |
12597 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
12598 | builtin_description field. */ | |
12599 | #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \ | |
12600 | LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE) | |
12601 | ||
12602 | /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name. | |
12603 | We use functions of this form when the same insn can be usefully applied | |
12604 | to more than one datatype. */ | |
12605 | #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \ | |
12606 | LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE) | |
12607 | ||
ab77a036 | 12608 | #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 |
ab77a036 RS |
12609 | #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 |
12610 | #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 | |
12611 | #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 | |
12612 | #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3 | |
12613 | #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3 | |
293b77b0 CF |
12614 | #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit |
12615 | #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit | |
dc884a86 | 12616 | |
93581857 MS |
12617 | #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si |
12618 | #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi | |
12619 | #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi | |
12620 | #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3 | |
12621 | #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3 | |
12622 | #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3 | |
12623 | #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3 | |
12624 | #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3 | |
12625 | #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3 | |
12626 | #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3 | |
12627 | #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3 | |
12628 | #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3 | |
12629 | #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3 | |
12630 | #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3 | |
12631 | #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart | |
12632 | #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart | |
a44ecea1 | 12633 | #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3 |
59bdeecb MX |
12634 | #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3 |
12635 | #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3 | |
12636 | #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3 | |
12637 | #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3 | |
12638 | #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3 | |
12639 | #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3 | |
93581857 MS |
12640 | #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3 |
12641 | #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3 | |
12642 | #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3 | |
12643 | #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3 | |
12644 | #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3 | |
12645 | #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3 | |
12646 | #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3 | |
12647 | #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi | |
12648 | #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi | |
12649 | #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si | |
12650 | #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi | |
12651 | #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi | |
12652 | #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si | |
12653 | ||
fd0eb897 RS |
12654 | static const struct mips_builtin_description mips_builtins[] = { |
12655 | DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12656 | DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12657 | DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12658 | DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12659 | DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single), | |
12660 | DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single), | |
12661 | DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single), | |
12662 | DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single), | |
12663 | ||
12664 | DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single), | |
12665 | DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12666 | DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12667 | DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12668 | DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12669 | ||
12670 | DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d), | |
12671 | DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d), | |
12672 | DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12673 | DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
12674 | DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
12675 | DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12676 | ||
12677 | DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d), | |
12678 | DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d), | |
12679 | DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12680 | DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
12681 | DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
12682 | DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12683 | ||
12684 | MIPS_FP_CONDITIONS (CMP_BUILTINS), | |
12685 | ||
12686 | /* Built-in functions for the SB-1 processor. */ | |
12687 | DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single), | |
12688 | ||
12689 | /* Built-in functions for the DSP ASE (32-bit and 64-bit). */ | |
12690 | DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12691 | DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12692 | DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12693 | DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12694 | DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12695 | DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12696 | DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12697 | DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12698 | DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12699 | DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12700 | DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp), | |
12701 | DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp), | |
12702 | DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp), | |
12703 | DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp), | |
12704 | DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp), | |
12705 | DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp), | |
12706 | DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
12707 | DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
12708 | DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
12709 | DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
12710 | DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp), | |
12711 | DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp), | |
12712 | DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12713 | DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12714 | DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12715 | DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12716 | DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12717 | DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12718 | DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12719 | DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12720 | DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
12721 | DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12722 | DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12723 | DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12724 | DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
12725 | DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12726 | DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12727 | DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12728 | DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
12729 | DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
12730 | DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12731 | DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
12732 | DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
12733 | DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp), | |
12734 | DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp), | |
12735 | DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp), | |
12736 | DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp), | |
12737 | DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
12738 | DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
12739 | DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
12740 | DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
12741 | DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
12742 | DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
12743 | DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
12744 | DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
12745 | DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
12746 | DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12747 | DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12748 | DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12749 | DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp), | |
12750 | DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp), | |
12751 | DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
12752 | DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
12753 | DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
12754 | BPOSGE_BUILTIN (32, dsp), | |
12755 | ||
12756 | /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */ | |
12757 | DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2), | |
12758 | DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12759 | DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12760 | DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12761 | DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12762 | DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
12763 | DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
12764 | DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
12765 | DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
12766 | DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
12767 | DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12768 | DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12769 | DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12770 | DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12771 | DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12772 | DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2), | |
12773 | DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
12774 | DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
12775 | DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
12776 | DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
12777 | DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
12778 | DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2), | |
12779 | DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12780 | DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12781 | DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12782 | DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12783 | DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12784 | DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12785 | DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12786 | DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12787 | DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12788 | DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12789 | DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12790 | DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12791 | ||
12792 | /* Built-in functions for the DSP ASE (32-bit only). */ | |
12793 | DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12794 | DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12795 | DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12796 | DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12797 | DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12798 | DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12799 | DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12800 | DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
12801 | DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
12802 | DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12803 | DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12804 | DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12805 | DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12806 | DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12807 | DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12808 | DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12809 | DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12810 | DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12811 | DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12812 | DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
12813 | DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
293b77b0 CF |
12814 | DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), |
12815 | DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), | |
12816 | DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
12817 | DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), | |
12818 | DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32), | |
12819 | DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32), | |
fd0eb897 RS |
12820 | |
12821 | /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */ | |
12822 | DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12823 | DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
fd0eb897 | 12824 | DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
fd0eb897 RS |
12825 | DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
12826 | DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12827 | DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12828 | DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12829 | DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
93581857 MS |
12830 | DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
12831 | ||
12832 | /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ | |
12833 | LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), | |
12834 | LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), | |
12835 | LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI), | |
12836 | LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12837 | LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12838 | LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12839 | LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12840 | LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12841 | LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12842 | LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
12843 | LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI), | |
12844 | LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12845 | LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12846 | LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12847 | LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12848 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI), | |
12849 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12850 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12851 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12852 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI), | |
12853 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12854 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12855 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12856 | LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12857 | LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12858 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12859 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12860 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12861 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12862 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12863 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12864 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12865 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12866 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12867 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12868 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12869 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12870 | LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI), | |
12871 | LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI), | |
12872 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12873 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12874 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12875 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12876 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12877 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12878 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12879 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12880 | LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI), | |
12881 | LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12882 | LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12883 | LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12884 | LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12885 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI), | |
12886 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI), | |
12887 | LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12888 | LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12889 | LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12890 | LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI), | |
12891 | LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12892 | LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI), | |
12893 | LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI), | |
12894 | LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI), | |
12895 | LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI), | |
12896 | LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
12897 | LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
12898 | LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
12899 | LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
12900 | LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
12901 | LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
12902 | LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
12903 | LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
12904 | LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
12905 | LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
12906 | LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
12907 | LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
12908 | LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12909 | LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12910 | LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12911 | LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12912 | LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12913 | LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12914 | LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
12915 | LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI), | |
12916 | LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12917 | LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12918 | LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12919 | LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12920 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12921 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12922 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12923 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12924 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12925 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12926 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12927 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12928 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12929 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12930 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
4d210b07 RS |
12931 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), |
12932 | ||
12933 | /* Sundry other built-in functions. */ | |
12934 | DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache) | |
ab77a036 | 12935 | }; |
dc884a86 | 12936 | |
7725086e RS |
12937 | /* Index I is the function declaration for mips_builtins[I], or null if the |
12938 | function isn't defined on this target. */ | |
12939 | static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)]; | |
12940 | ||
41030557 RS |
12941 | /* MODE is a vector mode whose elements have type TYPE. Return the type |
12942 | of the vector itself. */ | |
dc884a86 | 12943 | |
41030557 RS |
12944 | static tree |
12945 | mips_builtin_vector_type (tree type, enum machine_mode mode) | |
dc884a86 | 12946 | { |
93581857 MS |
12947 | static tree types[2 * (int) MAX_MACHINE_MODE]; |
12948 | int mode_index; | |
dc884a86 | 12949 | |
93581857 MS |
12950 | mode_index = (int) mode; |
12951 | ||
12952 | if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type)) | |
12953 | mode_index += MAX_MACHINE_MODE; | |
12954 | ||
12955 | if (types[mode_index] == NULL_TREE) | |
12956 | types[mode_index] = build_vector_type_for_mode (type, mode); | |
12957 | return types[mode_index]; | |
41030557 | 12958 | } |
dc884a86 | 12959 | |
4d210b07 RS |
12960 | /* Return a type for 'const volatile void *'. */ |
12961 | ||
12962 | static tree | |
12963 | mips_build_cvpointer_type (void) | |
12964 | { | |
12965 | static tree cache; | |
12966 | ||
12967 | if (cache == NULL_TREE) | |
12968 | cache = build_pointer_type (build_qualified_type | |
12969 | (void_type_node, | |
12970 | TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)); | |
12971 | return cache; | |
12972 | } | |
12973 | ||
41030557 RS |
12974 | /* Source-level argument types. */ |
12975 | #define MIPS_ATYPE_VOID void_type_node | |
12976 | #define MIPS_ATYPE_INT integer_type_node | |
12977 | #define MIPS_ATYPE_POINTER ptr_type_node | |
4d210b07 | 12978 | #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type () |
dc884a86 | 12979 | |
41030557 | 12980 | /* Standard mode-based argument types. */ |
93581857 | 12981 | #define MIPS_ATYPE_UQI unsigned_intQI_type_node |
41030557 RS |
12982 | #define MIPS_ATYPE_SI intSI_type_node |
12983 | #define MIPS_ATYPE_USI unsigned_intSI_type_node | |
12984 | #define MIPS_ATYPE_DI intDI_type_node | |
93581857 | 12985 | #define MIPS_ATYPE_UDI unsigned_intDI_type_node |
41030557 RS |
12986 | #define MIPS_ATYPE_SF float_type_node |
12987 | #define MIPS_ATYPE_DF double_type_node | |
dc884a86 | 12988 | |
41030557 RS |
12989 | /* Vector argument types. */ |
12990 | #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode) | |
12991 | #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode) | |
93581857 | 12992 | #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode) |
41030557 | 12993 | #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode) |
93581857 MS |
12994 | #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode) |
12995 | #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode) | |
12996 | #define MIPS_ATYPE_UV2SI \ | |
12997 | mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode) | |
12998 | #define MIPS_ATYPE_UV4HI \ | |
12999 | mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode) | |
13000 | #define MIPS_ATYPE_UV8QI \ | |
13001 | mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode) | |
dc884a86 | 13002 | |
41030557 RS |
13003 | /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists |
13004 | their associated MIPS_ATYPEs. */ | |
13005 | #define MIPS_FTYPE_ATYPES1(A, B) \ | |
13006 | MIPS_ATYPE_##A, MIPS_ATYPE_##B | |
dc884a86 | 13007 | |
41030557 RS |
13008 | #define MIPS_FTYPE_ATYPES2(A, B, C) \ |
13009 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C | |
dc884a86 | 13010 | |
41030557 RS |
13011 | #define MIPS_FTYPE_ATYPES3(A, B, C, D) \ |
13012 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D | |
dc884a86 | 13013 | |
41030557 RS |
13014 | #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \ |
13015 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \ | |
13016 | MIPS_ATYPE_##E | |
dc884a86 | 13017 | |
41030557 | 13018 | /* Return the function type associated with function prototype TYPE. */ |
dc884a86 | 13019 | |
41030557 RS |
13020 | static tree |
13021 | mips_build_function_type (enum mips_function_type type) | |
13022 | { | |
13023 | static tree types[(int) MIPS_MAX_FTYPE_MAX]; | |
dc884a86 | 13024 | |
41030557 RS |
13025 | if (types[(int) type] == NULL_TREE) |
13026 | switch (type) | |
13027 | { | |
13028 | #define DEF_MIPS_FTYPE(NUM, ARGS) \ | |
13029 | case MIPS_FTYPE_NAME##NUM ARGS: \ | |
13030 | types[(int) type] \ | |
13031 | = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \ | |
13032 | NULL_TREE); \ | |
13033 | break; | |
13034 | #include "config/mips/mips-ftypes.def" | |
13035 | #undef DEF_MIPS_FTYPE | |
13036 | default: | |
13037 | gcc_unreachable (); | |
13038 | } | |
dc884a86 | 13039 | |
41030557 RS |
13040 | return types[(int) type]; |
13041 | } | |
6f2993e5 | 13042 | |
65239d20 | 13043 | /* Implement TARGET_INIT_BUILTINS. */ |
41030557 RS |
13044 | |
13045 | static void | |
13046 | mips_init_builtins (void) | |
13047 | { | |
65239d20 | 13048 | const struct mips_builtin_description *d; |
fd0eb897 | 13049 | unsigned int i; |
6f2993e5 | 13050 | |
ab77a036 RS |
13051 | /* Iterate through all of the bdesc arrays, initializing all of the |
13052 | builtin functions. */ | |
fd0eb897 | 13053 | for (i = 0; i < ARRAY_SIZE (mips_builtins); i++) |
ab77a036 | 13054 | { |
fd0eb897 RS |
13055 | d = &mips_builtins[i]; |
13056 | if (d->avail ()) | |
7725086e RS |
13057 | mips_builtin_decls[i] |
13058 | = add_builtin_function (d->name, | |
13059 | mips_build_function_type (d->function_type), | |
13060 | i, BUILT_IN_MD, NULL, NULL); | |
ab77a036 RS |
13061 | } |
13062 | } | |
6f2993e5 | 13063 | |
7725086e RS |
13064 | /* Implement TARGET_BUILTIN_DECL. */ |
13065 | ||
13066 | static tree | |
13067 | mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED) | |
13068 | { | |
13069 | if (code >= ARRAY_SIZE (mips_builtins)) | |
13070 | return error_mark_node; | |
13071 | return mips_builtin_decls[code]; | |
13072 | } | |
13073 | ||
b99ce2a8 RS |
13074 | /* Take argument ARGNO from EXP's argument list and convert it into |
13075 | an expand operand. Store the operand in *OP. */ | |
987a3c2b | 13076 | |
b99ce2a8 RS |
13077 | static void |
13078 | mips_prepare_builtin_arg (struct expand_operand *op, tree exp, | |
13079 | unsigned int argno) | |
ab77a036 | 13080 | { |
26b69f64 | 13081 | tree arg; |
ab77a036 | 13082 | rtx value; |
6f2993e5 | 13083 | |
26b69f64 RS |
13084 | arg = CALL_EXPR_ARG (exp, argno); |
13085 | value = expand_normal (arg); | |
b99ce2a8 RS |
13086 | create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg))); |
13087 | } | |
26b69f64 | 13088 | |
b99ce2a8 RS |
13089 | /* Expand instruction ICODE as part of a built-in function sequence. |
13090 | Use the first NOPS elements of OPS as the instruction's operands. | |
13091 | HAS_TARGET_P is true if operand 0 is a target; it is false if the | |
13092 | instruction has no target. | |
26b69f64 | 13093 | |
b99ce2a8 | 13094 | Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */ |
4d210b07 | 13095 | |
b99ce2a8 RS |
13096 | static rtx |
13097 | mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, | |
13098 | struct expand_operand *ops, bool has_target_p) | |
13099 | { | |
13100 | if (!maybe_expand_insn (icode, nops, ops)) | |
13101 | { | |
13102 | error ("invalid argument to built-in function"); | |
13103 | return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx; | |
ab77a036 | 13104 | } |
b99ce2a8 | 13105 | return has_target_p ? ops[0].value : const0_rtx; |
ab77a036 | 13106 | } |
0ac40e7a | 13107 | |
b99ce2a8 RS |
13108 | /* Expand a floating-point comparison for built-in function call EXP. |
13109 | The first NARGS arguments are the values to be compared. ICODE is | |
13110 | the .md pattern that does the comparison and COND is the condition | |
13111 | that is being tested. Return an rtx for the result. */ | |
0ac40e7a | 13112 | |
ab77a036 | 13113 | static rtx |
b99ce2a8 RS |
13114 | mips_expand_builtin_compare_1 (enum insn_code icode, |
13115 | enum mips_fp_condition cond, | |
13116 | tree exp, int nargs) | |
ab77a036 | 13117 | { |
b99ce2a8 RS |
13118 | struct expand_operand ops[MAX_RECOG_OPERANDS]; |
13119 | int opno, argno; | |
6f2993e5 | 13120 | |
b99ce2a8 RS |
13121 | /* The instruction should have a target operand, an operand for each |
13122 | argument, and an operand for COND. */ | |
f04713ee | 13123 | gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args); |
6f2993e5 | 13124 | |
b99ce2a8 RS |
13125 | opno = 0; |
13126 | create_output_operand (&ops[opno++], NULL_RTX, | |
13127 | insn_data[(int) icode].operand[0].mode); | |
13128 | for (argno = 0; argno < nargs; argno++) | |
13129 | mips_prepare_builtin_arg (&ops[opno++], exp, argno); | |
13130 | create_integer_operand (&ops[opno++], (int) cond); | |
13131 | return mips_expand_builtin_insn (icode, opno, ops, true); | |
6f2993e5 RS |
13132 | } |
13133 | ||
65239d20 RS |
13134 | /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function; |
13135 | HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function | |
13136 | and ICODE is the code of the associated .md pattern. TARGET, if nonnull, | |
13137 | suggests a good place to put the result. */ | |
6f2993e5 | 13138 | |
ab77a036 RS |
13139 | static rtx |
13140 | mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, | |
65239d20 | 13141 | bool has_target_p) |
6f2993e5 | 13142 | { |
b99ce2a8 | 13143 | struct expand_operand ops[MAX_RECOG_OPERANDS]; |
65239d20 | 13144 | int opno, argno; |
c15c90bb | 13145 | |
65239d20 RS |
13146 | /* Map any target to operand 0. */ |
13147 | opno = 0; | |
13148 | if (has_target_p) | |
b99ce2a8 | 13149 | create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp))); |
c235ddf2 | 13150 | |
f04713ee RS |
13151 | /* Map the arguments to the other operands. */ |
13152 | gcc_assert (opno + call_expr_nargs (exp) | |
13153 | == insn_data[icode].n_generator_args); | |
b99ce2a8 RS |
13154 | for (argno = 0; argno < call_expr_nargs (exp); argno++) |
13155 | mips_prepare_builtin_arg (&ops[opno++], exp, argno); | |
c15c90bb | 13156 | |
b99ce2a8 | 13157 | return mips_expand_builtin_insn (icode, opno, ops, has_target_p); |
c15c90bb | 13158 | } |
6f2993e5 | 13159 | |
65239d20 RS |
13160 | /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps |
13161 | function; TYPE says which. EXP is the CALL_EXPR that calls the | |
ab77a036 RS |
13162 | function, ICODE is the instruction that should be used to compare |
13163 | the first two arguments, and COND is the condition it should test. | |
13164 | TARGET, if nonnull, suggests a good place to put the result. */ | |
d604bca3 | 13165 | |
ab77a036 RS |
13166 | static rtx |
13167 | mips_expand_builtin_movtf (enum mips_builtin_type type, | |
13168 | enum insn_code icode, enum mips_fp_condition cond, | |
13169 | rtx target, tree exp) | |
13170 | { | |
b99ce2a8 RS |
13171 | struct expand_operand ops[4]; |
13172 | rtx cmp_result; | |
d604bca3 | 13173 | |
b99ce2a8 RS |
13174 | cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2); |
13175 | create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp))); | |
ab77a036 | 13176 | if (type == MIPS_BUILTIN_MOVT) |
d604bca3 | 13177 | { |
b99ce2a8 RS |
13178 | mips_prepare_builtin_arg (&ops[2], exp, 2); |
13179 | mips_prepare_builtin_arg (&ops[1], exp, 3); | |
c1bd2d66 | 13180 | } |
ab77a036 | 13181 | else |
d604bca3 | 13182 | { |
b99ce2a8 RS |
13183 | mips_prepare_builtin_arg (&ops[1], exp, 2); |
13184 | mips_prepare_builtin_arg (&ops[2], exp, 3); | |
c1bd2d66 | 13185 | } |
b99ce2a8 RS |
13186 | create_fixed_operand (&ops[3], cmp_result); |
13187 | return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps, | |
13188 | 4, ops, true); | |
d604bca3 MH |
13189 | } |
13190 | ||
ab77a036 RS |
13191 | /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE |
13192 | into TARGET otherwise. Return TARGET. */ | |
0ff83799 | 13193 | |
ab77a036 RS |
13194 | static rtx |
13195 | mips_builtin_branch_and_move (rtx condition, rtx target, | |
13196 | rtx value_if_true, rtx value_if_false) | |
0ff83799 | 13197 | { |
ab77a036 | 13198 | rtx true_label, done_label; |
0ff83799 | 13199 | |
ab77a036 RS |
13200 | true_label = gen_label_rtx (); |
13201 | done_label = gen_label_rtx (); | |
21c9500d | 13202 | |
ab77a036 RS |
13203 | /* First assume that CONDITION is false. */ |
13204 | mips_emit_move (target, value_if_false); | |
21c9500d | 13205 | |
ab77a036 RS |
13206 | /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */ |
13207 | emit_jump_insn (gen_condjump (condition, true_label)); | |
13208 | emit_jump_insn (gen_jump (done_label)); | |
13209 | emit_barrier (); | |
21c9500d | 13210 | |
ab77a036 RS |
13211 | /* Fix TARGET if CONDITION is true. */ |
13212 | emit_label (true_label); | |
13213 | mips_emit_move (target, value_if_true); | |
0ff83799 | 13214 | |
ab77a036 RS |
13215 | emit_label (done_label); |
13216 | return target; | |
0ff83799 MM |
13217 | } |
13218 | ||
65239d20 RS |
13219 | /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is |
13220 | the CALL_EXPR that calls the function, ICODE is the code of the | |
13221 | comparison instruction, and COND is the condition it should test. | |
13222 | TARGET, if nonnull, suggests a good place to put the boolean result. */ | |
c8520e56 | 13223 | |
ab77a036 RS |
13224 | static rtx |
13225 | mips_expand_builtin_compare (enum mips_builtin_type builtin_type, | |
13226 | enum insn_code icode, enum mips_fp_condition cond, | |
13227 | rtx target, tree exp) | |
c8520e56 | 13228 | { |
b99ce2a8 | 13229 | rtx offset, condition, cmp_result; |
c8520e56 | 13230 | |
ab77a036 RS |
13231 | if (target == 0 || GET_MODE (target) != SImode) |
13232 | target = gen_reg_rtx (SImode); | |
b99ce2a8 RS |
13233 | cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, |
13234 | call_expr_nargs (exp)); | |
0ff83799 | 13235 | |
ab77a036 RS |
13236 | /* If the comparison sets more than one register, we define the result |
13237 | to be 0 if all registers are false and -1 if all registers are true. | |
13238 | The value of the complete result is indeterminate otherwise. */ | |
13239 | switch (builtin_type) | |
a8c1d5f8 | 13240 | { |
ab77a036 RS |
13241 | case MIPS_BUILTIN_CMP_ALL: |
13242 | condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx); | |
13243 | return mips_builtin_branch_and_move (condition, target, | |
13244 | const0_rtx, const1_rtx); | |
13245 | ||
13246 | case MIPS_BUILTIN_CMP_UPPER: | |
13247 | case MIPS_BUILTIN_CMP_LOWER: | |
13248 | offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER); | |
13249 | condition = gen_single_cc (cmp_result, offset); | |
13250 | return mips_builtin_branch_and_move (condition, target, | |
13251 | const1_rtx, const0_rtx); | |
13252 | ||
13253 | default: | |
13254 | condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx); | |
13255 | return mips_builtin_branch_and_move (condition, target, | |
13256 | const1_rtx, const0_rtx); | |
a8c1d5f8 | 13257 | } |
ab77a036 | 13258 | } |
0ff83799 | 13259 | |
65239d20 RS |
13260 | /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET, |
13261 | if nonnull, suggests a good place to put the boolean result. */ | |
0ff83799 | 13262 | |
ab77a036 RS |
13263 | static rtx |
13264 | mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) | |
13265 | { | |
13266 | rtx condition, cmp_result; | |
13267 | int cmp_value; | |
0ff83799 | 13268 | |
ab77a036 RS |
13269 | if (target == 0 || GET_MODE (target) != SImode) |
13270 | target = gen_reg_rtx (SImode); | |
0ff83799 | 13271 | |
ab77a036 RS |
13272 | cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM); |
13273 | ||
13274 | if (builtin_type == MIPS_BUILTIN_BPOSGE32) | |
13275 | cmp_value = 32; | |
a8c1d5f8 | 13276 | else |
ab77a036 RS |
13277 | gcc_assert (0); |
13278 | ||
13279 | condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value)); | |
13280 | return mips_builtin_branch_and_move (condition, target, | |
13281 | const1_rtx, const0_rtx); | |
13282 | } | |
13283 | ||
65239d20 | 13284 | /* Implement TARGET_EXPAND_BUILTIN. */ |
ab77a036 RS |
13285 | |
13286 | static rtx | |
13287 | mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
0767b03f | 13288 | enum machine_mode mode, int ignore) |
ab77a036 | 13289 | { |
ab77a036 | 13290 | tree fndecl; |
fd0eb897 RS |
13291 | unsigned int fcode, avail; |
13292 | const struct mips_builtin_description *d; | |
ab77a036 RS |
13293 | |
13294 | fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
13295 | fcode = DECL_FUNCTION_CODE (fndecl); | |
fd0eb897 RS |
13296 | gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); |
13297 | d = &mips_builtins[fcode]; | |
13298 | avail = d->avail (); | |
13299 | gcc_assert (avail != 0); | |
ab77a036 | 13300 | if (TARGET_MIPS16) |
a8c1d5f8 | 13301 | { |
29d08eba JM |
13302 | error ("built-in function %qE not supported for MIPS16", |
13303 | DECL_NAME (fndecl)); | |
0767b03f | 13304 | return ignore ? const0_rtx : CONST0_RTX (mode); |
a8c1d5f8 | 13305 | } |
fd0eb897 | 13306 | switch (d->builtin_type) |
0ff83799 | 13307 | { |
fd0eb897 RS |
13308 | case MIPS_BUILTIN_DIRECT: |
13309 | return mips_expand_builtin_direct (d->icode, target, exp, true); | |
13310 | ||
13311 | case MIPS_BUILTIN_DIRECT_NO_TARGET: | |
13312 | return mips_expand_builtin_direct (d->icode, target, exp, false); | |
13313 | ||
13314 | case MIPS_BUILTIN_MOVT: | |
13315 | case MIPS_BUILTIN_MOVF: | |
13316 | return mips_expand_builtin_movtf (d->builtin_type, d->icode, | |
13317 | d->cond, target, exp); | |
13318 | ||
13319 | case MIPS_BUILTIN_CMP_ANY: | |
13320 | case MIPS_BUILTIN_CMP_ALL: | |
13321 | case MIPS_BUILTIN_CMP_UPPER: | |
13322 | case MIPS_BUILTIN_CMP_LOWER: | |
13323 | case MIPS_BUILTIN_CMP_SINGLE: | |
13324 | return mips_expand_builtin_compare (d->builtin_type, d->icode, | |
13325 | d->cond, target, exp); | |
13326 | ||
13327 | case MIPS_BUILTIN_BPOSGE32: | |
13328 | return mips_expand_builtin_bposge (d->builtin_type, target); | |
a8c1d5f8 | 13329 | } |
5f5fe6d9 | 13330 | gcc_unreachable (); |
0ff83799 | 13331 | } |
a27fb29b | 13332 | \f |
65239d20 | 13333 | /* An entry in the MIPS16 constant pool. VALUE is the pool constant, |
ab77a036 | 13334 | MODE is its mode, and LABEL is the CODE_LABEL associated with it. */ |
ab77a036 RS |
13335 | struct mips16_constant { |
13336 | struct mips16_constant *next; | |
13337 | rtx value; | |
13338 | rtx label; | |
13339 | enum machine_mode mode; | |
13340 | }; | |
6ba7b547 | 13341 | |
65239d20 | 13342 | /* Information about an incomplete MIPS16 constant pool. FIRST is the |
ab77a036 RS |
13343 | first constant, HIGHEST_ADDRESS is the highest address that the first |
13344 | byte of the pool can have, and INSN_ADDRESS is the current instruction | |
13345 | address. */ | |
ab77a036 RS |
13346 | struct mips16_constant_pool { |
13347 | struct mips16_constant *first; | |
13348 | int highest_address; | |
13349 | int insn_address; | |
13350 | }; | |
6ba7b547 | 13351 | |
ab77a036 RS |
13352 | /* Add constant VALUE to POOL and return its label. MODE is the |
13353 | value's mode (used for CONST_INTs, etc.). */ | |
6ba7b547 | 13354 | |
ab77a036 | 13355 | static rtx |
65239d20 RS |
13356 | mips16_add_constant (struct mips16_constant_pool *pool, |
13357 | rtx value, enum machine_mode mode) | |
ab77a036 RS |
13358 | { |
13359 | struct mips16_constant **p, *c; | |
13360 | bool first_of_size_p; | |
6ba7b547 | 13361 | |
ab77a036 RS |
13362 | /* See whether the constant is already in the pool. If so, return the |
13363 | existing label, otherwise leave P pointing to the place where the | |
13364 | constant should be added. | |
6ba7b547 | 13365 | |
ab77a036 RS |
13366 | Keep the pool sorted in increasing order of mode size so that we can |
13367 | reduce the number of alignments needed. */ | |
13368 | first_of_size_p = true; | |
13369 | for (p = &pool->first; *p != 0; p = &(*p)->next) | |
13370 | { | |
13371 | if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value)) | |
13372 | return (*p)->label; | |
13373 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode)) | |
13374 | break; | |
13375 | if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode)) | |
13376 | first_of_size_p = false; | |
13377 | } | |
6ba7b547 | 13378 | |
ab77a036 RS |
13379 | /* In the worst case, the constant needed by the earliest instruction |
13380 | will end up at the end of the pool. The entire pool must then be | |
13381 | accessible from that instruction. | |
6ba7b547 | 13382 | |
ab77a036 RS |
13383 | When adding the first constant, set the pool's highest address to |
13384 | the address of the first out-of-range byte. Adjust this address | |
13385 | downwards each time a new constant is added. */ | |
13386 | if (pool->first == 0) | |
65239d20 RS |
13387 | /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address |
13388 | of the instruction with the lowest two bits clear. The base PC | |
13389 | value for LDPC has the lowest three bits clear. Assume the worst | |
13390 | case here; namely that the PC-relative instruction occupies the | |
13391 | last 2 bytes in an aligned word. */ | |
ab77a036 RS |
13392 | pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000; |
13393 | pool->highest_address -= GET_MODE_SIZE (mode); | |
13394 | if (first_of_size_p) | |
13395 | /* Take into account the worst possible padding due to alignment. */ | |
13396 | pool->highest_address -= GET_MODE_SIZE (mode) - 1; | |
6ba7b547 | 13397 | |
ab77a036 | 13398 | /* Create a new entry. */ |
65239d20 | 13399 | c = XNEW (struct mips16_constant); |
ab77a036 RS |
13400 | c->value = value; |
13401 | c->mode = mode; | |
13402 | c->label = gen_label_rtx (); | |
13403 | c->next = *p; | |
13404 | *p = c; | |
6ba7b547 | 13405 | |
ab77a036 RS |
13406 | return c->label; |
13407 | } | |
6ba7b547 | 13408 | |
ab77a036 RS |
13409 | /* Output constant VALUE after instruction INSN and return the last |
13410 | instruction emitted. MODE is the mode of the constant. */ | |
6ba7b547 | 13411 | |
ab77a036 | 13412 | static rtx |
65239d20 | 13413 | mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn) |
ab77a036 | 13414 | { |
65239d20 | 13415 | if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode)) |
ab77a036 RS |
13416 | { |
13417 | rtx size = GEN_INT (GET_MODE_SIZE (mode)); | |
13418 | return emit_insn_after (gen_consttable_int (value, size), insn); | |
13419 | } | |
6ba7b547 | 13420 | |
ab77a036 RS |
13421 | if (SCALAR_FLOAT_MODE_P (mode)) |
13422 | return emit_insn_after (gen_consttable_float (value), insn); | |
6ba7b547 | 13423 | |
ab77a036 RS |
13424 | if (VECTOR_MODE_P (mode)) |
13425 | { | |
13426 | int i; | |
6ba7b547 | 13427 | |
ab77a036 | 13428 | for (i = 0; i < CONST_VECTOR_NUNITS (value); i++) |
65239d20 RS |
13429 | insn = mips16_emit_constants_1 (GET_MODE_INNER (mode), |
13430 | CONST_VECTOR_ELT (value, i), insn); | |
ab77a036 RS |
13431 | return insn; |
13432 | } | |
6ba7b547 | 13433 | |
ab77a036 RS |
13434 | gcc_unreachable (); |
13435 | } | |
6ba7b547 | 13436 | |
ab77a036 | 13437 | /* Dump out the constants in CONSTANTS after INSN. */ |
32ad6a47 | 13438 | |
ab77a036 | 13439 | static void |
65239d20 | 13440 | mips16_emit_constants (struct mips16_constant *constants, rtx insn) |
32ad6a47 | 13441 | { |
ab77a036 RS |
13442 | struct mips16_constant *c, *next; |
13443 | int align; | |
46490403 | 13444 | |
ab77a036 RS |
13445 | align = 0; |
13446 | for (c = constants; c != NULL; c = next) | |
32ad6a47 | 13447 | { |
ab77a036 RS |
13448 | /* If necessary, increase the alignment of PC. */ |
13449 | if (align < GET_MODE_SIZE (c->mode)) | |
c9e0ce37 | 13450 | { |
ab77a036 RS |
13451 | int align_log = floor_log2 (GET_MODE_SIZE (c->mode)); |
13452 | insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn); | |
c9e0ce37 | 13453 | } |
ab77a036 | 13454 | align = GET_MODE_SIZE (c->mode); |
a27fb29b | 13455 | |
ab77a036 | 13456 | insn = emit_label_after (c->label, insn); |
65239d20 | 13457 | insn = mips16_emit_constants_1 (c->mode, c->value, insn); |
d07d525a | 13458 | |
ab77a036 RS |
13459 | next = c->next; |
13460 | free (c); | |
13461 | } | |
7dac2f89 | 13462 | |
ab77a036 | 13463 | emit_barrier_after (insn); |
a27fb29b | 13464 | } |
7dac2f89 | 13465 | |
ab77a036 | 13466 | /* Return the length of instruction INSN. */ |
f41a6bf1 | 13467 | |
ab77a036 RS |
13468 | static int |
13469 | mips16_insn_length (rtx insn) | |
13470 | { | |
13471 | if (JUMP_P (insn)) | |
13472 | { | |
13473 | rtx body = PATTERN (insn); | |
13474 | if (GET_CODE (body) == ADDR_VEC) | |
13475 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0); | |
13476 | if (GET_CODE (body) == ADDR_DIFF_VEC) | |
13477 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1); | |
13478 | } | |
13479 | return get_attr_length (insn); | |
13480 | } | |
7dac2f89 | 13481 | |
ab77a036 RS |
13482 | /* If *X is a symbolic constant that refers to the constant pool, add |
13483 | the constant to POOL and rewrite *X to use the constant's label. */ | |
7dac2f89 | 13484 | |
ab77a036 RS |
13485 | static void |
13486 | mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x) | |
a27fb29b | 13487 | { |
ab77a036 | 13488 | rtx base, offset, label; |
7dac2f89 | 13489 | |
ab77a036 RS |
13490 | split_const (*x, &base, &offset); |
13491 | if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base)) | |
13492 | { | |
65239d20 RS |
13493 | label = mips16_add_constant (pool, get_pool_constant (base), |
13494 | get_pool_mode (base)); | |
ab77a036 RS |
13495 | base = gen_rtx_LABEL_REF (Pmode, label); |
13496 | *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE); | |
13497 | } | |
a27fb29b | 13498 | } |
7dac2f89 | 13499 | |
ab77a036 RS |
13500 | /* This structure is used to communicate with mips16_rewrite_pool_refs. |
13501 | INSN is the instruction we're rewriting and POOL points to the current | |
13502 | constant pool. */ | |
13503 | struct mips16_rewrite_pool_refs_info { | |
13504 | rtx insn; | |
13505 | struct mips16_constant_pool *pool; | |
13506 | }; | |
7dac2f89 | 13507 | |
ab77a036 RS |
13508 | /* Rewrite *X so that constant pool references refer to the constant's |
13509 | label instead. DATA points to a mips16_rewrite_pool_refs_info | |
13510 | structure. */ | |
a27fb29b | 13511 | |
ab77a036 RS |
13512 | static int |
13513 | mips16_rewrite_pool_refs (rtx *x, void *data) | |
a27fb29b | 13514 | { |
5ead67f6 KG |
13515 | struct mips16_rewrite_pool_refs_info *info = |
13516 | (struct mips16_rewrite_pool_refs_info *) data; | |
7dac2f89 | 13517 | |
ab77a036 RS |
13518 | if (force_to_mem_operand (*x, Pmode)) |
13519 | { | |
13520 | rtx mem = force_const_mem (GET_MODE (*x), *x); | |
13521 | validate_change (info->insn, x, mem, false); | |
13522 | } | |
a27fb29b | 13523 | |
ab77a036 RS |
13524 | if (MEM_P (*x)) |
13525 | { | |
13526 | mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0)); | |
13527 | return -1; | |
13528 | } | |
a27fb29b | 13529 | |
ab77a036 RS |
13530 | if (TARGET_MIPS16_TEXT_LOADS) |
13531 | mips16_rewrite_pool_constant (info->pool, x); | |
a27fb29b | 13532 | |
ab77a036 | 13533 | return GET_CODE (*x) == CONST ? -1 : 0; |
7dac2f89 | 13534 | } |
7c262518 | 13535 | |
b53da244 AN |
13536 | /* Return whether CFG is used in mips_reorg. */ |
13537 | ||
13538 | static bool | |
13539 | mips_cfg_in_reorg (void) | |
13540 | { | |
13541 | return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE | |
13542 | || TARGET_RELAX_PIC_CALLS); | |
13543 | } | |
13544 | ||
ab77a036 | 13545 | /* Build MIPS16 constant pools. */ |
a27fb29b | 13546 | |
ab77a036 RS |
13547 | static void |
13548 | mips16_lay_out_constants (void) | |
a27fb29b | 13549 | { |
ab77a036 RS |
13550 | struct mips16_constant_pool pool; |
13551 | struct mips16_rewrite_pool_refs_info info; | |
13552 | rtx insn, barrier; | |
a27fb29b | 13553 | |
ab77a036 RS |
13554 | if (!TARGET_MIPS16_PCREL_LOADS) |
13555 | return; | |
a27fb29b | 13556 | |
b53da244 AN |
13557 | if (mips_cfg_in_reorg ()) |
13558 | split_all_insns (); | |
13559 | else | |
13560 | split_all_insns_noflow (); | |
ab77a036 RS |
13561 | barrier = 0; |
13562 | memset (&pool, 0, sizeof (pool)); | |
13563 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
13564 | { | |
13565 | /* Rewrite constant pool references in INSN. */ | |
006b29ab | 13566 | if (USEFUL_INSN_P (insn)) |
ab77a036 RS |
13567 | { |
13568 | info.insn = insn; | |
13569 | info.pool = &pool; | |
13570 | for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info); | |
13571 | } | |
dfad12b5 | 13572 | |
ab77a036 | 13573 | pool.insn_address += mips16_insn_length (insn); |
0e5a4ad8 | 13574 | |
ab77a036 RS |
13575 | if (pool.first != NULL) |
13576 | { | |
13577 | /* If there are no natural barriers between the first user of | |
13578 | the pool and the highest acceptable address, we'll need to | |
13579 | create a new instruction to jump around the constant pool. | |
13580 | In the worst case, this instruction will be 4 bytes long. | |
dfad12b5 | 13581 | |
ab77a036 RS |
13582 | If it's too late to do this transformation after INSN, |
13583 | do it immediately before INSN. */ | |
13584 | if (barrier == 0 && pool.insn_address + 4 > pool.highest_address) | |
13585 | { | |
13586 | rtx label, jump; | |
54401342 | 13587 | |
ab77a036 RS |
13588 | label = gen_label_rtx (); |
13589 | ||
13590 | jump = emit_jump_insn_before (gen_jump (label), insn); | |
13591 | JUMP_LABEL (jump) = label; | |
13592 | LABEL_NUSES (label) = 1; | |
13593 | barrier = emit_barrier_after (jump); | |
13594 | ||
13595 | emit_label_after (label, barrier); | |
13596 | pool.insn_address += 4; | |
13597 | } | |
13598 | ||
13599 | /* See whether the constant pool is now out of range of the first | |
13600 | user. If so, output the constants after the previous barrier. | |
13601 | Note that any instructions between BARRIER and INSN (inclusive) | |
13602 | will use negative offsets to refer to the pool. */ | |
13603 | if (pool.insn_address > pool.highest_address) | |
13604 | { | |
65239d20 | 13605 | mips16_emit_constants (pool.first, barrier); |
ab77a036 RS |
13606 | pool.first = NULL; |
13607 | barrier = 0; | |
13608 | } | |
13609 | else if (BARRIER_P (insn)) | |
13610 | barrier = insn; | |
13611 | } | |
13612 | } | |
65239d20 | 13613 | mips16_emit_constants (pool.first, get_last_insn ()); |
0c8da560 | 13614 | } |
50d32cf6 | 13615 | \f |
4d210b07 RS |
13616 | /* Return true if it is worth r10k_simplify_address's while replacing |
13617 | an address with X. We are looking for constants, and for addresses | |
13618 | at a known offset from the incoming stack pointer. */ | |
13619 | ||
13620 | static bool | |
13621 | r10k_simplified_address_p (rtx x) | |
13622 | { | |
13623 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) | |
13624 | x = XEXP (x, 0); | |
13625 | return x == virtual_incoming_args_rtx || CONSTANT_P (x); | |
13626 | } | |
13627 | ||
13628 | /* X is an expression that appears in INSN. Try to use the UD chains | |
13629 | to simplify it, returning the simplified form on success and the | |
13630 | original form otherwise. Replace the incoming value of $sp with | |
13631 | virtual_incoming_args_rtx (which should never occur in X otherwise). */ | |
13632 | ||
13633 | static rtx | |
13634 | r10k_simplify_address (rtx x, rtx insn) | |
13635 | { | |
13636 | rtx newx, op0, op1, set, def_insn, note; | |
57512f53 | 13637 | df_ref use, def; |
4d210b07 RS |
13638 | struct df_link *defs; |
13639 | ||
13640 | newx = NULL_RTX; | |
13641 | if (UNARY_P (x)) | |
13642 | { | |
13643 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
13644 | if (op0 != XEXP (x, 0)) | |
13645 | newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x), | |
13646 | op0, GET_MODE (XEXP (x, 0))); | |
13647 | } | |
13648 | else if (BINARY_P (x)) | |
13649 | { | |
13650 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
13651 | op1 = r10k_simplify_address (XEXP (x, 1), insn); | |
13652 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
13653 | newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); | |
13654 | } | |
13655 | else if (GET_CODE (x) == LO_SUM) | |
13656 | { | |
13657 | /* LO_SUMs can be offset from HIGHs, if we know they won't | |
13658 | overflow. See mips_classify_address for the rationale behind | |
13659 | the lax check. */ | |
13660 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
13661 | if (GET_CODE (op0) == HIGH) | |
13662 | newx = XEXP (x, 1); | |
13663 | } | |
13664 | else if (REG_P (x)) | |
13665 | { | |
13666 | /* Uses are recorded by regno_reg_rtx, not X itself. */ | |
13667 | use = df_find_use (insn, regno_reg_rtx[REGNO (x)]); | |
13668 | gcc_assert (use); | |
13669 | defs = DF_REF_CHAIN (use); | |
13670 | ||
13671 | /* Require a single definition. */ | |
13672 | if (defs && defs->next == NULL) | |
13673 | { | |
13674 | def = defs->ref; | |
13675 | if (DF_REF_IS_ARTIFICIAL (def)) | |
13676 | { | |
13677 | /* Replace the incoming value of $sp with | |
13678 | virtual_incoming_args_rtx. */ | |
13679 | if (x == stack_pointer_rtx | |
13680 | && DF_REF_BB (def) == ENTRY_BLOCK_PTR) | |
13681 | newx = virtual_incoming_args_rtx; | |
13682 | } | |
13683 | else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use), | |
13684 | DF_REF_BB (def))) | |
13685 | { | |
13686 | /* Make sure that DEF_INSN is a single set of REG. */ | |
13687 | def_insn = DF_REF_INSN (def); | |
13688 | if (NONJUMP_INSN_P (def_insn)) | |
13689 | { | |
13690 | set = single_set (def_insn); | |
13691 | if (set && rtx_equal_p (SET_DEST (set), x)) | |
13692 | { | |
13693 | /* Prefer to use notes, since the def-use chains | |
13694 | are often shorter. */ | |
13695 | note = find_reg_equal_equiv_note (def_insn); | |
13696 | if (note) | |
13697 | newx = XEXP (note, 0); | |
13698 | else | |
13699 | newx = SET_SRC (set); | |
13700 | newx = r10k_simplify_address (newx, def_insn); | |
13701 | } | |
13702 | } | |
13703 | } | |
13704 | } | |
13705 | } | |
13706 | if (newx && r10k_simplified_address_p (newx)) | |
13707 | return newx; | |
13708 | return x; | |
13709 | } | |
13710 | ||
13711 | /* Return true if ADDRESS is known to be an uncached address | |
13712 | on R10K systems. */ | |
13713 | ||
13714 | static bool | |
13715 | r10k_uncached_address_p (unsigned HOST_WIDE_INT address) | |
13716 | { | |
13717 | unsigned HOST_WIDE_INT upper; | |
13718 | ||
13719 | /* Check for KSEG1. */ | |
13720 | if (address + 0x60000000 < 0x20000000) | |
13721 | return true; | |
13722 | ||
13723 | /* Check for uncached XKPHYS addresses. */ | |
13724 | if (Pmode == DImode) | |
13725 | { | |
13726 | upper = (address >> 40) & 0xf9ffff; | |
13727 | if (upper == 0x900000 || upper == 0xb80000) | |
13728 | return true; | |
13729 | } | |
13730 | return false; | |
13731 | } | |
13732 | ||
13733 | /* Return true if we can prove that an access to address X in instruction | |
13734 | INSN would be safe from R10K speculation. This X is a general | |
13735 | expression; it might not be a legitimate address. */ | |
13736 | ||
13737 | static bool | |
13738 | r10k_safe_address_p (rtx x, rtx insn) | |
13739 | { | |
13740 | rtx base, offset; | |
13741 | HOST_WIDE_INT offset_val; | |
13742 | ||
13743 | x = r10k_simplify_address (x, insn); | |
13744 | ||
13745 | /* Check for references to the stack frame. It doesn't really matter | |
13746 | how much of the frame has been allocated at INSN; -mr10k-cache-barrier | |
13747 | allows us to assume that accesses to any part of the eventual frame | |
13748 | is safe from speculation at any point in the function. */ | |
13749 | mips_split_plus (x, &base, &offset_val); | |
13750 | if (base == virtual_incoming_args_rtx | |
13751 | && offset_val >= -cfun->machine->frame.total_size | |
13752 | && offset_val < cfun->machine->frame.args_size) | |
13753 | return true; | |
13754 | ||
13755 | /* Check for uncached addresses. */ | |
13756 | if (CONST_INT_P (x)) | |
13757 | return r10k_uncached_address_p (INTVAL (x)); | |
13758 | ||
13759 | /* Check for accesses to a static object. */ | |
13760 | split_const (x, &base, &offset); | |
13761 | return offset_within_block_p (base, INTVAL (offset)); | |
13762 | } | |
13763 | ||
13764 | /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is | |
13765 | an in-range access to an automatic variable, or to an object with | |
13766 | a link-time-constant address. */ | |
13767 | ||
13768 | static bool | |
527210c4 | 13769 | r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset) |
4d210b07 | 13770 | { |
527210c4 | 13771 | if (offset < 0 || offset >= int_size_in_bytes (TREE_TYPE (expr))) |
4d210b07 RS |
13772 | return false; |
13773 | ||
13774 | while (TREE_CODE (expr) == COMPONENT_REF) | |
13775 | { | |
13776 | expr = TREE_OPERAND (expr, 0); | |
13777 | if (expr == NULL_TREE) | |
13778 | return false; | |
13779 | } | |
13780 | ||
13781 | return DECL_P (expr); | |
13782 | } | |
13783 | ||
13784 | /* A for_each_rtx callback for which DATA points to the instruction | |
13785 | containing *X. Stop the search if we find a MEM that is not safe | |
13786 | from R10K speculation. */ | |
13787 | ||
13788 | static int | |
13789 | r10k_needs_protection_p_1 (rtx *loc, void *data) | |
13790 | { | |
13791 | rtx mem; | |
13792 | ||
13793 | mem = *loc; | |
13794 | if (!MEM_P (mem)) | |
13795 | return 0; | |
13796 | ||
527210c4 RS |
13797 | if (MEM_EXPR (mem) |
13798 | && MEM_OFFSET_KNOWN_P (mem) | |
13799 | && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem))) | |
4d210b07 RS |
13800 | return -1; |
13801 | ||
13802 | if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data)) | |
13803 | return -1; | |
13804 | ||
13805 | return 1; | |
13806 | } | |
13807 | ||
13808 | /* A note_stores callback for which DATA points to an instruction pointer. | |
13809 | If *DATA is nonnull, make it null if it X contains a MEM that is not | |
13810 | safe from R10K speculation. */ | |
13811 | ||
13812 | static void | |
13813 | r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED, | |
13814 | void *data) | |
13815 | { | |
13816 | rtx *insn_ptr; | |
13817 | ||
13818 | insn_ptr = (rtx *) data; | |
13819 | if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr)) | |
13820 | *insn_ptr = NULL_RTX; | |
13821 | } | |
13822 | ||
13823 | /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN. | |
13824 | Return nonzero if the call is not to a declared function. */ | |
13825 | ||
13826 | static int | |
13827 | r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
13828 | { | |
13829 | rtx x; | |
13830 | ||
13831 | x = *loc; | |
13832 | if (!MEM_P (x)) | |
13833 | return 0; | |
13834 | ||
13835 | x = XEXP (x, 0); | |
13836 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x)) | |
13837 | return -1; | |
13838 | ||
13839 | return 1; | |
13840 | } | |
13841 | ||
13842 | /* Return true if instruction INSN needs to be protected by an R10K | |
13843 | cache barrier. */ | |
13844 | ||
13845 | static bool | |
13846 | r10k_needs_protection_p (rtx insn) | |
13847 | { | |
13848 | if (CALL_P (insn)) | |
13849 | return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL); | |
13850 | ||
13851 | if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE) | |
13852 | { | |
13853 | note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn); | |
13854 | return insn == NULL_RTX; | |
13855 | } | |
13856 | ||
13857 | return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn); | |
13858 | } | |
13859 | ||
13860 | /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every | |
13861 | edge is unconditional. */ | |
13862 | ||
13863 | static bool | |
13864 | r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs) | |
13865 | { | |
13866 | edge_iterator ei; | |
13867 | edge e; | |
13868 | ||
13869 | FOR_EACH_EDGE (e, ei, bb->preds) | |
13870 | if (!single_succ_p (e->src) | |
13871 | || !TEST_BIT (protected_bbs, e->src->index) | |
13872 | || (e->flags & EDGE_COMPLEX) != 0) | |
13873 | return false; | |
13874 | return true; | |
13875 | } | |
13876 | ||
13877 | /* Implement -mr10k-cache-barrier= for the current function. */ | |
13878 | ||
13879 | static void | |
13880 | r10k_insert_cache_barriers (void) | |
13881 | { | |
13882 | int *rev_post_order; | |
13883 | unsigned int i, n; | |
13884 | basic_block bb; | |
13885 | sbitmap protected_bbs; | |
13886 | rtx insn, end, unprotected_region; | |
13887 | ||
13888 | if (TARGET_MIPS16) | |
13889 | { | |
13890 | sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier"); | |
13891 | return; | |
13892 | } | |
13893 | ||
4d210b07 RS |
13894 | /* Calculate dominators. */ |
13895 | calculate_dominance_info (CDI_DOMINATORS); | |
13896 | ||
13897 | /* Bit X of PROTECTED_BBS is set if the last operation in basic block | |
13898 | X is protected by a cache barrier. */ | |
13899 | protected_bbs = sbitmap_alloc (last_basic_block); | |
13900 | sbitmap_zero (protected_bbs); | |
13901 | ||
13902 | /* Iterate over the basic blocks in reverse post-order. */ | |
13903 | rev_post_order = XNEWVEC (int, last_basic_block); | |
13904 | n = pre_and_rev_post_order_compute (NULL, rev_post_order, false); | |
13905 | for (i = 0; i < n; i++) | |
13906 | { | |
13907 | bb = BASIC_BLOCK (rev_post_order[i]); | |
13908 | ||
13909 | /* If this block is only reached by unconditional edges, and if the | |
13910 | source of every edge is protected, the beginning of the block is | |
13911 | also protected. */ | |
13912 | if (r10k_protected_bb_p (bb, protected_bbs)) | |
13913 | unprotected_region = NULL_RTX; | |
13914 | else | |
13915 | unprotected_region = pc_rtx; | |
13916 | end = NEXT_INSN (BB_END (bb)); | |
13917 | ||
13918 | /* UNPROTECTED_REGION is: | |
13919 | ||
13920 | - null if we are processing a protected region, | |
13921 | - pc_rtx if we are processing an unprotected region but have | |
13922 | not yet found the first instruction in it | |
13923 | - the first instruction in an unprotected region otherwise. */ | |
13924 | for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn)) | |
13925 | { | |
006b29ab | 13926 | if (unprotected_region && USEFUL_INSN_P (insn)) |
4d210b07 RS |
13927 | { |
13928 | if (recog_memoized (insn) == CODE_FOR_mips_cache) | |
13929 | /* This CACHE instruction protects the following code. */ | |
13930 | unprotected_region = NULL_RTX; | |
13931 | else | |
13932 | { | |
13933 | /* See if INSN is the first instruction in this | |
13934 | unprotected region. */ | |
13935 | if (unprotected_region == pc_rtx) | |
13936 | unprotected_region = insn; | |
13937 | ||
13938 | /* See if INSN needs to be protected. If so, | |
13939 | we must insert a cache barrier somewhere between | |
13940 | PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't | |
13941 | clear which position is better performance-wise, | |
13942 | but as a tie-breaker, we assume that it is better | |
13943 | to allow delay slots to be back-filled where | |
13944 | possible, and that it is better not to insert | |
13945 | barriers in the middle of already-scheduled code. | |
13946 | We therefore insert the barrier at the beginning | |
13947 | of the region. */ | |
13948 | if (r10k_needs_protection_p (insn)) | |
13949 | { | |
13950 | emit_insn_before (gen_r10k_cache_barrier (), | |
13951 | unprotected_region); | |
13952 | unprotected_region = NULL_RTX; | |
13953 | } | |
13954 | } | |
13955 | } | |
13956 | ||
13957 | if (CALL_P (insn)) | |
13958 | /* The called function is not required to protect the exit path. | |
13959 | The code that follows a call is therefore unprotected. */ | |
13960 | unprotected_region = pc_rtx; | |
13961 | } | |
13962 | ||
13963 | /* Record whether the end of this block is protected. */ | |
13964 | if (unprotected_region == NULL_RTX) | |
13965 | SET_BIT (protected_bbs, bb->index); | |
13966 | } | |
13967 | XDELETEVEC (rev_post_order); | |
13968 | ||
13969 | sbitmap_free (protected_bbs); | |
13970 | ||
13971 | free_dominance_info (CDI_DOMINATORS); | |
b53da244 AN |
13972 | } |
13973 | \f | |
13974 | /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX | |
951771dc JW |
13975 | otherwise. If INSN has two call rtx, then store the second one in |
13976 | SECOND_CALL. */ | |
4d210b07 | 13977 | |
b53da244 | 13978 | static rtx |
951771dc | 13979 | mips_call_expr_from_insn (rtx insn, rtx *second_call) |
b53da244 AN |
13980 | { |
13981 | rtx x; | |
951771dc | 13982 | rtx x2; |
b53da244 AN |
13983 | |
13984 | if (!CALL_P (insn)) | |
13985 | return NULL_RTX; | |
4d210b07 | 13986 | |
b53da244 AN |
13987 | x = PATTERN (insn); |
13988 | if (GET_CODE (x) == PARALLEL) | |
951771dc JW |
13989 | { |
13990 | /* Calls returning complex values have two CALL rtx. Look for the second | |
13991 | one here, and return it via the SECOND_CALL arg. */ | |
13992 | x2 = XVECEXP (x, 0, 1); | |
13993 | if (GET_CODE (x2) == SET) | |
13994 | x2 = XEXP (x2, 1); | |
13995 | if (GET_CODE (x2) == CALL) | |
13996 | *second_call = x2; | |
13997 | ||
13998 | x = XVECEXP (x, 0, 0); | |
13999 | } | |
b53da244 AN |
14000 | if (GET_CODE (x) == SET) |
14001 | x = XEXP (x, 1); | |
b53da244 | 14002 | gcc_assert (GET_CODE (x) == CALL); |
951771dc | 14003 | |
b53da244 AN |
14004 | return x; |
14005 | } | |
14006 | ||
14007 | /* REG is set in DEF. See if the definition is one of the ways we load a | |
ee3ee488 RS |
14008 | register with a symbol address for a mips_use_pic_fn_addr_reg_p call. |
14009 | If it is, return the symbol reference of the function, otherwise return | |
14010 | NULL_RTX. | |
14011 | ||
14012 | If RECURSE_P is true, use mips_find_pic_call_symbol to interpret | |
14013 | the values of source registers, otherwise treat such registers as | |
14014 | having an unknown value. */ | |
b53da244 AN |
14015 | |
14016 | static rtx | |
ee3ee488 | 14017 | mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p) |
b53da244 AN |
14018 | { |
14019 | rtx def_insn, set; | |
14020 | ||
14021 | if (DF_REF_IS_ARTIFICIAL (def)) | |
14022 | return NULL_RTX; | |
14023 | ||
14024 | def_insn = DF_REF_INSN (def); | |
14025 | set = single_set (def_insn); | |
14026 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
14027 | { | |
14028 | rtx note, src, symbol; | |
14029 | ||
14030 | /* First, look at REG_EQUAL/EQUIV notes. */ | |
14031 | note = find_reg_equal_equiv_note (def_insn); | |
14032 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
14033 | return XEXP (note, 0); | |
14034 | ||
14035 | /* For %call16 references we don't have REG_EQUAL. */ | |
14036 | src = SET_SRC (set); | |
14037 | symbol = mips_strip_unspec_call (src); | |
14038 | if (symbol) | |
14039 | { | |
14040 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
14041 | return symbol; | |
14042 | } | |
14043 | ||
ee3ee488 RS |
14044 | /* Follow at most one simple register copy. Such copies are |
14045 | interesting in cases like: | |
14046 | ||
14047 | for (...) | |
14048 | { | |
14049 | locally_binding_fn (...); | |
14050 | } | |
14051 | ||
14052 | and: | |
14053 | ||
14054 | locally_binding_fn (...); | |
14055 | ... | |
14056 | locally_binding_fn (...); | |
14057 | ||
14058 | where the load of locally_binding_fn can legitimately be | |
14059 | hoisted or shared. However, we do not expect to see complex | |
14060 | chains of copies, so a full worklist solution to the problem | |
14061 | would probably be overkill. */ | |
14062 | if (recurse_p && REG_P (src)) | |
14063 | return mips_find_pic_call_symbol (def_insn, src, false); | |
b53da244 AN |
14064 | } |
14065 | ||
14066 | return NULL_RTX; | |
14067 | } | |
14068 | ||
ee3ee488 RS |
14069 | /* Find the definition of the use of REG in INSN. See if the definition |
14070 | is one of the ways we load a register with a symbol address for a | |
14071 | mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference | |
14072 | of the function, otherwise return NULL_RTX. RECURSE_P is as for | |
14073 | mips_pic_call_symbol_from_set. */ | |
b53da244 AN |
14074 | |
14075 | static rtx | |
ee3ee488 | 14076 | mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p) |
b53da244 AN |
14077 | { |
14078 | df_ref use; | |
14079 | struct df_link *defs; | |
14080 | rtx symbol; | |
14081 | ||
14082 | use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]); | |
14083 | if (!use) | |
14084 | return NULL_RTX; | |
14085 | defs = DF_REF_CHAIN (use); | |
14086 | if (!defs) | |
14087 | return NULL_RTX; | |
ee3ee488 | 14088 | symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); |
b53da244 AN |
14089 | if (!symbol) |
14090 | return NULL_RTX; | |
14091 | ||
14092 | /* If we have more than one definition, they need to be identical. */ | |
14093 | for (defs = defs->next; defs; defs = defs->next) | |
14094 | { | |
14095 | rtx other; | |
14096 | ||
ee3ee488 | 14097 | other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); |
b53da244 AN |
14098 | if (!rtx_equal_p (symbol, other)) |
14099 | return NULL_RTX; | |
14100 | } | |
14101 | ||
14102 | return symbol; | |
14103 | } | |
14104 | ||
14105 | /* Replace the args_size operand of the call expression CALL with the | |
14106 | call-attribute UNSPEC and fill in SYMBOL as the function symbol. */ | |
14107 | ||
14108 | static void | |
14109 | mips_annotate_pic_call_expr (rtx call, rtx symbol) | |
14110 | { | |
14111 | rtx args_size; | |
14112 | ||
14113 | args_size = XEXP (call, 1); | |
14114 | XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size), | |
14115 | gen_rtvec (2, args_size, symbol), | |
14116 | UNSPEC_CALL_ATTR); | |
14117 | } | |
14118 | ||
14119 | /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See | |
14120 | if instead of the arg_size argument it contains the call attributes. If | |
14121 | yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function | |
14122 | symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is | |
14123 | -1. */ | |
14124 | ||
14125 | bool | |
14126 | mips_get_pic_call_symbol (rtx *operands, int args_size_opno) | |
14127 | { | |
14128 | rtx args_size, symbol; | |
14129 | ||
14130 | if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1) | |
14131 | return false; | |
14132 | ||
14133 | args_size = operands[args_size_opno]; | |
14134 | if (GET_CODE (args_size) != UNSPEC) | |
14135 | return false; | |
14136 | gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR); | |
14137 | ||
14138 | symbol = XVECEXP (args_size, 0, 1); | |
14139 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
14140 | ||
14141 | operands[args_size_opno] = symbol; | |
14142 | return true; | |
14143 | } | |
14144 | ||
14145 | /* Use DF to annotate PIC indirect calls with the function symbol they | |
14146 | dispatch to. */ | |
14147 | ||
14148 | static void | |
14149 | mips_annotate_pic_calls (void) | |
14150 | { | |
14151 | basic_block bb; | |
14152 | rtx insn; | |
14153 | ||
14154 | FOR_EACH_BB (bb) | |
14155 | FOR_BB_INSNS (bb, insn) | |
14156 | { | |
951771dc | 14157 | rtx call, reg, symbol, second_call; |
b53da244 | 14158 | |
951771dc JW |
14159 | second_call = 0; |
14160 | call = mips_call_expr_from_insn (insn, &second_call); | |
b53da244 AN |
14161 | if (!call) |
14162 | continue; | |
14163 | gcc_assert (MEM_P (XEXP (call, 0))); | |
14164 | reg = XEXP (XEXP (call, 0), 0); | |
14165 | if (!REG_P (reg)) | |
14166 | continue; | |
14167 | ||
ee3ee488 | 14168 | symbol = mips_find_pic_call_symbol (insn, reg, true); |
b53da244 | 14169 | if (symbol) |
951771dc JW |
14170 | { |
14171 | mips_annotate_pic_call_expr (call, symbol); | |
14172 | if (second_call) | |
14173 | mips_annotate_pic_call_expr (second_call, symbol); | |
14174 | } | |
b53da244 | 14175 | } |
4d210b07 RS |
14176 | } |
14177 | \f | |
ab77a036 RS |
14178 | /* A temporary variable used by for_each_rtx callbacks, etc. */ |
14179 | static rtx mips_sim_insn; | |
39ba1719 | 14180 | |
ab77a036 RS |
14181 | /* A structure representing the state of the processor pipeline. |
14182 | Used by the mips_sim_* family of functions. */ | |
14183 | struct mips_sim { | |
14184 | /* The maximum number of instructions that can be issued in a cycle. | |
14185 | (Caches mips_issue_rate.) */ | |
14186 | unsigned int issue_rate; | |
39ba1719 | 14187 | |
ab77a036 RS |
14188 | /* The current simulation time. */ |
14189 | unsigned int time; | |
39ba1719 | 14190 | |
ab77a036 RS |
14191 | /* How many more instructions can be issued in the current cycle. */ |
14192 | unsigned int insns_left; | |
39ba1719 | 14193 | |
ab77a036 RS |
14194 | /* LAST_SET[X].INSN is the last instruction to set register X. |
14195 | LAST_SET[X].TIME is the time at which that instruction was issued. | |
14196 | INSN is null if no instruction has yet set register X. */ | |
14197 | struct { | |
14198 | rtx insn; | |
14199 | unsigned int time; | |
14200 | } last_set[FIRST_PSEUDO_REGISTER]; | |
39ba1719 | 14201 | |
ab77a036 RS |
14202 | /* The pipeline's current DFA state. */ |
14203 | state_t dfa_state; | |
14204 | }; | |
39ba1719 | 14205 | |
ab77a036 RS |
14206 | /* Reset STATE to the initial simulation state. */ |
14207 | ||
14208 | static void | |
14209 | mips_sim_reset (struct mips_sim *state) | |
14210 | { | |
14211 | state->time = 0; | |
14212 | state->insns_left = state->issue_rate; | |
14213 | memset (&state->last_set, 0, sizeof (state->last_set)); | |
14214 | state_reset (state->dfa_state); | |
39ba1719 | 14215 | } |
39ba1719 | 14216 | |
ab77a036 RS |
14217 | /* Initialize STATE before its first use. DFA_STATE points to an |
14218 | allocated but uninitialized DFA state. */ | |
39ba1719 | 14219 | |
ab77a036 RS |
14220 | static void |
14221 | mips_sim_init (struct mips_sim *state, state_t dfa_state) | |
14222 | { | |
14223 | state->issue_rate = mips_issue_rate (); | |
14224 | state->dfa_state = dfa_state; | |
14225 | mips_sim_reset (state); | |
14226 | } | |
14227 | ||
14228 | /* Advance STATE by one clock cycle. */ | |
39ba1719 RS |
14229 | |
14230 | static void | |
ab77a036 | 14231 | mips_sim_next_cycle (struct mips_sim *state) |
39ba1719 | 14232 | { |
ab77a036 RS |
14233 | state->time++; |
14234 | state->insns_left = state->issue_rate; | |
14235 | state_transition (state->dfa_state, 0); | |
39ba1719 RS |
14236 | } |
14237 | ||
ab77a036 RS |
14238 | /* Advance simulation state STATE until instruction INSN can read |
14239 | register REG. */ | |
39ba1719 RS |
14240 | |
14241 | static void | |
ab77a036 | 14242 | mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg) |
39ba1719 | 14243 | { |
65239d20 | 14244 | unsigned int regno, end_regno; |
39ba1719 | 14245 | |
65239d20 RS |
14246 | end_regno = END_REGNO (reg); |
14247 | for (regno = REGNO (reg); regno < end_regno; regno++) | |
14248 | if (state->last_set[regno].insn != 0) | |
ab77a036 RS |
14249 | { |
14250 | unsigned int t; | |
dc884a86 | 14251 | |
65239d20 RS |
14252 | t = (state->last_set[regno].time |
14253 | + insn_latency (state->last_set[regno].insn, insn)); | |
ab77a036 RS |
14254 | while (state->time < t) |
14255 | mips_sim_next_cycle (state); | |
14256 | } | |
14257 | } | |
dc884a86 | 14258 | |
ab77a036 RS |
14259 | /* A for_each_rtx callback. If *X is a register, advance simulation state |
14260 | DATA until mips_sim_insn can read the register's value. */ | |
dc884a86 | 14261 | |
ab77a036 RS |
14262 | static int |
14263 | mips_sim_wait_regs_2 (rtx *x, void *data) | |
dc884a86 | 14264 | { |
ab77a036 | 14265 | if (REG_P (*x)) |
5ead67f6 | 14266 | mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x); |
ab77a036 | 14267 | return 0; |
dc884a86 RS |
14268 | } |
14269 | ||
ab77a036 | 14270 | /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */ |
dc884a86 | 14271 | |
ab77a036 RS |
14272 | static void |
14273 | mips_sim_wait_regs_1 (rtx *x, void *data) | |
dc884a86 | 14274 | { |
ab77a036 | 14275 | for_each_rtx (x, mips_sim_wait_regs_2, data); |
dc884a86 RS |
14276 | } |
14277 | ||
ab77a036 RS |
14278 | /* Advance simulation state STATE until all of INSN's register |
14279 | dependencies are satisfied. */ | |
dc884a86 | 14280 | |
ab77a036 RS |
14281 | static void |
14282 | mips_sim_wait_regs (struct mips_sim *state, rtx insn) | |
dc884a86 | 14283 | { |
ab77a036 RS |
14284 | mips_sim_insn = insn; |
14285 | note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state); | |
14286 | } | |
dc884a86 | 14287 | |
ab77a036 RS |
14288 | /* Advance simulation state STATE until the units required by |
14289 | instruction INSN are available. */ | |
dc884a86 | 14290 | |
ab77a036 RS |
14291 | static void |
14292 | mips_sim_wait_units (struct mips_sim *state, rtx insn) | |
14293 | { | |
14294 | state_t tmp_state; | |
dc884a86 | 14295 | |
ab77a036 RS |
14296 | tmp_state = alloca (state_size ()); |
14297 | while (state->insns_left == 0 | |
14298 | || (memcpy (tmp_state, state->dfa_state, state_size ()), | |
14299 | state_transition (tmp_state, insn) >= 0)) | |
14300 | mips_sim_next_cycle (state); | |
dc884a86 RS |
14301 | } |
14302 | ||
ab77a036 | 14303 | /* Advance simulation state STATE until INSN is ready to issue. */ |
dc884a86 RS |
14304 | |
14305 | static void | |
ab77a036 | 14306 | mips_sim_wait_insn (struct mips_sim *state, rtx insn) |
dc884a86 | 14307 | { |
ab77a036 RS |
14308 | mips_sim_wait_regs (state, insn); |
14309 | mips_sim_wait_units (state, insn); | |
dc884a86 | 14310 | } |
ab77a036 RS |
14311 | |
14312 | /* mips_sim_insn has just set X. Update the LAST_SET array | |
14313 | in simulation state DATA. */ | |
39ba1719 RS |
14314 | |
14315 | static void | |
ab77a036 | 14316 | mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
39ba1719 | 14317 | { |
ab77a036 | 14318 | struct mips_sim *state; |
39ba1719 | 14319 | |
5ead67f6 | 14320 | state = (struct mips_sim *) data; |
ab77a036 | 14321 | if (REG_P (x)) |
65239d20 RS |
14322 | { |
14323 | unsigned int regno, end_regno; | |
14324 | ||
14325 | end_regno = END_REGNO (x); | |
14326 | for (regno = REGNO (x); regno < end_regno; regno++) | |
14327 | { | |
14328 | state->last_set[regno].insn = mips_sim_insn; | |
14329 | state->last_set[regno].time = state->time; | |
14330 | } | |
14331 | } | |
39ba1719 RS |
14332 | } |
14333 | ||
ab77a036 RS |
14334 | /* Issue instruction INSN in scheduler state STATE. Assume that INSN |
14335 | can issue immediately (i.e., that mips_sim_wait_insn has already | |
14336 | been called). */ | |
39ba1719 | 14337 | |
174bd8ca | 14338 | static void |
ab77a036 | 14339 | mips_sim_issue_insn (struct mips_sim *state, rtx insn) |
174bd8ca | 14340 | { |
ab77a036 RS |
14341 | state_transition (state->dfa_state, insn); |
14342 | state->insns_left--; | |
174bd8ca | 14343 | |
ab77a036 RS |
14344 | mips_sim_insn = insn; |
14345 | note_stores (PATTERN (insn), mips_sim_record_set, state); | |
14346 | } | |
174bd8ca | 14347 | |
ab77a036 | 14348 | /* Simulate issuing a NOP in state STATE. */ |
174bd8ca SL |
14349 | |
14350 | static void | |
ab77a036 | 14351 | mips_sim_issue_nop (struct mips_sim *state) |
174bd8ca | 14352 | { |
ab77a036 RS |
14353 | if (state->insns_left == 0) |
14354 | mips_sim_next_cycle (state); | |
14355 | state->insns_left--; | |
174bd8ca SL |
14356 | } |
14357 | ||
ab77a036 RS |
14358 | /* Update simulation state STATE so that it's ready to accept the instruction |
14359 | after INSN. INSN should be part of the main rtl chain, not a member of a | |
14360 | SEQUENCE. */ | |
174bd8ca SL |
14361 | |
14362 | static void | |
ab77a036 | 14363 | mips_sim_finish_insn (struct mips_sim *state, rtx insn) |
39ba1719 | 14364 | { |
ab77a036 RS |
14365 | /* If INSN is a jump with an implicit delay slot, simulate a nop. */ |
14366 | if (JUMP_P (insn)) | |
14367 | mips_sim_issue_nop (state); | |
174bd8ca | 14368 | |
ab77a036 | 14369 | switch (GET_CODE (SEQ_BEGIN (insn))) |
39ba1719 | 14370 | { |
ab77a036 RS |
14371 | case CODE_LABEL: |
14372 | case CALL_INSN: | |
14373 | /* We can't predict the processor state after a call or label. */ | |
14374 | mips_sim_reset (state); | |
14375 | break; | |
d33289b2 | 14376 | |
ab77a036 RS |
14377 | case JUMP_INSN: |
14378 | /* The delay slots of branch likely instructions are only executed | |
14379 | when the branch is taken. Therefore, if the caller has simulated | |
14380 | the delay slot instruction, STATE does not really reflect the state | |
14381 | of the pipeline for the instruction after the delay slot. Also, | |
14382 | branch likely instructions tend to incur a penalty when not taken, | |
14383 | so there will probably be an extra delay between the branch and | |
14384 | the instruction after the delay slot. */ | |
14385 | if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn))) | |
14386 | mips_sim_reset (state); | |
14387 | break; | |
d33289b2 | 14388 | |
ab77a036 RS |
14389 | default: |
14390 | break; | |
dc884a86 | 14391 | } |
174bd8ca | 14392 | } |
ab77a036 RS |
14393 | \f |
14394 | /* The VR4130 pipeline issues aligned pairs of instructions together, | |
14395 | but it stalls the second instruction if it depends on the first. | |
14396 | In order to cut down the amount of logic required, this dependence | |
14397 | check is not based on a full instruction decode. Instead, any non-SPECIAL | |
14398 | instruction is assumed to modify the register specified by bits 20-16 | |
14399 | (which is usually the "rt" field). | |
174bd8ca | 14400 | |
65239d20 | 14401 | In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an |
ab77a036 RS |
14402 | input, so we can end up with a false dependence between the branch |
14403 | and its delay slot. If this situation occurs in instruction INSN, | |
14404 | try to avoid it by swapping rs and rt. */ | |
174bd8ca SL |
14405 | |
14406 | static void | |
ab77a036 | 14407 | vr4130_avoid_branch_rt_conflict (rtx insn) |
174bd8ca | 14408 | { |
ab77a036 | 14409 | rtx first, second; |
39ba1719 | 14410 | |
ab77a036 RS |
14411 | first = SEQ_BEGIN (insn); |
14412 | second = SEQ_END (insn); | |
14413 | if (JUMP_P (first) | |
14414 | && NONJUMP_INSN_P (second) | |
14415 | && GET_CODE (PATTERN (first)) == SET | |
14416 | && GET_CODE (SET_DEST (PATTERN (first))) == PC | |
14417 | && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE) | |
39ba1719 | 14418 | { |
ab77a036 RS |
14419 | /* Check for the right kind of condition. */ |
14420 | rtx cond = XEXP (SET_SRC (PATTERN (first)), 0); | |
14421 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
14422 | && REG_P (XEXP (cond, 0)) | |
14423 | && REG_P (XEXP (cond, 1)) | |
14424 | && reg_referenced_p (XEXP (cond, 1), PATTERN (second)) | |
14425 | && !reg_referenced_p (XEXP (cond, 0), PATTERN (second))) | |
14426 | { | |
14427 | /* SECOND mentions the rt register but not the rs register. */ | |
14428 | rtx tmp = XEXP (cond, 0); | |
14429 | XEXP (cond, 0) = XEXP (cond, 1); | |
14430 | XEXP (cond, 1) = tmp; | |
14431 | } | |
39ba1719 | 14432 | } |
39ba1719 RS |
14433 | } |
14434 | ||
ab77a036 RS |
14435 | /* Implement -mvr4130-align. Go through each basic block and simulate the |
14436 | processor pipeline. If we find that a pair of instructions could execute | |
65239d20 | 14437 | in parallel, and the first of those instructions is not 8-byte aligned, |
ab77a036 | 14438 | insert a nop to make it aligned. */ |
0c8da560 | 14439 | |
ab77a036 RS |
14440 | static void |
14441 | vr4130_align_insns (void) | |
b875d2ee | 14442 | { |
ab77a036 RS |
14443 | struct mips_sim state; |
14444 | rtx insn, subinsn, last, last2, next; | |
14445 | bool aligned_p; | |
b875d2ee | 14446 | |
ab77a036 | 14447 | dfa_start (); |
50d32cf6 | 14448 | |
ab77a036 RS |
14449 | /* LAST is the last instruction before INSN to have a nonzero length. |
14450 | LAST2 is the last such instruction before LAST. */ | |
14451 | last = 0; | |
14452 | last2 = 0; | |
54401342 | 14453 | |
ab77a036 RS |
14454 | /* ALIGNED_P is true if INSN is known to be at an aligned address. */ |
14455 | aligned_p = true; | |
50d32cf6 | 14456 | |
ab77a036 RS |
14457 | mips_sim_init (&state, alloca (state_size ())); |
14458 | for (insn = get_insns (); insn != 0; insn = next) | |
14459 | { | |
14460 | unsigned int length; | |
50d32cf6 | 14461 | |
ab77a036 | 14462 | next = NEXT_INSN (insn); |
c81d6e2a | 14463 | |
ab77a036 RS |
14464 | /* See the comment above vr4130_avoid_branch_rt_conflict for details. |
14465 | This isn't really related to the alignment pass, but we do it on | |
14466 | the fly to avoid a separate instruction walk. */ | |
14467 | vr4130_avoid_branch_rt_conflict (insn); | |
c81d6e2a | 14468 | |
ab77a036 RS |
14469 | if (USEFUL_INSN_P (insn)) |
14470 | FOR_EACH_SUBINSN (subinsn, insn) | |
14471 | { | |
14472 | mips_sim_wait_insn (&state, subinsn); | |
c81d6e2a | 14473 | |
ab77a036 RS |
14474 | /* If we want this instruction to issue in parallel with the |
14475 | previous one, make sure that the previous instruction is | |
14476 | aligned. There are several reasons why this isn't worthwhile | |
14477 | when the second instruction is a call: | |
5ce6f47b | 14478 | |
ab77a036 RS |
14479 | - Calls are less likely to be performance critical, |
14480 | - There's a good chance that the delay slot can execute | |
14481 | in parallel with the call. | |
14482 | - The return address would then be unaligned. | |
4767c570 | 14483 | |
ab77a036 RS |
14484 | In general, if we're going to insert a nop between instructions |
14485 | X and Y, it's better to insert it immediately after X. That | |
14486 | way, if the nop makes Y aligned, it will also align any labels | |
14487 | between X and Y. */ | |
14488 | if (state.insns_left != state.issue_rate | |
14489 | && !CALL_P (subinsn)) | |
14490 | { | |
14491 | if (subinsn == SEQ_BEGIN (insn) && aligned_p) | |
14492 | { | |
14493 | /* SUBINSN is the first instruction in INSN and INSN is | |
14494 | aligned. We want to align the previous instruction | |
14495 | instead, so insert a nop between LAST2 and LAST. | |
8f2e3902 | 14496 | |
ab77a036 RS |
14497 | Note that LAST could be either a single instruction |
14498 | or a branch with a delay slot. In the latter case, | |
14499 | LAST, like INSN, is already aligned, but the delay | |
14500 | slot must have some extra delay that stops it from | |
14501 | issuing at the same time as the branch. We therefore | |
14502 | insert a nop before the branch in order to align its | |
14503 | delay slot. */ | |
14504 | emit_insn_after (gen_nop (), last2); | |
14505 | aligned_p = false; | |
14506 | } | |
14507 | else if (subinsn != SEQ_BEGIN (insn) && !aligned_p) | |
14508 | { | |
14509 | /* SUBINSN is the delay slot of INSN, but INSN is | |
14510 | currently unaligned. Insert a nop between | |
14511 | LAST and INSN to align it. */ | |
14512 | emit_insn_after (gen_nop (), last); | |
14513 | aligned_p = true; | |
14514 | } | |
14515 | } | |
14516 | mips_sim_issue_insn (&state, subinsn); | |
14517 | } | |
14518 | mips_sim_finish_insn (&state, insn); | |
06a4ab70 | 14519 | |
ab77a036 RS |
14520 | /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ |
14521 | length = get_attr_length (insn); | |
14522 | if (length > 0) | |
14523 | { | |
14524 | /* If the instruction is an asm statement or multi-instruction | |
14525 | mips.md patern, the length is only an estimate. Insert an | |
14526 | 8 byte alignment after it so that the following instructions | |
14527 | can be handled correctly. */ | |
14528 | if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) | |
14529 | && (recog_memoized (insn) < 0 || length >= 8)) | |
14530 | { | |
14531 | next = emit_insn_after (gen_align (GEN_INT (3)), insn); | |
14532 | next = NEXT_INSN (next); | |
14533 | mips_sim_next_cycle (&state); | |
14534 | aligned_p = true; | |
14535 | } | |
14536 | else if (length & 4) | |
14537 | aligned_p = !aligned_p; | |
14538 | last2 = last; | |
14539 | last = insn; | |
14540 | } | |
4ca1f68f | 14541 | |
ab77a036 RS |
14542 | /* See whether INSN is an aligned label. */ |
14543 | if (LABEL_P (insn) && label_to_alignment (insn) >= 3) | |
14544 | aligned_p = true; | |
14545 | } | |
14546 | dfa_finish (); | |
14547 | } | |
14548 | \f | |
a35de342 RS |
14549 | /* This structure records that the current function has a LO_SUM |
14550 | involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is | |
14551 | the largest offset applied to BASE by all such LO_SUMs. */ | |
14552 | struct mips_lo_sum_offset { | |
14553 | rtx base; | |
14554 | HOST_WIDE_INT offset; | |
14555 | }; | |
14556 | ||
14557 | /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ | |
14558 | ||
14559 | static hashval_t | |
14560 | mips_hash_base (rtx base) | |
14561 | { | |
14562 | int do_not_record_p; | |
14563 | ||
14564 | return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); | |
14565 | } | |
14566 | ||
14567 | /* Hash-table callbacks for mips_lo_sum_offsets. */ | |
14568 | ||
14569 | static hashval_t | |
14570 | mips_lo_sum_offset_hash (const void *entry) | |
14571 | { | |
14572 | return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base); | |
14573 | } | |
14574 | ||
14575 | static int | |
14576 | mips_lo_sum_offset_eq (const void *entry, const void *value) | |
14577 | { | |
14578 | return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base, | |
14579 | (const_rtx) value); | |
14580 | } | |
14581 | ||
14582 | /* Look up symbolic constant X in HTAB, which is a hash table of | |
14583 | mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be | |
14584 | paired with a recorded LO_SUM, otherwise record X in the table. */ | |
14585 | ||
14586 | static bool | |
14587 | mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option) | |
14588 | { | |
14589 | rtx base, offset; | |
14590 | void **slot; | |
14591 | struct mips_lo_sum_offset *entry; | |
14592 | ||
14593 | /* Split X into a base and offset. */ | |
14594 | split_const (x, &base, &offset); | |
14595 | if (UNSPEC_ADDRESS_P (base)) | |
14596 | base = UNSPEC_ADDRESS (base); | |
14597 | ||
14598 | /* Look up the base in the hash table. */ | |
14599 | slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option); | |
14600 | if (slot == NULL) | |
14601 | return false; | |
14602 | ||
14603 | entry = (struct mips_lo_sum_offset *) *slot; | |
14604 | if (option == INSERT) | |
14605 | { | |
14606 | if (entry == NULL) | |
14607 | { | |
14608 | entry = XNEW (struct mips_lo_sum_offset); | |
14609 | entry->base = base; | |
14610 | entry->offset = INTVAL (offset); | |
14611 | *slot = entry; | |
14612 | } | |
14613 | else | |
14614 | { | |
14615 | if (INTVAL (offset) > entry->offset) | |
14616 | entry->offset = INTVAL (offset); | |
14617 | } | |
14618 | } | |
14619 | return INTVAL (offset) <= entry->offset; | |
14620 | } | |
14621 | ||
14622 | /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table. | |
14623 | Record every LO_SUM in *LOC. */ | |
14624 | ||
14625 | static int | |
14626 | mips_record_lo_sum (rtx *loc, void *data) | |
14627 | { | |
14628 | if (GET_CODE (*loc) == LO_SUM) | |
14629 | mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT); | |
14630 | return 0; | |
14631 | } | |
14632 | ||
14633 | /* Return true if INSN is a SET of an orphaned high-part relocation. | |
14634 | HTAB is a hash table of mips_lo_sum_offsets that describes all the | |
14635 | LO_SUMs in the current function. */ | |
14636 | ||
14637 | static bool | |
14638 | mips_orphaned_high_part_p (htab_t htab, rtx insn) | |
14639 | { | |
14640 | enum mips_symbol_type type; | |
14641 | rtx x, set; | |
14642 | ||
14643 | set = single_set (insn); | |
14644 | if (set) | |
14645 | { | |
14646 | /* Check for %his. */ | |
14647 | x = SET_SRC (set); | |
14648 | if (GET_CODE (x) == HIGH | |
14649 | && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) | |
14650 | return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); | |
14651 | ||
14652 | /* Check for local %gots (and %got_pages, which is redundant but OK). */ | |
14653 | if (GET_CODE (x) == UNSPEC | |
14654 | && XINT (x, 1) == UNSPEC_LOAD_GOT | |
14655 | && mips_symbolic_constant_p (XVECEXP (x, 0, 1), | |
14656 | SYMBOL_CONTEXT_LEA, &type) | |
14657 | && type == SYMBOL_GOTOFF_PAGE) | |
14658 | return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT); | |
14659 | } | |
14660 | return false; | |
14661 | } | |
14662 | ||
14663 | /* Subroutine of mips_reorg_process_insns. If there is a hazard between | |
14664 | INSN and a previous instruction, avoid it by inserting nops after | |
ab77a036 | 14665 | instruction AFTER. |
308cd611 | 14666 | |
ab77a036 RS |
14667 | *DELAYED_REG and *HILO_DELAY describe the hazards that apply at |
14668 | this point. If *DELAYED_REG is non-null, INSN must wait a cycle | |
14669 | before using the value of that register. *HILO_DELAY counts the | |
14670 | number of instructions since the last hilo hazard (that is, | |
65239d20 | 14671 | the number of instructions since the last MFLO or MFHI). |
4ca1f68f | 14672 | |
ab77a036 RS |
14673 | After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY |
14674 | for the next instruction. | |
4ca1f68f | 14675 | |
ab77a036 | 14676 | LO_REG is an rtx for the LO register, used in dependence checking. */ |
4ca1f68f | 14677 | |
ab77a036 RS |
14678 | static void |
14679 | mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay, | |
14680 | rtx *delayed_reg, rtx lo_reg) | |
14681 | { | |
14682 | rtx pattern, set; | |
dbc90b65 | 14683 | int nops, ninsns; |
06a4ab70 | 14684 | |
ab77a036 | 14685 | pattern = PATTERN (insn); |
4ca1f68f | 14686 | |
ab77a036 RS |
14687 | /* Do not put the whole function in .set noreorder if it contains |
14688 | an asm statement. We don't know whether there will be hazards | |
14689 | between the asm statement and the gcc-generated code. */ | |
14690 | if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0) | |
14691 | cfun->machine->all_noreorder_p = false; | |
4ca1f68f | 14692 | |
ab77a036 RS |
14693 | /* Ignore zero-length instructions (barriers and the like). */ |
14694 | ninsns = get_attr_length (insn) / 4; | |
14695 | if (ninsns == 0) | |
14696 | return; | |
4ca1f68f | 14697 | |
ab77a036 RS |
14698 | /* Work out how many nops are needed. Note that we only care about |
14699 | registers that are explicitly mentioned in the instruction's pattern. | |
14700 | It doesn't matter that calls use the argument registers or that they | |
14701 | clobber hi and lo. */ | |
14702 | if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) | |
14703 | nops = 2 - *hilo_delay; | |
14704 | else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) | |
14705 | nops = 1; | |
14706 | else | |
14707 | nops = 0; | |
4ca1f68f | 14708 | |
ab77a036 RS |
14709 | /* Insert the nops between this instruction and the previous one. |
14710 | Each new nop takes us further from the last hilo hazard. */ | |
14711 | *hilo_delay += nops; | |
14712 | while (nops-- > 0) | |
14713 | emit_insn_after (gen_hazard_nop (), after); | |
4ca1f68f | 14714 | |
ab77a036 RS |
14715 | /* Set up the state for the next instruction. */ |
14716 | *hilo_delay += ninsns; | |
14717 | *delayed_reg = 0; | |
14718 | if (INSN_CODE (insn) >= 0) | |
14719 | switch (get_attr_hazard (insn)) | |
14720 | { | |
14721 | case HAZARD_NONE: | |
14722 | break; | |
21c425ee | 14723 | |
ab77a036 RS |
14724 | case HAZARD_HILO: |
14725 | *hilo_delay = 0; | |
14726 | break; | |
4ca1f68f | 14727 | |
ab77a036 | 14728 | case HAZARD_DELAY: |
dbc90b65 RS |
14729 | set = single_set (insn); |
14730 | gcc_assert (set); | |
ab77a036 RS |
14731 | *delayed_reg = SET_DEST (set); |
14732 | break; | |
14733 | } | |
14734 | } | |
4ca1f68f | 14735 | |
ab77a036 | 14736 | /* Go through the instruction stream and insert nops where necessary. |
a35de342 RS |
14737 | Also delete any high-part relocations whose partnering low parts |
14738 | are now all dead. See if the whole function can then be put into | |
14739 | .set noreorder and .set nomacro. */ | |
06a4ab70 | 14740 | |
ab77a036 | 14741 | static void |
a35de342 | 14742 | mips_reorg_process_insns (void) |
ab77a036 | 14743 | { |
a35de342 RS |
14744 | rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg; |
14745 | int hilo_delay; | |
14746 | htab_t htab; | |
1823bf53 | 14747 | |
ab77a036 RS |
14748 | /* Force all instructions to be split into their final form. */ |
14749 | split_all_insns_noflow (); | |
1823bf53 | 14750 | |
ab77a036 RS |
14751 | /* Recalculate instruction lengths without taking nops into account. */ |
14752 | cfun->machine->ignore_hazard_length_p = true; | |
14753 | shorten_branches (get_insns ()); | |
1823bf53 | 14754 | |
ab77a036 | 14755 | cfun->machine->all_noreorder_p = true; |
118ea793 | 14756 | |
08d0963a RS |
14757 | /* We don't track MIPS16 PC-relative offsets closely enough to make |
14758 | a good job of "set .noreorder" code in MIPS16 mode. */ | |
14759 | if (TARGET_MIPS16) | |
14760 | cfun->machine->all_noreorder_p = false; | |
14761 | ||
a35de342 RS |
14762 | /* Code that doesn't use explicit relocs can't be ".set nomacro". */ |
14763 | if (!TARGET_EXPLICIT_RELOCS) | |
14764 | cfun->machine->all_noreorder_p = false; | |
14765 | ||
ab77a036 RS |
14766 | /* Profiled functions can't be all noreorder because the profiler |
14767 | support uses assembler macros. */ | |
e3b5732b | 14768 | if (crtl->profile) |
ab77a036 | 14769 | cfun->machine->all_noreorder_p = false; |
118ea793 | 14770 | |
0eda4033 CM |
14771 | /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder |
14772 | because we rely on the assembler to work around some errata. */ | |
14773 | if (TARGET_FIX_VR4120 || TARGET_FIX_24K) | |
ab77a036 | 14774 | cfun->machine->all_noreorder_p = false; |
118ea793 | 14775 | |
65239d20 RS |
14776 | /* The same is true for -mfix-vr4130 if we might generate MFLO or |
14777 | MFHI instructions. Note that we avoid using MFLO and MFHI if | |
14778 | the VR4130 MACC and DMACC instructions are available instead; | |
ab77a036 RS |
14779 | see the *mfhilo_{si,di}_macc patterns. */ |
14780 | if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI) | |
14781 | cfun->machine->all_noreorder_p = false; | |
118ea793 | 14782 | |
a35de342 RS |
14783 | htab = htab_create (37, mips_lo_sum_offset_hash, |
14784 | mips_lo_sum_offset_eq, free); | |
14785 | ||
14786 | /* Make a first pass over the instructions, recording all the LO_SUMs. */ | |
14787 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14788 | FOR_EACH_SUBINSN (subinsn, insn) | |
006b29ab | 14789 | if (USEFUL_INSN_P (subinsn)) |
a35de342 RS |
14790 | for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab); |
14791 | ||
ab77a036 RS |
14792 | last_insn = 0; |
14793 | hilo_delay = 2; | |
14794 | delayed_reg = 0; | |
14795 | lo_reg = gen_rtx_REG (SImode, LO_REGNUM); | |
32041385 | 14796 | |
a35de342 RS |
14797 | /* Make a second pass over the instructions. Delete orphaned |
14798 | high-part relocations or turn them into NOPs. Avoid hazards | |
14799 | by inserting NOPs. */ | |
14800 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
14801 | { | |
14802 | next_insn = NEXT_INSN (insn); | |
006b29ab | 14803 | if (USEFUL_INSN_P (insn)) |
a35de342 RS |
14804 | { |
14805 | if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
14806 | { | |
14807 | /* If we find an orphaned high-part relocation in a delay | |
14808 | slot, it's easier to turn that instruction into a NOP than | |
14809 | to delete it. The delay slot will be a NOP either way. */ | |
14810 | FOR_EACH_SUBINSN (subinsn, insn) | |
14811 | if (INSN_P (subinsn)) | |
14812 | { | |
14813 | if (mips_orphaned_high_part_p (htab, subinsn)) | |
14814 | { | |
14815 | PATTERN (subinsn) = gen_nop (); | |
14816 | INSN_CODE (subinsn) = CODE_FOR_nop; | |
14817 | } | |
14818 | mips_avoid_hazard (last_insn, subinsn, &hilo_delay, | |
14819 | &delayed_reg, lo_reg); | |
14820 | } | |
14821 | last_insn = insn; | |
14822 | } | |
14823 | else | |
14824 | { | |
14825 | /* INSN is a single instruction. Delete it if it's an | |
14826 | orphaned high-part relocation. */ | |
14827 | if (mips_orphaned_high_part_p (htab, insn)) | |
14828 | delete_insn (insn); | |
4d210b07 RS |
14829 | /* Also delete cache barriers if the last instruction |
14830 | was an annulled branch. INSN will not be speculatively | |
14831 | executed. */ | |
14832 | else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier | |
14833 | && last_insn | |
14834 | && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn))) | |
14835 | delete_insn (insn); | |
a35de342 RS |
14836 | else |
14837 | { | |
14838 | mips_avoid_hazard (last_insn, insn, &hilo_delay, | |
14839 | &delayed_reg, lo_reg); | |
14840 | last_insn = insn; | |
14841 | } | |
14842 | } | |
14843 | } | |
14844 | } | |
32041385 | 14845 | |
a35de342 | 14846 | htab_delete (htab); |
ab77a036 RS |
14847 | } |
14848 | ||
0c433c31 RS |
14849 | /* If we are using a GOT, but have not decided to use a global pointer yet, |
14850 | see whether we need one to implement long branches. Convert the ghost | |
14851 | global-pointer instructions into real ones if so. */ | |
14852 | ||
14853 | static bool | |
14854 | mips_expand_ghost_gp_insns (void) | |
14855 | { | |
14856 | rtx insn; | |
14857 | int normal_length; | |
14858 | ||
14859 | /* Quick exit if we already know that we will or won't need a | |
14860 | global pointer. */ | |
14861 | if (!TARGET_USE_GOT | |
14862 | || cfun->machine->global_pointer == INVALID_REGNUM | |
14863 | || mips_must_initialize_gp_p ()) | |
14864 | return false; | |
14865 | ||
14866 | shorten_branches (get_insns ()); | |
14867 | ||
14868 | /* Look for a branch that is longer than normal. The normal length for | |
14869 | non-MIPS16 branches is 8, because the length includes the delay slot. | |
14870 | It is 4 for MIPS16, because MIPS16 branches are extended instructions, | |
14871 | but they have no delay slot. */ | |
14872 | normal_length = (TARGET_MIPS16 ? 4 : 8); | |
14873 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
14874 | if (JUMP_P (insn) | |
14875 | && USEFUL_INSN_P (insn) | |
14876 | && get_attr_length (insn) > normal_length) | |
14877 | break; | |
14878 | ||
14879 | if (insn == NULL_RTX) | |
14880 | return false; | |
14881 | ||
14882 | /* We've now established that we need $gp. */ | |
14883 | cfun->machine->must_initialize_gp_p = true; | |
14884 | split_all_insns_noflow (); | |
14885 | ||
14886 | return true; | |
14887 | } | |
14888 | ||
b53da244 AN |
14889 | /* Subroutine of mips_reorg to manage passes that require DF. */ |
14890 | ||
14891 | static void | |
14892 | mips_df_reorg (void) | |
14893 | { | |
14894 | /* Create def-use chains. */ | |
14895 | df_set_flags (DF_EQ_NOTES); | |
14896 | df_chain_add_problem (DF_UD_CHAIN); | |
14897 | df_analyze (); | |
14898 | ||
14899 | if (TARGET_RELAX_PIC_CALLS) | |
14900 | mips_annotate_pic_calls (); | |
14901 | ||
14902 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE) | |
14903 | r10k_insert_cache_barriers (); | |
14904 | ||
14905 | df_finish_pass (false); | |
14906 | } | |
14907 | ||
ab77a036 RS |
14908 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ |
14909 | ||
14910 | static void | |
14911 | mips_reorg (void) | |
32041385 | 14912 | { |
b53da244 AN |
14913 | /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during |
14914 | insn splitting in mips16_lay_out_constants, DF insn info is only kept up | |
14915 | to date if the CFG is available. */ | |
14916 | if (mips_cfg_in_reorg ()) | |
14917 | compute_bb_for_insn (); | |
ab77a036 | 14918 | mips16_lay_out_constants (); |
b53da244 AN |
14919 | if (mips_cfg_in_reorg ()) |
14920 | { | |
14921 | mips_df_reorg (); | |
14922 | free_bb_for_insn (); | |
14923 | } | |
14924 | ||
c7789bfb | 14925 | if (optimize > 0 && flag_delayed_branch) |
a35de342 RS |
14926 | dbr_schedule (get_insns ()); |
14927 | mips_reorg_process_insns (); | |
08d0963a RS |
14928 | if (!TARGET_MIPS16 |
14929 | && TARGET_EXPLICIT_RELOCS | |
14930 | && TUNE_MIPS4130 | |
14931 | && TARGET_VR4130_ALIGN) | |
a35de342 | 14932 | vr4130_align_insns (); |
0c433c31 RS |
14933 | if (mips_expand_ghost_gp_insns ()) |
14934 | /* The expansion could invalidate some of the VR4130 alignment | |
14935 | optimizations, but this should be an extremely rare case anyhow. */ | |
14936 | mips_reorg_process_insns (); | |
ab77a036 RS |
14937 | } |
14938 | \f | |
14939 | /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text | |
14940 | in order to avoid duplicating too much logic from elsewhere. */ | |
32041385 | 14941 | |
ab77a036 RS |
14942 | static void |
14943 | mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | |
14944 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
14945 | tree function) | |
14946 | { | |
0a2aaacc | 14947 | rtx this_rtx, temp1, temp2, insn, fnaddr; |
ab77a036 RS |
14948 | bool use_sibcall_p; |
14949 | ||
14950 | /* Pretend to be a post-reload pass while generating rtl. */ | |
14951 | reload_completed = 1; | |
14952 | ||
14953 | /* Mark the end of the (empty) prologue. */ | |
14954 | emit_note (NOTE_INSN_PROLOGUE_END); | |
14955 | ||
14956 | /* Determine if we can use a sibcall to call FUNCTION directly. */ | |
14957 | fnaddr = XEXP (DECL_RTL (function), 0); | |
14958 | use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL) | |
14959 | && const_call_insn_operand (fnaddr, Pmode)); | |
14960 | ||
14961 | /* Determine if we need to load FNADDR from the GOT. */ | |
08d0963a RS |
14962 | if (!use_sibcall_p |
14963 | && (mips_got_symbol_type_p | |
14964 | (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA)))) | |
14965 | { | |
14966 | /* Pick a global pointer. Use a call-clobbered register if | |
14967 | TARGET_CALL_SAVED_GP. */ | |
14968 | cfun->machine->global_pointer | |
14969 | = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM; | |
0c433c31 | 14970 | cfun->machine->must_initialize_gp_p = true; |
08d0963a | 14971 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); |
ab77a036 | 14972 | |
08d0963a RS |
14973 | /* Set up the global pointer for n32 or n64 abicalls. */ |
14974 | mips_emit_loadgp (); | |
14975 | } | |
ab77a036 RS |
14976 | |
14977 | /* We need two temporary registers in some cases. */ | |
14978 | temp1 = gen_rtx_REG (Pmode, 2); | |
14979 | temp2 = gen_rtx_REG (Pmode, 3); | |
14980 | ||
14981 | /* Find out which register contains the "this" pointer. */ | |
14982 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
0a2aaacc | 14983 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); |
ab77a036 | 14984 | else |
0a2aaacc | 14985 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); |
ab77a036 | 14986 | |
0a2aaacc | 14987 | /* Add DELTA to THIS_RTX. */ |
ab77a036 RS |
14988 | if (delta != 0) |
14989 | { | |
14990 | rtx offset = GEN_INT (delta); | |
14991 | if (!SMALL_OPERAND (delta)) | |
14992 | { | |
14993 | mips_emit_move (temp1, offset); | |
14994 | offset = temp1; | |
14995 | } | |
0a2aaacc | 14996 | emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); |
ab77a036 RS |
14997 | } |
14998 | ||
0a2aaacc | 14999 | /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ |
ab77a036 RS |
15000 | if (vcall_offset != 0) |
15001 | { | |
15002 | rtx addr; | |
15003 | ||
0a2aaacc KG |
15004 | /* Set TEMP1 to *THIS_RTX. */ |
15005 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); | |
ab77a036 | 15006 | |
0a2aaacc | 15007 | /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ |
ab77a036 RS |
15008 | addr = mips_add_offset (temp2, temp1, vcall_offset); |
15009 | ||
0a2aaacc | 15010 | /* Load the offset and add it to THIS_RTX. */ |
ab77a036 | 15011 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); |
0a2aaacc | 15012 | emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); |
ab77a036 RS |
15013 | } |
15014 | ||
15015 | /* Jump to the target function. Use a sibcall if direct jumps are | |
15016 | allowed, otherwise load the address into a register first. */ | |
15017 | if (use_sibcall_p) | |
15018 | { | |
15019 | insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); | |
15020 | SIBLING_CALL_P (insn) = 1; | |
15021 | } | |
15022 | else | |
15023 | { | |
65239d20 | 15024 | /* This is messy. GAS treats "la $25,foo" as part of a call |
ab77a036 RS |
15025 | sequence and may allow a global "foo" to be lazily bound. |
15026 | The general move patterns therefore reject this combination. | |
15027 | ||
15028 | In this context, lazy binding would actually be OK | |
15029 | for TARGET_CALL_CLOBBERED_GP, but it's still wrong for | |
15030 | TARGET_CALL_SAVED_GP; see mips_load_call_address. | |
15031 | We must therefore load the address via a temporary | |
15032 | register if mips_dangerous_for_la25_p. | |
15033 | ||
08d0963a RS |
15034 | If we jump to the temporary register rather than $25, |
15035 | the assembler can use the move insn to fill the jump's | |
15036 | delay slot. | |
15037 | ||
15038 | We can use the same technique for MIPS16 code, where $25 | |
15039 | is not a valid JR register. */ | |
ab77a036 | 15040 | if (TARGET_USE_PIC_FN_ADDR_REG |
08d0963a | 15041 | && !TARGET_MIPS16 |
ab77a036 RS |
15042 | && !mips_dangerous_for_la25_p (fnaddr)) |
15043 | temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
08d0963a | 15044 | mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr); |
ab77a036 RS |
15045 | |
15046 | if (TARGET_USE_PIC_FN_ADDR_REG | |
15047 | && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM) | |
15048 | mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1); | |
15049 | emit_jump_insn (gen_indirect_jump (temp1)); | |
15050 | } | |
15051 | ||
15052 | /* Run just enough of rest_of_compilation. This sequence was | |
15053 | "borrowed" from alpha.c. */ | |
15054 | insn = get_insns (); | |
15055 | insn_locators_alloc (); | |
15056 | split_all_insns_noflow (); | |
15057 | mips16_lay_out_constants (); | |
15058 | shorten_branches (insn); | |
15059 | final_start_function (insn, file, 1); | |
15060 | final (insn, file, 1); | |
15061 | final_end_function (); | |
15062 | ||
15063 | /* Clean up the vars set above. Note that final_end_function resets | |
15064 | the global pointer for us. */ | |
15065 | reload_completed = 0; | |
15066 | } | |
15067 | \f | |
65239d20 | 15068 | /* The last argument passed to mips_set_mips16_mode, or negative if the |
60730ade RS |
15069 | function hasn't been called yet. |
15070 | ||
15071 | There are two copies of this information. One is saved and restored | |
15072 | by the PCH process while the other is specific to this compiler | |
15073 | invocation. The information calculated by mips_set_mips16_mode | |
15074 | is invalid unless the two variables are the same. */ | |
15075 | static int was_mips16_p = -1; | |
15076 | static GTY(()) int was_mips16_pch_p = -1; | |
ab77a036 RS |
15077 | |
15078 | /* Set up the target-dependent global state so that it matches the | |
15079 | current function's ISA mode. */ | |
15080 | ||
15081 | static void | |
15082 | mips_set_mips16_mode (int mips16_p) | |
15083 | { | |
60730ade RS |
15084 | if (mips16_p == was_mips16_p |
15085 | && mips16_p == was_mips16_pch_p) | |
ab77a036 RS |
15086 | return; |
15087 | ||
15088 | /* Restore base settings of various flags. */ | |
15089 | target_flags = mips_base_target_flags; | |
ab77a036 RS |
15090 | flag_schedule_insns = mips_base_schedule_insns; |
15091 | flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition; | |
15092 | flag_move_loop_invariants = mips_base_move_loop_invariants; | |
15093 | align_loops = mips_base_align_loops; | |
15094 | align_jumps = mips_base_align_jumps; | |
15095 | align_functions = mips_base_align_functions; | |
15096 | ||
15097 | if (mips16_p) | |
15098 | { | |
65239d20 | 15099 | /* Switch to MIPS16 mode. */ |
ab77a036 RS |
15100 | target_flags |= MASK_MIPS16; |
15101 | ||
15102 | /* Don't run the scheduler before reload, since it tends to | |
15103 | increase register pressure. */ | |
15104 | flag_schedule_insns = 0; | |
15105 | ||
65239d20 | 15106 | /* Don't do hot/cold partitioning. mips16_lay_out_constants expects |
ab77a036 RS |
15107 | the whole function to be in a single section. */ |
15108 | flag_reorder_blocks_and_partition = 0; | |
15109 | ||
15110 | /* Don't move loop invariants, because it tends to increase | |
15111 | register pressure. It also introduces an extra move in cases | |
15112 | where the constant is the first operand in a two-operand binary | |
15113 | instruction, or when it forms a register argument to a functon | |
15114 | call. */ | |
15115 | flag_move_loop_invariants = 0; | |
15116 | ||
08d0963a | 15117 | target_flags |= MASK_EXPLICIT_RELOCS; |
ab77a036 | 15118 | |
65239d20 RS |
15119 | /* Experiments suggest we get the best overall section-anchor |
15120 | results from using the range of an unextended LW or SW. Code | |
15121 | that makes heavy use of byte or short accesses can do better | |
15122 | with ranges of 0...31 and 0...63 respectively, but most code is | |
15123 | sensitive to the range of LW and SW instead. */ | |
ab77a036 RS |
15124 | targetm.min_anchor_offset = 0; |
15125 | targetm.max_anchor_offset = 127; | |
15126 | ||
2c5bfdf7 AN |
15127 | targetm.const_anchor = 0; |
15128 | ||
b53da244 AN |
15129 | /* MIPS16 has no BAL instruction. */ |
15130 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
15131 | ||
08d0963a RS |
15132 | if (flag_pic && !TARGET_OLDABI) |
15133 | sorry ("MIPS16 PIC for ABIs other than o32 and o64"); | |
15134 | ||
15135 | if (TARGET_XGOT) | |
15136 | sorry ("MIPS16 -mxgot code"); | |
d375fd5e RS |
15137 | |
15138 | if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI) | |
15139 | sorry ("hard-float MIPS16 code for ABIs other than o32 and o64"); | |
ab77a036 RS |
15140 | } |
15141 | else | |
15142 | { | |
65239d20 | 15143 | /* Switch to normal (non-MIPS16) mode. */ |
ab77a036 RS |
15144 | target_flags &= ~MASK_MIPS16; |
15145 | ||
ab77a036 RS |
15146 | /* Provide default values for align_* for 64-bit targets. */ |
15147 | if (TARGET_64BIT) | |
15148 | { | |
15149 | if (align_loops == 0) | |
15150 | align_loops = 8; | |
15151 | if (align_jumps == 0) | |
15152 | align_jumps = 8; | |
15153 | if (align_functions == 0) | |
15154 | align_functions = 8; | |
15155 | } | |
1823bf53 | 15156 | |
ab77a036 RS |
15157 | targetm.min_anchor_offset = -32768; |
15158 | targetm.max_anchor_offset = 32767; | |
2c5bfdf7 AN |
15159 | |
15160 | targetm.const_anchor = 0x8000; | |
ab77a036 | 15161 | } |
1823bf53 | 15162 | |
65239d20 | 15163 | /* (Re)initialize MIPS target internals for new ISA. */ |
ab77a036 | 15164 | mips_init_relocs (); |
1823bf53 | 15165 | |
5aa62249 RS |
15166 | if (mips16_p) |
15167 | { | |
15168 | if (!mips16_globals) | |
15169 | mips16_globals = save_target_globals (); | |
15170 | else | |
15171 | restore_target_globals (mips16_globals); | |
15172 | } | |
15173 | else | |
15174 | restore_target_globals (&default_target_globals); | |
32041385 | 15175 | |
65239d20 | 15176 | was_mips16_p = mips16_p; |
60730ade | 15177 | was_mips16_pch_p = mips16_p; |
ab77a036 | 15178 | } |
1823bf53 | 15179 | |
ab77a036 RS |
15180 | /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current |
15181 | function should use the MIPS16 ISA and switch modes accordingly. */ | |
15182 | ||
15183 | static void | |
15184 | mips_set_current_function (tree fndecl) | |
1823bf53 | 15185 | { |
ab77a036 RS |
15186 | mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl)); |
15187 | } | |
15188 | \f | |
15189 | /* Allocate a chunk of memory for per-function machine-dependent data. */ | |
65239d20 | 15190 | |
ab77a036 RS |
15191 | static struct machine_function * |
15192 | mips_init_machine_status (void) | |
15193 | { | |
a9429e29 | 15194 | return ggc_alloc_cleared_machine_function (); |
ab77a036 | 15195 | } |
06a4ab70 | 15196 | |
ab77a036 RS |
15197 | /* Return the processor associated with the given ISA level, or null |
15198 | if the ISA isn't valid. */ | |
ff55fb9c | 15199 | |
ab77a036 RS |
15200 | static const struct mips_cpu_info * |
15201 | mips_cpu_info_from_isa (int isa) | |
ff55fb9c | 15202 | { |
ab77a036 | 15203 | unsigned int i; |
ff55fb9c | 15204 | |
ab77a036 RS |
15205 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
15206 | if (mips_cpu_info_table[i].isa == isa) | |
15207 | return mips_cpu_info_table + i; | |
ff55fb9c | 15208 | |
65239d20 | 15209 | return NULL; |
ff55fb9c RS |
15210 | } |
15211 | ||
d371df6f JM |
15212 | /* Return a mips_cpu_info entry determined by an option valued |
15213 | OPT. */ | |
ff55fb9c | 15214 | |
d371df6f JM |
15215 | static const struct mips_cpu_info * |
15216 | mips_cpu_info_from_opt (int opt) | |
ab77a036 | 15217 | { |
d371df6f JM |
15218 | switch (opt) |
15219 | { | |
15220 | case MIPS_ARCH_OPTION_FROM_ABI: | |
15221 | /* 'from-abi' selects the most compatible architecture for the | |
15222 | given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit | |
15223 | ABIs. For the EABIs, we have to decide whether we're using | |
15224 | the 32-bit or 64-bit version. */ | |
15225 | return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1 | |
15226 | : ABI_NEEDS_64BIT_REGS ? 3 | |
15227 | : (TARGET_64BIT ? 3 : 1)); | |
ab77a036 | 15228 | |
d371df6f JM |
15229 | case MIPS_ARCH_OPTION_NATIVE: |
15230 | gcc_unreachable (); | |
ab77a036 | 15231 | |
d371df6f JM |
15232 | default: |
15233 | return &mips_cpu_info_table[opt]; | |
15234 | } | |
ff55fb9c RS |
15235 | } |
15236 | ||
d371df6f JM |
15237 | /* Return a default mips_cpu_info entry, given that no -march= option |
15238 | was explicitly specified. */ | |
ab77a036 RS |
15239 | |
15240 | static const struct mips_cpu_info * | |
d371df6f | 15241 | mips_default_arch (void) |
06a4ab70 | 15242 | { |
872dab53 | 15243 | #if defined (MIPS_CPU_STRING_DEFAULT) |
ab77a036 | 15244 | unsigned int i; |
ab77a036 | 15245 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
d371df6f | 15246 | if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0) |
ab77a036 | 15247 | return mips_cpu_info_table + i; |
d371df6f | 15248 | gcc_unreachable (); |
872dab53 RS |
15249 | #elif defined (MIPS_ISA_DEFAULT) |
15250 | return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT); | |
d371df6f JM |
15251 | #else |
15252 | /* 'from-abi' makes a good default: you get whatever the ABI | |
15253 | requires. */ | |
15254 | return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI); | |
15255 | #endif | |
ab77a036 RS |
15256 | } |
15257 | ||
ab77a036 RS |
15258 | /* Set up globals to generate code for the ISA or processor |
15259 | described by INFO. */ | |
15260 | ||
15261 | static void | |
15262 | mips_set_architecture (const struct mips_cpu_info *info) | |
15263 | { | |
15264 | if (info != 0) | |
f9e4a411 | 15265 | { |
ab77a036 RS |
15266 | mips_arch_info = info; |
15267 | mips_arch = info->cpu; | |
15268 | mips_isa = info->isa; | |
f9e4a411 | 15269 | } |
ab77a036 | 15270 | } |
f9e4a411 | 15271 | |
ab77a036 RS |
15272 | /* Likewise for tuning. */ |
15273 | ||
15274 | static void | |
15275 | mips_set_tune (const struct mips_cpu_info *info) | |
15276 | { | |
15277 | if (info != 0) | |
1823bf53 | 15278 | { |
ab77a036 RS |
15279 | mips_tune_info = info; |
15280 | mips_tune = info->cpu; | |
1823bf53 | 15281 | } |
ab77a036 | 15282 | } |
ff55fb9c | 15283 | |
525c561d | 15284 | /* Implement TARGET_OPTION_OVERRIDE. */ |
06a4ab70 | 15285 | |
525c561d AS |
15286 | static void |
15287 | mips_option_override (void) | |
06a4ab70 | 15288 | { |
65239d20 | 15289 | int i, start, regno, mode; |
06a4ab70 | 15290 | |
d371df6f JM |
15291 | if (global_options_set.x_mips_isa_option) |
15292 | mips_isa_option_info = &mips_cpu_info_table[mips_isa_option]; | |
15293 | ||
60730ade RS |
15294 | /* Process flags as though we were generating non-MIPS16 code. */ |
15295 | mips_base_mips16 = TARGET_MIPS16; | |
15296 | target_flags &= ~MASK_MIPS16; | |
15297 | ||
ab77a036 RS |
15298 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
15299 | SUBTARGET_OVERRIDE_OPTIONS; | |
15300 | #endif | |
06a4ab70 | 15301 | |
9f946bc1 RS |
15302 | /* -mno-float overrides -mhard-float and -msoft-float. */ |
15303 | if (TARGET_NO_FLOAT) | |
15304 | { | |
15305 | target_flags |= MASK_SOFT_FLOAT_ABI; | |
15306 | target_flags_explicit |= MASK_SOFT_FLOAT_ABI; | |
15307 | } | |
15308 | ||
ac9b0eea RS |
15309 | if (TARGET_FLIP_MIPS16) |
15310 | TARGET_INTERLINK_MIPS16 = 1; | |
15311 | ||
65239d20 | 15312 | /* Set the small data limit. */ |
fa37ed29 | 15313 | mips_small_data_threshold = (global_options_set.x_g_switch_value |
65239d20 RS |
15314 | ? g_switch_value |
15315 | : MIPS_DEFAULT_GVALUE); | |
8f2e3902 | 15316 | |
ab77a036 RS |
15317 | /* The following code determines the architecture and register size. |
15318 | Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()). | |
15319 | The GAS and GCC code should be kept in sync as much as possible. */ | |
06a4ab70 | 15320 | |
d371df6f JM |
15321 | if (global_options_set.x_mips_arch_option) |
15322 | mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option)); | |
06a4ab70 | 15323 | |
65239d20 | 15324 | if (mips_isa_option_info != 0) |
ab77a036 RS |
15325 | { |
15326 | if (mips_arch_info == 0) | |
65239d20 RS |
15327 | mips_set_architecture (mips_isa_option_info); |
15328 | else if (mips_arch_info->isa != mips_isa_option_info->isa) | |
15329 | error ("%<-%s%> conflicts with the other architecture options, " | |
ab77a036 | 15330 | "which specify a %s processor", |
65239d20 | 15331 | mips_isa_option_info->name, |
ab77a036 RS |
15332 | mips_cpu_info_from_isa (mips_arch_info->isa)->name); |
15333 | } | |
06a4ab70 | 15334 | |
ab77a036 | 15335 | if (mips_arch_info == 0) |
d371df6f | 15336 | mips_set_architecture (mips_default_arch ()); |
06a4ab70 | 15337 | |
ab77a036 | 15338 | if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS) |
65239d20 | 15339 | error ("%<-march=%s%> is not compatible with the selected ABI", |
ab77a036 | 15340 | mips_arch_info->name); |
06a4ab70 | 15341 | |
ab77a036 | 15342 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
d371df6f JM |
15343 | if (global_options_set.x_mips_tune_option) |
15344 | mips_set_tune (mips_cpu_info_from_opt (mips_tune_option)); | |
118ea793 | 15345 | |
ab77a036 RS |
15346 | if (mips_tune_info == 0) |
15347 | mips_set_tune (mips_arch_info); | |
118ea793 | 15348 | |
ab77a036 RS |
15349 | if ((target_flags_explicit & MASK_64BIT) != 0) |
15350 | { | |
15351 | /* The user specified the size of the integer registers. Make sure | |
15352 | it agrees with the ABI and ISA. */ | |
15353 | if (TARGET_64BIT && !ISA_HAS_64BIT_REGS) | |
65239d20 | 15354 | error ("%<-mgp64%> used with a 32-bit processor"); |
ab77a036 | 15355 | else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS) |
65239d20 | 15356 | error ("%<-mgp32%> used with a 64-bit ABI"); |
ab77a036 | 15357 | else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS) |
65239d20 | 15358 | error ("%<-mgp64%> used with a 32-bit ABI"); |
ab77a036 RS |
15359 | } |
15360 | else | |
15361 | { | |
15362 | /* Infer the integer register size from the ABI and processor. | |
15363 | Restrict ourselves to 32-bit registers if that's all the | |
15364 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15365 | if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS) | |
15366 | target_flags &= ~MASK_64BIT; | |
15367 | else | |
15368 | target_flags |= MASK_64BIT; | |
118ea793 CF |
15369 | } |
15370 | ||
ab77a036 | 15371 | if ((target_flags_explicit & MASK_FLOAT64) != 0) |
118ea793 | 15372 | { |
65239d20 | 15373 | if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64) |
ab77a036 | 15374 | error ("unsupported combination: %s", "-mfp64 -msingle-float"); |
65239d20 RS |
15375 | else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64) |
15376 | error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float"); | |
15377 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
15378 | { | |
15379 | if (!ISA_HAS_MXHC1) | |
15380 | error ("%<-mgp32%> and %<-mfp64%> can only be combined if" | |
15381 | " the target supports the mfhc1 and mthc1 instructions"); | |
15382 | else if (mips_abi != ABI_32) | |
15383 | error ("%<-mgp32%> and %<-mfp64%> can only be combined when using" | |
15384 | " the o32 ABI"); | |
15385 | } | |
ab77a036 RS |
15386 | } |
15387 | else | |
15388 | { | |
15389 | /* -msingle-float selects 32-bit float registers. Otherwise the | |
15390 | float registers should be the same size as the integer ones. */ | |
15391 | if (TARGET_64BIT && TARGET_DOUBLE_FLOAT) | |
15392 | target_flags |= MASK_FLOAT64; | |
15393 | else | |
15394 | target_flags &= ~MASK_FLOAT64; | |
15395 | } | |
118ea793 | 15396 | |
ab77a036 | 15397 | /* End of code shared with GAS. */ |
118ea793 | 15398 | |
65239d20 | 15399 | /* If no -mlong* option was given, infer it from the other options. */ |
ab77a036 RS |
15400 | if ((target_flags_explicit & MASK_LONG64) == 0) |
15401 | { | |
15402 | if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64) | |
15403 | target_flags |= MASK_LONG64; | |
15404 | else | |
15405 | target_flags &= ~MASK_LONG64; | |
15406 | } | |
118ea793 | 15407 | |
ab77a036 RS |
15408 | if (!TARGET_OLDABI) |
15409 | flag_pcc_struct_return = 0; | |
118ea793 | 15410 | |
65239d20 RS |
15411 | /* Decide which rtx_costs structure to use. */ |
15412 | if (optimize_size) | |
15413 | mips_cost = &mips_rtx_cost_optimize_size; | |
15414 | else | |
15415 | mips_cost = &mips_rtx_cost_data[mips_tune]; | |
15416 | ||
15417 | /* If the user hasn't specified a branch cost, use the processor's | |
15418 | default. */ | |
15419 | if (mips_branch_cost == 0) | |
15420 | mips_branch_cost = mips_cost->branch_cost; | |
15421 | ||
15422 | /* If neither -mbranch-likely nor -mno-branch-likely was given | |
15423 | on the command line, set MASK_BRANCHLIKELY based on the target | |
15424 | architecture and tuning flags. Annulled delay slots are a | |
15425 | size win, so we only consider the processor-specific tuning | |
15426 | for !optimize_size. */ | |
ab77a036 RS |
15427 | if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0) |
15428 | { | |
ab77a036 RS |
15429 | if (ISA_HAS_BRANCHLIKELY |
15430 | && (optimize_size | |
15431 | || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0)) | |
15432 | target_flags |= MASK_BRANCHLIKELY; | |
15433 | else | |
15434 | target_flags &= ~MASK_BRANCHLIKELY; | |
15435 | } | |
15436 | else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) | |
15437 | warning (0, "the %qs architecture does not support branch-likely" | |
15438 | " instructions", mips_arch_info->name); | |
118ea793 | 15439 | |
ab77a036 RS |
15440 | /* The effect of -mabicalls isn't defined for the EABI. */ |
15441 | if (mips_abi == ABI_EABI && TARGET_ABICALLS) | |
15442 | { | |
15443 | error ("unsupported combination: %s", "-mabicalls -mabi=eabi"); | |
15444 | target_flags &= ~MASK_ABICALLS; | |
15445 | } | |
118ea793 | 15446 | |
e21d5757 | 15447 | if (TARGET_ABICALLS_PIC2) |
ab77a036 RS |
15448 | /* We need to set flag_pic for executables as well as DSOs |
15449 | because we may reference symbols that are not defined in | |
15450 | the final executable. (MIPS does not use things like | |
15451 | copy relocs, for example.) | |
118ea793 | 15452 | |
e21d5757 DJ |
15453 | There is a body of code that uses __PIC__ to distinguish |
15454 | between -mabicalls and -mno-abicalls code. The non-__PIC__ | |
15455 | variant is usually appropriate for TARGET_ABICALLS_PIC0, as | |
15456 | long as any indirect jumps use $25. */ | |
ab77a036 | 15457 | flag_pic = 1; |
118ea793 | 15458 | |
ab77a036 RS |
15459 | /* -mvr4130-align is a "speed over size" optimization: it usually produces |
15460 | faster code, but at the expense of more nops. Enable it at -O3 and | |
15461 | above. */ | |
15462 | if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) | |
15463 | target_flags |= MASK_VR4130_ALIGN; | |
118ea793 | 15464 | |
ab77a036 RS |
15465 | /* Prefer a call to memcpy over inline code when optimizing for size, |
15466 | though see MOVE_RATIO in mips.h. */ | |
15467 | if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) | |
15468 | target_flags |= MASK_MEMCPY; | |
118ea793 | 15469 | |
ab77a036 RS |
15470 | /* If we have a nonzero small-data limit, check that the -mgpopt |
15471 | setting is consistent with the other target flags. */ | |
65239d20 | 15472 | if (mips_small_data_threshold > 0) |
ab77a036 RS |
15473 | { |
15474 | if (!TARGET_GPOPT) | |
15475 | { | |
60730ade | 15476 | if (!TARGET_EXPLICIT_RELOCS) |
ab77a036 | 15477 | error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>"); |
118ea793 | 15478 | |
ab77a036 RS |
15479 | TARGET_LOCAL_SDATA = false; |
15480 | TARGET_EXTERN_SDATA = false; | |
15481 | } | |
15482 | else | |
15483 | { | |
15484 | if (TARGET_VXWORKS_RTP) | |
15485 | warning (0, "cannot use small-data accesses for %qs", "-mrtp"); | |
118ea793 | 15486 | |
ab77a036 RS |
15487 | if (TARGET_ABICALLS) |
15488 | warning (0, "cannot use small-data accesses for %qs", | |
15489 | "-mabicalls"); | |
15490 | } | |
15491 | } | |
118ea793 | 15492 | |
ab77a036 RS |
15493 | #ifdef MIPS_TFMODE_FORMAT |
15494 | REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT; | |
15495 | #endif | |
118ea793 | 15496 | |
ab77a036 RS |
15497 | /* Make sure that the user didn't turn off paired single support when |
15498 | MIPS-3D support is requested. */ | |
65239d20 RS |
15499 | if (TARGET_MIPS3D |
15500 | && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT) | |
ab77a036 | 15501 | && !TARGET_PAIRED_SINGLE_FLOAT) |
65239d20 | 15502 | error ("%<-mips3d%> requires %<-mpaired-single%>"); |
118ea793 | 15503 | |
ab77a036 RS |
15504 | /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */ |
15505 | if (TARGET_MIPS3D) | |
15506 | target_flags |= MASK_PAIRED_SINGLE_FLOAT; | |
118ea793 | 15507 | |
ab77a036 RS |
15508 | /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 |
15509 | and TARGET_HARD_FLOAT_ABI are both true. */ | |
15510 | if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) | |
65239d20 RS |
15511 | error ("%qs must be used with %qs", |
15512 | TARGET_MIPS3D ? "-mips3d" : "-mpaired-single", | |
15513 | TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float"); | |
118ea793 | 15514 | |
ab77a036 RS |
15515 | /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is |
15516 | enabled. */ | |
e5a2b69d RS |
15517 | if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE) |
15518 | warning (0, "the %qs architecture does not support paired-single" | |
15519 | " instructions", mips_arch_info->name); | |
118ea793 | 15520 | |
4d210b07 RS |
15521 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE |
15522 | && !TARGET_CACHE_BUILTIN) | |
15523 | { | |
15524 | error ("%qs requires a target that provides the %qs instruction", | |
15525 | "-mr10k-cache-barrier", "cache"); | |
15526 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; | |
15527 | } | |
15528 | ||
ab77a036 RS |
15529 | /* If TARGET_DSPR2, enable MASK_DSP. */ |
15530 | if (TARGET_DSPR2) | |
15531 | target_flags |= MASK_DSP; | |
118ea793 | 15532 | |
082d2ebb RS |
15533 | /* .eh_frame addresses should be the same width as a C pointer. |
15534 | Most MIPS ABIs support only one pointer size, so the assembler | |
15535 | will usually know exactly how big an .eh_frame address is. | |
15536 | ||
15537 | Unfortunately, this is not true of the 64-bit EABI. The ABI was | |
15538 | originally defined to use 64-bit pointers (i.e. it is LP64), and | |
15539 | this is still the default mode. However, we also support an n32-like | |
15540 | ILP32 mode, which is selected by -mlong32. The problem is that the | |
15541 | assembler has traditionally not had an -mlong option, so it has | |
15542 | traditionally not known whether we're using the ILP32 or LP64 form. | |
15543 | ||
15544 | As it happens, gas versions up to and including 2.19 use _32-bit_ | |
15545 | addresses for EABI64 .cfi_* directives. This is wrong for the | |
15546 | default LP64 mode, so we can't use the directives by default. | |
15547 | Moreover, since gas's current behavior is at odds with gcc's | |
15548 | default behavior, it seems unwise to rely on future versions | |
15549 | of gas behaving the same way. We therefore avoid using .cfi | |
15550 | directives for -mlong32 as well. */ | |
15551 | if (mips_abi == ABI_EABI && TARGET_64BIT) | |
15552 | flag_dwarf2_cfi_asm = 0; | |
15553 | ||
49576e25 RS |
15554 | /* .cfi_* directives generate a read-only section, so fall back on |
15555 | manual .eh_frame creation if we need the section to be writable. */ | |
15556 | if (TARGET_WRITABLE_EH_FRAME) | |
15557 | flag_dwarf2_cfi_asm = 0; | |
15558 | ||
07045266 | 15559 | mips_init_print_operand_punct (); |
118ea793 | 15560 | |
ab77a036 RS |
15561 | /* Set up array to map GCC register number to debug register number. |
15562 | Ignore the special purpose register numbers. */ | |
118ea793 | 15563 | |
ab77a036 RS |
15564 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
15565 | { | |
15566 | mips_dbx_regno[i] = INVALID_REGNUM; | |
15567 | if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i)) | |
15568 | mips_dwarf_regno[i] = i; | |
15569 | else | |
15570 | mips_dwarf_regno[i] = INVALID_REGNUM; | |
15571 | } | |
118ea793 | 15572 | |
ab77a036 RS |
15573 | start = GP_DBX_FIRST - GP_REG_FIRST; |
15574 | for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) | |
15575 | mips_dbx_regno[i] = i + start; | |
118ea793 | 15576 | |
ab77a036 RS |
15577 | start = FP_DBX_FIRST - FP_REG_FIRST; |
15578 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
15579 | mips_dbx_regno[i] = i + start; | |
118ea793 | 15580 | |
65239d20 | 15581 | /* Accumulator debug registers use big-endian ordering. */ |
ab77a036 RS |
15582 | mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0; |
15583 | mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1; | |
15584 | mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0; | |
15585 | mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1; | |
15586 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
15587 | { | |
15588 | mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i; | |
15589 | mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1; | |
15590 | } | |
118ea793 | 15591 | |
5f5fe6d9 RS |
15592 | /* Set up mips_hard_regno_mode_ok. */ |
15593 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
15594 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
bbbbb16a ILT |
15595 | mips_hard_regno_mode_ok[mode][regno] |
15596 | = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode); | |
06a4ab70 | 15597 | |
ab77a036 RS |
15598 | /* Function to allocate machine-dependent function status. */ |
15599 | init_machine_status = &mips_init_machine_status; | |
4ca1f68f | 15600 | |
ab77a036 RS |
15601 | /* Default to working around R4000 errata only if the processor |
15602 | was selected explicitly. */ | |
15603 | if ((target_flags_explicit & MASK_FIX_R4000) == 0 | |
d371df6f | 15604 | && strcmp (mips_arch_info->name, "r4000") == 0) |
ab77a036 | 15605 | target_flags |= MASK_FIX_R4000; |
4ca1f68f | 15606 | |
ab77a036 RS |
15607 | /* Default to working around R4400 errata only if the processor |
15608 | was selected explicitly. */ | |
15609 | if ((target_flags_explicit & MASK_FIX_R4400) == 0 | |
d371df6f | 15610 | && strcmp (mips_arch_info->name, "r4400") == 0) |
ab77a036 | 15611 | target_flags |= MASK_FIX_R4400; |
4ca1f68f | 15612 | |
ee9a72e5 JK |
15613 | /* Default to working around R10000 errata only if the processor |
15614 | was selected explicitly. */ | |
15615 | if ((target_flags_explicit & MASK_FIX_R10000) == 0 | |
d371df6f | 15616 | && strcmp (mips_arch_info->name, "r10000") == 0) |
ee9a72e5 JK |
15617 | target_flags |= MASK_FIX_R10000; |
15618 | ||
15619 | /* Make sure that branch-likely instructions available when using | |
15620 | -mfix-r10000. The instructions are not available if either: | |
15621 | ||
15622 | 1. -mno-branch-likely was passed. | |
15623 | 2. The selected ISA does not support branch-likely and | |
15624 | the command line does not include -mbranch-likely. */ | |
15625 | if (TARGET_FIX_R10000 | |
15626 | && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0 | |
15627 | ? !ISA_HAS_BRANCHLIKELY | |
15628 | : !TARGET_BRANCHLIKELY)) | |
15629 | sorry ("%qs requires branch-likely instructions", "-mfix-r10000"); | |
15630 | ||
b96c5923 DD |
15631 | if (TARGET_SYNCI && !ISA_HAS_SYNCI) |
15632 | { | |
15633 | warning (0, "the %qs architecture does not support the synci " | |
15634 | "instruction", mips_arch_info->name); | |
15635 | target_flags &= ~MASK_SYNCI; | |
15636 | } | |
15637 | ||
b53da244 AN |
15638 | /* Only optimize PIC indirect calls if they are actually required. */ |
15639 | if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS) | |
15640 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
15641 | ||
ab77a036 | 15642 | /* Save base state of options. */ |
ab77a036 | 15643 | mips_base_target_flags = target_flags; |
ab77a036 RS |
15644 | mips_base_schedule_insns = flag_schedule_insns; |
15645 | mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition; | |
15646 | mips_base_move_loop_invariants = flag_move_loop_invariants; | |
15647 | mips_base_align_loops = align_loops; | |
15648 | mips_base_align_jumps = align_jumps; | |
15649 | mips_base_align_functions = align_functions; | |
118ea793 | 15650 | |
60730ade RS |
15651 | /* Now select the ISA mode. |
15652 | ||
15653 | Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to | |
15654 | MIPS16 mode afterwards if need be. */ | |
15655 | mips_set_mips16_mode (false); | |
ab77a036 | 15656 | } |
4ca1f68f | 15657 | |
ab77a036 RS |
15658 | /* Swap the register information for registers I and I + 1, which |
15659 | currently have the wrong endianness. Note that the registers' | |
15660 | fixedness and call-clobberedness might have been set on the | |
15661 | command line. */ | |
4ca1f68f | 15662 | |
ab77a036 RS |
15663 | static void |
15664 | mips_swap_registers (unsigned int i) | |
15665 | { | |
15666 | int tmpi; | |
15667 | const char *tmps; | |
4ca1f68f | 15668 | |
ab77a036 RS |
15669 | #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi) |
15670 | #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps) | |
4ca1f68f | 15671 | |
ab77a036 RS |
15672 | SWAP_INT (fixed_regs[i], fixed_regs[i + 1]); |
15673 | SWAP_INT (call_used_regs[i], call_used_regs[i + 1]); | |
15674 | SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]); | |
15675 | SWAP_STRING (reg_names[i], reg_names[i + 1]); | |
15676 | ||
15677 | #undef SWAP_STRING | |
15678 | #undef SWAP_INT | |
06a4ab70 CF |
15679 | } |
15680 | ||
5efd84c5 | 15681 | /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ |
06a4ab70 | 15682 | |
5efd84c5 | 15683 | static void |
ab77a036 | 15684 | mips_conditional_register_usage (void) |
06a4ab70 | 15685 | { |
1e27273f CM |
15686 | |
15687 | if (ISA_HAS_DSP) | |
15688 | { | |
15689 | /* These DSP control register fields are global. */ | |
15690 | global_regs[CCDSP_PO_REGNUM] = 1; | |
15691 | global_regs[CCDSP_SC_REGNUM] = 1; | |
15692 | } | |
15693 | else | |
ab77a036 RS |
15694 | { |
15695 | int regno; | |
06a4ab70 | 15696 | |
ab77a036 RS |
15697 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) |
15698 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
15699 | } | |
15700 | if (!TARGET_HARD_FLOAT) | |
15701 | { | |
15702 | int regno; | |
06a4ab70 | 15703 | |
ab77a036 RS |
15704 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) |
15705 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
15706 | for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) | |
15707 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
15708 | } | |
15709 | else if (! ISA_HAS_8CC) | |
ff55fb9c | 15710 | { |
ab77a036 RS |
15711 | int regno; |
15712 | ||
65239d20 RS |
15713 | /* We only have a single condition-code register. We implement |
15714 | this by fixing all the condition-code registers and generating | |
15715 | RTL that refers directly to ST_REG_FIRST. */ | |
ab77a036 RS |
15716 | for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) |
15717 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
ff55fb9c | 15718 | } |
65239d20 | 15719 | /* In MIPS16 mode, we permit the $t temporary registers to be used |
ab77a036 | 15720 | for reload. We prohibit the unused $s registers, since they |
65239d20 | 15721 | are call-saved, and saving them via a MIPS16 register would |
ab77a036 RS |
15722 | probably waste more time than just reloading the value. */ |
15723 | if (TARGET_MIPS16) | |
ff55fb9c | 15724 | { |
ab77a036 RS |
15725 | fixed_regs[18] = call_used_regs[18] = 1; |
15726 | fixed_regs[19] = call_used_regs[19] = 1; | |
15727 | fixed_regs[20] = call_used_regs[20] = 1; | |
15728 | fixed_regs[21] = call_used_regs[21] = 1; | |
15729 | fixed_regs[22] = call_used_regs[22] = 1; | |
15730 | fixed_regs[23] = call_used_regs[23] = 1; | |
15731 | fixed_regs[26] = call_used_regs[26] = 1; | |
15732 | fixed_regs[27] = call_used_regs[27] = 1; | |
15733 | fixed_regs[30] = call_used_regs[30] = 1; | |
15734 | } | |
65239d20 | 15735 | /* $f20-$f23 are call-clobbered for n64. */ |
ab77a036 RS |
15736 | if (mips_abi == ABI_64) |
15737 | { | |
15738 | int regno; | |
15739 | for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) | |
15740 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
15741 | } | |
65239d20 RS |
15742 | /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered |
15743 | for n32. */ | |
ab77a036 RS |
15744 | if (mips_abi == ABI_N32) |
15745 | { | |
15746 | int regno; | |
15747 | for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) | |
15748 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
15749 | } | |
15750 | /* Make sure that double-register accumulator values are correctly | |
15751 | ordered for the current endianness. */ | |
15752 | if (TARGET_LITTLE_ENDIAN) | |
15753 | { | |
65239d20 RS |
15754 | unsigned int regno; |
15755 | ||
ab77a036 RS |
15756 | mips_swap_registers (MD_REG_FIRST); |
15757 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2) | |
15758 | mips_swap_registers (regno); | |
ff55fb9c | 15759 | } |
ff55fb9c | 15760 | } |
06a4ab70 | 15761 | |
93581857 MS |
15762 | /* Initialize vector TARGET to VALS. */ |
15763 | ||
15764 | void | |
15765 | mips_expand_vector_init (rtx target, rtx vals) | |
15766 | { | |
15767 | enum machine_mode mode; | |
15768 | enum machine_mode inner; | |
15769 | unsigned int i, n_elts; | |
15770 | rtx mem; | |
15771 | ||
15772 | mode = GET_MODE (target); | |
15773 | inner = GET_MODE_INNER (mode); | |
15774 | n_elts = GET_MODE_NUNITS (mode); | |
15775 | ||
15776 | gcc_assert (VECTOR_MODE_P (mode)); | |
15777 | ||
15778 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
15779 | for (i = 0; i < n_elts; i++) | |
15780 | emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)), | |
15781 | XVECEXP (vals, 0, i)); | |
15782 | ||
15783 | emit_move_insn (target, mem); | |
15784 | } | |
15785 | ||
65239d20 RS |
15786 | /* When generating MIPS16 code, we want to allocate $24 (T_REG) before |
15787 | other registers for instructions for which it is possible. This | |
15788 | encourages the compiler to use CMP in cases where an XOR would | |
15789 | require some register shuffling. */ | |
a8c1d5f8 | 15790 | |
ab77a036 RS |
15791 | void |
15792 | mips_order_regs_for_local_alloc (void) | |
a8c1d5f8 | 15793 | { |
65239d20 | 15794 | int i; |
a8c1d5f8 | 15795 | |
ab77a036 RS |
15796 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
15797 | reg_alloc_order[i] = i; | |
a8c1d5f8 | 15798 | |
ab77a036 RS |
15799 | if (TARGET_MIPS16) |
15800 | { | |
15801 | /* It really doesn't matter where we put register 0, since it is | |
15802 | a fixed register anyhow. */ | |
15803 | reg_alloc_order[0] = 24; | |
15804 | reg_alloc_order[24] = 0; | |
15805 | } | |
a8c1d5f8 | 15806 | } |
e19da24c | 15807 | |
0c433c31 RS |
15808 | /* Implement EH_USES. */ |
15809 | ||
15810 | bool | |
15811 | mips_eh_uses (unsigned int regno) | |
15812 | { | |
15813 | if (reload_completed && !TARGET_ABSOLUTE_JUMPS) | |
15814 | { | |
15815 | /* We need to force certain registers to be live in order to handle | |
15816 | PIC long branches correctly. See mips_must_initialize_gp_p for | |
15817 | details. */ | |
15818 | if (mips_cfun_has_cprestore_slot_p ()) | |
15819 | { | |
15820 | if (regno == CPRESTORE_SLOT_REGNUM) | |
15821 | return true; | |
15822 | } | |
15823 | else | |
15824 | { | |
15825 | if (cfun->machine->global_pointer == regno) | |
15826 | return true; | |
15827 | } | |
15828 | } | |
15829 | ||
15830 | return false; | |
15831 | } | |
15832 | ||
e19da24c CF |
15833 | /* Implement EPILOGUE_USES. */ |
15834 | ||
15835 | bool | |
15836 | mips_epilogue_uses (unsigned int regno) | |
15837 | { | |
15838 | /* Say that the epilogue uses the return address register. Note that | |
15839 | in the case of sibcalls, the values "used by the epilogue" are | |
15840 | considered live at the start of the called function. */ | |
293593b1 | 15841 | if (regno == RETURN_ADDR_REGNUM) |
e19da24c CF |
15842 | return true; |
15843 | ||
15844 | /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM. | |
15845 | See the comment above load_call<mode> for details. */ | |
15846 | if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM) | |
15847 | return true; | |
15848 | ||
15849 | /* An interrupt handler must preserve some registers that are | |
15850 | ordinarily call-clobbered. */ | |
15851 | if (cfun->machine->interrupt_handler_p | |
15852 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
15853 | return true; | |
15854 | ||
15855 | return false; | |
15856 | } | |
1afc5373 CF |
15857 | |
15858 | /* A for_each_rtx callback. Stop the search if *X is an AT register. */ | |
15859 | ||
15860 | static int | |
15861 | mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED) | |
15862 | { | |
47ac44d6 | 15863 | return REG_P (*x) && REGNO (*x) == AT_REGNUM; |
1afc5373 CF |
15864 | } |
15865 | ||
cf5fb4b0 RS |
15866 | /* Return true if INSN needs to be wrapped in ".set noat". |
15867 | INSN has NOPERANDS operands, stored in OPVEC. */ | |
1afc5373 | 15868 | |
cf5fb4b0 RS |
15869 | static bool |
15870 | mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands) | |
1afc5373 CF |
15871 | { |
15872 | int i; | |
15873 | ||
1afc5373 CF |
15874 | if (recog_memoized (insn) >= 0) |
15875 | for (i = 0; i < noperands; i++) | |
15876 | if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL)) | |
cf5fb4b0 RS |
15877 | return true; |
15878 | return false; | |
15879 | } | |
15880 | ||
15881 | /* Implement FINAL_PRESCAN_INSN. */ | |
15882 | ||
15883 | void | |
15884 | mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands) | |
15885 | { | |
15886 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) | |
15887 | mips_push_asm_switch (&mips_noat); | |
1afc5373 CF |
15888 | } |
15889 | ||
15890 | /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */ | |
15891 | ||
0e097268 | 15892 | static void |
cf5fb4b0 RS |
15893 | mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn, |
15894 | rtx *opvec, int noperands) | |
1afc5373 | 15895 | { |
cf5fb4b0 RS |
15896 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) |
15897 | mips_pop_asm_switch (&mips_noat); | |
1afc5373 | 15898 | } |
a3c7bb26 AN |
15899 | |
15900 | /* Return the function that is used to expand the <u>mulsidi3 pattern. | |
15901 | EXT_CODE is the code of the extension used. Return NULL if widening | |
15902 | multiplication shouldn't be used. */ | |
15903 | ||
15904 | mulsidi3_gen_fn | |
15905 | mips_mulsidi3_gen_fn (enum rtx_code ext_code) | |
15906 | { | |
15907 | bool signed_p; | |
15908 | ||
15909 | signed_p = ext_code == SIGN_EXTEND; | |
15910 | if (TARGET_64BIT) | |
15911 | { | |
15912 | /* Don't use widening multiplication with MULT when we have DMUL. Even | |
15913 | with the extension of its input operands DMUL is faster. Note that | |
15914 | the extension is not needed for signed multiplication. In order to | |
15915 | ensure that we always remove the redundant sign-extension in this | |
15916 | case we still expand mulsidi3 for DMUL. */ | |
15917 | if (ISA_HAS_DMUL3) | |
15918 | return signed_p ? gen_mulsidi3_64bit_dmul : NULL; | |
15919 | if (TARGET_FIX_R4000) | |
15920 | return NULL; | |
15921 | return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit; | |
15922 | } | |
15923 | else | |
15924 | { | |
293b77b0 | 15925 | if (TARGET_FIX_R4000 && !ISA_HAS_DSP) |
a3c7bb26 | 15926 | return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000; |
a3c7bb26 AN |
15927 | return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit; |
15928 | } | |
15929 | } | |
a1d29c8c | 15930 | \f |
c640a3bd RS |
15931 | /* Return the size in bytes of the trampoline code, padded to |
15932 | TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target | |
15933 | function address immediately follow. */ | |
a1d29c8c | 15934 | |
c640a3bd RS |
15935 | int |
15936 | mips_trampoline_code_size (void) | |
15937 | { | |
15938 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
15939 | return 4 * 4; | |
15940 | else if (ptr_mode == DImode) | |
15941 | return 8 * 4; | |
15942 | else if (ISA_HAS_LOAD_DELAY) | |
15943 | return 6 * 4; | |
a1d29c8c | 15944 | else |
c640a3bd | 15945 | return 4 * 4; |
a1d29c8c RH |
15946 | } |
15947 | ||
15948 | /* Implement TARGET_TRAMPOLINE_INIT. */ | |
15949 | ||
15950 | static void | |
15951 | mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
15952 | { | |
c640a3bd RS |
15953 | rtx addr, end_addr, high, low, opcode, mem; |
15954 | rtx trampoline[8]; | |
15955 | unsigned int i, j; | |
15956 | HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset; | |
15957 | ||
15958 | /* Work out the offsets of the pointers from the start of the | |
15959 | trampoline code. */ | |
15960 | end_addr_offset = mips_trampoline_code_size (); | |
15961 | static_chain_offset = end_addr_offset; | |
15962 | target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); | |
a1d29c8c | 15963 | |
c640a3bd RS |
15964 | /* Get pointers to the beginning and end of the code block. */ |
15965 | addr = force_reg (Pmode, XEXP (m_tramp, 0)); | |
15966 | end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset)); | |
a1d29c8c | 15967 | |
c640a3bd | 15968 | #define OP(X) gen_int_mode (X, SImode) |
a1d29c8c | 15969 | |
c640a3bd RS |
15970 | /* Build up the code in TRAMPOLINE. */ |
15971 | i = 0; | |
15972 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
15973 | { | |
15974 | /* $25 contains the address of the trampoline. Emit code of the form: | |
15975 | ||
15976 | l[wd] $1, target_function_offset($25) | |
15977 | l[wd] $static_chain, static_chain_offset($25) | |
15978 | jr $1 | |
15979 | move $25,$1. */ | |
15980 | trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM, | |
15981 | target_function_offset, | |
15982 | PIC_FUNCTION_ADDR_REGNUM)); | |
15983 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
15984 | static_chain_offset, | |
15985 | PIC_FUNCTION_ADDR_REGNUM)); | |
15986 | trampoline[i++] = OP (MIPS_JR (AT_REGNUM)); | |
15987 | trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM)); | |
15988 | } | |
15989 | else if (ptr_mode == DImode) | |
15990 | { | |
15991 | /* It's too cumbersome to create the full 64-bit address, so let's | |
15992 | instead use: | |
15993 | ||
15994 | move $1, $31 | |
15995 | bal 1f | |
15996 | nop | |
15997 | 1: l[wd] $25, target_function_offset - 12($31) | |
15998 | l[wd] $static_chain, static_chain_offset - 12($31) | |
15999 | jr $25 | |
16000 | move $31, $1 | |
16001 | ||
16002 | where 12 is the offset of "1:" from the start of the code block. */ | |
16003 | trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM)); | |
16004 | trampoline[i++] = OP (MIPS_BAL (1)); | |
16005 | trampoline[i++] = OP (MIPS_NOP); | |
16006 | trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
16007 | target_function_offset - 12, | |
16008 | RETURN_ADDR_REGNUM)); | |
16009 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16010 | static_chain_offset - 12, | |
16011 | RETURN_ADDR_REGNUM)); | |
16012 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16013 | trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM)); | |
16014 | } | |
16015 | else | |
16016 | { | |
16017 | /* If the target has load delays, emit: | |
16018 | ||
16019 | lui $1, %hi(end_addr) | |
16020 | lw $25, %lo(end_addr + ...)($1) | |
16021 | lw $static_chain, %lo(end_addr + ...)($1) | |
16022 | jr $25 | |
16023 | nop | |
16024 | ||
16025 | Otherwise emit: | |
16026 | ||
16027 | lui $1, %hi(end_addr) | |
16028 | lw $25, %lo(end_addr + ...)($1) | |
16029 | jr $25 | |
16030 | lw $static_chain, %lo(end_addr + ...)($1). */ | |
16031 | ||
16032 | /* Split END_ADDR into %hi and %lo values. Trampolines are aligned | |
16033 | to 64 bits, so the %lo value will have the bottom 3 bits clear. */ | |
16034 | high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000), | |
16035 | NULL, false, OPTAB_WIDEN); | |
16036 | high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16), | |
16037 | NULL, false, OPTAB_WIDEN); | |
16038 | low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true); | |
16039 | ||
16040 | /* Emit the LUI. */ | |
16041 | opcode = OP (MIPS_LUI (AT_REGNUM, 0)); | |
16042 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high, | |
16043 | NULL, false, OPTAB_WIDEN); | |
16044 | ||
16045 | /* Emit the load of the target function. */ | |
16046 | opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
16047 | target_function_offset - end_addr_offset, | |
16048 | AT_REGNUM)); | |
16049 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
16050 | NULL, false, OPTAB_WIDEN); | |
16051 | ||
16052 | /* Emit the JR here, if we can. */ | |
16053 | if (!ISA_HAS_LOAD_DELAY) | |
16054 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16055 | ||
16056 | /* Emit the load of the static chain register. */ | |
16057 | opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16058 | static_chain_offset - end_addr_offset, | |
16059 | AT_REGNUM)); | |
16060 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
16061 | NULL, false, OPTAB_WIDEN); | |
16062 | ||
16063 | /* Emit the JR, if we couldn't above. */ | |
16064 | if (ISA_HAS_LOAD_DELAY) | |
16065 | { | |
16066 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16067 | trampoline[i++] = OP (MIPS_NOP); | |
16068 | } | |
16069 | } | |
16070 | ||
16071 | #undef OP | |
16072 | ||
16073 | /* Copy the trampoline code. Leave any padding uninitialized. */ | |
16074 | for (j = 0; j < i; j++) | |
16075 | { | |
16076 | mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode)); | |
16077 | mips_emit_move (mem, trampoline[j]); | |
16078 | } | |
16079 | ||
16080 | /* Set up the static chain pointer field. */ | |
16081 | mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); | |
16082 | mips_emit_move (mem, chain_value); | |
16083 | ||
16084 | /* Set up the target function field. */ | |
16085 | mem = adjust_address (m_tramp, ptr_mode, target_function_offset); | |
16086 | mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); | |
16087 | ||
16088 | /* Flush the code part of the trampoline. */ | |
a1d29c8c RH |
16089 | emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); |
16090 | emit_insn (gen_clear_cache (addr, end_addr)); | |
16091 | } | |
c376dbfb DD |
16092 | |
16093 | /* Implement FUNCTION_PROFILER. */ | |
16094 | ||
16095 | void mips_function_profiler (FILE *file) | |
16096 | { | |
16097 | if (TARGET_MIPS16) | |
16098 | sorry ("mips16 function profiling"); | |
16099 | if (TARGET_LONG_CALLS) | |
16100 | { | |
16101 | /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ | |
16102 | if (Pmode == DImode) | |
16103 | fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]); | |
16104 | else | |
16105 | fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]); | |
16106 | } | |
16107 | mips_push_asm_switch (&mips_noat); | |
16108 | fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n", | |
16109 | reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]); | |
16110 | /* _mcount treats $2 as the static chain register. */ | |
16111 | if (cfun->static_chain_decl != NULL) | |
16112 | fprintf (file, "\tmove\t%s,%s\n", reg_names[2], | |
16113 | reg_names[STATIC_CHAIN_REGNUM]); | |
16114 | if (TARGET_MCOUNT_RA_ADDRESS) | |
16115 | { | |
16116 | /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the | |
16117 | ra save location. */ | |
16118 | if (cfun->machine->frame.ra_fp_offset == 0) | |
16119 | /* ra not saved, pass zero. */ | |
16120 | fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]); | |
16121 | else | |
16122 | fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n", | |
16123 | Pmode == DImode ? "dla" : "la", reg_names[12], | |
16124 | cfun->machine->frame.ra_fp_offset, | |
16125 | reg_names[STACK_POINTER_REGNUM]); | |
16126 | } | |
16127 | if (!TARGET_NEWABI) | |
16128 | fprintf (file, | |
16129 | "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", | |
16130 | TARGET_64BIT ? "dsubu" : "subu", | |
16131 | reg_names[STACK_POINTER_REGNUM], | |
16132 | reg_names[STACK_POINTER_REGNUM], | |
16133 | Pmode == DImode ? 16 : 8); | |
16134 | ||
16135 | if (TARGET_LONG_CALLS) | |
16136 | fprintf (file, "\tjalr\t%s\n", reg_names[3]); | |
16137 | else | |
16138 | fprintf (file, "\tjal\t_mcount\n"); | |
16139 | mips_pop_asm_switch (&mips_noat); | |
16140 | /* _mcount treats $2 as the static chain register. */ | |
16141 | if (cfun->static_chain_decl != NULL) | |
16142 | fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], | |
16143 | reg_names[2]); | |
16144 | } | |
49042313 MX |
16145 | |
16146 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default | |
16147 | behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even | |
1f5f063d | 16148 | when TARGET_LOONGSON_VECTORS is true. */ |
49042313 MX |
16149 | |
16150 | static unsigned HOST_WIDE_INT | |
16151 | mips_shift_truncation_mask (enum machine_mode mode) | |
16152 | { | |
1f5f063d | 16153 | if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) |
49042313 MX |
16154 | return 0; |
16155 | ||
16156 | return GET_MODE_BITSIZE (mode) - 1; | |
16157 | } | |
16158 | ||
ab77a036 RS |
16159 | \f |
16160 | /* Initialize the GCC target structure. */ | |
16161 | #undef TARGET_ASM_ALIGNED_HI_OP | |
16162 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
16163 | #undef TARGET_ASM_ALIGNED_SI_OP | |
16164 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
16165 | #undef TARGET_ASM_ALIGNED_DI_OP | |
16166 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
a8c1d5f8 | 16167 | |
525c561d AS |
16168 | #undef TARGET_OPTION_OVERRIDE |
16169 | #define TARGET_OPTION_OVERRIDE mips_option_override | |
16170 | ||
506d7b68 PB |
16171 | #undef TARGET_LEGITIMIZE_ADDRESS |
16172 | #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address | |
16173 | ||
ab77a036 RS |
16174 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
16175 | #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue | |
16176 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
16177 | #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue | |
16178 | #undef TARGET_ASM_SELECT_RTX_SECTION | |
16179 | #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section | |
16180 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION | |
16181 | #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section | |
4ca1f68f | 16182 | |
ab77a036 RS |
16183 | #undef TARGET_SCHED_INIT |
16184 | #define TARGET_SCHED_INIT mips_sched_init | |
16185 | #undef TARGET_SCHED_REORDER | |
16186 | #define TARGET_SCHED_REORDER mips_sched_reorder | |
16187 | #undef TARGET_SCHED_REORDER2 | |
646e6f41 | 16188 | #define TARGET_SCHED_REORDER2 mips_sched_reorder2 |
ab77a036 RS |
16189 | #undef TARGET_SCHED_VARIABLE_ISSUE |
16190 | #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue | |
16191 | #undef TARGET_SCHED_ADJUST_COST | |
16192 | #define TARGET_SCHED_ADJUST_COST mips_adjust_cost | |
16193 | #undef TARGET_SCHED_ISSUE_RATE | |
16194 | #define TARGET_SCHED_ISSUE_RATE mips_issue_rate | |
58684fa0 MK |
16195 | #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN |
16196 | #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn | |
16197 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
16198 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle | |
ab77a036 RS |
16199 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
16200 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
16201 | mips_multipass_dfa_lookahead | |
e472d6bf | 16202 | #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P |
a1c4f19f AP |
16203 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
16204 | mips_small_register_classes_for_mode_p | |
4ca1f68f | 16205 | |
ab77a036 RS |
16206 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
16207 | #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall | |
4ca1f68f | 16208 | |
ab77a036 RS |
16209 | #undef TARGET_INSERT_ATTRIBUTES |
16210 | #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes | |
16211 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
16212 | #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes | |
16213 | #undef TARGET_SET_CURRENT_FUNCTION | |
16214 | #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function | |
06a4ab70 | 16215 | |
ab77a036 RS |
16216 | #undef TARGET_VALID_POINTER_MODE |
16217 | #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode | |
faa832a7 AS |
16218 | #undef TARGET_REGISTER_MOVE_COST |
16219 | #define TARGET_REGISTER_MOVE_COST mips_register_move_cost | |
16220 | #undef TARGET_MEMORY_MOVE_COST | |
16221 | #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost | |
ab77a036 RS |
16222 | #undef TARGET_RTX_COSTS |
16223 | #define TARGET_RTX_COSTS mips_rtx_costs | |
16224 | #undef TARGET_ADDRESS_COST | |
16225 | #define TARGET_ADDRESS_COST mips_address_cost | |
06a4ab70 | 16226 | |
ab77a036 RS |
16227 | #undef TARGET_IN_SMALL_DATA_P |
16228 | #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p | |
118ea793 | 16229 | |
ab77a036 RS |
16230 | #undef TARGET_MACHINE_DEPENDENT_REORG |
16231 | #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg | |
118ea793 | 16232 | |
ef78aed6 AS |
16233 | #undef TARGET_PREFERRED_RELOAD_CLASS |
16234 | #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class | |
16235 | ||
ab77a036 RS |
16236 | #undef TARGET_ASM_FILE_START |
16237 | #define TARGET_ASM_FILE_START mips_file_start | |
16238 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
16239 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
118ea793 | 16240 | |
ab77a036 RS |
16241 | #undef TARGET_INIT_LIBFUNCS |
16242 | #define TARGET_INIT_LIBFUNCS mips_init_libfuncs | |
118ea793 | 16243 | |
ab77a036 RS |
16244 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
16245 | #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list | |
d7bd8aeb JJ |
16246 | #undef TARGET_EXPAND_BUILTIN_VA_START |
16247 | #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start | |
ab77a036 RS |
16248 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
16249 | #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr | |
118ea793 | 16250 | |
cde0f3fd PB |
16251 | #undef TARGET_PROMOTE_FUNCTION_MODE |
16252 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
ab77a036 RS |
16253 | #undef TARGET_PROMOTE_PROTOTYPES |
16254 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
118ea793 | 16255 | |
47be3d6d AS |
16256 | #undef TARGET_FUNCTION_VALUE |
16257 | #define TARGET_FUNCTION_VALUE mips_function_value | |
16258 | #undef TARGET_LIBCALL_VALUE | |
16259 | #define TARGET_LIBCALL_VALUE mips_libcall_value | |
16260 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
16261 | #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p | |
ab77a036 RS |
16262 | #undef TARGET_RETURN_IN_MEMORY |
16263 | #define TARGET_RETURN_IN_MEMORY mips_return_in_memory | |
16264 | #undef TARGET_RETURN_IN_MSB | |
16265 | #define TARGET_RETURN_IN_MSB mips_return_in_msb | |
4dbdb061 | 16266 | |
ab77a036 RS |
16267 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
16268 | #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk | |
16269 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
16270 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true | |
4dbdb061 | 16271 | |
6e9e0126 NF |
16272 | #undef TARGET_PRINT_OPERAND |
16273 | #define TARGET_PRINT_OPERAND mips_print_operand | |
16274 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
16275 | #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address | |
16276 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
16277 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p | |
16278 | ||
ab77a036 RS |
16279 | #undef TARGET_SETUP_INCOMING_VARARGS |
16280 | #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs | |
16281 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
16282 | #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming | |
16283 | #undef TARGET_MUST_PASS_IN_STACK | |
16284 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
16285 | #undef TARGET_PASS_BY_REFERENCE | |
16286 | #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference | |
16287 | #undef TARGET_CALLEE_COPIES | |
16288 | #define TARGET_CALLEE_COPIES mips_callee_copies | |
16289 | #undef TARGET_ARG_PARTIAL_BYTES | |
16290 | #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes | |
c8717ea3 NF |
16291 | #undef TARGET_FUNCTION_ARG |
16292 | #define TARGET_FUNCTION_ARG mips_function_arg | |
16293 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
16294 | #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance | |
c2ed6cf8 NF |
16295 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
16296 | #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary | |
cd3a59b3 | 16297 | |
ab77a036 RS |
16298 | #undef TARGET_MODE_REP_EXTENDED |
16299 | #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended | |
912f2dac | 16300 | |
ab77a036 RS |
16301 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
16302 | #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p | |
912f2dac | 16303 | |
ab77a036 RS |
16304 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
16305 | #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p | |
912f2dac | 16306 | |
cc4b5170 RG |
16307 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
16308 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode | |
26983c22 | 16309 | |
ab77a036 RS |
16310 | #undef TARGET_INIT_BUILTINS |
16311 | #define TARGET_INIT_BUILTINS mips_init_builtins | |
7725086e RS |
16312 | #undef TARGET_BUILTIN_DECL |
16313 | #define TARGET_BUILTIN_DECL mips_builtin_decl | |
ab77a036 RS |
16314 | #undef TARGET_EXPAND_BUILTIN |
16315 | #define TARGET_EXPAND_BUILTIN mips_expand_builtin | |
b12cbf2c | 16316 | |
ab77a036 RS |
16317 | #undef TARGET_HAVE_TLS |
16318 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
b12cbf2c | 16319 | |
ab77a036 RS |
16320 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
16321 | #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem | |
a44380d2 | 16322 | |
1a627b35 RS |
16323 | #undef TARGET_LEGITIMATE_CONSTANT_P |
16324 | #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p | |
16325 | ||
ab77a036 RS |
16326 | #undef TARGET_ENCODE_SECTION_INFO |
16327 | #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info | |
a44380d2 | 16328 | |
ab77a036 RS |
16329 | #undef TARGET_ATTRIBUTE_TABLE |
16330 | #define TARGET_ATTRIBUTE_TABLE mips_attribute_table | |
16331 | /* All our function attributes are related to how out-of-line copies should | |
16332 | be compiled or called. They don't in themselves prevent inlining. */ | |
16333 | #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P | |
16334 | #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true | |
a44380d2 | 16335 | |
ab77a036 RS |
16336 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
16337 | #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry | |
076a5ce6 | 16338 | |
ab77a036 RS |
16339 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P |
16340 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p | |
16341 | #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P | |
16342 | #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p | |
076a5ce6 | 16343 | |
ab77a036 RS |
16344 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
16345 | #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes | |
076a5ce6 | 16346 | |
ab77a036 RS |
16347 | #ifdef HAVE_AS_DTPRELWORD |
16348 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
16349 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel | |
16350 | #endif | |
16351 | #undef TARGET_DWARF_REGISTER_SPAN | |
16352 | #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span | |
076a5ce6 | 16353 | |
1afc5373 CF |
16354 | #undef TARGET_ASM_FINAL_POSTSCAN_INSN |
16355 | #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn | |
16356 | ||
c6c3dba9 PB |
16357 | #undef TARGET_LEGITIMATE_ADDRESS_P |
16358 | #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p | |
16359 | ||
b52b1749 AS |
16360 | #undef TARGET_FRAME_POINTER_REQUIRED |
16361 | #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required | |
16362 | ||
7b5cbb57 AS |
16363 | #undef TARGET_CAN_ELIMINATE |
16364 | #define TARGET_CAN_ELIMINATE mips_can_eliminate | |
16365 | ||
5efd84c5 NF |
16366 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
16367 | #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage | |
16368 | ||
a1d29c8c RH |
16369 | #undef TARGET_TRAMPOLINE_INIT |
16370 | #define TARGET_TRAMPOLINE_INIT mips_trampoline_init | |
16371 | ||
b5f5d41d AS |
16372 | #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME |
16373 | #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename | |
16374 | ||
49042313 MX |
16375 | #undef TARGET_SHIFT_TRUNCATION_MASK |
16376 | #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask | |
16377 | ||
ab77a036 | 16378 | struct gcc_target targetm = TARGET_INITIALIZER; |
a44380d2 | 16379 | \f |
e2500fed | 16380 | #include "gt-mips.h" |