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Merge in gcc2-ss-010999
[thirdparty/gcc.git] / gcc / config / mips / mips.c
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cee98a59 1/* Subroutines for insn-output.c for MIPS
2d7423eb 2 Copyright (C) 1989, 90, 91, 93-98, 1999 Free Software Foundation, Inc.
cee98a59 3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
b2a68403 4 Changes by Michael Meissner, meissner@osf.org.
147255d8
JW		 5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
cee98a59
MM		 7
8This file is part of GNU CC.
9
10GNU CC is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15GNU CC is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with GNU CC; see the file COPYING. If not, write to
0e29e3c9
RK		 22the Free Software Foundation, 59 Temple Place - Suite 330,
23Boston, MA 02111-1307, USA. */
cee98a59 24
147255d8
JW		 25/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
28
cee98a59 29#include "config.h"
50b2596f
KG		 30#include "system.h"
31#include <signal.h>
cee98a59
MM		 32#include "rtl.h"
33#include "regs.h"
34#include "hard-reg-set.h"
35#include "real.h"
36#include "insn-config.h"
37#include "conditions.h"
38#include "insn-flags.h"
39#include "insn-attr.h"
40#include "insn-codes.h"
41#include "recog.h"
50b2596f 42#include "toplev.h"
c5c76735
JL		 43#include "output.h"
44
cee98a59 45#include "tree.h"
49ad7cfa 46#include "function.h"
cee98a59
MM		 47#include "expr.h"
48#include "flags.h"
2bcb2ab3 49#include "reload.h"
50b2596f 50#include "output.h"
cee98a59 51
c7391272 52#if defined(USG) || !defined(HAVE_STAB_H)
cee98a59
MM		 53#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
54#else
55#include <stab.h> /* On BSD, use the system's stab.h. */
56#endif /* not USG */
57
58#ifdef __GNU_STAB__
59#define STAB_CODE_TYPE enum __stab_debug_code
60#else
61#define STAB_CODE_TYPE int
62#endif
63
0fb5ac6f 64extern char *mktemp ();
0fb5ac6f 65extern tree lookup_name ();
cee98a59 66
34b650b3
MM		 67/* Enumeration for all of the relational tests, so that we can build
68 arrays indexed by the test type, and not worry about the order
69 of EQ, NE, etc. */
70
71enum internal_test {
72 ITEST_EQ,
73 ITEST_NE,
74 ITEST_GT,
75 ITEST_GE,
76 ITEST_LT,
77 ITEST_LE,
78 ITEST_GTU,
79 ITEST_GEU,
80 ITEST_LTU,
81 ITEST_LEU,
82 ITEST_MAX
83 };
84
881060d0
JL		 85
86struct constant;
87static enum internal_test map_test_to_internal_test PROTO ((enum rtx_code));
88static int mips16_simple_memory_operand PROTO ((rtx, rtx,
89 enum machine_mode));
90static int m16_check_op PROTO ((rtx, int, int, int));
91static void block_move_loop PROTO ((rtx, rtx, int, int,
92 rtx, rtx));
93static void block_move_call PROTO ((rtx, rtx, rtx));
94static FILE *make_temp_file PROTO ((void));
95static void save_restore_insns PROTO ((int, rtx,
96 long, FILE *));
97static void mips16_output_gp_offset PROTO ((FILE *, rtx));
98static void mips16_fp_args PROTO ((FILE *, int, int));
99static void build_mips16_function_stub PROTO ((FILE *));
100static void mips16_optimize_gp PROTO ((rtx));
101static rtx add_constant PROTO ((struct constant **,
102 rtx,
103 enum machine_mode));
104static void dump_constants PROTO ((struct constant *,
105 rtx));
106static rtx mips_find_symbol PROTO ((rtx));
e2fe6aba
KG		 107static void abort_with_insn PROTO ((rtx, const char *))
108 ATTRIBUTE_NORETURN;
d660677d 109static int symbolic_expression_p PROTO ((rtx));
881060d0 110
cee98a59
MM		 111/* Global variables for machine-dependent things. */
112
113/* Threshold for data being put into the small data/bss area, instead
114 of the normal data area (references to the small data/bss area take
115 1 instruction, and use the global pointer, references to the normal
116 data area takes 2 instructions). */
117int mips_section_threshold = -1;
118
119/* Count the number of .file directives, so that .loc is up to date. */
120int num_source_filenames = 0;
121
cee98a59
MM		 122/* Count the number of sdb related labels are generated (to find block
123 start and end boundaries). */
124int sdb_label_count = 0;
125
ddd5a7c1 126/* Next label # for each statement for Silicon Graphics IRIS systems. */
cee98a59
MM		 127int sym_lineno = 0;
128
129/* Non-zero if inside of a function, because the stupid MIPS asm can't
130 handle .files inside of functions. */
131int inside_function = 0;
132
cee98a59
MM		 133/* Files to separate the text and the data output, so that all of the data
134 can be emitted before the text, which will mean that the assembler will
135 generate smaller code, based on the global pointer. */
136FILE *asm_out_data_file;
137FILE *asm_out_text_file;
138
139/* Linked list of all externals that are to be emitted when optimizing
140 for the global pointer if they haven't been declared by the end of
141 the program with an appropriate .comm or initialization. */
142
f5963e61
JL		 143struct extern_list
144{
cee98a59
MM		 145 struct extern_list *next; /* next external */
146 char *name; /* name of the external */
147 int size; /* size in bytes */
148} *extern_head = 0;
149
cee98a59 150/* Name of the file containing the current function. */
e2fe6aba 151const char *current_function_file = "";
cee98a59
MM		 152
153/* Warning given that Mips ECOFF can't support changing files
154 within a function. */
155int file_in_function_warning = FALSE;
156
c831afd5 157/* Whether to suppress issuing .loc's because the user attempted
cee98a59
MM		 158 to change the filename within a function. */
159int ignore_line_number = FALSE;
160
161/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
162int set_noreorder;
163int set_noat;
164int set_nomacro;
165int set_volatile;
166
167/* The next branch instruction is a branch likely, not branch normal. */
168int mips_branch_likely;
169
170/* Count of delay slots and how many are filled. */
171int dslots_load_total;
172int dslots_load_filled;
173int dslots_jump_total;
174int dslots_jump_filled;
175
176/* # of nops needed by previous insn */
177int dslots_number_nops;
178
179/* Number of 1/2/3 word references to data items (ie, not jal's). */
180int num_refs[3];
181
182/* registers to check for load delay */
183rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
184
185/* Cached operands, and operator to compare for use in set/branch on
186 condition codes. */
187rtx branch_cmp[2];
188
189/* what type of branch to use */
190enum cmp_type branch_type;
191
6f3c667f
MM		 192/* Number of previously seen half-pic pointers and references. */
193static int prev_half_pic_ptrs = 0;
194static int prev_half_pic_refs = 0;
195
cee98a59
MM		 196/* which cpu are we scheduling for */
197enum processor_type mips_cpu;
198
199/* which instruction set architecture to use. */
200int mips_isa;
201
ade6c319 202#ifdef MIPS_ABI_DEFAULT
04bd620d 203/* Which ABI to use. This is defined to a constant in mips.h if the target
ade6c319 204 doesn't support multiple ABIs. */
04bd620d 205int mips_abi;
ade6c319
JW		 206#endif
207
cee98a59 208/* Strings to hold which cpu and instruction set architecture to use. */
e2fe6aba
KG		 209const char *mips_cpu_string; /* for -mcpu=<xxx> */
210const char *mips_isa_string; /* for -mips{1,2,3,4} */
211const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
cee98a59 212
2bcb2ab3
GK		 213/* Whether we are generating mips16 code. This is a synonym for
214 TARGET_MIPS16, and exists for use as an attribute. */
215int mips16;
216
217/* This variable is set by -mno-mips16. We only care whether
218 -mno-mips16 appears or not, and using a string in this fashion is
219 just a way to avoid using up another bit in target_flags. */
e2fe6aba 220const char *mips_no_mips16_string;
2bcb2ab3 221
3ce1ba83
GRK		 222/* This is only used to determine if an type size setting option was
223 explicitly specified (-mlong64, -mint64, -mlong32). The specs
224 set this option if such an option is used. */
d8c8a706 225const char *mips_explicit_type_size_string;
3ce1ba83 226
2bcb2ab3
GK		 227/* Whether we are generating mips16 hard float code. In mips16 mode
228 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
229 -msoft-float was not specified by the user, which means that we
230 should arrange to call mips32 hard floating point code. */
231int mips16_hard_float;
232
233/* This variable is set by -mentry. We only care whether -mentry
234 appears or not, and using a string in this fashion is just a way to
235 avoid using up another bit in target_flags. */
e2fe6aba 236const char *mips_entry_string;
2bcb2ab3
GK		 237
238/* Whether we should entry and exit pseudo-ops in mips16 mode. */
239int mips_entry;
240
910628b8
JW		 241/* If TRUE, we split addresses into their high and low parts in the RTL. */
242int mips_split_addresses;
243
ffa9d0b1 244/* Generating calls to position independent functions? */
1d6ce736 245enum mips_abicalls_type mips_abicalls;
ffa9d0b1 246
147255d8
JW		 247/* High and low marks for floating point values which we will accept
248 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
249 initialized in override_options. */
250REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
251
bfed8dac 252/* Mode used for saving/restoring general purpose registers. */
b3fb0b5e 253static enum machine_mode gpr_mode;
bfed8dac 254
cee98a59
MM		 255/* Array giving truth value on whether or not a given hard register
256 can support a given mode. */
257char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
258
259/* Current frame information calculated by compute_frame_size. */
260struct mips_frame_info current_frame_info;
261
262/* Zero structure to initialize current_frame_info. */
263struct mips_frame_info zero_frame_info;
264
c831afd5
MM		 265/* Temporary filename used to buffer .text until end of program
266 for -mgpopt. */
267static char *temp_filename;
268
92544bdf
ILT		 269/* Pseudo-reg holding the address of the current function when
270 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
271 by mips_finalize_pic if it was created. */
272rtx embedded_pic_fnaddr_rtx;
273
2bcb2ab3
GK		 274/* The length of all strings seen when compiling for the mips16. This
275 is used to tell how many strings are in the constant pool, so that
276 we can see if we may have an overflow. This is reset each time the
277 constant pool is output. */
278int mips_string_length;
279
280/* Pseudo-reg holding the value of $28 in a mips16 function which
281 refers to GP relative global variables. */
282rtx mips16_gp_pseudo_rtx;
283
284/* In mips16 mode, we build a list of all the string constants we see
285 in a particular function. */
286
287struct string_constant
288{
289 struct string_constant *next;
290 char *label;
291};
292
293static struct string_constant *string_constants;
294
cee98a59
MM		 295/* List of all MIPS punctuation characters used by print_operand. */
296char mips_print_operand_punct[256];
297
298/* Map GCC register number to debugger register number. */
299int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
300
301/* Buffer to use to enclose a load/store operation with %{ %} to
302 turn on .set volatile. */
303static char volatile_buffer[60];
304
305/* Hardware names for the registers. If -mrnames is used, this
306 will be overwritten with mips_sw_reg_names. */
307
308char mips_reg_names[][8] =
309{
310 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
311 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
312 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
313 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
314 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
315 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
316 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
317 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
b8eb88d0
ILT		 318 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
319 "$fcc5","$fcc6","$fcc7","$rap"
cee98a59
MM		 320};
321
322/* Mips software names for the registers, used to overwrite the
323 mips_reg_names array. */
324
325char mips_sw_reg_names[][8] =
326{
147255d8
JW		 327 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
328 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
329 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
330 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
cee98a59
MM		 331 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
332 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
333 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
334 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
b8eb88d0
ILT		 335 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
336 "$fcc5","$fcc6","$fcc7","$rap"
cee98a59
MM		 337};
338
339/* Map hard register number to register class */
340enum reg_class mips_regno_to_class[] =
341{
2bcb2ab3
GK		 342 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
343 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
cee98a59
MM		 344 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
345 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
2bcb2ab3 346 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
cee98a59 347 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
2bcb2ab3 348 T_REG, GR_REGS, GR_REGS, GR_REGS,
cee98a59
MM		 349 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
350 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
351 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
352 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
353 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
354 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
355 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
b987661c 358 HI_REG, LO_REG, HILO_REG, ST_REGS,
b8eb88d0
ILT		 359 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
360 ST_REGS, ST_REGS, ST_REGS, GR_REGS
cee98a59
MM		 361};
362
363/* Map register constraint character to register class. */
364enum reg_class mips_char_to_class[256] =
365{
366 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
367 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430};
431
432\f
433/* Return truth value of whether OP can be used as an operands
434 where a register or 16 bit unsigned integer is needed. */
435
436int
437uns_arith_operand (op, mode)
438 rtx op;
439 enum machine_mode mode;
440{
441 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
f5963e61 442 return 1;
cee98a59
MM		 443
444 return register_operand (op, mode);
445}
446
447/* Return truth value of whether OP can be used as an operands
448 where a 16 bit integer is needed */
449
450int
451arith_operand (op, mode)
452 rtx op;
453 enum machine_mode mode;
454{
455 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
f5963e61 456 return 1;
cee98a59 457
2bcb2ab3
GK		 458 /* On the mips16, a GP relative value is a signed 16 bit offset. */
459 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
460 return 1;
461
cee98a59
MM		 462 return register_operand (op, mode);
463}
464
465/* Return truth value of whether OP can be used as an operand in a two
466 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
467
468int
469arith32_operand (op, mode)
470 rtx op;
471 enum machine_mode mode;
472{
473 if (GET_CODE (op) == CONST_INT)
f5963e61 474 return 1;
cee98a59
MM		 475
476 return register_operand (op, mode);
477}
478
479/* Return truth value of whether OP is a integer which fits in 16 bits */
480
481int
482small_int (op, mode)
483 rtx op;
38831dfe 484 enum machine_mode mode ATTRIBUTE_UNUSED;
cee98a59
MM		 485{
486 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
487}
488
33563487 489/* Return truth value of whether OP is a 32 bit integer which is too big to
cee98a59
MM		 490 be loaded with one instruction. */
491
492int
493large_int (op, mode)
494 rtx op;
38831dfe 495 enum machine_mode mode ATTRIBUTE_UNUSED;
cee98a59 496{
85f5e2b6 497 HOST_WIDE_INT value;
cee98a59
MM		 498
499 if (GET_CODE (op) != CONST_INT)
f5963e61 500 return 0;
cee98a59
MM		 501
502 value = INTVAL (op);
cee98a59 503
f5963e61
JL		 504 /* ior reg,$r0,value */
505 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
506 return 0;
cee98a59 507
f5963e61
JL		 508 /* subu reg,$r0,value */
509 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
510 return 0;
cee98a59 511
f5963e61
JL		 512 /* lui reg,value>>16 */
513 if ((value & 0x0000ffff) == 0)
514 return 0;
515
516 return 1;
cee98a59
MM		 517}
518
2bcb2ab3
GK		 519/* Return truth value of whether OP is a register or the constant 0.
520 In mips16 mode, we only accept a register, since the mips16 does
521 not have $0. */
cee98a59
MM		 522
523int
524reg_or_0_operand (op, mode)
525 rtx op;
526 enum machine_mode mode;
527{
528 switch (GET_CODE (op))
529 {
530 case CONST_INT:
2bcb2ab3 531 if (TARGET_MIPS16)
f5963e61
JL		 532 return 0;
533 return INTVAL (op) == 0;
cee98a59
MM		 534
535 case CONST_DOUBLE:
f5963e61
JL		 536 if (TARGET_MIPS16)
537 return 0;
538 return op == CONST0_RTX (mode);
cee98a59
MM		 539
540 case REG:
541 case SUBREG:
542 return register_operand (op, mode);
f5963e61
JL		 543
544 default:
545 break;
cee98a59
MM		 546 }
547
f5963e61 548 return 0;
cee98a59
MM		 549}
550
def72bd2
GRK		 551/* Return truth value of whether OP is a register or the constant 0,
552 even in mips16 mode. */
553
554int
555true_reg_or_0_operand (op, mode)
556 rtx op;
557 enum machine_mode mode;
558{
559 switch (GET_CODE (op))
560 {
561 case CONST_INT:
562 return INTVAL (op) == 0;
563
564 case CONST_DOUBLE:
565 return op == CONST0_RTX (mode);
566
567 case REG:
568 case SUBREG:
569 return register_operand (op, mode);
570
571 default:
572 break;
573 }
574
575 return 0;
576}
577
cee98a59
MM		 578/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
579
580int
581mips_const_double_ok (op, mode)
582 rtx op;
583 enum machine_mode mode;
584{
85098019
JW		 585 REAL_VALUE_TYPE d;
586
cee98a59 587 if (GET_CODE (op) != CONST_DOUBLE)
f5963e61 588 return 0;
cee98a59 589
79438502 590 if (mode == VOIDmode)
f5963e61 591 return 1;
cee98a59
MM		 592
593 if (mode != SFmode && mode != DFmode)
f5963e61 594 return 0;
cee98a59 595
147255d8 596 if (op == CONST0_RTX (mode))
f5963e61 597 return 1;
cee98a59 598
33563487 599 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
a53f72db 600 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
f5963e61 601 return 0;
33563487 602
85098019 603 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
cee98a59 604
85098019
JW		 605 if (REAL_VALUE_ISNAN (d))
606 return FALSE;
cee98a59 607
85098019
JW		 608 if (REAL_VALUE_NEGATIVE (d))
609 d = REAL_VALUE_NEGATE (d);
cee98a59 610
85098019
JW		 611 if (mode == DFmode)
612 {
613 if (REAL_VALUES_LESS (d, dfhigh)
614 && REAL_VALUES_LESS (dflow, d))
f5963e61 615 return 1;
85098019
JW		 616 }
617 else
618 {
619 if (REAL_VALUES_LESS (d, sfhigh)
620 && REAL_VALUES_LESS (sflow, d))
f5963e61 621 return 1;
cee98a59 622 }
cee98a59 623
f5963e61 624 return 0;
cee98a59
MM		 625}
626
b8eb88d0
ILT		 627/* Accept the floating point constant 1 in the appropriate mode. */
628
629int
630const_float_1_operand (op, mode)
631 rtx op;
632 enum machine_mode mode;
633{
634 REAL_VALUE_TYPE d;
635 static REAL_VALUE_TYPE onedf;
636 static REAL_VALUE_TYPE onesf;
637 static int one_initialized;
638
639 if (GET_CODE (op) != CONST_DOUBLE
640 || mode != GET_MODE (op)
641 || (mode != DFmode && mode != SFmode))
f5963e61 642 return 0;
b8eb88d0
ILT		 643
644 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
645
646 /* We only initialize these values if we need them, since we will
647 never get called unless mips_isa >= 4. */
648 if (! one_initialized)
649 {
650 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
651 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
f5963e61 652 one_initialized = 1;
b8eb88d0
ILT		 653 }
654
655 if (mode == DFmode)
656 return REAL_VALUES_EQUAL (d, onedf);
657 else
658 return REAL_VALUES_EQUAL (d, onesf);
659}
660
2bcb2ab3
GK		 661/* Return true if a memory load or store of REG plus OFFSET in MODE
662 can be represented in a single word on the mips16. */
663
664static int
665mips16_simple_memory_operand (reg, offset, mode)
666 rtx reg;
667 rtx offset;
668 enum machine_mode mode;
669{
670 int size, off;
671
672 if (mode == BLKmode)
673 {
674 /* We can't tell, because we don't know how the value will
f5963e61 675 eventually be accessed. Returning 0 here does no great
2bcb2ab3 676 harm; it just prevents some possible instruction scheduling. */
f5963e61 677 return 0;
2bcb2ab3
GK		 678 }
679
680 size = GET_MODE_SIZE (mode);
681
682 if (INTVAL (offset) % size != 0)
f5963e61 683 return 0;
2bcb2ab3
GK		 684 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
685 off = 0x100;
686 else
687 off = 0x20;
688 if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
f5963e61
JL		 689 return 1;
690 return 0;
2bcb2ab3
GK		 691}
692
cee98a59
MM		 693/* Return truth value if a memory operand fits in a single instruction
694 (ie, register + small offset). */
695
696int
697simple_memory_operand (op, mode)
698 rtx op;
699 enum machine_mode mode;
700{
701 rtx addr, plus0, plus1;
cee98a59
MM		 702
703 /* Eliminate non-memory operations */
704 if (GET_CODE (op) != MEM)
f5963e61 705 return 0;
cee98a59
MM		 706
707 /* dword operations really put out 2 instructions, so eliminate them. */
910628b8
JW		 708 /* ??? This isn't strictly correct. It is OK to accept multiword modes
709 here, since the length attributes are being set correctly, but only
710 if the address is offsettable. LO_SUM is not offsettable. */
147255d8 711 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
f5963e61 712 return 0;
cee98a59
MM		 713
714 /* Decode the address now. */
715 addr = XEXP (op, 0);
716 switch (GET_CODE (addr))
717 {
718 case REG:
910628b8 719 case LO_SUM:
f5963e61 720 return 1;
cee98a59
MM		 721
722 case CONST_INT:
2bcb2ab3 723 if (TARGET_MIPS16)
f5963e61 724 return 0;
cee98a59
MM		 725 return SMALL_INT (op);
726
727 case PLUS:
728 plus0 = XEXP (addr, 0);
729 plus1 = XEXP (addr, 1);
730 if (GET_CODE (plus0) == REG
f5963e61 731 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
2bcb2ab3
GK		 732 && (! TARGET_MIPS16
733 || mips16_simple_memory_operand (plus0, plus1, mode)))
f5963e61 734 return 1;
cee98a59
MM		 735
736 else if (GET_CODE (plus1) == REG
f5963e61 737 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
2bcb2ab3
GK		 738 && (! TARGET_MIPS16
739 || mips16_simple_memory_operand (plus1, plus0, mode)))
f5963e61 740 return 1;
cee98a59
MM		 741
742 else
f5963e61 743 return 0;
cee98a59
MM		 744
745#if 0
746 /* We used to allow small symbol refs here (ie, stuff in .sdata
747 or .sbss), but this causes some bugs in G++. Also, it won't
748 interfere if the MIPS linker rewrites the store instruction
749 because the function is PIC. */
750
751 case LABEL_REF: /* never gp relative */
752 break;
753
754 case CONST:
755 /* If -G 0, we can never have a GP relative memory operation.
756 Also, save some time if not optimizing. */
147255d8 757 if (!TARGET_GP_OPT)
f5963e61 758 return 0;
cee98a59 759
c831afd5
MM		 760 {
761 rtx offset = const0_rtx;
147255d8 762 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
c831afd5 763 if (GET_CODE (op) != SYMBOL_REF)
f5963e61 764 return 0;
cee98a59 765
c831afd5 766 /* let's be paranoid.... */
147255d8 767 if (! SMALL_INT (offset))
f5963e61 768 return 0;
c831afd5 769 }
f5963e61 770
cee98a59
MM		 771 /* fall through */
772
773 case SYMBOL_REF:
cee98a59
MM		 774 return SYMBOL_REF_FLAG (addr);
775#endif
2bcb2ab3
GK		 776
777 /* This SYMBOL_REF case is for the mips16. If the above case is
778 reenabled, this one should be merged in. */
779 case SYMBOL_REF:
780 /* References to the constant pool on the mips16 use a small
781 offset if the function is small. The only time we care about
782 getting this right is during delayed branch scheduling, so
783 don't need to check until then. The machine_dependent_reorg
784 function will set the total length of the instructions used
785 in the function in current_frame_info. If that is small
786 enough, we know for sure that this is a small offset. It
787 would be better if we could take into account the location of
788 the instruction within the function, but we can't, because we
789 don't know where we are. */
790 if (TARGET_MIPS16
791 && CONSTANT_POOL_ADDRESS_P (addr)
792 && current_frame_info.insns_len > 0)
793 {
794 long size;
795
796 size = current_frame_info.insns_len + get_pool_size ();
797 if (GET_MODE_SIZE (mode) == 4)
798 return size < 4 * 0x100;
799 else if (GET_MODE_SIZE (mode) == 8)
800 return size < 8 * 0x20;
801 else
f5963e61 802 return 0;
2bcb2ab3
GK		 803 }
804
f5963e61
JL		 805 return 0;
806
807 default:
808 break;
cee98a59
MM		 809 }
810
f5963e61 811 return 0;
cee98a59
MM		 812}
813
f5963e61 814/* Return nonzero for a memory address that can be used to load or store
2bcb2ab3
GK		 815 a doubleword. */
816
817int
818double_memory_operand (op, mode)
819 rtx op;
820 enum machine_mode mode;
821{
822 rtx addr;
823
824 if (GET_CODE (op) != MEM
825 || ! memory_operand (op, mode))
826 {
827 /* During reload, we accept a pseudo register if it has an
828 appropriate memory address. If we don't do this, we will
829 wind up reloading into a register, and then reloading that
830 register from memory, when we could just reload directly from
831 memory. */
832 if (reload_in_progress
833 && GET_CODE (op) == REG
834 && REGNO (op) >= FIRST_PSEUDO_REGISTER
835 && reg_renumber[REGNO (op)] < 0
836 && reg_equiv_mem[REGNO (op)] != 0
837 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
f5963e61 838 return 1;
2bcb2ab3 839
f85c8be7
JW		 840 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
841 the same test performed for 'm' in find_reloads. */
842
843 if (reload_in_progress
844 && TARGET_64BIT
845 && (GET_CODE (op) == MEM
846 || (GET_CODE (op) == REG
847 && REGNO (op) >= FIRST_PSEUDO_REGISTER
848 && reg_renumber[REGNO (op)] < 0)))
849 return 1;
850
2bcb2ab3
GK		 851 if (reload_in_progress
852 && TARGET_MIPS16
853 && GET_CODE (op) == MEM)
854 {
855 rtx addr;
856
857 addr = XEXP (op, 0);
858
859 /* During reload on the mips16, we accept a large offset
860 from the frame pointer or the stack pointer. This large
861 address will get reloaded anyhow. */
862 if (GET_CODE (addr) == PLUS
863 && GET_CODE (XEXP (addr, 0)) == REG
864 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
865 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
866 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
867 && ! SMALL_INT (XEXP (addr, 1)))
868 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
869 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
f5963e61 870 return 1;
2bcb2ab3
GK		 871
872 /* Similarly, we accept a case where the memory address is
873 itself on the stack, and will be reloaded. */
874 if (GET_CODE (addr) == MEM)
875 {
876 rtx maddr;
877
878 maddr = XEXP (addr, 0);
879 if (GET_CODE (maddr) == PLUS
880 && GET_CODE (XEXP (maddr, 0)) == REG
881 && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
882 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
883 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
884 && ! SMALL_INT (XEXP (maddr, 1)))
885 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
886 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
f5963e61 887 return 1;
2bcb2ab3
GK		 888 }
889
890 /* We also accept the same case when we have a 16 bit signed
891 offset mixed in as well. The large address will get
892 reloaded, and the 16 bit offset will be OK. */
893 if (GET_CODE (addr) == PLUS
894 && GET_CODE (XEXP (addr, 0)) == MEM
895 && GET_CODE (XEXP (addr, 1)) == CONST_INT
896 && SMALL_INT (XEXP (addr, 1)))
897 {
898 addr = XEXP (XEXP (addr, 0), 0);
899 if (GET_CODE (addr) == PLUS
900 && GET_CODE (XEXP (addr, 0)) == REG
901 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
902 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
903 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
904 && ! SMALL_INT (XEXP (addr, 1)))
905 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
906 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
f5963e61 907 return 1;
2bcb2ab3
GK		 908 }
909 }
910
f5963e61 911 return 0;
2bcb2ab3
GK		 912 }
913
914 if (TARGET_64BIT)
915 {
916 /* In this case we can use an instruction like sd. */
f5963e61 917 return 1;
2bcb2ab3
GK		 918 }
919
920 /* Make sure that 4 added to the address is a valid memory address.
921 This essentially just checks for overflow in an added constant. */
922
923 addr = XEXP (op, 0);
924
925 if (CONSTANT_ADDRESS_P (addr))
f5963e61 926 return 1;
2bcb2ab3
GK		 927
928 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
929 ? SImode
930 : SFmode),
931 plus_constant_for_output (addr, 4));
932}
933
f5963e61 934/* Return nonzero if the code of this rtx pattern is EQ or NE. */
cee98a59
MM		 935
936int
937equality_op (op, mode)
938 rtx op;
939 enum machine_mode mode;
940{
941 if (mode != GET_MODE (op))
f5963e61 942 return 0;
cee98a59 943
f5963e61 944 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
cee98a59
MM		 945}
946
f5963e61 947/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
cee98a59
MM		 948
949int
950cmp_op (op, mode)
951 rtx op;
952 enum machine_mode mode;
953{
954 if (mode != GET_MODE (op))
f5963e61 955 return 0;
cee98a59 956
f5963e61 957 return GET_RTX_CLASS (GET_CODE (op)) == '<';
cee98a59
MM		 958}
959
f5963e61 960/* Return nonzero if the operand is either the PC or a label_ref. */
34b650b3
MM		 961
962int
963pc_or_label_operand (op, mode)
964 rtx op;
38831dfe 965 enum machine_mode mode ATTRIBUTE_UNUSED;
34b650b3
MM		 966{
967 if (op == pc_rtx)
f5963e61 968 return 1;
34b650b3
MM		 969
970 if (GET_CODE (op) == LABEL_REF)
f5963e61 971 return 1;
34b650b3 972
f5963e61 973 return 0;
34b650b3
MM		 974}
975
50c0000c
RS		 976/* Test for a valid operand for a call instruction.
977 Don't allow the arg pointer register or virtual regs
978 since they may change into reg + const, which the patterns
979 can't handle yet. */
980
981int
982call_insn_operand (op, mode)
983 rtx op;
38831dfe 984 enum machine_mode mode ATTRIBUTE_UNUSED;
50c0000c 985{
f5963e61
JL		 986 return (CONSTANT_ADDRESS_P (op)
987 || (GET_CODE (op) == REG && op != arg_pointer_rtx
988 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
989 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
910628b8
JW		 990}
991
f5963e61 992/* Return nonzero if OPERAND is valid as a source operand for a move
910628b8
JW		 993 instruction. */
994
995int
996move_operand (op, mode)
997 rtx op;
998 enum machine_mode mode;
999{
15f3d16a
JL		 1000 /* Accept any general operand after reload has started; doing so
1001 avoids losing if reload does an in-place replacement of a register
1002 with a SYMBOL_REF or CONST. */
910628b8 1003 return (general_operand (op, mode)
15f3d16a 1004 && (! (mips_split_addresses && mips_check_split (op, mode))
f5963e61 1005 || reload_in_progress || reload_completed)
2bcb2ab3
GK		 1006 && ! (TARGET_MIPS16
1007 && GET_CODE (op) == SYMBOL_REF
1008 && ! mips16_constant (op, mode, 1, 0)));
910628b8
JW		 1009}
1010
f5963e61 1011/* Return nonzero if OPERAND is valid as a source operand for movdi.
2a0b0bf5
ILT		 1012 This accepts not only general_operand, but also sign extended
1013 constants and registers. We need to accept sign extended constants
1014 in case a sign extended register which is used in an expression,
1015 and is equivalent to a constant, is spilled. */
1016
1017int
1018movdi_operand (op, mode)
1019 rtx op;
1020 enum machine_mode mode;
1021{
1022 if (TARGET_64BIT
1023 && mode == DImode
1024 && GET_CODE (op) == SIGN_EXTEND
1025 && GET_MODE (op) == DImode
1026 && (GET_MODE (XEXP (op, 0)) == SImode
1027 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1028 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1029 && (register_operand (XEXP (op, 0), SImode)
1030 || immediate_operand (XEXP (op, 0), SImode)))
1031 return 1;
1032
3871c609
GK		 1033 return (general_operand (op, mode)
1034 && ! (TARGET_MIPS16
1035 && GET_CODE (op) == SYMBOL_REF
1036 && ! mips16_constant (op, mode, 1, 0)));
2a0b0bf5
ILT		 1037}
1038
1039/* Like register_operand, but when in 64 bit mode also accept a sign
1040 extend of a 32 bit register, since the value is known to be already
1041 sign extended. */
1042
1043int
1044se_register_operand (op, mode)
1045 rtx op;
1046 enum machine_mode mode;
1047{
1048 if (TARGET_64BIT
1049 && mode == DImode
1050 && GET_CODE (op) == SIGN_EXTEND
1051 && GET_MODE (op) == DImode
1052 && GET_MODE (XEXP (op, 0)) == SImode
1053 && register_operand (XEXP (op, 0), SImode))
1054 return 1;
1055
1056 return register_operand (op, mode);
1057}
1058
1059/* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1060 extend of a 32 bit register, since the value is known to be already
1061 sign extended. */
1062
1063int
1064se_reg_or_0_operand (op, mode)
1065 rtx op;
1066 enum machine_mode mode;
1067{
1068 if (TARGET_64BIT
1069 && mode == DImode
1070 && GET_CODE (op) == SIGN_EXTEND
1071 && GET_MODE (op) == DImode
1072 && GET_MODE (XEXP (op, 0)) == SImode
1073 && register_operand (XEXP (op, 0), SImode))
1074 return 1;
1075
1076 return reg_or_0_operand (op, mode);
1077}
1078
1079/* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1080 extend of a 32 bit register, since the value is known to be already
1081 sign extended. */
1082
1083int
1084se_uns_arith_operand (op, mode)
1085 rtx op;
1086 enum machine_mode mode;
1087{
1088 if (TARGET_64BIT
1089 && mode == DImode
1090 && GET_CODE (op) == SIGN_EXTEND
1091 && GET_MODE (op) == DImode
1092 && GET_MODE (XEXP (op, 0)) == SImode
1093 && register_operand (XEXP (op, 0), SImode))
1094 return 1;
1095
1096 return uns_arith_operand (op, mode);
1097}
1098
1099/* Like arith_operand, but when in 64 bit mode also accept a sign
1100 extend of a 32 bit register, since the value is known to be already
1101 sign extended. */
1102
1103int
1104se_arith_operand (op, mode)
1105 rtx op;
1106 enum machine_mode mode;
1107{
1108 if (TARGET_64BIT
1109 && mode == DImode
1110 && GET_CODE (op) == SIGN_EXTEND
1111 && GET_MODE (op) == DImode
1112 && GET_MODE (XEXP (op, 0)) == SImode
1113 && register_operand (XEXP (op, 0), SImode))
1114 return 1;
1115
1116 return arith_operand (op, mode);
1117}
1118
1119/* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1120 extend of a 32 bit register, since the value is known to be already
1121 sign extended. */
1122
1123int
1124se_nonmemory_operand (op, mode)
1125 rtx op;
1126 enum machine_mode mode;
1127{
1128 if (TARGET_64BIT
1129 && mode == DImode
1130 && GET_CODE (op) == SIGN_EXTEND
1131 && GET_MODE (op) == DImode
1132 && GET_MODE (XEXP (op, 0)) == SImode
1133 && register_operand (XEXP (op, 0), SImode))
1134 return 1;
1135
1136 return nonmemory_operand (op, mode);
1137}
1138
1139/* Like nonimmediate_operand, but when in 64 bit mode also accept a
1140 sign extend of a 32 bit register, since the value is known to be
1141 already sign extended. */
1142
1143int
1144se_nonimmediate_operand (op, mode)
1145 rtx op;
1146 enum machine_mode mode;
1147{
1148 if (TARGET_64BIT
1149 && mode == DImode
1150 && GET_CODE (op) == SIGN_EXTEND
1151 && GET_MODE (op) == DImode
1152 && GET_MODE (XEXP (op, 0)) == SImode
1153 && register_operand (XEXP (op, 0), SImode))
1154 return 1;
1155
1156 return nonimmediate_operand (op, mode);
1157}
1158
2bcb2ab3
GK		 1159/* Accept any operand that can appear in a mips16 constant table
1160 instruction. We can't use any of the standard operand functions
1161 because for these instructions we accept values that are not
1162 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1163
1164int
1165consttable_operand (op, mode)
1166 rtx op;
38831dfe 1167 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1168{
1169 return CONSTANT_P (op);
1170}
1171
f5963e61 1172/* Return nonzero if we split the address into high and low parts. */
910628b8
JW		 1173
1174/* ??? We should also handle reg+array somewhere. We get four
1175 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1176 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1177 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1178 out of the address, then we have 4 instructions to combine. Perhaps
1179 add a 3->2 define_split for combine. */
1180
1181/* ??? We could also split a CONST_INT here if it is a large_int().
1182 However, it doesn't seem to be very useful to have %hi(constant).
1183 We would be better off by doing the masking ourselves and then putting
1184 the explicit high part of the constant in the RTL. This will give better
1185 optimization. Also, %hi(constant) needs assembler changes to work.
1186 There is already a define_split that does this. */
1187
1188int
1189mips_check_split (address, mode)
1190 rtx address;
1191 enum machine_mode mode;
1192{
1193 /* ??? This is the same check used in simple_memory_operand.
1194 We use it here because LO_SUM is not offsettable. */
1195 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1196 return 0;
1197
1198 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1199 || (GET_CODE (address) == CONST
1200 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1201 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1202 || GET_CODE (address) == LABEL_REF)
50c0000c 1203 return 1;
910628b8 1204
50c0000c
RS		 1205 return 0;
1206}
cee98a59 1207\f
2bcb2ab3
GK		 1208/* We need a lot of little routines to check constant values on the
1209 mips16. These are used to figure out how long the instruction will
1210 be. It would be much better to do this using constraints, but
1211 there aren't nearly enough letters available. */
1212
1213static int
1214m16_check_op (op, low, high, mask)
1215 rtx op;
1216 int low;
1217 int high;
1218 int mask;
1219{
1220 return (GET_CODE (op) == CONST_INT
1221 && INTVAL (op) >= low
1222 && INTVAL (op) <= high
1223 && (INTVAL (op) & mask) == 0);
1224}
1225
1226int
1227m16_uimm3_b (op, mode)
1228 rtx op;
38831dfe 1229 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1230{
1231 return m16_check_op (op, 0x1, 0x8, 0);
1232}
1233
1234int
1235m16_simm4_1 (op, mode)
1236 rtx op;
38831dfe 1237 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1238{
1239 return m16_check_op (op, - 0x8, 0x7, 0);
1240}
1241
1242int
1243m16_nsimm4_1 (op, mode)
1244 rtx op;
38831dfe 1245 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1246{
1247 return m16_check_op (op, - 0x7, 0x8, 0);
1248}
1249
1250int
1251m16_simm5_1 (op, mode)
1252 rtx op;
38831dfe 1253 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1254{
1255 return m16_check_op (op, - 0x10, 0xf, 0);
1256}
1257
1258int
1259m16_nsimm5_1 (op, mode)
1260 rtx op;
38831dfe 1261 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1262{
1263 return m16_check_op (op, - 0xf, 0x10, 0);
1264}
1265
1266int
1267m16_uimm5_4 (op, mode)
1268 rtx op;
38831dfe 1269 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1270{
1271 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1272}
1273
1274int
1275m16_nuimm5_4 (op, mode)
1276 rtx op;
38831dfe 1277 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1278{
1279 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1280}
1281
1282int
1283m16_simm8_1 (op, mode)
1284 rtx op;
38831dfe 1285 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1286{
1287 return m16_check_op (op, - 0x80, 0x7f, 0);
1288}
1289
1290int
1291m16_nsimm8_1 (op, mode)
1292 rtx op;
38831dfe 1293 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1294{
1295 return m16_check_op (op, - 0x7f, 0x80, 0);
1296}
1297
1298int
1299m16_uimm8_1 (op, mode)
1300 rtx op;
38831dfe 1301 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1302{
1303 return m16_check_op (op, 0x0, 0xff, 0);
1304}
1305
1306int
1307m16_nuimm8_1 (op, mode)
1308 rtx op;
38831dfe 1309 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1310{
1311 return m16_check_op (op, - 0xff, 0x0, 0);
1312}
1313
1314int
1315m16_uimm8_m1_1 (op, mode)
1316 rtx op;
38831dfe 1317 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1318{
1319 return m16_check_op (op, - 0x1, 0xfe, 0);
1320}
1321
1322int
1323m16_uimm8_4 (op, mode)
1324 rtx op;
38831dfe 1325 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1326{
1327 return m16_check_op (op, 0x0, 0xff << 2, 3);
1328}
1329
1330int
1331m16_nuimm8_4 (op, mode)
1332 rtx op;
38831dfe 1333 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1334{
1335 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1336}
1337
1338int
1339m16_simm8_8 (op, mode)
1340 rtx op;
38831dfe 1341 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1342{
1343 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1344}
1345
1346int
1347m16_nsimm8_8 (op, mode)
1348 rtx op;
38831dfe 1349 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1350{
1351 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1352}
1353
1354/* References to the string table on the mips16 only use a small
1355 offset if the function is small. See the comment in the SYMBOL_REF
1356 case in simple_memory_operand. We can't check for LABEL_REF here,
1357 because the offset is always large if the label is before the
1358 referencing instruction. */
1359
1360int
1361m16_usym8_4 (op, mode)
1362 rtx op;
38831dfe 1363 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1364{
1365 if (GET_CODE (op) == SYMBOL_REF
1366 && SYMBOL_REF_FLAG (op)
1367 && current_frame_info.insns_len > 0
1368 && XSTR (op, 0)[0] == '*'
1369 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1370 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1371 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1372 < 4 * 0x100))
1373 {
1374 struct string_constant *l;
1375
1376 /* Make sure this symbol is on thelist of string constants to be
1377 output for this function. It is possible that it has already
1378 been output, in which case this requires a large offset. */
1379 for (l = string_constants; l != NULL; l = l->next)
1380 if (strcmp (l->label, XSTR (op, 0)) == 0)
1381 return 1;
1382 }
1383
1384 return 0;
1385}
1386
1387int
1388m16_usym5_4 (op, mode)
1389 rtx op;
38831dfe 1390 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1391{
1392 if (GET_CODE (op) == SYMBOL_REF
1393 && SYMBOL_REF_FLAG (op)
1394 && current_frame_info.insns_len > 0
1395 && XSTR (op, 0)[0] == '*'
1396 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1397 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1398 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1399 < 4 * 0x20))
1400 {
1401 struct string_constant *l;
1402
1403 /* Make sure this symbol is on thelist of string constants to be
1404 output for this function. It is possible that it has already
1405 been output, in which case this requires a large offset. */
1406 for (l = string_constants; l != NULL; l = l->next)
1407 if (strcmp (l->label, XSTR (op, 0)) == 0)
1408 return 1;
1409 }
1410
1411 return 0;
1412}
1413\f
85098019
JW		 1414/* Returns an operand string for the given instruction's delay slot,
1415 after updating filled delay slot statistics.
cee98a59
MM		 1416
1417 We assume that operands[0] is the target register that is set.
1418
1419 In order to check the next insn, most of this functionality is moved
1420 to FINAL_PRESCAN_INSN, and we just set the global variables that
1421 it needs. */
1422
85098019
JW		 1423/* ??? This function no longer does anything useful, because final_prescan_insn
1424 now will never emit a nop. */
1425
cee98a59
MM		 1426char *
1427mips_fill_delay_slot (ret, type, operands, cur_insn)
1428 char *ret; /* normal string to return */
1429 enum delay_type type; /* type of delay */
1430 rtx operands[]; /* operands to use */
1431 rtx cur_insn; /* current insn */
1432{
1433 register rtx set_reg;
1434 register enum machine_mode mode;
f5963e61 1435 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
cee98a59
MM		 1436 register int num_nops;
1437
34b650b3 1438 if (type == DELAY_LOAD || type == DELAY_FCMP)
cee98a59
MM		 1439 num_nops = 1;
1440
1441 else if (type == DELAY_HILO)
1442 num_nops = 2;
1443
1444 else
1445 num_nops = 0;
1446
1447 /* Make sure that we don't put nop's after labels. */
1448 next_insn = NEXT_INSN (cur_insn);
f5963e61 1449 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
cee98a59
MM		 1450 next_insn = NEXT_INSN (next_insn);
1451
1452 dslots_load_total += num_nops;
1453 if (TARGET_DEBUG_F_MODE
1454 || !optimize
1455 || type == DELAY_NONE
f5963e61
JL		 1456 || operands == 0
1457 || cur_insn == 0
1458 || next_insn == 0
cee98a59 1459 || GET_CODE (next_insn) == CODE_LABEL
f5963e61 1460 || (set_reg = operands[0]) == 0)
cee98a59
MM		 1461 {
1462 dslots_number_nops = 0;
f5963e61
JL		 1463 mips_load_reg = 0;
1464 mips_load_reg2 = 0;
1465 mips_load_reg3 = 0;
1466 mips_load_reg4 = 0;
cee98a59
MM		 1467 return ret;
1468 }
1469
1470 set_reg = operands[0];
f5963e61 1471 if (set_reg == 0)
cee98a59
MM		 1472 return ret;
1473
1474 while (GET_CODE (set_reg) == SUBREG)
1475 set_reg = SUBREG_REG (set_reg);
1476
1477 mode = GET_MODE (set_reg);
1478 dslots_number_nops = num_nops;
147255d8
JW		 1479 mips_load_reg = set_reg;
1480 if (GET_MODE_SIZE (mode)
b2a68403 1481 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
c5c76735 1482 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
147255d8
JW		 1483 else
1484 mips_load_reg2 = 0;
cee98a59
MM		 1485
1486 if (type == DELAY_HILO)
1487 {
c5c76735
JL		 1488 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1489 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
cee98a59
MM		 1490 }
1491 else
1492 {
1493 mips_load_reg3 = 0;
1494 mips_load_reg4 = 0;
1495 }
1496
cee98a59
MM		 1497 return ret;
1498}
1499
1500\f
f5963e61
JL		 1501/* Determine whether a memory reference takes one (based off of the GP
1502 pointer), two (normal), or three (label + reg) instructions, and bump the
1503 appropriate counter for -mstats. */
cee98a59
MM		 1504
1505void
1506mips_count_memory_refs (op, num)
1507 rtx op;
1508 int num;
1509{
1510 int additional = 0;
1511 int n_words = 0;
1512 rtx addr, plus0, plus1;
1513 enum rtx_code code0, code1;
1514 int looping;
1515
1516 if (TARGET_DEBUG_B_MODE)
1517 {
1518 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1519 debug_rtx (op);
1520 }
1521
1522 /* Skip MEM if passed, otherwise handle movsi of address. */
1523 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1524
f5963e61 1525 /* Loop, going through the address RTL. */
cee98a59
MM		 1526 do
1527 {
1528 looping = FALSE;
1529 switch (GET_CODE (addr))
1530 {
1531 case REG:
1532 case CONST_INT:
910628b8 1533 case LO_SUM:
cee98a59
MM		 1534 break;
1535
1536 case PLUS:
1537 plus0 = XEXP (addr, 0);
1538 plus1 = XEXP (addr, 1);
1539 code0 = GET_CODE (plus0);
1540 code1 = GET_CODE (plus1);
1541
1542 if (code0 == REG)
1543 {
1544 additional++;
1545 addr = plus1;
f5963e61 1546 looping = 1;
cee98a59
MM		 1547 continue;
1548 }
1549
1550 if (code0 == CONST_INT)
1551 {
1552 addr = plus1;
f5963e61 1553 looping = 1;
cee98a59
MM		 1554 continue;
1555 }
1556
1557 if (code1 == REG)
1558 {
1559 additional++;
1560 addr = plus0;
f5963e61 1561 looping = 1;
cee98a59
MM		 1562 continue;
1563 }
1564
1565 if (code1 == CONST_INT)
1566 {
1567 addr = plus0;
f5963e61 1568 looping = 1;
cee98a59
MM		 1569 continue;
1570 }
1571
1572 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1573 {
1574 addr = plus0;
f5963e61 1575 looping = 1;
cee98a59
MM		 1576 continue;
1577 }
1578
1579 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1580 {
1581 addr = plus1;
f5963e61 1582 looping = 1;
cee98a59
MM		 1583 continue;
1584 }
1585
1586 break;
1587
1588 case LABEL_REF:
1589 n_words = 2; /* always 2 words */
1590 break;
1591
1592 case CONST:
1593 addr = XEXP (addr, 0);
f5963e61 1594 looping = 1;
cee98a59
MM		 1595 continue;
1596
1597 case SYMBOL_REF:
1598 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1599 break;
f5963e61
JL		 1600
1601 default:
1602 break;
cee98a59
MM		 1603 }
1604 }
1605 while (looping);
1606
1607 if (n_words == 0)
1608 return;
1609
1610 n_words += additional;
1611 if (n_words > 3)
1612 n_words = 3;
1613
1614 num_refs[n_words-1] += num;
1615}
1616
1617\f
f5963e61
JL		 1618/* Return RTL for the offset from the current function to the argument.
1619
1620 ??? Which argument is this? */
92544bdf
ILT		 1621
1622rtx
1623embedded_pic_offset (x)
1624 rtx x;
1625{
1626 if (embedded_pic_fnaddr_rtx == NULL)
40f8d046
JW		 1627 {
1628 rtx seq;
1629
1630 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1631
abc95ed3 1632 /* Output code at function start to initialize the pseudo-reg. */
40f8d046
JW		 1633 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1634 inline functions, because it is called after RTL for the function
1635 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1636 does not get copied, and ends up not matching the rest of the RTL.
1637 This solution works, but means that we get unnecessary code to
abc95ed3 1638 initialize this value every time a function is inlined into another
40f8d046
JW		 1639 function. */
1640 start_sequence ();
1641 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1642 XEXP (DECL_RTL (current_function_decl), 0)));
1643 seq = gen_sequence ();
1644 end_sequence ();
1645 push_topmost_sequence ();
1646 emit_insn_after (seq, get_insns ());
1647 pop_topmost_sequence ();
1648 }
1649
c5c76735
JL		 1650 return
1651 gen_rtx_CONST (Pmode,
1652 gen_rtx_MINUS (Pmode, x,
1653 XEXP (DECL_RTL (current_function_decl), 0)));
92544bdf
ILT		 1654}
1655
cee98a59
MM		 1656/* Return the appropriate instructions to move one operand to another. */
1657
e2fe6aba 1658const char *
cee98a59
MM		 1659mips_move_1word (operands, insn, unsignedp)
1660 rtx operands[];
1661 rtx insn;
1662 int unsignedp;
1663{
e2fe6aba 1664 const char *ret = 0;
cee98a59
MM		 1665 rtx op0 = operands[0];
1666 rtx op1 = operands[1];
1667 enum rtx_code code0 = GET_CODE (op0);
1668 enum rtx_code code1 = GET_CODE (op1);
1669 enum machine_mode mode = GET_MODE (op0);
1670 int subreg_word0 = 0;
1671 int subreg_word1 = 0;
1672 enum delay_type delay = DELAY_NONE;
1673
1674 while (code0 == SUBREG)
1675 {
1676 subreg_word0 += SUBREG_WORD (op0);
1677 op0 = SUBREG_REG (op0);
1678 code0 = GET_CODE (op0);
1679 }
1680
1681 while (code1 == SUBREG)
1682 {
1683 subreg_word1 += SUBREG_WORD (op1);
1684 op1 = SUBREG_REG (op1);
1685 code1 = GET_CODE (op1);
1686 }
1687
b8eb88d0
ILT		 1688 /* For our purposes, a condition code mode is the same as SImode. */
1689 if (mode == CCmode)
1690 mode = SImode;
1691
cee98a59
MM		 1692 if (code0 == REG)
1693 {
1694 int regno0 = REGNO (op0) + subreg_word0;
1695
1696 if (code1 == REG)
1697 {
1698 int regno1 = REGNO (op1) + subreg_word1;
1699
1700 /* Just in case, don't do anything for assigning a register
1701 to itself, unless we are filling a delay slot. */
1702 if (regno0 == regno1 && set_nomacro == 0)
1703 ret = "";
1704
1705 else if (GP_REG_P (regno0))
1706 {
1707 if (GP_REG_P (regno1))
1708 ret = "move\t%0,%1";
1709
1710 else if (MD_REG_P (regno1))
1711 {
1712 delay = DELAY_HILO;
225b8835
ILT		 1713 if (regno1 != HILO_REGNUM)
1714 ret = "mf%1\t%0";
1715 else
1716 ret = "mflo\t%0";
cee98a59
MM		 1717 }
1718
b8eb88d0
ILT		 1719 else if (ST_REG_P (regno1) && mips_isa >= 4)
1720 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1721
cee98a59
MM		 1722 else
1723 {
1724 delay = DELAY_LOAD;
1725 if (FP_REG_P (regno1))
1726 ret = "mfc1\t%0,%1";
1727
b8eb88d0 1728 else if (regno1 == FPSW_REGNUM && mips_isa < 4)
cee98a59
MM		 1729 ret = "cfc1\t%0,$31";
1730 }
1731 }
1732
1733 else if (FP_REG_P (regno0))
1734 {
1735 if (GP_REG_P (regno1))
1736 {
1737 delay = DELAY_LOAD;
1738 ret = "mtc1\t%1,%0";
1739 }
1740
1741 if (FP_REG_P (regno1))
1742 ret = "mov.s\t%0,%1";
1743 }
1744
1745 else if (MD_REG_P (regno0))
1746 {
1747 if (GP_REG_P (regno1))
1748 {
1749 delay = DELAY_HILO;
2bcb2ab3 1750 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
225b8835 1751 ret = "mt%0\t%1";
cee98a59
MM		 1752 }
1753 }
1754
b8eb88d0 1755 else if (regno0 == FPSW_REGNUM && mips_isa < 4)
cee98a59
MM		 1756 {
1757 if (GP_REG_P (regno1))
1758 {
1759 delay = DELAY_LOAD;
1760 ret = "ctc1\t%0,$31";
1761 }
1762 }
1763 }
1764
1765 else if (code1 == MEM)
1766 {
1767 delay = DELAY_LOAD;
1768
1769 if (TARGET_STATS)
1770 mips_count_memory_refs (op1, 1);
1771
1772 if (GP_REG_P (regno0))
1773 {
1774 /* For loads, use the mode of the memory item, instead of the
1775 target, so zero/sign extend can use this code as well. */
1776 switch (GET_MODE (op1))
1777 {
147255d8
JW		 1778 default:
1779 break;
1780 case SFmode:
1781 ret = "lw\t%0,%1";
1782 break;
1783 case SImode:
b8eb88d0 1784 case CCmode:
147255d8
JW		 1785 ret = ((unsignedp && TARGET_64BIT)
1786 ? "lwu\t%0,%1"
1787 : "lw\t%0,%1");
1788 break;
1789 case HImode:
1790 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1791 break;
1792 case QImode:
1793 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1794 break;
cee98a59
MM		 1795 }
1796 }
1797
1798 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1799 ret = "l.s\t%0,%1";
1800
1801 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1802 {
38831dfe 1803 size_t i = strlen (ret);
cee98a59
MM		 1804 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1805 abort ();
1806
1807 sprintf (volatile_buffer, "%%{%s%%}", ret);
1808 ret = volatile_buffer;
1809 }
1810 }
1811
79438502
JW		 1812 else if (code1 == CONST_INT
1813 || (code1 == CONST_DOUBLE
1814 && GET_MODE (op1) == VOIDmode))
cee98a59 1815 {
79438502
JW		 1816 if (code1 == CONST_DOUBLE)
1817 {
1818 /* This can happen when storing constants into long long
1819 bitfields. Just store the least significant word of
1820 the value. */
1821 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1822 }
1823
2bcb2ab3 1824 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
cee98a59
MM		 1825 {
1826 if (GP_REG_P (regno0))
1827 ret = "move\t%0,%z1";
1828
1829 else if (FP_REG_P (regno0))
1830 {
1831 delay = DELAY_LOAD;
842eb20e 1832 ret = "mtc1\t%z1,%0";
cee98a59 1833 }
225b8835
ILT		 1834
1835 else if (MD_REG_P (regno0))
1836 {
1837 delay = DELAY_HILO;
1838 ret = "mt%0\t%.";
1839 }
cee98a59
MM		 1840 }
1841
1842 else if (GP_REG_P (regno0))
2bcb2ab3
GK		 1843 {
1844 /* Don't use X format, because that will give out of
1845 range numbers for 64 bit host and 32 bit target. */
1846 if (! TARGET_MIPS16)
1847 ret = "li\t%0,%1\t\t\t# %X1";
1848 else
1849 {
1850 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
1851 ret = "li\t%0,%1";
1852 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
1853 ret = "li\t%0,%n1\n\tneg\t%0";
1854 }
1855 }
cee98a59
MM		 1856 }
1857
1858 else if (code1 == CONST_DOUBLE && mode == SFmode)
1859 {
147255d8 1860 if (op1 == CONST0_RTX (SFmode))
cee98a59
MM		 1861 {
1862 if (GP_REG_P (regno0))
1863 ret = "move\t%0,%.";
1864
1865 else if (FP_REG_P (regno0))
1866 {
1867 delay = DELAY_LOAD;
1868 ret = "mtc1\t%.,%0";
1869 }
1870 }
1871
1872 else
1873 {
1874 delay = DELAY_LOAD;
1875 ret = "li.s\t%0,%1";
1876 }
1877 }
1878
1879 else if (code1 == LABEL_REF)
cee98a59
MM		 1880 {
1881 if (TARGET_STATS)
1882 mips_count_memory_refs (op1, 1);
1883
c7343333
MM		 1884 ret = "la\t%0,%a1";
1885 }
1886
1887 else if (code1 == SYMBOL_REF || code1 == CONST)
1888 {
c831afd5 1889 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
cee98a59 1890 {
c7343333
MM		 1891 rtx offset = const0_rtx;
1892
1893 if (GET_CODE (op1) == CONST)
1894 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1895
1896 if (GET_CODE (op1) == SYMBOL_REF)
1897 {
1898 operands[2] = HALF_PIC_PTR (op1);
1899
1900 if (TARGET_STATS)
1901 mips_count_memory_refs (operands[2], 1);
1902
1903 if (INTVAL (offset) == 0)
1904 {
1905 delay = DELAY_LOAD;
147255d8
JW		 1906 ret = (unsignedp && TARGET_64BIT
1907 ? "lwu\t%0,%2"
1908 : "lw\t%0,%2");
c7343333
MM		 1909 }
1910 else
1911 {
1912 dslots_load_total++;
1913 operands[3] = offset;
147255d8 1914 if (unsignedp && TARGET_64BIT)
f5963e61
JL		 1915 ret = (SMALL_INT (offset)
1916 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1917 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
147255d8 1918 else
f5963e61
JL		 1919 ret = (SMALL_INT (offset)
1920 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1921 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
c7343333
MM		 1922 }
1923 }
cee98a59 1924 }
2bcb2ab3
GK		 1925 else if (TARGET_MIPS16
1926 && code1 == CONST
1927 && GET_CODE (XEXP (op1, 0)) == REG
1928 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
1929 {
1930 /* This case arises on the mips16; see
1931 mips16_gp_pseudo_reg. */
1932 ret = "move\t%0,%+";
1933 }
1934 else if (TARGET_MIPS16
1935 && code1 == SYMBOL_REF
1936 && SYMBOL_REF_FLAG (op1)
1937 && (XSTR (op1, 0)[0] != '*'
1938 || strncmp (XSTR (op1, 0) + 1,
1939 LOCAL_LABEL_PREFIX,
1940 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
1941 {
1942 /* This can occur when reloading the address of a GP
1943 relative symbol on the mips16. */
1944 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
1945 }
cee98a59 1946 else
c7343333
MM		 1947 {
1948 if (TARGET_STATS)
1949 mips_count_memory_refs (op1, 1);
1950
1951 ret = "la\t%0,%a1";
1952 }
cee98a59
MM		 1953 }
1954
1955 else if (code1 == PLUS)
1956 {
1957 rtx add_op0 = XEXP (op1, 0);
1958 rtx add_op1 = XEXP (op1, 1);
1959
f5963e61
JL		 1960 if (GET_CODE (XEXP (op1, 1)) == REG
1961 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1962 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
cee98a59
MM		 1963
1964 operands[2] = add_op0;
1965 operands[3] = add_op1;
1966 ret = "add%:\t%0,%2,%3";
1967 }
910628b8
JW		 1968
1969 else if (code1 == HIGH)
1970 {
1971 operands[1] = XEXP (op1, 0);
1972 ret = "lui\t%0,%%hi(%1)";
1973 }
cee98a59
MM		 1974 }
1975
1976 else if (code0 == MEM)
1977 {
1978 if (TARGET_STATS)
1979 mips_count_memory_refs (op0, 1);
1980
1981 if (code1 == REG)
1982 {
1983 int regno1 = REGNO (op1) + subreg_word1;
1984
1985 if (GP_REG_P (regno1))
1986 {
1987 switch (mode)
1988 {
1989 case SFmode: ret = "sw\t%1,%0"; break;
1990 case SImode: ret = "sw\t%1,%0"; break;
1991 case HImode: ret = "sh\t%1,%0"; break;
1992 case QImode: ret = "sb\t%1,%0"; break;
f5963e61 1993 default: break;
cee98a59
MM		 1994 }
1995 }
1996
1997 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1998 ret = "s.s\t%1,%0";
1999 }
2000
2001 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2002 {
2003 switch (mode)
2004 {
2005 case SFmode: ret = "sw\t%z1,%0"; break;
2006 case SImode: ret = "sw\t%z1,%0"; break;
2007 case HImode: ret = "sh\t%z1,%0"; break;
2008 case QImode: ret = "sb\t%z1,%0"; break;
f5963e61 2009 default: break;
cee98a59
MM		 2010 }
2011 }
2012
147255d8 2013 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
cee98a59
MM		 2014 {
2015 switch (mode)
2016 {
2017 case SFmode: ret = "sw\t%.,%0"; break;
2018 case SImode: ret = "sw\t%.,%0"; break;
2019 case HImode: ret = "sh\t%.,%0"; break;
2020 case QImode: ret = "sb\t%.,%0"; break;
f5963e61 2021 default: break;
cee98a59
MM		 2022 }
2023 }
2024
f5963e61 2025 if (ret != 0 && MEM_VOLATILE_P (op0))
cee98a59 2026 {
38831dfe 2027 size_t i = strlen (ret);
f5963e61 2028
cee98a59
MM		 2029 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2030 abort ();
2031
2032 sprintf (volatile_buffer, "%%{%s%%}", ret);
2033 ret = volatile_buffer;
2034 }
2035 }
2036
f5963e61 2037 if (ret == 0)
cee98a59
MM		 2038 {
2039 abort_with_insn (insn, "Bad move");
2040 return 0;
2041 }
2042
2043 if (delay != DELAY_NONE)
2044 return mips_fill_delay_slot (ret, delay, operands, insn);
2045
2046 return ret;
2047}
2048
2049\f
2050/* Return the appropriate instructions to move 2 words */
2051
e2fe6aba 2052const char *
cee98a59
MM		 2053mips_move_2words (operands, insn)
2054 rtx operands[];
2055 rtx insn;
2056{
e2fe6aba 2057 const char *ret = 0;
cee98a59
MM		 2058 rtx op0 = operands[0];
2059 rtx op1 = operands[1];
2060 enum rtx_code code0 = GET_CODE (operands[0]);
2061 enum rtx_code code1 = GET_CODE (operands[1]);
2062 int subreg_word0 = 0;
2063 int subreg_word1 = 0;
2064 enum delay_type delay = DELAY_NONE;
2065
2066 while (code0 == SUBREG)
2067 {
2068 subreg_word0 += SUBREG_WORD (op0);
2069 op0 = SUBREG_REG (op0);
2070 code0 = GET_CODE (op0);
2071 }
2072
2a0b0bf5
ILT		 2073 if (code1 == SIGN_EXTEND)
2074 {
2075 op1 = XEXP (op1, 0);
2076 code1 = GET_CODE (op1);
2077 }
2078
cee98a59
MM		 2079 while (code1 == SUBREG)
2080 {
2081 subreg_word1 += SUBREG_WORD (op1);
2082 op1 = SUBREG_REG (op1);
2083 code1 = GET_CODE (op1);
2084 }
2085
2a0b0bf5
ILT		 2086 /* Sanity check. */
2087 if (GET_CODE (operands[1]) == SIGN_EXTEND
2088 && code1 != REG
27c38b75
JW		 2089 && code1 != CONST_INT
2090 /* The following three can happen as the result of a questionable
2091 cast. */
2092 && code1 != LABEL_REF
2093 && code1 != SYMBOL_REF
2094 && code1 != CONST)
2a0b0bf5
ILT		 2095 abort ();
2096
cee98a59
MM		 2097 if (code0 == REG)
2098 {
2099 int regno0 = REGNO (op0) + subreg_word0;
2100
2101 if (code1 == REG)
2102 {
2103 int regno1 = REGNO (op1) + subreg_word1;
2104
2105 /* Just in case, don't do anything for assigning a register
2106 to itself, unless we are filling a delay slot. */
2107 if (regno0 == regno1 && set_nomacro == 0)
2108 ret = "";
2109
2110 else if (FP_REG_P (regno0))
2111 {
2112 if (FP_REG_P (regno1))
2113 ret = "mov.d\t%0,%1";
2114
2115 else
2116 {
2117 delay = DELAY_LOAD;
f8151871 2118 if (TARGET_FLOAT64)
147255d8 2119 {
f8151871
JW		 2120 if (!TARGET_64BIT)
2121 abort_with_insn (insn, "Bad move");
f5963e61 2122
147255d8
JW		 2123#ifdef TARGET_FP_CALL_32
2124 if (FP_CALL_GP_REG_P (regno1))
2125 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2126 else
2127#endif
2128 ret = "dmtc1\t%1,%0";
2129 }
2130 else
2131 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
cee98a59
MM		 2132 }
2133 }
2134
2135 else if (FP_REG_P (regno1))
2136 {
2137 delay = DELAY_LOAD;
f8151871 2138 if (TARGET_FLOAT64)
147255d8 2139 {
f8151871
JW		 2140 if (!TARGET_64BIT)
2141 abort_with_insn (insn, "Bad move");
f5963e61 2142
147255d8
JW		 2143#ifdef TARGET_FP_CALL_32
2144 if (FP_CALL_GP_REG_P (regno0))
2145 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2146 else
2147#endif
2148 ret = "dmfc1\t%0,%1";
2149 }
2150 else
2151 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
cee98a59
MM		 2152 }
2153
2bcb2ab3 2154 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
cee98a59
MM		 2155 {
2156 delay = DELAY_HILO;
147255d8 2157 if (TARGET_64BIT)
225b8835
ILT		 2158 {
2159 if (regno0 != HILO_REGNUM)
2160 ret = "mt%0\t%1";
2161 else if (regno1 == 0)
2162 ret = "mtlo\t%.\n\tmthi\t%.";
2163 }
147255d8
JW		 2164 else
2165 ret = "mthi\t%M1\n\tmtlo\t%L1";
cee98a59
MM		 2166 }
2167
2168 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2169 {
2170 delay = DELAY_HILO;
147255d8 2171 if (TARGET_64BIT)
225b8835
ILT		 2172 {
2173 if (regno1 != HILO_REGNUM)
2174 ret = "mf%1\t%0";
2175 }
147255d8
JW		 2176 else
2177 ret = "mfhi\t%M0\n\tmflo\t%L0";
cee98a59
MM		 2178 }
2179
147255d8
JW		 2180 else if (TARGET_64BIT)
2181 ret = "move\t%0,%1";
2182
cee98a59
MM		 2183 else if (regno0 != (regno1+1))
2184 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2185
2186 else
2187 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2188 }
2189
2190 else if (code1 == CONST_DOUBLE)
2191 {
f8151871
JW		 2192 /* Move zero from $0 unless !TARGET_64BIT and recipient
2193 is 64-bit fp reg, in which case generate a constant. */
2194 if (op1 != CONST0_RTX (GET_MODE (op1))
2195 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
cee98a59
MM		 2196 {
2197 if (GET_MODE (op1) == DFmode)
2198 {
2199 delay = DELAY_LOAD;
f5963e61 2200
147255d8
JW		 2201#ifdef TARGET_FP_CALL_32
2202 if (FP_CALL_GP_REG_P (regno0))
f8151871
JW		 2203 {
2204 if (TARGET_FLOAT64 && !TARGET_64BIT)
2205 {
96abdcb1
ILT		 2206 split_double (op1, operands + 2, operands + 3);
2207 ret = "li\t%0,%2\n\tli\t%D0,%3";
f8151871
JW		 2208 }
2209 else
2210 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2211 }
147255d8
JW		 2212 else
2213#endif
2214 ret = "li.d\t%0,%1";
cee98a59
MM		 2215 }
2216
33563487 2217 else if (TARGET_64BIT)
2bcb2ab3
GK		 2218 {
2219 if (! TARGET_MIPS16)
2220 ret = "dli\t%0,%1";
2221 }
147255d8 2222
cee98a59
MM		 2223 else
2224 {
96abdcb1
ILT		 2225 split_double (op1, operands + 2, operands + 3);
2226 ret = "li\t%0,%2\n\tli\t%D0,%3";
cee98a59
MM		 2227 }
2228 }
2229
2230 else
2231 {
2232 if (GP_REG_P (regno0))
147255d8
JW		 2233 ret = (TARGET_64BIT
2234#ifdef TARGET_FP_CALL_32
2235 && ! FP_CALL_GP_REG_P (regno0)
2236#endif
f5963e61
JL		 2237 ? "move\t%0,%."
2238 : "move\t%0,%.\n\tmove\t%D0,%.");
cee98a59
MM		 2239
2240 else if (FP_REG_P (regno0))
2241 {
2242 delay = DELAY_LOAD;
f5963e61
JL		 2243 ret = (TARGET_64BIT
2244 ? "dmtc1\t%.,%0"
2245 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
cee98a59
MM		 2246 }
2247 }
2248 }
2249
2bcb2ab3 2250 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
cee98a59
MM		 2251 {
2252 if (GP_REG_P (regno0))
f5963e61
JL		 2253 ret = (TARGET_64BIT
2254 ? "move\t%0,%."
2255 : "move\t%0,%.\n\tmove\t%D0,%.");
2256
cee98a59
MM		 2257 else if (FP_REG_P (regno0))
2258 {
2259 delay = DELAY_LOAD;
f5963e61
JL		 2260 ret = (TARGET_64BIT
2261 ? "dmtc1\t%.,%0"
2262 : (TARGET_FLOAT64
2263 ? "li.d\t%0,%1"
2264 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
cee98a59 2265 }
225b8835
ILT		 2266 else if (MD_REG_P (regno0))
2267 {
2268 delay = DELAY_HILO;
f5963e61
JL		 2269 ret = (regno0 == HILO_REGNUM
2270 ? "mtlo\t%.\n\tmthi\t%."
2271 : "mt%0\t%.\n");
225b8835 2272 }
cee98a59
MM		 2273 }
2274
f5963e61
JL		 2275 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2276 && GP_REG_P (regno0))
cee98a59 2277 {
147255d8 2278 if (TARGET_64BIT)
33563487 2279 {
2bcb2ab3
GK		 2280 if (TARGET_MIPS16)
2281 {
2282 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2283 ret = "li\t%0,%1";
2284 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2285 ret = "li\t%0,%n1\n\tneg\t%0";
2286 }
2287 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2a0b0bf5
ILT		 2288 ret = "li\t%0,%1\t\t# %X1";
2289 else if (HOST_BITS_PER_WIDE_INT < 64)
33563487
JW		 2290 /* We can't use 'X' for negative numbers, because then we won't
2291 get the right value for the upper 32 bits. */
f5963e61
JL		 2292 ret = (INTVAL (op1) < 0
2293 ? "dli\t%0,%1\t\t\t# %X1"
33563487
JW		 2294 : "dli\t%0,%X1\t\t# %1");
2295 else
2296 /* We must use 'X', because otherwise LONG_MIN will print as
2297 a number that the assembler won't accept. */
2298 ret = "dli\t%0,%X1\t\t# %1";
2299 }
ade6c319 2300 else if (HOST_BITS_PER_WIDE_INT < 64)
147255d8
JW		 2301 {
2302 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2bcb2ab3
GK		 2303 if (TARGET_MIPS16)
2304 {
2305 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2306 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2307 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2308 {
2309 operands[2] = GEN_INT (1);
2310 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2311 }
2312 }
2313 else
2314 ret = "li\t%M0,%2\n\tli\t%L0,%1";
147255d8 2315 }
ade6c319
JW		 2316 else
2317 {
5107b750
JW		 2318 /* We use multiple shifts here, to avoid warnings about out
2319 of range shifts on 32 bit hosts. */
2320 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
f5963e61
JL		 2321 operands[1]
2322 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
ade6c319
JW		 2323 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2324 }
cee98a59
MM		 2325 }
2326
2327 else if (code1 == MEM)
2328 {
2329 delay = DELAY_LOAD;
2330
2331 if (TARGET_STATS)
2332 mips_count_memory_refs (op1, 2);
2333
2334 if (FP_REG_P (regno0))
2335 ret = "l.d\t%0,%1";
2336
147255d8
JW		 2337 else if (TARGET_64BIT)
2338 {
f5963e61 2339
147255d8
JW		 2340#ifdef TARGET_FP_CALL_32
2341 if (FP_CALL_GP_REG_P (regno0))
f5963e61
JL		 2342 ret = (double_memory_operand (op1, GET_MODE (op1))
2343 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2344 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
147255d8
JW		 2345 else
2346#endif
2347 ret = "ld\t%0,%1";
2348 }
2349
2bcb2ab3 2350 else if (double_memory_operand (op1, GET_MODE (op1)))
cee98a59
MM		 2351 {
2352 operands[2] = adj_offsettable_operand (op1, 4);
f5963e61
JL		 2353 ret = (reg_mentioned_p (op0, op1)
2354 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2355 : "lw\t%0,%1\n\tlw\t%D0,%2");
cee98a59
MM		 2356 }
2357
f5963e61 2358 if (ret != 0 && MEM_VOLATILE_P (op1))
cee98a59 2359 {
38831dfe 2360 size_t i = strlen (ret);
f5963e61 2361
cee98a59
MM		 2362 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2363 abort ();
2364
2365 sprintf (volatile_buffer, "%%{%s%%}", ret);
2366 ret = volatile_buffer;
2367 }
2368 }
147255d8 2369
3871c609 2370 else if (code1 == LABEL_REF)
147255d8 2371 {
33563487
JW		 2372 if (TARGET_STATS)
2373 mips_count_memory_refs (op1, 2);
2374
27c38b75
JW		 2375 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2376 /* We deliberately remove the 'a' from '%1', so that we don't
2377 have to add SIGN_EXTEND support to print_operand_address.
2378 print_operand will just call print_operand_address in this
2379 case, so there is no problem. */
2380 ret = "la\t%0,%1";
2381 else
2382 ret = "dla\t%0,%a1";
147255d8 2383 }
f5963e61 2384 else if (code1 == SYMBOL_REF || code1 == CONST)
3871c609
GK		 2385 {
2386 if (TARGET_MIPS16
2387 && code1 == CONST
2388 && GET_CODE (XEXP (op1, 0)) == REG
2389 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2390 {
2391 /* This case arises on the mips16; see
2392 mips16_gp_pseudo_reg. */
2393 ret = "move\t%0,%+";
2394 }
2395 else if (TARGET_MIPS16
2396 && code1 == SYMBOL_REF
2397 && SYMBOL_REF_FLAG (op1)
2398 && (XSTR (op1, 0)[0] != '*'
2399 || strncmp (XSTR (op1, 0) + 1,
2400 LOCAL_LABEL_PREFIX,
2401 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2402 {
2403 /* This can occur when reloading the address of a GP
2404 relative symbol on the mips16. */
2405 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2406 }
2407 else
2408 {
2409 if (TARGET_STATS)
2410 mips_count_memory_refs (op1, 2);
2411
2412 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2413 /* We deliberately remove the 'a' from '%1', so that we don't
2414 have to add SIGN_EXTEND support to print_operand_address.
2415 print_operand will just call print_operand_address in this
2416 case, so there is no problem. */
2417 ret = "la\t%0,%1";
2418 else
2419 ret = "dla\t%0,%a1";
2420 }
2421 }
cee98a59
MM		 2422 }
2423
2424 else if (code0 == MEM)
2425 {
2426 if (code1 == REG)
2427 {
2428 int regno1 = REGNO (op1) + subreg_word1;
2429
2430 if (FP_REG_P (regno1))
2431 ret = "s.d\t%1,%0";
2432
147255d8
JW		 2433 else if (TARGET_64BIT)
2434 {
f5963e61 2435
147255d8
JW		 2436#ifdef TARGET_FP_CALL_32
2437 if (FP_CALL_GP_REG_P (regno1))
2438 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2439 else
2440#endif
2441 ret = "sd\t%1,%0";
2442 }
2443
2bcb2ab3 2444 else if (double_memory_operand (op0, GET_MODE (op0)))
cee98a59
MM		 2445 {
2446 operands[2] = adj_offsettable_operand (op0, 4);
2447 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2448 }
2449 }
2450
147255d8
JW		 2451 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2452 || (code1 == CONST_DOUBLE
2453 && op1 == CONST0_RTX (GET_MODE (op1))))
2454 && (TARGET_64BIT
2bcb2ab3 2455 || double_memory_operand (op0, GET_MODE (op0))))
cee98a59 2456 {
147255d8 2457 if (TARGET_64BIT)
cee98a59
MM		 2458 ret = "sd\t%.,%0";
2459 else
2460 {
2461 operands[2] = adj_offsettable_operand (op0, 4);
2462 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2463 }
2464 }
2465
2466 if (TARGET_STATS)
2467 mips_count_memory_refs (op0, 2);
2468
f5963e61 2469 if (ret != 0 && MEM_VOLATILE_P (op0))
cee98a59 2470 {
38831dfe 2471 size_t i = strlen (ret);
f5963e61 2472
cee98a59
MM		 2473 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2474 abort ();
2475
2476 sprintf (volatile_buffer, "%%{%s%%}", ret);
2477 ret = volatile_buffer;
2478 }
2479 }
2480
f5963e61 2481 if (ret == 0)
cee98a59
MM		 2482 {
2483 abort_with_insn (insn, "Bad move");
2484 return 0;
2485 }
2486
2487 if (delay != DELAY_NONE)
2488 return mips_fill_delay_slot (ret, delay, operands, insn);
2489
2490 return ret;
2491}
cee98a59
MM		 2492\f
2493/* Provide the costs of an addressing mode that contains ADDR.
c831afd5 2494 If ADDR is not a valid address, its cost is irrelevant. */
cee98a59
MM		 2495
2496int
2497mips_address_cost (addr)
2498 rtx addr;
2499{
cee98a59
MM		 2500 switch (GET_CODE (addr))
2501 {
2502 case LO_SUM:
cee98a59
MM		 2503 return 1;
2504
2505 case LABEL_REF:
2506 return 2;
2507
2508 case CONST:
c831afd5
MM		 2509 {
2510 rtx offset = const0_rtx;
147255d8 2511 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
c831afd5
MM		 2512 if (GET_CODE (addr) == LABEL_REF)
2513 return 2;
cee98a59 2514
c831afd5
MM		 2515 if (GET_CODE (addr) != SYMBOL_REF)
2516 return 4;
cee98a59 2517
147255d8 2518 if (! SMALL_INT (offset))
c831afd5
MM		 2519 return 2;
2520 }
f5963e61
JL		 2521
2522 /* ... fall through ... */
cee98a59
MM		 2523
2524 case SYMBOL_REF:
2525 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2526
2527 case PLUS:
2528 {
2529 register rtx plus0 = XEXP (addr, 0);
2530 register rtx plus1 = XEXP (addr, 1);
2531
2532 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
f5963e61 2533 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
cee98a59
MM		 2534
2535 if (GET_CODE (plus0) != REG)
2536 break;
2537
2538 switch (GET_CODE (plus1))
2539 {
2540 case CONST_INT:
f5963e61 2541 return SMALL_INT (plus1) ? 1 : 2;
cee98a59
MM		 2542
2543 case CONST:
2544 case SYMBOL_REF:
2545 case LABEL_REF:
2546 case HIGH:
2547 case LO_SUM:
2548 return mips_address_cost (plus1) + 1;
f5963e61
JL		 2549
2550 default:
2551 break;
cee98a59
MM		 2552 }
2553 }
f5963e61
JL		 2554
2555 default:
2556 break;
cee98a59
MM		 2557 }
2558
2559 return 4;
2560}
2561
f5963e61 2562/* Return nonzero if X is an address which needs a temporary register when
508a48d1
JW		 2563 reloaded while generating PIC code. */
2564
2565int
2566pic_address_needs_scratch (x)
2567 rtx x;
2568{
2569 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2570 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2571 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2572 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2573 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2574 return 1;
2575
2576 return 0;
2577}
34b650b3
MM		 2578\f
2579/* Make normal rtx_code into something we can index from an array */
2580
2581static enum internal_test
2582map_test_to_internal_test (test_code)
2583 enum rtx_code test_code;
2584{
2585 enum internal_test test = ITEST_MAX;
2586
2587 switch (test_code)
2588 {
2589 case EQ: test = ITEST_EQ; break;
2590 case NE: test = ITEST_NE; break;
2591 case GT: test = ITEST_GT; break;
2592 case GE: test = ITEST_GE; break;
2593 case LT: test = ITEST_LT; break;
2594 case LE: test = ITEST_LE; break;
2595 case GTU: test = ITEST_GTU; break;
2596 case GEU: test = ITEST_GEU; break;
2597 case LTU: test = ITEST_LTU; break;
2598 case LEU: test = ITEST_LEU; break;
f5963e61 2599 default: break;
34b650b3
MM		 2600 }
2601
2602 return test;
2603}
2604
2605\f
2606/* Generate the code to compare two integer values. The return value is:
2607 (reg:SI xx) The pseudo register the comparison is in
f5963e61 2608 0 No register, generate a simple branch.
147255d8
JW		 2609
2610 ??? This is called with result nonzero by the Scond patterns in
2611 mips.md. These patterns are called with a target in the mode of
2612 the Scond instruction pattern. Since this must be a constant, we
2613 must use SImode. This means that if RESULT is non-zero, it will
2614 always be an SImode register, even if TARGET_64BIT is true. We
2615 cope with this by calling convert_move rather than emit_move_insn.
2616 This will sometimes lead to an unnecessary extension of the result;
2617 for example:
2618
2619 long long
2620 foo (long long i)
2621 {
2622 return i < 5;
2623 }
2624
2625 */
34b650b3
MM		 2626
2627rtx
2628gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2629 enum rtx_code test_code; /* relational test (EQ, etc) */
2630 rtx result; /* result to store comp. or 0 if branch */
2631 rtx cmp0; /* first operand to compare */
2632 rtx cmp1; /* second operand to compare */
2633 int *p_invert; /* NULL or ptr to hold whether branch needs */
2296cba3 2634 /* to reverse its test */
34b650b3 2635{
f5963e61
JL		 2636 struct cmp_info
2637 {
34b650b3
MM		 2638 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2639 int const_low; /* low bound of constant we can accept */
2640 int const_high; /* high bound of constant we can accept */
2641 int const_add; /* constant to add (convert LE -> LT) */
2642 int reverse_regs; /* reverse registers in test */
2643 int invert_const; /* != 0 if invert value if cmp1 is constant */
2644 int invert_reg; /* != 0 if invert value if cmp1 is register */
55f8a64c 2645 int unsignedp; /* != 0 for unsigned comparisons. */
34b650b3
MM		 2646 };
2647
2648 static struct cmp_info info[ (int)ITEST_MAX ] = {
2649
55f8a64c
RS		 2650 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2651 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2652 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2653 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2654 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2655 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2656 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2657 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2658 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2659 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
34b650b3
MM		 2660 };
2661
2662 enum internal_test test;
147255d8 2663 enum machine_mode mode;
34b650b3
MM		 2664 struct cmp_info *p_info;
2665 int branch_p;
2666 int eqne_p;
2667 int invert;
2668 rtx reg;
2669 rtx reg2;
2670
2671 test = map_test_to_internal_test (test_code);
2672 if (test == ITEST_MAX)
2673 abort ();
2674
f5963e61 2675 p_info = &info[(int) test];
34b650b3
MM		 2676 eqne_p = (p_info->test_code == XOR);
2677
147255d8
JW		 2678 mode = GET_MODE (cmp0);
2679 if (mode == VOIDmode)
2680 mode = GET_MODE (cmp1);
2681
34b650b3 2682 /* Eliminate simple branches */
f5963e61 2683 branch_p = (result == 0);
34b650b3
MM		 2684 if (branch_p)
2685 {
2686 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2687 {
2688 /* Comparisons against zero are simple branches */
2bcb2ab3
GK		 2689 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2690 && (! TARGET_MIPS16 || eqne_p))
f5963e61 2691 return 0;
34b650b3
MM		 2692
2693 /* Test for beq/bne. */
2bcb2ab3 2694 if (eqne_p && ! TARGET_MIPS16)
f5963e61 2695 return 0;
34b650b3
MM		 2696 }
2697
2296cba3 2698 /* allocate a pseudo to calculate the value in. */
147255d8 2699 result = gen_reg_rtx (mode);
34b650b3
MM		 2700 }
2701
2702 /* Make sure we can handle any constants given to us. */
2703 if (GET_CODE (cmp0) == CONST_INT)
147255d8 2704 cmp0 = force_reg (mode, cmp0);
34b650b3
MM		 2705
2706 if (GET_CODE (cmp1) == CONST_INT)
2707 {
85f5e2b6 2708 HOST_WIDE_INT value = INTVAL (cmp1);
f5963e61 2709
147255d8
JW		 2710 if (value < p_info->const_low
2711 || value > p_info->const_high
2712 /* ??? Why? And why wasn't the similar code below modified too? */
2713 || (TARGET_64BIT
2714 && HOST_BITS_PER_WIDE_INT < 64
2715 && p_info->const_add != 0
2716 && ((p_info->unsignedp
2717 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
e51712db 2718 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
147255d8
JW		 2719 : (value + p_info->const_add) > INTVAL (cmp1))
2720 != (p_info->const_add > 0))))
2721 cmp1 = force_reg (mode, cmp1);
34b650b3
MM		 2722 }
2723
2724 /* See if we need to invert the result. */
f5963e61
JL		 2725 invert = (GET_CODE (cmp1) == CONST_INT
2726 ? p_info->invert_const : p_info->invert_reg);
34b650b3
MM		 2727
2728 if (p_invert != (int *)0)
2729 {
2730 *p_invert = invert;
f5963e61 2731 invert = 0;
34b650b3
MM		 2732 }
2733
2734 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2735 Comparison between two registers, may involve switching operands. */
2736 if (GET_CODE (cmp1) == CONST_INT)
2737 {
2738 if (p_info->const_add != 0)
55f8a64c
RS		 2739 {
2740 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
f5963e61 2741
55f8a64c
RS		 2742 /* If modification of cmp1 caused overflow,
2743 we would get the wrong answer if we follow the usual path;
4db7b4ce 2744 thus, x > 0xffffffffU would turn into x > 0U. */
55f8a64c 2745 if ((p_info->unsignedp
e51712db
KG		 2746 ? (unsigned HOST_WIDE_INT) new >
2747 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
55f8a64c
RS		 2748 : new > INTVAL (cmp1))
2749 != (p_info->const_add > 0))
d40bb52a
RS		 2750 {
2751 /* This test is always true, but if INVERT is true then
2752 the result of the test needs to be inverted so 0 should
2753 be returned instead. */
2754 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2755 return result;
2756 }
55f8a64c
RS		 2757 else
2758 cmp1 = GEN_INT (new);
2759 }
34b650b3 2760 }
f5963e61 2761
34b650b3
MM		 2762 else if (p_info->reverse_regs)
2763 {
2764 rtx temp = cmp0;
2765 cmp0 = cmp1;
2766 cmp1 = temp;
2767 }
2768
34b650b3 2769 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
bbdb5552
MM		 2770 reg = cmp0;
2771 else
2772 {
147255d8
JW		 2773 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2774 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
bbdb5552
MM		 2775 }
2776
2777 if (test == ITEST_NE)
34b650b3 2778 {
2bcb2ab3
GK		 2779 if (! TARGET_MIPS16)
2780 {
2781 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
f5963e61 2782 invert = 0;
2bcb2ab3
GK		 2783 }
2784 else
2785 {
2786 reg2 = invert ? gen_reg_rtx (mode) : result;
2787 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2788 reg = reg2;
2789 }
34b650b3
MM		 2790 }
2791
bbdb5552 2792 else if (test == ITEST_EQ)
34b650b3 2793 {
f5963e61 2794 reg2 = invert ? gen_reg_rtx (mode) : result;
c5c76735 2795 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
34b650b3
MM		 2796 reg = reg2;
2797 }
2798
2799 if (invert)
2bcb2ab3
GK		 2800 {
2801 rtx one;
2802
2803 if (! TARGET_MIPS16)
2804 one = const1_rtx;
2805 else
2806 {
2807 /* The value is in $24. Copy it to another register, so
2808 that reload doesn't think it needs to store the $24 and
2809 the input to the XOR in the same location. */
2810 reg2 = gen_reg_rtx (mode);
2811 emit_move_insn (reg2, reg);
2812 reg = reg2;
2813 one = force_reg (mode, const1_rtx);
2814 }
2815 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
2816 }
34b650b3
MM		 2817
2818 return result;
2819}
cee98a59
MM		 2820\f
2821/* Emit the common code for doing conditional branches.
2822 operand[0] is the label to jump to.
147255d8 2823 The comparison operands are saved away by cmp{si,di,sf,df}. */
cee98a59
MM		 2824
2825void
2826gen_conditional_branch (operands, test_code)
2827 rtx operands[];
2828 enum rtx_code test_code;
2829{
b8eb88d0
ILT		 2830 enum cmp_type type = branch_type;
2831 rtx cmp0 = branch_cmp[0];
2832 rtx cmp1 = branch_cmp[1];
cee98a59 2833 enum machine_mode mode;
b8eb88d0
ILT		 2834 rtx reg;
2835 int invert;
2836 rtx label1, label2;
cee98a59 2837
147255d8 2838 switch (type)
cee98a59 2839 {
cee98a59 2840 case CMP_SI:
147255d8 2841 case CMP_DI:
b8eb88d0 2842 mode = type == CMP_SI ? SImode : DImode;
f5963e61 2843 invert = 0;
b8eb88d0 2844 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
f5963e61 2845
b8eb88d0 2846 if (reg)
cee98a59 2847 {
34b650b3
MM		 2848 cmp0 = reg;
2849 cmp1 = const0_rtx;
2850 test_code = NE;
cee98a59 2851 }
34b650b3 2852 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
f5963e61
JL		 2853 /* We don't want to build a comparison against a non-zero
2854 constant. */
2855 cmp1 = force_reg (mode, cmp1);
2856
cee98a59
MM		 2857 break;
2858
cee98a59 2859 case CMP_SF:
b8eb88d0
ILT		 2860 case CMP_DF:
2861 if (mips_isa < 4)
c5c76735 2862 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
b8eb88d0
ILT		 2863 else
2864 reg = gen_reg_rtx (CCmode);
2865
2866 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2867 0 in the instruction built below. The MIPS FPU handles
2868 inequality testing by testing for equality and looking for a
2869 false result. */
c5c76735
JL		 2870 emit_insn (gen_rtx_SET (VOIDmode, reg,
2871 gen_rtx (test_code == NE ? EQ : test_code,
2872 CCmode, cmp0, cmp1)));
2873
b8eb88d0
ILT		 2874 test_code = test_code == NE ? EQ : NE;
2875 mode = CCmode;
2876 cmp0 = reg;
2877 cmp1 = const0_rtx;
f5963e61 2878 invert = 0;
cee98a59 2879 break;
f5963e61
JL		 2880
2881 default:
2882 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
cee98a59 2883 }
85f5e2b6 2884
b8eb88d0
ILT		 2885 /* Generate the branch. */
2886
c5c76735 2887 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
b8eb88d0
ILT		 2888 label2 = pc_rtx;
2889
34b650b3
MM		 2890 if (invert)
2891 {
2892 label2 = label1;
2893 label1 = pc_rtx;
2894 }
2895
c5c76735
JL		 2896 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2897 gen_rtx_IF_THEN_ELSE (VOIDmode,
2898 gen_rtx (test_code, mode,
2899 cmp0, cmp1),
2900 label1, label2)));
b8eb88d0 2901}
34b650b3 2902
b8eb88d0
ILT		 2903/* Emit the common code for conditional moves. OPERANDS is the array
2904 of operands passed to the conditional move defined_expand. */
cee98a59 2905
b8eb88d0
ILT		 2906void
2907gen_conditional_move (operands)
2908 rtx *operands;
2909{
2910 rtx op0 = branch_cmp[0];
2911 rtx op1 = branch_cmp[1];
2912 enum machine_mode mode = GET_MODE (branch_cmp[0]);
2913 enum rtx_code cmp_code = GET_CODE (operands[1]);
2914 enum rtx_code move_code = NE;
2915 enum machine_mode op_mode = GET_MODE (operands[0]);
2916 enum machine_mode cmp_mode;
2917 rtx cmp_reg;
2918
2919 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2920 {
2921 switch (cmp_code)
2922 {
2923 case EQ:
2924 cmp_code = XOR;
2925 move_code = EQ;
2926 break;
2927 case NE:
2928 cmp_code = XOR;
2929 break;
2930 case LT:
2931 break;
2932 case GE:
2933 cmp_code = LT;
2934 move_code = EQ;
2935 break;
2936 case GT:
2937 cmp_code = LT;
2938 op0 = force_reg (mode, branch_cmp[1]);
2939 op1 = branch_cmp[0];
2940 break;
2941 case LE:
2942 cmp_code = LT;
2943 op0 = force_reg (mode, branch_cmp[1]);
2944 op1 = branch_cmp[0];
2945 move_code = EQ;
2946 break;
2947 case LTU:
2948 break;
2949 case GEU:
2950 cmp_code = LTU;
2951 move_code = EQ;
2952 break;
2953 case GTU:
2954 cmp_code = LTU;
2955 op0 = force_reg (mode, branch_cmp[1]);
2956 op1 = branch_cmp[0];
2957 break;
2958 case LEU:
2959 cmp_code = LTU;
2960 op0 = force_reg (mode, branch_cmp[1]);
2961 op1 = branch_cmp[0];
2962 move_code = EQ;
2963 break;
2964 default:
2965 abort ();
2966 }
2967 }
f5963e61
JL		 2968 else if (cmp_code == NE)
2969 cmp_code = EQ, move_code = EQ;
b8eb88d0
ILT		 2970
2971 if (mode == SImode || mode == DImode)
2972 cmp_mode = mode;
2973 else if (mode == SFmode || mode == DFmode)
2974 cmp_mode = CCmode;
2975 else
2976 abort ();
cee98a59 2977
b8eb88d0 2978 cmp_reg = gen_reg_rtx (cmp_mode);
c5c76735
JL		 2979 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
2980 gen_rtx (cmp_code, cmp_mode, op0, op1)));
2981
2982 emit_insn (gen_rtx_SET (op_mode, operands[0],
2983 gen_rtx_IF_THEN_ELSE (op_mode,
2984 gen_rtx (move_code, VOIDmode,
2985 cmp_reg,
2986 CONST0_RTX (SImode)),
2987 operands[2], operands[3])));
b8eb88d0 2988}
cee98a59 2989\f
f5963e61
JL		 2990/* Write a loop to move a constant number of bytes.
2991 Generate load/stores as follows:
cee98a59
MM		 2992
2993 do {
2994 temp1 = src[0];
2995 temp2 = src[1];
2996 ...
2997 temp<last> = src[MAX_MOVE_REGS-1];
cee98a59
MM		 2998 dest[0] = temp1;
2999 dest[1] = temp2;
3000 ...
3001 dest[MAX_MOVE_REGS-1] = temp<last>;
842eb20e 3002 src += MAX_MOVE_REGS;
cee98a59
MM		 3003 dest += MAX_MOVE_REGS;
3004 } while (src != final);
3005
3006 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3007 registers are needed.
3008
3009 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3010 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3011 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3012
3013#define MAX_MOVE_REGS 4
3014#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3015
3016static void
7cabe29a 3017block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
cee98a59
MM		 3018 rtx dest_reg; /* register holding destination address */
3019 rtx src_reg; /* register holding source address */
3020 int bytes; /* # bytes to move */
3021 int align; /* alignment */
7cabe29a 3022 rtx orig_dest; /* original dest for change_address */
842eb20e 3023 rtx orig_src; /* original source for making a reg note */
cee98a59 3024{
f5963e61
JL		 3025 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3026 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3027 rtx align_rtx = GEN_INT (align);
cee98a59
MM		 3028 rtx label;
3029 rtx final_src;
3030 rtx bytes_rtx;
cee98a59 3031 int leftover;
cee98a59 3032
f5963e61 3033 if (bytes < 2 * MAX_MOVE_BYTES)
cee98a59
MM		 3034 abort ();
3035
3036 leftover = bytes % MAX_MOVE_BYTES;
3037 bytes -= leftover;
3038
3039 label = gen_label_rtx ();
3040 final_src = gen_reg_rtx (Pmode);
0fb5ac6f 3041 bytes_rtx = GEN_INT (bytes);
cee98a59
MM		 3042
3043 if (bytes > 0x7fff)
3044 {
1eeed24e 3045 if (Pmode == DImode)
147255d8
JW		 3046 {
3047 emit_insn (gen_movdi (final_src, bytes_rtx));
3048 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3049 }
3050 else
3051 {
3052 emit_insn (gen_movsi (final_src, bytes_rtx));
3053 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3054 }
cee98a59
MM		 3055 }
3056 else
147255d8 3057 {
1eeed24e 3058 if (Pmode == DImode)
147255d8
JW		 3059 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3060 else
3061 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3062 }
cee98a59
MM		 3063
3064 emit_label (label);
3065
0fb5ac6f 3066 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
842eb20e 3067 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
f5963e61 3068
1eeed24e 3069 if (Pmode == DImode)
147255d8
JW		 3070 {
3071 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3072 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3073 emit_insn (gen_cmpdi (src_reg, final_src));
3074 }
3075 else
3076 {
3077 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3078 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3079 emit_insn (gen_cmpsi (src_reg, final_src));
3080 }
f5963e61 3081
cee98a59
MM		 3082 emit_jump_insn (gen_bne (label));
3083
3084 if (leftover)
f5963e61 3085 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
842eb20e 3086 align_rtx));
cee98a59 3087}
cee98a59
MM		 3088\f
3089/* Use a library function to move some bytes. */
3090
3091static void
3092block_move_call (dest_reg, src_reg, bytes_rtx)
3093 rtx dest_reg;
3094 rtx src_reg;
3095 rtx bytes_rtx;
3096{
147255d8
JW		 3097 /* We want to pass the size as Pmode, which will normally be SImode
3098 but will be DImode if we are using 64 bit longs and pointers. */
3099 if (GET_MODE (bytes_rtx) != VOIDmode
3100 && GET_MODE (bytes_rtx) != Pmode)
f5963e61 3101 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
147255d8 3102
cee98a59 3103#ifdef TARGET_MEM_FUNCTIONS
c5c76735 3104 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
f5963e61 3105 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
e24b8776
JW		 3106 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3107 TREE_UNSIGNED (sizetype)),
3108 TYPE_MODE (sizetype));
cee98a59 3109#else
c5c76735 3110 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
f5963e61
JL		 3111 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3112 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3113 TREE_UNSIGNED (integer_type_node)),
e24b8776 3114 TYPE_MODE (integer_type_node));
cee98a59
MM		 3115#endif
3116}
cee98a59
MM		 3117\f
3118/* Expand string/block move operations.
3119
3120 operands[0] is the pointer to the destination.
3121 operands[1] is the pointer to the source.
3122 operands[2] is the number of bytes to move.
3123 operands[3] is the alignment. */
3124
3125void
3126expand_block_move (operands)
3127 rtx operands[];
3128{
3129 rtx bytes_rtx = operands[2];
842eb20e 3130 rtx align_rtx = operands[3];
f5963e61
JL		 3131 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3132 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3133 int align = INTVAL (align_rtx);
842eb20e 3134 rtx orig_src = operands[1];
7cabe29a 3135 rtx orig_dest = operands[0];
cee98a59
MM		 3136 rtx src_reg;
3137 rtx dest_reg;
3138
3139 if (constp && bytes <= 0)
3140 return;
3141
842eb20e
MM		 3142 if (align > UNITS_PER_WORD)
3143 align = UNITS_PER_WORD;
3144
cee98a59 3145 /* Move the address into scratch registers. */
7cabe29a 3146 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
842eb20e 3147 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
cee98a59
MM		 3148
3149 if (TARGET_MEMCPY)
3150 block_move_call (dest_reg, src_reg, bytes_rtx);
3151
2e245dac
JL		 3152 else if (constp && bytes <= 2 * MAX_MOVE_BYTES
3153 && align == UNITS_PER_WORD)
3154 move_by_pieces (orig_dest, orig_src, bytes, align);
3155
f5963e61 3156 else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
7cabe29a
JW		 3157 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3158 dest_reg),
ff18b63b
RK		 3159 change_address (orig_src, BLKmode,
3160 src_reg),
842eb20e 3161 bytes_rtx, align_rtx));
cee98a59
MM		 3162
3163 else if (constp && align >= UNITS_PER_WORD && optimize)
7cabe29a 3164 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
cee98a59
MM		 3165
3166 else if (constp && optimize)
3167 {
3168 /* If the alignment is not word aligned, generate a test at
3169 runtime, to see whether things wound up aligned, and we
3170 can use the faster lw/sw instead ulw/usw. */
3171
f5963e61 3172 rtx temp = gen_reg_rtx (Pmode);
cee98a59 3173 rtx aligned_label = gen_label_rtx ();
f5963e61
JL		 3174 rtx join_label = gen_label_rtx ();
3175 int leftover = bytes % MAX_MOVE_BYTES;
cee98a59
MM		 3176
3177 bytes -= leftover;
3178
1eeed24e 3179 if (Pmode == DImode)
147255d8
JW		 3180 {
3181 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
f5963e61 3182 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
147255d8
JW		 3183 emit_insn (gen_cmpdi (temp, const0_rtx));
3184 }
3185 else
3186 {
3187 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
f5963e61 3188 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
147255d8
JW		 3189 emit_insn (gen_cmpsi (temp, const0_rtx));
3190 }
f5963e61 3191
cee98a59
MM		 3192 emit_jump_insn (gen_beq (aligned_label));
3193
3194 /* Unaligned loop. */
7cabe29a 3195 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
cee98a59
MM		 3196 emit_jump_insn (gen_jump (join_label));
3197 emit_barrier ();
3198
3199 /* Aligned loop. */
3200 emit_label (aligned_label);
7cabe29a
JW		 3201 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3202 orig_src);
cee98a59
MM		 3203 emit_label (join_label);
3204
3205 /* Bytes at the end of the loop. */
3206 if (leftover)
7cabe29a
JW		 3207 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3208 dest_reg),
3209 change_address (orig_src, BLKmode,
3210 src_reg),
3211 GEN_INT (leftover),
3212 GEN_INT (align)));
cee98a59
MM		 3213 }
3214
3215 else
3216 block_move_call (dest_reg, src_reg, bytes_rtx);
3217}
842eb20e
MM		 3218\f
3219/* Emit load/stores for a small constant block_move.
3220
3221 operands[0] is the memory address of the destination.
3222 operands[1] is the memory address of the source.
3223 operands[2] is the number of bytes to move.
3224 operands[3] is the alignment.
3225 operands[4] is a temp register.
3226 operands[5] is a temp register.
c4b9be8e
MM		 3227 ...
3228 operands[3+num_regs] is the last temp register.
3229
3230 The block move type can be one of the following:
3231 BLOCK_MOVE_NORMAL Do all of the block move.
3232 BLOCK_MOVE_NOT_LAST Do all but the last store.
3233 BLOCK_MOVE_LAST Do just the last store. */
842eb20e 3234
e2fe6aba 3235const char *
c4b9be8e 3236output_block_move (insn, operands, num_regs, move_type)
842eb20e
MM		 3237 rtx insn;
3238 rtx operands[];
3239 int num_regs;
c4b9be8e 3240 enum block_move_type move_type;
842eb20e 3241{
f5963e61
JL		 3242 rtx dest_reg = XEXP (operands[0], 0);
3243 rtx src_reg = XEXP (operands[1], 0);
3244 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3245 int align = INTVAL (operands[3]);
3246 int num = 0;
3247 int offset = 0;
3248 int use_lwl_lwr = 0;
3249 int last_operand = num_regs + 4;
3250 int safe_regs = 4;
842eb20e
MM		 3251 int i;
3252 rtx xoperands[10];
3253
3254 struct {
e2fe6aba
KG		 3255 const char *load; /* load insn without nop */
3256 const char *load_nop; /* load insn with trailing nop */
3257 const char *store; /* store insn */
3258 const char *final; /* if last_store used: NULL or swr */
3259 const char *last_store; /* last store instruction */
842eb20e
MM		 3260 int offset; /* current offset */
3261 enum machine_mode mode; /* mode to use on (MEM) */
3262 } load_store[4];
3263
f5963e61 3264 /* ??? Detect a bug in GCC, where it can give us a register
4bb89a8e
MM		 3265 the same as one of the addressing registers and reduce
3266 the number of registers available. */
3267 for (i = 4;
f5963e61 3268 i < last_operand
e51712db 3269 && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0]));
4bb89a8e 3270 i++)
f5963e61
JL		 3271 if (! reg_mentioned_p (operands[i], operands[0])
3272 && ! reg_mentioned_p (operands[i], operands[1]))
3273 xoperands[safe_regs++] = operands[i];
4bb89a8e
MM		 3274
3275 if (safe_regs < last_operand)
3276 {
3277 xoperands[0] = operands[0];
3278 xoperands[1] = operands[1];
3279 xoperands[2] = operands[2];
3280 xoperands[3] = operands[3];
f5963e61 3281 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
c6f3187f
RS		 3282 }
3283
842eb20e
MM		 3284 /* If we are given global or static addresses, and we would be
3285 emitting a few instructions, try to save time by using a
3286 temporary register for the pointer. */
a8136932
JW		 3287 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3288 an ldl/ldr instruction pair. We play it safe, and always move
3289 constant addresses into registers when generating N32/N64 code, just
3290 in case we might emit an unaligned load instruction. */
f5963e61 3291 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
a8136932 3292 || mips_abi == ABI_N32 || mips_abi == ABI_64))
842eb20e
MM		 3293 {
3294 if (CONSTANT_P (src_reg))
3295 {
4e09f580
MM		 3296 if (TARGET_STATS)
3297 mips_count_memory_refs (operands[1], 1);
3298
f5963e61 3299 src_reg = operands[3 + num_regs--];
c4b9be8e
MM		 3300 if (move_type != BLOCK_MOVE_LAST)
3301 {
3302 xoperands[1] = operands[1];
3303 xoperands[0] = src_reg;
33563487
JW		 3304 if (Pmode == DImode)
3305 output_asm_insn ("dla\t%0,%1", xoperands);
3306 else
3307 output_asm_insn ("la\t%0,%1", xoperands);
c4b9be8e 3308 }
842eb20e
MM		 3309 }
3310
3311 if (CONSTANT_P (dest_reg))
3312 {
4e09f580
MM		 3313 if (TARGET_STATS)
3314 mips_count_memory_refs (operands[0], 1);
3315
f5963e61 3316 dest_reg = operands[3 + num_regs--];
c4b9be8e
MM		 3317 if (move_type != BLOCK_MOVE_LAST)
3318 {
3319 xoperands[1] = operands[0];
3320 xoperands[0] = dest_reg;
33563487
JW		 3321 if (Pmode == DImode)
3322 output_asm_insn ("dla\t%0,%1", xoperands);
3323 else
3324 output_asm_insn ("la\t%0,%1", xoperands);
c4b9be8e 3325 }
842eb20e
MM		 3326 }
3327 }
3328
910628b8
JW		 3329 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3330 are not offsettable, however, offsettable_address_p says they are
3331 offsettable. I think this is a bug in offsettable_address_p.
3332 For expediency, we fix this by just loading the address into a register
3333 if we happen to get one. */
3334
3335 if (GET_CODE (src_reg) == LO_SUM)
3336 {
f5963e61 3337 src_reg = operands[3 + num_regs--];
910628b8
JW		 3338 if (move_type != BLOCK_MOVE_LAST)
3339 {
3340 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3341 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3342 xoperands[0] = src_reg;
3343 if (Pmode == DImode)
3344 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3345 else
3346 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3347 }
3348 }
3349
3350 if (GET_CODE (dest_reg) == LO_SUM)
3351 {
f5963e61 3352 dest_reg = operands[3 + num_regs--];
910628b8
JW		 3353 if (move_type != BLOCK_MOVE_LAST)
3354 {
3355 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3356 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3357 xoperands[0] = dest_reg;
3358 if (Pmode == DImode)
3359 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3360 else
3361 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3362 }
3363 }
3364
e51712db 3365 if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0])))
f5963e61 3366 num_regs = sizeof (load_store) / sizeof (load_store[0]);
842eb20e
MM		 3367
3368 else if (num_regs < 1)
f5963e61
JL		 3369 abort_with_insn (insn,
3370 "Cannot do block move, not enough scratch registers");
842eb20e 3371
842eb20e
MM		 3372 while (bytes > 0)
3373 {
3374 load_store[num].offset = offset;
3375
147255d8
JW		 3376 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3377 {
f5963e61
JL		 3378 load_store[num].load = "ld\t%0,%1";
3379 load_store[num].load_nop = "ld\t%0,%1%#";
3380 load_store[num].store = "sd\t%0,%1";
147255d8 3381 load_store[num].last_store = "sd\t%0,%1";
f5963e61
JL		 3382 load_store[num].final = 0;
3383 load_store[num].mode = DImode;
147255d8
JW		 3384 offset += 8;
3385 bytes -= 8;
3386 }
3387
2bcb2ab3
GK		 3388 /* ??? Fails because of a MIPS assembler bug? */
3389 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
147255d8 3390 {
96abdcb1
ILT		 3391 if (BYTES_BIG_ENDIAN)
3392 {
f5963e61
JL		 3393 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3394 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3395 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
96abdcb1 3396 load_store[num].last_store = "sdr\t%0,%2";
f5963e61 3397 load_store[num].final = "sdl\t%0,%1";
96abdcb1
ILT		 3398 }
3399 else
3400 {
f5963e61
JL		 3401 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3402 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3403 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
96abdcb1 3404 load_store[num].last_store = "sdr\t%0,%1";
f5963e61 3405 load_store[num].final = "sdl\t%0,%2";
96abdcb1 3406 }
f5963e61 3407
147255d8
JW		 3408 load_store[num].mode = DImode;
3409 offset += 8;
3410 bytes -= 8;
f5963e61 3411 use_lwl_lwr = 1;
147255d8
JW		 3412 }
3413
3414 else if (bytes >= 4 && align >= 4)
842eb20e 3415 {
f5963e61
JL		 3416 load_store[num].load = "lw\t%0,%1";
3417 load_store[num].load_nop = "lw\t%0,%1%#";
3418 load_store[num].store = "sw\t%0,%1";
c4b9be8e 3419 load_store[num].last_store = "sw\t%0,%1";
f5963e61
JL		 3420 load_store[num].final = 0;
3421 load_store[num].mode = SImode;
147255d8
JW		 3422 offset += 4;
3423 bytes -= 4;
842eb20e
MM		 3424 }
3425
2bcb2ab3 3426 else if (bytes >= 4 && ! TARGET_MIPS16)
0cebb05d 3427 {
96abdcb1
ILT		 3428 if (BYTES_BIG_ENDIAN)
3429 {
f5963e61
JL		 3430 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3431 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3432 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
96abdcb1 3433 load_store[num].last_store = "swr\t%0,%2";
f5963e61 3434 load_store[num].final = "swl\t%0,%1";
96abdcb1
ILT		 3435 }
3436 else
3437 {
f5963e61
JL		 3438 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3439 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3440 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
96abdcb1 3441 load_store[num].last_store = "swr\t%0,%1";
f5963e61 3442 load_store[num].final = "swl\t%0,%2";
96abdcb1 3443 }
f5963e61 3444
0cebb05d 3445 load_store[num].mode = SImode;
147255d8
JW		 3446 offset += 4;
3447 bytes -= 4;
f5963e61 3448 use_lwl_lwr = 1;
0cebb05d
MM		 3449 }
3450
147255d8 3451 else if (bytes >= 2 && align >= 2)
842eb20e 3452 {
f5963e61
JL		 3453 load_store[num].load = "lh\t%0,%1";
3454 load_store[num].load_nop = "lh\t%0,%1%#";
3455 load_store[num].store = "sh\t%0,%1";
c4b9be8e 3456 load_store[num].last_store = "sh\t%0,%1";
f5963e61
JL		 3457 load_store[num].final = 0;
3458 load_store[num].mode = HImode;
147255d8
JW		 3459 offset += 2;
3460 bytes -= 2;
842eb20e 3461 }
842eb20e
MM		 3462 else
3463 {
f5963e61
JL		 3464 load_store[num].load = "lb\t%0,%1";
3465 load_store[num].load_nop = "lb\t%0,%1%#";
3466 load_store[num].store = "sb\t%0,%1";
c4b9be8e 3467 load_store[num].last_store = "sb\t%0,%1";
f5963e61
JL		 3468 load_store[num].final = 0;
3469 load_store[num].mode = QImode;
842eb20e
MM		 3470 offset++;
3471 bytes--;
3472 }
3473
c4b9be8e 3474 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4e09f580 3475 {
c4b9be8e
MM		 3476 dslots_load_total++;
3477 dslots_load_filled++;
3478
4e09f580
MM		 3479 if (CONSTANT_P (src_reg))
3480 mips_count_memory_refs (src_reg, 1);
3481
3482 if (CONSTANT_P (dest_reg))
3483 mips_count_memory_refs (dest_reg, 1);
3484 }
3485
842eb20e
MM		 3486 /* Emit load/stores now if we have run out of registers or are
3487 at the end of the move. */
3488
4e09f580 3489 if (++num == num_regs || bytes == 0)
842eb20e
MM		 3490 {
3491 /* If only load/store, we need a NOP after the load. */
3492 if (num == 1)
4e09f580
MM		 3493 {
3494 load_store[0].load = load_store[0].load_nop;
c4b9be8e
MM		 3495 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3496 dslots_load_filled--;
4e09f580 3497 }
842eb20e 3498
c4b9be8e 3499 if (move_type != BLOCK_MOVE_LAST)
842eb20e 3500 {
c4b9be8e
MM		 3501 for (i = 0; i < num; i++)
3502 {
3503 int offset;
0cebb05d 3504
f5963e61 3505 if (!operands[i + 4])
c4b9be8e 3506 abort ();
842eb20e 3507
f5963e61 3508 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
c5c76735
JL		 3509 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3510 REGNO (operands[i + 4]));
842eb20e 3511
c4b9be8e 3512 offset = load_store[i].offset;
f5963e61 3513 xoperands[0] = operands[i + 4];
c5c76735
JL		 3514 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3515 plus_constant (src_reg, offset));
0cebb05d 3516
c4b9be8e 3517 if (use_lwl_lwr)
147255d8 3518 {
f5963e61
JL		 3519 int extra_offset
3520 = GET_MODE_SIZE (load_store[i].mode) - 1;
3521
c5c76735
JL		 3522 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3523 plus_constant (src_reg,
3524 extra_offset
3525 + offset));
147255d8 3526 }
0cebb05d 3527
c4b9be8e
MM		 3528 output_asm_insn (load_store[i].load, xoperands);
3529 }
842eb20e
MM		 3530 }
3531
3532 for (i = 0; i < num; i++)
3533 {
c4b9be8e 3534 int last_p = (i == num-1 && bytes == 0);
0cebb05d 3535 int offset = load_store[i].offset;
c4b9be8e 3536
f5963e61 3537 xoperands[0] = operands[i + 4];
c5c76735
JL		 3538 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3539 plus_constant (dest_reg, offset));
0cebb05d
MM		 3540
3541
3542 if (use_lwl_lwr)
147255d8 3543 {
f5963e61 3544 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
c5c76735
JL		 3545 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3546 plus_constant (dest_reg,
3547 extra_offset
3548 + offset));
147255d8 3549 }
0cebb05d 3550
c4b9be8e
MM		 3551 if (move_type == BLOCK_MOVE_NORMAL)
3552 output_asm_insn (load_store[i].store, xoperands);
3553
3554 else if (move_type == BLOCK_MOVE_NOT_LAST)
3555 {
3556 if (!last_p)
3557 output_asm_insn (load_store[i].store, xoperands);
3558
f5963e61 3559 else if (load_store[i].final != 0)
c4b9be8e
MM		 3560 output_asm_insn (load_store[i].final, xoperands);
3561 }
3562
3563 else if (last_p)
3564 output_asm_insn (load_store[i].last_store, xoperands);
842eb20e
MM		 3565 }
3566
3567 num = 0; /* reset load_store */
f5963e61 3568 use_lwl_lwr = 0;
842eb20e
MM		 3569 }
3570 }
3571
842eb20e
MM		 3572 return "";
3573}
cee98a59
MM		 3574\f
3575/* Argument support functions. */
3576
3577/* Initialize CUMULATIVE_ARGS for a function. */
3578
3579void
3580init_cumulative_args (cum, fntype, libname)
38831dfe
KG		 3581 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3582 tree fntype; /* tree ptr for function decl */
3583 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
cee98a59 3584{
3f1f8d8c 3585 static CUMULATIVE_ARGS zero_cum;
cee98a59
MM		 3586 tree param, next_param;
3587
3588 if (TARGET_DEBUG_E_MODE)
6cb6c3b3 3589 {
f5963e61
JL		 3590 fprintf (stderr,
3591 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3592
6cb6c3b3
MM		 3593 if (!fntype)
3594 fputc ('\n', stderr);
3595
3596 else
3597 {
3598 tree ret_type = TREE_TYPE (fntype);
3599 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
f5963e61
JL		 3600 tree_code_name[(int)TREE_CODE (fntype)],
3601 tree_code_name[(int)TREE_CODE (ret_type)]);
6cb6c3b3
MM		 3602 }
3603 }
cee98a59 3604
3f1f8d8c 3605 *cum = zero_cum;
cee98a59
MM		 3606
3607 /* Determine if this function has variable arguments. This is
3608 indicated by the last argument being 'void_type_mode' if there
3609 are no variable arguments. The standard MIPS calling sequence
f5963e61 3610 passes all arguments in the general purpose registers in this case. */
cee98a59 3611
f5963e61
JL		 3612 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3613 param != 0; param = next_param)
cee98a59
MM		 3614 {
3615 next_param = TREE_CHAIN (param);
f5963e61 3616 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
cee98a59
MM		 3617 cum->gp_reg_found = 1;
3618 }
cee98a59
MM		 3619}
3620
3621/* Advance the argument to the next argument position. */
3622
3623void
3624function_arg_advance (cum, mode, type, named)
3625 CUMULATIVE_ARGS *cum; /* current arg information */
3626 enum machine_mode mode; /* current arg mode */
3627 tree type; /* type of the argument or 0 if lib support */
0fb5ac6f 3628 int named; /* whether or not the argument was named */
cee98a59
MM		 3629{
3630 if (TARGET_DEBUG_E_MODE)
38831dfe
KG		 3631 {
3632 fprintf (stderr,
3633 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3634 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3635 GET_MODE_NAME (mode));
3636 fprintf (stderr, HOST_PTR_PRINTF, type);
3637 fprintf (stderr, ", %d )\n\n", named);
3638 }
cee98a59
MM		 3639
3640 cum->arg_number++;
3641 switch (mode)
3642 {
b4b93495 3643 case VOIDmode:
cee98a59
MM		 3644 break;
3645
b4b93495
RS		 3646 default:
3647 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3648 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3649 abort ();
f5963e61 3650
b4b93495 3651 cum->gp_reg_found = 1;
147255d8
JW		 3652 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3653 / UNITS_PER_WORD);
cee98a59
MM		 3654 break;
3655
3656 case BLKmode:
3657 cum->gp_reg_found = 1;
147255d8
JW		 3658 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3659 / UNITS_PER_WORD);
cee98a59
MM		 3660 break;
3661
3662 case SFmode:
293a36eb
ILT		 3663 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3664 cum->fp_arg_words++;
3665 else
3666 cum->arg_words++;
2bcb2ab3
GK		 3667 if (! cum->gp_reg_found && cum->arg_number <= 2)
3668 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
cee98a59
MM		 3669 break;
3670
3671 case DFmode:
293a36eb
ILT		 3672 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3673 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3674 else
3675 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2bcb2ab3
GK		 3676 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3677 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
cee98a59
MM		 3678 break;
3679
3680 case DImode:
3681 cum->gp_reg_found = 1;
147255d8 3682 cum->arg_words += (TARGET_64BIT ? 1 : 2);
cee98a59
MM		 3683 break;
3684
3685 case QImode:
3686 case HImode:
3687 case SImode:
3688 cum->gp_reg_found = 1;
3689 cum->arg_words++;
3690 break;
3691 }
3692}
3693
147255d8
JW		 3694/* Return an RTL expression containing the register for the given mode,
3695 or 0 if the argument is to be passed on the stack. */
cee98a59
MM		 3696
3697struct rtx_def *
3698function_arg (cum, mode, type, named)
3699 CUMULATIVE_ARGS *cum; /* current arg information */
3700 enum machine_mode mode; /* current arg mode */
3701 tree type; /* type of the argument or 0 if lib support */
3702 int named; /* != 0 for normal args, == 0 for ... args */
3703{
3f1f8d8c 3704 rtx ret;
cee98a59
MM		 3705 int regbase = -1;
3706 int bias = 0;
293a36eb 3707 int *arg_words = &cum->arg_words;
f5963e61 3708 int struct_p = (type != 0
3f1f8d8c 3709 && (TREE_CODE (type) == RECORD_TYPE
f5963e61
JL		 3710 || TREE_CODE (type) == UNION_TYPE
3711 || TREE_CODE (type) == QUAL_UNION_TYPE));
cee98a59
MM		 3712
3713 if (TARGET_DEBUG_E_MODE)
38831dfe
KG		 3714 {
3715 fprintf (stderr,
3716 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3717 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3718 GET_MODE_NAME (mode));
3719 fprintf (stderr, HOST_PTR_PRINTF, type);
3720 fprintf (stderr, ", %d ) = ", named);
3721 }
3722
cee98a59 3723
293a36eb 3724 cum->last_arg_fp = 0;
cee98a59
MM		 3725 switch (mode)
3726 {
cee98a59 3727 case SFmode:
a53f72db 3728 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
dc55be0e 3729 {
33563487
JW		 3730 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3731 regbase = GP_ARG_FIRST;
3732 else
3733 {
3734 regbase = FP_ARG_FIRST;
f5963e61 3735
33563487
JW		 3736 /* If the first arg was a float in a floating point register,
3737 then set bias to align this float arg properly. */
3738 if (cum->arg_words == 1)
3739 bias = 1;
3740 }
dc55be0e 3741 }
293a36eb
ILT		 3742 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3743 {
3744 if (! TARGET_64BIT)
3745 cum->fp_arg_words += cum->fp_arg_words & 1;
3746 cum->last_arg_fp = 1;
3747 arg_words = &cum->fp_arg_words;
3748 regbase = FP_ARG_FIRST;
3749 }
33563487
JW		 3750 else
3751 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
cee98a59
MM		 3752 break;
3753
3754 case DFmode:
147255d8 3755 if (! TARGET_64BIT)
293a36eb
ILT		 3756 {
3757 if (mips_abi == ABI_EABI
f5963e61 3758 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
293a36eb
ILT		 3759 cum->fp_arg_words += cum->fp_arg_words & 1;
3760 else
3761 cum->arg_words += cum->arg_words & 1;
3762 }
f5963e61 3763
a53f72db 3764 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
33563487 3765 regbase = ((cum->gp_reg_found
f5963e61 3766 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
33563487 3767 || cum->arg_number >= 2)
f5963e61 3768 ? GP_ARG_FIRST : FP_ARG_FIRST);
293a36eb 3769 else if (mips_abi == ABI_EABI
f5963e61 3770 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
293a36eb
ILT		 3771 {
3772 cum->last_arg_fp = 1;
3773 arg_words = &cum->fp_arg_words;
3774 regbase = FP_ARG_FIRST;
3775 }
33563487
JW		 3776 else
3777 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3778 ? GP_ARG_FIRST : FP_ARG_FIRST);
cee98a59
MM		 3779 break;
3780
b4b93495
RS		 3781 default:
3782 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3783 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3784 abort ();
3785
3786 /* Drops through. */
cee98a59 3787 case BLKmode:
e51712db 3788 if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
293a36eb 3789 && ! TARGET_64BIT && mips_abi != ABI_EABI)
df7fef57 3790 cum->arg_words += (cum->arg_words & 1);
df7fef57
MM		 3791 regbase = GP_ARG_FIRST;
3792 break;
3793
3794 case VOIDmode:
cee98a59
MM		 3795 case QImode:
3796 case HImode:
3797 case SImode:
3798 regbase = GP_ARG_FIRST;
3799 break;
3800
3801 case DImode:
147255d8
JW		 3802 if (! TARGET_64BIT)
3803 cum->arg_words += (cum->arg_words & 1);
cee98a59
MM		 3804 regbase = GP_ARG_FIRST;
3805 }
3806
293a36eb 3807 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
cee98a59
MM		 3808 {
3809 if (TARGET_DEBUG_E_MODE)
3f1f8d8c 3810 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
cee98a59 3811
f5963e61 3812 ret = 0;
cee98a59 3813 }
3f1f8d8c
MM		 3814 else
3815 {
3816 if (regbase == -1)
3817 abort ();
cee98a59 3818
a20b7b05 3819 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
a53f72db 3820 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named)
c5c76735 3821 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
a20b7b05
JW		 3822 else
3823 {
3824 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3825 structure contains a double in its entirety, then that 64 bit
3826 chunk is passed in a floating point register. */
3827 tree field;
3828
3829 /* First check to see if there is any such field. */
3830 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
320aba9c
JW		 3831 if (TREE_CODE (field) == FIELD_DECL
3832 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
a20b7b05
JW		 3833 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3834 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3835 % BITS_PER_WORD == 0))
3836 break;
3837
e9a25f70
JL		 3838 /* If the whole struct fits a DFmode register,
3839 we don't need the PARALLEL. */
15039abe 3840 if (! field || mode == DFmode)
c5c76735 3841 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
a20b7b05
JW		 3842 else
3843 {
3844 /* Now handle the special case by returning a PARALLEL
3845 indicating where each 64 bit chunk goes. */
3846 int chunks;
3847 int bitpos;
3848 int regno;
3849 int i;
3850
3851 /* ??? If this is a packed structure, then the last hunk won't
3852 be 64 bits. */
3853
a20b7b05 3854 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
293a36eb
ILT		 3855 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
3856 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
a20b7b05
JW		 3857
3858 /* assign_parms checks the mode of ENTRY_PARM, so we must
3859 use the actual mode here. */
c5c76735 3860 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
a20b7b05
JW		 3861
3862 bitpos = 0;
293a36eb 3863 regno = regbase + *arg_words + bias;
a20b7b05
JW		 3864 field = TYPE_FIELDS (type);
3865 for (i = 0; i < chunks; i++)
3866 {
3867 rtx reg;
3868
3869 for (; field; field = TREE_CHAIN (field))
320aba9c
JW		 3870 if (TREE_CODE (field) == FIELD_DECL
3871 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3872 >= bitpos))
a20b7b05
JW		 3873 break;
3874
3875 if (field
3876 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3877 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3878 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
c5c76735
JL		 3879 reg = gen_rtx_REG (DFmode,
3880 regno + FP_ARG_FIRST - GP_ARG_FIRST);
a20b7b05 3881 else
c5c76735
JL		 3882 reg = gen_rtx_REG (word_mode, regno);
3883
f5963e61 3884 XVECEXP (ret, 0, i)
c5c76735
JL		 3885 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3886 GEN_INT (bitpos / BITS_PER_UNIT));
a20b7b05
JW		 3887
3888 bitpos += 64;
3889 regno++;
3890 }
3891 }
3892 }
cee98a59 3893
3f1f8d8c 3894 if (TARGET_DEBUG_E_MODE)
293a36eb 3895 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3f1f8d8c
MM		 3896 struct_p ? ", [struct]" : "");
3897
3898 /* The following is a hack in order to pass 1 byte structures
3899 the same way that the MIPS compiler does (namely by passing
3900 the structure in the high byte or half word of the register).
3901 This also makes varargs work. If we have such a structure,
3902 we save the adjustment RTL, and the call define expands will
3903 emit them. For the VOIDmode argument (argument after the
147255d8 3904 last real argument), pass back a parallel vector holding each
3f1f8d8c
MM		 3905 of the adjustments. */
3906
894715dd
RS		 3907 /* ??? function_arg can be called more than once for each argument.
3908 As a result, we compute more adjustments than we need here.
3909 See the CUMULATIVE_ARGS definition in mips.h. */
3910
147255d8
JW		 3911 /* ??? This scheme requires everything smaller than the word size to
3912 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3913 that would mean every int needs to be shifted left, which is very
3914 inefficient. Let's not carry this compatibility to the 64 bit
3915 calling convention for now. */
3916
3917 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
293a36eb 3918 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3f1f8d8c 3919 {
f4ef129a
JW		 3920 rtx amount = GEN_INT (BITS_PER_WORD
3921 - int_size_in_bytes (type) * BITS_PER_UNIT);
c5c76735 3922 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
f5963e61 3923
147255d8 3924 if (TARGET_64BIT)
f5963e61 3925 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
147255d8 3926 else
f5963e61 3927 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
3f1f8d8c
MM		 3928 }
3929 }
3930
2bcb2ab3
GK		 3931 /* We will be called with a mode of VOIDmode after the last argument
3932 has been seen. Whatever we return will be passed to the call
3933 insn. If we need any shifts for small structures, return them in
3934 a PARALLEL; in that case, stuff the mips16 fp_code in as the
3935 mode. Otherwise, if we have need a mips16 fp_code, return a REG
3936 with the code stored as the mode. */
3937 if (mode == VOIDmode)
3938 {
3939 if (cum->num_adjusts > 0)
3940 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
3941 gen_rtvec_v (cum->num_adjusts, cum->adjust));
3942 else if (TARGET_MIPS16 && cum->fp_code != 0)
3943 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
3944 }
cee98a59 3945
3f1f8d8c 3946 return ret;
cee98a59
MM		 3947}
3948
cee98a59
MM		 3949int
3950function_arg_partial_nregs (cum, mode, type, named)
3951 CUMULATIVE_ARGS *cum; /* current arg information */
3952 enum machine_mode mode; /* current arg mode */
3953 tree type; /* type of the argument or 0 if lib support */
38831dfe 3954 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
cee98a59 3955{
b4b93495
RS		 3956 if ((mode == BLKmode
3957 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3958 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
293a36eb
ILT		 3959 && cum->arg_words < MAX_ARGS_IN_REGISTERS
3960 && mips_abi != ABI_EABI)
cee98a59 3961 {
b4b93495
RS		 3962 int words;
3963 if (mode == BLKmode)
147255d8
JW		 3964 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3965 / UNITS_PER_WORD);
b4b93495 3966 else
147255d8 3967 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
cee98a59 3968
47f113fe 3969 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
cee98a59
MM		 3970 return 0; /* structure fits in registers */
3971
3972 if (TARGET_DEBUG_E_MODE)
3973 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3974 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3975
3976 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3977 }
3978
147255d8 3979 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
f5963e61 3980 && ! TARGET_64BIT && mips_abi != ABI_EABI)
cee98a59
MM		 3981 {
3982 if (TARGET_DEBUG_E_MODE)
3983 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3984
3985 return 1;
3986 }
3987
3988 return 0;
3989}
cee98a59
MM		 3990\f
3991/* Abort after printing out a specific insn. */
3992
e2fe6aba 3993static void
cee98a59
MM		 3994abort_with_insn (insn, reason)
3995 rtx insn;
e2fe6aba 3996 const char *reason;
cee98a59
MM		 3997{
3998 error (reason);
3999 debug_rtx (insn);
4000 abort ();
4001}
4002
4003/* Write a message to stderr (for use in macros expanded in files that do not
4004 include stdio.h). */
4005
4006void
4007trace (s, s1, s2)
4008 char *s, *s1, *s2;
4009{
4010 fprintf (stderr, s, s1, s2);
4011}
cee98a59
MM		 4012\f
4013/* Set up the threshold for data to go into the small data area, instead
4014 of the normal data area, and detect any conflicts in the switches. */
4015
4016void
4017override_options ()
4018{
4019 register int i, start;
4020 register int regno;
4021 register enum machine_mode mode;
4022
f5963e61 4023 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
cee98a59 4024
147255d8
JW		 4025 if (mips_section_threshold <= 0)
4026 target_flags &= ~MASK_GPOPT;
4027 else if (optimize)
4028 target_flags |= MASK_GPOPT;
4029
2bcb2ab3
GK		 4030#ifndef MIPS_ISA_DEFAULT
4031#define MIPS_ISA_DEFAULT 1
4032#endif
4033
4034 /* If both single-float and soft-float are set, then clear the one that
4035 was set by TARGET_DEFAULT, leaving the one that was set by the
4036 user. We assume here that the specs prevent both being set by the
4037 user. */
4038#ifdef TARGET_DEFAULT
4039 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4040 target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
4041#endif
4042
147255d8 4043 /* Get the architectural level. */
f5963e61 4044 if (mips_isa_string == 0)
2bcb2ab3 4045 mips_isa = MIPS_ISA_DEFAULT;
147255d8 4046
38831dfe 4047 else if (ISDIGIT (*mips_isa_string))
147255d8
JW		 4048 {
4049 mips_isa = atoi (mips_isa_string);
2bcb2ab3
GK		 4050 if (mips_isa == 16)
4051 {
4052 /* -mno-mips16 overrides -mips16. */
4053 if (mips_no_mips16_string == NULL)
4054 {
4055 target_flags |= MASK_MIPS16;
4056 if (TARGET_64BIT)
4057 mips_isa = 3;
4058 else
4059 mips_isa = MIPS_ISA_DEFAULT;
4060 }
4061 else
4062 {
4063 mips_isa = MIPS_ISA_DEFAULT;
4064 }
4065 }
4066 else if (mips_isa < 1 || mips_isa > 4)
147255d8
JW		 4067 {
4068 error ("-mips%d not supported", mips_isa);
4069 mips_isa = 1;
4070 }
4071 }
4072
4073 else
4074 {
4075 error ("bad value (%s) for -mips switch", mips_isa_string);
4076 mips_isa = 1;
4077 }
4078
ade6c319 4079#ifdef MIPS_ABI_DEFAULT
a53f72db 4080 /* Get the ABI to use. */
ade6c319
JW		 4081 if (mips_abi_string == (char *) 0)
4082 mips_abi = MIPS_ABI_DEFAULT;
748b909e 4083 else if (! strcmp (mips_abi_string, "32"))
ade6c319 4084 mips_abi = ABI_32;
a53f72db
GRK		 4085 else if (! strcmp (mips_abi_string, "o64"))
4086 mips_abi = ABI_O64;
ade6c319
JW		 4087 else if (! strcmp (mips_abi_string, "n32"))
4088 mips_abi = ABI_N32;
748b909e 4089 else if (! strcmp (mips_abi_string, "64"))
ade6c319 4090 mips_abi = ABI_64;
293a36eb
ILT		 4091 else if (! strcmp (mips_abi_string, "eabi"))
4092 mips_abi = ABI_EABI;
ade6c319
JW		 4093 else
4094 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4095
4096 /* A specified ISA defaults the ABI if it was not specified. */
a53f72db
GRK		 4097 if (mips_abi_string == 0 && mips_isa_string
4098 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
ade6c319
JW		 4099 {
4100 if (mips_isa <= 2)
4101 mips_abi = ABI_32;
4102 else
4103 mips_abi = ABI_64;
4104 }
f5963e61 4105
ade6c319 4106 /* A specified ABI defaults the ISA if it was not specified. */
a53f72db
GRK		 4107 else if (mips_isa_string == 0 && mips_abi_string
4108 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
ade6c319
JW		 4109 {
4110 if (mips_abi == ABI_32)
4111 mips_isa = 1;
4112 else if (mips_abi == ABI_N32)
4113 mips_isa = 3;
4114 else
4115 mips_isa = 4;
4116 }
f5963e61 4117
ade6c319
JW		 4118 /* If both ABI and ISA were specified, check for conflicts. */
4119 else if (mips_isa_string && mips_abi_string)
4120 {
a53f72db
GRK		 4121 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
4122 || mips_abi == ABI_O64))
ade6c319
JW		 4123 || (mips_isa >= 3 && mips_abi == ABI_32))
4124 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4125 }
4126
4127 /* Override TARGET_DEFAULT if necessary. */
4128 if (mips_abi == ABI_32)
4129 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4130
3ce1ba83
GRK		 4131 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4132 then set the type sizes. In the EABI in 64 bit mode, longs and
4133 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4134 if (mips_explicit_type_size_string == NULL
4135 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4136 || mips_abi == ABI_64))
29a5d7cc
ILT		 4137 target_flags |= MASK_LONG64;
4138
ade6c319
JW		 4139 /* ??? This doesn't work yet, so don't let people try to use it. */
4140 if (mips_abi == ABI_32)
4141 error ("The -mabi=32 support does not work yet.");
f5963e61 4142
ade6c319
JW		 4143#else
4144 if (mips_abi_string)
4145 error ("This target does not support the -mabi switch.");
4146#endif
4147
1bd9166e
JW		 4148#ifdef MIPS_CPU_STRING_DEFAULT
4149 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4150 greater than that supported by the default processor, then the user gets
4151 an error. Normally, the compiler will just default to the base level cpu
4152 for the indicated isa. */
f5963e61 4153 if (mips_cpu_string == 0)
1bd9166e
JW		 4154 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4155#endif
4156
cee98a59 4157 /* Identify the processor type */
f5963e61 4158 if (mips_cpu_string == 0
cee98a59
MM		 4159 || !strcmp (mips_cpu_string, "default")
4160 || !strcmp (mips_cpu_string, "DEFAULT"))
4161 {
147255d8
JW		 4162 switch (mips_isa)
4163 {
4164 default:
4165 mips_cpu_string = "3000";
4166 mips_cpu = PROCESSOR_R3000;
4167 break;
4168 case 2:
4169 mips_cpu_string = "6000";
4170 mips_cpu = PROCESSOR_R6000;
4171 break;
4172 case 3:
4173 mips_cpu_string = "4000";
4174 mips_cpu = PROCESSOR_R4000;
4175 break;
33563487
JW		 4176 case 4:
4177 mips_cpu_string = "8000";
4178 mips_cpu = PROCESSOR_R8000;
4179 break;
147255d8 4180 }
cee98a59
MM		 4181 }
4182
4183 else
4184 {
e2fe6aba 4185 const char *p = mips_cpu_string;
f5963e61 4186 int seen_v = 0;
cee98a59 4187
5034b7bd
JW		 4188 /* We need to cope with the various "vr" prefixes for the NEC 4300
4189 and 4100 processors. */
4190 if (*p == 'v' || *p == 'V')
f5963e61
JL		 4191 seen_v = 1, p++;
4192
cee98a59
MM		 4193 if (*p == 'r' || *p == 'R')
4194 p++;
4195
4196 /* Since there is no difference between a R2000 and R3000 in
4197 terms of the scheduler, we collapse them into just an R3000. */
4198
4199 mips_cpu = PROCESSOR_DEFAULT;
4200 switch (*p)
4201 {
2bcb2ab3 4202 case '2':
cee98a59
MM		 4203 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4204 mips_cpu = PROCESSOR_R3000;
4205 break;
4206
4207 case '3':
4208 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4209 mips_cpu = PROCESSOR_R3000;
e9a25f70
JL		 4210 else if (!strcmp (p, "3900"))
4211 mips_cpu = PROCESSOR_R3900;
cee98a59
MM		 4212 break;
4213
4214 case '4':
4215 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4216 mips_cpu = PROCESSOR_R4000;
5034b7bd
JW		 4217 /* The vr4100 is a non-FP ISA III processor with some extra
4218 instructions. */
f5963e61
JL		 4219 else if (!strcmp (p, "4100"))
4220 {
4221 mips_cpu = PROCESSOR_R4100;
4222 target_flags |= MASK_SOFT_FLOAT ;
4223 }
5034b7bd
JW		 4224 /* The vr4300 is a standard ISA III processor, but with a different
4225 pipeline. */
4226 else if (!strcmp (p, "4300"))
4227 mips_cpu = PROCESSOR_R4300;
147255d8
JW		 4228 /* The r4400 is exactly the same as the r4000 from the compiler's
4229 viewpoint. */
4230 else if (!strcmp (p, "4400"))
4231 mips_cpu = PROCESSOR_R4000;
4232 else if (!strcmp (p, "4600"))
4233 mips_cpu = PROCESSOR_R4600;
46299de9 4234 else if (!strcmp (p, "4650"))
053665d7 4235 mips_cpu = PROCESSOR_R4650;
cee98a59
MM		 4236 break;
4237
b8eb88d0
ILT		 4238 case '5':
4239 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4240 mips_cpu = PROCESSOR_R5000;
4241 break;
4242
cee98a59
MM		 4243 case '6':
4244 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4245 mips_cpu = PROCESSOR_R6000;
4246 break;
147255d8 4247
33563487
JW		 4248 case '8':
4249 if (!strcmp (p, "8000"))
4250 mips_cpu = PROCESSOR_R8000;
4251 break;
4252
147255d8
JW		 4253 case 'o':
4254 if (!strcmp (p, "orion"))
4255 mips_cpu = PROCESSOR_R4600;
4256 break;
cee98a59
MM		 4257 }
4258
b8eb88d0
ILT		 4259 if (seen_v
4260 && mips_cpu != PROCESSOR_R4300
4261 && mips_cpu != PROCESSOR_R4100
4262 && mips_cpu != PROCESSOR_R5000)
5034b7bd
JW		 4263 mips_cpu = PROCESSOR_DEFAULT;
4264
cee98a59
MM		 4265 if (mips_cpu == PROCESSOR_DEFAULT)
4266 {
4267 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4268 mips_cpu_string = "default";
4269 }
4270 }
4271
147255d8 4272 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
33563487 4273 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
053665d7 4274 || ((mips_cpu == PROCESSOR_R4000
5034b7bd
JW		 4275 || mips_cpu == PROCESSOR_R4100
4276 || mips_cpu == PROCESSOR_R4300
053665d7
ILT		 4277 || mips_cpu == PROCESSOR_R4600
4278 || mips_cpu == PROCESSOR_R4650)
33563487 4279 && mips_isa > 3))
cee98a59
MM		 4280 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4281
4282 /* make sure sizes of ints/longs/etc. are ok */
4283 if (mips_isa < 3)
4284 {
fb1bf66d 4285 if (TARGET_FLOAT64)
33563487 4286 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
f8151871
JW		 4287
4288 else if (TARGET_64BIT)
33563487 4289 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
147255d8 4290 }
cee98a59 4291
a53f72db 4292 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
33563487
JW		 4293 flag_pcc_struct_return = 0;
4294
cee98a59
MM		 4295 /* Tell halfpic.c that we have half-pic code if we do. */
4296 if (TARGET_HALF_PIC)
c831afd5 4297 HALF_PIC_INIT ();
cee98a59 4298
508a48d1
JW		 4299 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4300 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4301 /* ??? -non_shared turns off pic code generation, but this is not
4302 implemented. */
ffa9d0b1 4303 if (TARGET_ABICALLS)
508a48d1
JW		 4304 {
4305 mips_abicalls = MIPS_ABICALLS_YES;
4306 flag_pic = 1;
508a48d1
JW		 4307 if (mips_section_threshold > 0)
4308 warning ("-G is incompatible with PIC code which is the default");
4309 }
ffa9d0b1 4310 else
1d6ce736 4311 mips_abicalls = MIPS_ABICALLS_NO;
ffa9d0b1 4312
e0bfcea5
ILT		 4313 /* -membedded-pic is a form of PIC code suitable for embedded
4314 systems. All calls are made using PC relative addressing, and
4315 all data is addressed using the $gp register. This requires gas,
4316 which does most of the work, and GNU ld, which automatically
4317 expands PC relative calls which are out of range into a longer
4318 instruction sequence. All gcc really does differently is
4319 generate a different sequence for a switch. */
4320 if (TARGET_EMBEDDED_PIC)
4321 {
4322 flag_pic = 1;
4323 if (TARGET_ABICALLS)
4324 warning ("-membedded-pic and -mabicalls are incompatible");
f5963e61 4325
e0bfcea5
ILT		 4326 if (g_switch_set)
4327 warning ("-G and -membedded-pic are incompatible");
f5963e61 4328
e0bfcea5
ILT		 4329 /* Setting mips_section_threshold is not required, because gas
4330 will force everything to be GP addressable anyhow, but
4331 setting it will cause gcc to make better estimates of the
4332 number of instructions required to access a particular data
4333 item. */
4334 mips_section_threshold = 0x7fffffff;
4335 }
4336
8acd7d30 4337 /* This optimization requires a linker that can support a R_MIPS_LO16
f5963e61 4338 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
8acd7d30
JW		 4339 GNU ld has this support, but not all other MIPS linkers do, so we enable
4340 this optimization only if the user requests it, or if GNU ld is the
4341 standard linker for this configuration. */
910628b8
JW		 4342 /* ??? This does not work when target addresses are DImode.
4343 This is because we are missing DImode high/lo_sum patterns. */
2bcb2ab3 4344 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
8acd7d30 4345 && Pmode == SImode)
910628b8
JW		 4346 mips_split_addresses = 1;
4347 else
4348 mips_split_addresses = 0;
4349
cee98a59 4350 /* -mrnames says to use the MIPS software convention for register
147255d8 4351 names instead of the hardware names (ie, $a0 instead of $4).
cee98a59
MM		 4352 We do this by switching the names in mips_reg_names, which the
4353 reg_names points into via the REGISTER_NAMES macro. */
4354
4355 if (TARGET_NAME_REGS)
f5963e61
JL		 4356 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
4357 sizeof (mips_reg_names));
cee98a59 4358
2bcb2ab3
GK		 4359 /* When compiling for the mips16, we can not use floating point. We
4360 record the original hard float value in mips16_hard_float. */
4361 if (TARGET_MIPS16)
4362 {
4363 if (TARGET_SOFT_FLOAT)
4364 mips16_hard_float = 0;
4365 else
4366 mips16_hard_float = 1;
4367 target_flags |= MASK_SOFT_FLOAT;
4368
4369 /* Don't run the scheduler before reload, since it tends to
4370 increase register pressure. */
4371 flag_schedule_insns = 0;
4372 }
4373
4374 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4375 to avoid using up another bit in target_flags. */
4376 if (mips_entry_string != NULL)
4377 {
4378 if (*mips_entry_string != '\0')
4379 error ("Invalid option `entry%s'", mips_entry_string);
4380
4381 if (! TARGET_MIPS16)
4382 warning ("-mentry is only meaningful with -mips-16");
4383 else
4384 mips_entry = 1;
4385 }
4386
4387 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4388 attributes can access it. */
4389 if (TARGET_MIPS16)
4390 mips16 = 1;
4391 else
4392 mips16 = 0;
4393
147255d8
JW		 4394 /* Initialize the high and low values for legitimate floating point
4395 constants. Rather than trying to get the accuracy down to the
4396 last bit, just use approximate ranges. */
4397 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
4398 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
4399 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
4400 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
4401
f5963e61
JL		 4402 mips_print_operand_punct['?'] = 1;
4403 mips_print_operand_punct['#'] = 1;
4404 mips_print_operand_punct['&'] = 1;
4405 mips_print_operand_punct['!'] = 1;
4406 mips_print_operand_punct['*'] = 1;
4407 mips_print_operand_punct['@'] = 1;
4408 mips_print_operand_punct['.'] = 1;
4409 mips_print_operand_punct['('] = 1;
4410 mips_print_operand_punct[')'] = 1;
4411 mips_print_operand_punct['['] = 1;
4412 mips_print_operand_punct[']'] = 1;
4413 mips_print_operand_punct['<'] = 1;
4414 mips_print_operand_punct['>'] = 1;
4415 mips_print_operand_punct['{'] = 1;
4416 mips_print_operand_punct['}'] = 1;
4417 mips_print_operand_punct['^'] = 1;
4418 mips_print_operand_punct['$'] = 1;
4419 mips_print_operand_punct['+'] = 1;
efa3896a 4420 mips_print_operand_punct['~'] = 1;
cee98a59 4421
2bcb2ab3
GK		 4422 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4423 mips_char_to_class['e'] = M16_NA_REGS;
4424 mips_char_to_class['t'] = T_REG;
f5963e61 4425 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
cee98a59
MM		 4426 mips_char_to_class['h'] = HI_REG;
4427 mips_char_to_class['l'] = LO_REG;
225b8835 4428 mips_char_to_class['a'] = HILO_REG;
cee98a59 4429 mips_char_to_class['x'] = MD_REGS;
225b8835 4430 mips_char_to_class['b'] = ALL_REGS;
cee98a59 4431 mips_char_to_class['y'] = GR_REGS;
34b650b3 4432 mips_char_to_class['z'] = ST_REGS;
cee98a59
MM		 4433
4434 /* Set up array to map GCC register number to debug register number.
4435 Ignore the special purpose register numbers. */
4436
4437 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4438 mips_dbx_regno[i] = -1;
4439
4440 start = GP_DBX_FIRST - GP_REG_FIRST;
4441 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4442 mips_dbx_regno[i] = i + start;
4443
4444 start = FP_DBX_FIRST - FP_REG_FIRST;
4445 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4446 mips_dbx_regno[i] = i + start;
4447
4448 /* Set up array giving whether a given register can hold a given mode.
4449 At present, restrict ints from being in FP registers, because reload
4450 is a little enthusiastic about storing extra values in FP registers,
4451 and this is not good for things like OS kernels. Also, due to the
c831afd5 4452 mandatory delay, it is as fast to load from cached memory as to move
cee98a59
MM		 4453 from the FP register. */
4454
4455 for (mode = VOIDmode;
4456 mode != MAX_MACHINE_MODE;
f5963e61 4457 mode = (enum machine_mode) ((int)mode + 1))
cee98a59
MM		 4458 {
4459 register int size = GET_MODE_SIZE (mode);
4460 register enum mode_class class = GET_MODE_CLASS (mode);
4461
4462 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4463 {
34b650b3
MM		 4464 register int temp;
4465
b8eb88d0
ILT		 4466 if (mode == CCmode)
4467 {
4468 if (mips_isa < 4)
4469 temp = (regno == FPSW_REGNUM);
4470 else
f5963e61 4471 temp = (ST_REG_P (regno) || GP_REG_P (regno)
b8eb88d0
ILT		 4472 || FP_REG_P (regno));
4473 }
cee98a59 4474
34b650b3 4475 else if (GP_REG_P (regno))
f5963e61 4476 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
cee98a59
MM		 4477
4478 else if (FP_REG_P (regno))
4479 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
34b650b3
MM		 4480 && (class == MODE_FLOAT
4481 || class == MODE_COMPLEX_FLOAT
46299de9
ILT		 4482 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
4483 && (! TARGET_SINGLE_FLOAT || size <= 4));
cee98a59
MM		 4484
4485 else if (MD_REG_P (regno))
1cfb3048
RK		 4486 temp = (class == MODE_INT
4487 && (size <= UNITS_PER_WORD
f5963e61
JL		 4488 || (regno == MD_REG_FIRST
4489 && size == 2 * UNITS_PER_WORD)));
cee98a59 4490
34b650b3 4491 else
f5963e61 4492 temp = 0;
cee98a59
MM		 4493
4494 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4495 }
4496 }
bfed8dac 4497
45cc4c09
JW		 4498 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4499 initialized yet, so we can't use that here. */
4500 gpr_mode = TARGET_64BIT ? DImode : SImode;
efa3896a
GK		 4501
4502 /* Provide default values for align_* for 64-bit targets. */
4503 if (TARGET_64BIT)
4504 {
4505 if (align_loops == 0)
4506 align_loops = 8;
4507 if (align_jumps == 0)
4508 align_jumps = 8;
4509 if (align_functions == 0)
4510 align_functions = 8;
4511 }
cee98a59
MM		 4512}
4513
2bcb2ab3
GK		 4514/* On the mips16, we want to allocate $24 (T_REG) before other
4515 registers for instructions for which it is possible. This helps
4516 avoid shuffling registers around in order to set up for an xor,
4517 encouraging the compiler to use a cmp instead. */
4518
4519void
4520mips_order_regs_for_local_alloc ()
4521{
4522 register int i;
4523
4524 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4525 reg_alloc_order[i] = i;
4526
4527 if (TARGET_MIPS16)
4528 {
4529 /* It really doesn't matter where we put register 0, since it is
4530 a fixed register anyhow. */
4531 reg_alloc_order[0] = 24;
4532 reg_alloc_order[24] = 0;
4533 }
4534}
4535
cee98a59 4536\f
f5963e61
JL		 4537/* The MIPS debug format wants all automatic variables and arguments
4538 to be in terms of the virtual frame pointer (stack pointer before
4539 any adjustment in the function), while the MIPS 3.0 linker wants
4540 the frame pointer to be the stack pointer after the initial
4541 adjustment. So, we do the adjustment here. The arg pointer (which
4542 is eliminated) points to the virtual frame pointer, while the frame
4543 pointer (which may be eliminated) points to the stack pointer after
4544 the initial adjustments. */
4545
4546HOST_WIDE_INT
cee98a59
MM		 4547mips_debugger_offset (addr, offset)
4548 rtx addr;
f5963e61 4549 HOST_WIDE_INT offset;
cee98a59 4550{
c831afd5 4551 rtx offset2 = const0_rtx;
cee98a59
MM		 4552 rtx reg = eliminate_constant_term (addr, &offset2);
4553
f5963e61 4554 if (offset == 0)
c831afd5 4555 offset = INTVAL (offset2);
cee98a59 4556
2bcb2ab3
GK		 4557 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4558 || reg == hard_frame_pointer_rtx)
c831afd5 4559 {
f5963e61
JL		 4560 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
4561 ? compute_frame_size (get_frame_size ())
4562 : current_frame_info.total_size;
c831afd5 4563
a50f2a09
AC		 4564 /* MIPS16 frame is smaller */
4565 if (frame_pointer_needed && TARGET_MIPS16)
4566 frame_size -= current_function_outgoing_args_size;
4567
c831afd5
MM		 4568 offset = offset - frame_size;
4569 }
f5963e61 4570
acc15f57
RS		 4571 /* sdbout_parms does not want this to crash for unrecognized cases. */
4572#if 0
ab78d4a8
MM		 4573 else if (reg != arg_pointer_rtx)
4574 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
acc15f57 4575#endif
cee98a59
MM		 4576
4577 return offset;
4578}
4579\f
4580/* A C compound statement to output to stdio stream STREAM the
4581 assembler syntax for an instruction operand X. X is an RTL
4582 expression.
4583
4584 CODE is a value that can be used to specify one of several ways
4585 of printing the operand. It is used when identical operands
4586 must be printed differently depending on the context. CODE
4587 comes from the `%' specification that was used to request
4588 printing of the operand. If the specification was just `%DIGIT'
4589 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4590 is the ASCII code for LTR.
4591
4592 If X is a register, this macro should print the register's name.
4593 The names can be found in an array `reg_names' whose type is
4594 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4595
4596 When the machine description has a specification `%PUNCT' (a `%'
4597 followed by a punctuation character), this macro is called with
4598 a null pointer for X and the punctuation character for CODE.
4599
4600 The MIPS specific codes are:
4601
4602 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4603 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4604 'd' output integer constant in decimal,
4605 'z' if the operand is 0, use $0 instead of normal operand.
4606 'D' print second register of double-word register operand.
4607 'L' print low-order register of double-word register operand.
4608 'M' print high-order register of double-word register operand.
4609 'C' print part of opcode for a branch condition.
0ff83799 4610 'F' print part of opcode for a floating-point branch condition.
cee98a59 4611 'N' print part of opcode for a branch condition, inverted.
0ff83799 4612 'W' print part of opcode for a floating-point branch condition, inverted.
e0bfcea5 4613 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
33563487
JW		 4614 'B' print 'z' for EQ, 'n' for NE
4615 'b' print 'n' for EQ, 'z' for NE
4616 'T' print 'f' for EQ, 't' for NE
4617 't' print 't' for EQ, 'f' for NE
b8eb88d0 4618 'Z' print register and a comma, but print nothing for $fcc0
cee98a59
MM		 4619 '(' Turn on .set noreorder
4620 ')' Turn on .set reorder
4621 '[' Turn on .set noat
4622 ']' Turn on .set at
4623 '<' Turn on .set nomacro
4624 '>' Turn on .set macro
4625 '{' Turn on .set volatile (not GAS)
4626 '}' Turn on .set novolatile (not GAS)
4627 '&' Turn on .set noreorder if filling delay slots
4628 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4629 '!' Turn on .set nomacro if filling delay slots
4630 '#' Print nop if in a .set noreorder section.
4631 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4632 '@' Print the name of the assembler temporary register (at or $1).
ffa9d0b1 4633 '.' Print the name of the register with a hard-wired zero (zero or $0).
2bcb2ab3
GK		 4634 '^' Print the name of the pic call-through register (t9 or $25).
4635 '$' Print the name of the stack pointer register (sp or $29).
efa3896a
GK		 4636 '+' Print the name of the gp register (gp or $28).
4637 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
cee98a59
MM		 4638
4639void
4640print_operand (file, op, letter)
4641 FILE *file; /* file to write to */
4642 rtx op; /* operand to print */
4643 int letter; /* %<letter> or 0 */
4644{
4645 register enum rtx_code code;
4646
4647 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4648 {
4649 switch (letter)
4650 {
cee98a59
MM		 4651 case '?':
4652 if (mips_branch_likely)
4653 putc ('l', file);
4654 break;
4655
4656 case '@':
4657 fputs (reg_names [GP_REG_FIRST + 1], file);
4658 break;
4659
ffa9d0b1
JW		 4660 case '^':
4661 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4662 break;
4663
cee98a59
MM		 4664 case '.':
4665 fputs (reg_names [GP_REG_FIRST + 0], file);
4666 break;
4667
2bcb2ab3
GK		 4668 case '$':
4669 fputs (reg_names[STACK_POINTER_REGNUM], file);
4670 break;
4671
4672 case '+':
4673 fputs (reg_names[GP_REG_FIRST + 28], file);
4674 break;
4675
cee98a59
MM		 4676 case '&':
4677 if (final_sequence != 0 && set_noreorder++ == 0)
4678 fputs (".set\tnoreorder\n\t", file);
4679 break;
4680
4681 case '*':
4682 if (final_sequence != 0)
4683 {
4684 if (set_noreorder++ == 0)
4685 fputs (".set\tnoreorder\n\t", file);
4686
4687 if (set_nomacro++ == 0)
4688 fputs (".set\tnomacro\n\t", file);
4689 }
4690 break;
4691
4692 case '!':
4693 if (final_sequence != 0 && set_nomacro++ == 0)
4694 fputs ("\n\t.set\tnomacro", file);
4695 break;
4696
4697 case '#':
4698 if (set_noreorder != 0)
4699 fputs ("\n\tnop", file);
85098019 4700 else if (TARGET_STATS)
cee98a59
MM		 4701 fputs ("\n\t#nop", file);
4702
4703 break;
4704
4705 case '(':
4706 if (set_noreorder++ == 0)
4707 fputs (".set\tnoreorder\n\t", file);
4708 break;
4709
4710 case ')':
4711 if (set_noreorder == 0)
4712 error ("internal error: %%) found without a %%( in assembler pattern");
4713
4714 else if (--set_noreorder == 0)
4715 fputs ("\n\t.set\treorder", file);
4716
4717 break;
4718
4719 case '[':
4720 if (set_noat++ == 0)
4721 fputs (".set\tnoat\n\t", file);
4722 break;
4723
4724 case ']':
4725 if (set_noat == 0)
4726 error ("internal error: %%] found without a %%[ in assembler pattern");
cee98a59
MM		 4727 else if (--set_noat == 0)
4728 fputs ("\n\t.set\tat", file);
4729
4730 break;
4731
4732 case '<':
4733 if (set_nomacro++ == 0)
4734 fputs (".set\tnomacro\n\t", file);
4735 break;
4736
4737 case '>':
4738 if (set_nomacro == 0)
4739 error ("internal error: %%> found without a %%< in assembler pattern");
cee98a59
MM		 4740 else if (--set_nomacro == 0)
4741 fputs ("\n\t.set\tmacro", file);
4742
4743 break;
4744
4745 case '{':
4746 if (set_volatile++ == 0)
f5963e61 4747 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
cee98a59
MM		 4748 break;
4749
4750 case '}':
4751 if (set_volatile == 0)
4752 error ("internal error: %%} found without a %%{ in assembler pattern");
cee98a59
MM		 4753 else if (--set_volatile == 0)
4754 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
4755
4756 break;
f5963e61 4757
efa3896a
GK		 4758 case '~':
4759 {
4760 if (align_labels_log > 0)
4761 ASM_OUTPUT_ALIGN (file, align_labels_log);
4762 }
4763 break;
4764
f5963e61
JL		 4765 default:
4766 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
4767 break;
cee98a59 4768 }
f5963e61 4769
cee98a59
MM		 4770 return;
4771 }
4772
4773 if (! op)
4774 {
4775 error ("PRINT_OPERAND null pointer");
4776 return;
4777 }
4778
4779 code = GET_CODE (op);
2a0b0bf5
ILT		 4780
4781 if (code == SIGN_EXTEND)
f5963e61 4782 op = XEXP (op, 0), code = GET_CODE (op);
2a0b0bf5 4783
cee98a59
MM		 4784 if (letter == 'C')
4785 switch (code)
4786 {
4787 case EQ: fputs ("eq", file); break;
4788 case NE: fputs ("ne", file); break;
4789 case GT: fputs ("gt", file); break;
4790 case GE: fputs ("ge", file); break;
4791 case LT: fputs ("lt", file); break;
4792 case LE: fputs ("le", file); break;
4793 case GTU: fputs ("gtu", file); break;
4794 case GEU: fputs ("geu", file); break;
4795 case LTU: fputs ("ltu", file); break;
4796 case LEU: fputs ("leu", file); break;
cee98a59 4797 default:
e7f6e33b 4798 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
cee98a59
MM		 4799 }
4800
4801 else if (letter == 'N')
4802 switch (code)
4803 {
4804 case EQ: fputs ("ne", file); break;
4805 case NE: fputs ("eq", file); break;
4806 case GT: fputs ("le", file); break;
4807 case GE: fputs ("lt", file); break;
4808 case LT: fputs ("ge", file); break;
4809 case LE: fputs ("gt", file); break;
4810 case GTU: fputs ("leu", file); break;
4811 case GEU: fputs ("ltu", file); break;
4812 case LTU: fputs ("geu", file); break;
4813 case LEU: fputs ("gtu", file); break;
cee98a59 4814 default:
e7f6e33b 4815 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
cee98a59
MM		 4816 }
4817
0ff83799
MM		 4818 else if (letter == 'F')
4819 switch (code)
4820 {
4821 case EQ: fputs ("c1f", file); break;
4822 case NE: fputs ("c1t", file); break;
4823 default:
4824 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
4825 }
4826
4827 else if (letter == 'W')
4828 switch (code)
4829 {
4830 case EQ: fputs ("c1t", file); break;
4831 case NE: fputs ("c1f", file); break;
4832 default:
4833 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
4834 }
4835
e0bfcea5
ILT		 4836 else if (letter == 'S')
4837 {
4838 char buffer[100];
4839
4840 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
4841 assemble_name (file, buffer);
4842 }
4843
b8eb88d0
ILT		 4844 else if (letter == 'Z')
4845 {
4846 register int regnum;
4847
4848 if (code != REG)
4849 abort ();
f5963e61 4850
b8eb88d0
ILT		 4851 regnum = REGNO (op);
4852 if (! ST_REG_P (regnum))
4853 abort ();
f5963e61 4854
b8eb88d0
ILT		 4855 if (regnum != ST_REG_FIRST)
4856 fprintf (file, "%s,", reg_names[regnum]);
4857 }
4858
2a0b0bf5 4859 else if (code == REG || code == SUBREG)
cee98a59 4860 {
2a0b0bf5
ILT		 4861 register int regnum;
4862
4863 if (code == REG)
4864 regnum = REGNO (op);
4865 else
4866 regnum = true_regnum (op);
cee98a59 4867
96abdcb1
ILT		 4868 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
4869 || (letter == 'L' && WORDS_BIG_ENDIAN)
4870 || letter == 'D')
cee98a59
MM		 4871 regnum++;
4872
4873 fprintf (file, "%s", reg_names[regnum]);
4874 }
4875
4876 else if (code == MEM)
4877 output_address (XEXP (op, 0));
4878
28ae04f1
ILT		 4879 else if (code == CONST_DOUBLE
4880 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
cee98a59 4881 {
147255d8
JW		 4882 REAL_VALUE_TYPE d;
4883 char s[30];
4884
4885 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
4886 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
4887 fprintf (file, s);
cee98a59
MM		 4888 }
4889
f5963e61 4890 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
8f9661dd 4891 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
f5963e61
JL		 4892
4893 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
4894 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
4895
4896 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
4897 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
cee98a59 4898
f5963e61 4899 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
cee98a59
MM		 4900 fputs (reg_names[GP_REG_FIRST], file);
4901
4902 else if (letter == 'd' || letter == 'x' || letter == 'X')
f5963e61
JL		 4903 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
4904 letter);
cee98a59 4905
33563487
JW		 4906 else if (letter == 'B')
4907 fputs (code == EQ ? "z" : "n", file);
4908 else if (letter == 'b')
4909 fputs (code == EQ ? "n" : "z", file);
4910 else if (letter == 'T')
4911 fputs (code == EQ ? "f" : "t", file);
4912 else if (letter == 't')
4913 fputs (code == EQ ? "t" : "f", file);
4914
2bcb2ab3
GK		 4915 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
4916 {
4917 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
4918 print_operand (file, XEXP (op, 0), letter);
4919 }
4920
4921 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
4922 {
4923 fputs ("%gprel(", file);
4924 mips16_output_gp_offset (file, op);
4925 fputs (")", file);
4926 }
4927
cee98a59
MM		 4928 else
4929 output_addr_const (file, op);
4930}
cee98a59
MM		 4931\f
4932/* A C compound statement to output to stdio stream STREAM the
4933 assembler syntax for an instruction operand that is a memory
4934 reference whose address is ADDR. ADDR is an RTL expression.
4935
4936 On some machines, the syntax for a symbolic address depends on
4937 the section that the address refers to. On these machines,
4938 define the macro `ENCODE_SECTION_INFO' to store the information
4939 into the `symbol_ref', and then check for it here. */
4940
4941void
4942print_operand_address (file, addr)
4943 FILE *file;
4944 rtx addr;
4945{
4946 if (!addr)
4947 error ("PRINT_OPERAND_ADDRESS, null pointer");
4948
4949 else
4950 switch (GET_CODE (addr))
4951 {
cee98a59 4952 case REG:
2bcb2ab3 4953 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
ab78d4a8
MM		 4954 abort_with_insn (addr, "Arg pointer not eliminated.");
4955
cee98a59
MM		 4956 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
4957 break;
4958
910628b8
JW		 4959 case LO_SUM:
4960 {
f5963e61
JL		 4961 register rtx arg0 = XEXP (addr, 0);
4962 register rtx arg1 = XEXP (addr, 1);
910628b8
JW		 4963
4964 if (! mips_split_addresses)
4965 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4966
4967 if (GET_CODE (arg0) != REG)
f5963e61
JL		 4968 abort_with_insn (addr,
4969 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
910628b8
JW		 4970
4971 fprintf (file, "%%lo(");
4972 print_operand_address (file, arg1);
4973 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
4974 }
4975 break;
4976
cee98a59
MM		 4977 case PLUS:
4978 {
f5963e61
JL		 4979 register rtx reg = 0;
4980 register rtx offset = 0;
4981 register rtx arg0 = XEXP (addr, 0);
4982 register rtx arg1 = XEXP (addr, 1);
cee98a59
MM		 4983
4984 if (GET_CODE (arg0) == REG)
4985 {
4986 reg = arg0;
4987 offset = arg1;
4988 if (GET_CODE (offset) == REG)
4989 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
4990 }
f5963e61 4991
cee98a59 4992 else if (GET_CODE (arg1) == REG)
f5963e61 4993 reg = arg1, offset = arg0;
cee98a59
MM		 4994 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
4995 {
4996 output_addr_const (file, addr);
4997 break;
4998 }
4999 else
5000 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5001
f5963e61 5002 if (! CONSTANT_P (offset))
e7f6e33b 5003 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
cee98a59 5004
910628b8
JW		 5005 if (REGNO (reg) == ARG_POINTER_REGNUM)
5006 abort_with_insn (addr, "Arg pointer not eliminated.");
ab78d4a8 5007
2bcb2ab3
GK		 5008 if (TARGET_MIPS16
5009 && GET_CODE (offset) == CONST
5010 && mips16_gp_offset_p (offset))
5011 {
5012 fputs ("%gprel(", file);
5013 mips16_output_gp_offset (file, offset);
5014 fputs (")", file);
5015 }
5016 else
5017 output_addr_const (file, offset);
cee98a59
MM		 5018 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5019 }
5020 break;
5021
5022 case LABEL_REF:
5023 case SYMBOL_REF:
5024 case CONST_INT:
5025 case CONST:
5026 output_addr_const (file, addr);
5027 break;
f5963e61
JL		 5028
5029 default:
5030 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5031 break;
cee98a59
MM		 5032 }
5033}
5034
5035\f
f5963e61
JL		 5036/* If optimizing for the global pointer, keep track of all of the externs, so
5037 that at the end of the file, we can emit the appropriate .extern
5038 declaration for them, before writing out the text section. We assume all
5039 names passed to us are in the permanent obstack, so they will be valid at
5040 the end of the compilation.
5041
5042 If we have -G 0, or the extern size is unknown, or the object is in a user
5043 specified section that is not .sbss/.sdata, don't bother emitting the
5044 .externs. In the case of user specified sections this behaviour is
5045 required as otherwise GAS will think the object lives in .sbss/.sdata. */
cee98a59
MM		 5046
5047int
5048mips_output_external (file, decl, name)
38831dfe 5049 FILE *file ATTRIBUTE_UNUSED;
cee98a59
MM		 5050 tree decl;
5051 char *name;
5052{
5053 register struct extern_list *p;
5054 int len;
4144ff62 5055 tree section_name;
cee98a59
MM		 5056
5057 if (TARGET_GP_OPT
f5963e61
JL		 5058 && TREE_CODE (decl) != FUNCTION_DECL
5059 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5060 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
4144ff62
DE		 5061 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5062 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
cee98a59 5063 {
f5963e61 5064 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
cee98a59
MM		 5065 p->next = extern_head;
5066 p->name = name;
5067 p->size = len;
5068 extern_head = p;
5069 }
5619cc87
JW		 5070
5071#ifdef ASM_OUTPUT_UNDEF_FUNCTION
dd947ed9
RK		 5072 if (TREE_CODE (decl) == FUNCTION_DECL
5073 /* ??? Don't include alloca, since gcc will always expand it
e5e809f4 5074 inline. If we don't do this, the C++ library fails to build. */
9f770b61
JW		 5075 && strcmp (name, "alloca")
5076 /* ??? Don't include __builtin_next_arg, because then gcc will not
5077 bootstrap under Irix 5.1. */
5078 && strcmp (name, "__builtin_next_arg"))
5619cc87 5079 {
f5963e61 5080 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5619cc87
JW		 5081 p->next = extern_head;
5082 p->name = name;
5083 p->size = -1;
5084 extern_head = p;
5085 }
5086#endif
5087
5088 return 0;
5089}
5090
5091#ifdef ASM_OUTPUT_UNDEF_FUNCTION
5092int
5093mips_output_external_libcall (file, name)
5094 FILE *file;
5095 char *name;
5096{
5097 register struct extern_list *p;
5098
f5963e61 5099 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5619cc87
JW		 5100 p->next = extern_head;
5101 p->name = name;
5102 p->size = -1;
5103 extern_head = p;
5104
cee98a59
MM		 5105 return 0;
5106}
5619cc87 5107#endif
cee98a59
MM		 5108\f
5109/* Compute a string to use as a temporary file name. */
5110
147255d8
JW		 5111/* On MSDOS, write temp files in current dir
5112 because there's no place else we can expect to use. */
5113#if __MSDOS__
5114#ifndef P_tmpdir
5115#define P_tmpdir "./"
5116#endif
5117#endif
5118
cee98a59
MM		 5119static FILE *
5120make_temp_file ()
5121{
cee98a59 5122 FILE *stream;
e2fe6aba 5123 const char *base = getenv ("TMPDIR");
cee98a59
MM		 5124 int len;
5125
f5963e61 5126 if (base == 0)
cee98a59
MM		 5127 {
5128#ifdef P_tmpdir
5129 if (access (P_tmpdir, R_OK | W_OK) == 0)
5130 base = P_tmpdir;
5131 else
5132#endif
5133 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5134 base = "/usr/tmp/";
5135 else
5136 base = "/tmp/";
5137 }
5138
5139 len = strlen (base);
147255d8
JW		 5140 /* temp_filename is global, so we must use malloc, not alloca. */
5141 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
cee98a59
MM		 5142 strcpy (temp_filename, base);
5143 if (len > 0 && temp_filename[len-1] != '/')
5144 temp_filename[len++] = '/';
5145
147255d8 5146 strcpy (temp_filename + len, "ctXXXXXX");
cee98a59
MM		 5147 mktemp (temp_filename);
5148
5149 stream = fopen (temp_filename, "w+");
5150 if (!stream)
5151 pfatal_with_name (temp_filename);
5152
147255d8
JW		 5153#ifndef __MSDOS__
5154 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5155 it. Otherwise, we delete it now, so that it will be gone even if the
5156 compiler happens to crash. */
cee98a59 5157 unlink (temp_filename);
147255d8 5158#endif
cee98a59
MM		 5159 return stream;
5160}
cee98a59
MM		 5161\f
5162/* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5163 for .file's that start within a function. If we are smuggling stabs, try to
5164 put out a MIPS ECOFF file and a stab. */
5165
5166void
5167mips_output_filename (stream, name)
5168 FILE *stream;
5169 char *name;
5170{
f5963e61 5171 static int first_time = 1;
cee98a59
MM		 5172 char ltext_label_name[100];
5173
5174 if (first_time)
5175 {
f5963e61 5176 first_time = 0;
cee98a59
MM		 5177 SET_FILE_NUMBER ();
5178 current_function_file = name;
33563487 5179 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
2bacb292 5180 /* This tells mips-tfile that stabs will follow. */
9987501f
MM		 5181 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5182 fprintf (stream, "\t#@stabs\n");
cee98a59
MM		 5183 }
5184
2bacb292 5185 else if (write_symbols == DBX_DEBUG)
cee98a59
MM		 5186 {
5187 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
99107e86
PE		 5188 fprintf (stream, "%s ", ASM_STABS_OP);
5189 output_quoted_string (stream, name);
5190 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
cee98a59
MM		 5191 }
5192
5193 else if (name != current_function_file
5194 && strcmp (name, current_function_file) != 0)
5195 {
5196 if (inside_function && !TARGET_GAS)
5197 {
5198 if (!file_in_function_warning)
5199 {
f5963e61
JL		 5200 file_in_function_warning = 1;
5201 ignore_line_number = 1;
cee98a59
MM		 5202 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5203 }
cee98a59 5204 }
cee98a59
MM		 5205 else
5206 {
5207 SET_FILE_NUMBER ();
5208 current_function_file = name;
33563487 5209 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
cee98a59
MM		 5210 }
5211 }
5212}
cee98a59
MM		 5213\f
5214/* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5215 as well as a .loc, since it is possible that MIPS ECOFF might not be
5216 able to represent the location for inlines that come from a different
5217 file. */
5218
5219void
5220mips_output_lineno (stream, line)
5221 FILE *stream;
5222 int line;
5223{
2bacb292 5224 if (write_symbols == DBX_DEBUG)
cee98a59
MM		 5225 {
5226 ++sym_lineno;
dccc9e85
JW		 5227 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5228 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5229 LOCAL_LABEL_PREFIX, sym_lineno);
cee98a59
MM		 5230 }
5231
5232 else
5233 {
5234 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5235 (ignore_line_number) ? "#" : "",
5236 num_source_filenames, line);
5237
5238 LABEL_AFTER_LOC (stream);
5239 }
5240}
65437fe8 5241\f
f5963e61
JL		 5242/* If defined, a C statement to be executed just prior to the output of
5243 assembler code for INSN, to modify the extracted operands so they will be
5244 output differently.
65437fe8 5245
f5963e61
JL		 5246 Here the argument OPVEC is the vector containing the operands extracted
5247 from INSN, and NOPERANDS is the number of elements of the vector which
5248 contain meaningful data for this insn. The contents of this vector are
5249 what will be used to convert the insn template into assembler code, so you
5250 can change the assembler output by changing the contents of the vector.
65437fe8 5251
f5963e61
JL		 5252 We use it to check if the current insn needs a nop in front of it because
5253 of load delays, and also to update the delay slot statistics. */
65437fe8 5254
85098019
JW		 5255/* ??? There is no real need for this function, because it never actually
5256 emits a NOP anymore. */
5257
65437fe8
MM		 5258void
5259final_prescan_insn (insn, opvec, noperands)
5260 rtx insn;
38831dfe
KG		 5261 rtx opvec[] ATTRIBUTE_UNUSED;
5262 int noperands ATTRIBUTE_UNUSED;
65437fe8
MM		 5263{
5264 if (dslots_number_nops > 0)
5265 {
65437fe8
MM		 5266 rtx pattern = PATTERN (insn);
5267 int length = get_attr_length (insn);
5268
5269 /* Do we need to emit a NOP? */
5270 if (length == 0
f5963e61
JL		 5271 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5272 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5273 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5274 || (mips_load_reg4 != 0
5275 && reg_mentioned_p (mips_load_reg4, pattern)))
85098019 5276 fputs ("\t#nop\n", asm_out_file);
65437fe8
MM		 5277
5278 else
5279 dslots_load_filled++;
5280
5281 while (--dslots_number_nops > 0)
85098019 5282 fputs ("\t#nop\n", asm_out_file);
65437fe8 5283
f5963e61
JL		 5284 mips_load_reg = 0;
5285 mips_load_reg2 = 0;
5286 mips_load_reg3 = 0;
5287 mips_load_reg4 = 0;
65437fe8
MM		 5288 }
5289
f5963e61
JL		 5290 if (TARGET_STATS
5291 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5292 dslots_jump_total++;
65437fe8 5293}
cee98a59
MM		 5294\f
5295/* Output at beginning of assembler file.
f5963e61
JL		 5296
5297 If we are optimizing to use the global pointer, create a temporary file to
5298 hold all of the text stuff, and write it out to the end. This is needed
5299 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5300 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5301 processed, it generates a two instruction sequence. */
cee98a59
MM		 5302
5303void
5304mips_asm_file_start (stream)
5305 FILE *stream;
5306{
5307 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5308
f5963e61
JL		 5309 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5310 inside of a .set noreorder section jumps to a label outside of the .set
5311 noreorder section. Revision 2.20 just set nobopt silently rather than
5312 fixing the bug. */
cee98a59
MM		 5313
5314 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5315 fprintf (stream, "\t.set\tnobopt\n");
5316
ffa9d0b1 5317 /* Generate the pseudo ops that System V.4 wants. */
c388a0c4
RS		 5318#ifndef ABICALLS_ASM_OP
5319#define ABICALLS_ASM_OP ".abicalls"
5320#endif
cee98a59 5321 if (TARGET_ABICALLS)
ffa9d0b1 5322 /* ??? but do not want this (or want pic0) if -non-shared? */
c388a0c4 5323 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
cee98a59 5324
2bcb2ab3
GK		 5325 if (TARGET_MIPS16)
5326 fprintf (stream, "\t.set\tmips16\n");
5327
33563487
JW		 5328 /* Start a section, so that the first .popsection directive is guaranteed
5329 to have a previously defined section to pop back to. */
a53f72db 5330 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
33563487
JW		 5331 fprintf (stream, "\t.section\t.text\n");
5332
d7a58f30 5333 /* This code exists so that we can put all externs before all symbol
d46c6fce 5334 references. This is necessary for the MIPS assembler's global pointer
d7a58f30 5335 optimizations to work. */
2bcb2ab3 5336 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
cee98a59
MM		 5337 {
5338 asm_out_data_file = stream;
5339 asm_out_text_file = make_temp_file ();
5340 }
f5963e61 5341
cee98a59
MM		 5342 else
5343 asm_out_data_file = asm_out_text_file = stream;
5344
2096c147
DE		 5345 if (flag_verbose_asm)
5346 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5347 ASM_COMMENT_START,
5348 mips_section_threshold, mips_cpu_string, mips_isa);
cee98a59 5349}
cee98a59 5350\f
f5963e61
JL		 5351/* If we are optimizing the global pointer, emit the text section now and any
5352 small externs which did not have .comm, etc that are needed. Also, give a
5353 warning if the data area is more than 32K and -pic because 3 instructions
5354 are needed to reference the data pointers. */
cee98a59
MM		 5355
5356void
5357mips_asm_file_end (file)
5358 FILE *file;
5359{
5360 char buffer[8192];
5361 tree name_tree;
5362 struct extern_list *p;
5363 int len;
842eb20e
MM		 5364
5365 if (HALF_PIC_P ())
6e92f4b6
KG		 5366 {
5367 HALF_PIC_FINISH (file);
5368 }
cee98a59 5369
5619cc87 5370 if (extern_head)
cee98a59 5371 {
5619cc87 5372 fputs ("\n", file);
cee98a59
MM		 5373
5374 for (p = extern_head; p != 0; p = p->next)
5375 {
5376 name_tree = get_identifier (p->name);
c831afd5
MM		 5377
5378 /* Positively ensure only one .extern for any given symbol. */
5379 if (! TREE_ASM_WRITTEN (name_tree))
cee98a59 5380 {
c831afd5 5381 TREE_ASM_WRITTEN (name_tree) = 1;
5619cc87
JW		 5382#ifdef ASM_OUTPUT_UNDEF_FUNCTION
5383 if (p->size == -1)
5384 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
5385 else
5386#endif
5387 {
5388 fputs ("\t.extern\t", file);
5389 assemble_name (file, p->name);
5390 fprintf (file, ", %d\n", p->size);
5391 }
cee98a59
MM		 5392 }
5393 }
5619cc87
JW		 5394 }
5395
2bcb2ab3 5396 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5619cc87 5397 {
cee98a59
MM		 5398 fprintf (file, "\n\t.text\n");
5399 rewind (asm_out_text_file);
5400 if (ferror (asm_out_text_file))
c831afd5 5401 fatal_io_error (temp_filename);
cee98a59
MM		 5402
5403 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
973838fd 5404 if ((int) fwrite (buffer, 1, len, file) != len)
c831afd5 5405 pfatal_with_name (asm_file_name);
cee98a59
MM		 5406
5407 if (len < 0)
c831afd5 5408 pfatal_with_name (temp_filename);
cee98a59
MM		 5409
5410 if (fclose (asm_out_text_file) != 0)
c831afd5 5411 pfatal_with_name (temp_filename);
147255d8
JW		 5412
5413#ifdef __MSDOS__
5414 unlink (temp_filename);
5415#endif
cee98a59
MM		 5416 }
5417}
5418
f5963e61
JL		 5419/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
5420 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
9987501f
MM		 5421
5422void
5423mips_declare_object (stream, name, init_string, final_string, size)
5424 FILE *stream;
5425 char *name;
5426 char *init_string;
5427 char *final_string;
5428 int size;
5429{
5430 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5431 assemble_name (stream, name);
5432 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5433
147255d8 5434 if (TARGET_GP_OPT)
9987501f
MM		 5435 {
5436 tree name_tree = get_identifier (name);
5437 TREE_ASM_WRITTEN (name_tree) = 1;
5438 }
5439}
dbe9742d
MM		 5440\f
5441/* Output a double precision value to the assembler. If both the
5442 host and target are IEEE, emit the values in hex. */
5443
5444void
5445mips_output_double (stream, value)
5446 FILE *stream;
5447 REAL_VALUE_TYPE value;
5448{
5449#ifdef REAL_VALUE_TO_TARGET_DOUBLE
5450 long value_long[2];
5451 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
5452
5453 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5454 value_long[0], value, value_long[1]);
5455#else
5456 fprintf (stream, "\t.double\t%.20g\n", value);
5457#endif
5458}
5459
dbe9742d
MM		 5460/* Output a single precision value to the assembler. If both the
5461 host and target are IEEE, emit the values in hex. */
5462
5463void
5464mips_output_float (stream, value)
5465 FILE *stream;
5466 REAL_VALUE_TYPE value;
5467{
5468#ifdef REAL_VALUE_TO_TARGET_SINGLE
5469 long value_long;
5470 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
5471
5472 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
5473#else
5474 fprintf (stream, "\t.float\t%.12g\n", value);
5475#endif
5476}
cee98a59
MM		 5477\f
5478/* Return the bytes needed to compute the frame pointer from the current
5479 stack pointer.
5480
5481 Mips stack frames look like:
5482
5483 Before call After call
5484 +-----------------------+ +-----------------------+
5485 high | | | |
5486 mem. | | | |
5487 | caller's temps. | | caller's temps. |
5488 | | | |
5489 +-----------------------+ +-----------------------+
5490 | | | |
5491 | arguments on stack. | | arguments on stack. |
5492 | | | |
5493 +-----------------------+ +-----------------------+
5494 | 4 words to save | | 4 words to save |
5495 | arguments passed | | arguments passed |
5496 | in registers, even | | in registers, even |
ffa9d0b1 5497 SP->| if not passed. | VFP->| if not passed. |
cee98a59 5498 +-----------------------+ +-----------------------+
cee98a59
MM		 5499 | |
5500 | fp register save |
5501 | |
5502 +-----------------------+
5503 | |
5504 | gp register save |
5505 | |
5506 +-----------------------+
5507 | |
ab78d4a8
MM		 5508 | local variables |
5509 | |
5510 +-----------------------+
5511 | |
cee98a59
MM		 5512 | alloca allocations |
5513 | |
5514 +-----------------------+
5515 | |
ffa9d0b1
JW		 5516 | GP save for V.4 abi |
5517 | |
5518 +-----------------------+
5519 | |
cee98a59
MM		 5520 | arguments on stack |
5521 | |
5522 +-----------------------+
5523 | 4 words to save |
5524 | arguments passed |
5525 | in registers, even |
5526 low SP->| if not passed. |
5527 memory +-----------------------+
5528
5529*/
5530
f5963e61 5531HOST_WIDE_INT
cee98a59 5532compute_frame_size (size)
db4c1c35 5533 HOST_WIDE_INT size; /* # of var. bytes allocated */
cee98a59
MM		 5534{
5535 int regno;
f5963e61
JL		 5536 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5537 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5538 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5539 HOST_WIDE_INT extra_size; /* # extra bytes */
5540 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5541 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5542 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
7bea35e7
MM		 5543 long mask; /* mask of saved gp registers */
5544 long fmask; /* mask of saved fp registers */
5545 int fp_inc; /* 1 or 2 depending on the size of fp regs */
5546 long fp_bits; /* bitmask to use for each fp register */
cee98a59 5547
f5963e61
JL		 5548 gp_reg_size = 0;
5549 fp_reg_size = 0;
5550 mask = 0;
5551 fmask = 0;
5552 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
5553 var_size = MIPS_STACK_ALIGN (size);
5554 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
ab78d4a8
MM		 5555
5556 /* The MIPS 3.0 linker does not like functions that dynamically
5557 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5558 looks like we are trying to create a second frame pointer to the
5559 function, so allocate some stack space to make it happy. */
5560
5561 if (args_size == 0 && current_function_calls_alloca)
f5963e61 5562 args_size = 4 * UNITS_PER_WORD;
ab78d4a8
MM		 5563
5564 total_size = var_size + args_size + extra_size;
cee98a59
MM		 5565
5566 /* Calculate space needed for gp registers. */
5567 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5568 {
2bcb2ab3
GK		 5569 /* $18 is a special case on the mips16. It may be used to call
5570 a function which returns a floating point value, but it is
5571 marked in call_used_regs. $31 is also a special case. When
5572 not using -mentry, it will be used to copy a return value
5573 into the floating point registers if the return value is
5574 floating point. */
5575 if (MUST_SAVE_REGISTER (regno)
5576 || (TARGET_MIPS16
5577 && regno == GP_REG_FIRST + 18
5578 && regs_ever_live[regno])
5579 || (TARGET_MIPS16
5580 && regno == GP_REG_FIRST + 31
5581 && mips16_hard_float
5582 && ! mips_entry
5583 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
5584 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
5585 == MODE_FLOAT)
5586 && (! TARGET_SINGLE_FLOAT
5587 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
5588 <= 4))))
cee98a59 5589 {
bfed8dac 5590 gp_reg_size += GET_MODE_SIZE (gpr_mode);
7bea35e7 5591 mask |= 1L << (regno - GP_REG_FIRST);
2bcb2ab3
GK		 5592
5593 /* The entry and exit pseudo instructions can not save $17
5594 without also saving $16. */
5595 if (mips_entry
5596 && regno == GP_REG_FIRST + 17
5597 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
5598 {
5599 gp_reg_size += UNITS_PER_WORD;
5600 mask |= 1L << 16;
5601 }
cee98a59
MM		 5602 }
5603 }
5604
5605 /* Calculate space needed for fp registers. */
46299de9 5606 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
cee98a59
MM		 5607 {
5608 fp_inc = 1;
5609 fp_bits = 1;
5610 }
5611 else
5612 {
5613 fp_inc = 2;
5614 fp_bits = 3;
5615 }
5616
d1d3a2df
JL		 5617 /* This loop must iterate over the same space as its companion in
5618 save_restore_regs. */
5619 for (regno = (FP_REG_LAST - fp_inc + 1);
5620 regno >= FP_REG_FIRST;
5621 regno -= fp_inc)
cee98a59
MM		 5622 {
5623 if (regs_ever_live[regno] && !call_used_regs[regno])
5624 {
147255d8 5625 fp_reg_size += fp_inc * UNITS_PER_FPREG;
cee98a59
MM		 5626 fmask |= fp_bits << (regno - FP_REG_FIRST);
5627 }
5628 }
5629
5630 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
46299de9 5631 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
cee98a59 5632
33563487
JW		 5633 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
5634 for leaf routines (total_size == extra_size) to save the gp reg.
5635 The gp reg is callee saved in the 64 bit ABI, so all routines must
a944a4eb
JW		 5636 save the gp reg. This is not a leaf routine if -p, because of the
5637 call to mcount. */
a53f72db
GRK		 5638 if (total_size == extra_size
5639 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
a944a4eb 5640 && ! profile_flag)
cee98a59 5641 total_size = extra_size = 0;
ffa9d0b1
JW		 5642 else if (TARGET_ABICALLS)
5643 {
5644 /* Add the context-pointer to the saved registers. */
5645 gp_reg_size += UNITS_PER_WORD;
5646 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
5647 total_size -= gp_reg_rounded;
5648 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5649 total_size += gp_reg_rounded;
5650 }
cee98a59 5651
33563487
JW		 5652 /* Add in space reserved on the stack by the callee for storing arguments
5653 passed in registers. */
a53f72db 5654 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
33563487
JW		 5655 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5656
2bcb2ab3
GK		 5657 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
5658 if (mips_entry && total_size > 0 && total_size < 32)
5659 total_size = 32;
5660
cee98a59 5661 /* Save other computed information. */
f5963e61
JL		 5662 current_frame_info.total_size = total_size;
5663 current_frame_info.var_size = var_size;
5664 current_frame_info.args_size = args_size;
5665 current_frame_info.extra_size = extra_size;
cee98a59
MM		 5666 current_frame_info.gp_reg_size = gp_reg_size;
5667 current_frame_info.fp_reg_size = fp_reg_size;
f5963e61
JL		 5668 current_frame_info.mask = mask;
5669 current_frame_info.fmask = fmask;
cee98a59 5670 current_frame_info.initialized = reload_completed;
f5963e61
JL		 5671 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
5672 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
cee98a59
MM		 5673
5674 if (mask)
5675 {
2bcb2ab3
GK		 5676 unsigned long offset;
5677
5678 /* When using mips_entry, the registers are always saved at the
5679 top of the stack. */
5680 if (! mips_entry)
5681 offset = (args_size + extra_size + var_size
bfed8dac 5682 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
2bcb2ab3 5683 else
bfed8dac
JL		 5684 offset = total_size - GET_MODE_SIZE (gpr_mode);
5685
cee98a59
MM		 5686 current_frame_info.gp_sp_offset = offset;
5687 current_frame_info.gp_save_offset = offset - total_size;
5688 }
258d81a8
MM		 5689 else
5690 {
5691 current_frame_info.gp_sp_offset = 0;
5692 current_frame_info.gp_save_offset = 0;
5693 }
5694
cee98a59
MM		 5695 if (fmask)
5696 {
147255d8
JW		 5697 unsigned long offset = (args_size + extra_size + var_size
5698 + gp_reg_rounded + fp_reg_size
5699 - fp_inc * UNITS_PER_FPREG);
cee98a59 5700 current_frame_info.fp_sp_offset = offset;
a94dbf2c 5701 current_frame_info.fp_save_offset = offset - total_size;
cee98a59 5702 }
258d81a8
MM		 5703 else
5704 {
5705 current_frame_info.fp_sp_offset = 0;
5706 current_frame_info.fp_save_offset = 0;
5707 }
cee98a59
MM		 5708
5709 /* Ok, we're done. */
5710 return total_size;
5711}
cee98a59 5712\f
7bea35e7
MM		 5713/* Common code to emit the insns (or to write the instructions to a file)
5714 to save/restore registers.
cee98a59 5715
7bea35e7
MM		 5716 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
5717 is not modified within save_restore_insns. */
5718
f5963e61 5719#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
7bea35e7
MM		 5720
5721static void
5722save_restore_insns (store_p, large_reg, large_offset, file)
f5963e61
JL		 5723 int store_p; /* true if this is prologue */
5724 rtx large_reg; /* register holding large offset constant or NULL */
5725 long large_offset; /* large constant offset value */
5726 FILE *file; /* file to write instructions instead of making RTL */
cee98a59 5727{
f5963e61
JL		 5728 long mask = current_frame_info.mask;
5729 long fmask = current_frame_info.fmask;
cee98a59 5730 int regno;
7bea35e7 5731 rtx base_reg_rtx;
f5963e61
JL		 5732 HOST_WIDE_INT base_offset;
5733 HOST_WIDE_INT gp_offset;
5734 HOST_WIDE_INT fp_offset;
5735 HOST_WIDE_INT end_offset;
141719a8 5736 rtx insn;
7bea35e7 5737
f5963e61 5738 if (frame_pointer_needed
1b15c5de 5739 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
7bea35e7 5740 abort ();
cee98a59
MM		 5741
5742 if (mask == 0 && fmask == 0)
5743 return;
5744
f5963e61
JL		 5745 /* Save registers starting from high to low. The debuggers prefer at least
5746 the return register be stored at func+4, and also it allows us not to
5747 need a nop in the epilog if at least one register is reloaded in
5748 addition to return address. */
cee98a59 5749
7bea35e7
MM		 5750 /* Save GP registers if needed. */
5751 if (mask)
cee98a59 5752 {
f5963e61
JL		 5753 /* Pick which pointer to use as a base register. For small frames, just
5754 use the stack pointer. Otherwise, use a temporary register. Save 2
5755 cycles if the save area is near the end of a large frame, by reusing
5756 the constant created in the prologue/epilogue to adjust the stack
5757 frame. */
cee98a59 5758
f5963e61
JL		 5759 gp_offset = current_frame_info.gp_sp_offset;
5760 end_offset
bfed8dac
JL		 5761 = gp_offset - (current_frame_info.gp_reg_size
5762 - GET_MODE_SIZE (gpr_mode));
7bea35e7
MM		 5763
5764 if (gp_offset < 0 || end_offset < 0)
5765 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
38831dfe 5766 (long) gp_offset, (long) end_offset);
7bea35e7 5767
2bcb2ab3
GK		 5768 /* If we see a large frame in mips16 mode, we save the registers
5769 before adjusting the stack pointer, and load them afterward. */
5770 else if (TARGET_MIPS16 && large_offset > 32767)
f5963e61 5771 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
2bcb2ab3 5772
7bea35e7 5773 else if (gp_offset < 32768)
f5963e61 5774 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
cee98a59 5775
f5963e61
JL		 5776 else if (large_reg != 0
5777 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
5778 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7bea35e7 5779 {
c5c76735 5780 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 5781 base_offset = large_offset;
5782 if (file == 0)
147255d8 5783 {
1eeed24e 5784 if (Pmode == DImode)
f5963e61
JL		 5785 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
5786 stack_pointer_rtx));
147255d8 5787 else
f5963e61
JL		 5788 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
5789 stack_pointer_rtx));
4b7e467b
JW		 5790 if (store_p)
5791 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 5792 }
7bea35e7 5793 else
147255d8 5794 fprintf (file, "\t%s\t%s,%s,%s\n",
1eeed24e 5795 Pmode == DImode ? "daddu" : "addu",
7bea35e7
MM		 5796 reg_names[MIPS_TEMP2_REGNUM],
5797 reg_names[REGNO (large_reg)],
5798 reg_names[STACK_POINTER_REGNUM]);
5799 }
cee98a59 5800
7bea35e7 5801 else
cee98a59 5802 {
c5c76735 5803 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 5804 base_offset = gp_offset;
5805 if (file == 0)
cee98a59 5806 {
218c2cdb
JW		 5807 rtx gp_offset_rtx = GEN_INT (gp_offset);
5808
5809 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5810 bit, so make sure that we don't emit anything that can be
5811 split. */
5812 /* ??? There is no DImode ori immediate pattern, so we can only
5813 do this for 32 bit code. */
5814 if (large_int (gp_offset_rtx)
5815 && GET_MODE (base_reg_rtx) == SImode)
5816 {
5817 insn = emit_move_insn (base_reg_rtx,
5818 GEN_INT (gp_offset & 0xffff0000));
5819 if (store_p)
5820 RTX_FRAME_RELATED_P (insn) = 1;
f5963e61
JL		 5821 insn
5822 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
5823 GEN_INT (gp_offset & 0x0000ffff)));
218c2cdb
JW		 5824 if (store_p)
5825 RTX_FRAME_RELATED_P (insn) = 1;
5826 }
5827 else
5828 {
5829 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
5830 if (store_p)
5831 RTX_FRAME_RELATED_P (insn) = 1;
5832 }
5833
1eeed24e 5834 if (Pmode == DImode)
f5963e61
JL		 5835 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
5836 stack_pointer_rtx));
147255d8 5837 else
f5963e61
JL		 5838 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
5839 stack_pointer_rtx));
4b7e467b
JW		 5840 if (store_p)
5841 RTX_FRAME_RELATED_P (insn) = 1;
cee98a59 5842 }
7bea35e7 5843 else
38831dfe
KG		 5844 {
5845 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
e51712db 5846 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
38831dfe
KG		 5847 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
5848 fprintf (file, "\n\t%s\t%s,%s,%s\n",
5849 Pmode == DImode ? "daddu" : "addu",
5850 reg_names[MIPS_TEMP2_REGNUM],
5851 reg_names[MIPS_TEMP2_REGNUM],
5852 reg_names[STACK_POINTER_REGNUM]);
5853 }
cee98a59 5854 }
0fb5ac6f 5855
2bcb2ab3
GK		 5856 /* When we restore the registers in MIPS16 mode, then if we are
5857 using a frame pointer, and this is not a large frame, the
5858 current stack pointer will be offset by
5859 current_function_outgoing_args_size. Doing it this way lets
5860 us avoid offsetting the frame pointer before copying it into
5861 the stack pointer; there is no instruction to set the stack
5862 pointer to the sum of a register and a constant. */
5863 if (TARGET_MIPS16
5864 && ! store_p
5865 && frame_pointer_needed
5866 && large_offset <= 32767)
5867 base_offset += current_function_outgoing_args_size;
5868
5869 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
f5963e61
JL		 5870 if (BITSET_P (mask, regno - GP_REG_FIRST))
5871 {
5872 if (file == 0)
5873 {
5874 rtx reg_rtx;
5875 rtx mem_rtx
bfed8dac 5876 = gen_rtx (MEM, gpr_mode,
f5963e61
JL		 5877 gen_rtx (PLUS, Pmode, base_reg_rtx,
5878 GEN_INT (gp_offset - base_offset)));
5879
5880 RTX_UNCHANGING_P (mem_rtx) = 1;
5881
5882 /* The mips16 does not have an instruction to load
5883 $31, so we load $7 instead, and work things out
5884 in the caller. */
5885 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
bfed8dac 5886 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
f5963e61
JL		 5887 /* The mips16 sometimes needs to save $18. */
5888 else if (TARGET_MIPS16
5889 && regno != GP_REG_FIRST + 31
5890 && ! M16_REG_P (regno))
5891 {
5892 if (! store_p)
bfed8dac 5893 reg_rtx = gen_rtx (REG, gpr_mode, 6);
f5963e61
JL		 5894 else
5895 {
bfed8dac 5896 reg_rtx = gen_rtx (REG, gpr_mode, 3);
f5963e61 5897 emit_move_insn (reg_rtx,
bfed8dac 5898 gen_rtx (REG, gpr_mode, regno));
f5963e61
JL		 5899 }
5900 }
5901 else
bfed8dac 5902 reg_rtx = gen_rtx (REG, gpr_mode, regno);
f5963e61
JL		 5903
5904 if (store_p)
5905 {
5906 insn = emit_move_insn (mem_rtx, reg_rtx);
5907 RTX_FRAME_RELATED_P (insn) = 1;
5908 }
a53f72db
GRK		 5909 else if (!TARGET_ABICALLS
5910 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
f5963e61
JL		 5911 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5912 {
5913 emit_move_insn (reg_rtx, mem_rtx);
5914 if (TARGET_MIPS16
5915 && regno != GP_REG_FIRST + 31
5916 && ! M16_REG_P (regno))
bfed8dac 5917 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
f5963e61
JL		 5918 reg_rtx);
5919 }
5920 }
5921 else
5922 {
a53f72db
GRK		 5923 if (store_p || !TARGET_ABICALLS
5924 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
f5963e61
JL		 5925 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5926 {
5927 int r = regno;
5928
5929 /* The mips16 does not have an instruction to
5930 load $31, so we load $7 instead, and work
5931 things out in the caller. */
5932 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
5933 r = GP_REG_FIRST + 7;
2bcb2ab3 5934 /* The mips16 sometimes needs to save $18. */
f5963e61
JL		 5935 if (TARGET_MIPS16
5936 && regno != GP_REG_FIRST + 31
5937 && ! M16_REG_P (regno))
5938 {
5939 if (! store_p)
5940 r = GP_REG_FIRST + 6;
5941 else
5942 {
5943 r = GP_REG_FIRST + 3;
5944 fprintf (file, "\tmove\t%s,%s\n",
5945 reg_names[r], reg_names[regno]);
5946 }
5947 }
38831dfe 5948 fprintf (file, "\t%s\t%s,",
f5963e61
JL		 5949 (TARGET_64BIT
5950 ? (store_p) ? "sd" : "ld"
5951 : (store_p) ? "sw" : "lw"),
38831dfe
KG		 5952 reg_names[r]);
5953 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5954 gp_offset - base_offset);
5955 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
f5963e61
JL		 5956 if (! store_p
5957 && TARGET_MIPS16
5958 && regno != GP_REG_FIRST + 31
5959 && ! M16_REG_P (regno))
5960 fprintf (file, "\tmove\t%s,%s\n",
5961 reg_names[regno], reg_names[r]);
5962 }
5963
5964 }
bfed8dac 5965 gp_offset -= GET_MODE_SIZE (gpr_mode);
f5963e61 5966 }
0fb5ac6f 5967 }
7bea35e7 5968 else
f5963e61 5969 base_reg_rtx = 0, base_offset = 0;
0fb5ac6f 5970
7bea35e7 5971 /* Save floating point registers if needed. */
0fb5ac6f
MM		 5972 if (fmask)
5973 {
46299de9 5974 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
147255d8 5975 int fp_size = fp_inc * UNITS_PER_FPREG;
0fb5ac6f 5976
7bea35e7 5977 /* Pick which pointer to use as a base register. */
f5963e61 5978 fp_offset = current_frame_info.fp_sp_offset;
147255d8 5979 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
7bea35e7
MM		 5980
5981 if (fp_offset < 0 || end_offset < 0)
5982 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
38831dfe 5983 (long) fp_offset, (long) end_offset);
7bea35e7
MM		 5984
5985 else if (fp_offset < 32768)
f5963e61 5986 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
7bea35e7 5987
f5963e61
JL		 5988 else if (base_reg_rtx != 0
5989 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
5990 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
5991 ; /* already set up for gp registers above */
7bea35e7 5992
f5963e61
JL		 5993 else if (large_reg != 0
5994 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
5995 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7bea35e7 5996 {
c5c76735 5997 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 5998 base_offset = large_offset;
5999 if (file == 0)
147255d8 6000 {
1eeed24e 6001 if (Pmode == DImode)
f5963e61
JL		 6002 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6003 stack_pointer_rtx));
147255d8 6004 else
f5963e61
JL		 6005 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6006 stack_pointer_rtx));
4b7e467b
JW		 6007 if (store_p)
6008 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 6009 }
f5963e61 6010
7bea35e7 6011 else
147255d8 6012 fprintf (file, "\t%s\t%s,%s,%s\n",
1eeed24e 6013 Pmode == DImode ? "daddu" : "addu",
7bea35e7
MM		 6014 reg_names[MIPS_TEMP2_REGNUM],
6015 reg_names[REGNO (large_reg)],
6016 reg_names[STACK_POINTER_REGNUM]);
6017 }
6018
6019 else
6020 {
c5c76735 6021 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 6022 base_offset = fp_offset;
6023 if (file == 0)
7bea35e7 6024 {
218c2cdb
JW		 6025 rtx fp_offset_rtx = GEN_INT (fp_offset);
6026
6027 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6028 bit, so make sure that we don't emit anything that can be
6029 split. */
6030 /* ??? There is no DImode ori immediate pattern, so we can only
6031 do this for 32 bit code. */
6032 if (large_int (fp_offset_rtx)
6033 && GET_MODE (base_reg_rtx) == SImode)
6034 {
6035 insn = emit_move_insn (base_reg_rtx,
6036 GEN_INT (fp_offset & 0xffff0000));
6037 if (store_p)
6038 RTX_FRAME_RELATED_P (insn) = 1;
6039 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6040 GEN_INT (fp_offset & 0x0000ffff)));
6041 if (store_p)
6042 RTX_FRAME_RELATED_P (insn) = 1;
6043 }
6044 else
6045 {
6046 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6047 if (store_p)
6048 RTX_FRAME_RELATED_P (insn) = 1;
6049 }
6050
4b7e467b
JW		 6051 if (store_p)
6052 RTX_FRAME_RELATED_P (insn) = 1;
1eeed24e 6053 if (Pmode == DImode)
f5963e61
JL		 6054 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6055 stack_pointer_rtx));
147255d8 6056 else
f5963e61
JL		 6057 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6058 stack_pointer_rtx));
4b7e467b
JW		 6059 if (store_p)
6060 RTX_FRAME_RELATED_P (insn) = 1;
7bea35e7
MM		 6061 }
6062 else
38831dfe
KG		 6063 {
6064 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
e51712db 6065 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
38831dfe
KG		 6066 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6067 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6068 Pmode == DImode ? "daddu" : "addu",
6069 reg_names[MIPS_TEMP2_REGNUM],
6070 reg_names[MIPS_TEMP2_REGNUM],
6071 reg_names[STACK_POINTER_REGNUM]);
6072 }
7bea35e7
MM		 6073 }
6074
d1d3a2df
JL		 6075 /* This loop must iterate over the same space as its companion in
6076 compute_frame_size. */
6077 for (regno = (FP_REG_LAST - fp_inc + 1);
6078 regno >= FP_REG_FIRST;
6079 regno -= fp_inc)
f5963e61
JL		 6080 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6081 {
6082 if (file == 0)
6083 {
6084 enum machine_mode sz
6085 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6086 rtx reg_rtx = gen_rtx (REG, sz, regno);
6087 rtx mem_rtx = gen_rtx (MEM, sz,
6088 gen_rtx (PLUS, Pmode, base_reg_rtx,
6089 GEN_INT (fp_offset
6090 - base_offset)));
6091 RTX_UNCHANGING_P (mem_rtx) = 1;
6092
6093 if (store_p)
6094 {
6095 insn = emit_move_insn (mem_rtx, reg_rtx);
6096 RTX_FRAME_RELATED_P (insn) = 1;
6097 }
6098 else
6099 emit_move_insn (reg_rtx, mem_rtx);
6100 }
6101 else
38831dfe
KG		 6102 {
6103 fprintf (file, "\t%s\t%s,",
6104 (TARGET_SINGLE_FLOAT
6105 ? (store_p ? "s.s" : "l.s")
6106 : (store_p ? "s.d" : "l.d")),
6107 reg_names[regno]);
6108 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6109 fp_offset - base_offset);
6110 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6111 }
f5963e61
JL		 6112
6113 fp_offset -= fp_size;
6114 }
0fb5ac6f
MM		 6115 }
6116}
cee98a59
MM		 6117\f
6118/* Set up the stack and frame (if desired) for the function. */
6119
6120void
6121function_prologue (file, size)
6122 FILE *file;
38831dfe 6123 int size ATTRIBUTE_UNUSED;
cee98a59 6124{
6e92f4b6 6125#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52 6126 char *fnname;
6e92f4b6 6127#endif
7bea35e7 6128 long tsize = current_frame_info.total_size;
cee98a59
MM		 6129
6130 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
8a2d2f90 6131
8bd8e198 6132#ifdef SDB_DEBUGGING_INFO
af173031 6133 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8a2d2f90 6134 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8bd8e198 6135#endif
cee98a59 6136
2bcb2ab3
GK		 6137 /* In mips16 mode, we may need to generate a 32 bit to handle
6138 floating point arguments. The linker will arrange for any 32 bit
6139 functions to call this stub, which will then jump to the 16 bit
6140 function proper. */
6141 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6142 && current_function_args_info.fp_code != 0)
6143 build_mips16_function_stub (file);
6144
993cd990
JW		 6145 inside_function = 1;
6146
6147#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52
RK		 6148 /* Get the function name the same way that toplev.c does before calling
6149 assemble_start_function. This is needed so that the name used here
6150 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6151 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6152
e9a25f70
JL		 6153 if (!flag_inhibit_size_directive)
6154 {
6155 fputs ("\t.ent\t", file);
6156 assemble_name (file, fnname);
6157 fputs ("\n", file);
6158 }
7bea35e7 6159
10389f52 6160 assemble_name (file, fnname);
cee98a59 6161 fputs (":\n", file);
993cd990 6162#endif
cee98a59 6163
e9a25f70
JL		 6164 if (!flag_inhibit_size_directive)
6165 {
a50f2a09 6166 /* .frame FRAMEREG, FRAMESIZE, RETREG */
f5963e61
JL		 6167 fprintf (file,
6168 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6169 (reg_names[(frame_pointer_needed)
6170 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
a50f2a09
AC		 6171 ((frame_pointer_needed && TARGET_MIPS16)
6172 ? (tsize - current_function_outgoing_args_size)
6173 : tsize),
6174 reg_names[31 + GP_REG_FIRST],
f5963e61
JL		 6175 current_frame_info.var_size,
6176 current_frame_info.num_gp,
6177 current_frame_info.num_fp,
6178 current_function_outgoing_args_size,
6179 current_frame_info.extra_size);
e9a25f70 6180
a50f2a09 6181 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
3afaa6e8 6182 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
e9a25f70 6183 current_frame_info.mask,
a50f2a09 6184 current_frame_info.gp_save_offset,
e9a25f70
JL		 6185 current_frame_info.fmask,
6186 current_frame_info.fp_save_offset);
a50f2a09
AC		 6187
6188 /* Require:
6189 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6190 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
e9a25f70 6191 }
ffa9d0b1 6192
2bcb2ab3
GK		 6193 if (mips_entry && ! mips_can_use_return_insn ())
6194 {
6195 int save16 = BITSET_P (current_frame_info.mask, 16);
6196 int save17 = BITSET_P (current_frame_info.mask, 17);
6197 int save31 = BITSET_P (current_frame_info.mask, 31);
6198 int savearg = 0;
6199 rtx insn;
6200
6201 /* Look through the initial insns to see if any of them store
6202 the function parameters into the incoming parameter storage
6203 area. If they do, we delete the insn, and save the register
6204 using the entry pseudo-instruction instead. We don't try to
6205 look past a label, jump, or call. */
6206 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6207 {
6208 rtx note, set, src, dest, base, offset;
6209 int hireg;
6210
6211 if (GET_CODE (insn) == CODE_LABEL
6212 || GET_CODE (insn) == JUMP_INSN
6213 || GET_CODE (insn) == CALL_INSN)
6214 break;
6215 if (GET_CODE (insn) != INSN)
6216 continue;
6217 set = PATTERN (insn);
6218 if (GET_CODE (set) != SET)
6219 continue;
6220
6221 /* An insn storing a function parameter will still have a
6222 REG_EQUIV note on it mentioning the argument pointer. */
6223 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6224 if (note == NULL_RTX)
6225 continue;
6226 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6227 continue;
6228
6229 src = SET_SRC (set);
6230 if (GET_CODE (src) != REG
6231 || REGNO (src) < GP_REG_FIRST + 4
6232 || REGNO (src) > GP_REG_FIRST + 7)
6233 continue;
6234
6235 dest = SET_DEST (set);
6236 if (GET_CODE (dest) != MEM)
6237 continue;
6238 if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
6239 ;
6240 else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
6241 && REGNO (src) < GP_REG_FIRST + 7)
6242 ;
6243 else
6244 continue;
6245 offset = const0_rtx;
6246 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6247 if (GET_CODE (base) != REG
6248 || GET_CODE (offset) != CONST_INT)
6249 continue;
6250 if (REGNO (base) == STACK_POINTER_REGNUM
6251 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6252 ;
6253 else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
6254 && (INTVAL (offset)
6255 == (tsize
6256 + (REGNO (src) - 4) * UNITS_PER_WORD
6257 - current_function_outgoing_args_size)))
6258 ;
6259 else
6260 continue;
6261
6262 /* This insn stores a parameter onto the stack, in the same
6263 location where the entry pseudo-instruction will put it.
6264 Delete the insn, and arrange to tell the entry
6265 instruction to save the register. */
6266 PUT_CODE (insn, NOTE);
6267 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6268 NOTE_SOURCE_FILE (insn) = 0;
6269
6270 hireg = (REGNO (src)
6271 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6272 - 1);
6273 if (hireg > savearg)
6274 savearg = hireg;
6275 }
6276
6277 /* If this is a varargs function, we need to save all the
6278 registers onto the stack anyhow. */
6279 if (current_function_stdarg || current_function_varargs)
6280 savearg = GP_REG_FIRST + 7;
6281
6282 fprintf (file, "\tentry\t");
6283 if (savearg > 0)
6284 {
6285 if (savearg == GP_REG_FIRST + 4)
6286 fprintf (file, "%s", reg_names[savearg]);
6287 else
6288 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6289 reg_names[savearg]);
6290 }
6291 if (save16 || save17)
6292 {
6293 if (savearg > 0)
6294 fprintf (file, ",");
6295 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6296 if (save17)
6297 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6298 }
6299 if (save31)
6300 {
6301 if (savearg > 0 || save16 || save17)
6302 fprintf (file, ",");
6303 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6304 }
6305 fprintf (file, "\n");
6306 }
6307
a53f72db 6308 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
ffa9d0b1
JW		 6309 {
6310 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6311
6312 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6313 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6314 if (tsize > 0)
6315 {
3afaa6e8 6316 fprintf (file, "\t%s\t%s,%s,%ld\n",
1eeed24e 6317 (Pmode == DImode ? "dsubu" : "subu"),
147255d8 6318 sp_str, sp_str, tsize);
3afaa6e8 6319 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
ffa9d0b1 6320 }
0021b564
JM		 6321
6322 if (dwarf2out_do_frame ())
6323 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
ffa9d0b1 6324 }
0fb5ac6f 6325}
0fb5ac6f
MM		 6326\f
6327/* Expand the prologue into a bunch of separate insns. */
6328
6329void
6330mips_expand_prologue ()
6331{
6332 int regno;
f5963e61
JL		 6333 HOST_WIDE_INT tsize;
6334 rtx tmp_rtx = 0;
6335 char *arg_name = 0;
6336 tree fndecl = current_function_decl;
6337 tree fntype = TREE_TYPE (fndecl);
6338 tree fnargs = DECL_ARGUMENTS (fndecl);
3f1f8d8c
MM		 6339 rtx next_arg_reg;
6340 int i;
0fb5ac6f
MM		 6341 tree next_arg;
6342 tree cur_arg;
0fb5ac6f 6343 CUMULATIVE_ARGS args_so_far;
2bcb2ab3 6344 rtx reg_18_save = NULL_RTX;
0fb5ac6f 6345
518e5ce8
JW		 6346 /* If struct value address is treated as the first argument, make it so. */
6347 if (aggregate_value_p (DECL_RESULT (fndecl))
6348 && ! current_function_returns_pcc_struct
6349 && struct_value_incoming_rtx == 0)
6350 {
6351 tree type = build_pointer_type (fntype);
6352 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
f5963e61 6353
518e5ce8
JW		 6354 DECL_ARG_TYPE (function_result_decl) = type;
6355 TREE_CHAIN (function_result_decl) = fnargs;
6356 fnargs = function_result_decl;
6357 }
6358
cee98a59 6359 /* Determine the last argument, and get its name. */
3f1f8d8c 6360
f5963e61 6361 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
3f1f8d8c
MM		 6362 regno = GP_ARG_FIRST;
6363
f5963e61 6364 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
cee98a59 6365 {
6f673359
JW		 6366 tree passed_type = DECL_ARG_TYPE (cur_arg);
6367 enum machine_mode passed_mode = TYPE_MODE (passed_type);
6368 rtx entry_parm;
6369
e0c228da 6370 if (TREE_ADDRESSABLE (passed_type))
6f673359
JW		 6371 {
6372 passed_type = build_pointer_type (passed_type);
6373 passed_mode = Pmode;
6374 }
6375
6376 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
3f1f8d8c
MM		 6377
6378 if (entry_parm)
6379 {
6380 int words;
6381
6382 /* passed in a register, so will get homed automatically */
6383 if (GET_MODE (entry_parm) == BLKmode)
6f673359 6384 words = (int_size_in_bytes (passed_type) + 3) / 4;
3f1f8d8c
MM		 6385 else
6386 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
6387
6388 regno = REGNO (entry_parm) + words - 1;
6389 }
6390 else
6391 {
6392 regno = GP_ARG_LAST+1;
6393 break;
6394 }
6395
6f673359 6396 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
3f1f8d8c 6397
cee98a59 6398 next_arg = TREE_CHAIN (cur_arg);
f5963e61 6399 if (next_arg == 0)
cee98a59
MM		 6400 {
6401 if (DECL_NAME (cur_arg))
6402 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
6403
6404 break;
6405 }
6406 }
6407
f5963e61
JL		 6408 /* In order to pass small structures by value in registers compatibly with
6409 the MIPS compiler, we need to shift the value into the high part of the
6410 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
6411 adjustments to be made as the next_arg_reg variable, so we split up the
6412 insns, and emit them separately. */
cee98a59 6413
3f1f8d8c 6414 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
f5963e61 6415 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
3f1f8d8c
MM		 6416 {
6417 rtvec adjust = XVEC (next_arg_reg, 0);
6418 int num = GET_NUM_ELEM (adjust);
cee98a59 6419
3f1f8d8c 6420 for (i = 0; i < num; i++)
cee98a59 6421 {
3f1f8d8c
MM		 6422 rtx pattern = RTVEC_ELT (adjust, i);
6423 if (GET_CODE (pattern) != SET
6424 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
6425 abort_with_insn (pattern, "Insn is not a shift");
cee98a59 6426
3f1f8d8c
MM		 6427 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
6428 emit_insn (pattern);
cee98a59 6429 }
3f1f8d8c 6430 }
cee98a59 6431
ffa9d0b1
JW		 6432 tsize = compute_frame_size (get_frame_size ());
6433
3f1f8d8c
MM		 6434 /* If this function is a varargs function, store any registers that
6435 would normally hold arguments ($4 - $7) on the stack. */
a53f72db 6436 if ((mips_abi == ABI_32 || mips_abi == ABI_O64)
2bcb2ab3 6437 && (! mips_entry || mips_can_use_return_insn ())
33563487 6438 && ((TYPE_ARG_TYPES (fntype) != 0
f5963e61
JL		 6439 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6440 != void_type_node))
6441 || (arg_name != 0
6442 && ((arg_name[0] == '_'
6443 && strcmp (arg_name, "__builtin_va_alist") == 0)
6444 || (arg_name[0] == 'v'
6445 && strcmp (arg_name, "va_alist") == 0)))))
3f1f8d8c 6446 {
ffa9d0b1
JW		 6447 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
6448 rtx ptr = stack_pointer_rtx;
6449
6450 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
ade6c319 6451 if (TARGET_ABICALLS)
ffa9d0b1
JW		 6452 offset += tsize;
6453
0fb5ac6f 6454 for (; regno <= GP_ARG_LAST; regno++)
cee98a59 6455 {
ffa9d0b1
JW		 6456 if (offset != 0)
6457 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
bfed8dac
JL		 6458 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
6459 gen_rtx (REG, gpr_mode, regno));
6460
6461 offset += GET_MODE_SIZE (gpr_mode);
cee98a59
MM		 6462 }
6463 }
6464
2bcb2ab3
GK		 6465 /* If we are using the entry pseudo instruction, it will
6466 automatically subtract 32 from the stack pointer, so we don't
6467 need to. The entry pseudo instruction is emitted by
6468 function_prologue. */
6469 if (mips_entry && ! mips_can_use_return_insn ())
6470 {
6471 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
6472 {
6473 rtx insn;
6474
6475 /* If we are using a frame pointer with a small stack frame,
6476 we need to initialize it here since it won't be done
6477 below. */
6478 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6479 {
6480 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 6481 if (Pmode == DImode)
2bcb2ab3
GK		 6482 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6483 stack_pointer_rtx,
6484 incr));
6485 else
6486 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6487 stack_pointer_rtx,
6488 incr));
6489 }
1eeed24e 6490 else if (Pmode == DImode)
f5963e61
JL		 6491 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6492 stack_pointer_rtx));
2bcb2ab3 6493 else
f5963e61
JL		 6494 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6495 stack_pointer_rtx));
2bcb2ab3
GK		 6496
6497 RTX_FRAME_RELATED_P (insn) = 1;
6498 }
6499
6500 /* We may need to save $18, if it is used to call a function
6501 which may return a floating point value. Set up a sequence
6502 of instructions to do so. Later on we emit them at the right
6503 moment. */
6504 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
6505 {
bfed8dac 6506 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
2bcb2ab3
GK		 6507 long gp_offset, base_offset;
6508
6509 gp_offset = current_frame_info.gp_sp_offset;
6510 if (BITSET_P (current_frame_info.mask, 16))
6511 gp_offset -= UNITS_PER_WORD;
6512 if (BITSET_P (current_frame_info.mask, 17))
6513 gp_offset -= UNITS_PER_WORD;
6514 if (BITSET_P (current_frame_info.mask, 31))
6515 gp_offset -= UNITS_PER_WORD;
6516 if (tsize > 32767)
6517 base_offset = tsize;
6518 else
6519 base_offset = 0;
6520 start_sequence ();
6521 emit_move_insn (reg_rtx,
bfed8dac
JL		 6522 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
6523 emit_move_insn (gen_rtx (MEM, gpr_mode,
2bcb2ab3
GK		 6524 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
6525 GEN_INT (gp_offset
6526 - base_offset))),
6527 reg_rtx);
6528 reg_18_save = gen_sequence ();
6529 end_sequence ();
6530 }
6531
6532 if (tsize > 32)
6533 tsize -= 32;
6534 else
6535 {
6536 tsize = 0;
6537 if (reg_18_save != NULL_RTX)
6538 emit_insn (reg_18_save);
6539 }
6540 }
6541
cee98a59
MM		 6542 if (tsize > 0)
6543 {
0fb5ac6f 6544 rtx tsize_rtx = GEN_INT (tsize);
cee98a59 6545
2bcb2ab3
GK		 6546 /* If we are doing svr4-abi, sp move is done by
6547 function_prologue. In mips16 mode with a large frame, we
6548 save the registers before adjusting the stack. */
a53f72db 6549 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3 6550 && (!TARGET_MIPS16 || tsize <= 32767))
0fb5ac6f 6551 {
a94dbf2c
JM		 6552 rtx insn;
6553
ffa9d0b1
JW		 6554 if (tsize > 32767)
6555 {
147255d8 6556 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
119f2738
JW		 6557
6558 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6559 bit, so make sure that we don't emit anything that can be
6560 split. */
9d1cf1d9
JW		 6561 /* ??? There is no DImode ori immediate pattern, so we can only
6562 do this for 32 bit code. */
6563 if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
119f2738
JW		 6564 {
6565 insn = emit_move_insn (tmp_rtx,
6566 GEN_INT (tsize & 0xffff0000));
6567 RTX_FRAME_RELATED_P (insn) = 1;
6568 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
6569 GEN_INT (tsize & 0x0000ffff)));
6570 RTX_FRAME_RELATED_P (insn) = 1;
6571 }
6572 else
6573 {
6574 insn = emit_move_insn (tmp_rtx, tsize_rtx);
6575 RTX_FRAME_RELATED_P (insn) = 1;
6576 }
6577
ffa9d0b1
JW		 6578 tsize_rtx = tmp_rtx;
6579 }
cee98a59 6580
1eeed24e 6581 if (Pmode == DImode)
a94dbf2c
JM		 6582 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6583 tsize_rtx));
147255d8 6584 else
a94dbf2c
JM		 6585 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
6586 tsize_rtx));
6587
469ac993 6588 RTX_FRAME_RELATED_P (insn) = 1;
ffa9d0b1 6589 }
cee98a59 6590
2bcb2ab3 6591 if (! mips_entry)
f5963e61 6592 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
2bcb2ab3
GK		 6593 else if (reg_18_save != NULL_RTX)
6594 emit_insn (reg_18_save);
cee98a59 6595
a53f72db 6596 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3
GK		 6597 && TARGET_MIPS16
6598 && tsize > 32767)
147255d8 6599 {
2bcb2ab3 6600 rtx reg_rtx;
a94dbf2c 6601
2bcb2ab3
GK		 6602 if (!frame_pointer_needed)
6603 abort ();
6604
c3499f00 6605 reg_rtx = gen_rtx (REG, Pmode, 3);
2bcb2ab3
GK		 6606 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6607 emit_move_insn (reg_rtx, tsize_rtx);
1eeed24e 6608 if (Pmode == DImode)
2bcb2ab3
GK		 6609 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
6610 hard_frame_pointer_rtx,
6611 reg_rtx));
6612 else
6613 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
6614 hard_frame_pointer_rtx,
6615 reg_rtx));
6616 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6617 }
6618
6619 if (frame_pointer_needed)
6620 {
6621 rtx insn = 0;
6622
6623 /* On the mips16, we encourage the use of unextended
6624 instructions when using the frame pointer by pointing the
6625 frame pointer ahead of the argument space allocated on
6626 the stack. */
a53f72db 6627 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3
GK		 6628 && TARGET_MIPS16
6629 && tsize > 32767)
6630 {
6631 /* In this case, we have already copied the stack
6632 pointer into the frame pointer, above. We need only
6633 adjust for the outgoing argument size. */
6634 if (current_function_outgoing_args_size != 0)
6635 {
6636 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 6637 if (Pmode == DImode)
2bcb2ab3
GK		 6638 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6639 hard_frame_pointer_rtx,
6640 incr));
6641 else
6642 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6643 hard_frame_pointer_rtx,
6644 incr));
6645 }
6646 }
6647 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6648 {
6649 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 6650 if (Pmode == DImode)
2bcb2ab3
GK		 6651 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6652 stack_pointer_rtx,
6653 incr));
6654 else
6655 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6656 stack_pointer_rtx,
6657 incr));
6658 }
1eeed24e 6659 else if (Pmode == DImode)
f5963e61
JL		 6660 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6661 stack_pointer_rtx));
147255d8 6662 else
f5963e61
JL		 6663 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6664 stack_pointer_rtx));
a94dbf2c 6665
8fa4e1b4
JL		 6666 if (insn)
6667 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 6668 }
33563487 6669
a53f72db 6670 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
e5e809f4 6671 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
c5c76735 6672 gen_rtx_REG (DImode, 25)));
cee98a59 6673 }
d8d5b1e1
MM		 6674
6675 /* If we are profiling, make sure no instructions are scheduled before
6676 the call to mcount. */
6677
6678 if (profile_flag || profile_block_flag)
6679 emit_insn (gen_blockage ());
cee98a59 6680}
cee98a59 6681\f
f5963e61
JL		 6682/* Do any necessary cleanup after a function to restore stack, frame,
6683 and regs. */
cee98a59 6684
b5e9dd03 6685#define RA_MASK ((long) 0x80000000) /* 1 << 31 */
4d889da9 6686#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
b5e9dd03 6687
cee98a59
MM		 6688void
6689function_epilogue (file, size)
38831dfe
KG		 6690 FILE *file ATTRIBUTE_UNUSED;
6691 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
cee98a59 6692{
10389f52 6693 char *fnname;
cee98a59 6694
993cd990 6695#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52
RK		 6696 /* Get the function name the same way that toplev.c does before calling
6697 assemble_start_function. This is needed so that the name used here
6698 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6699 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6700
e9a25f70
JL		 6701 if (!flag_inhibit_size_directive)
6702 {
6703 fputs ("\t.end\t", file);
6704 assemble_name (file, fnname);
6705 fputs ("\n", file);
6706 }
993cd990 6707#endif
cee98a59
MM		 6708
6709 if (TARGET_STATS)
6710 {
6711 int num_gp_regs = current_frame_info.gp_reg_size / 4;
6712 int num_fp_regs = current_frame_info.fp_reg_size / 8;
f5963e61
JL		 6713 int num_regs = num_gp_regs + num_fp_regs;
6714 char *name = fnname;
ab78d4a8
MM		 6715
6716 if (name[0] == '*')
6717 name++;
cee98a59
MM		 6718
6719 dslots_load_total += num_regs;
6720
cee98a59 6721 fprintf (stderr,
38831dfe 6722 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
f5963e61
JL		 6723 name, frame_pointer_needed ? 'y' : 'n',
6724 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
6725 current_function_calls_alloca ? 'y' : 'n',
6726 current_function_calls_setjmp ? 'y' : 'n',
6727 current_frame_info.total_size,
6728 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
cee98a59
MM		 6729 dslots_load_total, dslots_load_filled,
6730 dslots_jump_total, dslots_jump_filled,
6731 num_refs[0], num_refs[1], num_refs[2]);
ddd8ab48 6732
6f3c667f
MM		 6733 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
6734 {
f5963e61
JL		 6735 fprintf (stderr,
6736 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
6f3c667f
MM		 6737 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
6738 }
ddd8ab48 6739
6f3c667f
MM		 6740 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
6741 {
f5963e61
JL		 6742 fprintf (stderr,
6743 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
6f3c667f
MM		 6744 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
6745 }
ddd8ab48
MM		 6746
6747 fputc ('\n', stderr);
cee98a59
MM		 6748 }
6749
6750 /* Reset state info for each function. */
f5963e61
JL		 6751 inside_function = 0;
6752 ignore_line_number = 0;
6753 dslots_load_total = 0;
6754 dslots_jump_total = 0;
cee98a59
MM		 6755 dslots_load_filled = 0;
6756 dslots_jump_filled = 0;
f5963e61
JL		 6757 num_refs[0] = 0;
6758 num_refs[1] = 0;
6759 num_refs[2] = 0;
6760 mips_load_reg = 0;
6761 mips_load_reg2 = 0;
cee98a59
MM		 6762 current_frame_info = zero_frame_info;
6763
2bcb2ab3
GK		 6764 while (string_constants != NULL)
6765 {
6766 struct string_constant *next;
6767
6768 next = string_constants->next;
6769 free (string_constants);
6770 string_constants = next;
6771 }
6772
cee98a59
MM		 6773 /* Restore the output file if optimizing the GP (optimizing the GP causes
6774 the text to be diverted to a tempfile, so that data decls come before
6775 references to the data). */
6776
2bcb2ab3 6777 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
cee98a59
MM		 6778 asm_out_file = asm_out_data_file;
6779}
0fb5ac6f
MM		 6780\f
6781/* Expand the epilogue into a bunch of separate insns. */
6782
6783void
6784mips_expand_epilogue ()
6785{
f5963e61 6786 HOST_WIDE_INT tsize = current_frame_info.total_size;
0fb5ac6f 6787 rtx tsize_rtx = GEN_INT (tsize);
7bea35e7 6788 rtx tmp_rtx = (rtx)0;
0fb5ac6f 6789
1f2d8f51
JL		 6790 if (mips_can_use_return_insn ())
6791 {
6792 emit_insn (gen_return ());
6793 return;
6794 }
6795
2bcb2ab3
GK		 6796 if (mips_entry && ! mips_can_use_return_insn ())
6797 tsize -= 32;
6798
6799 if (tsize > 32767 && ! TARGET_MIPS16)
0fb5ac6f 6800 {
c5c76735 6801 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
0fb5ac6f
MM		 6802 emit_move_insn (tmp_rtx, tsize_rtx);
6803 tsize_rtx = tmp_rtx;
6804 }
6805
6806 if (tsize > 0)
6807 {
2bcb2ab3
GK		 6808 long orig_tsize = tsize;
6809
0fb5ac6f 6810 if (frame_pointer_needed)
147255d8 6811 {
1f2d8f51 6812 emit_insn (gen_blockage ());
2bcb2ab3
GK		 6813
6814 /* On the mips16, the frame pointer is offset from the stack
6815 pointer by current_function_outgoing_args_size. We
6816 account for that by changing tsize. Note that this can
6817 actually make tsize negative. */
6818 if (TARGET_MIPS16)
6819 {
6820 tsize -= current_function_outgoing_args_size;
6821
6822 /* If we have a large frame, it's easier to add to $17
6823 than to $sp, since the mips16 has no instruction to
6824 add a register to $sp. */
6825 if (orig_tsize > 32767)
6826 {
c3499f00 6827 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
2bcb2ab3
GK		 6828
6829 emit_move_insn (g6_rtx, GEN_INT (tsize));
1eeed24e 6830 if (Pmode == DImode)
2bcb2ab3
GK		 6831 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6832 hard_frame_pointer_rtx,
6833 g6_rtx));
6834 else
6835 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6836 hard_frame_pointer_rtx,
6837 g6_rtx));
6838 tsize = 0;
6839 }
a4dee8a5
GK		 6840
6841 if (tsize && tsize != orig_tsize)
6842 tsize_rtx = GEN_INT (tsize);
2bcb2ab3
GK		 6843 }
6844
1eeed24e 6845 if (Pmode == DImode)
2bcb2ab3 6846 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
147255d8 6847 else
2bcb2ab3 6848 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
147255d8 6849 }
f5963e61 6850
ab00eb0a
JW		 6851 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
6852 are going to restore it, then we must emit a blockage insn to
6853 prevent the scheduler from moving the restore out of the epilogue. */
a53f72db 6854 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
ab00eb0a
JW		 6855 && (current_frame_info.mask
6856 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
6857 emit_insn (gen_blockage ());
0fb5ac6f 6858
f5963e61 6859 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
0fb5ac6f 6860
2bcb2ab3
GK		 6861 /* In mips16 mode with a large frame, we adjust the stack
6862 pointer before restoring the registers. In this case, we
6863 should always be using a frame pointer, so everything should
6864 have been handled above. */
6865 if (tsize > 32767 && TARGET_MIPS16)
6866 abort ();
6867
1f2d8f51 6868 emit_insn (gen_blockage ());
1eeed24e 6869 if (Pmode == DImode && tsize != 0)
147255d8
JW		 6870 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
6871 tsize_rtx));
8fa4e1b4 6872 else if (tsize != 0)
147255d8
JW		 6873 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6874 tsize_rtx));
0fb5ac6f
MM		 6875 }
6876
2bcb2ab3
GK		 6877 /* The mips16 loads the return address into $7, not $31. */
6878 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
6879 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6880 GP_REG_FIRST + 7)));
6881 else
6882 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6883 GP_REG_FIRST + 31)));
cee98a59 6884}
cee98a59 6885\f
f5963e61 6886/* Return nonzero if this function is known to have a null epilogue.
cee98a59
MM		 6887 This allows the optimizer to omit jumps to jumps if no stack
6888 was created. */
6889
6890int
1f2d8f51 6891mips_can_use_return_insn ()
cee98a59 6892{
f5963e61 6893 if (! reload_completed)
cee98a59
MM		 6894 return 0;
6895
1f2d8f51
JL		 6896 if (regs_ever_live[31] || profile_flag)
6897 return 0;
6898
2bcb2ab3
GK		 6899 /* In mips16 mode, a function which returns a floating point value
6900 needs to arrange to copy the return value into the floating point
6901 registers. */
6902 if (TARGET_MIPS16
6903 && mips16_hard_float
6904 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6905 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6906 == MODE_FLOAT)
6907 && (! TARGET_SINGLE_FLOAT
6908 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6909 <= 4)))
6910 return 0;
6911
cee98a59
MM		 6912 if (current_frame_info.initialized)
6913 return current_frame_info.total_size == 0;
6914
f5963e61 6915 return compute_frame_size (get_frame_size ()) == 0;
cee98a59 6916}
9753d4e4 6917\f
d660677d
MM		 6918/* Returns non-zero if X contains a SYMBOL_REF. */
6919
6920static int
6921symbolic_expression_p (x)
6922 rtx x;
6923{
6924 if (GET_CODE (x) == SYMBOL_REF)
6925 return 1;
6926
6927 if (GET_CODE (x) == CONST)
6928 return symbolic_expression_p (XEXP (x, 0));
6929
6930 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
6931 return symbolic_expression_p (XEXP (x, 0));
6932
6933 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
6934 || GET_RTX_CLASS (GET_CODE (x)) == '2')
6935 return (symbolic_expression_p (XEXP (x, 0))
6936 || symbolic_expression_p (XEXP (x, 1)));
6937
6938 return 0;
6939}
6940
9753d4e4
JW		 6941/* Choose the section to use for the constant rtx expression X that has
6942 mode MODE. */
6943
6e92f4b6 6944void
9753d4e4
JW		 6945mips_select_rtx_section (mode, x)
6946 enum machine_mode mode;
38831dfe 6947 rtx x ATTRIBUTE_UNUSED;
9753d4e4 6948{
2bcb2ab3
GK		 6949 if (TARGET_MIPS16)
6950 {
52ecdfda
JW		 6951 /* In mips16 mode, the constant table always goes in the same section
6952 as the function, so that constants can be loaded using PC relative
2bcb2ab3 6953 addressing. */
52ecdfda 6954 function_section (current_function_decl);
2bcb2ab3
GK		 6955 }
6956 else if (TARGET_EMBEDDED_DATA)
9753d4e4
JW		 6957 {
6958 /* For embedded applications, always put constants in read-only data,
6959 in order to reduce RAM usage. */
8bd8e198 6960 READONLY_DATA_SECTION ();
9753d4e4
JW		 6961 }
6962 else
6963 {
6964 /* For hosted applications, always put constants in small data if
6965 possible, as this gives the best performance. */
6966
6967 if (GET_MODE_SIZE (mode) <= mips_section_threshold
6968 && mips_section_threshold > 0)
8bd8e198 6969 SMALL_DATA_SECTION ();
d660677d
MM		 6970 else if (flag_pic && symbolic_expression_p (x))
6971 /* Any expression involving a SYMBOL_REF might need a run-time
6972 relocation. (The symbol might be defined in a shared
6973 library loaded at an unexpected base address.) So, we must
6974 put such expressions in the data segment (which is
6975 writable), rather than the text segment (which is
6976 read-only). */
6977 data_section ();
9753d4e4 6978 else
8bd8e198 6979 READONLY_DATA_SECTION ();
9753d4e4
JW		 6980 }
6981}
6982
6983/* Choose the section to use for DECL. RELOC is true if its value contains
5f680ab6
DD		 6984 any relocatable expression.
6985
6986 Some of the logic used here needs to be replicated in
6987 ENCODE_SECTION_INFO in mips.h so that references to these symbols
6988 are done correctly. Specifically, at least all symbols assigned
6989 here to rom (.text and/or .rodata) must not be referenced via
6990 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
6991
6992 If you need to make a change here, you probably should check
6993 ENCODE_SECTION_INFO to see if it needs a similar change. */
9753d4e4 6994
6e92f4b6 6995void
9753d4e4
JW		 6996mips_select_section (decl, reloc)
6997 tree decl;
6998 int reloc;
6999{
7000 int size = int_size_in_bytes (TREE_TYPE (decl));
7001
2bcb2ab3 7002 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
92544bdf
ILT		 7003 && TREE_CODE (decl) == STRING_CST
7004 && !flag_writable_strings)
f5963e61
JL		 7005 /* For embedded position independent code, put constant strings in the
7006 text section, because the data section is limited to 64K in size.
7007 For mips16 code, put strings in the text section so that a PC
7008 relative load instruction can be used to get their address. */
7009 text_section ();
92544bdf 7010 else if (TARGET_EMBEDDED_DATA)
9753d4e4
JW		 7011 {
7012 /* For embedded applications, always put an object in read-only data
7013 if possible, in order to reduce RAM usage. */
7014
1d306530
JW		 7015 if (((TREE_CODE (decl) == VAR_DECL
7016 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
9753d4e4
JW		 7017 && DECL_INITIAL (decl)
7018 && (DECL_INITIAL (decl) == error_mark_node
7019 || TREE_CONSTANT (DECL_INITIAL (decl))))
7020 /* Deal with calls from output_constant_def_contents. */
7021 || (TREE_CODE (decl) != VAR_DECL
7022 && (TREE_CODE (decl) != STRING_CST
7023 || !flag_writable_strings)))
7024 && ! (flag_pic && reloc))
8bd8e198 7025 READONLY_DATA_SECTION ();
9753d4e4 7026 else if (size > 0 && size <= mips_section_threshold)
8bd8e198 7027 SMALL_DATA_SECTION ();
9753d4e4
JW		 7028 else
7029 data_section ();
7030 }
7031 else
7032 {
7033 /* For hosted applications, always put an object in small data if
7034 possible, as this gives the best performance. */
7035
7036 if (size > 0 && size <= mips_section_threshold)
8bd8e198 7037 SMALL_DATA_SECTION ();
1d306530
JW		 7038 else if (((TREE_CODE (decl) == VAR_DECL
7039 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
9753d4e4
JW		 7040 && DECL_INITIAL (decl)
7041 && (DECL_INITIAL (decl) == error_mark_node
7042 || TREE_CONSTANT (DECL_INITIAL (decl))))
7043 /* Deal with calls from output_constant_def_contents. */
7044 || (TREE_CODE (decl) != VAR_DECL
7045 && (TREE_CODE (decl) != STRING_CST
7046 || !flag_writable_strings)))
7047 && ! (flag_pic && reloc))
8bd8e198 7048 READONLY_DATA_SECTION ();
9753d4e4
JW		 7049 else
7050 data_section ();
7051 }
7052}
33563487 7053\f
ade6c319 7054#ifdef MIPS_ABI_DEFAULT
f5963e61 7055
33563487
JW		 7056/* Support functions for the 64 bit ABI. */
7057
33563487
JW		 7058/* Return register to use for a function return value with VALTYPE for function
7059 FUNC. */
7060
7061rtx
7062mips_function_value (valtype, func)
7063 tree valtype;
38831dfe 7064 tree func ATTRIBUTE_UNUSED;
33563487
JW		 7065{
7066 int reg = GP_RETURN;
7067 enum machine_mode mode = TYPE_MODE (valtype);
7068 enum mode_class mclass = GET_MODE_CLASS (mode);
2bcb2ab3
GK		 7069 int unsignedp = TREE_UNSIGNED (valtype);
7070
7071 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7072 just as PROMOTE_MODE does. */
7073 mode = promote_mode (valtype, mode, &unsignedp, 1);
33563487 7074
a20b7b05 7075 /* ??? How should we return complex float? */
33563487 7076 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
efcedf42
ILT		 7077 {
7078 if (TARGET_SINGLE_FLOAT
7079 && (mclass == MODE_FLOAT
f5963e61 7080 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
efcedf42
ILT		 7081 reg = GP_RETURN;
7082 else
7083 reg = FP_RETURN;
7084 }
f5963e61 7085
293a36eb 7086 else if (TREE_CODE (valtype) == RECORD_TYPE
a53f72db
GRK		 7087 && mips_abi != ABI_32
7088 && mips_abi != ABI_O64
7089 && mips_abi != ABI_EABI)
33563487
JW		 7090 {
7091 /* A struct with only one or two floating point fields is returned in
7092 the floating point registers. */
320aba9c 7093 tree field, fields[2];
33563487
JW		 7094 int i;
7095
7096 for (i = 0, field = TYPE_FIELDS (valtype); field;
320aba9c 7097 field = TREE_CHAIN (field))
33563487 7098 {
320aba9c
JW		 7099 if (TREE_CODE (field) != FIELD_DECL)
7100 continue;
f5963e61 7101
33563487
JW		 7102 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7103 break;
320aba9c
JW		 7104
7105 fields[i++] = field;
33563487
JW		 7106 }
7107
1417e9bd 7108 /* Must check i, so that we reject structures with no elements. */
a20b7b05
JW		 7109 if (! field)
7110 {
7111 if (i == 1)
7112 {
320aba9c
JW		 7113 /* The structure has DImode, but we don't allow DImode values
7114 in FP registers, so we use a PARALLEL even though it isn't
7115 strictly necessary. */
7116 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7117
c5c76735
JL		 7118 return gen_rtx_PARALLEL
7119 (mode,
7120 gen_rtvec (1,
7121 gen_rtx_EXPR_LIST (VOIDmode,
7122 gen_rtx_REG (field_mode,
7123 FP_RETURN),
7124 const0_rtx)));
a20b7b05 7125 }
f5963e61 7126
a20b7b05
JW		 7127 else if (i == 2)
7128 {
7129 enum machine_mode first_mode
320aba9c 7130 = TYPE_MODE (TREE_TYPE (fields[0]));
a20b7b05 7131 enum machine_mode second_mode
320aba9c 7132 = TYPE_MODE (TREE_TYPE (fields[1]));
a20b7b05 7133 int first_offset
320aba9c 7134 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
a20b7b05 7135 int second_offset
320aba9c 7136 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
a20b7b05 7137
c5c76735
JL		 7138 return gen_rtx_PARALLEL
7139 (mode,
7140 gen_rtvec (2,
7141 gen_rtx_EXPR_LIST (VOIDmode,
7142 gen_rtx_REG (first_mode,
7143 FP_RETURN),
7144 GEN_INT (first_offset
7145 / BITS_PER_UNIT)),
7146 gen_rtx_EXPR_LIST (VOIDmode,
7147 gen_rtx_REG (second_mode,
7148 FP_RETURN + 2),
7149 GEN_INT (second_offset
7150 / BITS_PER_UNIT))));
a20b7b05
JW		 7151 }
7152 }
33563487
JW		 7153 }
7154
c5c76735 7155 return gen_rtx_REG (mode, reg);
33563487 7156}
293a36eb
ILT		 7157
7158/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7159 nonzero when an argument must be passed by reference. */
7160
7161int
7162function_arg_pass_by_reference (cum, mode, type, named)
38831dfe 7163 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
293a36eb
ILT		 7164 enum machine_mode mode;
7165 tree type;
38831dfe 7166 int named ATTRIBUTE_UNUSED;
293a36eb
ILT		 7167{
7168 int size;
7169
c5c76735
JL		 7170 /* We must pass by reference if we would be both passing in registers
7171 and the stack. This is because any subsequent partial arg would be
7172 handled incorrectly in this case.
7173
7174 ??? This is really a kludge. We should either fix GCC so that such
7175 a situation causes an abort and then do something in the MIPS port
7176 to prevent it, or add code to function.c to properly handle the case. */
7177 if (FUNCTION_ARG (*cum, mode, type, named) != 0
7178 && MUST_PASS_IN_STACK (mode, type))
7179 return 1;
7180
7181 /* Otherwise, we only do this if EABI is selected. */
293a36eb
ILT		 7182 if (mips_abi != ABI_EABI)
7183 return 0;
7184
7185 /* ??? How should SCmode be handled? */
7186 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7187 return 0;
7188
7189 size = int_size_in_bytes (type);
7190 return size == -1 || size > UNITS_PER_WORD;
7191}
33563487 7192#endif
46299de9 7193
225b8835
ILT		 7194/* This function returns the register class required for a secondary
7195 register when copying between one of the registers in CLASS, and X,
7196 using MODE. If IN_P is nonzero, the copy is going from X to the
7197 register, otherwise the register is the source. A return value of
7198 NO_REGS means that no secondary register is required. */
46299de9
ILT		 7199
7200enum reg_class
225b8835 7201mips_secondary_reload_class (class, mode, x, in_p)
46299de9
ILT		 7202 enum reg_class class;
7203 enum machine_mode mode;
7204 rtx x;
225b8835 7205 int in_p;
46299de9 7206{
2bcb2ab3 7207 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
225b8835 7208 int regno = -1;
2bcb2ab3 7209 int gp_reg_p;
46299de9 7210
2a0b0bf5
ILT		 7211 if (GET_CODE (x) == SIGN_EXTEND)
7212 {
7213 int off = 0;
7214
7215 x = XEXP (x, 0);
7216
7217 /* We may be called with reg_renumber NULL from regclass.
7218 ??? This is probably a bug. */
7219 if (reg_renumber)
7220 regno = true_regnum (x);
7221 else
7222 {
7223 while (GET_CODE (x) == SUBREG)
7224 {
7225 off += SUBREG_WORD (x);
7226 x = SUBREG_REG (x);
7227 }
f5963e61 7228
2a0b0bf5
ILT		 7229 if (GET_CODE (x) == REG)
7230 regno = REGNO (x) + off;
7231 }
7232 }
f5963e61 7233
2a0b0bf5 7234 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
225b8835
ILT		 7235 regno = true_regnum (x);
7236
2bcb2ab3
GK		 7237 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7238
225b8835
ILT		 7239 /* We always require a general register when copying anything to
7240 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7241 to a general register, or when copying from register 0. */
7242 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
f5963e61 7243 return ((! in_p
33d7a521 7244 && gp_reg_p
f5963e61 7245 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
33d7a521 7246 ? NO_REGS : gr_regs);
f5963e61
JL		 7247 else if (regno == HILO_REGNUM)
7248 return ((in_p
33d7a521 7249 && class == gr_regs
f5963e61 7250 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
33d7a521 7251 ? NO_REGS : gr_regs);
46299de9 7252
225b8835
ILT		 7253 /* Copying from HI or LO to anywhere other than a general register
7254 requires a general register. */
7255 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7256 {
2bcb2ab3
GK		 7257 if (TARGET_MIPS16 && in_p)
7258 {
7259 /* We can't really copy to HI or LO at all in mips16 mode. */
7260 return M16_REGS;
7261 }
33d7a521 7262 return gp_reg_p ? NO_REGS : gr_regs;
225b8835
ILT		 7263 }
7264 if (MD_REG_P (regno))
7265 {
2bcb2ab3
GK		 7266 if (TARGET_MIPS16 && ! in_p)
7267 {
7268 /* We can't really copy to HI or LO at all in mips16 mode. */
7269 return M16_REGS;
7270 }
33d7a521 7271 return class == gr_regs ? NO_REGS : gr_regs;
46299de9
ILT		 7272 }
7273
b8eb88d0
ILT		 7274 /* We can only copy a value to a condition code register from a
7275 floating point register, and even then we require a scratch
7276 floating point register. We can only copy a value out of a
7277 condition code register into a general register. */
7278 if (class == ST_REGS)
7279 {
7280 if (in_p)
7281 return FP_REGS;
f5963e61 7282 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
b8eb88d0
ILT		 7283 }
7284 if (ST_REG_P (regno))
7285 {
7286 if (! in_p)
7287 return FP_REGS;
f5963e61 7288 return class == GR_REGS ? NO_REGS : GR_REGS;
b8eb88d0
ILT		 7289 }
7290
2bcb2ab3
GK		 7291 /* In mips16 mode, going between memory and anything but M16_REGS
7292 requires an M16_REG. */
7293 if (TARGET_MIPS16)
7294 {
7295 if (class != M16_REGS && class != M16_NA_REGS)
7296 {
7297 if (gp_reg_p)
7298 return NO_REGS;
7299 return M16_REGS;
7300 }
7301 if (! gp_reg_p)
7302 {
bf4f78ee
JW		 7303 /* The stack pointer isn't a valid operand to an add instruction,
7304 so we need to load it into M16_REGS first. This can happen as
7305 a result of register elimination and form_sum converting
7306 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7307 need an extra register if the dest is the same as the other
7308 register. In that case, we can't fix the problem by loading SP
7309 into the dest first. */
7310 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
7311 && GET_CODE (XEXP (x, 1)) == REG
7312 && (XEXP (x, 0) == stack_pointer_rtx
7313 || XEXP (x, 1) == stack_pointer_rtx))
7314 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
7315
2bcb2ab3
GK		 7316 if (class == M16_REGS || class == M16_NA_REGS)
7317 return NO_REGS;
7318 return M16_REGS;
7319 }
7320 }
7321
225b8835 7322 return NO_REGS;
46299de9 7323}
2bcb2ab3
GK		 7324\f
7325/* For each mips16 function which refers to GP relative symbols, we
7326 use a pseudo register, initialized at the start of the function, to
7327 hold the $gp value. */
7328
7329rtx
7330mips16_gp_pseudo_reg ()
7331{
7332 if (mips16_gp_pseudo_rtx == NULL_RTX)
7333 {
7334 rtx const_gp;
7335 rtx insn, scan;
7336
7337 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7338 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
7339
7340 /* We want to initialize this to a value which gcc will believe
7341 is constant. */
7342 const_gp = gen_rtx (CONST, Pmode,
7343 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
7344
7345 start_sequence ();
7346 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
7347 insn = gen_sequence ();
7348 end_sequence ();
7349
7350 push_topmost_sequence ();
7351 /* We need to emit the initialization after the FUNCTION_BEG
7352 note, so that it will be integrated. */
7353 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7354 if (GET_CODE (scan) == NOTE
7355 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7356 break;
7357 if (scan == NULL_RTX)
7358 scan = get_insns ();
7359 insn = emit_insn_after (insn, scan);
7360 pop_topmost_sequence ();
7361 }
7362
7363 return mips16_gp_pseudo_rtx;
7364}
7365
7366/* Return an RTX which represents the signed 16 bit offset from the
7367 $gp register for the given symbol. This is only used on the
7368 mips16. */
7369
7370rtx
7371mips16_gp_offset (sym)
7372 rtx sym;
7373{
7374 tree gp;
7375
7376 if (GET_CODE (sym) != SYMBOL_REF
7377 || ! SYMBOL_REF_FLAG (sym))
7378 abort ();
7379
7380 /* We use a special identifier to represent the value of the gp
7381 register. */
7382 gp = get_identifier ("__mips16_gp_value");
7383
7384 return gen_rtx (CONST, Pmode,
7385 gen_rtx (MINUS, Pmode, sym,
7386 gen_rtx (SYMBOL_REF, Pmode,
7387 IDENTIFIER_POINTER (gp))));
7388}
7389
7390/* Return nonzero if the given RTX represents a signed 16 bit offset
7391 from the $gp register. */
7392
7393int
7394mips16_gp_offset_p (x)
7395 rtx x;
7396{
7397 if (GET_CODE (x) == CONST)
7398 x = XEXP (x, 0);
7399
7400 /* It's OK to add a small integer value to a gp offset. */
7401 if (GET_CODE (x) == PLUS)
7402 {
7403 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7404 && SMALL_INT (XEXP (x, 1)))
7405 return mips16_gp_offset_p (XEXP (x, 0));
7406 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7407 && SMALL_INT (XEXP (x, 0)))
7408 return mips16_gp_offset_p (XEXP (x, 1));
7409 return 0;
7410 }
7411
7412 /* Make sure it is in the form SYM - __mips16_gp_value. */
7413 return (GET_CODE (x) == MINUS
7414 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
7415 && SYMBOL_REF_FLAG (XEXP (x, 0))
7416 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7417 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
7418}
7419
7420/* Output a GP offset. We don't want to print the subtraction of
7421 __mips16_gp_value; it is implicitly represented by the %gprel which
7422 should have been printed by the caller. */
7423
7424static void
7425mips16_output_gp_offset (file, x)
7426 FILE *file;
7427 rtx x;
7428{
7429 if (GET_CODE (x) == CONST)
7430 x = XEXP (x, 0);
7431
7432 if (GET_CODE (x) == PLUS)
7433 {
7434 mips16_output_gp_offset (file, XEXP (x, 0));
7435 fputs ("+", file);
7436 mips16_output_gp_offset (file, XEXP (x, 1));
7437 return;
7438 }
7439
7440 if (GET_CODE (x) == MINUS
7441 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7442 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
7443 {
7444 mips16_output_gp_offset (file, XEXP (x, 0));
7445 return;
7446 }
7447
7448 output_addr_const (file, x);
7449}
7450
7451/* Return nonzero if a constant should not be output until after the
7452 function. This is true of most string constants, so that we can
7453 use a more efficient PC relative reference. However, a static
7454 inline function may never call assemble_function_end to write out
7455 the constant pool, so don't try to postpone the constant in that
7456 case.
7457
7458 ??? It's really a bug that a static inline function can put stuff
7459 in the constant pool even if the function itself is not output.
7460
7461 We record which string constants we've seen, so that we know which
7462 ones might use the more efficient reference. */
7463
7464int
7465mips16_constant_after_function_p (x)
7466 tree x;
7467{
7468 if (TREE_CODE (x) == STRING_CST
7469 && ! flag_writable_strings
7470 && current_function_decl != 0
7471 && ! DECL_DEFER_OUTPUT (current_function_decl)
7472 && ! (DECL_INLINE (current_function_decl)
7473 && ((! TREE_PUBLIC (current_function_decl)
7474 && ! TREE_ADDRESSABLE (current_function_decl)
7475 && ! flag_keep_inline_functions)
7476 || DECL_EXTERNAL (current_function_decl))))
7477 {
7478 struct string_constant *n;
7479
7480 n = (struct string_constant *) xmalloc (sizeof *n);
7481 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
7482 n->next = string_constants;
7483 string_constants = n;
7484
7485 return 1;
7486 }
7487
7488 return 0;
7489}
7490
7491/* Validate a constant for the mips16. This rejects general symbolic
7492 addresses, which must be loaded from memory. If ADDR is nonzero,
7493 this should reject anything which is not a legal address. If
7494 ADDEND is nonzero, this is being added to something else. */
7495
7496int
7497mips16_constant (x, mode, addr, addend)
7498 rtx x;
7499 enum machine_mode mode;
7500 int addr;
7501 int addend;
7502{
7503 while (GET_CODE (x) == CONST)
7504 x = XEXP (x, 0);
7505
7506 switch (GET_CODE (x))
7507 {
7508 default:
7509 return 0;
7510
7511 case PLUS:
7512 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
7513 && mips16_constant (XEXP (x, 1), mode, addr, 1));
7514
7515 case SYMBOL_REF:
7516 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7517 return 0;
7518 if (CONSTANT_POOL_ADDRESS_P (x))
7519 return 1;
7520
7521 /* If we aren't looking for a memory address, we can accept a GP
7522 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7523 knows how to handle this. We can always accept a string
7524 constant, which is the other case in which SYMBOL_REF_FLAG
7525 will be set. */
7526 if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
7527 return 1;
7528
7529 /* We can accept a string constant, which will have
7530 SYMBOL_REF_FLAG set but must be recognized by name to
7531 distinguish from a GP accessible symbol. The name of a
7532 string constant will have been generated by
7533 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7534 if (SYMBOL_REF_FLAG (x))
7535 {
7536 char *name = XSTR (x, 0);
7537
7538 return (name[0] == '*'
7539 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
7540 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
7541 }
7542
7543 return 0;
7544
7545 case LABEL_REF:
7546 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7547 return 0;
7548 return 1;
7549
7550 case CONST_INT:
7551 if (addr && ! addend)
7552 return 0;
7553 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
7554
7555 case REG:
7556 /* We need to treat $gp as a legitimate constant, because
7557 mips16_gp_pseudo_reg assumes that. */
7558 return REGNO (x) == GP_REG_FIRST + 28;
7559 }
7560}
7561
7562/* Write out code to move floating point arguments in or out of
7563 general registers. Output the instructions to FILE. FP_CODE is
7564 the code describing which arguments are present (see the comment at
7565 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7566 we are copying from the floating point registers. */
7567
7568static void
7569mips16_fp_args (file, fp_code, from_fp_p)
7570 FILE *file;
7571 int fp_code;
7572 int from_fp_p;
7573{
e2fe6aba 7574 const char *s;
2bcb2ab3
GK		 7575 int gparg, fparg;
7576 unsigned int f;
7577
a53f72db
GRK		 7578 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7579 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
2bcb2ab3
GK		 7580 abort ();
7581
7582 if (from_fp_p)
7583 s = "mfc1";
7584 else
7585 s = "mtc1";
7586 gparg = GP_ARG_FIRST;
7587 fparg = FP_ARG_FIRST;
7588 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7589 {
7590 if ((f & 3) == 1)
7591 {
7592 if ((fparg & 1) != 0)
7593 ++fparg;
7594 fprintf (file, "\t%s\t%s,%s\n", s,
7595 reg_names[gparg], reg_names[fparg]);
7596 }
7597 else if ((f & 3) == 2)
7598 {
7599 if (TARGET_64BIT)
7600 fprintf (file, "\td%s\t%s,%s\n", s,
7601 reg_names[gparg], reg_names[fparg]);
7602 else
7603 {
7604 if ((fparg & 1) != 0)
7605 ++fparg;
a3bc83cc
AC		 7606 if (TARGET_BIG_ENDIAN)
7607 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7608 reg_names[gparg], reg_names[fparg + 1], s,
7609 reg_names[gparg + 1], reg_names[fparg]);
7610 else
7611 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7612 reg_names[gparg], reg_names[fparg], s,
7613 reg_names[gparg + 1], reg_names[fparg + 1]);
2bcb2ab3
GK		 7614 ++gparg;
7615 ++fparg;
7616 }
7617 }
7618 else
7619 abort ();
7620
7621 ++gparg;
7622 ++fparg;
7623 }
7624}
7625
7626/* Build a mips16 function stub. This is used for functions which
7627 take aruments in the floating point registers. It is 32 bit code
7628 that moves the floating point args into the general registers, and
7629 then jumps to the 16 bit code. */
7630
7631static void
7632build_mips16_function_stub (file)
7633 FILE *file;
7634{
7635 char *fnname;
7636 char *secname, *stubname;
7637 tree stubid, stubdecl;
7638 int need_comma;
7639 unsigned int f;
7640
7641 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7642 secname = (char *) alloca (strlen (fnname) + 20);
7643 sprintf (secname, ".mips16.fn.%s", fnname);
7644 stubname = (char *) alloca (strlen (fnname) + 20);
7645 sprintf (stubname, "__fn_stub_%s", fnname);
7646 stubid = get_identifier (stubname);
7647 stubdecl = build_decl (FUNCTION_DECL, stubid,
7648 build_function_type (void_type_node, NULL_TREE));
7649 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7650
7651 fprintf (file, "\t# Stub function for %s (", current_function_name);
7652 need_comma = 0;
7653 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7654 {
7655 fprintf (file, "%s%s",
7656 need_comma ? ", " : "",
7657 (f & 3) == 1 ? "float" : "double");
7658 need_comma = 1;
7659 }
7660 fprintf (file, ")\n");
7661
7662 fprintf (file, "\t.set\tnomips16\n");
7663 function_section (stubdecl);
7664 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7665
7666 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7667 within a .ent, and we can not emit another .ent. */
7668#ifndef FUNCTION_NAME_ALREADY_DECLARED
7669 fputs ("\t.ent\t", file);
7670 assemble_name (file, stubname);
7671 fputs ("\n", file);
7672#endif
7673
7674 assemble_name (file, stubname);
7675 fputs (":\n", file);
7676
7677 /* We don't want the assembler to insert any nops here. */
7678 fprintf (file, "\t.set\tnoreorder\n");
7679
7680 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7681
7682 fprintf (asm_out_file, "\t.set\tnoat\n");
7683 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7684 assemble_name (file, fnname);
7685 fprintf (file, "\n");
7686 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7687 fprintf (asm_out_file, "\t.set\tat\n");
7688
7689 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7690 with one of the mfc1 instructions, because the result is not
7691 available for one instruction, so if the very first instruction
7692 in the function refers to the register, it will see the wrong
7693 value. */
7694 fprintf (file, "\tnop\n");
7695
7696 fprintf (file, "\t.set\treorder\n");
7697
7698#ifndef FUNCTION_NAME_ALREADY_DECLARED
7699 fputs ("\t.end\t", file);
7700 assemble_name (file, stubname);
7701 fputs ("\n", file);
7702#endif
7703
7704 fprintf (file, "\t.set\tmips16\n");
7705
7706 function_section (current_function_decl);
7707}
7708
7709/* We keep a list of functions for which we have already built stubs
7710 in build_mips16_call_stub. */
7711
7712struct mips16_stub
7713{
7714 struct mips16_stub *next;
7715 char *name;
7716 int fpret;
7717};
7718
7719static struct mips16_stub *mips16_stubs;
7720
7721/* Build a call stub for a mips16 call. A stub is needed if we are
7722 passing any floating point values which should go into the floating
7723 point registers. If we are, and the call turns out to be to a 32
7724 bit function, the stub will be used to move the values into the
7725 floating point registers before calling the 32 bit function. The
7726 linker will magically adjust the function call to either the 16 bit
7727 function or the 32 bit stub, depending upon where the function call
7728 is actually defined.
7729
7730 Similarly, we need a stub if the return value might come back in a
7731 floating point register.
7732
7733 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
7734 (RETVAL is NULL if this is call rather than call_value). FP_CODE
7735 is the code built by function_arg. This function returns a nonzero
7736 value if it builds the call instruction itself. */
7737
7738int
7739build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
7740 rtx retval;
7741 rtx fnmem;
7742 rtx arg_size;
7743 int fp_code;
7744{
7745 int fpret;
7746 rtx fn;
7747 char *fnname, *secname, *stubname;
7748 struct mips16_stub *l;
7749 tree stubid, stubdecl;
7750 int need_comma;
7751 unsigned int f;
7752
7753 /* We don't need to do anything if we aren't in mips16 mode, or if
7754 we were invoked with the -msoft-float option. */
7755 if (! TARGET_MIPS16 || ! mips16_hard_float)
7756 return 0;
7757
7758 /* Figure out whether the value might come back in a floating point
7759 register. */
7760 fpret = (retval != 0
7761 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7762 && (! TARGET_SINGLE_FLOAT
7763 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
7764
7765 /* We don't need to do anything if there were no floating point
7766 arguments and the value will not be returned in a floating point
7767 register. */
7768 if (fp_code == 0 && ! fpret)
7769 return 0;
7770
7771 if (GET_CODE (fnmem) != MEM)
7772 abort ();
7773 fn = XEXP (fnmem, 0);
7774
7775 /* We don't need to do anything if this is a call to a special
7776 mips16 support function. */
7777 if (GET_CODE (fn) == SYMBOL_REF
7778 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7779 return 0;
7780
a53f72db 7781 /* This code will only work for o32 and o64 abis. The other ABI's
2bcb2ab3 7782 require more sophisticated support. */
a53f72db 7783 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
2bcb2ab3
GK		 7784 abort ();
7785
7786 /* We can only handle SFmode and DFmode floating point return
7787 values. */
7788 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7789 abort ();
7790
7791 /* If we're calling via a function pointer, then we must always call
7792 via a stub. There are magic stubs provided in libgcc.a for each
7793 of the required cases. Each of them expects the function address
7794 to arrive in register $2. */
7795
7796 if (GET_CODE (fn) != SYMBOL_REF)
7797 {
7798 char buf[30];
7799 tree id;
7800 rtx stub_fn, stub_mem, insn;
7801
7802 /* ??? If this code is modified to support other ABI's, we need
7803 to handle PARALLEL return values here. */
7804
7805 sprintf (buf, "__mips16_call_stub_%s%d",
7806 (fpret
7807 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7808 : ""),
7809 fp_code);
7810 id = get_identifier (buf);
7811 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
7812 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
7813
7814 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
7815
7816 if (retval == NULL_RTX)
7817 insn = gen_call_internal0 (stub_mem, arg_size,
7818 gen_rtx (REG, SImode,
7819 GP_REG_FIRST + 31));
7820 else
7821 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
7822 gen_rtx (REG, SImode,
7823 GP_REG_FIRST + 31));
7824 insn = emit_call_insn (insn);
7825
7826 /* Put the register usage information on the CALL. */
7827 if (GET_CODE (insn) != CALL_INSN)
7828 abort ();
7829 CALL_INSN_FUNCTION_USAGE (insn) =
7830 gen_rtx (EXPR_LIST, VOIDmode,
7831 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
7832 CALL_INSN_FUNCTION_USAGE (insn));
7833
7834 /* If we are handling a floating point return value, we need to
7835 save $18 in the function prologue. Putting a note on the
7836 call will mean that regs_ever_live[$18] will be true if the
7837 call is not eliminated, and we can check that in the prologue
7838 code. */
7839 if (fpret)
7840 CALL_INSN_FUNCTION_USAGE (insn) =
7841 gen_rtx (EXPR_LIST, VOIDmode,
7842 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7843 CALL_INSN_FUNCTION_USAGE (insn));
7844
7845 /* Return 1 to tell the caller that we've generated the call
7846 insn. */
7847 return 1;
7848 }
7849
7850 /* We know the function we are going to call. If we have already
7851 built a stub, we don't need to do anything further. */
7852
7853 fnname = XSTR (fn, 0);
7854 for (l = mips16_stubs; l != NULL; l = l->next)
7855 if (strcmp (l->name, fnname) == 0)
7856 break;
7857
7858 if (l == NULL)
7859 {
7860 /* Build a special purpose stub. When the linker sees a
7861 function call in mips16 code, it will check where the target
7862 is defined. If the target is a 32 bit call, the linker will
7863 search for the section defined here. It can tell which
7864 symbol this section is associated with by looking at the
7865 relocation information (the name is unreliable, since this
7866 might be a static function). If such a section is found, the
7867 linker will redirect the call to the start of the magic
7868 section.
7869
7870 If the function does not return a floating point value, the
7871 special stub section is named
7872 .mips16.call.FNNAME
7873
7874 If the function does return a floating point value, the stub
7875 section is named
7876 .mips16.call.fp.FNNAME
7877 */
7878
7879 secname = (char *) alloca (strlen (fnname) + 40);
7880 sprintf (secname, ".mips16.call.%s%s",
7881 fpret ? "fp." : "",
7882 fnname);
7883 stubname = (char *) alloca (strlen (fnname) + 20);
7884 sprintf (stubname, "__call_stub_%s%s",
7885 fpret ? "fp_" : "",
7886 fnname);
7887 stubid = get_identifier (stubname);
7888 stubdecl = build_decl (FUNCTION_DECL, stubid,
7889 build_function_type (void_type_node, NULL_TREE));
7890 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7891
7892 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7893 (fpret
7894 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7895 : ""),
7896 fnname);
7897 need_comma = 0;
7898 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7899 {
7900 fprintf (asm_out_file, "%s%s",
7901 need_comma ? ", " : "",
7902 (f & 3) == 1 ? "float" : "double");
7903 need_comma = 1;
7904 }
7905 fprintf (asm_out_file, ")\n");
7906
7907 fprintf (asm_out_file, "\t.set\tnomips16\n");
7908 assemble_start_function (stubdecl, stubname);
7909
7910#ifndef FUNCTION_NAME_ALREADY_DECLARED
7911 fputs ("\t.ent\t", asm_out_file);
7912 assemble_name (asm_out_file, stubname);
7913 fputs ("\n", asm_out_file);
7914
7915 assemble_name (asm_out_file, stubname);
7916 fputs (":\n", asm_out_file);
7917#endif
7918
7919 /* We build the stub code by hand. That's the only way we can
7920 do it, since we can't generate 32 bit code during a 16 bit
7921 compilation. */
7922
7923 /* We don't want the assembler to insert any nops here. */
7924 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7925
7926 mips16_fp_args (asm_out_file, fp_code, 0);
7927
7928 if (! fpret)
7929 {
7930 fprintf (asm_out_file, "\t.set\tnoat\n");
7931 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7932 fnname);
7933 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7934 fprintf (asm_out_file, "\t.set\tat\n");
7935 /* Unfortunately, we can't fill the jump delay slot. We
7936 can't fill with one of the mtc1 instructions, because the
7937 result is not available for one instruction, so if the
7938 very first instruction in the function refers to the
7939 register, it will see the wrong value. */
7940 fprintf (asm_out_file, "\tnop\n");
7941 }
7942 else
7943 {
7944 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7945 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7946 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7947 /* As above, we can't fill the delay slot. */
7948 fprintf (asm_out_file, "\tnop\n");
7949 if (GET_MODE (retval) == SFmode)
7950 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7951 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7952 else
7953 {
a3bc83cc
AC		 7954 if (TARGET_BIG_ENDIAN)
7955 {
7956 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7957 reg_names[GP_REG_FIRST + 2],
7958 reg_names[FP_REG_FIRST + 1]);
7959 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7960 reg_names[GP_REG_FIRST + 3],
7961 reg_names[FP_REG_FIRST + 0]);
7962 }
7963 else
7964 {
7965 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7966 reg_names[GP_REG_FIRST + 2],
7967 reg_names[FP_REG_FIRST + 0]);
7968 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7969 reg_names[GP_REG_FIRST + 3],
7970 reg_names[FP_REG_FIRST + 1]);
7971 }
2bcb2ab3
GK		 7972 }
7973 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7974 /* As above, we can't fill the delay slot. */
7975 fprintf (asm_out_file, "\tnop\n");
7976 }
7977
7978 fprintf (asm_out_file, "\t.set\treorder\n");
7979
7980#ifdef ASM_DECLARE_FUNCTION_SIZE
7981 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7982#endif
7983
7984#ifndef FUNCTION_NAME_ALREADY_DECLARED
7985 fputs ("\t.end\t", asm_out_file);
7986 assemble_name (asm_out_file, stubname);
7987 fputs ("\n", asm_out_file);
7988#endif
7989
7990 fprintf (asm_out_file, "\t.set\tmips16\n");
7991
7992 /* Record this stub. */
7993 l = (struct mips16_stub *) xmalloc (sizeof *l);
ad85216e 7994 l->name = xstrdup (fnname);
2bcb2ab3
GK		 7995 l->fpret = fpret;
7996 l->next = mips16_stubs;
7997 mips16_stubs = l;
7998 }
7999
8000 /* If we expect a floating point return value, but we've built a
8001 stub which does not expect one, then we're in trouble. We can't
8002 use the existing stub, because it won't handle the floating point
8003 value. We can't build a new stub, because the linker won't know
8004 which stub to use for the various calls in this object file.
8005 Fortunately, this case is illegal, since it means that a function
8006 was declared in two different ways in a single compilation. */
8007 if (fpret && ! l->fpret)
8008 error ("can not handle inconsistent calls to `%s'", fnname);
8009
8010 /* If we are calling a stub which handles a floating point return
8011 value, we need to arrange to save $18 in the prologue. We do
8012 this by marking the function call as using the register. The
8013 prologue will later see that it is used, and emit code to save
8014 it. */
8015
8016 if (l->fpret)
8017 {
8018 rtx insn;
8019
8020 if (retval == NULL_RTX)
8021 insn = gen_call_internal0 (fnmem, arg_size,
8022 gen_rtx (REG, SImode,
8023 GP_REG_FIRST + 31));
8024 else
8025 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8026 gen_rtx (REG, SImode,
8027 GP_REG_FIRST + 31));
8028 insn = emit_call_insn (insn);
8029
8030 if (GET_CODE (insn) != CALL_INSN)
8031 abort ();
8032
8033 CALL_INSN_FUNCTION_USAGE (insn) =
8034 gen_rtx (EXPR_LIST, VOIDmode,
8035 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8036 CALL_INSN_FUNCTION_USAGE (insn));
8037
8038 /* Return 1 to tell the caller that we've generated the call
8039 insn. */
8040 return 1;
8041 }
8042
8043 /* Return 0 to let the caller generate the call insn. */
8044 return 0;
8045}
8046
8047/* This function looks through the code for a function, and tries to
8048 optimize the usage of the $gp register. We arrange to copy $gp
8049 into a pseudo-register, and then let gcc's normal reload handling
8050 deal with the pseudo-register. Unfortunately, if reload choose to
8051 put the pseudo-register into a call-clobbered register, it will
8052 emit saves and restores for that register around any function
8053 calls. We don't need the saves, and it's faster to copy $gp than
8054 to do an actual restore. ??? This still means that we waste a
8055 stack slot.
8056
8057 This is an optimization, and the code which gcc has actually
8058 generated is correct, so we do not need to catch all cases. */
8059
8060static void
8061mips16_optimize_gp (first)
8062 rtx first;
8063{
8064 rtx gpcopy, slot, insn;
8065
8066 /* Look through the instructions. Set GPCOPY to the register which
8067 holds a copy of $gp. Set SLOT to the stack slot where it is
8068 saved. If we find an instruction which sets GPCOPY to anything
8069 other than $gp or SLOT, then we can't use it. If we find an
8070 instruction which sets SLOT to anything other than GPCOPY, we
8071 can't use it. */
8072
8073 gpcopy = NULL_RTX;
8074 slot = NULL_RTX;
8075 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8076 {
8077 rtx set;
8078
8079 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8080 continue;
8081
8082 set = PATTERN (insn);
8083
8084 /* We know that all references to memory will be inside a SET,
8085 because there is no other way to access memory on the mips16.
8086 We don't have to worry about a PARALLEL here, because the
8087 mips.md file will never generate them for memory references. */
8088 if (GET_CODE (set) != SET)
8089 continue;
8090
8091 if (gpcopy == NULL_RTX
8092 && GET_CODE (SET_SRC (set)) == CONST
8093 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8094 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8095 && GET_CODE (SET_DEST (set)) == REG
8096 && GET_MODE (SET_DEST (set)) == Pmode)
8097 gpcopy = SET_DEST (set);
8098 else if (slot == NULL_RTX
8099 && gpcopy != NULL_RTX
8100 && GET_CODE (SET_DEST (set)) == MEM
8101 && GET_CODE (SET_SRC (set)) == REG
8102 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8103 && GET_MODE (SET_DEST (set)) == Pmode)
8104 {
8105 rtx base, offset;
8106
8107 offset = const0_rtx;
8108 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8109 if (GET_CODE (base) == REG
8110 && (REGNO (base) == STACK_POINTER_REGNUM
8111 || REGNO (base) == FRAME_POINTER_REGNUM))
8112 slot = SET_DEST (set);
8113 }
8114 else if (gpcopy != NULL_RTX
8115 && (GET_CODE (SET_DEST (set)) == REG
8116 || GET_CODE (SET_DEST (set)) == SUBREG)
8117 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8118 && (GET_CODE (SET_DEST (set)) != REG
8119 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8120 || GET_MODE (SET_DEST (set)) != Pmode
8121 || ((GET_CODE (SET_SRC (set)) != CONST
8122 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8123 || (REGNO (XEXP (SET_SRC (set), 0))
8124 != GP_REG_FIRST + 28))
8125 && ! rtx_equal_p (SET_SRC (set), slot))))
8126 break;
8127 else if (slot != NULL_RTX
8128 && GET_CODE (SET_DEST (set)) == MEM
8129 && rtx_equal_p (SET_DEST (set), slot)
8130 && (GET_CODE (SET_SRC (set)) != REG
8131 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8132 break;
8133 }
8134
8135 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8136 different optimization. Any time we find a copy of $28 into a
8137 register, followed by an add of a symbol_ref to that register, we
8138 convert it to load the value from the constant table instead.
8139 The copy and add will take six bytes, just as the load and
8140 constant table entry will take six bytes. However, it is
8141 possible that the constant table entry will be shared.
8142
8143 This could be a peephole optimization, but I don't know if the
8144 peephole code can call force_const_mem.
8145
8146 Using the same register for the copy of $28 and the add of the
8147 symbol_ref is actually pretty likely, since the add instruction
8148 requires the destination and the first addend to be the same
8149 register. */
8150
8151 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8152 {
8153 rtx next;
8154
8155 /* This optimization is only reasonable if the constant table
8156 entries are only 4 bytes. */
8157 if (Pmode != SImode)
8158 return;
8159
8160 for (insn = first; insn != NULL_RTX; insn = next)
8161 {
8162 rtx set1, set2;
8163
8164 next = insn;
8165 do
8166 {
8167 next = NEXT_INSN (next);
8168 }
8169 while (next != NULL_RTX
8170 && (GET_CODE (next) == NOTE
8171 || (GET_CODE (next) == INSN
8172 && (GET_CODE (PATTERN (next)) == USE
8173 || GET_CODE (PATTERN (next)) == CLOBBER))));
8174
8175 if (next == NULL_RTX)
8176 break;
8177
8178 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8179 continue;
8180
8181 if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
8182 continue;
8183
8184 set1 = PATTERN (insn);
8185 if (GET_CODE (set1) != SET)
8186 continue;
8187 set2 = PATTERN (next);
8188 if (GET_CODE (set2) != SET)
8189 continue;
8190
8191 if (GET_CODE (SET_DEST (set1)) == REG
8192 && GET_CODE (SET_SRC (set1)) == CONST
8193 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8194 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8195 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8196 && GET_CODE (SET_SRC (set2)) == PLUS
8197 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8198 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8199 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8200 {
8201 rtx sym;
8202
8203 /* We've found a case we can change to load from the
8204 constant table. */
8205
8206 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8207 if (GET_CODE (sym) != SYMBOL_REF)
8208 abort ();
8209 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8210 force_const_mem (Pmode, sym)),
8211 next);
8212
8213 PUT_CODE (insn, NOTE);
8214 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8215 NOTE_SOURCE_FILE (insn) = 0;
8216
8217 PUT_CODE (next, NOTE);
8218 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8219 NOTE_SOURCE_FILE (next) = 0;
8220 }
8221 }
8222
8223 return;
8224 }
8225
8226 /* We can safely remove all assignments to SLOT from GPCOPY, and
8227 replace all assignments from SLOT to GPCOPY with assignments from
8228 $28. */
8229
8230 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8231 {
8232 rtx set;
8233
8234 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8235 continue;
8236
8237 set = PATTERN (insn);
8238 if (GET_CODE (set) != SET
8239 || GET_MODE (SET_DEST (set)) != Pmode)
8240 continue;
8241
8242 if (GET_CODE (SET_DEST (set)) == MEM
8243 && rtx_equal_p (SET_DEST (set), slot)
8244 && GET_CODE (SET_SRC (set)) == REG
8245 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8246 {
8247 PUT_CODE (insn, NOTE);
8248 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8249 NOTE_SOURCE_FILE (insn) = 0;
8250 }
8251 else if (GET_CODE (SET_DEST (set)) == REG
8252 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8253 && GET_CODE (SET_SRC (set)) == MEM
8254 && rtx_equal_p (SET_SRC (set), slot))
8255 {
8256 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8257 gen_rtx (CONST, Pmode,
8258 gen_rtx (REG, Pmode,
8259 GP_REG_FIRST + 28))),
8260 insn);
8261 PUT_CODE (insn, NOTE);
8262 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8263 NOTE_SOURCE_FILE (insn) = 0;
8264 }
8265 }
8266}
8267
8268/* We keep a list of constants we which we have to add to internal
8269 constant tables in the middle of large functions. */
8270
8271struct constant
8272{
8273 struct constant *next;
8274 rtx value;
8275 rtx label;
8276 enum machine_mode mode;
8277};
8278
8279/* Add a constant to the list in *PCONSTANTS. */
8280
8281static rtx
8282add_constant (pconstants, val, mode)
8283 struct constant **pconstants;
8284 rtx val;
8285 enum machine_mode mode;
8286{
8287 struct constant *c;
8288
8289 for (c = *pconstants; c != NULL; c = c->next)
8290 if (mode == c->mode && rtx_equal_p (val, c->value))
8291 return c->label;
8292
8293 c = (struct constant *) xmalloc (sizeof *c);
8294 c->value = val;
8295 c->mode = mode;
8296 c->label = gen_label_rtx ();
8297 c->next = *pconstants;
8298 *pconstants = c;
8299 return c->label;
8300}
8301
8302/* Dump out the constants in CONSTANTS after INSN. */
8303
8304static void
8305dump_constants (constants, insn)
8306 struct constant *constants;
8307 rtx insn;
8308{
8309 struct constant *c;
8310 int align;
8311
8312 c = constants;
8313 align = 0;
8314 while (c != NULL)
8315 {
8316 rtx r;
8317 struct constant *next;
8318
8319 switch (GET_MODE_SIZE (c->mode))
8320 {
8321 case 1:
8322 align = 0;
8323 break;
8324 case 2:
8325 if (align < 1)
8326 insn = emit_insn_after (gen_align_2 (), insn);
8327 align = 1;
8328 break;
8329 case 4:
8330 if (align < 2)
8331 insn = emit_insn_after (gen_align_4 (), insn);
8332 align = 2;
8333 break;
8334 default:
8335 if (align < 3)
8336 insn = emit_insn_after (gen_align_8 (), insn);
8337 align = 3;
8338 break;
8339 }
8340
8341 insn = emit_label_after (c->label, insn);
8342
8343 switch (c->mode)
8344 {
8345 case QImode:
8346 r = gen_consttable_qi (c->value);
8347 break;
8348 case HImode:
8349 r = gen_consttable_hi (c->value);
8350 break;
8351 case SImode:
8352 r = gen_consttable_si (c->value);
8353 break;
8354 case SFmode:
8355 r = gen_consttable_sf (c->value);
8356 break;
8357 case DImode:
8358 r = gen_consttable_di (c->value);
8359 break;
8360 case DFmode:
8361 r = gen_consttable_df (c->value);
8362 break;
8363 default:
8364 abort ();
8365 }
8366
8367 insn = emit_insn_after (r, insn);
8368
8369 next = c->next;
8370 free (c);
8371 c = next;
8372 }
8373
8374 emit_barrier_after (insn);
8375}
8376
8377/* Find the symbol in an address expression. */
8378
8379static rtx
8380mips_find_symbol (addr)
8381 rtx addr;
8382{
8383 if (GET_CODE (addr) == MEM)
8384 addr = XEXP (addr, 0);
8385 while (GET_CODE (addr) == CONST)
8386 addr = XEXP (addr, 0);
8387 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8388 return addr;
8389 if (GET_CODE (addr) == PLUS)
8390 {
8391 rtx l1, l2;
8392
8393 l1 = mips_find_symbol (XEXP (addr, 0));
8394 l2 = mips_find_symbol (XEXP (addr, 1));
8395 if (l1 != NULL_RTX && l2 == NULL_RTX)
8396 return l1;
8397 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8398 return l2;
8399 }
8400 return NULL_RTX;
8401}
8402
8403/* Exported to toplev.c.
8404
8405 Do a final pass over the function, just before delayed branch
8406 scheduling. */
8407
8408void
8409machine_dependent_reorg (first)
8410 rtx first;
8411{
82305258 8412 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
2bcb2ab3
GK		 8413 rtx insn;
8414 struct constant *constants;
8415
8416 if (! TARGET_MIPS16)
8417 return;
8418
8419 /* If $gp is used, try to remove stores, and replace loads with
8420 copies from $gp. */
8421 if (optimize)
8422 mips16_optimize_gp (first);
8423
8424 /* Scan the function looking for PC relative loads which may be out
8425 of range. All such loads will either be from the constant table,
8426 or be getting the address of a constant string. If the size of
8427 the function plus the size of the constant table is less than
8428 0x8000, then all loads are in range. */
8429
8430 insns_len = 0;
8431 for (insn = first; insn; insn = NEXT_INSN (insn))
8432 {
0ff83799 8433 insns_len += get_attr_length (insn);
2bcb2ab3
GK		 8434
8435 /* ??? We put switch tables in .text, but we don't define
8436 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8437 compute their lengths correctly. */
8438 if (GET_CODE (insn) == JUMP_INSN)
8439 {
8440 rtx body;
8441
8442 body = PATTERN (insn);
8443 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8444 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8445 * GET_MODE_SIZE (GET_MODE (body)));
8446 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8447 }
8448 }
8449
8450 /* Store the original value of insns_len in current_frame_info, so
8451 that simple_memory_operand can look at it. */
8452 current_frame_info.insns_len = insns_len;
8453
8454 pool_size = get_pool_size ();
8455 if (insns_len + pool_size + mips_string_length < 0x8000)
8456 return;
8457
8458 /* Loop over the insns and figure out what the maximum internal pool
8459 size could be. */
8460 max_internal_pool_size = 0;
8461 for (insn = first; insn; insn = NEXT_INSN (insn))
8462 {
8463 if (GET_CODE (insn) == INSN
8464 && GET_CODE (PATTERN (insn)) == SET)
8465 {
8466 rtx src;
8467
8468 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8469 if (src == NULL_RTX)
8470 continue;
8471 if (CONSTANT_POOL_ADDRESS_P (src))
8472 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8473 else if (SYMBOL_REF_FLAG (src))
8474 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8475 }
8476 }
8477
8478 constants = NULL;
8479 addr = 0;
82305258 8480 first_constant_ref = -1;
2bcb2ab3
GK		 8481
8482 for (insn = first; insn; insn = NEXT_INSN (insn))
8483 {
8484 if (GET_CODE (insn) == INSN
8485 && GET_CODE (PATTERN (insn)) == SET)
8486 {
8487 rtx val, src;
8488 enum machine_mode mode;
8489
8490 val = NULL_RTX;
8491 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8492 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8493 {
8494 /* ??? This is very conservative, which means that we
8495 will generate too many copies of the constant table.
8496 The only solution would seem to be some form of
8497 relaxing. */
8498 if (((insns_len - addr)
8499 + max_internal_pool_size
8500 + get_pool_offset (src))
8501 >= 0x8000)
8502 {
8503 val = get_pool_constant (src);
8504 mode = get_pool_mode (src);
8505 }
8506 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8507 }
8508 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8509 {
8510 /* Including all of mips_string_length is conservative,
8511 and so is including all of max_internal_pool_size. */
8512 if (((insns_len - addr)
8513 + max_internal_pool_size
8514 + pool_size
8515 + mips_string_length)
8516 >= 0x8000)
8517 val = src;
8518 mode = Pmode;
8519 max_internal_pool_size -= Pmode;
8520 }
8521
8522 if (val != NULL_RTX)
8523 {
8524 rtx lab, newsrc;
8525
8526 /* This PC relative load is out of range. ??? In the
8527 case of a string constant, we are only guessing that
8528 it is range, since we don't know the offset of a
8529 particular string constant. */
8530
8531 lab = add_constant (&constants, val, mode);
8532 newsrc = gen_rtx (MEM, mode,
8533 gen_rtx (LABEL_REF, VOIDmode, lab));
8534 RTX_UNCHANGING_P (newsrc) = 1;
8535 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8536 SET_DEST (PATTERN (insn)),
8537 newsrc);
8538 INSN_CODE (insn) = -1;
82305258
AH		 8539
8540 if (first_constant_ref < 0)
8541 first_constant_ref = addr;
2bcb2ab3
GK		 8542 }
8543 }
8544
0ff83799 8545 addr += get_attr_length (insn);
2bcb2ab3
GK		 8546
8547 /* ??? We put switch tables in .text, but we don't define
8548 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8549 compute their lengths correctly. */
8550 if (GET_CODE (insn) == JUMP_INSN)
8551 {
8552 rtx body;
8553
8554 body = PATTERN (insn);
8555 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8556 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8557 * GET_MODE_SIZE (GET_MODE (body)));
8558 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8559 }
8560
8561 if (GET_CODE (insn) == BARRIER)
8562 {
8563 /* Output any constants we have accumulated. Note that we
8564 don't need to change ADDR, since its only use is
8565 subtraction from INSNS_LEN, and both would be changed by
8566 the same amount.
8567 ??? If the instructions up to the next barrier reuse a
8568 constant, it would often be better to continue
8569 accumulating. */
8570 if (constants != NULL)
8571 dump_constants (constants, insn);
8572 constants = NULL;
82305258 8573 first_constant_ref = -1;
2bcb2ab3 8574 }
82305258
AH		 8575
8576 if (constants != NULL
8577 && (NEXT_INSN (insn) == NULL
8578 || (first_constant_ref >= 0
8579 && (((addr - first_constant_ref)
8580 + 2 /* for alignment */
8581 + 2 /* for a short jump insn */
8582 + pool_size)
8583 >= 0x8000))))
8584 {
8585 /* If we haven't had a barrier within 0x8000 bytes of a
8586 constant reference or we are at the end of the function,
8587 emit a barrier now. */
2bcb2ab3 8588
82305258
AH		 8589 rtx label, jump, barrier;
8590
8591 label = gen_label_rtx ();
8592 jump = emit_jump_insn_after (gen_jump (label), insn);
8593 JUMP_LABEL (jump) = label;
8594 LABEL_NUSES (label) = 1;
8595 barrier = emit_barrier_after (jump);
8596 emit_label_after (label, barrier);
8597 first_constant_ref = -1;
8598 }
8599 }
2bcb2ab3
GK		 8600
8601 /* ??? If we output all references to a constant in internal
8602 constants table, we don't need to output the constant in the real
8603 constant table, but we have no way to prevent that. */
8604}
cb923660
KR		 8605
8606/* Return nonzero if X is a SIGN or ZERO extend operator. */
8607int
8608extend_operator (x, mode)
8609 rtx x;
38831dfe 8610 enum machine_mode mode ATTRIBUTE_UNUSED;
cb923660
KR		 8611{
8612 enum rtx_code code = GET_CODE (x);
8613 return code == SIGN_EXTEND || code == ZERO_EXTEND;
8614}
8615
8616/* Accept any operator that can be used to shift the high half of the
8617 input value to the lower half, suitable for truncation. The
8618 remainder (the lower half of the input, and the upper half of the
8619 output) will be discarded. */
8620int
8621highpart_shift_operator (x, mode)
8622 rtx x;
38831dfe 8623 enum machine_mode mode ATTRIBUTE_UNUSED;
cb923660
KR		 8624{
8625 enum rtx_code code = GET_CODE (x);
8626 return (code == LSHIFTRT
8627 || code == ASHIFTRT
8628 || code == ROTATERT
8629 || code == ROTATE);
8630}
0ff83799
MM		 8631
8632/* Return the length of INSN. LENGTH is the initial length computed by
8633 attributes in the machine-description file. */
8634
8635int
8636mips_adjust_insn_length (insn, length)
8637 rtx insn;
8638 int length;
8639{
8640 /* A unconditional jump has an unfilled delay slot if it is not part
8641 of a sequence. A conditional jump normally has a delay slot, but
8642 does not on MIPS16. */
8643 if (simplejump_p (insn)
8644 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8645 || GET_CODE (insn) == CALL_INSN)))
8646 length += 4;
8647
8648 /* All MIPS16 instructions are a measly two bytes. */
8649 if (TARGET_MIPS16)
8650 length /= 2;
8651
8652 return length;
8653}
8654
8655/* Output assembly instructions to peform a conditional branch.
8656
8657 INSN is the branch instruction. OPERANDS[0] is the condition.
8658 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8659 of the first operand to the condition. If TWO_OPERANDS_P is
8660 non-zero the comparison takes two operands; OPERANDS[3] will be the
8661 second operand.
8662
8663 If INVERTED_P is non-zero we are to branch if the condition does
8664 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
8665
8666 LENGTH is the length (in bytes) of the sequence we are to generate.
8667 That tells us whether to generate a simple conditional branch, or a
8668 reversed conditional branch around a `jr' instruction. */
8669char *
8670mips_output_conditional_branch (insn,
8671 operands,
8672 two_operands_p,
8673 float_p,
8674 inverted_p,
8675 length)
8676 rtx insn;
8677 rtx *operands;
8678 int two_operands_p;
8679 int float_p;
8680 int inverted_p;
8681 int length;
8682{
8683 static char buffer[200];
8684 /* The kind of comparison we are doing. */
8685 enum rtx_code code = GET_CODE (operands[0]);
8686 /* Non-zero if the opcode for the comparison needs a `z' indicating
8687 that it is a comparision against zero. */
8688 int need_z_p;
8689 /* A string to use in the assembly output to represent the first
8690 operand. */
8691 char *op1 = "%z2";
8692 /* A string to use in the assembly output to represent the second
8693 operand. Use the hard-wired zero register if there's no second
8694 operand. */
8695 char *op2 = (two_operands_p ? ",%z3" : ",%.");
8696 /* The operand-printing string for the comparison. */
8697 char *comp = (float_p ? "%F0" : "%C0");
8698 /* The operand-printing string for the inverted comparison. */
8699 char *inverted_comp = (float_p ? "%W0" : "%N0");
8700
8701 /* The MIPS processors (for levels of the ISA at least two), have
8702 "likely" variants of each branch instruction. These instructions
8703 annul the instruction in the delay slot if the branch is not
8704 taken. */
8705 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8706
8707 if (!two_operands_p)
8708 {
8709 /* To compute whether than A > B, for example, we normally
8710 subtract B from A and then look at the sign bit. But, if we
8711 are doing an unsigned comparison, and B is zero, we don't
8712 have to do the subtraction. Instead, we can just check to
8713 see if A is non-zero. Thus, we change the CODE here to
8714 reflect the simpler comparison operation. */
8715 switch (code)
8716 {
8717 case GTU:
8718 code = NE;
8719 break;
8720
8721 case LEU:
8722 code = EQ;
8723 break;
8724
8725 case GEU:
8726 /* A condition which will always be true. */
8727 code = EQ;
8728 op1 = "%.";
8729 break;
8730
8731 case LTU:
8732 /* A condition which will always be false. */
8733 code = NE;
8734 op1 = "%.";
8735 break;
8736
8737 default:
8738 /* Not a special case. */
c4e992ae 8739 break;
0ff83799
MM		 8740 }
8741 }
8742
8743 /* Relative comparisons are always done against zero. But
8744 equality comparisons are done between two operands, and therefore
8745 do not require a `z' in the assembly language output. */
8746 need_z_p = (!float_p && code != EQ && code != NE);
8747 /* For comparisons against zero, the zero is not provided
8748 explicitly. */
8749 if (need_z_p)
8750 op2 = "";
8751
8752 /* Begin by terminating the buffer. That way we can always use
8753 strcat to add to it. */
8754 buffer[0] = '\0';
8755
8756 switch (length)
8757 {
8758 case 4:
8759 case 8:
8760 /* Just a simple conditional branch. */
8761 if (float_p)
8762 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
8763 inverted_p ? inverted_comp : comp);
8764 else
8765 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
8766 inverted_p ? inverted_comp : comp,
8767 need_z_p ? "z" : "",
8768 op1,
8769 op2);
8770 return buffer;
8771
8772 case 12:
8773 case 16:
8774 {
8775 /* Generate a reversed conditional branch around ` j'
8776 instruction:
8777
8778 .set noreorder
8779 .set nomacro
8780 bc l
8781 nop
8782 j target
8783 .set macro
8784 .set reorder
8785 l:
8786
8787 Because we have to jump four bytes *past* the following
8788 instruction if this branch was annulled, we can't just use
8789 a label, as in the picture above; there's no way to put the
8790 label after the next instruction, as the assembler does not
8791 accept `.L+4' as the target of a branch. (We can't just
8792 wait until the next instruction is output; it might be a
8793 macro and take up more than four bytes. Once again, we see
8794 why we want to eliminate macros.)
8795
8796 If the branch is annulled, we jump four more bytes that we
8797 would otherwise; that way we skip the annulled instruction
8798 in the delay slot. */
8799
8800 char *target
8801 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
8802 char *c;
8803
8804 strcpy (buffer, "%(%<");
8805 c = strchr (buffer, '\0');
8806 /* Generate the reversed comparision. This takes four
8807 bytes. */
8808 if (float_p)
8809 sprintf (c, "%%*b%s\t%%Z2%s",
8810 inverted_p ? comp : inverted_comp,
8811 target);
8812 else
8813 sprintf (c, "%%*b%s%s\t%s%s,%s",
8814 inverted_p ? comp : inverted_comp,
8815 need_z_p ? "z" : "",
8816 op1,
8817 op2,
8818 target);
8819 strcat (c, "\n\tnop\n\tj\t%1");
8820 if (length == 16)
8821 /* The delay slot was unfilled. Since we're inside
8822 .noreorder, the assembler will not fill in the NOP for
8823 us, so we must do it ourselves. */
8824 strcat (buffer, "\n\tnop");
8825 strcat (buffer, "%>%)");
8826 return buffer;
8827 }
8828
8829 /* We do not currently use this code. It handles jumps to
8830 arbitrary locations, using `jr', even across a 256MB boundary.
8831 We could add a -mhuge switch, and then use this code instead of
8832 the `j' alternative above when -mhuge was used. */
8833#if 0
8834 case 16:
8835 case 20:
8836 {
8837 /* Generate a reversed conditional branch around a `jr'
8838 instruction:
8839
8840 .set noreorder
8841 .set nomacro
8842 .set noat
8843 bc l
8844 la $at, target
8845 jr $at
8846 .set at
8847 .set macro
8848 .set reorder
8849 l:
8850
8851 Not pretty, but allows a conditional branch anywhere in the
8852 32-bit address space. If the original branch is annulled,
8853 then the instruction in the delay slot should be executed
8854 only if the branch is taken. The la instruction is really
8855 a macro which will usually take eight bytes, but sometimes
8856 takes only four, if the instruction to which we're jumping
8857 gets its own entry in the global pointer table, which will
8858 happen if its a case label. The assembler will then
8859 generate only a four-byte sequence, rather than eight, and
8860 there seems to be no way to tell it not to. Thus, we can't
8861 just use a `.+x' addressing form; we don't know what value
8862 to give for `x'.
8863
8864 So, we resort to using the explicit relocation syntax
8865 available in the assembler and do:
8866
8867 lw $at,%got_page(target)($gp)
8868 daddiu $at,$at,%got_ofst(target)
8869
8870 That way, this always takes up eight bytes, and we can use
8871 the `.+x' form. Of course, these explicit machinations
8872 with relocation will not work with old assemblers. Then
8873 again, neither do out-of-range branches, so we haven't lost
8874 anything. */
8875
8876 /* The target of the reversed branch. */
8877 char *target
8878 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
8879 char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
8880 char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
8881 char *c;
8882
8883 strcpy (buffer, "%(%<%[");
8884 c = strchr (buffer, '\0');
8885 /* Generate the reversed comparision. This takes four
8886 bytes. */
8887 if (float_p)
8888 sprintf (c, "%%*b%s\t%%Z2%s",
8889 inverted_p ? comp : inverted_comp,
8890 target);
8891 else
8892 sprintf (c, "%%*b%s%s\t%s%s,%s",
8893 inverted_p ? comp : inverted_comp,
8894 need_z_p ? "z" : "",
8895 op1,
8896 op2,
8897 target);
8898 c = strchr (buffer, '\0');
8899 /* Generate the load-address, and jump. This takes twelve
8900 bytes, for a total of 16. */
8901 sprintf (c,
8902 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
8903 at_register,
8904 gp_register,
8905 at_register,
8906 at_register,
8907 at_register);
8908 if (length == 20)
8909 /* The delay slot was unfilled. Since we're inside
8910 .noreorder, the assembler will not fill in the NOP for
8911 us, so we must do it ourselves. */
8912 strcat (buffer, "\n\tnop");
8913 strcat (buffer, "%]%>%)");
8914 return buffer;
8915 }
8916#endif
8917
8918 default:
8919 abort ();
8920 }
8921
8922 /* NOTREACHED */
8923 return 0;
8924}
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