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expr.c (move_block_from_reg): Remove "size" parm.
[thirdparty/gcc.git] / gcc / config / mips / mips.c
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cee98a59 1/* Subroutines for insn-output.c for MIPS
214be03f 2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
2d2a50c3 3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
cee98a59 4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
b2a68403 5 Changes by Michael Meissner, meissner@osf.org.
147255d8
JW		 6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
cee98a59
MM		 8
9This file is part of GNU CC.
10
11GNU CC is free software; you can redistribute it and/or modify
12it under the terms of the GNU General Public License as published by
13the Free Software Foundation; either version 2, or (at your option)
14any later version.
15
16GNU CC is distributed in the hope that it will be useful,
17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
22along with GNU CC; see the file COPYING. If not, write to
0e29e3c9
RK		 23the Free Software Foundation, 59 Temple Place - Suite 330,
24Boston, MA 02111-1307, USA. */
cee98a59 25
147255d8
JW		 26/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
29
cee98a59 30#include "config.h"
50b2596f 31#include "system.h"
4977bab6
ZW		 32#include "coretypes.h"
33#include "tm.h"
50b2596f 34#include <signal.h>
cee98a59
MM		 35#include "rtl.h"
36#include "regs.h"
37#include "hard-reg-set.h"
38#include "real.h"
39#include "insn-config.h"
40#include "conditions.h"
cee98a59 41#include "insn-attr.h"
cee98a59 42#include "recog.h"
50b2596f 43#include "toplev.h"
c5c76735 44#include "output.h"
cee98a59 45#include "tree.h"
49ad7cfa 46#include "function.h"
cee98a59
MM		 47#include "expr.h"
48#include "flags.h"
2bcb2ab3 49#include "reload.h"
50b2596f 50#include "output.h"
bd9f1972 51#include "tm_p.h"
d07d525a 52#include "ggc.h"
7719ffbf 53#include "gstab.h"
920ae24b
RH		 54#include "hashtab.h"
55#include "debug.h"
672a6f42
NB		 56#include "target.h"
57#include "target-def.h"
cafe096b 58#include "integrate.h"
cee98a59
MM		 59
60#ifdef __GNU_STAB__
61#define STAB_CODE_TYPE enum __stab_debug_code
62#else
63#define STAB_CODE_TYPE int
64#endif
65
bd9f1972 66extern tree lookup_name PARAMS ((tree));
cee98a59 67
34b650b3
MM		 68/* Enumeration for all of the relational tests, so that we can build
69 arrays indexed by the test type, and not worry about the order
987ba558 70 of EQ, NE, etc. */
34b650b3
MM		 71
72enum internal_test {
73 ITEST_EQ,
74 ITEST_NE,
75 ITEST_GT,
76 ITEST_GE,
77 ITEST_LT,
78 ITEST_LE,
79 ITEST_GTU,
80 ITEST_GEU,
81 ITEST_LTU,
82 ITEST_LEU,
83 ITEST_MAX
84 };
85
cafe096b
EC		 86/* Return true if it is likely that the given mode will be accessed
87 using only a single instruction. */
88#define SINGLE_WORD_MODE_P(MODE) \
89 ((MODE) != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
90
91
92/* Classifies a non-literal integer constant.
93
94 CONSTANT_NONE
95 Not one of the constants below.
96
97 CONSTANT_GP
98 The global pointer, treated as a constant when TARGET_MIPS16.
99 The rtx has the form:
100
101 (const (reg $gp)).
102
103 CONSTANT_RELOC
104 A signed 16-bit relocation against either a symbol
105 or a symbol plus an offset. The relocation has the form:
106
107 (unspec [(SYMBOL) ...] RELOC)
108
109 Any offset is added outside the unspec, such as:
110
111 (plus (unspec [(SYMBOL) ...] RELOC) (const_int OFFSET))
112
113 In either case, the whole expression is wrapped in a (const ...).
114
115 CONSTANT_SYMBOLIC
116 A reference to a symbol, possibly with an offset. */
117enum mips_constant_type {
118 CONSTANT_NONE,
119 CONSTANT_GP,
120 CONSTANT_RELOC,
121 CONSTANT_SYMBOLIC
122};
123
124
125/* Classifies a SYMBOL_REF or LABEL_REF.
126
127 SYMBOL_GENERAL
128 Used when none of the below apply.
129
130 SYMBOL_SMALL_DATA
131 The symbol refers to something in a small data section.
132
133 SYMBOL_CONSTANT_POOL
134 The symbol refers to something in the mips16 constant pool.
135
136 SYMBOL_GOT_LOCAL
137 The symbol refers to local data that will be found using
138 the global offset table.
139
140 SYMBOL_GOT_GLOBAL
141 Likewise non-local data. */
142enum mips_symbol_type {
143 SYMBOL_GENERAL,
144 SYMBOL_SMALL_DATA,
145 SYMBOL_CONSTANT_POOL,
146 SYMBOL_GOT_LOCAL,
147 SYMBOL_GOT_GLOBAL
148};
149
150
151/* Classifies an address.
152
153 ADDRESS_INVALID
154 The address should be rejected as invalid.
155
156 ADDRESS_REG
157 A natural register + offset address. The register satisfies
158 mips_valid_base_register_p and the offset is a const_arith_operand.
159
160 ADDRESS_LO_SUM
161 A LO_SUM rtx. The first operand is a valid base register and
162 the second operand is a symbolic address.
163
164 ADDRESS_CONST_INT
165 A signed 16-bit constant address.
166
167 ADDRESS_SYMBOLIC:
168 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
169enum mips_address_type {
170 ADDRESS_INVALID,
171 ADDRESS_REG,
172 ADDRESS_LO_SUM,
173 ADDRESS_CONST_INT,
174 ADDRESS_SYMBOLIC
175};
176
881060d0
JL		 177
178struct constant;
4d72536e 179struct mips_arg_info;
cafe096b
EC		 180struct mips_constant_info;
181struct mips_address_info;
b259a9a6 182struct mips_integer_op;
cafe096b
EC		 183static enum mips_constant_type mips_classify_constant
184 PARAMS ((struct mips_constant_info *, rtx));
185static enum mips_symbol_type mips_classify_symbol
186 PARAMS ((rtx));
187static bool mips_valid_base_register_p
188 PARAMS ((rtx, enum machine_mode, int));
189static bool mips_symbolic_address_p
190 PARAMS ((rtx, HOST_WIDE_INT,
191 enum machine_mode, int));
192static enum mips_address_type mips_classify_address
193 PARAMS ((struct mips_address_info *,
194 rtx, enum machine_mode, int, int));
f6da8bc3 195static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
8ab907e8
RS		 196static void get_float_compare_codes PARAMS ((enum rtx_code, enum rtx_code *,
197 enum rtx_code *));
cafe096b
EC		 198static const char *mips_reloc_string PARAMS ((int));
199static bool mips_splittable_symbol_p PARAMS ((enum mips_symbol_type));
200static int mips_symbol_insns PARAMS ((enum mips_symbol_type));
201static bool mips16_unextended_reference_p
202 PARAMS ((enum machine_mode mode,
203 rtx, rtx));
204static rtx mips_force_temporary PARAMS ((rtx, rtx));
205static rtx mips_add_offset PARAMS ((rtx, HOST_WIDE_INT));
206static rtx mips_load_got PARAMS ((rtx, rtx, int));
207static rtx mips_load_got16 PARAMS ((rtx, int));
208static rtx mips_load_got32 PARAMS ((rtx, rtx, int, int));
209static rtx mips_emit_high PARAMS ((rtx, rtx));
210static bool mips_legitimize_symbol PARAMS ((rtx, rtx *, int));
211static rtx mips_reloc PARAMS ((rtx, int));
212static rtx mips_lui_reloc PARAMS ((rtx, int));
b259a9a6
RS		 213static unsigned int mips_build_shift PARAMS ((struct mips_integer_op *,
214 HOST_WIDE_INT));
215static unsigned int mips_build_lower PARAMS ((struct mips_integer_op *,
216 unsigned HOST_WIDE_INT));
217static unsigned int mips_build_integer PARAMS ((struct mips_integer_op *,
218 unsigned HOST_WIDE_INT));
219static void mips_move_integer PARAMS ((rtx, unsigned HOST_WIDE_INT));
cafe096b
EC		 220static void mips_legitimize_const_move PARAMS ((enum machine_mode,
221 rtx, rtx));
f6da8bc3 222static int m16_check_op PARAMS ((rtx, int, int, int));
cafe096b 223static bool mips_function_ok_for_sibcall PARAMS ((tree, tree));
c94c9817 224static void block_move_loop PARAMS ((rtx, rtx,
7dac2f89 225 unsigned int,
c94c9817
MM		 226 int,
227 rtx, rtx));
f6da8bc3 228static void block_move_call PARAMS ((rtx, rtx, rtx));
4d72536e
RS		 229static void mips_arg_info PARAMS ((const CUMULATIVE_ARGS *,
230 enum machine_mode,
231 tree, int,
232 struct mips_arg_info *));
cafe096b
EC		 233static bool mips_get_unaligned_mem PARAMS ((rtx *, unsigned int,
234 int, rtx *, rtx *));
a8b4881f 235static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT));
5b0f0db6
RS		 236static void mips_set_frame_expr PARAMS ((rtx));
237static rtx mips_frame_set PARAMS ((rtx, int));
67070ffe
RS		 238static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
239 HOST_WIDE_INT));
a8b4881f 240static void save_restore_insns PARAMS ((int, rtx, long));
f6da8bc3
KG		 241static void mips16_fp_args PARAMS ((FILE *, int, int));
242static void build_mips16_function_stub PARAMS ((FILE *));
243static void mips16_optimize_gp PARAMS ((rtx));
244static rtx add_constant PARAMS ((struct constant **,
881060d0
JL		 245 rtx,
246 enum machine_mode));
f6da8bc3 247static void dump_constants PARAMS ((struct constant *,
881060d0 248 rtx));
f6da8bc3
KG		 249static rtx mips_find_symbol PARAMS ((rtx));
250static void abort_with_insn PARAMS ((rtx, const char *))
e2fe6aba 251 ATTRIBUTE_NORETURN;
f6da8bc3 252static int symbolic_expression_p PARAMS ((rtx));
301d03af 253static bool mips_assemble_integer PARAMS ((rtx, unsigned int, int));
08c148a8
NB		 254static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
255static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
a27fb29b
RS		 256static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
257static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
258static bool mips_strict_matching_cpu_name_p PARAMS ((const char *,
259 const char *));
260static bool mips_matching_cpu_name_p PARAMS ((const char *,
261 const char *));
262static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
263 const char *));
264static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
920ae24b
RH		 265static void copy_file_data PARAMS ((FILE *, FILE *));
266#ifdef TARGET_IRIX6
267static void iris6_asm_named_section_1 PARAMS ((const char *,
268 unsigned int,
269 unsigned int));
7c262518 270static void iris6_asm_named_section PARAMS ((const char *,
7c262518 271 unsigned int));
920ae24b
RH		 272static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
273static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
274static int iris6_section_align_1 PARAMS ((void **, void *));
275#endif
c237e94a 276static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
b875d2ee 277static int mips_issue_rate PARAMS ((void));
920ae24b 278
e2500fed 279static struct machine_function * mips_init_machine_status PARAMS ((void));
ae46c4e0
RH		 280static void mips_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
281 ATTRIBUTE_UNUSED;
282static void mips_unique_section PARAMS ((tree, int))
283 ATTRIBUTE_UNUSED;
b64a1b53
RH		 284static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
285 unsigned HOST_WIDE_INT));
5ce6f47b 286static int mips_use_dfa_pipeline_interface PARAMS ((void));
3c50106f 287static bool mips_rtx_costs PARAMS ((rtx, int, int, int *));
cafe096b
EC		 288static int mips_address_cost PARAMS ((rtx));
289static void mips_encode_section_info PARAMS ((tree, rtx, int));
3c50106f 290
c8d1b2b7 291
b2471838
RS		 292/* Structure to be filled in by compute_frame_size with register
293 save masks, and offsets for the current function. */
294
295struct mips_frame_info GTY(())
296{
297 long total_size; /* # bytes that the entire frame takes up */
298 long var_size; /* # bytes that variables take up */
299 long args_size; /* # bytes that outgoing arguments take up */
300 long extra_size; /* # bytes of extra gunk */
301 int gp_reg_size; /* # bytes needed to store gp regs */
302 int fp_reg_size; /* # bytes needed to store fp regs */
303 long mask; /* mask of saved gp registers */
304 long fmask; /* mask of saved fp registers */
305 long gp_save_offset; /* offset from vfp to store gp registers */
306 long fp_save_offset; /* offset from vfp to store fp registers */
307 long gp_sp_offset; /* offset from new sp to store gp registers */
308 long fp_sp_offset; /* offset from new sp to store fp registers */
309 int initialized; /* != 0 if frame size already calculated */
310 int num_gp; /* number of gp registers saved */
311 int num_fp; /* number of fp registers saved */
312};
313
e2500fed 314struct machine_function GTY(()) {
c8d1b2b7
AO		 315 /* Pseudo-reg holding the address of the current function when
316 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
317 used by mips_finalize_pic if it was created. */
318 rtx embedded_pic_fnaddr_rtx;
319
320 /* Pseudo-reg holding the value of $28 in a mips16 function which
321 refers to GP relative global variables. */
322 rtx mips16_gp_pseudo_rtx;
b2471838
RS		 323
324 /* Current frame information, calculated by compute_frame_size. */
325 struct mips_frame_info frame;
326
327 /* Length of instructions in function; mips16 only. */
328 long insns_len;
c8d1b2b7
AO		 329};
330
4d72536e
RS		 331/* Information about a single argument. */
332struct mips_arg_info
333{
334 /* True if the argument is a record or union type. */
335 bool struct_p;
336
337 /* True if the argument is passed in a floating-point register, or
338 would have been if we hadn't run out of registers. */
339 bool fpr_p;
340
341 /* The argument's size, in bytes. */
342 unsigned int num_bytes;
343
344 /* The number of words passed in registers, rounded up. */
345 unsigned int reg_words;
346
347 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
348 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
349 on the stack. */
350 unsigned int reg_offset;
351
352 /* The number of words that must be passed on the stack, rounded up. */
353 unsigned int stack_words;
354
355 /* The offset from the start of the stack overflow area of the argument's
a0ab749a 356 first stack word. Only meaningful when STACK_WORDS is nonzero. */
4d72536e
RS		 357 unsigned int stack_offset;
358};
c8d1b2b7 359
cafe096b
EC		 360
361/* Struct for recording constants. The meaning of the fields depends
362 on a mips_constant_type:
363
364 CONSTANT_NONE
365 CONSTANT_GP
366 No fields are valid.
367
368 CONSTANT_RELOC
369 SYMBOL is the relocation UNSPEC and OFFSET is the offset applied
370 to the symbol.
371
372 CONSTANT_SYMBOLIC
373 SYMBOL is the referenced symbol and OFFSET is the constant offset. */
374struct mips_constant_info
375{
376 rtx symbol;
377 HOST_WIDE_INT offset;
378};
379
380
381/* Information about an address described by mips_address_type.
382
383 ADDRESS_INVALID
384 ADDRESS_CONST_INT
385 No fields are used.
386
387 ADDRESS_REG
388 REG is the base register and OFFSET is the constant offset.
389
390 ADDRESS_LO_SUM
391 REG is the register that contains the high part of the address,
392 OFFSET is the symbolic address being referenced, and C contains
393 the individual components of the symbolic address.
394
395 ADDRESS_SYMBOLIC
396 C contains the symbol and offset. */
397struct mips_address_info
398{
399 rtx reg;
400 rtx offset;
401 struct mips_constant_info c;
402};
403
404
b259a9a6
RS		 405/* One stage in a constant building sequence. These sequences have
406 the form:
407
408 A = VALUE[0]
409 A = A CODE[1] VALUE[1]
410 A = A CODE[2] VALUE[2]
411 ...
412
413 where A is an accumulator, each CODE[i] is a binary rtl operation
414 and each VALUE[i] is a constant integer. */
415struct mips_integer_op {
416 enum rtx_code code;
417 unsigned HOST_WIDE_INT value;
418};
419
420
421/* The largest number of operations needed to load an integer constant.
422 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
423 When the lowest bit is clear, we can try, but reject a sequence with
424 an extra SLL at the end. */
425#define MIPS_MAX_INTEGER_OPS 7
426
427
cee98a59
MM		 428/* Global variables for machine-dependent things. */
429
430/* Threshold for data being put into the small data/bss area, instead
431 of the normal data area (references to the small data/bss area take
432 1 instruction, and use the global pointer, references to the normal
433 data area takes 2 instructions). */
434int mips_section_threshold = -1;
435
436/* Count the number of .file directives, so that .loc is up to date. */
437int num_source_filenames = 0;
438
cee98a59
MM		 439/* Count the number of sdb related labels are generated (to find block
440 start and end boundaries). */
441int sdb_label_count = 0;
442
987ba558 443/* Next label # for each statement for Silicon Graphics IRIS systems. */
cee98a59
MM		 444int sym_lineno = 0;
445
a0ab749a 446/* Nonzero if inside of a function, because the stupid MIPS asm can't
cee98a59
MM		 447 handle .files inside of functions. */
448int inside_function = 0;
449
cee98a59
MM		 450/* Files to separate the text and the data output, so that all of the data
451 can be emitted before the text, which will mean that the assembler will
452 generate smaller code, based on the global pointer. */
453FILE *asm_out_data_file;
454FILE *asm_out_text_file;
455
456/* Linked list of all externals that are to be emitted when optimizing
457 for the global pointer if they haven't been declared by the end of
458 the program with an appropriate .comm or initialization. */
459
f5963e61
JL		 460struct extern_list
461{
cee98a59 462 struct extern_list *next; /* next external */
bd9f1972 463 const char *name; /* name of the external */
cee98a59
MM		 464 int size; /* size in bytes */
465} *extern_head = 0;
466
cee98a59 467/* Name of the file containing the current function. */
e2fe6aba 468const char *current_function_file = "";
cee98a59
MM		 469
470/* Warning given that Mips ECOFF can't support changing files
471 within a function. */
472int file_in_function_warning = FALSE;
473
c831afd5 474/* Whether to suppress issuing .loc's because the user attempted
cee98a59
MM		 475 to change the filename within a function. */
476int ignore_line_number = FALSE;
477
478/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
479int set_noreorder;
480int set_noat;
481int set_nomacro;
482int set_volatile;
483
484/* The next branch instruction is a branch likely, not branch normal. */
485int mips_branch_likely;
486
487/* Count of delay slots and how many are filled. */
488int dslots_load_total;
489int dslots_load_filled;
490int dslots_jump_total;
491int dslots_jump_filled;
492
493/* # of nops needed by previous insn */
494int dslots_number_nops;
495
496/* Number of 1/2/3 word references to data items (ie, not jal's). */
497int num_refs[3];
498
499/* registers to check for load delay */
500rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
501
a0b6cdee
GM		 502/* Cached operands, and operator to compare for use in set/branch/trap
503 on condition codes. */
cee98a59
MM		 504rtx branch_cmp[2];
505
506/* what type of branch to use */
507enum cmp_type branch_type;
508
7dac2f89
EC		 509/* The target cpu for code generation. */
510enum processor_type mips_arch;
a27fb29b 511const struct mips_cpu_info *mips_arch_info;
7dac2f89
EC		 512
513/* The target cpu for optimization and scheduling. */
514enum processor_type mips_tune;
a27fb29b 515const struct mips_cpu_info *mips_tune_info;
7dac2f89 516
cee98a59
MM		 517/* which instruction set architecture to use. */
518int mips_isa;
519
009da785 520/* which abi to use. */
04bd620d 521int mips_abi;
ade6c319 522
cee98a59 523/* Strings to hold which cpu and instruction set architecture to use. */
7dac2f89
EC		 524const char *mips_arch_string; /* for -march=<xxx> */
525const char *mips_tune_string; /* for -mtune=<xxx> */
e2fe6aba
KG		 526const char *mips_isa_string; /* for -mips{1,2,3,4} */
527const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
cee98a59 528
2bcb2ab3
GK		 529/* Whether we are generating mips16 code. This is a synonym for
530 TARGET_MIPS16, and exists for use as an attribute. */
531int mips16;
532
533/* This variable is set by -mno-mips16. We only care whether
534 -mno-mips16 appears or not, and using a string in this fashion is
535 just a way to avoid using up another bit in target_flags. */
e2fe6aba 536const char *mips_no_mips16_string;
2bcb2ab3
GK		 537
538/* Whether we are generating mips16 hard float code. In mips16 mode
539 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
540 -msoft-float was not specified by the user, which means that we
541 should arrange to call mips32 hard floating point code. */
542int mips16_hard_float;
543
544/* This variable is set by -mentry. We only care whether -mentry
545 appears or not, and using a string in this fashion is just a way to
546 avoid using up another bit in target_flags. */
e2fe6aba 547const char *mips_entry_string;
2bcb2ab3 548
d490e8ad
DD		 549const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
550
2bcb2ab3
GK		 551/* Whether we should entry and exit pseudo-ops in mips16 mode. */
552int mips_entry;
553
910628b8
JW		 554/* If TRUE, we split addresses into their high and low parts in the RTL. */
555int mips_split_addresses;
556
ffa9d0b1 557/* Generating calls to position independent functions? */
1d6ce736 558enum mips_abicalls_type mips_abicalls;
ffa9d0b1 559
bfed8dac 560/* Mode used for saving/restoring general purpose registers. */
b3fb0b5e 561static enum machine_mode gpr_mode;
bfed8dac 562
cee98a59
MM		 563/* Array giving truth value on whether or not a given hard register
564 can support a given mode. */
565char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
566
2bcb2ab3
GK		 567/* The length of all strings seen when compiling for the mips16. This
568 is used to tell how many strings are in the constant pool, so that
569 we can see if we may have an overflow. This is reset each time the
570 constant pool is output. */
571int mips_string_length;
572
366356d3
RS		 573/* When generating mips16 code, a list of all strings that are to be
574 output after the current function. */
575
576static GTY(()) rtx mips16_strings;
577
2bcb2ab3
GK		 578/* In mips16 mode, we build a list of all the string constants we see
579 in a particular function. */
580
581struct string_constant
582{
583 struct string_constant *next;
bd9f1972 584 const char *label;
2bcb2ab3
GK		 585};
586
587static struct string_constant *string_constants;
588
cee98a59
MM		 589/* List of all MIPS punctuation characters used by print_operand. */
590char mips_print_operand_punct[256];
591
592/* Map GCC register number to debugger register number. */
593int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
594
cafe096b
EC		 595/* An alias set for the GOT. */
596static int mips_got_alias_set;
597
598static GTY (()) int mips_output_filename_first_time = 1;
599
cee98a59
MM		 600/* Hardware names for the registers. If -mrnames is used, this
601 will be overwritten with mips_sw_reg_names. */
602
603char mips_reg_names[][8] =
604{
605 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
606 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
607 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
608 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
609 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
610 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
611 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
612 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
b8eb88d0 613 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
cafe096b 614 "$fcc5","$fcc6","$fcc7","", "", "", "", "",
d604bca3
MH		 615 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
616 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
617 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
618 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
619 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
620 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
621 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
622 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
623 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
624 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
625 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
626 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
cee98a59
MM		 627};
628
629/* Mips software names for the registers, used to overwrite the
630 mips_reg_names array. */
631
d604bca3 632char mips_sw_reg_names[][8] =
cee98a59 633{
147255d8
JW		 634 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
635 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
636 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
637 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
cee98a59
MM		 638 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
639 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
640 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
641 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
b8eb88d0 642 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
d604bca3
MH		 643 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
644 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
645 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
646 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
647 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
648 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
649 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
650 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
651 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
652 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
653 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
654 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
655 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
cee98a59
MM		 656};
657
658/* Map hard register number to register class */
8b60264b 659const enum reg_class mips_regno_to_class[] =
cee98a59 660{
cafe096b 661 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
2bcb2ab3 662 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
cafe096b
EC		 663 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
664 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
665 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
666 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
667 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
668 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
cee98a59
MM		 669 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
670 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
676 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
b987661c 677 HI_REG, LO_REG, HILO_REG, ST_REGS,
b8eb88d0 678 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
cafe096b 679 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
d604bca3
MH		 680 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
681 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
682 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
688 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
689 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
690 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
696 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
697 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
698 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
704 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
cee98a59
MM		 705};
706
707/* Map register constraint character to register class. */
708enum reg_class mips_char_to_class[256] =
709{
710 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
711 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
712 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
713 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
714 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
715 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
716 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
717 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
718 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
719 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
720 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
721 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
722 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
723 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
724 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
725 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
726 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
727 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
728 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
729 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
730 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
731 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
732 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
733 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
734 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
735 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
736 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
737 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
738 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
739 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
740 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
741 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
742 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
743 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
744 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
745 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
746 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
747 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
748 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
749 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
750 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
751 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
752 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
753 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
754 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
755 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
756 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
757 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
758 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
759 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
760 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
761 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
762 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
763 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
764 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
765 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
766 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
767 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
768 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
769 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
770 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
771 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
772 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
773 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
774};
672a6f42 775\f
a27fb29b
RS		 776/* A table describing all the processors gcc knows about. Names are
777 matched in the order listed. The first mention of an ISA level is
778 taken as the canonical name for that ISA.
779
780 To ease comparison, please keep this table in the same order as
781 gas's mips_cpu_info_table[]. */
782const struct mips_cpu_info mips_cpu_info_table[] = {
783 /* Entries for generic ISAs */
784 { "mips1", PROCESSOR_R3000, 1 },
785 { "mips2", PROCESSOR_R6000, 2 },
786 { "mips3", PROCESSOR_R4000, 3 },
787 { "mips4", PROCESSOR_R8000, 4 },
2d2a50c3
CD		 788 { "mips32", PROCESSOR_4KC, 32 },
789 { "mips32r2", PROCESSOR_M4K, 33 },
790 { "mips64", PROCESSOR_5KC, 64 },
a27fb29b
RS		 791
792 /* MIPS I */
793 { "r3000", PROCESSOR_R3000, 1 },
794 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
795 { "r3900", PROCESSOR_R3900, 1 },
796
797 /* MIPS II */
798 { "r6000", PROCESSOR_R6000, 2 },
799
800 /* MIPS III */
801 { "r4000", PROCESSOR_R4000, 3 },
802 { "vr4100", PROCESSOR_R4100, 3 },
5ce6f47b 803 { "vr4111", PROCESSOR_R4111, 3 },
3f7967e3 804 { "vr4120", PROCESSOR_R4120, 3 },
a27fb29b
RS		 805 { "vr4300", PROCESSOR_R4300, 3 },
806 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
807 { "r4600", PROCESSOR_R4600, 3 },
808 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
809 { "r4650", PROCESSOR_R4650, 3 },
810
811 /* MIPS IV */
812 { "r8000", PROCESSOR_R8000, 4 },
813 { "vr5000", PROCESSOR_R5000, 4 },
5ce6f47b
EC		 814 { "vr5400", PROCESSOR_R5400, 4 },
815 { "vr5500", PROCESSOR_R5500, 4 },
816
2d2a50c3
CD		 817 /* MIPS32 */
818 { "4kc", PROCESSOR_4KC, 32 },
819 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
a27fb29b 820
2d2a50c3
CD		 821 /* MIPS32 Release 2 */
822 { "m4k", PROCESSOR_M4K, 33 },
a27fb29b 823
2d2a50c3
CD		 824 /* MIPS64 */
825 { "5kc", PROCESSOR_5KC, 64 },
826 { "20kc", PROCESSOR_20KC, 64 },
5b552f76 827 { "sb1", PROCESSOR_SB1, 64 },
2d2a50c3 828 { "sr71000", PROCESSOR_SR71000, 64 },
5b552f76 829
a27fb29b
RS		 830 /* End marker */
831 { 0, 0, 0 }
832};
833\f
60bc2b4b
RS		 834/* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
835#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
836#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
837#endif
838\f
672a6f42 839/* Initialize the GCC target structure. */
301d03af
RS		 840#undef TARGET_ASM_ALIGNED_HI_OP
841#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
842#undef TARGET_ASM_ALIGNED_SI_OP
843#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
844#undef TARGET_ASM_INTEGER
845#define TARGET_ASM_INTEGER mips_assemble_integer
846
847#if TARGET_IRIX5 && !TARGET_IRIX6
848#undef TARGET_ASM_UNALIGNED_HI_OP
849#define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
850#undef TARGET_ASM_UNALIGNED_SI_OP
851#define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
789b7de5
RO		 852#undef TARGET_ASM_UNALIGNED_DI_OP
853#define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.dword\t"
301d03af
RS		 854#endif
855
08c148a8
NB		 856#undef TARGET_ASM_FUNCTION_PROLOGUE
857#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
858#undef TARGET_ASM_FUNCTION_EPILOGUE
859#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
b64a1b53
RH		 860#undef TARGET_ASM_SELECT_RTX_SECTION
861#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
cee98a59 862
c237e94a
ZW		 863#undef TARGET_SCHED_ADJUST_COST
864#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
b875d2ee
EC		 865#undef TARGET_SCHED_ISSUE_RATE
866#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
5ce6f47b
EC		 867#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
868#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
b875d2ee 869
cafe096b
EC		 870#undef TARGET_FUNCTION_OK_FOR_SIBCALL
871#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
fb49053f 872
4977bab6
ZW		 873#undef TARGET_VALID_POINTER_MODE
874#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
3c50106f
RH		 875#undef TARGET_RTX_COSTS
876#define TARGET_RTX_COSTS mips_rtx_costs
dcefdf67
RH		 877#undef TARGET_ADDRESS_COST
878#define TARGET_ADDRESS_COST mips_address_cost
e8b84d3d
RS		 879#undef TARGET_DELEGITIMIZE_ADDRESS
880#define TARGET_DELEGITIMIZE_ADDRESS mips_delegitimize_address
4977bab6 881
cafe096b
EC		 882#undef TARGET_ENCODE_SECTION_INFO
883#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
884
f6897b10 885struct gcc_target targetm = TARGET_INITIALIZER;
cee98a59 886\f
cafe096b
EC		 887/* If X is one of the constants described by mips_constant_type,
888 store its components in INFO and return its type. */
cee98a59 889
cafe096b
EC		 890static enum mips_constant_type
891mips_classify_constant (info, x)
892 struct mips_constant_info *info;
893 rtx x;
cee98a59 894{
cafe096b
EC		 895 info->offset = 0;
896 info->symbol = x;
897 if (GET_CODE (x) == CONST)
898 {
899 x = XEXP (x, 0);
cee98a59 900
cafe096b
EC		 901 if (GET_CODE (x) == REG && REGNO (x) == GP_REG_FIRST + 28)
902 return CONSTANT_GP;
903
904 while (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
905 {
906 info->offset += INTVAL (XEXP (x, 1));
907 x = XEXP (x, 0);
908 }
909 info->symbol = x;
910 if (GET_CODE (x) == UNSPEC)
911 switch (XINT (x, 1))
912 {
913 case RELOC_GPREL16:
914 case RELOC_GOT_PAGE:
915 /* These relocations can be applied to symbols with offsets. */
916 return CONSTANT_RELOC;
917
918 case RELOC_GOT_HI:
919 case RELOC_GOT_LO:
920 case RELOC_GOT_DISP:
921 case RELOC_CALL16:
922 case RELOC_CALL_HI:
923 case RELOC_CALL_LO:
924 /* These relocations should be applied to bare symbols only. */
925 return (info->offset == 0 ? CONSTANT_RELOC : CONSTANT_NONE);
926 }
927 }
928 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
929 return CONSTANT_SYMBOLIC;
930 return CONSTANT_NONE;
cee98a59
MM		 931}
932
cee98a59 933
cafe096b
EC		 934/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
935
936static enum mips_symbol_type
937mips_classify_symbol (x)
938 rtx x;
cee98a59 939{
cafe096b
EC		 940 if (GET_CODE (x) == LABEL_REF)
941 return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
cee98a59 942
cafe096b
EC		 943 if (GET_CODE (x) != SYMBOL_REF)
944 abort ();
2bcb2ab3 945
cafe096b
EC		 946 if (CONSTANT_POOL_ADDRESS_P (x))
947 {
948 if (TARGET_MIPS16)
949 return SYMBOL_CONSTANT_POOL;
cee98a59 950
cafe096b
EC		 951 if (TARGET_ABICALLS)
952 return SYMBOL_GOT_LOCAL;
cee98a59 953
cafe096b
EC		 954 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
955 return SYMBOL_SMALL_DATA;
cee98a59 956
cafe096b
EC		 957 return SYMBOL_GENERAL;
958 }
959
960 if (XSTR (x, 0)[0] == '*'
961 && strncmp (XSTR (x, 0) + 1, LOCAL_LABEL_PREFIX,
962 sizeof LOCAL_LABEL_PREFIX - 1) == 0)
963 {
964 /* The symbol is a local label. For TARGET_MIPS16, SYMBOL_REF_FLAG
965 will be set if the symbol refers to a string in the current
966 function's constant pool. */
967 if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
968 return SYMBOL_CONSTANT_POOL;
969
970 if (TARGET_ABICALLS)
971 return SYMBOL_GOT_LOCAL;
972 }
973
974 if (TARGET_ABICALLS)
975 return (SYMBOL_REF_FLAG (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL);
976
977 return (SYMBOL_REF_FLAG (x) ? SYMBOL_SMALL_DATA : SYMBOL_GENERAL);
cee98a59
MM		 978}
979
cafe096b
EC		 980
981/* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
cee98a59
MM		 982
983int
cafe096b
EC		 984mips_reg_mode_ok_for_base_p (reg, mode, strict)
985 rtx reg;
986 enum machine_mode mode;
987 int strict;
cee98a59 988{
cafe096b
EC		 989 return (strict
990 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
991 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
cee98a59
MM		 992}
993
cee98a59 994
cafe096b
EC		 995/* Return true if X is a valid base register for the given mode.
996 Allow only hard registers if STRICT. */
cee98a59 997
cafe096b
EC		 998static bool
999mips_valid_base_register_p (x, mode, strict)
1000 rtx x;
1001 enum machine_mode mode;
1002 int strict;
1003{
1004 if (!strict && GET_CODE (x) == SUBREG)
1005 x = SUBREG_REG (x);
cee98a59 1006
cafe096b
EC		 1007 return (GET_CODE (x) == REG
1008 && mips_reg_mode_ok_for_base_p (x, mode, strict));
1009}
cee98a59 1010
cee98a59 1011
cafe096b
EC		 1012/* Return true if SYMBOL + OFFSET should be considered a legitimate
1013 address. LEA_P is true and MODE is word_mode if the address
1014 will be used in an LA or DLA macro. Otherwise MODE is the
1015 mode of the value being accessed.
cee98a59 1016
cafe096b 1017 Some guiding principles:
f5963e61 1018
cafe096b
EC		 1019 - Allow a nonzero offset when it takes no additional instructions.
1020 Ask for other offsets to be added separately.
cee98a59 1021
cafe096b
EC		 1022 - Only allow multi-instruction load or store macros when MODE is
1023 word-sized or smaller. For other modes (including BLKmode)
1024 it is better to move the address into a register first. */
cee98a59 1025
cafe096b
EC		 1026static bool
1027mips_symbolic_address_p (symbol, offset, mode, lea_p)
1028 rtx symbol;
1029 HOST_WIDE_INT offset;
cee98a59 1030 enum machine_mode mode;
cafe096b 1031 int lea_p;
cee98a59 1032{
cafe096b
EC		 1033 if (TARGET_EXPLICIT_RELOCS)
1034 return false;
cee98a59 1035
cafe096b
EC		 1036 switch (mips_classify_symbol (symbol))
1037 {
1038 case SYMBOL_GENERAL:
1039 /* General symbols aren't valid addresses in mips16 code:
1040 they have to go into the constant pool. */
1041 return (!TARGET_MIPS16
1042 && !mips_split_addresses
1043 && SINGLE_WORD_MODE_P (mode));
1044
1045 case SYMBOL_SMALL_DATA:
1046 /* Small data references are normally OK for any address.
1047 But for mips16 code, we need to use a pseudo register
1048 instead of $gp as the base register. */
1049 return !TARGET_MIPS16;
1050
1051 case SYMBOL_CONSTANT_POOL:
1052 /* PC-relative addressing is only available for lw, sw, ld and sd.
1053 There's also a PC-relative add instruction. */
1054 return lea_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1055
1056 case SYMBOL_GOT_GLOBAL:
1057 /* The address of the symbol is stored in the GOT. We can load
1058 it using an LA or DLA instruction, but any offset is added
1059 afterwards. */
1060 return lea_p && offset == 0;
1061
1062 case SYMBOL_GOT_LOCAL:
1063 /* The symbol is part of a block of local memory. We fetch the
1064 address of the local memory from the GOT and then add the
1065 offset for this symbol. This addition can take the form of an
1066 offset(base) address, so the symbol is a legitimate address. */
1067 return SINGLE_WORD_MODE_P (mode);
cee98a59 1068 }
cafe096b 1069 abort ();
cee98a59
MM		 1070}
1071
def72bd2 1072
cafe096b
EC		 1073/* If X is a valid address, describe it in INFO and return its type.
1074 STRICT says to only allow hard registers. MODE and LEA_P are
1075 the same as for mips_symbolic_address_p. */
1076
1077static enum mips_address_type
1078mips_classify_address (info, x, mode, strict, lea_p)
1079 struct mips_address_info *info;
1080 rtx x;
def72bd2 1081 enum machine_mode mode;
cafe096b 1082 int strict, lea_p;
def72bd2 1083{
cafe096b 1084 switch (GET_CODE (x))
def72bd2 1085 {
cafe096b
EC		 1086 case REG:
1087 case SUBREG:
1088 if (mips_valid_base_register_p (x, mode, strict))
1089 {
1090 info->reg = x;
1091 info->offset = const0_rtx;
1092 return ADDRESS_REG;
1093 }
1094 return ADDRESS_INVALID;
1095
1096 case PLUS:
1097 if (mips_valid_base_register_p (XEXP (x, 0), mode, strict)
1098 && const_arith_operand (XEXP (x, 1), VOIDmode))
1099 {
1100 info->reg = XEXP (x, 0);
1101 info->offset = XEXP (x, 1);
1102 return ADDRESS_REG;
1103 }
1104 return ADDRESS_INVALID;
1105
1106 case LO_SUM:
1107 if (SINGLE_WORD_MODE_P (mode)
1108 && mips_valid_base_register_p (XEXP (x, 0), mode, strict)
1109 && (mips_classify_constant (&info->c, XEXP (x, 1))
1110 == CONSTANT_SYMBOLIC)
1111 && mips_splittable_symbol_p (mips_classify_symbol (info->c.symbol)))
1112 {
1113 info->reg = XEXP (x, 0);
1114 info->offset = XEXP (x, 1);
1115 return ADDRESS_LO_SUM;
1116 }
1117 return ADDRESS_INVALID;
1118
def72bd2 1119 case CONST_INT:
cafe096b
EC		 1120 /* Small-integer addressses don't occur very often, but they
1121 are legitimate if $0 is a valid base register. */
1122 if (!TARGET_MIPS16 && SMALL_INT (x))
1123 return ADDRESS_CONST_INT;
1124 return ADDRESS_INVALID;
def72bd2 1125
cafe096b
EC		 1126 case CONST:
1127 case LABEL_REF:
1128 case SYMBOL_REF:
1129 if (mips_classify_constant (&info->c, x) == CONSTANT_SYMBOLIC
1130 && mips_symbolic_address_p (info->c.symbol, info->c.offset,
1131 mode, lea_p))
1132 return ADDRESS_SYMBOLIC;
1133 return ADDRESS_INVALID;
def72bd2 1134
def72bd2 1135 default:
cafe096b 1136 return ADDRESS_INVALID;
def72bd2 1137 }
def72bd2 1138}
cafe096b
EC		 1139\f
1140/* Return true if symbols of the given type can be split into a
1141 HIGH/LO_SUM pair. */
def72bd2 1142
cafe096b
EC		 1143static bool
1144mips_splittable_symbol_p (type)
1145 enum mips_symbol_type type;
cee98a59 1146{
cafe096b
EC		 1147 if (TARGET_EXPLICIT_RELOCS)
1148 return (type == SYMBOL_GENERAL || type == SYMBOL_GOT_LOCAL);
1149 if (mips_split_addresses)
1150 return (type == SYMBOL_GENERAL);
1151 return false;
1152}
cee98a59 1153
cee98a59 1154
cafe096b
EC		 1155/* Return the number of instructions needed to load a symbol of the
1156 given type into a register. If valid in an address, the same number
1157 of instructions are needed for loads and stores. Treat extended
1158 mips16 instructions as two instructions. */
1f7422bd 1159
cafe096b
EC		 1160static int
1161mips_symbol_insns (type)
1162 enum mips_symbol_type type;
1163{
1164 switch (type)
1165 {
1166 case SYMBOL_GENERAL:
1167 /* When using 64-bit symbols, we need 5 preparatory instructions,
1168 such as:
cee98a59 1169
cafe096b
EC		 1170 lui $at,%highest(symbol)
1171 daddiu $at,$at,%higher(symbol)
1172 dsll $at,$at,16
1173 daddiu $at,$at,%hi(symbol)
1174 dsll $at,$at,16
cee98a59 1175
cafe096b
EC		 1176 The final address is then $at + %lo(symbol). With 32-bit
1177 symbols we just need a preparatory lui. */
1178 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
cee98a59 1179
cafe096b
EC		 1180 case SYMBOL_SMALL_DATA:
1181 return 1;
b8eb88d0 1182
cafe096b
EC		 1183 case SYMBOL_CONSTANT_POOL:
1184 /* This case is for mips16 only. Assume we'll need an
1185 extended instruction. */
1186 return 2;
b8eb88d0 1187
cafe096b
EC		 1188 case SYMBOL_GOT_GLOBAL:
1189 /* When using a small GOT, we just fetch the address using
1190 a gp-relative load. For a big GOT, we need a sequence
1191 such as:
b8eb88d0 1192
cafe096b
EC		 1193 lui $at,%got_hi(symbol)
1194 daddu $at,$at,$gp
b8eb88d0 1195
cafe096b
EC		 1196 and the final address is $at + %got_lo(symbol). */
1197 return (flag_pic == 1 ? 1 : 3);
b8eb88d0 1198
cafe096b
EC		 1199 case SYMBOL_GOT_LOCAL:
1200 /* For o32 and o64, the sequence is:
2bcb2ab3 1201
cafe096b
EC		 1202 lw $at,%got(symbol)
1203 nop
2bcb2ab3 1204
cafe096b
EC		 1205 and the final address is $at + %lo(symbol). A load/add
1206 sequence is also needed for n32 and n64. Some versions
1207 of GAS insert a nop in the n32/n64 sequences too so, for
1208 simplicity, use the worst case of 3 instructions. */
1209 return 3;
2bcb2ab3 1210 }
cafe096b
EC		 1211 abort ();
1212}
2bcb2ab3 1213
2bcb2ab3 1214
cafe096b
EC		 1215/* Return true if a value at OFFSET bytes from BASE can be accessed
1216 using an unextended mips16 instruction. MODE is the mode of the
1217 value.
2bcb2ab3 1218
cafe096b
EC		 1219 Usually the offset in an unextended instruction is a 5-bit field.
1220 The offset is unsigned and shifted left once for HIs, twice
1221 for SIs, and so on. An exception is SImode accesses off the
1222 stack pointer, which have an 8-bit immediate field. */
cee98a59 1223
cafe096b
EC		 1224static bool
1225mips16_unextended_reference_p (mode, base, offset)
cee98a59 1226 enum machine_mode mode;
cafe096b 1227 rtx base, offset;
cee98a59 1228{
cafe096b
EC		 1229 if (TARGET_MIPS16
1230 && GET_CODE (offset) == CONST_INT
1231 && INTVAL (offset) >= 0
1232 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1233 {
1234 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1235 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1236 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1237 }
1238 return false;
1239}
cee98a59 1240
cee98a59 1241
cafe096b
EC		 1242/* Return the number of instructions needed to load or store a value
1243 of mode MODE at X. Return 0 if X isn't valid for MODE.
1244
1245 For mips16 code, count extended instructions as two instructions. */
cee98a59 1246
cafe096b
EC		 1247int
1248mips_address_insns (x, mode)
1249 rtx x;
1250 enum machine_mode mode;
1251{
1252 struct mips_address_info addr;
1253 int factor;
1254
1255 /* Each word of a multi-word value will be accessed individually. */
1256 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1257 switch (mips_classify_address (&addr, x, mode, 0, 0))
cee98a59 1258 {
cafe096b
EC		 1259 case ADDRESS_INVALID:
1260 return 0;
1261
1262 case ADDRESS_REG:
1263 if (TARGET_MIPS16
1264 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1265 return factor * 2;
1266 return factor;
1267
1268 case ADDRESS_LO_SUM:
1269 case ADDRESS_CONST_INT:
1270 return factor;
1271
1272 case ADDRESS_SYMBOLIC:
1273 return factor * mips_symbol_insns (mips_classify_symbol (addr.c.symbol));
1274 }
1275 abort ();
1276}
1277
1278
1279/* Likewise for constant X. */
1280
1281int
1282mips_const_insns (x)
1283 rtx x;
1284{
1285 struct mips_constant_info c;
b259a9a6 1286 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
cafe096b
EC		 1287
1288 switch (GET_CODE (x))
1289 {
1290 case CONSTANT_P_RTX:
1291 case HIGH:
f5963e61 1292 return 1;
cee98a59
MM		 1293
1294 case CONST_INT:
2bcb2ab3 1295 if (TARGET_MIPS16)
cafe096b
EC		 1296 /* Unsigned 8-bit constants can be loaded using an unextended
1297 LI instruction. Unsigned 16-bit constants can be loaded
1298 using an extended LI. Negative constants must be loaded
1299 using LI and then negated. */
1300 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1301 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1302 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1303 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1304 : 0);
1305
b259a9a6 1306 return mips_build_integer (codes, INTVAL (x));
cee98a59 1307
cafe096b
EC		 1308 case CONST_DOUBLE:
1309 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
cee98a59 1310
cafe096b
EC		 1311 default:
1312 switch (mips_classify_constant (&c, x))
1313 {
1314 case CONSTANT_NONE:
1315 return 0;
cee98a59 1316
cafe096b
EC		 1317 case CONSTANT_GP:
1318 return 1;
cee98a59 1319
cafe096b
EC		 1320 case CONSTANT_RELOC:
1321 /* When generating mips16 code, we need to set the destination to
5b0f0db6 1322 $0 and then add in the signed offset. See mips_output_move. */
cafe096b 1323 return (TARGET_MIPS16 ? 3 : 1);
cee98a59 1324
cafe096b
EC		 1325 case CONSTANT_SYMBOLIC:
1326 return mips_symbol_insns (mips_classify_symbol (c.symbol));
1327 }
1328 abort ();
1329 }
1330}
cee98a59 1331
cee98a59 1332
cafe096b
EC		 1333/* Return the number of instructions needed for memory reference X.
1334 Count extended mips16 instructions as two instructions. */
f5963e61 1335
cafe096b
EC		 1336int
1337mips_fetch_insns (x)
1338 rtx x;
1339{
1340 if (GET_CODE (x) != MEM)
1341 abort ();
cee98a59 1342
cafe096b
EC		 1343 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1344}
2bcb2ab3 1345
2bcb2ab3 1346
cafe096b
EC		 1347/* Return true if OP is a symbolic constant that refers to a
1348 global PIC symbol. */
2bcb2ab3 1349
cafe096b
EC		 1350bool
1351mips_global_pic_constant_p (op)
1352 rtx op;
1353{
1354 struct mips_constant_info c;
f5963e61 1355
cafe096b
EC		 1356 return (mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC
1357 && mips_classify_symbol (c.symbol) == SYMBOL_GOT_GLOBAL);
1358}
cee98a59 1359
cafe096b
EC		 1360
1361/* Return truth value of whether OP can be used as an operands
1362 where a register or 16 bit unsigned integer is needed. */
1363
1364int
1365uns_arith_operand (op, mode)
1366 rtx op;
1367 enum machine_mode mode;
1368{
1369 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1370 return 1;
1371
1372 return register_operand (op, mode);
1373}
1374
1375
1376/* True if OP can be treated as a signed 16-bit constant. */
1377
1378int
1379const_arith_operand (op, mode)
1380 rtx op;
1381 enum machine_mode mode ATTRIBUTE_UNUSED;
1382{
1383 struct mips_constant_info c;
1384
1385 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1386 || mips_classify_constant (&c, op) == CONSTANT_RELOC);
1387}
1388
1389
1390/* Return truth value of whether OP can be used as an operands
1391 where a 16 bit integer is needed */
1392
1393int
1394arith_operand (op, mode)
1395 rtx op;
1396 enum machine_mode mode;
1397{
1398 return const_arith_operand (op, mode) || register_operand (op, mode);
cee98a59
MM		 1399}
1400
cafe096b
EC		 1401/* Return truth value of whether OP can be used as an operand in a two
1402 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
2bcb2ab3
GK		 1403
1404int
cafe096b 1405arith32_operand (op, mode)
2bcb2ab3
GK		 1406 rtx op;
1407 enum machine_mode mode;
1408{
cafe096b
EC		 1409 if (GET_CODE (op) == CONST_INT)
1410 return 1;
2bcb2ab3 1411
cafe096b
EC		 1412 return register_operand (op, mode);
1413}
2bcb2ab3 1414
cafe096b
EC		 1415/* Return truth value of whether OP is an integer which fits in 16 bits. */
1416
1417int
1418small_int (op, mode)
1419 rtx op;
1420 enum machine_mode mode ATTRIBUTE_UNUSED;
1421{
1422 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1423}
1424
1425/* Return truth value of whether OP is a 32 bit integer which is too big to
1426 be loaded with one instruction. */
1427
1428int
1429large_int (op, mode)
1430 rtx op;
1431 enum machine_mode mode ATTRIBUTE_UNUSED;
1432{
1433 HOST_WIDE_INT value;
1434
1435 if (GET_CODE (op) != CONST_INT)
1436 return 0;
1437
1438 value = INTVAL (op);
1439
1440 /* ior reg,$r0,value */
1441 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
1442 return 0;
1443
1444 /* subu reg,$r0,value */
1445 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
1446 return 0;
1447
1448 /* lui reg,value>>16 */
1449 if ((value & 0x0000ffff) == 0)
1450 return 0;
1451
1452 return 1;
1453}
1454
1455/* Return truth value of whether OP is a register or the constant 0.
1456 In mips16 mode, we only accept a register, since the mips16 does
1457 not have $0. */
1458
1459int
1460reg_or_0_operand (op, mode)
1461 rtx op;
1462 enum machine_mode mode;
1463{
1464 switch (GET_CODE (op))
1465 {
1466 case CONST_INT:
1467 if (TARGET_MIPS16)
1468 return 0;
1469 return INTVAL (op) == 0;
1470
1471 case CONST_DOUBLE:
1472 if (TARGET_MIPS16)
1473 return 0;
1474 return op == CONST0_RTX (mode);
1475
1476 default:
1477 return register_operand (op, mode);
2bcb2ab3 1478 }
cafe096b 1479}
2bcb2ab3 1480
cafe096b
EC		 1481/* Return truth value of whether OP is a register or the constant 0,
1482 even in mips16 mode. */
1483
1484int
1485true_reg_or_0_operand (op, mode)
1486 rtx op;
1487 enum machine_mode mode;
1488{
1489 switch (GET_CODE (op))
2bcb2ab3 1490 {
cafe096b
EC		 1491 case CONST_INT:
1492 return INTVAL (op) == 0;
1493
1494 case CONST_DOUBLE:
1495 return op == CONST0_RTX (mode);
1496
1497 default:
1498 return register_operand (op, mode);
2bcb2ab3 1499 }
cafe096b 1500}
2bcb2ab3 1501
cafe096b 1502/* Accept the floating point constant 1 in the appropriate mode. */
2bcb2ab3 1503
cafe096b
EC		 1504int
1505const_float_1_operand (op, mode)
1506 rtx op;
1507 enum machine_mode mode;
1508{
1509 REAL_VALUE_TYPE d;
1510
1511 if (GET_CODE (op) != CONST_DOUBLE
1512 || mode != GET_MODE (op)
1513 || (mode != DFmode && mode != SFmode))
1514 return 0;
2bcb2ab3 1515
cafe096b
EC		 1516 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1517
1518 return REAL_VALUES_EQUAL (d, dconst1);
2bcb2ab3
GK		 1519}
1520
f5963e61 1521/* Return nonzero if the code of this rtx pattern is EQ or NE. */
cee98a59
MM		 1522
1523int
1524equality_op (op, mode)
1525 rtx op;
1526 enum machine_mode mode;
1527{
1528 if (mode != GET_MODE (op))
f5963e61 1529 return 0;
cee98a59 1530
f5963e61 1531 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
cee98a59
MM		 1532}
1533
f5963e61 1534/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
cee98a59
MM		 1535
1536int
1537cmp_op (op, mode)
1538 rtx op;
1539 enum machine_mode mode;
1540{
1541 if (mode != GET_MODE (op))
f5963e61 1542 return 0;
cee98a59 1543
f5963e61 1544 return GET_RTX_CLASS (GET_CODE (op)) == '<';
cee98a59
MM		 1545}
1546
a0b6cdee
GM		 1547/* Return nonzero if the code is a relational operation suitable for a
1548 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1549 We need this in the insn that expands `trap_if' in order to prevent
1550 combine from erroneously altering the condition. */
1551
1552int
1553trap_cmp_op (op, mode)
1554 rtx op;
1555 enum machine_mode mode;
1556{
1557 if (mode != GET_MODE (op))
1558 return 0;
1559
1560 switch (GET_CODE (op))
1561 {
1562 case EQ:
1563 case NE:
1564 case LT:
1565 case LTU:
1566 case GE:
1567 case GEU:
1568 return 1;
1569
1570 default:
1571 return 0;
1572 }
1573}
1574
f5963e61 1575/* Return nonzero if the operand is either the PC or a label_ref. */
34b650b3
MM		 1576
1577int
1578pc_or_label_operand (op, mode)
1579 rtx op;
38831dfe 1580 enum machine_mode mode ATTRIBUTE_UNUSED;
34b650b3
MM		 1581{
1582 if (op == pc_rtx)
f5963e61 1583 return 1;
34b650b3
MM		 1584
1585 if (GET_CODE (op) == LABEL_REF)
f5963e61 1586 return 1;
34b650b3 1587
f5963e61 1588 return 0;
34b650b3
MM		 1589}
1590
cafe096b 1591/* Test for a valid call address. */
50c0000c
RS		 1592
1593int
1594call_insn_operand (op, mode)
910628b8
JW		 1595 rtx op;
1596 enum machine_mode mode;
1597{
cafe096b 1598 struct mips_constant_info c;
2a0b0bf5 1599
cafe096b
EC		 1600 if (mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC)
1601 switch (mips_classify_symbol (c.symbol))
1602 {
1603 case SYMBOL_GENERAL:
1604 /* If -mlong-calls, force all calls to use register addressing. */
1605 return !TARGET_LONG_CALLS;
1606
1607 case SYMBOL_GOT_GLOBAL:
1608 /* Without explicit relocs, there is no special syntax for
1609 loading the address of a call destination into a register.
1610 Using "la $25,foo; jal $25" would prevent the lazy binding
1611 of "foo", so keep the address of global symbols with the
1612 jal macro. */
1613 return c.offset == 0 && !TARGET_EXPLICIT_RELOCS;
2a0b0bf5 1614
cafe096b
EC		 1615 default:
1616 return false;
1617 }
2a0b0bf5
ILT		 1618 return register_operand (op, mode);
1619}
1620
2a0b0bf5 1621
cafe096b
EC		 1622/* Return nonzero if OP is valid as a source operand for a move
1623 instruction. */
2a0b0bf5
ILT		 1624
1625int
cafe096b 1626move_operand (op, mode)
2a0b0bf5
ILT		 1627 rtx op;
1628 enum machine_mode mode;
1629{
cafe096b 1630 struct mips_constant_info c;
2a0b0bf5 1631
cafe096b
EC		 1632 if (GET_CODE (op) == HIGH && TARGET_ABICALLS)
1633 return false;
b259a9a6
RS		 1634 if (GET_CODE (op) == CONST_INT && !TARGET_MIPS16)
1635 return (SMALL_INT (op) || SMALL_INT_UNSIGNED (op) || LUI_INT (op));
cafe096b
EC		 1636 if (mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC)
1637 return mips_symbolic_address_p (c.symbol, c.offset, word_mode, 1);
1638 return general_operand (op, mode);
2a0b0bf5
ILT		 1639}
1640
2a0b0bf5 1641
2bcb2ab3
GK		 1642/* Accept any operand that can appear in a mips16 constant table
1643 instruction. We can't use any of the standard operand functions
1644 because for these instructions we accept values that are not
1645 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1646
1647int
1648consttable_operand (op, mode)
1649 rtx op;
38831dfe 1650 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1651{
1652 return CONSTANT_P (op);
1653}
1654
d604bca3
MH		 1655/* Coprocessor operand; return true if rtx is a REG and refers to a
1656 coprocessor. */
1657
1658int
1659coprocessor_operand (op, mode)
1660 rtx op;
1661 enum machine_mode mode ATTRIBUTE_UNUSED;
1662{
1663 return (GET_CODE (op) == REG
1664 && COP0_REG_FIRST <= REGNO (op)
1665 && REGNO (op) <= COP3_REG_LAST);
1666}
1667
1668int
1669coprocessor2_operand (op, mode)
1670 rtx op;
1671 enum machine_mode mode ATTRIBUTE_UNUSED;
1672{
1673 return (GET_CODE (op) == REG
1674 && COP2_REG_FIRST <= REGNO (op)
1675 && REGNO (op) <= COP2_REG_LAST);
1676}
1677
8f2e3902
EC		 1678/* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1679 possibly with an offset. */
1680
1681int
1682symbolic_operand (op, mode)
cafe096b
EC		 1683 rtx op;
1684 enum machine_mode mode ATTRIBUTE_UNUSED;
8f2e3902 1685{
cafe096b
EC		 1686 struct mips_constant_info c;
1687
1688 return mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC;
8f2e3902
EC		 1689}
1690
910628b8 1691
cafe096b
EC		 1692/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1693 returns a nonzero value if X is a legitimate address for a memory
1694 operand of the indicated MODE. STRICT is nonzero if this function
1695 is called during reload. */
1696
1697bool
1698mips_legitimate_address_p (mode, x, strict)
1699 enum machine_mode mode;
1700 rtx x;
1701 int strict;
1702{
1703 struct mips_address_info addr;
1704
1705 return mips_classify_address (&addr, x, mode, strict, 0) != ADDRESS_INVALID;
1706}
1707
1708
1709/* Return an rtx that represents the effect of applying relocation
1710 RELOC to symbolic address ADDR. */
1711
1712static rtx
1713mips_reloc (addr, reloc)
1714 rtx addr;
1715 int reloc;
1716{
1717 struct mips_constant_info c;
1718 rtx x;
1719
1720 if (mips_classify_constant (&c, addr) != CONSTANT_SYMBOLIC)
1721 abort ();
1722
1723 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, c.symbol), reloc);
1724 return plus_constant (gen_rtx_CONST (VOIDmode, x), c.offset);
1725}
1726
1727
1728/* Likewise, but shift the result left 16 bits. The expression can be
1729 used as the right hand side of an LUISI or LUIDI pattern. */
1730
1731static rtx
1732mips_lui_reloc (addr, reloc)
1733 rtx addr;
1734 int reloc;
1735{
1736 return gen_rtx_UNSPEC (Pmode,
1737 gen_rtvec (1, mips_reloc (addr, reloc)),
1738 UNSPEC_HIGH);
1739}
1740
1741/* Copy VALUE to a register and return that register. Use DEST as the
1742 register if non-null, otherwise create a new one.
1743
1744 VALUE must be valid on the right hand side of a simple SET pattern.
1745 The operation happens in Pmode. */
1746
1747static rtx
1748mips_force_temporary (dest, value)
1749 rtx dest, value;
1750{
1751 if (dest == 0)
1752 return force_reg (Pmode, value);
1753 else
1754 {
1755 if (!rtx_equal_p (dest, value))
1756 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (dest), value));
1757 return dest;
1758 }
1759}
1760
1761
1762/* Return a legitimate address for REG + OFFSET. This function will
1763 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1764
1765static rtx
1766mips_add_offset (reg, offset)
1767 rtx reg;
1768 HOST_WIDE_INT offset;
1769{
1770 if (!SMALL_OPERAND (offset))
1771 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1772 GEN_INT (CONST_HIGH_PART (offset)),
1773 reg, NULL, 0, OPTAB_WIDEN);
1774
1775 return plus_constant (reg, CONST_LOW_PART (offset));
1776}
1777
1778
1779/* Return the GOT entry whose address is given by %RELOC(ADDR)(BASE).
1780 BASE is a base register (such as $gp), ADDR is addresses being
1781 sought and RELOC is the relocation that should be used. */
1782
1783static rtx
1784mips_load_got (base, addr, reloc)
1785 rtx base, addr;
1786 int reloc;
1787{
1788 rtx mem;
1789
1790 mem = gen_rtx_MEM (ptr_mode,
1791 gen_rtx_PLUS (Pmode, base, mips_reloc (addr, reloc)));
1792 set_mem_alias_set (mem, mips_got_alias_set);
1793
1794 /* If we allow a function's address to be lazily bound, its entry
1795 may change after the first call. Other entries are constant. */
1796 if (reloc != RELOC_CALL16 && reloc != RELOC_CALL_LO)
1797 RTX_UNCHANGING_P (mem) = 1;
1798
1799 if (Pmode != ptr_mode)
1800 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
1801
1802 return mem;
1803}
1804
1805
1806/* Obtain the address of ADDR from the GOT using relocation RELOC.
1807 The returned address may be used on the right hand side of a SET. */
1808
1809static rtx
1810mips_load_got16 (addr, reloc)
1811 rtx addr;
1812 int reloc;
1813{
1814 return mips_load_got (pic_offset_table_rtx, addr, reloc);
1815}
1816
1817
1818/* Like mips_load_got16, but for 32-bit offsets. HIGH_RELOC is the
1819 relocation that gives the high 16 bits of the offset and LOW_RELOC is
1820 the relocation that gives the low 16 bits. TEMP is a Pmode register
1821 to use a temporary, or null if new registers can be created at will. */
1822
1823static rtx
1824mips_load_got32 (temp, addr, high_reloc, low_reloc)
1825 rtx temp, addr;
1826 int high_reloc, low_reloc;
1827{
1828 rtx x;
1829
1830 x = mips_force_temporary (temp, mips_lui_reloc (addr, high_reloc));
1831 x = mips_force_temporary (temp,
1832 gen_rtx_PLUS (Pmode, pic_offset_table_rtx, x));
1833 return mips_load_got (x, addr, low_reloc);
1834}
1835
1836
1837/* Copy the high part of ADDR into a register and return the register.
1838 Use DEST as the register if non-null. */
1839
1840static rtx
1841mips_emit_high (dest, addr)
1842 rtx dest, addr;
1843{
1844 rtx high, x;
1845
1846 high = gen_rtx_HIGH (Pmode, addr);
1847 if (TARGET_ABICALLS)
1848 {
1849 x = mips_load_got16 (copy_rtx (addr), RELOC_GOT_PAGE);
1850 x = mips_force_temporary (dest, x);
1851 set_unique_reg_note (get_last_insn (), REG_EQUAL, high);
1852 }
1853 else
1854 x = mips_force_temporary (dest, high);
1855
1856 return x;
1857}
1858
1859/* See if *XLOC is a symbolic constant that can be reduced in some way.
1860 If it is, set *XLOC to the reduced expression and return true.
1861 The new expression will be both a legitimate address and a legitimate
1862 source operand for a mips.md SET pattern. If OFFSETABLE_P, the
1863 address will be offsetable.
1864
1865 DEST is a register to use a temporary, or null if new registers
1866 can be created at will. */
1867
1868static bool
1869mips_legitimize_symbol (dest, xloc, offsetable_p)
1870 rtx dest, *xloc;
1871 int offsetable_p;
1872{
1873 struct mips_constant_info c;
1874 enum mips_symbol_type symbol_type;
1875 rtx x;
1876
1877 if (mips_classify_constant (&c, *xloc) != CONSTANT_SYMBOLIC)
1878 return false;
1879
1880 symbol_type = mips_classify_symbol (c.symbol);
1881
1882 /* Convert a mips16 reference to the small data section into
1883 an address of the form:
1884
1885 (plus BASE (const (plus (unspec [SYMBOL] UNSPEC_GPREL) OFFSET)))
1886
1887 BASE is the pseudo created by mips16_gp_pseudo_reg.
1888 The (const ...) may include an offset. */
1889 if (TARGET_MIPS16
1890 && symbol_type == SYMBOL_SMALL_DATA
1891 && !no_new_pseudos)
1892 {
1893 *xloc = gen_rtx_PLUS (Pmode, mips16_gp_pseudo_reg (),
1894 mips_reloc (*xloc, RELOC_GPREL16));
1895 return true;
1896 }
1897
1898 /* Likewise for normal-mode code. In this case we can use $gp
1899 as a base register. */
1900 if (!TARGET_MIPS16
1901 && TARGET_EXPLICIT_RELOCS
1902 && symbol_type == SYMBOL_SMALL_DATA)
1903 {
1904 *xloc = gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1905 mips_reloc (*xloc, RELOC_GPREL16));
1906 return true;
1907 }
1908
1909 /* If a non-offsetable address is OK, convert general symbols into
1910 a HIGH/LO_SUM pair. */
1911 if (!offsetable_p && mips_splittable_symbol_p (symbol_type))
1912 {
1913 x = mips_emit_high (dest, *xloc);
1914 *xloc = gen_rtx_LO_SUM (Pmode, x, copy_rtx (*xloc));
1915 return true;
1916 }
1917
1918 /* If generating PIC, and ADDR is a global symbol with an offset,
1919 load the symbol into a register and apply the offset separately.
1920 We need a temporary when adding large offsets. */
1921 if (symbol_type == SYMBOL_GOT_GLOBAL
1922 && c.offset != 0
1923 && (SMALL_OPERAND (c.offset) || dest == 0))
1924 {
1925 x = (dest == 0 ? gen_reg_rtx (Pmode) : dest);
1926 emit_move_insn (copy_rtx (x), c.symbol);
1927 *xloc = mips_add_offset (x, c.offset);
1928 return true;
1929 }
1930
1931 return false;
1932}
1933
910628b8 1934
cafe096b
EC		 1935/* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1936 be legitimized in a way that the generic machinery might not expect,
1937 put the new address in *XLOC and return true. MODE is the mode of
1938 the memory being accessed. */
910628b8 1939
cafe096b
EC		 1940bool
1941mips_legitimize_address (xloc, mode)
1942 rtx *xloc;
910628b8 1943 enum machine_mode mode;
7dac2f89 1944{
cafe096b
EC		 1945 if (mips_legitimize_symbol (0, xloc, !SINGLE_WORD_MODE_P (mode)))
1946 return true;
910628b8 1947
cafe096b
EC		 1948 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1949 {
1950 /* Handle REG + CONSTANT using mips_add_offset. */
1951 rtx reg;
910628b8 1952
cafe096b
EC		 1953 reg = XEXP (*xloc, 0);
1954 if (!mips_valid_base_register_p (reg, mode, 0))
1955 reg = copy_to_mode_reg (Pmode, reg);
1956 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1957 return true;
1958 }
1959
1960 return false;
50c0000c 1961}
c94c9817 1962
c94c9817 1963
b259a9a6
RS		 1964/* Subroutine of mips_build_integer (with the same interface).
1965 Assume that the final action in the sequence should be a left shift. */
1966
1967static unsigned int
1968mips_build_shift (codes, value)
1969 struct mips_integer_op *codes;
1970 HOST_WIDE_INT value;
1971{
1972 unsigned int i, shift;
1973
1974 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1975 since signed numbers are easier to load than unsigned ones. */
1976 shift = 0;
1977 while ((value & 1) == 0)
1978 value /= 2, shift++;
1979
1980 i = mips_build_integer (codes, value);
1981 codes[i].code = ASHIFT;
1982 codes[i].value = shift;
1983 return i + 1;
1984}
1985
1986
1987/* As for mips_build_shift, but assume that the final action will be
1988 an IOR or PLUS operation. */
1989
1990static unsigned int
1991mips_build_lower (codes, value)
1992 struct mips_integer_op *codes;
1993 unsigned HOST_WIDE_INT value;
1994{
1995 unsigned HOST_WIDE_INT high;
1996 unsigned int i;
1997
1998 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1999 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2000 {
2001 /* The constant is too complex to load with a simple lui/ori pair
2002 so our goal is to clear as many trailing zeros as possible.
2003 In this case, we know bit 16 is set and that the low 16 bits
2004 form a negative number. If we subtract that number from VALUE,
2005 we will clear at least the lowest 17 bits, maybe more. */
2006 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2007 codes[i].code = PLUS;
2008 codes[i].value = CONST_LOW_PART (value);
2009 }
2010 else
2011 {
2012 i = mips_build_integer (codes, high);
2013 codes[i].code = IOR;
2014 codes[i].value = value & 0xffff;
2015 }
2016 return i + 1;
2017}
2018
2019
2020/* Fill CODES with a sequence of rtl operations to load VALUE.
2021 Return the number of operations needed. */
2022
2023static unsigned int
2024mips_build_integer (codes, value)
2025 struct mips_integer_op *codes;
2026 unsigned HOST_WIDE_INT value;
2027{
2028 if (SMALL_OPERAND (value)
2029 || SMALL_OPERAND_UNSIGNED (value)
2030 || LUI_OPERAND (value))
2031 {
2032 /* The value can be loaded with a single instruction. */
2033 codes[0].code = NIL;
2034 codes[0].value = value;
2035 return 1;
2036 }
2037 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2038 {
2039 /* Either the constant is a simple LUI/ORI combination or its
2040 lowest bit is set. We don't want to shift in this case. */
2041 return mips_build_lower (codes, value);
2042 }
2043 else if ((value & 0xffff) == 0)
2044 {
2045 /* The constant will need at least three actions. The lowest
2046 16 bits are clear, so the final action will be a shift. */
2047 return mips_build_shift (codes, value);
2048 }
2049 else
2050 {
2051 /* The final action could be a shift, add or inclusive OR.
2052 Rather than use a complex condition to select the best
2053 approach, try both mips_build_shift and mips_build_lower
2054 and pick the one that gives the shortest sequence.
2055 Note that this case is only used once per constant. */
2056 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2057 unsigned int cost, alt_cost;
2058
2059 cost = mips_build_shift (codes, value);
2060 alt_cost = mips_build_lower (alt_codes, value);
2061 if (alt_cost < cost)
2062 {
2063 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2064 cost = alt_cost;
2065 }
2066 return cost;
2067 }
2068}
2069
2070
2071/* Move VALUE into register DEST. */
2072
2073static void
2074mips_move_integer (dest, value)
2075 rtx dest;
2076 unsigned HOST_WIDE_INT value;
2077{
2078 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2079 enum machine_mode mode;
2080 unsigned int i, cost;
2081 rtx x;
2082
2083 mode = GET_MODE (dest);
2084 cost = mips_build_integer (codes, value);
2085
2086 /* Apply each binary operation to X. Invariant: X is a legitimate
2087 source operand for a SET pattern. */
2088 x = GEN_INT (codes[0].value);
2089 for (i = 1; i < cost; i++)
2090 {
2091 if (no_new_pseudos)
2092 emit_move_insn (dest, x), x = dest;
2093 else
2094 x = force_reg (mode, x);
2095 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2096 }
2097
2098 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2099}
2100
2101
cafe096b
EC		 2102/* Subroutine of mips_legitimize_move. Move constant SRC into register
2103 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2104 move_operand. */
2105
2106static void
2107mips_legitimize_const_move (mode, dest, src)
c94c9817 2108 enum machine_mode mode;
cafe096b 2109 rtx dest, src;
c94c9817 2110{
cafe096b
EC		 2111 rtx temp;
2112
2113 temp = no_new_pseudos ? dest : 0;
2114
2115 /* If generating PIC, the high part of an address is loaded from the GOT. */
2116 if (GET_CODE (src) == HIGH)
2117 {
2118 mips_emit_high (dest, XEXP (src, 0));
2119 return;
2120 }
2121
b259a9a6
RS		 2122 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
2123 {
2124 mips_move_integer (dest, INTVAL (src));
2125 return;
2126 }
2127
cafe096b
EC		 2128 /* Fetch global symbols from the GOT. */
2129 if (TARGET_EXPLICIT_RELOCS
2130 && GET_CODE (src) == SYMBOL_REF
2131 && mips_classify_symbol (src) == SYMBOL_GOT_GLOBAL)
2132 {
2133 if (flag_pic == 1)
2134 src = mips_load_got16 (src, RELOC_GOT_DISP);
2135 else
2136 src = mips_load_got32 (temp, src, RELOC_GOT_HI, RELOC_GOT_LO);
2137 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2138 return;
2139 }
2140
2141 /* Try handling the source operand as a symbolic address. */
2142 if (mips_legitimize_symbol (temp, &src, false))
2143 {
2144 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2145 return;
2146 }
2147
2148 src = force_const_mem (mode, src);
2149
2150 /* When using explicit relocs, constant pool references are sometimes
2151 not legitimate addresses. mips_legitimize_symbol must be able to
2152 deal with all such cases. */
2153 if (GET_CODE (src) == MEM && !memory_operand (src, VOIDmode))
2154 {
2155 src = copy_rtx (src);
2156 if (!mips_legitimize_symbol (temp, &XEXP (src, 0), false))
2157 abort ();
2158 }
2159 emit_move_insn (dest, src);
c94c9817
MM		 2160}
2161
c94c9817 2162
cafe096b
EC		 2163/* If (set DEST SRC) is not a valid instruction, emit an equivalent
2164 sequence that is valid. */
2165
2166bool
2167mips_legitimize_move (mode, dest, src)
c94c9817 2168 enum machine_mode mode;
cafe096b 2169 rtx dest, src;
c94c9817 2170{
cafe096b 2171 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
7dac2f89 2172 {
cafe096b
EC		 2173 emit_move_insn (dest, force_reg (mode, src));
2174 return true;
7dac2f89
EC		 2175 }
2176
b259a9a6
RS		 2177 /* The source of an SImode move must be a move_operand. Likewise
2178 DImode moves on 64-bit targets. We need to deal with constants
2179 that would be legitimate immediate_operands but not legitimate
2180 move_operands. */
2181 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2182 && CONSTANT_P (src)
2183 && !move_operand (src, mode))
cafe096b
EC		 2184 {
2185 mips_legitimize_const_move (mode, dest, src);
2186 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2187 return true;
2188 }
2189 return false;
2190}
7dac2f89 2191
7dac2f89 2192
e8b84d3d
RS		 2193/* Convert GOT and GP-relative accesses back into their original form.
2194 Used by bothh TARGET_DELEGITIMIZE_ADDRESS and FIND_BASE_TERM. */
cafe096b
EC		 2195
2196rtx
e8b84d3d 2197mips_delegitimize_address (x)
cafe096b
EC		 2198 rtx x;
2199{
2200 struct mips_constant_info c;
c94c9817 2201
cafe096b
EC		 2202 if (GET_CODE (x) == MEM
2203 && GET_CODE (XEXP (x, 0)) == PLUS
2204 && mips_classify_constant (&c, XEXP (XEXP (x, 0), 1)) == CONSTANT_RELOC
2205 && mips_classify_symbol (XVECEXP (c.symbol, 0, 0)) == SYMBOL_GOT_GLOBAL)
2206 return XVECEXP (c.symbol, 0, 0);
e8b84d3d
RS		 2207
2208 if (GET_CODE (x) == PLUS
2209 && (XEXP (x, 0) == pic_offset_table_rtx
2210 || XEXP (x, 0) == cfun->machine->mips16_gp_pseudo_rtx)
2211 && mips_classify_constant (&c, XEXP (x, 1)) == CONSTANT_RELOC
2212 && mips_classify_symbol (XVECEXP (c.symbol, 0, 0)) == SYMBOL_SMALL_DATA)
2213 return plus_constant (XVECEXP (c.symbol, 0, 0), c.offset);
2214
cafe096b
EC		 2215 return x;
2216}
cee98a59 2217\f
2bcb2ab3
GK		 2218/* We need a lot of little routines to check constant values on the
2219 mips16. These are used to figure out how long the instruction will
2220 be. It would be much better to do this using constraints, but
2221 there aren't nearly enough letters available. */
2222
2223static int
2224m16_check_op (op, low, high, mask)
2225 rtx op;
2226 int low;
2227 int high;
2228 int mask;
2229{
2230 return (GET_CODE (op) == CONST_INT
2231 && INTVAL (op) >= low
2232 && INTVAL (op) <= high
2233 && (INTVAL (op) & mask) == 0);
2234}
2235
2236int
2237m16_uimm3_b (op, mode)
2238 rtx op;
38831dfe 2239 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2240{
2241 return m16_check_op (op, 0x1, 0x8, 0);
2242}
2243
2244int
2245m16_simm4_1 (op, mode)
2246 rtx op;
38831dfe 2247 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2248{
2249 return m16_check_op (op, - 0x8, 0x7, 0);
2250}
2251
2252int
2253m16_nsimm4_1 (op, mode)
2254 rtx op;
38831dfe 2255 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2256{
2257 return m16_check_op (op, - 0x7, 0x8, 0);
2258}
2259
2260int
2261m16_simm5_1 (op, mode)
2262 rtx op;
38831dfe 2263 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2264{
2265 return m16_check_op (op, - 0x10, 0xf, 0);
2266}
2267
2268int
2269m16_nsimm5_1 (op, mode)
2270 rtx op;
38831dfe 2271 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2272{
2273 return m16_check_op (op, - 0xf, 0x10, 0);
2274}
2275
2276int
2277m16_uimm5_4 (op, mode)
2278 rtx op;
38831dfe 2279 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2280{
2281 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2282}
2283
2284int
2285m16_nuimm5_4 (op, mode)
2286 rtx op;
38831dfe 2287 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2288{
2289 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2290}
2291
2292int
2293m16_simm8_1 (op, mode)
2294 rtx op;
38831dfe 2295 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2296{
2297 return m16_check_op (op, - 0x80, 0x7f, 0);
2298}
2299
2300int
2301m16_nsimm8_1 (op, mode)
2302 rtx op;
38831dfe 2303 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2304{
2305 return m16_check_op (op, - 0x7f, 0x80, 0);
2306}
2307
2308int
2309m16_uimm8_1 (op, mode)
2310 rtx op;
38831dfe 2311 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2312{
2313 return m16_check_op (op, 0x0, 0xff, 0);
2314}
2315
2316int
2317m16_nuimm8_1 (op, mode)
2318 rtx op;
38831dfe 2319 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2320{
2321 return m16_check_op (op, - 0xff, 0x0, 0);
2322}
2323
2324int
2325m16_uimm8_m1_1 (op, mode)
2326 rtx op;
38831dfe 2327 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2328{
2329 return m16_check_op (op, - 0x1, 0xfe, 0);
2330}
2331
2332int
2333m16_uimm8_4 (op, mode)
2334 rtx op;
38831dfe 2335 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2336{
2337 return m16_check_op (op, 0x0, 0xff << 2, 3);
2338}
2339
2340int
2341m16_nuimm8_4 (op, mode)
2342 rtx op;
38831dfe 2343 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2344{
2345 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2346}
2347
2348int
2349m16_simm8_8 (op, mode)
2350 rtx op;
38831dfe 2351 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2352{
2353 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2354}
2355
2356int
2357m16_nsimm8_8 (op, mode)
2358 rtx op;
38831dfe 2359 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2360{
2361 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2362}
2363
2364/* References to the string table on the mips16 only use a small
cafe096b 2365 offset if the function is small. We can't check for LABEL_REF here,
2bcb2ab3
GK		 2366 because the offset is always large if the label is before the
2367 referencing instruction. */
2368
2369int
2370m16_usym8_4 (op, mode)
2371 rtx op;
38831dfe 2372 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2373{
2374 if (GET_CODE (op) == SYMBOL_REF
2375 && SYMBOL_REF_FLAG (op)
b2471838 2376 && cfun->machine->insns_len > 0
2bcb2ab3
GK		 2377 && XSTR (op, 0)[0] == '*'
2378 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
2379 sizeof LOCAL_LABEL_PREFIX - 1) == 0
b2471838 2380 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2bcb2ab3
GK		 2381 < 4 * 0x100))
2382 {
2383 struct string_constant *l;
2384
2385 /* Make sure this symbol is on thelist of string constants to be
2386 output for this function. It is possible that it has already
2387 been output, in which case this requires a large offset. */
2388 for (l = string_constants; l != NULL; l = l->next)
2389 if (strcmp (l->label, XSTR (op, 0)) == 0)
2390 return 1;
2391 }
2392
2393 return 0;
2394}
2395
2396int
2397m16_usym5_4 (op, mode)
2398 rtx op;
38831dfe 2399 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 2400{
2401 if (GET_CODE (op) == SYMBOL_REF
2402 && SYMBOL_REF_FLAG (op)
b2471838 2403 && cfun->machine->insns_len > 0
2bcb2ab3
GK		 2404 && XSTR (op, 0)[0] == '*'
2405 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
2406 sizeof LOCAL_LABEL_PREFIX - 1) == 0
b2471838 2407 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2bcb2ab3
GK		 2408 < 4 * 0x20))
2409 {
2410 struct string_constant *l;
2411
2412 /* Make sure this symbol is on thelist of string constants to be
2413 output for this function. It is possible that it has already
2414 been output, in which case this requires a large offset. */
2415 for (l = string_constants; l != NULL; l = l->next)
2416 if (strcmp (l->label, XSTR (op, 0)) == 0)
2417 return 1;
2418 }
2419
2420 return 0;
2421}
2422\f
85098019
JW		 2423/* Returns an operand string for the given instruction's delay slot,
2424 after updating filled delay slot statistics.
cee98a59
MM		 2425
2426 We assume that operands[0] is the target register that is set.
2427
2428 In order to check the next insn, most of this functionality is moved
2429 to FINAL_PRESCAN_INSN, and we just set the global variables that
2430 it needs. */
2431
85098019
JW		 2432/* ??? This function no longer does anything useful, because final_prescan_insn
2433 now will never emit a nop. */
2434
bd9f1972 2435const char *
cee98a59 2436mips_fill_delay_slot (ret, type, operands, cur_insn)
bd9f1972 2437 const char *ret; /* normal string to return */
cee98a59
MM		 2438 enum delay_type type; /* type of delay */
2439 rtx operands[]; /* operands to use */
2440 rtx cur_insn; /* current insn */
2441{
2442 register rtx set_reg;
2443 register enum machine_mode mode;
f5963e61 2444 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
cee98a59
MM		 2445 register int num_nops;
2446
34b650b3 2447 if (type == DELAY_LOAD || type == DELAY_FCMP)
cee98a59
MM		 2448 num_nops = 1;
2449
2450 else if (type == DELAY_HILO)
2451 num_nops = 2;
2452
2453 else
2454 num_nops = 0;
2455
2456 /* Make sure that we don't put nop's after labels. */
2457 next_insn = NEXT_INSN (cur_insn);
f5963e61 2458 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
cee98a59
MM		 2459 next_insn = NEXT_INSN (next_insn);
2460
2461 dslots_load_total += num_nops;
2462 if (TARGET_DEBUG_F_MODE
2463 || !optimize
2464 || type == DELAY_NONE
f5963e61
JL		 2465 || operands == 0
2466 || cur_insn == 0
2467 || next_insn == 0
cee98a59 2468 || GET_CODE (next_insn) == CODE_LABEL
f5963e61 2469 || (set_reg = operands[0]) == 0)
cee98a59
MM		 2470 {
2471 dslots_number_nops = 0;
f5963e61
JL		 2472 mips_load_reg = 0;
2473 mips_load_reg2 = 0;
2474 mips_load_reg3 = 0;
2475 mips_load_reg4 = 0;
cee98a59
MM		 2476 return ret;
2477 }
2478
2479 set_reg = operands[0];
f5963e61 2480 if (set_reg == 0)
cee98a59
MM		 2481 return ret;
2482
2483 while (GET_CODE (set_reg) == SUBREG)
2484 set_reg = SUBREG_REG (set_reg);
2485
2486 mode = GET_MODE (set_reg);
2487 dslots_number_nops = num_nops;
147255d8
JW		 2488 mips_load_reg = set_reg;
2489 if (GET_MODE_SIZE (mode)
0da9afa6 2490 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
c5c76735 2491 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
147255d8
JW		 2492 else
2493 mips_load_reg2 = 0;
cee98a59
MM		 2494
2495 if (type == DELAY_HILO)
2496 {
c5c76735
JL		 2497 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
2498 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
cee98a59
MM		 2499 }
2500 else
2501 {
2502 mips_load_reg3 = 0;
2503 mips_load_reg4 = 0;
2504 }
2505
cee98a59
MM		 2506 return ret;
2507}
2508
2509\f
cafe096b
EC		 2510static bool
2511mips_rtx_costs (x, code, outer_code, total)
2512 rtx x;
2513 int code, outer_code;
2514 int *total;
2515{
2516 enum machine_mode mode = GET_MODE (x);
2517
2518 switch (code)
2519 {
2520 case CONST_INT:
2521 if (!TARGET_MIPS16)
2522 {
2523 /* Always return 0, since we don't have different sized
2524 instructions, hence different costs according to Richard
2525 Kenner */
2526 *total = 0;
2527 return true;
2528 }
2529
2530 /* A number between 1 and 8 inclusive is efficient for a shift.
2531 Otherwise, we will need an extended instruction. */
2532 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2533 || (outer_code) == LSHIFTRT)
2534 {
2535 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2536 *total = 0;
2537 else
2538 *total = COSTS_N_INSNS (1);
2539 return true;
2540 }
2541 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2542
2543 if ((outer_code) == XOR
2544 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2545 {
2546 *total = 0;
2547 return true;
2548 }
2549
2550 /* We may be able to use slt or sltu for a comparison with a
2551 signed 16 bit value. (The boundary conditions aren't quite
2552 right, but this is just a heuristic anyhow.) */
2553 if (((outer_code) == LT || (outer_code) == LE
2554 || (outer_code) == GE || (outer_code) == GT
2555 || (outer_code) == LTU || (outer_code) == LEU
2556 || (outer_code) == GEU || (outer_code) == GTU)
2557 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2558 {
2559 *total = 0;
2560 return true;
2561 }
2562
2563 /* Equality comparisons with 0 are cheap. */
2564 if (((outer_code) == EQ || (outer_code) == NE)
2565 && INTVAL (x) == 0)
2566 {
2567 *total = 0;
2568 return true;
2569 }
2570
2571 /* Otherwise fall through to the handling below. */
2572
2573 case CONST:
2574 case SYMBOL_REF:
2575 case LABEL_REF:
2576 case CONST_DOUBLE:
2577 if (((outer_code) == PLUS || (outer_code) == MINUS)
2578 && const_arith_operand (x, VOIDmode))
2579 {
2580 *total = 0;
2581 return true;
2582 }
2583 else
2584 {
2585 int n = mips_const_insns (x);
2586 return (n == 0 ? CONSTANT_POOL_COST : COSTS_N_INSNS (n));
2587 }
2588
2589 case MEM:
2590 {
2591 /* If the address is legitimate, return the number of
2592 instructions it needs, otherwise use the default handling. */
2593 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2594 if (n > 0)
2595 {
2596 *total = COSTS_N_INSNS (1 + n);
2597 return true;
2598 }
2599 return false;
2600 }
2601
2602 case FFS:
2603 *total = COSTS_N_INSNS (6);
2604 return true;
2605
2606 case NOT:
2607 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2608 return true;
2609
2610 case AND:
2611 case IOR:
2612 case XOR:
2613 if (mode == DImode && !TARGET_64BIT)
2614 {
2615 *total = COSTS_N_INSNS (2);
2616 return true;
2617 }
2618 return false;
2619
2620 case ASHIFT:
2621 case ASHIFTRT:
2622 case LSHIFTRT:
2623 if (mode == DImode && !TARGET_64BIT)
2624 {
2625 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2626 ? 4 : 12);
2627 return true;
2628 }
2629 return false;
2630
2631 case ABS:
2632 if (mode == SFmode || mode == DFmode)
2633 *total = COSTS_N_INSNS (1);
2634 else
2635 *total = COSTS_N_INSNS (4);
2636 return true;
2637
2638 case LO_SUM:
2639 *total = COSTS_N_INSNS (1);
2640 return true;
2641
2642 case PLUS:
2643 case MINUS:
2644 if (mode == SFmode || mode == DFmode)
2645 {
2646 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2647 *total = COSTS_N_INSNS (2);
2648 else if (TUNE_MIPS6000)
2649 *total = COSTS_N_INSNS (3);
2650 else
2651 *total = COSTS_N_INSNS (6);
2652 return true;
2653 }
2654 if (mode == DImode && !TARGET_64BIT)
2655 {
2656 *total = COSTS_N_INSNS (4);
2657 return true;
2658 }
2659 return false;
2660
2661 case NEG:
2662 if (mode == DImode && !TARGET_64BIT)
2663 {
2664 *total = 4;
2665 return true;
2666 }
2667 return false;
2668
2669 case MULT:
2670 if (mode == SFmode)
2671 {
2672 if (TUNE_MIPS3000
2673 || TUNE_MIPS3900
2674 || TUNE_MIPS5000)
2675 *total = COSTS_N_INSNS (4);
2676 else if (TUNE_MIPS6000
2677 || TUNE_MIPS5400
2678 || TUNE_MIPS5500)
2679 *total = COSTS_N_INSNS (5);
2680 else
2681 *total = COSTS_N_INSNS (7);
2682 return true;
2683 }
2684
2685 if (mode == DFmode)
2686 {
2687 if (TUNE_MIPS3000
2688 || TUNE_MIPS3900
2689 || TUNE_MIPS5000)
2690 *total = COSTS_N_INSNS (5);
2691 else if (TUNE_MIPS6000
2692 || TUNE_MIPS5400
2693 || TUNE_MIPS5500)
2694 *total = COSTS_N_INSNS (6);
2695 else
2696 *total = COSTS_N_INSNS (8);
2697 return true;
2698 }
2699
2700 if (TUNE_MIPS3000)
2701 *total = COSTS_N_INSNS (12);
2702 else if (TUNE_MIPS3900)
2703 *total = COSTS_N_INSNS (2);
2704 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2705 *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2706 else if (TUNE_MIPS6000)
2707 *total = COSTS_N_INSNS (17);
2708 else if (TUNE_MIPS5000)
2709 *total = COSTS_N_INSNS (5);
2710 else
2711 *total = COSTS_N_INSNS (10);
2712 return true;
2713
2714 case DIV:
2715 case MOD:
2716 if (mode == SFmode)
2717 {
2718 if (TUNE_MIPS3000
2719 || TUNE_MIPS3900)
2720 *total = COSTS_N_INSNS (12);
2721 else if (TUNE_MIPS6000)
2722 *total = COSTS_N_INSNS (15);
2723 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2724 *total = COSTS_N_INSNS (30);
2725 else
2726 *total = COSTS_N_INSNS (23);
2727 return true;
2728 }
2729
2730 if (mode == DFmode)
2731 {
2732 if (TUNE_MIPS3000
2733 || TUNE_MIPS3900)
2734 *total = COSTS_N_INSNS (19);
2735 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2736 *total = COSTS_N_INSNS (59);
2737 else if (TUNE_MIPS6000)
2738 *total = COSTS_N_INSNS (16);
2739 else
2740 *total = COSTS_N_INSNS (36);
2741 return true;
2742 }
2743 /* FALLTHRU */
2744
2745 case UDIV:
2746 case UMOD:
2747 if (TUNE_MIPS3000
2748 || TUNE_MIPS3900)
2749 *total = COSTS_N_INSNS (35);
2750 else if (TUNE_MIPS6000)
2751 *total = COSTS_N_INSNS (38);
2752 else if (TUNE_MIPS5000)
2753 *total = COSTS_N_INSNS (36);
2754 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2755 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2756 else
2757 *total = COSTS_N_INSNS (69);
2758 return true;
2759
2760 case SIGN_EXTEND:
2761 /* A sign extend from SImode to DImode in 64 bit mode is often
2762 zero instructions, because the result can often be used
2763 directly by another instruction; we'll call it one. */
2764 if (TARGET_64BIT && mode == DImode
2765 && GET_MODE (XEXP (x, 0)) == SImode)
2766 *total = COSTS_N_INSNS (1);
2767 else
2768 *total = COSTS_N_INSNS (2);
2769 return true;
2770
2771 case ZERO_EXTEND:
2772 if (TARGET_64BIT && mode == DImode
2773 && GET_MODE (XEXP (x, 0)) == SImode)
2774 *total = COSTS_N_INSNS (2);
2775 else
2776 *total = COSTS_N_INSNS (1);
2777 return true;
2778
2779 default:
2780 return false;
2781 }
2782}
2783
2784/* Provide the costs of an addressing mode that contains ADDR.
2785 If ADDR is not a valid address, its cost is irrelevant. */
2786
2787static int
2788mips_address_cost (addr)
2789 rtx addr;
2790{
2791 return mips_address_insns (addr, SImode);
2792}
2793
f5963e61
JL		 2794/* Determine whether a memory reference takes one (based off of the GP
2795 pointer), two (normal), or three (label + reg) instructions, and bump the
2796 appropriate counter for -mstats. */
cee98a59
MM		 2797
2798void
2799mips_count_memory_refs (op, num)
2800 rtx op;
2801 int num;
2802{
2803 int additional = 0;
2804 int n_words = 0;
2805 rtx addr, plus0, plus1;
2806 enum rtx_code code0, code1;
2807 int looping;
2808
2809 if (TARGET_DEBUG_B_MODE)
2810 {
2811 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
2812 debug_rtx (op);
2813 }
2814
2815 /* Skip MEM if passed, otherwise handle movsi of address. */
2816 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
2817
f5963e61 2818 /* Loop, going through the address RTL. */
cee98a59
MM		 2819 do
2820 {
2821 looping = FALSE;
2822 switch (GET_CODE (addr))
2823 {
2824 case REG:
2825 case CONST_INT:
910628b8 2826 case LO_SUM:
cee98a59
MM		 2827 break;
2828
2829 case PLUS:
2830 plus0 = XEXP (addr, 0);
2831 plus1 = XEXP (addr, 1);
2832 code0 = GET_CODE (plus0);
2833 code1 = GET_CODE (plus1);
2834
2835 if (code0 == REG)
2836 {
2837 additional++;
2838 addr = plus1;
f5963e61 2839 looping = 1;
cee98a59
MM		 2840 continue;
2841 }
2842
2843 if (code0 == CONST_INT)
2844 {
2845 addr = plus1;
f5963e61 2846 looping = 1;
cee98a59
MM		 2847 continue;
2848 }
2849
2850 if (code1 == REG)
2851 {
2852 additional++;
2853 addr = plus0;
f5963e61 2854 looping = 1;
cee98a59
MM		 2855 continue;
2856 }
2857
2858 if (code1 == CONST_INT)
2859 {
2860 addr = plus0;
f5963e61 2861 looping = 1;
cee98a59
MM		 2862 continue;
2863 }
2864
2865 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
2866 {
2867 addr = plus0;
f5963e61 2868 looping = 1;
cee98a59
MM		 2869 continue;
2870 }
2871
2872 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
2873 {
2874 addr = plus1;
f5963e61 2875 looping = 1;
cee98a59
MM		 2876 continue;
2877 }
2878
2879 break;
2880
2881 case LABEL_REF:
2882 n_words = 2; /* always 2 words */
2883 break;
2884
2885 case CONST:
2886 addr = XEXP (addr, 0);
f5963e61 2887 looping = 1;
cee98a59
MM		 2888 continue;
2889
2890 case SYMBOL_REF:
2891 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
2892 break;
f5963e61
JL		 2893
2894 default:
2895 break;
cee98a59
MM		 2896 }
2897 }
2898 while (looping);
2899
2900 if (n_words == 0)
2901 return;
2902
2903 n_words += additional;
2904 if (n_words > 3)
2905 n_words = 3;
2906
2907 num_refs[n_words-1] += num;
2908}
2909
2910\f
c8d1b2b7
AO		 2911/* Return a pseudo that points to the address of the current function.
2912 The first time it is called for a function, an initializer for the
2913 pseudo is emitted in the beginning of the function. */
92544bdf
ILT		 2914
2915rtx
c8d1b2b7 2916embedded_pic_fnaddr_reg ()
92544bdf 2917{
c8d1b2b7 2918 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
40f8d046
JW		 2919 {
2920 rtx seq;
2921
c8d1b2b7 2922 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
7dac2f89 2923
abc95ed3 2924 /* Output code at function start to initialize the pseudo-reg. */
40f8d046
JW		 2925 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2926 inline functions, because it is called after RTL for the function
2927 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2928 does not get copied, and ends up not matching the rest of the RTL.
2929 This solution works, but means that we get unnecessary code to
abc95ed3 2930 initialize this value every time a function is inlined into another
40f8d046
JW		 2931 function. */
2932 start_sequence ();
c8d1b2b7 2933 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
40f8d046 2934 XEXP (DECL_RTL (current_function_decl), 0)));
882c7223 2935 seq = get_insns ();
40f8d046
JW		 2936 end_sequence ();
2937 push_topmost_sequence ();
2938 emit_insn_after (seq, get_insns ());
2939 pop_topmost_sequence ();
2940 }
2941
c8d1b2b7 2942 return cfun->machine->embedded_pic_fnaddr_rtx;
b875d2ee 2943}
c8d1b2b7
AO		 2944
2945/* Return RTL for the offset from the current function to the argument.
2946 X is the symbol whose offset from the current function we want. */
2947
2948rtx
2949embedded_pic_offset (x)
2950 rtx x;
2951{
2952 /* Make sure it is emitted. */
2953 embedded_pic_fnaddr_reg ();
2954
c5c76735
JL		 2955 return
2956 gen_rtx_CONST (Pmode,
2957 gen_rtx_MINUS (Pmode, x,
2958 XEXP (DECL_RTL (current_function_decl), 0)));
92544bdf 2959}
5b0f0db6
RS		 2960\f
2961/* Return one word of double-word value OP, taking into account the fixed
2962 endianness of certain registers. HIGH_P is true to select the high part,
2963 false to select the low part. */
92544bdf 2964
5b0f0db6
RS		 2965rtx
2966mips_subword (op, high_p)
2967 rtx op;
2968 int high_p;
2969{
2970 unsigned int byte;
2971 enum machine_mode mode;
cee98a59 2972
5b0f0db6
RS		 2973 mode = GET_MODE (op);
2974 if (mode == VOIDmode)
2975 mode = DImode;
cee98a59 2976
5b0f0db6
RS		 2977 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2978 byte = UNITS_PER_WORD;
2979 else
2980 byte = 0;
cee98a59 2981
5b0f0db6 2982 if (GET_CODE (op) == REG)
cee98a59 2983 {
5b0f0db6
RS		 2984 if (FP_REG_P (REGNO (op)))
2985 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2986 if (REGNO (op) == HI_REGNUM)
2987 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
cee98a59
MM		 2988 }
2989
5b0f0db6
RS		 2990 if (GET_CODE (op) == MEM)
2991 return adjust_address (op, word_mode, byte);
b8eb88d0 2992
5b0f0db6
RS		 2993 return simplify_gen_subreg (word_mode, op, mode, byte);
2994}
cee98a59 2995
cee98a59 2996
5b0f0db6 2997/* Return true if a 64-bit move from SRC to DEST should be split into two. */
cee98a59 2998
5b0f0db6
RS		 2999bool
3000mips_split_64bit_move_p (dest, src)
3001 rtx dest, src;
3002{
3003 if (TARGET_64BIT)
3004 return false;
cee98a59 3005
5b0f0db6
RS		 3006 /* FP->FP moves can be done in a single instruction. */
3007 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3008 return false;
cee98a59 3009
5b0f0db6
RS		 3010 /* Check for floating-point loads and stores. They can be done using
3011 ldc1 and sdc1 on MIPS II and above. */
3012 if (mips_isa > 1)
3013 {
3014 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
3015 return false;
3016 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
3017 return false;
3018 }
3019 return true;
3020}
b8eb88d0 3021
cee98a59 3022
5b0f0db6
RS		 3023/* Split a 64-bit move from SRC to DEST assuming that
3024 mips_split_64bit_move_p holds.
cee98a59 3025
5b0f0db6
RS		 3026 Moves into and out of FPRs cause some difficulty here. Such moves
3027 will always be DFmode, since paired FPRs are not allowed to store
3028 DImode values. The most natural representation would be two separate
3029 32-bit moves, such as:
cee98a59 3030
5b0f0db6
RS		 3031 (set (reg:SI $f0) (mem:SI ...))
3032 (set (reg:SI $f1) (mem:SI ...))
cee98a59 3033
5b0f0db6
RS		 3034 However, the second insn is invalid because odd-numbered FPRs are
3035 not allowed to store independent values. Use the patterns load_df_low,
3036 load_df_high and store_df_high instead. */
cee98a59 3037
5b0f0db6
RS		 3038void
3039mips_split_64bit_move (dest, src)
3040 rtx dest, src;
3041{
3042 if (FP_REG_RTX_P (dest))
3043 {
3044 /* Loading an FPR from memory or from GPRs. */
3045 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
3046 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
3047 copy_rtx (dest)));
3048 }
3049 else if (FP_REG_RTX_P (src))
3050 {
3051 /* Storing an FPR into memory or GPRs. */
3052 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3053 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
3054 }
3055 else
3056 {
3057 /* The operation can be split into two normal moves. Decide in
3058 which order to do them. */
3059 rtx low_dest;
cee98a59 3060
5b0f0db6
RS		 3061 low_dest = mips_subword (dest, 0);
3062 if (GET_CODE (low_dest) == REG
3063 && reg_overlap_mentioned_p (low_dest, src))
cee98a59 3064 {
5b0f0db6
RS		 3065 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3066 emit_move_insn (low_dest, mips_subword (src, 0));
cee98a59 3067 }
5b0f0db6 3068 else
cee98a59 3069 {
5b0f0db6
RS		 3070 emit_move_insn (low_dest, mips_subword (src, 0));
3071 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
cee98a59 3072 }
5b0f0db6
RS		 3073 }
3074}
3075\f
3076/* Return the appropriate instructions to move SRC into DEST. Assume
3077 that SRC is operand 1 and DEST is operand 0. */
cee98a59 3078
5b0f0db6
RS		 3079const char *
3080mips_output_move (dest, src)
3081 rtx dest, src;
3082{
3083 enum rtx_code dest_code, src_code;
3084 struct mips_constant_info c;
3085 bool dbl_p;
cee98a59 3086
5b0f0db6
RS		 3087 dest_code = GET_CODE (dest);
3088 src_code = GET_CODE (src);
3089 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
cee98a59 3090
5b0f0db6
RS		 3091 if (dbl_p && mips_split_64bit_move_p (dest, src))
3092 return "#";
910628b8 3093
5b0f0db6
RS		 3094 if ((src_code == REG && GP_REG_P (REGNO (src)))
3095 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3096 {
3097 if (dest_code == REG)
910628b8 3098 {
5b0f0db6
RS		 3099 if (GP_REG_P (REGNO (dest)))
3100 return "move\t%0,%z1";
cafe096b 3101
5b0f0db6
RS		 3102 if (MD_REG_P (REGNO (dest)))
3103 return "mt%0\t%z1";
cafe096b 3104
5b0f0db6
RS		 3105 if (FP_REG_P (REGNO (dest)))
3106 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
cafe096b 3107
5b0f0db6
RS		 3108 if (ALL_COP_REG_P (REGNO (dest)))
3109 {
3110 static char retval[] = "dmtc_\t%z1,%0";
cafe096b 3111
5b0f0db6
RS		 3112 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3113 return (dbl_p ? retval : retval + 1);
3114 }
3115 }
3116 if (dest_code == MEM)
3117 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
cee98a59 3118 }
5b0f0db6 3119 if (dest_code == REG && GP_REG_P (REGNO (dest)))
cee98a59 3120 {
5b0f0db6 3121 if (src_code == REG)
cee98a59 3122 {
5b0f0db6
RS		 3123 if (MD_REG_P (REGNO (src)))
3124 return "mf%1\t%0";
cee98a59 3125
5b0f0db6
RS		 3126 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3127 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3128
3129 if (FP_REG_P (REGNO (src)))
3130 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
cee98a59 3131
5b0f0db6 3132 if (ALL_COP_REG_P (REGNO (src)))
d604bca3 3133 {
5b0f0db6 3134 static char retval[] = "dmfc_\t%0,%1";
d604bca3 3135
5b0f0db6
RS		 3136 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3137 return (dbl_p ? retval : retval + 1);
d604bca3 3138 }
cee98a59
MM		 3139 }
3140
5b0f0db6
RS		 3141 if (src_code == MEM)
3142 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
cee98a59 3143
5b0f0db6 3144 if (src_code == CONST_INT)
cee98a59 3145 {
5b0f0db6
RS		 3146 /* Don't use the X format, because that will give out of
3147 range numbers for 64 bit hosts and 32 bit targets. */
3148 if (!TARGET_MIPS16)
3149 return "li\t%0,%1\t\t\t# %X1";
3150
3151 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3152 return "li\t%0,%1";
3153
3154 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3155 return "li\t%0,%n1\n\tneg\t%0";
cee98a59
MM		 3156 }
3157
5b0f0db6
RS		 3158 if (src_code == HIGH)
3159 return "lui\t%0,%h1";
3160
3161 switch (mips_classify_constant (&c, src))
cee98a59 3162 {
5b0f0db6
RS		 3163 case CONSTANT_NONE:
3164 break;
3165
3166 case CONSTANT_GP:
3167 return "move\t%0,%1";
f5963e61 3168
5b0f0db6
RS		 3169 case CONSTANT_RELOC:
3170 return (TARGET_MIPS16 ? "li\t%0,0\n\taddiu\t%0,%1" : "li\t%0,%1");
7dac2f89 3171
5b0f0db6
RS		 3172 case CONSTANT_SYMBOLIC:
3173 return (dbl_p ? "dla\t%0,%a1" : "la\t%0,%a1");
cee98a59
MM		 3174 }
3175 }
5b0f0db6
RS		 3176 if (src_code == REG && FP_REG_P (REGNO (src)))
3177 {
3178 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3179 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
cee98a59 3180
5b0f0db6
RS		 3181 if (dest_code == MEM)
3182 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3183 }
3184 if (dest_code == REG && FP_REG_P (REGNO (dest)))
cee98a59 3185 {
5b0f0db6
RS		 3186 if (src_code == MEM)
3187 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
cee98a59 3188 }
5b0f0db6
RS		 3189 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3190 {
3191 static char retval[] = "l_c_\t%0,%1";
cee98a59 3192
5b0f0db6
RS		 3193 retval[1] = (dbl_p ? 'd' : 'w');
3194 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3195 return retval;
3196 }
3197 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3198 {
3199 static char retval[] = "s_c_\t%1,%0";
cee98a59 3200
5b0f0db6
RS		 3201 retval[1] = (dbl_p ? 'd' : 'w');
3202 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3203 return retval;
3204 }
3205 abort ();
cee98a59 3206}
b2471838
RS		 3207\f
3208/* Return instructions to restore the global pointer from the stack,
3209 assuming TARGET_ABICALLS. Used by exception_receiver to set up
3210 the GP for exception handlers.
3211
3212 OPERANDS is an array of operands whose contents are undefined
5b0f0db6 3213 on entry. */
b2471838
RS		 3214
3215const char *
5b0f0db6
RS		 3216mips_restore_gp (operands)
3217 rtx *operands;
b2471838
RS		 3218{
3219 rtx loc;
3220
3221 operands[0] = pic_offset_table_rtx;
3222 if (frame_pointer_needed)
3223 loc = hard_frame_pointer_rtx;
3224 else
3225 loc = stack_pointer_rtx;
3226 loc = plus_constant (loc, cfun->machine->frame.args_size);
cafe096b 3227 operands[1] = gen_rtx_MEM (ptr_mode, loc);
cee98a59 3228
5b0f0db6 3229 return mips_output_move (operands[0], operands[1]);
b2471838 3230}
cee98a59 3231\f
cee98a59 3232\f
34b650b3
MM		 3233/* Make normal rtx_code into something we can index from an array */
3234
3235static enum internal_test
3236map_test_to_internal_test (test_code)
3237 enum rtx_code test_code;
3238{
3239 enum internal_test test = ITEST_MAX;
3240
3241 switch (test_code)
3242 {
3243 case EQ: test = ITEST_EQ; break;
3244 case NE: test = ITEST_NE; break;
3245 case GT: test = ITEST_GT; break;
3246 case GE: test = ITEST_GE; break;
3247 case LT: test = ITEST_LT; break;
3248 case LE: test = ITEST_LE; break;
3249 case GTU: test = ITEST_GTU; break;
3250 case GEU: test = ITEST_GEU; break;
3251 case LTU: test = ITEST_LTU; break;
3252 case LEU: test = ITEST_LEU; break;
f5963e61 3253 default: break;
34b650b3
MM		 3254 }
3255
3256 return test;
3257}
3258
3259\f
3260/* Generate the code to compare two integer values. The return value is:
3261 (reg:SI xx) The pseudo register the comparison is in
f5963e61 3262 0 No register, generate a simple branch.
147255d8
JW		 3263
3264 ??? This is called with result nonzero by the Scond patterns in
3265 mips.md. These patterns are called with a target in the mode of
3266 the Scond instruction pattern. Since this must be a constant, we
a0ab749a 3267 must use SImode. This means that if RESULT is nonzero, it will
147255d8
JW		 3268 always be an SImode register, even if TARGET_64BIT is true. We
3269 cope with this by calling convert_move rather than emit_move_insn.
3270 This will sometimes lead to an unnecessary extension of the result;
3271 for example:
3272
3273 long long
3274 foo (long long i)
3275 {
3276 return i < 5;
3277 }
3278
3279 */
34b650b3
MM		 3280
3281rtx
3282gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
3283 enum rtx_code test_code; /* relational test (EQ, etc) */
3284 rtx result; /* result to store comp. or 0 if branch */
3285 rtx cmp0; /* first operand to compare */
3286 rtx cmp1; /* second operand to compare */
3287 int *p_invert; /* NULL or ptr to hold whether branch needs */
2296cba3 3288 /* to reverse its test */
34b650b3 3289{
f5963e61
JL		 3290 struct cmp_info
3291 {
34b650b3
MM		 3292 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
3293 int const_low; /* low bound of constant we can accept */
3294 int const_high; /* high bound of constant we can accept */
3295 int const_add; /* constant to add (convert LE -> LT) */
3296 int reverse_regs; /* reverse registers in test */
3297 int invert_const; /* != 0 if invert value if cmp1 is constant */
3298 int invert_reg; /* != 0 if invert value if cmp1 is register */
55f8a64c 3299 int unsignedp; /* != 0 for unsigned comparisons. */
34b650b3
MM		 3300 };
3301
0139adca 3302 static const struct cmp_info info[ (int)ITEST_MAX ] = {
34b650b3 3303
55f8a64c
RS		 3304 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3305 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3306 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3307 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3308 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3309 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3310 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3311 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3312 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3313 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
34b650b3
MM		 3314 };
3315
3316 enum internal_test test;
147255d8 3317 enum machine_mode mode;
0139adca 3318 const struct cmp_info *p_info;
34b650b3
MM		 3319 int branch_p;
3320 int eqne_p;
3321 int invert;
3322 rtx reg;
3323 rtx reg2;
3324
3325 test = map_test_to_internal_test (test_code);
3326 if (test == ITEST_MAX)
3327 abort ();
3328
f5963e61 3329 p_info = &info[(int) test];
34b650b3
MM		 3330 eqne_p = (p_info->test_code == XOR);
3331
147255d8
JW		 3332 mode = GET_MODE (cmp0);
3333 if (mode == VOIDmode)
3334 mode = GET_MODE (cmp1);
3335
34b650b3 3336 /* Eliminate simple branches */
f5963e61 3337 branch_p = (result == 0);
34b650b3
MM		 3338 if (branch_p)
3339 {
3340 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
3341 {
3342 /* Comparisons against zero are simple branches */
2bcb2ab3
GK		 3343 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
3344 && (! TARGET_MIPS16 || eqne_p))
f5963e61 3345 return 0;
34b650b3
MM		 3346
3347 /* Test for beq/bne. */
2bcb2ab3 3348 if (eqne_p && ! TARGET_MIPS16)
f5963e61 3349 return 0;
34b650b3
MM		 3350 }
3351
2296cba3 3352 /* allocate a pseudo to calculate the value in. */
147255d8 3353 result = gen_reg_rtx (mode);
34b650b3
MM		 3354 }
3355
3356 /* Make sure we can handle any constants given to us. */
3357 if (GET_CODE (cmp0) == CONST_INT)
147255d8 3358 cmp0 = force_reg (mode, cmp0);
34b650b3
MM		 3359
3360 if (GET_CODE (cmp1) == CONST_INT)
3361 {
85f5e2b6 3362 HOST_WIDE_INT value = INTVAL (cmp1);
f5963e61 3363
147255d8
JW		 3364 if (value < p_info->const_low
3365 || value > p_info->const_high
3366 /* ??? Why? And why wasn't the similar code below modified too? */
3367 || (TARGET_64BIT
3368 && HOST_BITS_PER_WIDE_INT < 64
3369 && p_info->const_add != 0
3370 && ((p_info->unsignedp
3371 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
e51712db 3372 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
147255d8
JW		 3373 : (value + p_info->const_add) > INTVAL (cmp1))
3374 != (p_info->const_add > 0))))
3375 cmp1 = force_reg (mode, cmp1);
34b650b3
MM		 3376 }
3377
3378 /* See if we need to invert the result. */
f5963e61
JL		 3379 invert = (GET_CODE (cmp1) == CONST_INT
3380 ? p_info->invert_const : p_info->invert_reg);
34b650b3
MM		 3381
3382 if (p_invert != (int *)0)
3383 {
3384 *p_invert = invert;
f5963e61 3385 invert = 0;
34b650b3
MM		 3386 }
3387
3388 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3389 Comparison between two registers, may involve switching operands. */
3390 if (GET_CODE (cmp1) == CONST_INT)
3391 {
3392 if (p_info->const_add != 0)
55f8a64c
RS		 3393 {
3394 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
f5963e61 3395
55f8a64c
RS		 3396 /* If modification of cmp1 caused overflow,
3397 we would get the wrong answer if we follow the usual path;
4db7b4ce 3398 thus, x > 0xffffffffU would turn into x > 0U. */
55f8a64c 3399 if ((p_info->unsignedp
e51712db
KG		 3400 ? (unsigned HOST_WIDE_INT) new >
3401 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
55f8a64c
RS		 3402 : new > INTVAL (cmp1))
3403 != (p_info->const_add > 0))
d40bb52a
RS		 3404 {
3405 /* This test is always true, but if INVERT is true then
3406 the result of the test needs to be inverted so 0 should
3407 be returned instead. */
3408 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
3409 return result;
3410 }
55f8a64c
RS		 3411 else
3412 cmp1 = GEN_INT (new);
3413 }
34b650b3 3414 }
f5963e61 3415
34b650b3
MM		 3416 else if (p_info->reverse_regs)
3417 {
3418 rtx temp = cmp0;
3419 cmp0 = cmp1;
3420 cmp1 = temp;
3421 }
3422
34b650b3 3423 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
bbdb5552
MM		 3424 reg = cmp0;
3425 else
3426 {
147255d8
JW		 3427 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
3428 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
bbdb5552
MM		 3429 }
3430
3431 if (test == ITEST_NE)
34b650b3 3432 {
2bcb2ab3
GK		 3433 if (! TARGET_MIPS16)
3434 {
3435 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
b5265b32
RS		 3436 if (p_invert != NULL)
3437 *p_invert = 0;
f5963e61 3438 invert = 0;
2bcb2ab3
GK		 3439 }
3440 else
3441 {
3442 reg2 = invert ? gen_reg_rtx (mode) : result;
3443 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3444 reg = reg2;
3445 }
34b650b3
MM		 3446 }
3447
bbdb5552 3448 else if (test == ITEST_EQ)
34b650b3 3449 {
f5963e61 3450 reg2 = invert ? gen_reg_rtx (mode) : result;
c5c76735 3451 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
34b650b3
MM		 3452 reg = reg2;
3453 }
3454
3455 if (invert)
2bcb2ab3
GK		 3456 {
3457 rtx one;
3458
3459 if (! TARGET_MIPS16)
3460 one = const1_rtx;
3461 else
3462 {
3463 /* The value is in $24. Copy it to another register, so
3464 that reload doesn't think it needs to store the $24 and
3465 the input to the XOR in the same location. */
3466 reg2 = gen_reg_rtx (mode);
3467 emit_move_insn (reg2, reg);
3468 reg = reg2;
3469 one = force_reg (mode, const1_rtx);
3470 }
3471 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3472 }
34b650b3
MM		 3473
3474 return result;
3475}
cee98a59 3476\f
8ab907e8
RS		 3477/* Work out how to check a floating-point condition. We need a
3478 separate comparison instruction (C.cond.fmt), followed by a
3479 branch or conditional move. Given that IN_CODE is the
3480 required condition, set *CMP_CODE to the C.cond.fmt code
3481 and *action_code to the branch or move code. */
3482
3483static void
3484get_float_compare_codes (in_code, cmp_code, action_code)
3485 enum rtx_code in_code, *cmp_code, *action_code;
3486{
3487 switch (in_code)
3488 {
3489 case NE:
3490 case UNGE:
3491 case UNGT:
3492 case LTGT:
3493 case ORDERED:
3494 *cmp_code = reverse_condition_maybe_unordered (in_code);
3495 *action_code = EQ;
3496 break;
3497
3498 default:
3499 *cmp_code = in_code;
3500 *action_code = NE;
3501 break;
3502 }
3503}
3504
cee98a59
MM		 3505/* Emit the common code for doing conditional branches.
3506 operand[0] is the label to jump to.
147255d8 3507 The comparison operands are saved away by cmp{si,di,sf,df}. */
cee98a59
MM		 3508
3509void
3510gen_conditional_branch (operands, test_code)
3511 rtx operands[];
3512 enum rtx_code test_code;
3513{
b8eb88d0
ILT		 3514 enum cmp_type type = branch_type;
3515 rtx cmp0 = branch_cmp[0];
3516 rtx cmp1 = branch_cmp[1];
cee98a59 3517 enum machine_mode mode;
8ab907e8 3518 enum rtx_code cmp_code;
b8eb88d0
ILT		 3519 rtx reg;
3520 int invert;
3521 rtx label1, label2;
cee98a59 3522
147255d8 3523 switch (type)
cee98a59 3524 {
cee98a59 3525 case CMP_SI:
147255d8 3526 case CMP_DI:
b8eb88d0 3527 mode = type == CMP_SI ? SImode : DImode;
f5963e61 3528 invert = 0;
b8eb88d0 3529 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
f5963e61 3530
b8eb88d0 3531 if (reg)
cee98a59 3532 {
34b650b3
MM		 3533 cmp0 = reg;
3534 cmp1 = const0_rtx;
3535 test_code = NE;
cee98a59 3536 }
34b650b3 3537 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
a0ab749a 3538 /* We don't want to build a comparison against a nonzero
f5963e61
JL		 3539 constant. */
3540 cmp1 = force_reg (mode, cmp1);
3541
cee98a59
MM		 3542 break;
3543
cee98a59 3544 case CMP_SF:
b8eb88d0 3545 case CMP_DF:
76ee8042 3546 if (! ISA_HAS_8CC)
c5c76735 3547 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
b8eb88d0
ILT		 3548 else
3549 reg = gen_reg_rtx (CCmode);
3550
8ab907e8 3551 get_float_compare_codes (test_code, &cmp_code, &test_code);
c5c76735 3552 emit_insn (gen_rtx_SET (VOIDmode, reg,
8ab907e8 3553 gen_rtx (cmp_code, CCmode, cmp0, cmp1)));
7dac2f89 3554
b8eb88d0
ILT		 3555 mode = CCmode;
3556 cmp0 = reg;
3557 cmp1 = const0_rtx;
f5963e61 3558 invert = 0;
cee98a59 3559 break;
f5963e61
JL		 3560
3561 default:
3562 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
cee98a59 3563 }
85f5e2b6 3564
b8eb88d0
ILT		 3565 /* Generate the branch. */
3566
c5c76735 3567 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
b8eb88d0
ILT		 3568 label2 = pc_rtx;
3569
34b650b3
MM		 3570 if (invert)
3571 {
3572 label2 = label1;
3573 label1 = pc_rtx;
3574 }
3575
c5c76735
JL		 3576 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3577 gen_rtx_IF_THEN_ELSE (VOIDmode,
3578 gen_rtx (test_code, mode,
3579 cmp0, cmp1),
3580 label1, label2)));
b8eb88d0 3581}
34b650b3 3582
b8eb88d0
ILT		 3583/* Emit the common code for conditional moves. OPERANDS is the array
3584 of operands passed to the conditional move defined_expand. */
cee98a59 3585
b8eb88d0
ILT		 3586void
3587gen_conditional_move (operands)
3588 rtx *operands;
3589{
3590 rtx op0 = branch_cmp[0];
3591 rtx op1 = branch_cmp[1];
3592 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3593 enum rtx_code cmp_code = GET_CODE (operands[1]);
3594 enum rtx_code move_code = NE;
3595 enum machine_mode op_mode = GET_MODE (operands[0]);
3596 enum machine_mode cmp_mode;
3597 rtx cmp_reg;
3598
3599 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3600 {
3601 switch (cmp_code)
3602 {
3603 case EQ:
3604 cmp_code = XOR;
3605 move_code = EQ;
3606 break;
3607 case NE:
3608 cmp_code = XOR;
3609 break;
3610 case LT:
3611 break;
3612 case GE:
3613 cmp_code = LT;
3614 move_code = EQ;
3615 break;
3616 case GT:
3617 cmp_code = LT;
3618 op0 = force_reg (mode, branch_cmp[1]);
3619 op1 = branch_cmp[0];
3620 break;
3621 case LE:
3622 cmp_code = LT;
3623 op0 = force_reg (mode, branch_cmp[1]);
3624 op1 = branch_cmp[0];
3625 move_code = EQ;
3626 break;
3627 case LTU:
3628 break;
3629 case GEU:
3630 cmp_code = LTU;
3631 move_code = EQ;
3632 break;
3633 case GTU:
3634 cmp_code = LTU;
3635 op0 = force_reg (mode, branch_cmp[1]);
3636 op1 = branch_cmp[0];
3637 break;
3638 case LEU:
3639 cmp_code = LTU;
3640 op0 = force_reg (mode, branch_cmp[1]);
3641 op1 = branch_cmp[0];
3642 move_code = EQ;
3643 break;
3644 default:
3645 abort ();
3646 }
3647 }
8ab907e8
RS		 3648 else
3649 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
7dac2f89 3650
b8eb88d0
ILT		 3651 if (mode == SImode || mode == DImode)
3652 cmp_mode = mode;
3653 else if (mode == SFmode || mode == DFmode)
3654 cmp_mode = CCmode;
3655 else
3656 abort ();
cee98a59 3657
b8eb88d0 3658 cmp_reg = gen_reg_rtx (cmp_mode);
c5c76735
JL		 3659 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3660 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3661
3662 emit_insn (gen_rtx_SET (op_mode, operands[0],
3663 gen_rtx_IF_THEN_ELSE (op_mode,
3664 gen_rtx (move_code, VOIDmode,
3665 cmp_reg,
3666 CONST0_RTX (SImode)),
3667 operands[2], operands[3])));
b8eb88d0 3668}
a0b6cdee
GM		 3669
3670/* Emit the common code for conditional moves. OPERANDS is the array
3671 of operands passed to the conditional move defined_expand. */
3672
3673void
3674mips_gen_conditional_trap (operands)
3675 rtx operands[];
3676{
3677 rtx op0, op1;
3678 enum rtx_code cmp_code = GET_CODE (operands[0]);
3679 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3680
3681 /* MIPS conditional trap machine instructions don't have GT or LE
3682 flavors, so we must invert the comparison and convert to LT and
3683 GE, respectively. */
3684 switch (cmp_code)
3685 {
3686 case GT: cmp_code = LT; break;
3687 case LE: cmp_code = GE; break;
3688 case GTU: cmp_code = LTU; break;
3689 case LEU: cmp_code = GEU; break;
3690 default: break;
3691 }
3692 if (cmp_code == GET_CODE (operands[0]))
3693 {
3694 op0 = force_reg (mode, branch_cmp[0]);
3695 op1 = branch_cmp[1];
3696 }
3697 else
3698 {
3699 op0 = force_reg (mode, branch_cmp[1]);
3700 op1 = branch_cmp[0];
3701 }
3702 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3703 op1 = force_reg (mode, op1);
3704
3705 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3706 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3707 operands[1]));
3708}
cee98a59 3709\f
cafe096b
EC		 3710/* Expand a call or call_value instruction. RESULT is where the
3711 result will go (null for calls), ADDR is the address of the
3712 function, ARGS_SIZE is the size of the arguments and AUX is
3713 the value passed to us by mips_function_arg. SIBCALL_P is true
3714 if we are expanding a sibling call, false if we're expanding
3715 normal call. */
3716
3717void
3718mips_expand_call (result, addr, args_size, aux, sibcall_p)
3719 rtx result, addr, args_size, aux;
3720 int sibcall_p;
3721{
3722 int i;
3723
3724 if (!call_insn_operand (addr, VOIDmode))
3725 {
3726 /* When generating PIC, try to allow global functions to be
3727 lazily bound. */
3728 if (TARGET_EXPLICIT_RELOCS
3729 && GET_CODE (addr) == SYMBOL_REF
3730 && mips_classify_symbol (addr) == SYMBOL_GOT_GLOBAL)
3731 {
3732 if (flag_pic == 1)
3733 addr = mips_load_got16 (addr, RELOC_CALL16);
3734 else
3735 addr = mips_load_got32 (0, addr, RELOC_CALL_HI, RELOC_CALL_LO);
3736 }
3737 addr = force_reg (Pmode, addr);
3738 }
3739
3740 /* In order to pass small structures by value in registers
3741 compatibly with the MIPS compiler, we need to shift the value
3742 into the high part of the register. Function_arg has encoded
3743 a PARALLEL rtx, holding a vector of adjustments to be made
3744 as the next_arg_reg variable, so we split up the insns,
3745 and emit them separately. */
3746 if (aux != 0 && GET_CODE (aux) == PARALLEL)
3747 for (i = 0; i < XVECLEN (aux, 0); i++)
3748 emit_insn (XVECEXP (aux, 0, i));
3749
3750 if (TARGET_MIPS16
3751 && mips16_hard_float
3752 && build_mips16_call_stub (result, addr, args_size,
3753 aux == 0 ? 0 : (int) GET_MODE (aux)))
3754 /* Nothing more to do */;
3755 else if (result == 0)
3756 emit_call_insn (sibcall_p
3757 ? gen_sibcall_internal (addr, args_size)
3758 : gen_call_internal (addr, args_size));
3759 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3760 {
3761 rtx reg1, reg2;
3762
3763 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3764 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3765 emit_call_insn
3766 (sibcall_p
3767 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3768 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3769 }
3770 else
3771 emit_call_insn (sibcall_p
3772 ? gen_sibcall_value_internal (result, addr, args_size)
3773 : gen_call_value_internal (result, addr, args_size));
3774}
3775
3776
3777/* We can handle any sibcall when TARGET_SIBCALLS is true. */
3778
3779static bool
3780mips_function_ok_for_sibcall (decl, exp)
3781 tree decl ATTRIBUTE_UNUSED;
3782 tree exp ATTRIBUTE_UNUSED;
3783{
3784 return TARGET_SIBCALLS;
3785}
3786\f
d12b8c85
RS		 3787/* Return true if operand OP is a condition code register.
3788 Only for use during or after reload. */
3789
3790int
3791fcc_register_operand (op, mode)
3792 rtx op;
3793 enum machine_mode mode;
3794{
3795 return ((mode == VOIDmode || mode == GET_MODE (op))
3796 && (reload_in_progress || reload_completed)
3797 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3798 && ST_REG_P (true_regnum (op)));
3799}
3800
3801/* Emit code to move general operand SRC into condition-code
3802 register DEST. SCRATCH is a scratch TFmode float register.
3803 The sequence is:
3804
3805 FP1 = SRC
3806 FP2 = 0.0f
3807 DEST = FP2 < FP1
3808
3809 where FP1 and FP2 are single-precision float registers
3810 taken from SCRATCH. */
3811
3812void
3813mips_emit_fcc_reload (dest, src, scratch)
3814 rtx dest, src, scratch;
3815{
3816 rtx fp1, fp2;
3817
3818 /* Change the source to SFmode. */
3819 if (GET_CODE (src) == MEM)
3820 src = adjust_address (src, SFmode, 0);
3821 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3822 src = gen_rtx_REG (SFmode, true_regnum (src));
3823
3824 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3825 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3826
3827 emit_move_insn (copy_rtx (fp1), src);
3828 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3829 emit_insn (gen_slt_sf (dest, fp2, fp1));
3830}
3831\f
b2471838
RS		 3832/* Emit code to change the current function's return address to
3833 ADDRESS. SCRATCH is available as a scratch register, if needed.
3834 ADDRESS and SCRATCH are both word-mode GPRs. */
3835
3836void
3837mips_set_return_address (address, scratch)
3838 rtx address, scratch;
3839{
3840 HOST_WIDE_INT gp_offset;
3841
3842 compute_frame_size (get_frame_size ());
3843 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3844 abort ();
3845 gp_offset = cfun->machine->frame.gp_sp_offset;
3846
3847 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3848 if (gp_offset < 32768)
3849 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3850 else
3851 {
3852 emit_move_insn (scratch, GEN_INT (gp_offset));
3853 if (Pmode == DImode)
3854 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3855 else
3856 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3857 }
3858
3859 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3860}
3861\f
f5963e61
JL		 3862/* Write a loop to move a constant number of bytes.
3863 Generate load/stores as follows:
cee98a59
MM		 3864
3865 do {
3866 temp1 = src[0];
3867 temp2 = src[1];
3868 ...
3869 temp<last> = src[MAX_MOVE_REGS-1];
cee98a59
MM		 3870 dest[0] = temp1;
3871 dest[1] = temp2;
3872 ...
3873 dest[MAX_MOVE_REGS-1] = temp<last>;
842eb20e 3874 src += MAX_MOVE_REGS;
cee98a59
MM		 3875 dest += MAX_MOVE_REGS;
3876 } while (src != final);
3877
3878 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3879 registers are needed.
3880
3881 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3882 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3883 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3884
3885#define MAX_MOVE_REGS 4
3886#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3887
3888static void
7cabe29a 3889block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
cee98a59
MM		 3890 rtx dest_reg; /* register holding destination address */
3891 rtx src_reg; /* register holding source address */
c94c9817 3892 unsigned int bytes; /* # bytes to move */
cee98a59 3893 int align; /* alignment */
792760b9 3894 rtx orig_dest; /* original dest */
842eb20e 3895 rtx orig_src; /* original source for making a reg note */
cee98a59 3896{
792760b9
RK		 3897 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3898 rtx src_mem = replace_equiv_address (orig_src, src_reg);
f5963e61 3899 rtx align_rtx = GEN_INT (align);
cee98a59
MM		 3900 rtx label;
3901 rtx final_src;
3902 rtx bytes_rtx;
cee98a59 3903 int leftover;
cee98a59 3904
95adab8e 3905 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
cee98a59
MM		 3906 abort ();
3907
3908 leftover = bytes % MAX_MOVE_BYTES;
3909 bytes -= leftover;
3910
3911 label = gen_label_rtx ();
3912 final_src = gen_reg_rtx (Pmode);
0fb5ac6f 3913 bytes_rtx = GEN_INT (bytes);
cee98a59
MM		 3914
3915 if (bytes > 0x7fff)
3916 {
1eeed24e 3917 if (Pmode == DImode)
147255d8
JW		 3918 {
3919 emit_insn (gen_movdi (final_src, bytes_rtx));
3920 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3921 }
3922 else
3923 {
3924 emit_insn (gen_movsi (final_src, bytes_rtx));
3925 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3926 }
cee98a59
MM		 3927 }
3928 else
147255d8 3929 {
1eeed24e 3930 if (Pmode == DImode)
147255d8
JW		 3931 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3932 else
3933 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3934 }
cee98a59
MM		 3935
3936 emit_label (label);
3937
0fb5ac6f 3938 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
842eb20e 3939 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
f5963e61 3940
1eeed24e 3941 if (Pmode == DImode)
147255d8
JW		 3942 {
3943 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3944 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3945 emit_insn (gen_cmpdi (src_reg, final_src));
3946 }
3947 else
3948 {
3949 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3950 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3951 emit_insn (gen_cmpsi (src_reg, final_src));
3952 }
f5963e61 3953
cee98a59
MM		 3954 emit_jump_insn (gen_bne (label));
3955
3956 if (leftover)
f5963e61 3957 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
842eb20e 3958 align_rtx));
cee98a59 3959}
cee98a59
MM		 3960\f
3961/* Use a library function to move some bytes. */
3962
3963static void
3964block_move_call (dest_reg, src_reg, bytes_rtx)
3965 rtx dest_reg;
3966 rtx src_reg;
3967 rtx bytes_rtx;
3968{
147255d8
JW		 3969 /* We want to pass the size as Pmode, which will normally be SImode
3970 but will be DImode if we are using 64 bit longs and pointers. */
3971 if (GET_MODE (bytes_rtx) != VOIDmode
0da9afa6 3972 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
f5963e61 3973 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
147255d8 3974
cee98a59 3975#ifdef TARGET_MEM_FUNCTIONS
c5c76735 3976 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
f5963e61 3977 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
e24b8776
JW		 3978 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3979 TREE_UNSIGNED (sizetype)),
3980 TYPE_MODE (sizetype));
cee98a59 3981#else
c5c76735 3982 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
f5963e61
JL		 3983 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3984 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3985 TREE_UNSIGNED (integer_type_node)),
e24b8776 3986 TYPE_MODE (integer_type_node));
cee98a59
MM		 3987#endif
3988}
cee98a59
MM		 3989\f
3990/* Expand string/block move operations.
3991
3992 operands[0] is the pointer to the destination.
3993 operands[1] is the pointer to the source.
3994 operands[2] is the number of bytes to move.
3995 operands[3] is the alignment. */
3996
3997void
3998expand_block_move (operands)
3999 rtx operands[];
4000{
4001 rtx bytes_rtx = operands[2];
842eb20e 4002 rtx align_rtx = operands[3];
f5963e61 4003 int constp = GET_CODE (bytes_rtx) == CONST_INT;
c94c9817
MM		 4004 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
4005 unsigned int align = INTVAL (align_rtx);
842eb20e 4006 rtx orig_src = operands[1];
7cabe29a 4007 rtx orig_dest = operands[0];
cee98a59
MM		 4008 rtx src_reg;
4009 rtx dest_reg;
4010
c94c9817 4011 if (constp && bytes == 0)
cee98a59
MM		 4012 return;
4013
0da9afa6 4014 if (align > (unsigned) UNITS_PER_WORD)
842eb20e
MM		 4015 align = UNITS_PER_WORD;
4016
cee98a59 4017 /* Move the address into scratch registers. */
7cabe29a 4018 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
842eb20e 4019 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
cee98a59
MM		 4020
4021 if (TARGET_MEMCPY)
4022 block_move_call (dest_reg, src_reg, bytes_rtx);
4023
95adab8e 4024 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
0da9afa6 4025 && align == (unsigned) UNITS_PER_WORD)
460f6b71 4026 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
7dac2f89 4027
95adab8e 4028 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
792760b9
RK		 4029 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
4030 dest_reg),
4031 replace_equiv_address (orig_src,
4032 src_reg),
842eb20e 4033 bytes_rtx, align_rtx));
cee98a59 4034
0da9afa6 4035 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
7cabe29a 4036 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
cee98a59
MM		 4037
4038 else if (constp && optimize)
4039 {
4040 /* If the alignment is not word aligned, generate a test at
4041 runtime, to see whether things wound up aligned, and we
4042 can use the faster lw/sw instead ulw/usw. */
4043
f5963e61 4044 rtx temp = gen_reg_rtx (Pmode);
cee98a59 4045 rtx aligned_label = gen_label_rtx ();
f5963e61
JL		 4046 rtx join_label = gen_label_rtx ();
4047 int leftover = bytes % MAX_MOVE_BYTES;
cee98a59
MM		 4048
4049 bytes -= leftover;
4050
1eeed24e 4051 if (Pmode == DImode)
147255d8
JW		 4052 {
4053 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
f5963e61 4054 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
147255d8
JW		 4055 emit_insn (gen_cmpdi (temp, const0_rtx));
4056 }
4057 else
4058 {
4059 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
f5963e61 4060 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
147255d8
JW		 4061 emit_insn (gen_cmpsi (temp, const0_rtx));
4062 }
f5963e61 4063
cee98a59
MM		 4064 emit_jump_insn (gen_beq (aligned_label));
4065
4066 /* Unaligned loop. */
7cabe29a 4067 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
cee98a59
MM		 4068 emit_jump_insn (gen_jump (join_label));
4069 emit_barrier ();
4070
4071 /* Aligned loop. */
4072 emit_label (aligned_label);
7cabe29a
JW		 4073 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
4074 orig_src);
cee98a59
MM		 4075 emit_label (join_label);
4076
4077 /* Bytes at the end of the loop. */
4078 if (leftover)
792760b9
RK		 4079 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
4080 dest_reg),
4081 replace_equiv_address (orig_src,
4082 src_reg),
7cabe29a
JW		 4083 GEN_INT (leftover),
4084 GEN_INT (align)));
cee98a59
MM		 4085 }
4086
4087 else
4088 block_move_call (dest_reg, src_reg, bytes_rtx);
4089}
842eb20e 4090\f
7dac2f89 4091/* Emit load/stores for a small constant block_move.
842eb20e
MM		 4092
4093 operands[0] is the memory address of the destination.
4094 operands[1] is the memory address of the source.
4095 operands[2] is the number of bytes to move.
4096 operands[3] is the alignment.
4097 operands[4] is a temp register.
4098 operands[5] is a temp register.
c4b9be8e
MM		 4099 ...
4100 operands[3+num_regs] is the last temp register.
4101
4102 The block move type can be one of the following:
4103 BLOCK_MOVE_NORMAL Do all of the block move.
4104 BLOCK_MOVE_NOT_LAST Do all but the last store.
987ba558 4105 BLOCK_MOVE_LAST Do just the last store. */
842eb20e 4106
e2fe6aba 4107const char *
c4b9be8e 4108output_block_move (insn, operands, num_regs, move_type)
842eb20e
MM		 4109 rtx insn;
4110 rtx operands[];
4111 int num_regs;
c4b9be8e 4112 enum block_move_type move_type;
842eb20e 4113{
f5963e61
JL		 4114 rtx dest_reg = XEXP (operands[0], 0);
4115 rtx src_reg = XEXP (operands[1], 0);
4116 HOST_WIDE_INT bytes = INTVAL (operands[2]);
4117 int align = INTVAL (operands[3]);
4118 int num = 0;
4119 int offset = 0;
4120 int use_lwl_lwr = 0;
4121 int last_operand = num_regs + 4;
4122 int safe_regs = 4;
842eb20e
MM		 4123 int i;
4124 rtx xoperands[10];
4125
4126 struct {
e2fe6aba
KG		 4127 const char *load; /* load insn without nop */
4128 const char *load_nop; /* load insn with trailing nop */
4129 const char *store; /* store insn */
4130 const char *final; /* if last_store used: NULL or swr */
4131 const char *last_store; /* last store instruction */
842eb20e
MM		 4132 int offset; /* current offset */
4133 enum machine_mode mode; /* mode to use on (MEM) */
4134 } load_store[4];
4135
f5963e61 4136 /* ??? Detect a bug in GCC, where it can give us a register
4bb89a8e
MM		 4137 the same as one of the addressing registers and reduce
4138 the number of registers available. */
b6a1cbae 4139 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
f5963e61
JL		 4140 if (! reg_mentioned_p (operands[i], operands[0])
4141 && ! reg_mentioned_p (operands[i], operands[1]))
4142 xoperands[safe_regs++] = operands[i];
4bb89a8e
MM		 4143
4144 if (safe_regs < last_operand)
4145 {
4146 xoperands[0] = operands[0];
4147 xoperands[1] = operands[1];
4148 xoperands[2] = operands[2];
4149 xoperands[3] = operands[3];
f5963e61 4150 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
c6f3187f
RS		 4151 }
4152
842eb20e
MM		 4153 /* If we are given global or static addresses, and we would be
4154 emitting a few instructions, try to save time by using a
4155 temporary register for the pointer. */
a8136932
JW		 4156 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
4157 an ldl/ldr instruction pair. We play it safe, and always move
4158 constant addresses into registers when generating N32/N64 code, just
4159 in case we might emit an unaligned load instruction. */
f5963e61 4160 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
0e5a4ad8
EC		 4161 || mips_abi == ABI_N32
4162 || mips_abi == ABI_64))
842eb20e
MM		 4163 {
4164 if (CONSTANT_P (src_reg))
4165 {
4e09f580
MM		 4166 if (TARGET_STATS)
4167 mips_count_memory_refs (operands[1], 1);
4168
f5963e61 4169 src_reg = operands[3 + num_regs--];
c4b9be8e
MM		 4170 if (move_type != BLOCK_MOVE_LAST)
4171 {
4172 xoperands[1] = operands[1];
4173 xoperands[0] = src_reg;
33563487
JW		 4174 if (Pmode == DImode)
4175 output_asm_insn ("dla\t%0,%1", xoperands);
4176 else
4177 output_asm_insn ("la\t%0,%1", xoperands);
c4b9be8e 4178 }
842eb20e
MM		 4179 }
4180
4181 if (CONSTANT_P (dest_reg))
4182 {
4e09f580
MM		 4183 if (TARGET_STATS)
4184 mips_count_memory_refs (operands[0], 1);
4185
f5963e61 4186 dest_reg = operands[3 + num_regs--];
c4b9be8e
MM		 4187 if (move_type != BLOCK_MOVE_LAST)
4188 {
4189 xoperands[1] = operands[0];
4190 xoperands[0] = dest_reg;
33563487
JW		 4191 if (Pmode == DImode)
4192 output_asm_insn ("dla\t%0,%1", xoperands);
4193 else
4194 output_asm_insn ("la\t%0,%1", xoperands);
c4b9be8e 4195 }
842eb20e
MM		 4196 }
4197 }
4198
910628b8
JW		 4199 /* ??? We really shouldn't get any LO_SUM addresses here, because they
4200 are not offsettable, however, offsettable_address_p says they are
4201 offsettable. I think this is a bug in offsettable_address_p.
4202 For expediency, we fix this by just loading the address into a register
4203 if we happen to get one. */
4204
4205 if (GET_CODE (src_reg) == LO_SUM)
4206 {
f5963e61 4207 src_reg = operands[3 + num_regs--];
910628b8
JW		 4208 if (move_type != BLOCK_MOVE_LAST)
4209 {
4210 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
4211 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
4212 xoperands[0] = src_reg;
4213 if (Pmode == DImode)
4214 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
4215 else
4216 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
4217 }
4218 }
4219
4220 if (GET_CODE (dest_reg) == LO_SUM)
4221 {
f5963e61 4222 dest_reg = operands[3 + num_regs--];
910628b8
JW		 4223 if (move_type != BLOCK_MOVE_LAST)
4224 {
4225 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
4226 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
4227 xoperands[0] = dest_reg;
4228 if (Pmode == DImode)
4229 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
4230 else
4231 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
4232 }
4233 }
4234
b6a1cbae
GM		 4235 if (num_regs > (int) ARRAY_SIZE (load_store))
4236 num_regs = ARRAY_SIZE (load_store);
842eb20e
MM		 4237
4238 else if (num_regs < 1)
f5963e61 4239 abort_with_insn (insn,
c725bd79 4240 "cannot do block move, not enough scratch registers");
842eb20e 4241
842eb20e
MM		 4242 while (bytes > 0)
4243 {
4244 load_store[num].offset = offset;
4245
147255d8
JW		 4246 if (TARGET_64BIT && bytes >= 8 && align >= 8)
4247 {
f5963e61
JL		 4248 load_store[num].load = "ld\t%0,%1";
4249 load_store[num].load_nop = "ld\t%0,%1%#";
4250 load_store[num].store = "sd\t%0,%1";
147255d8 4251 load_store[num].last_store = "sd\t%0,%1";
f5963e61
JL		 4252 load_store[num].final = 0;
4253 load_store[num].mode = DImode;
147255d8
JW		 4254 offset += 8;
4255 bytes -= 8;
4256 }
4257
2bcb2ab3 4258 /* ??? Fails because of a MIPS assembler bug? */
5ce6f47b
EC		 4259 else if (TARGET_64BIT && bytes >= 8
4260 && ! TARGET_SR71K
4261 && ! TARGET_MIPS16)
147255d8 4262 {
96abdcb1
ILT		 4263 if (BYTES_BIG_ENDIAN)
4264 {
f5963e61
JL		 4265 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
4266 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
4267 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
96abdcb1 4268 load_store[num].last_store = "sdr\t%0,%2";
f5963e61 4269 load_store[num].final = "sdl\t%0,%1";
96abdcb1
ILT		 4270 }
4271 else
4272 {
f5963e61
JL		 4273 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
4274 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
4275 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
96abdcb1 4276 load_store[num].last_store = "sdr\t%0,%1";
f5963e61 4277 load_store[num].final = "sdl\t%0,%2";
96abdcb1 4278 }
f5963e61 4279
147255d8
JW		 4280 load_store[num].mode = DImode;
4281 offset += 8;
4282 bytes -= 8;
f5963e61 4283 use_lwl_lwr = 1;
147255d8
JW		 4284 }
4285
4286 else if (bytes >= 4 && align >= 4)
842eb20e 4287 {
f5963e61
JL		 4288 load_store[num].load = "lw\t%0,%1";
4289 load_store[num].load_nop = "lw\t%0,%1%#";
4290 load_store[num].store = "sw\t%0,%1";
c4b9be8e 4291 load_store[num].last_store = "sw\t%0,%1";
f5963e61
JL		 4292 load_store[num].final = 0;
4293 load_store[num].mode = SImode;
147255d8
JW		 4294 offset += 4;
4295 bytes -= 4;
842eb20e
MM		 4296 }
4297
5ce6f47b
EC		 4298 else if (bytes >= 4
4299 && ! TARGET_SR71K
4300 && ! TARGET_MIPS16)
0cebb05d 4301 {
96abdcb1
ILT		 4302 if (BYTES_BIG_ENDIAN)
4303 {
f5963e61
JL		 4304 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
4305 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
4306 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
96abdcb1 4307 load_store[num].last_store = "swr\t%0,%2";
f5963e61 4308 load_store[num].final = "swl\t%0,%1";
96abdcb1
ILT		 4309 }
4310 else
4311 {
f5963e61
JL		 4312 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
4313 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
4314 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
96abdcb1 4315 load_store[num].last_store = "swr\t%0,%1";
f5963e61 4316 load_store[num].final = "swl\t%0,%2";
96abdcb1 4317 }
f5963e61 4318
0cebb05d 4319 load_store[num].mode = SImode;
147255d8
JW		 4320 offset += 4;
4321 bytes -= 4;
f5963e61 4322 use_lwl_lwr = 1;
0cebb05d
MM		 4323 }
4324
147255d8 4325 else if (bytes >= 2 && align >= 2)
842eb20e 4326 {
f5963e61
JL		 4327 load_store[num].load = "lh\t%0,%1";
4328 load_store[num].load_nop = "lh\t%0,%1%#";
4329 load_store[num].store = "sh\t%0,%1";
c4b9be8e 4330 load_store[num].last_store = "sh\t%0,%1";
f5963e61
JL		 4331 load_store[num].final = 0;
4332 load_store[num].mode = HImode;
147255d8
JW		 4333 offset += 2;
4334 bytes -= 2;
842eb20e 4335 }
842eb20e
MM		 4336 else
4337 {
f5963e61
JL		 4338 load_store[num].load = "lb\t%0,%1";
4339 load_store[num].load_nop = "lb\t%0,%1%#";
4340 load_store[num].store = "sb\t%0,%1";
c4b9be8e 4341 load_store[num].last_store = "sb\t%0,%1";
f5963e61
JL		 4342 load_store[num].final = 0;
4343 load_store[num].mode = QImode;
842eb20e
MM		 4344 offset++;
4345 bytes--;
4346 }
4347
c4b9be8e 4348 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4e09f580 4349 {
c4b9be8e
MM		 4350 dslots_load_total++;
4351 dslots_load_filled++;
4352
4e09f580
MM		 4353 if (CONSTANT_P (src_reg))
4354 mips_count_memory_refs (src_reg, 1);
4355
4356 if (CONSTANT_P (dest_reg))
4357 mips_count_memory_refs (dest_reg, 1);
4358 }
4359
842eb20e
MM		 4360 /* Emit load/stores now if we have run out of registers or are
4361 at the end of the move. */
4362
4e09f580 4363 if (++num == num_regs || bytes == 0)
842eb20e
MM		 4364 {
4365 /* If only load/store, we need a NOP after the load. */
4366 if (num == 1)
4e09f580
MM		 4367 {
4368 load_store[0].load = load_store[0].load_nop;
c4b9be8e
MM		 4369 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4370 dslots_load_filled--;
4e09f580 4371 }
842eb20e 4372
c4b9be8e 4373 if (move_type != BLOCK_MOVE_LAST)
842eb20e 4374 {
c4b9be8e
MM		 4375 for (i = 0; i < num; i++)
4376 {
4377 int offset;
0cebb05d 4378
f5963e61 4379 if (!operands[i + 4])
c4b9be8e 4380 abort ();
842eb20e 4381
f5963e61 4382 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
c5c76735
JL		 4383 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
4384 REGNO (operands[i + 4]));
842eb20e 4385
c4b9be8e 4386 offset = load_store[i].offset;
f5963e61 4387 xoperands[0] = operands[i + 4];
c5c76735
JL		 4388 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4389 plus_constant (src_reg, offset));
0cebb05d 4390
c4b9be8e 4391 if (use_lwl_lwr)
147255d8 4392 {
f5963e61
JL		 4393 int extra_offset
4394 = GET_MODE_SIZE (load_store[i].mode) - 1;
4395
c5c76735
JL		 4396 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4397 plus_constant (src_reg,
4398 extra_offset
4399 + offset));
147255d8 4400 }
0cebb05d 4401
c4b9be8e
MM		 4402 output_asm_insn (load_store[i].load, xoperands);
4403 }
842eb20e
MM		 4404 }
4405
4406 for (i = 0; i < num; i++)
4407 {
c4b9be8e 4408 int last_p = (i == num-1 && bytes == 0);
0cebb05d 4409 int offset = load_store[i].offset;
c4b9be8e 4410
f5963e61 4411 xoperands[0] = operands[i + 4];
c5c76735
JL		 4412 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4413 plus_constant (dest_reg, offset));
0cebb05d
MM		 4414
4415
4416 if (use_lwl_lwr)
147255d8 4417 {
f5963e61 4418 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
c5c76735
JL		 4419 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4420 plus_constant (dest_reg,
4421 extra_offset
4422 + offset));
147255d8 4423 }
0cebb05d 4424
c4b9be8e
MM		 4425 if (move_type == BLOCK_MOVE_NORMAL)
4426 output_asm_insn (load_store[i].store, xoperands);
4427
4428 else if (move_type == BLOCK_MOVE_NOT_LAST)
4429 {
4430 if (!last_p)
4431 output_asm_insn (load_store[i].store, xoperands);
4432
f5963e61 4433 else if (load_store[i].final != 0)
c4b9be8e
MM		 4434 output_asm_insn (load_store[i].final, xoperands);
4435 }
4436
4437 else if (last_p)
4438 output_asm_insn (load_store[i].last_store, xoperands);
842eb20e
MM		 4439 }
4440
4441 num = 0; /* reset load_store */
f5963e61 4442 use_lwl_lwr = 0;
842eb20e
MM		 4443 }
4444 }
4445
842eb20e
MM		 4446 return "";
4447}
cee98a59
MM		 4448\f
4449/* Argument support functions. */
4450
4451/* Initialize CUMULATIVE_ARGS for a function. */
4452
4453void
4454init_cumulative_args (cum, fntype, libname)
38831dfe
KG		 4455 CUMULATIVE_ARGS *cum; /* argument info to initialize */
4456 tree fntype; /* tree ptr for function decl */
4457 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
cee98a59 4458{
3f1f8d8c 4459 static CUMULATIVE_ARGS zero_cum;
cee98a59
MM		 4460 tree param, next_param;
4461
4462 if (TARGET_DEBUG_E_MODE)
6cb6c3b3 4463 {
f5963e61
JL		 4464 fprintf (stderr,
4465 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
4466
6cb6c3b3
MM		 4467 if (!fntype)
4468 fputc ('\n', stderr);
4469
4470 else
4471 {
4472 tree ret_type = TREE_TYPE (fntype);
4473 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
f5963e61
JL		 4474 tree_code_name[(int)TREE_CODE (fntype)],
4475 tree_code_name[(int)TREE_CODE (ret_type)]);
6cb6c3b3
MM		 4476 }
4477 }
cee98a59 4478
3f1f8d8c 4479 *cum = zero_cum;
3054eeed 4480 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
cee98a59
MM		 4481
4482 /* Determine if this function has variable arguments. This is
4483 indicated by the last argument being 'void_type_mode' if there
4484 are no variable arguments. The standard MIPS calling sequence
987ba558 4485 passes all arguments in the general purpose registers in this case. */
cee98a59 4486
f5963e61
JL		 4487 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
4488 param != 0; param = next_param)
cee98a59
MM		 4489 {
4490 next_param = TREE_CHAIN (param);
f5963e61 4491 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
cee98a59
MM		 4492 cum->gp_reg_found = 1;
4493 }
cee98a59
MM		 4494}
4495
4d72536e
RS		 4496static void
4497mips_arg_info (cum, mode, type, named, info)
4498 const CUMULATIVE_ARGS *cum;
4499 enum machine_mode mode;
4500 tree type;
4501 int named;
4502 struct mips_arg_info *info;
4503{
4504 bool even_reg_p;
4505 unsigned int num_words, max_regs;
4506
4507 info->struct_p = (type != 0
4508 && (TREE_CODE (type) == RECORD_TYPE
4509 || TREE_CODE (type) == UNION_TYPE
4510 || TREE_CODE (type) == QUAL_UNION_TYPE));
4511
4512 /* Decide whether this argument should go in a floating-point register,
4513 assuming one is free. Later code checks for availablity. */
4514
4515 info->fpr_p = false;
4516 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4517 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
4518 {
4519 switch (mips_abi)
4520 {
4521 case ABI_32:
4522 case ABI_O64:
4523 info->fpr_p = (!cum->gp_reg_found && cum->arg_number < 2);
4524 break;
4525
4526 case ABI_EABI:
4527 info->fpr_p = true;
4528 break;
4529
4d72536e
RS		 4530 default:
4531 info->fpr_p = named;
4532 break;
4533 }
4534 }
4535
4536 /* Now decide whether the argument must go in an even-numbered register. */
4537
4538 even_reg_p = false;
4539 if (info->fpr_p)
4540 {
4541 /* Under the O64 ABI, the second float argument goes in $f13 if it
4542 is a double, but $f14 if it is a single. Otherwise, on a
4543 32-bit double-float machine, each FP argument must start in a
4544 new register pair. */
8a381273
AO		 4545 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
4546 || (mips_abi == ABI_O64 && mode == SFmode)
4547 || FP_INC > 1);
4d72536e 4548 }
8a381273 4549 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
4d72536e
RS		 4550 {
4551 if (GET_MODE_CLASS (mode) == MODE_INT
4552 || GET_MODE_CLASS (mode) == MODE_FLOAT)
4553 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
4554
4555 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
4556 even_reg_p = true;
4557 }
4558
4559 /* Set REG_OFFSET to the register count we're interested in.
4560 The EABI allocates the floating-point registers separately,
4561 but the other ABIs allocate them like integer registers. */
4562 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
bb63e5a0
RS		 4563 ? cum->num_fprs
4564 : cum->num_gprs);
4d72536e
RS		 4565
4566 if (even_reg_p)
4567 info->reg_offset += info->reg_offset & 1;
4568
4569 /* The alignment applied to registers is also applied to stack arguments. */
4570 info->stack_offset = cum->stack_words;
4571 if (even_reg_p)
4572 info->stack_offset += info->stack_offset & 1;
4573
4574 if (mode == BLKmode)
4575 info->num_bytes = int_size_in_bytes (type);
4576 else
4577 info->num_bytes = GET_MODE_SIZE (mode);
4578
4579 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4580 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4581
4582 /* Partition the argument between registers and stack. */
4583 info->reg_words = MIN (num_words, max_regs);
4584 info->stack_words = num_words - info->reg_words;
4585}
4586
4587
cee98a59
MM		 4588/* Advance the argument to the next argument position. */
4589
4590void
4591function_arg_advance (cum, mode, type, named)
4592 CUMULATIVE_ARGS *cum; /* current arg information */
4593 enum machine_mode mode; /* current arg mode */
4594 tree type; /* type of the argument or 0 if lib support */
0fb5ac6f 4595 int named; /* whether or not the argument was named */
cee98a59 4596{
4d72536e
RS		 4597 struct mips_arg_info info;
4598
4599 mips_arg_info (cum, mode, type, named, &info);
4600
4601 /* The following is a hack in order to pass 1 byte structures
4602 the same way that the MIPS compiler does (namely by passing
4603 the structure in the high byte or half word of the register).
4604 This also makes varargs work. If we have such a structure,
4605 we save the adjustment RTL, and the call define expands will
4606 emit them. For the VOIDmode argument (argument after the
4607 last real argument), pass back a parallel vector holding each
4608 of the adjustments. */
4609
4610 /* ??? This scheme requires everything smaller than the word size to
4611 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4612 that would mean every int needs to be shifted left, which is very
4613 inefficient. Let's not carry this compatibility to the 64 bit
4614 calling convention for now. */
4615
4616 if (info.struct_p
4617 && info.reg_words == 1
4618 && info.num_bytes < UNITS_PER_WORD
4619 && !TARGET_64BIT
cafe096b 4620 && mips_abi != ABI_EABI)
cee98a59 4621 {
4d72536e
RS		 4622 rtx amount = GEN_INT (BITS_PER_WORD - info.num_bytes * BITS_PER_UNIT);
4623 rtx reg = gen_rtx_REG (word_mode, GP_ARG_FIRST + info.reg_offset);
f5963e61 4624
4d72536e 4625 if (TARGET_64BIT)
88c65786 4626 cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashldi3 (reg, reg, amount));
4d72536e 4627 else
88c65786 4628 cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashlsi3 (reg, reg, amount));
4d72536e 4629 }
cee98a59 4630
4d72536e
RS		 4631 if (!info.fpr_p)
4632 cum->gp_reg_found = true;
cee98a59 4633
4d72536e
RS		 4634 /* See the comment above the cumulative args structure in mips.h
4635 for an explanation of what this code does. It assumes the O32
4636 ABI, which passes at most 2 arguments in float registers. */
4637 if (cum->arg_number < 2 && info.fpr_p)
4638 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
cee98a59 4639
4d72536e 4640 if (mips_abi != ABI_EABI || !info.fpr_p)
bb63e5a0 4641 cum->num_gprs = info.reg_offset + info.reg_words;
4d72536e 4642 else if (info.reg_words > 0)
bb63e5a0 4643 cum->num_fprs += FP_INC;
cee98a59 4644
4d72536e
RS		 4645 if (info.stack_words > 0)
4646 cum->stack_words = info.stack_offset + info.stack_words;
cee98a59 4647
4d72536e 4648 cum->arg_number++;
cee98a59
MM		 4649}
4650
147255d8
JW		 4651/* Return an RTL expression containing the register for the given mode,
4652 or 0 if the argument is to be passed on the stack. */
cee98a59
MM		 4653
4654struct rtx_def *
4655function_arg (cum, mode, type, named)
4d72536e 4656 const CUMULATIVE_ARGS *cum; /* current arg information */
cee98a59
MM		 4657 enum machine_mode mode; /* current arg mode */
4658 tree type; /* type of the argument or 0 if lib support */
4659 int named; /* != 0 for normal args, == 0 for ... args */
4660{
4d72536e 4661 struct mips_arg_info info;
cee98a59 4662
4d72536e
RS		 4663 /* We will be called with a mode of VOIDmode after the last argument
4664 has been seen. Whatever we return will be passed to the call
4665 insn. If we need any shifts for small structures, return them in
4666 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4667 mode. Otherwise, if we need a mips16 fp_code, return a REG
4668 with the code stored as the mode. */
4669 if (mode == VOIDmode)
cee98a59 4670 {
4d72536e
RS		 4671 if (cum->num_adjusts > 0)
4672 return gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code,
4673 gen_rtvec_v (cum->num_adjusts,
4674 (rtx *) cum->adjust));
cee98a59 4675
4d72536e
RS		 4676 else if (TARGET_MIPS16 && cum->fp_code != 0)
4677 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
f5963e61 4678
33563487 4679 else
4d72536e 4680 return 0;
cee98a59
MM		 4681 }
4682
4d72536e 4683 mips_arg_info (cum, mode, type, named, &info);
cee98a59 4684
4d72536e
RS		 4685 /* Return straight away if the whole argument is passed on the stack. */
4686 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4687 return 0;
cee98a59 4688
4d72536e
RS		 4689 if (type != 0
4690 && TREE_CODE (type) == RECORD_TYPE
4691 && (mips_abi == ABI_N32 || mips_abi == ABI_64)
4692 && TYPE_SIZE_UNIT (type)
4693 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4694 && named
4695 && mode != DFmode)
4696 {
4697 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4698 structure contains a double in its entirety, then that 64 bit
4699 chunk is passed in a floating point register. */
4700 tree field;
4701
4702 /* First check to see if there is any such field. */
4703 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4704 if (TREE_CODE (field) == FIELD_DECL
4705 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4706 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4707 && host_integerp (bit_position (field), 0)
4708 && int_bit_position (field) % BITS_PER_WORD == 0)
4709 break;
0e5a4ad8 4710
4d72536e 4711 if (field != 0)
a20b7b05 4712 {
4d72536e
RS		 4713 /* Now handle the special case by returning a PARALLEL
4714 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4715 chunks are passed in registers. */
4716 unsigned int i;
4717 HOST_WIDE_INT bitpos;
4718 rtx ret;
4719
4720 /* assign_parms checks the mode of ENTRY_PARM, so we must
4721 use the actual mode here. */
4722 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4723
4724 bitpos = 0;
4725 field = TYPE_FIELDS (type);
4726 for (i = 0; i < info.reg_words; i++)
a20b7b05 4727 {
4d72536e 4728 rtx reg;
7dac2f89 4729
4d72536e
RS		 4730 for (; field; field = TREE_CHAIN (field))
4731 if (TREE_CODE (field) == FIELD_DECL
4732 && int_bit_position (field) >= bitpos)
4733 break;
a20b7b05 4734
4d72536e
RS		 4735 if (field
4736 && int_bit_position (field) == bitpos
4737 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4738 && !TARGET_SOFT_FLOAT
4739 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4740 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4741 else
4742 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
cee98a59 4743
4d72536e
RS		 4744 XVECEXP (ret, 0, i)
4745 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4746 GEN_INT (bitpos / BITS_PER_UNIT));
f5963e61 4747
4d72536e
RS		 4748 bitpos += BITS_PER_WORD;
4749 }
4750 return ret;
3f1f8d8c
MM		 4751 }
4752 }
4753
4d72536e
RS		 4754 if (info.fpr_p)
4755 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
4756 else
4757 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
cee98a59
MM		 4758}
4759
cee98a59
MM		 4760int
4761function_arg_partial_nregs (cum, mode, type, named)
4d72536e 4762 const CUMULATIVE_ARGS *cum; /* current arg information */
cee98a59
MM		 4763 enum machine_mode mode; /* current arg mode */
4764 tree type; /* type of the argument or 0 if lib support */
4d72536e 4765 int named; /* != 0 for normal args, == 0 for ... args */
cee98a59 4766{
4d72536e 4767 struct mips_arg_info info;
cee98a59 4768
4d72536e
RS		 4769 mips_arg_info (cum, mode, type, named, &info);
4770 return info.stack_words > 0 ? info.reg_words : 0;
4771}
4772\f
4773int
4774mips_setup_incoming_varargs (cum, mode, type, no_rtl)
4775 const CUMULATIVE_ARGS *cum;
4776 enum machine_mode mode;
4777 tree type;
4778 int no_rtl;
4779{
4780 CUMULATIVE_ARGS local_cum;
4781 int gp_saved, fp_saved;
cee98a59 4782
4d72536e
RS		 4783 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4784 return 0;
cee98a59 4785
4d72536e
RS		 4786 /* The caller has advanced CUM up to, but not beyond, the last named
4787 argument. Advance a local copy of CUM past the last "real" named
6c535c69 4788 argument, to find out how many registers are left over. */
4d72536e 4789
4d72536e 4790 local_cum = *cum;
6c535c69 4791 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4d72536e
RS		 4792
4793 /* Found out how many registers we need to save. */
bb63e5a0 4794 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4d72536e 4795 fp_saved = (EABI_FLOAT_VARARGS_P
bb63e5a0 4796 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4d72536e 4797 : 0);
cee98a59 4798
4d72536e 4799 if (!no_rtl)
cee98a59 4800 {
4d72536e
RS		 4801 if (gp_saved > 0)
4802 {
4803 rtx ptr, mem;
4804
4805 ptr = virtual_incoming_args_rtx;
4806 if (mips_abi == ABI_EABI)
4807 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
4808 mem = gen_rtx_MEM (BLKmode, ptr);
4809
4810 /* va_arg is an array access in this case, which causes
4811 it to get MEM_IN_STRUCT_P set. We must set it here
4812 so that the insn scheduler won't assume that these
4813 stores can't possibly overlap with the va_arg loads. */
4814 if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)
4815 MEM_SET_IN_STRUCT_P (mem, 1);
4816
bb63e5a0 4817 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, mem,
c6b97fac 4818 gp_saved);
4d72536e
RS		 4819 }
4820 if (fp_saved > 0)
4821 {
4822 /* We can't use move_block_from_reg, because it will use
4823 the wrong mode. */
4824 enum machine_mode mode;
4825 int off, i;
cee98a59 4826
4d72536e
RS		 4827 /* Set OFF to the offset from virtual_incoming_args_rtx of
4828 the first float register. The FP save area lies below
4829 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4830 off = -gp_saved * UNITS_PER_WORD;
4831 off &= ~(UNITS_PER_FPVALUE - 1);
4832 off -= fp_saved * UNITS_PER_FPREG;
cee98a59 4833
4d72536e
RS		 4834 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4835
bb63e5a0 4836 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4d72536e
RS		 4837 {
4838 rtx ptr = plus_constant (virtual_incoming_args_rtx, off);
4839 emit_move_insn (gen_rtx_MEM (mode, ptr),
4840 gen_rtx_REG (mode, FP_ARG_FIRST + i));
8a381273 4841 off += UNITS_PER_HWFPVALUE;
4d72536e
RS		 4842 }
4843 }
4844 }
4845 return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
cee98a59 4846}
4d72536e 4847
4fe12442
DL		 4848/* Create the va_list data type.
4849 We keep 3 pointers, and two offsets.
7dac2f89 4850 Two pointers are to the overflow area, which starts at the CFA.
4fe12442
DL		 4851 One of these is constant, for addressing into the GPR save area below it.
4852 The other is advanced up the stack through the overflow region.
4853 The third pointer is to the GPR save area. Since the FPR save area
4854 is just below it, we can address FPR slots off this pointer.
4855 We also keep two one-byte offsets, which are to be subtracted from the
4856 constant pointers to yield addresses in the GPR and FPR save areas.
7dac2f89
EC		 4857 These are downcounted as float or non-float arguments are used,
4858 and when they get to zero, the argument must be obtained from the
4fe12442 4859 overflow region.
4d72536e
RS		 4860 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4861 pointer is enough. It's started at the GPR save area, and is
4862 advanced, period.
4fe12442
DL		 4863 Note that the GPR save area is not constant size, due to optimization
4864 in the prologue. Hence, we can't use a design with two pointers
4865 and two offsets, although we could have designed this with two pointers
987ba558 4866 and three offsets. */
4fe12442 4867
5d3f2bd5
RH		 4868
4869tree
4870mips_build_va_list ()
4871{
4d72536e 4872 if (EABI_FLOAT_VARARGS_P)
5d3f2bd5 4873 {
4fe12442 4874 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
5d3f2bd5
RH		 4875
4876 record = make_node (RECORD_TYPE);
4877
4fe12442
DL		 4878 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4879 ptr_type_node);
4880 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
5d3f2bd5 4881 ptr_type_node);
4fe12442 4882 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
5d3f2bd5 4883 ptr_type_node);
4fe12442
DL		 4884 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4885 unsigned_char_type_node);
4886 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4887 unsigned_char_type_node);
5d3f2bd5 4888
5d3f2bd5 4889
4fe12442
DL		 4890 DECL_FIELD_CONTEXT (f_ovfl) = record;
4891 DECL_FIELD_CONTEXT (f_gtop) = record;
4892 DECL_FIELD_CONTEXT (f_ftop) = record;
4893 DECL_FIELD_CONTEXT (f_goff) = record;
4894 DECL_FIELD_CONTEXT (f_foff) = record;
5d3f2bd5 4895
4fe12442
DL		 4896 TYPE_FIELDS (record) = f_ovfl;
4897 TREE_CHAIN (f_ovfl) = f_gtop;
4898 TREE_CHAIN (f_gtop) = f_ftop;
4899 TREE_CHAIN (f_ftop) = f_goff;
4900 TREE_CHAIN (f_goff) = f_foff;
5d3f2bd5 4901
4fe12442 4902 layout_type (record);
5d3f2bd5
RH		 4903 return record;
4904 }
4905 else
4906 return ptr_type_node;
4907}
4908
6c535c69 4909/* Implement va_start. stdarg_p is always 1. */
5d3f2bd5
RH		 4910
4911void
e5faf155 4912mips_va_start (valist, nextarg)
5d3f2bd5
RH		 4913 tree valist;
4914 rtx nextarg;
4915{
4d72536e 4916 const CUMULATIVE_ARGS *cum = &current_function_args_info;
5d3f2bd5 4917
8a381273
AO		 4918 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4919 since the stack is aligned for a pair of argument-passing slots,
4920 and the beginning of a variable argument list may be an odd slot,
4921 we have to decrease its alignment. */
4922 if (cfun && cfun->emit->regno_pointer_align)
4923 while (((current_function_pretend_args_size * BITS_PER_UNIT)
4924 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4925 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4926
5d3f2bd5
RH		 4927 if (mips_abi == ABI_EABI)
4928 {
4fe12442 4929 int gpr_save_area_size;
4fe12442 4930
4d72536e 4931 gpr_save_area_size
bb63e5a0 4932 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4d72536e
RS		 4933
4934 if (EABI_FLOAT_VARARGS_P)
5d3f2bd5 4935 {
7dac2f89
EC		 4936 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4937 tree ovfl, gtop, ftop, goff, foff;
4d72536e
RS		 4938 tree t;
4939 int fpr_offset;
4940 int fpr_save_area_size;
4fe12442 4941
4d72536e 4942 f_ovfl = TYPE_FIELDS (va_list_type_node);
4fe12442
DL		 4943 f_gtop = TREE_CHAIN (f_ovfl);
4944 f_ftop = TREE_CHAIN (f_gtop);
4945 f_goff = TREE_CHAIN (f_ftop);
4946 f_foff = TREE_CHAIN (f_goff);
4947
4948 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4949 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4950 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4951 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4952 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4953
4d72536e
RS		 4954 /* Emit code to initialize OVFL, which points to the next varargs
4955 stack argument. CUM->STACK_WORDS gives the number of stack
4956 words used by named arguments. */
4fe12442 4957 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4d72536e 4958 if (cum->stack_words > 0)
4fe12442 4959 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4d72536e 4960 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4fe12442
DL		 4961 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4962 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4963
4d72536e 4964 /* Emit code to initialize GTOP, the top of the GPR save area. */
4fe12442
DL		 4965 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4966 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4967 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4968
4d72536e
RS		 4969 /* Emit code to initialize FTOP, the top of the FPR save area.
4970 This address is gpr_save_area_bytes below GTOP, rounded
4971 down to the next fp-aligned boundary. */
4972 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4973 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4974 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4975 if (fpr_offset)
4976 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4977 build_int_2 (-fpr_offset, -1));
4978 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5d3f2bd5
RH		 4979 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4980
4d72536e
RS		 4981 /* Emit code to initialize GOFF, the offset from GTOP of the
4982 next GPR argument. */
4fe12442 4983 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4d72536e 4984 build_int_2 (gpr_save_area_size, 0));
5d3f2bd5
RH		 4985 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4986
4d72536e
RS		 4987 /* Likewise emit code to initialize FOFF, the offset from FTOP
4988 of the next FPR argument. */
4989 fpr_save_area_size
bb63e5a0 4990 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4fe12442 4991 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4d72536e 4992 build_int_2 (fpr_save_area_size, 0));
5d3f2bd5
RH		 4993 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4994 }
4995 else
4996 {
4fe12442 4997 /* Everything is in the GPR save area, or in the overflow
987ba558 4998 area which is contiguous with it. */
6c535c69 4999 nextarg = plus_constant (nextarg, -gpr_save_area_size);
e5faf155 5000 std_expand_builtin_va_start (valist, nextarg);
5d3f2bd5
RH		 5001 }
5002 }
5003 else
e5faf155 5004 std_expand_builtin_va_start (valist, nextarg);
5d3f2bd5 5005}
cafe096b
EC		 5006\f
5007/* Return true if it is possible to use left/right accesses for a
5008 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5009 returning true, update *OP, *LEFT and *RIGHT as follows:
5010
5011 *OP is a BLKmode reference to the whole field.
5012
5013 *LEFT is a QImode reference to the first byte if big endian or
5014 the last byte if little endian. This address can be used in the
5015 left-side instructions (lwl, swl, ldl, sdl).
5016
5017 *RIGHT is a QImode reference to the opposite end of the field and
5018 can be used in the parterning right-side instruction. */
5019
5020static bool
5021mips_get_unaligned_mem (op, width, bitpos, left, right)
5022 rtx *op, *left, *right;
5023 unsigned int width;
5024 int bitpos;
5025{
5026 rtx first, last;
5027
5028 /* Check that the operand really is a MEM. Not all the extv and
5029 extzv predicates are checked. */
5030 if (GET_CODE (*op) != MEM)
5031 return false;
5032
5033 /* Check that the size is valid. */
5034 if (width != 32 && (!TARGET_64BIT || width != 64))
5035 return false;
5036
5037 /* We can only access byte-aligned values. Since we are always passed
5038 a reference to the first byte of the field, it is not necessary to
5039 do anything with BITPOS after this check. */
5040 if (bitpos % BITS_PER_UNIT != 0)
5041 return false;
5042
5043 /* Reject aligned bitfields: we want to use a normal load or store
5044 instead of a left/right pair. */
5045 if (MEM_ALIGN (*op) >= width)
5046 return false;
5047
5048 /* Adjust *OP to refer to the whole field. This also has the effect
5049 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5050 *op = adjust_address (*op, BLKmode, 0);
5051 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
5052
5053 /* Get references to both ends of the field. We deliberately don't
5054 use the original QImode *OP for FIRST since the new BLKmode one
5055 might have a simpler address. */
5056 first = adjust_address (*op, QImode, 0);
5057 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
5058
5059 /* Allocate to LEFT and RIGHT according to endiannes. LEFT should
5060 be the upper word and RIGHT the lower word. */
5061 if (TARGET_BIG_ENDIAN)
5062 *left = first, *right = last;
5063 else
5064 *left = last, *right = first;
5065
5066 return true;
5067}
5068
5069
5070/* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
5071 Return true on success. We only handle cases where zero_extract is
5072 equivalent to sign_extract. */
5073
5074bool
5075mips_expand_unaligned_load (dest, src, width, bitpos)
5076 rtx dest, src;
5077 unsigned int width;
5078 int bitpos;
5079{
5080 rtx left, right;
5081
5082 /* If TARGET_64BIT, the destination of a 32-bit load will be a
5083 paradoxical word_mode subreg. This is the only case in which
5084 we allow the destination to be larger than the source. */
5085 if (GET_CODE (dest) == SUBREG
5086 && GET_MODE (dest) == DImode
5087 && SUBREG_BYTE (dest) == 0
5088 && GET_MODE (SUBREG_REG (dest)) == SImode)
5089 dest = SUBREG_REG (dest);
5090
5091 /* After the above adjustment, the destination must be the same
5092 width as the source. */
5093 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
5094 return false;
5095
5096 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
5097 return false;
5098
5099 if (GET_MODE (dest) == DImode)
5100 {
5101 emit_insn (gen_mov_ldl (dest, src, left));
5102 emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
5103 right, copy_rtx (dest)));
5104 }
5105 else
5106 {
5107 emit_insn (gen_mov_lwl (dest, src, left));
5108 emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
5109 right, copy_rtx (dest)));
5110 }
5111 return true;
5112}
5113
5114
5115/* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
5116 true on success. */
5117
5118bool
5119mips_expand_unaligned_store (dest, src, width, bitpos)
5120 rtx dest, src;
5121 unsigned int width;
5122 int bitpos;
5123{
5124 rtx left, right;
5125
5126 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
5127 return false;
5128
5129 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
5d3f2bd5 5130
cafe096b
EC		 5131 if (GET_MODE (src) == DImode)
5132 {
5133 emit_insn (gen_mov_sdl (dest, src, left));
5134 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
5135 }
5136 else
5137 {
5138 emit_insn (gen_mov_swl (dest, src, left));
5139 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
5140 }
5141 return true;
5142}
5143\f
5d3f2bd5
RH		 5144/* Implement va_arg. */
5145
5146rtx
5147mips_va_arg (valist, type)
5148 tree valist, type;
5149{
5150 HOST_WIDE_INT size, rsize;
5151 rtx addr_rtx;
5152 tree t;
5153
5154 size = int_size_in_bytes (type);
5155 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5156
5157 if (mips_abi == ABI_EABI)
5158 {
4d72536e
RS		 5159 bool indirect;
5160 rtx r;
5d3f2bd5
RH		 5161
5162 indirect
5163 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4d72536e 5164
5d3f2bd5 5165 if (indirect)
dd193c79
BS		 5166 {
5167 size = POINTER_SIZE / BITS_PER_UNIT;
5168 rsize = UNITS_PER_WORD;
5169 }
5d3f2bd5
RH		 5170
5171 addr_rtx = gen_reg_rtx (Pmode);
5172
4d72536e 5173 if (!EABI_FLOAT_VARARGS_P)
5d3f2bd5 5174 {
4d72536e 5175 /* Case of all args in a merged stack. No need to check bounds,
987ba558 5176 just advance valist along the stack. */
5d3f2bd5 5177
4fe12442 5178 tree gpr = valist;
4d72536e
RS		 5179 if (!indirect
5180 && !TARGET_64BIT
4fe12442 5181 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
5d3f2bd5 5182 {
4d72536e
RS		 5183 /* Align the pointer using: ap = (ap + align - 1) & -align,
5184 where align is 2 * UNITS_PER_WORD. */
4fe12442 5185 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4d72536e 5186 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
7dac2f89 5187 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4d72536e 5188 build_int_2 (-2 * UNITS_PER_WORD, -1));
4fe12442 5189 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
5d3f2bd5 5190 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4fe12442 5191 }
5d3f2bd5 5192
4d72536e
RS		 5193 /* Emit code to set addr_rtx to the valist, and postincrement
5194 the valist by the size of the argument, rounded up to the
5195 next word. */
5196 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
5197 size_int (rsize));
5198 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5199 if (r != addr_rtx)
4fe12442 5200 emit_move_insn (addr_rtx, r);
5d3f2bd5 5201
4d72536e
RS		 5202 /* Flush the POSTINCREMENT. */
5203 emit_queue();
5d3f2bd5 5204 }
4d72536e
RS		 5205 else
5206 {
5207 /* Not a simple merged stack. */
5d3f2bd5 5208
4d72536e
RS		 5209 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5210 tree ovfl, top, off;
5211 rtx lab_over = NULL_RTX, lab_false;
bf6d4777 5212 HOST_WIDE_INT osize;
4fe12442 5213
4d72536e
RS		 5214 f_ovfl = TYPE_FIELDS (va_list_type_node);
5215 f_gtop = TREE_CHAIN (f_ovfl);
5216 f_ftop = TREE_CHAIN (f_gtop);
5217 f_goff = TREE_CHAIN (f_ftop);
5218 f_foff = TREE_CHAIN (f_goff);
4fe12442 5219
4d72536e
RS		 5220 /* We maintain separate pointers and offsets for floating-point
5221 and integer arguments, but we need similar code in both cases.
5222 Let:
4fe12442 5223
4d72536e
RS		 5224 TOP be the top of the register save area;
5225 OFF be the offset from TOP of the next register;
5226 ADDR_RTX be the address of the argument; and
bf6d4777
RS		 5227 RSIZE be the number of bytes used to store the argument
5228 when it's in the register save area
5229 OSIZE be the number of bytes used to store it when it's
5230 in the stack overflow area
5231 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4fe12442 5232
4d72536e 5233 The code we want is:
4fe12442 5234
4d72536e
RS		 5235 1: off &= -rsize; // round down
5236 2: if (off != 0)
5237 3: {
5238 4: addr_rtx = top - off;
5239 5: off -= rsize;
5240 6: }
5241 7: else
5242 8: {
bf6d4777
RS		 5243 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
5244 10: addr_rtx = ovfl + PADDING;
5245 11: ovfl += osize;
5246 14: }
4fe12442 5247
4d72536e 5248 [1] and [9] can sometimes be optimized away. */
4fe12442 5249
4d72536e
RS		 5250 lab_false = gen_label_rtx ();
5251 lab_over = gen_label_rtx ();
4fe12442 5252
4d72536e 5253 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
7dac2f89 5254
4d72536e 5255 if (TREE_CODE (type) == REAL_TYPE)
4fe12442 5256 {
4d72536e
RS		 5257 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
5258 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
1e7a71c1 5259
4d72536e 5260 /* When floating-point registers are saved to the stack,
8a381273 5261 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4d72536e 5262 of the float's precision. */
8a381273 5263 rsize = UNITS_PER_HWFPVALUE;
4d72536e
RS		 5264 }
5265 else
4fe12442 5266 {
4d72536e
RS		 5267 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
5268 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
5269 if (rsize > UNITS_PER_WORD)
5270 {
5271 /* [1] Emit code for: off &= -rsize. */
5272 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
5273 build_int_2 (-rsize, -1));
5274 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
5275 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5276 }
4fe12442 5277 }
bf6d4777
RS		 5278 /* Every overflow argument must take up at least UNITS_PER_WORD
5279 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
5280 than that, such as in the combination -mgp64 -msingle-float
5281 -fshort-double. Doubles passed in registers will then take
8a381273 5282 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
bf6d4777
RS		 5283 take up UNITS_PER_WORD bytes. */
5284 osize = MAX (rsize, UNITS_PER_WORD);
5d3f2bd5 5285
4d72536e
RS		 5286 /* [2] Emit code to branch if off == 0. */
5287 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
5288 EXPAND_NORMAL);
5289 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
d43e0b7d 5290 1, lab_false);
4fe12442 5291
4d72536e
RS		 5292 /* [4] Emit code for: addr_rtx = top - off. */
5293 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
5294 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5295 if (r != addr_rtx)
5296 emit_move_insn (addr_rtx, r);
4fe12442 5297
4d72536e
RS		 5298 /* [5] Emit code for: off -= rsize. */
5299 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
5300 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
5301 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4fe12442 5302
4d72536e
RS		 5303 /* [7] Emit code to jump over the else clause, then the label
5304 that starts it. */
5305 emit_queue();
5306 emit_jump (lab_over);
5307 emit_barrier ();
5308 emit_label (lab_false);
a85cd407 5309
bf6d4777 5310 if (osize > UNITS_PER_WORD)
4d72536e 5311 {
bf6d4777 5312 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4d72536e 5313 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
bf6d4777 5314 build_int_2 (osize - 1, 0));
4d72536e 5315 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
bf6d4777 5316 build_int_2 (-osize, -1));
4d72536e
RS		 5317 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5318 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4fe12442 5319 }
a85cd407 5320
4d72536e 5321 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
bf6d4777
RS		 5322 post-increment ovfl by osize. On big-endian machines,
5323 the argument has OSIZE - RSIZE bytes of leading padding. */
4d72536e 5324 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
bf6d4777
RS		 5325 size_int (osize));
5326 if (BYTES_BIG_ENDIAN && osize > rsize)
5327 t = build (PLUS_EXPR, TREE_TYPE (t), t,
5328 build_int_2 (osize - rsize, 0));
4d72536e
RS		 5329 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5330 if (r != addr_rtx)
5331 emit_move_insn (addr_rtx, r);
5332
5333 emit_queue();
5334 emit_label (lab_over);
5335 }
83282119
RS		 5336 if (BYTES_BIG_ENDIAN && rsize != size)
5337 addr_rtx = plus_constant (addr_rtx, rsize - size);
4d72536e
RS		 5338 if (indirect)
5339 {
5340 addr_rtx = force_reg (Pmode, addr_rtx);
5341 r = gen_rtx_MEM (Pmode, addr_rtx);
5342 set_mem_alias_set (r, get_varargs_alias_set ());
5343 emit_move_insn (addr_rtx, r);
5d3f2bd5 5344 }
4d72536e 5345 return addr_rtx;
5d3f2bd5
RH		 5346 }
5347 else
5348 {
987ba558 5349 /* Not EABI. */
5d3f2bd5
RH		 5350 int align;
5351
7dac2f89 5352 /* ??? The original va-mips.h did always align, despite the fact
5d3f2bd5
RH		 5353 that alignments <= UNITS_PER_WORD are preserved by the va_arg
5354 increment mechanism. */
5355
8a381273
AO		 5356 if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
5357 && TYPE_ALIGN (type) > 64)
5358 align = 16;
5359 else if (TARGET_64BIT)
5d3f2bd5
RH		 5360 align = 8;
5361 else if (TYPE_ALIGN (type) > 32)
5362 align = 8;
5363 else
5364 align = 4;
7dac2f89 5365
5d3f2bd5
RH		 5366 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5367 build_int_2 (align - 1, 0));
5368 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
5369 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5d3f2bd5
RH		 5370 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5371
5372 /* Everything past the alignment is standard. */
5373 return std_expand_builtin_va_arg (valist, type);
5374 }
5375}
5376\f
cee98a59
MM		 5377/* Abort after printing out a specific insn. */
5378
e2fe6aba 5379static void
cee98a59
MM		 5380abort_with_insn (insn, reason)
5381 rtx insn;
e2fe6aba 5382 const char *reason;
cee98a59
MM		 5383{
5384 error (reason);
5385 debug_rtx (insn);
5386 abort ();
5387}
cee98a59 5388\f
a27fb29b
RS		 5389/* Set up globals to generate code for the ISA or processor
5390 described by INFO. */
5391
5392static void
5393mips_set_architecture (info)
5394 const struct mips_cpu_info *info;
5395{
5396 if (info != 0)
5397 {
5398 mips_arch_info = info;
5399 mips_arch = info->cpu;
5400 mips_isa = info->isa;
5401 }
5402}
5403
5404
5405/* Likewise for tuning. */
5406
5407static void
5408mips_set_tune (info)
5409 const struct mips_cpu_info *info;
5410{
5411 if (info != 0)
5412 {
5413 mips_tune_info = info;
5414 mips_tune = info->cpu;
5415 }
5416}
5417
5418
cee98a59
MM		 5419/* Set up the threshold for data to go into the small data area, instead
5420 of the normal data area, and detect any conflicts in the switches. */
5421
5422void
5423override_options ()
5424{
a27fb29b
RS		 5425 int i, start, regno;
5426 enum machine_mode mode;
cee98a59 5427
f5963e61 5428 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
cee98a59 5429
147255d8
JW		 5430 if (mips_section_threshold <= 0)
5431 target_flags &= ~MASK_GPOPT;
5432 else if (optimize)
5433 target_flags |= MASK_GPOPT;
5434
a27fb29b
RS		 5435 /* Interpret -mabi. */
5436 mips_abi = MIPS_ABI_DEFAULT;
5437 if (mips_abi_string != 0)
5438 {
5439 if (strcmp (mips_abi_string, "32") == 0)
5440 mips_abi = ABI_32;
5441 else if (strcmp (mips_abi_string, "o64") == 0)
5442 mips_abi = ABI_O64;
5443 else if (strcmp (mips_abi_string, "n32") == 0)
5444 mips_abi = ABI_N32;
5445 else if (strcmp (mips_abi_string, "64") == 0)
5446 mips_abi = ABI_64;
5447 else if (strcmp (mips_abi_string, "eabi") == 0)
5448 mips_abi = ABI_EABI;
a27fb29b
RS		 5449 else
5450 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
5451 }
5452
5453 /* The following code determines the architecture and register size.
5454 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5455 The GAS and GCC code should be kept in sync as much as possible. */
147255d8 5456
a27fb29b
RS		 5457 if (mips_arch_string != 0)
5458 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
5ae590d7 5459
a27fb29b
RS		 5460 if (mips_tune_string != 0)
5461 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
5462
5463 if (mips_isa_string != 0)
147255d8 5464 {
a27fb29b 5465 /* Handle -mipsN. */
2d2a50c3
CD		 5466
5467 if (strcmp (mips_isa_string, "16") == 0)
2bcb2ab3 5468 {
a27fb29b
RS		 5469 /* -mips16 specifies an ASE rather than a processor, so don't
5470 change mips_arch here. -mno-mips16 overrides -mips16. */
2bcb2ab3 5471 if (mips_no_mips16_string == NULL)
a27fb29b 5472 target_flags |= MASK_MIPS16;
2bcb2ab3 5473 }
2d2a50c3 5474 else
147255d8 5475 {
2d2a50c3
CD		 5476 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
5477 const struct mips_cpu_info *isa_info;
5478
5479 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
5480 free (whole_isa_str);
5481
a27fb29b
RS		 5482 /* -march takes precedence over -mipsN, since it is more descriptive.
5483 There's no harm in specifying both as long as the ISA levels
5484 are the same. */
2d2a50c3
CD		 5485 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
5486 error ("-mips%s conflicts with the other architecture options, which specify a MIPS%d processor",
5487 mips_isa_string, mips_isa);
5488
5489 /* Set architecture based on the given option. */
5490 mips_set_architecture (isa_info);
0e5a4ad8 5491 }
ade6c319 5492 }
f5963e61 5493
a27fb29b 5494 if (mips_arch_info == 0)
ade6c319 5495 {
a27fb29b
RS		 5496#ifdef MIPS_CPU_STRING_DEFAULT
5497 mips_set_architecture (mips_parse_cpu ("default CPU",
5498 MIPS_CPU_STRING_DEFAULT));
ade6c319 5499#else
a27fb29b 5500 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
ade6c319 5501#endif
a27fb29b 5502 }
ade6c319 5503
a27fb29b
RS		 5504 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
5505 error ("-march=%s is not compatible with the selected ABI",
5506 mips_arch_info->name);
1bd9166e 5507
a27fb29b
RS		 5508 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5509 if (mips_tune_info == 0)
5510 mips_set_tune (mips_arch_info);
7dac2f89 5511
a27fb29b 5512 if ((target_flags_explicit & MASK_64BIT) != 0)
7dac2f89 5513 {
a27fb29b
RS		 5514 /* The user specified the size of the integer registers. Make sure
5515 it agrees with the ABI and ISA. */
5516 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5517 error ("-mgp64 used with a 32-bit processor");
5518 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5519 error ("-mgp32 used with a 64-bit ABI");
5520 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5521 error ("-mgp64 used with a 32-bit ABI");
cee98a59 5522 }
cee98a59
MM		 5523 else
5524 {
a27fb29b
RS		 5525 /* Infer the integer register size from the ABI and processor.
5526 Restrict ourselves to 32-bit registers if that's all the
5527 processor has, or if the ABI cannot handle 64-bit registers. */
5528 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5529 target_flags &= ~MASK_64BIT;
7dac2f89 5530 else
a27fb29b
RS		 5531 target_flags |= MASK_64BIT;
5532 }
cee98a59 5533
a27fb29b
RS		 5534 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5535 {
5536 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5537 only one right answer here. */
5538 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5539 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5540 else if (!TARGET_64BIT && TARGET_FLOAT64)
5541 error ("unsupported combination: %s", "-mgp32 -mfp64");
5542 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5543 error ("unsupported combination: %s", "-mfp64 -msingle-float");
7dac2f89
EC		 5544 }
5545 else
5546 {
a27fb29b
RS		 5547 /* -msingle-float selects 32-bit float registers. Otherwise the
5548 float registers should be the same size as the integer ones. */
5549 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5550 target_flags |= MASK_FLOAT64;
5551 else
5552 target_flags &= ~MASK_FLOAT64;
cee98a59
MM		 5553 }
5554
a27fb29b 5555 /* End of code shared with GAS. */
f8151871 5556
a27fb29b
RS		 5557 if ((target_flags_explicit & MASK_LONG64) == 0)
5558 {
5559 /* If no type size setting options (-mlong64,-mint64,-mlong32)
5560 were used, then set the type sizes. In the EABI in 64 bit mode,
5561 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
5562 ABI. */
5563 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5564 target_flags |= MASK_LONG64;
5565 else
5566 target_flags &= ~MASK_LONG64;
147255d8 5567 }
cee98a59 5568
60bc2b4b
RS		 5569 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5570 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
5571 {
5572 /* For some configurations, it is useful to have -march control
5573 the default setting of MASK_SOFT_FLOAT. */
5574 switch ((int) mips_arch)
5575 {
5576 case PROCESSOR_R4100:
5577 case PROCESSOR_R4120:
5578 target_flags |= MASK_SOFT_FLOAT;
5579 break;
5580
5581 default:
5582 target_flags &= ~MASK_SOFT_FLOAT;
5583 break;
5584 }
5585 }
5586
a53f72db 5587 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
33563487
JW		 5588 flag_pcc_struct_return = 0;
5589
af34e51e
CD		 5590 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
5591 {
5592 /* If neither -mbranch-likely nor -mno-branch-likely was given
5593 on the command line, set MASK_BRANCHLIKELY based on the target
5594 architecture.
5595
5596 By default, we enable use of Branch Likely instructions on
5597 all architectures which support them except for MIPS32 and MIPS64
5598 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
5599 implement them).
5600
5601 The MIPS32 and MIPS64 architecture specifications say "Software
5602 is strongly encouraged to avoid use of Branch Likely
5603 instructions, as they will be removed from a future revision
5604 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5605 issue those instructions unless instructed to do so by
5606 -mbranch-likely. */
2d2a50c3 5607 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
af34e51e
CD		 5608 target_flags |= MASK_BRANCHLIKELY;
5609 else
5610 target_flags &= ~MASK_BRANCHLIKELY;
5611 }
5612 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
5613 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
5614
508a48d1
JW		 5615 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5616 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5617 /* ??? -non_shared turns off pic code generation, but this is not
5618 implemented. */
ffa9d0b1 5619 if (TARGET_ABICALLS)
508a48d1
JW		 5620 {
5621 mips_abicalls = MIPS_ABICALLS_YES;
cafe096b
EC		 5622 if (flag_pic == 0)
5623 flag_pic = 1;
508a48d1
JW		 5624 if (mips_section_threshold > 0)
5625 warning ("-G is incompatible with PIC code which is the default");
5626 }
ffa9d0b1 5627 else
1d6ce736 5628 mips_abicalls = MIPS_ABICALLS_NO;
ffa9d0b1 5629
e0bfcea5
ILT		 5630 /* -membedded-pic is a form of PIC code suitable for embedded
5631 systems. All calls are made using PC relative addressing, and
5632 all data is addressed using the $gp register. This requires gas,
5633 which does most of the work, and GNU ld, which automatically
5634 expands PC relative calls which are out of range into a longer
5635 instruction sequence. All gcc really does differently is
5636 generate a different sequence for a switch. */
5637 if (TARGET_EMBEDDED_PIC)
5638 {
5639 flag_pic = 1;
5640 if (TARGET_ABICALLS)
5641 warning ("-membedded-pic and -mabicalls are incompatible");
f5963e61 5642
e0bfcea5
ILT		 5643 if (g_switch_set)
5644 warning ("-G and -membedded-pic are incompatible");
f5963e61 5645
e0bfcea5
ILT		 5646 /* Setting mips_section_threshold is not required, because gas
5647 will force everything to be GP addressable anyhow, but
5648 setting it will cause gcc to make better estimates of the
5649 number of instructions required to access a particular data
5650 item. */
5651 mips_section_threshold = 0x7fffffff;
5652 }
5653
cafe096b
EC		 5654 /* mips_split_addresses is a half-way house between explicit
5655 relocations and the traditional assembler macros. It can
5656 split absolute 32-bit symbolic constants into a high/lo_sum
5657 pair but uses macros for other sorts of access.
5658
5659 Like explicit relocation support for REL targets, it relies
5660 on GNU extensions in the assembler and the linker.
5661
5662 Although this code should work for -O0, it has traditionally
5663 been treated as an optimization. */
5664 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
5665 && optimize && !flag_pic
5666 && !ABI_HAS_64BIT_SYMBOLS)
910628b8
JW		 5667 mips_split_addresses = 1;
5668 else
5669 mips_split_addresses = 0;
5670
cafe096b
EC		 5671 /* -mexplicit-relocs doesn't yet support non-PIC n64. We don't know
5672 how to generate %highest/%higher/%hi/%lo sequences. */
5673 if (mips_abi == ABI_64 && !TARGET_ABICALLS)
5674 {
5675 if ((target_flags_explicit & target_flags & MASK_EXPLICIT_RELOCS) != 0)
5676 sorry ("non-PIC n64 with explicit relocations");
5677 target_flags &= ~MASK_EXPLICIT_RELOCS;
5678 }
5679
cee98a59 5680 /* -mrnames says to use the MIPS software convention for register
147255d8 5681 names instead of the hardware names (ie, $a0 instead of $4).
cee98a59
MM		 5682 We do this by switching the names in mips_reg_names, which the
5683 reg_names points into via the REGISTER_NAMES macro. */
5684
5685 if (TARGET_NAME_REGS)
4e135bdd 5686 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
cee98a59 5687
2bcb2ab3
GK		 5688 /* When compiling for the mips16, we can not use floating point. We
5689 record the original hard float value in mips16_hard_float. */
5690 if (TARGET_MIPS16)
5691 {
5692 if (TARGET_SOFT_FLOAT)
5693 mips16_hard_float = 0;
5694 else
5695 mips16_hard_float = 1;
5696 target_flags |= MASK_SOFT_FLOAT;
5697
5698 /* Don't run the scheduler before reload, since it tends to
5699 increase register pressure. */
5700 flag_schedule_insns = 0;
cafe096b
EC		 5701
5702 /* Silently disable -mexplicit-relocs since it doesn't apply
5703 to mips16 code. Even so, it would overly pedantic to warn
5704 about "-mips16 -mexplicit-relocs", especially given that
5705 we use a %gprel() operator. */
5706 target_flags &= ~MASK_EXPLICIT_RELOCS;
2bcb2ab3
GK		 5707 }
5708
5709 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5710 to avoid using up another bit in target_flags. */
5711 if (mips_entry_string != NULL)
5712 {
5713 if (*mips_entry_string != '\0')
c725bd79 5714 error ("invalid option `entry%s'", mips_entry_string);
2bcb2ab3
GK		 5715
5716 if (! TARGET_MIPS16)
5717 warning ("-mentry is only meaningful with -mips-16");
5718 else
5719 mips_entry = 1;
5720 }
5721
5722 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5723 attributes can access it. */
5724 if (TARGET_MIPS16)
5725 mips16 = 1;
5726 else
5727 mips16 = 0;
5728
fe0002ee
AO		 5729 real_format_for_mode[SFmode - QFmode] = &mips_single_format;
5730 real_format_for_mode[DFmode - QFmode] = &mips_double_format;
3bd6d4c4
AO		 5731#ifdef MIPS_TFMODE_FORMAT
5732 real_format_for_mode[TFmode - QFmode] = &MIPS_TFMODE_FORMAT;
fe0002ee
AO		 5733#else
5734 real_format_for_mode[TFmode - QFmode] = &mips_quad_format;
3bd6d4c4 5735#endif
cafe096b 5736
f5963e61
JL		 5737 mips_print_operand_punct['?'] = 1;
5738 mips_print_operand_punct['#'] = 1;
5739 mips_print_operand_punct['&'] = 1;
5740 mips_print_operand_punct['!'] = 1;
5741 mips_print_operand_punct['*'] = 1;
5742 mips_print_operand_punct['@'] = 1;
5743 mips_print_operand_punct['.'] = 1;
5744 mips_print_operand_punct['('] = 1;
5745 mips_print_operand_punct[')'] = 1;
5746 mips_print_operand_punct['['] = 1;
5747 mips_print_operand_punct[']'] = 1;
5748 mips_print_operand_punct['<'] = 1;
5749 mips_print_operand_punct['>'] = 1;
5750 mips_print_operand_punct['{'] = 1;
5751 mips_print_operand_punct['}'] = 1;
5752 mips_print_operand_punct['^'] = 1;
5753 mips_print_operand_punct['$'] = 1;
5754 mips_print_operand_punct['+'] = 1;
efa3896a 5755 mips_print_operand_punct['~'] = 1;
cee98a59 5756
2bcb2ab3
GK		 5757 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5758 mips_char_to_class['e'] = M16_NA_REGS;
5759 mips_char_to_class['t'] = T_REG;
f5963e61 5760 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
cee98a59
MM		 5761 mips_char_to_class['h'] = HI_REG;
5762 mips_char_to_class['l'] = LO_REG;
225b8835 5763 mips_char_to_class['a'] = HILO_REG;
cee98a59 5764 mips_char_to_class['x'] = MD_REGS;
225b8835 5765 mips_char_to_class['b'] = ALL_REGS;
cafe096b
EC		 5766 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
5767 TARGET_MIPS16 ? M16_NA_REGS :
5768 GR_REGS);
5769 mips_char_to_class['e'] = LEA_REGS;
5770 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
cee98a59 5771 mips_char_to_class['y'] = GR_REGS;
34b650b3 5772 mips_char_to_class['z'] = ST_REGS;
d604bca3
MH		 5773 mips_char_to_class['B'] = COP0_REGS;
5774 mips_char_to_class['C'] = COP2_REGS;
5775 mips_char_to_class['D'] = COP3_REGS;
cee98a59
MM		 5776
5777 /* Set up array to map GCC register number to debug register number.
5778 Ignore the special purpose register numbers. */
5779
5780 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5781 mips_dbx_regno[i] = -1;
5782
5783 start = GP_DBX_FIRST - GP_REG_FIRST;
5784 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5785 mips_dbx_regno[i] = i + start;
5786
5787 start = FP_DBX_FIRST - FP_REG_FIRST;
5788 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5789 mips_dbx_regno[i] = i + start;
5790
77d4f3a4
KB		 5791 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5792 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5793
cee98a59
MM		 5794 /* Set up array giving whether a given register can hold a given mode.
5795 At present, restrict ints from being in FP registers, because reload
5796 is a little enthusiastic about storing extra values in FP registers,
5797 and this is not good for things like OS kernels. Also, due to the
c831afd5 5798 mandatory delay, it is as fast to load from cached memory as to move
cee98a59
MM		 5799 from the FP register. */
5800
5801 for (mode = VOIDmode;
5802 mode != MAX_MACHINE_MODE;
f5963e61 5803 mode = (enum machine_mode) ((int)mode + 1))
cee98a59
MM		 5804 {
5805 register int size = GET_MODE_SIZE (mode);
5806 register enum mode_class class = GET_MODE_CLASS (mode);
5807
5808 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5809 {
34b650b3
MM		 5810 register int temp;
5811
b8eb88d0
ILT		 5812 if (mode == CCmode)
5813 {
76ee8042 5814 if (! ISA_HAS_8CC)
b8eb88d0
ILT		 5815 temp = (regno == FPSW_REGNUM);
5816 else
f5963e61 5817 temp = (ST_REG_P (regno) || GP_REG_P (regno)
b8eb88d0
ILT		 5818 || FP_REG_P (regno));
5819 }
cee98a59 5820
34b650b3 5821 else if (GP_REG_P (regno))
f5963e61 5822 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
cee98a59
MM		 5823
5824 else if (FP_REG_P (regno))
cafe096b 5825 temp = ((regno % FP_INC) == 0)
8214bf98
RS		 5826 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
5827 && size <= UNITS_PER_FPVALUE)
5828 /* Allow integer modes that fit into a single
5829 register. We need to put integers into FPRs
5830 when using instructions like cvt and trunc. */
d12b8c85
RS		 5831 || (class == MODE_INT && size <= UNITS_PER_FPREG)
5832 /* Allow TFmode for CCmode reloads. */
cafe096b 5833 || (ISA_HAS_8CC && mode == TFmode));
cee98a59
MM		 5834
5835 else if (MD_REG_P (regno))
1cfb3048
RK		 5836 temp = (class == MODE_INT
5837 && (size <= UNITS_PER_WORD
f5963e61
JL		 5838 || (regno == MD_REG_FIRST
5839 && size == 2 * UNITS_PER_WORD)));
cee98a59 5840
d604bca3
MH		 5841 else if (ALL_COP_REG_P (regno))
5842 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
34b650b3 5843 else
f5963e61 5844 temp = 0;
cee98a59
MM		 5845
5846 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5847 }
5848 }
bfed8dac 5849
45cc4c09
JW		 5850 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5851 initialized yet, so we can't use that here. */
5852 gpr_mode = TARGET_64BIT ? DImode : SImode;
efa3896a
GK		 5853
5854 /* Provide default values for align_* for 64-bit targets. */
ea64cab4 5855 if (TARGET_64BIT && !TARGET_MIPS16)
efa3896a 5856 {
7dac2f89 5857 if (align_loops == 0)
efa3896a 5858 align_loops = 8;
7dac2f89 5859 if (align_jumps == 0)
efa3896a 5860 align_jumps = 8;
7dac2f89 5861 if (align_functions == 0)
efa3896a
GK		 5862 align_functions = 8;
5863 }
d07d525a 5864
e2500fed 5865 /* Function to allocate machine-dependent function status. */
c8d1b2b7 5866 init_machine_status = &mips_init_machine_status;
cafe096b
EC		 5867
5868 /* Create a unique alias set for GOT references. */
5869 mips_got_alias_set = new_alias_set ();
c8d1b2b7
AO		 5870}
5871
ac8ab9fe
RS		 5872/* Implement CONDITIONAL_REGISTER_USAGE. */
5873
5874void
5875mips_conditional_register_usage ()
5876{
5877 if (!TARGET_HARD_FLOAT)
5878 {
5879 int regno;
5880
5881 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5882 fixed_regs[regno] = call_used_regs[regno] = 1;
5883 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5884 fixed_regs[regno] = call_used_regs[regno] = 1;
5885 }
5886 else if (! ISA_HAS_8CC)
5887 {
5888 int regno;
5889
5890 /* We only have a single condition code register. We
5891 implement this by hiding all the condition code registers,
5892 and generating RTL that refers directly to ST_REG_FIRST. */
5893 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5894 fixed_regs[regno] = call_used_regs[regno] = 1;
5895 }
5896 /* In mips16 mode, we permit the $t temporary registers to be used
5897 for reload. We prohibit the unused $s registers, since they
5898 are caller saved, and saving them via a mips16 register would
5899 probably waste more time than just reloading the value. */
5900 if (TARGET_MIPS16)
5901 {
5902 fixed_regs[18] = call_used_regs[18] = 1;
5903 fixed_regs[19] = call_used_regs[19] = 1;
5904 fixed_regs[20] = call_used_regs[20] = 1;
5905 fixed_regs[21] = call_used_regs[21] = 1;
5906 fixed_regs[22] = call_used_regs[22] = 1;
5907 fixed_regs[23] = call_used_regs[23] = 1;
5908 fixed_regs[26] = call_used_regs[26] = 1;
5909 fixed_regs[27] = call_used_regs[27] = 1;
5910 fixed_regs[30] = call_used_regs[30] = 1;
5911 }
5912 /* fp20-23 are now caller saved. */
5913 if (mips_abi == ABI_64)
5914 {
5915 int regno;
5916 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5917 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5918 }
5919 /* odd registers from fp21 to fp31 are now caller saved. */
cafe096b 5920 if (mips_abi == ABI_N32)
ac8ab9fe
RS		 5921 {
5922 int regno;
5923 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5924 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5925 }
5926}
5927
c8d1b2b7 5928/* Allocate a chunk of memory for per-function machine-dependent data. */
e2500fed
GK		 5929static struct machine_function *
5930mips_init_machine_status ()
c8d1b2b7 5931{
e2500fed
GK		 5932 return ((struct machine_function *)
5933 ggc_alloc_cleared (sizeof (struct machine_function)));
cee98a59
MM		 5934}
5935
2bcb2ab3
GK		 5936/* On the mips16, we want to allocate $24 (T_REG) before other
5937 registers for instructions for which it is possible. This helps
5938 avoid shuffling registers around in order to set up for an xor,
5939 encouraging the compiler to use a cmp instead. */
5940
5941void
5942mips_order_regs_for_local_alloc ()
5943{
5944 register int i;
5945
5946 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5947 reg_alloc_order[i] = i;
5948
5949 if (TARGET_MIPS16)
5950 {
5951 /* It really doesn't matter where we put register 0, since it is
5952 a fixed register anyhow. */
5953 reg_alloc_order[0] = 24;
5954 reg_alloc_order[24] = 0;
5955 }
5956}
5957
cee98a59 5958\f
f5963e61
JL		 5959/* The MIPS debug format wants all automatic variables and arguments
5960 to be in terms of the virtual frame pointer (stack pointer before
5961 any adjustment in the function), while the MIPS 3.0 linker wants
5962 the frame pointer to be the stack pointer after the initial
5963 adjustment. So, we do the adjustment here. The arg pointer (which
5964 is eliminated) points to the virtual frame pointer, while the frame
5965 pointer (which may be eliminated) points to the stack pointer after
5966 the initial adjustments. */
5967
5968HOST_WIDE_INT
cee98a59
MM		 5969mips_debugger_offset (addr, offset)
5970 rtx addr;
f5963e61 5971 HOST_WIDE_INT offset;
cee98a59 5972{
c831afd5 5973 rtx offset2 = const0_rtx;
cee98a59
MM		 5974 rtx reg = eliminate_constant_term (addr, &offset2);
5975
f5963e61 5976 if (offset == 0)
c831afd5 5977 offset = INTVAL (offset2);
cee98a59 5978
2bcb2ab3
GK		 5979 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5980 || reg == hard_frame_pointer_rtx)
c831afd5 5981 {
b2471838 5982 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
f5963e61 5983 ? compute_frame_size (get_frame_size ())
b2471838 5984 : cfun->machine->frame.total_size;
c831afd5 5985
a50f2a09
AC		 5986 /* MIPS16 frame is smaller */
5987 if (frame_pointer_needed && TARGET_MIPS16)
5988 frame_size -= current_function_outgoing_args_size;
5989
c831afd5
MM		 5990 offset = offset - frame_size;
5991 }
f5963e61 5992
acc15f57
RS		 5993 /* sdbout_parms does not want this to crash for unrecognized cases. */
5994#if 0
ab78d4a8 5995 else if (reg != arg_pointer_rtx)
c725bd79 5996 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
acc15f57 5997#endif
cee98a59
MM		 5998
5999 return offset;
6000}
6001\f
6002/* A C compound statement to output to stdio stream STREAM the
6003 assembler syntax for an instruction operand X. X is an RTL
6004 expression.
6005
6006 CODE is a value that can be used to specify one of several ways
6007 of printing the operand. It is used when identical operands
6008 must be printed differently depending on the context. CODE
6009 comes from the `%' specification that was used to request
6010 printing of the operand. If the specification was just `%DIGIT'
6011 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
6012 is the ASCII code for LTR.
6013
6014 If X is a register, this macro should print the register's name.
6015 The names can be found in an array `reg_names' whose type is
6016 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
6017
6018 When the machine description has a specification `%PUNCT' (a `%'
6019 followed by a punctuation character), this macro is called with
6020 a null pointer for X and the punctuation character for CODE.
6021
6022 The MIPS specific codes are:
6023
6024 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
6025 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5b0f0db6 6026 'h' X is HIGH, prints %hi(X),
cee98a59
MM		 6027 'd' output integer constant in decimal,
6028 'z' if the operand is 0, use $0 instead of normal operand.
51c6b247 6029 'D' print second part of double-word register or memory operand.
cee98a59
MM		 6030 'L' print low-order register of double-word register operand.
6031 'M' print high-order register of double-word register operand.
6032 'C' print part of opcode for a branch condition.
0ff83799 6033 'F' print part of opcode for a floating-point branch condition.
cee98a59 6034 'N' print part of opcode for a branch condition, inverted.
0ff83799 6035 'W' print part of opcode for a floating-point branch condition, inverted.
e0bfcea5 6036 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
33563487
JW		 6037 'B' print 'z' for EQ, 'n' for NE
6038 'b' print 'n' for EQ, 'z' for NE
6039 'T' print 'f' for EQ, 't' for NE
6040 't' print 't' for EQ, 'f' for NE
b8eb88d0 6041 'Z' print register and a comma, but print nothing for $fcc0
cafe096b 6042 'R' print the reloc associated with LO_SUM
cee98a59
MM		 6043 '(' Turn on .set noreorder
6044 ')' Turn on .set reorder
6045 '[' Turn on .set noat
6046 ']' Turn on .set at
6047 '<' Turn on .set nomacro
6048 '>' Turn on .set macro
6049 '{' Turn on .set volatile (not GAS)
6050 '}' Turn on .set novolatile (not GAS)
6051 '&' Turn on .set noreorder if filling delay slots
6052 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
6053 '!' Turn on .set nomacro if filling delay slots
6054 '#' Print nop if in a .set noreorder section.
6055 '?' Print 'l' if we are to use a branch likely instead of normal branch.
6056 '@' Print the name of the assembler temporary register (at or $1).
ffa9d0b1 6057 '.' Print the name of the register with a hard-wired zero (zero or $0).
2bcb2ab3
GK		 6058 '^' Print the name of the pic call-through register (t9 or $25).
6059 '$' Print the name of the stack pointer register (sp or $29).
efa3896a 6060 '+' Print the name of the gp register (gp or $28).
5bdc5878 6061 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
cee98a59
MM		 6062
6063void
6064print_operand (file, op, letter)
6065 FILE *file; /* file to write to */
6066 rtx op; /* operand to print */
6067 int letter; /* %<letter> or 0 */
6068{
6069 register enum rtx_code code;
cafe096b 6070 struct mips_constant_info c;
cee98a59
MM		 6071
6072 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6073 {
6074 switch (letter)
6075 {
cee98a59
MM		 6076 case '?':
6077 if (mips_branch_likely)
6078 putc ('l', file);
6079 break;
6080
6081 case '@':
6082 fputs (reg_names [GP_REG_FIRST + 1], file);
6083 break;
6084
ffa9d0b1
JW		 6085 case '^':
6086 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
6087 break;
6088
cee98a59
MM		 6089 case '.':
6090 fputs (reg_names [GP_REG_FIRST + 0], file);
6091 break;
6092
2bcb2ab3
GK		 6093 case '$':
6094 fputs (reg_names[STACK_POINTER_REGNUM], file);
6095 break;
6096
6097 case '+':
6098 fputs (reg_names[GP_REG_FIRST + 28], file);
6099 break;
6100
cee98a59
MM		 6101 case '&':
6102 if (final_sequence != 0 && set_noreorder++ == 0)
6103 fputs (".set\tnoreorder\n\t", file);
6104 break;
6105
6106 case '*':
6107 if (final_sequence != 0)
6108 {
6109 if (set_noreorder++ == 0)
6110 fputs (".set\tnoreorder\n\t", file);
6111
6112 if (set_nomacro++ == 0)
6113 fputs (".set\tnomacro\n\t", file);
6114 }
6115 break;
6116
6117 case '!':
6118 if (final_sequence != 0 && set_nomacro++ == 0)
6119 fputs ("\n\t.set\tnomacro", file);
6120 break;
6121
6122 case '#':
6123 if (set_noreorder != 0)
6124 fputs ("\n\tnop", file);
85098019 6125 else if (TARGET_STATS)
cee98a59
MM		 6126 fputs ("\n\t#nop", file);
6127
6128 break;
6129
6130 case '(':
6131 if (set_noreorder++ == 0)
6132 fputs (".set\tnoreorder\n\t", file);
6133 break;
6134
6135 case ')':
6136 if (set_noreorder == 0)
6137 error ("internal error: %%) found without a %%( in assembler pattern");
6138
6139 else if (--set_noreorder == 0)
6140 fputs ("\n\t.set\treorder", file);
6141
6142 break;
6143
6144 case '[':
6145 if (set_noat++ == 0)
6146 fputs (".set\tnoat\n\t", file);
6147 break;
6148
7dac2f89 6149 case ']':
cee98a59
MM		 6150 if (set_noat == 0)
6151 error ("internal error: %%] found without a %%[ in assembler pattern");
cee98a59
MM		 6152 else if (--set_noat == 0)
6153 fputs ("\n\t.set\tat", file);
6154
6155 break;
6156
6157 case '<':
6158 if (set_nomacro++ == 0)
6159 fputs (".set\tnomacro\n\t", file);
6160 break;
6161
6162 case '>':
6163 if (set_nomacro == 0)
6164 error ("internal error: %%> found without a %%< in assembler pattern");
cee98a59
MM		 6165 else if (--set_nomacro == 0)
6166 fputs ("\n\t.set\tmacro", file);
6167
6168 break;
6169
6170 case '{':
6171 if (set_volatile++ == 0)
f5963e61 6172 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
cee98a59
MM		 6173 break;
6174
6175 case '}':
6176 if (set_volatile == 0)
6177 error ("internal error: %%} found without a %%{ in assembler pattern");
cee98a59
MM		 6178 else if (--set_volatile == 0)
6179 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
6180
6181 break;
f5963e61 6182
efa3896a
GK		 6183 case '~':
6184 {
6185 if (align_labels_log > 0)
6186 ASM_OUTPUT_ALIGN (file, align_labels_log);
6187 }
6188 break;
6189
f5963e61 6190 default:
c725bd79 6191 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
f5963e61 6192 break;
cee98a59 6193 }
f5963e61 6194
cee98a59
MM		 6195 return;
6196 }
6197
6198 if (! op)
6199 {
6200 error ("PRINT_OPERAND null pointer");
6201 return;
6202 }
6203
6204 code = GET_CODE (op);
2a0b0bf5
ILT		 6205
6206 if (code == SIGN_EXTEND)
f5963e61 6207 op = XEXP (op, 0), code = GET_CODE (op);
2a0b0bf5 6208
cafe096b
EC		 6209 if (letter == 'R')
6210 {
6211 if (TARGET_ABICALLS && TARGET_NEWABI)
6212 fputs ("%got_ofst(", file);
6213 else
6214 fputs ("%lo(", file);
6215 output_addr_const (file, op);
6216 fputc (')', file);
6217 }
6218
5b0f0db6
RS		 6219 else if (letter == 'h')
6220 {
6221 if (GET_CODE (op) != HIGH)
6222 abort ();
6223 fputs ("%hi(", file);
6224 output_addr_const (file, XEXP (op, 0));
6225 fputc (')', file);
6226 }
6227
cafe096b 6228 else if (letter == 'C')
cee98a59
MM		 6229 switch (code)
6230 {
6231 case EQ: fputs ("eq", file); break;
6232 case NE: fputs ("ne", file); break;
6233 case GT: fputs ("gt", file); break;
6234 case GE: fputs ("ge", file); break;
6235 case LT: fputs ("lt", file); break;
6236 case LE: fputs ("le", file); break;
6237 case GTU: fputs ("gtu", file); break;
6238 case GEU: fputs ("geu", file); break;
6239 case LTU: fputs ("ltu", file); break;
6240 case LEU: fputs ("leu", file); break;
cee98a59 6241 default:
e7f6e33b 6242 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
cee98a59
MM		 6243 }
6244
6245 else if (letter == 'N')
6246 switch (code)
6247 {
6248 case EQ: fputs ("ne", file); break;
6249 case NE: fputs ("eq", file); break;
6250 case GT: fputs ("le", file); break;
6251 case GE: fputs ("lt", file); break;
6252 case LT: fputs ("ge", file); break;
6253 case LE: fputs ("gt", file); break;
6254 case GTU: fputs ("leu", file); break;
6255 case GEU: fputs ("ltu", file); break;
6256 case LTU: fputs ("geu", file); break;
6257 case LEU: fputs ("gtu", file); break;
cee98a59 6258 default:
e7f6e33b 6259 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
cee98a59
MM		 6260 }
6261
0ff83799
MM		 6262 else if (letter == 'F')
6263 switch (code)
6264 {
6265 case EQ: fputs ("c1f", file); break;
6266 case NE: fputs ("c1t", file); break;
6267 default:
6268 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
6269 }
6270
6271 else if (letter == 'W')
6272 switch (code)
6273 {
6274 case EQ: fputs ("c1t", file); break;
6275 case NE: fputs ("c1f", file); break;
6276 default:
6277 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
6278 }
6279
e0bfcea5
ILT		 6280 else if (letter == 'S')
6281 {
6282 char buffer[100];
6283
6284 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
6285 assemble_name (file, buffer);
6286 }
6287
b8eb88d0
ILT		 6288 else if (letter == 'Z')
6289 {
6290 register int regnum;
6291
6292 if (code != REG)
6293 abort ();
f5963e61 6294
b8eb88d0
ILT		 6295 regnum = REGNO (op);
6296 if (! ST_REG_P (regnum))
6297 abort ();
f5963e61 6298
b8eb88d0
ILT		 6299 if (regnum != ST_REG_FIRST)
6300 fprintf (file, "%s,", reg_names[regnum]);
6301 }
6302
2a0b0bf5 6303 else if (code == REG || code == SUBREG)
cee98a59 6304 {
2a0b0bf5
ILT		 6305 register int regnum;
6306
6307 if (code == REG)
6308 regnum = REGNO (op);
6309 else
6310 regnum = true_regnum (op);
cee98a59 6311
96abdcb1
ILT		 6312 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
6313 || (letter == 'L' && WORDS_BIG_ENDIAN)
6314 || letter == 'D')
cee98a59
MM		 6315 regnum++;
6316
6317 fprintf (file, "%s", reg_names[regnum]);
6318 }
6319
6320 else if (code == MEM)
51c6b247
RS		 6321 {
6322 if (letter == 'D')
6323 output_address (plus_constant (XEXP (op, 0), 4));
6324 else
6325 output_address (XEXP (op, 0));
6326 }
cee98a59 6327
f5963e61 6328 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
8f9661dd 6329 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
f5963e61
JL		 6330
6331 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
6332 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6333
6334 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
6335 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
cee98a59 6336
5b0f0db6 6337 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
cee98a59
MM		 6338 fputs (reg_names[GP_REG_FIRST], file);
6339
6340 else if (letter == 'd' || letter == 'x' || letter == 'X')
400500c4 6341 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
cee98a59 6342
33563487
JW		 6343 else if (letter == 'B')
6344 fputs (code == EQ ? "z" : "n", file);
6345 else if (letter == 'b')
6346 fputs (code == EQ ? "n" : "z", file);
6347 else if (letter == 'T')
6348 fputs (code == EQ ? "f" : "t", file);
6349 else if (letter == 't')
6350 fputs (code == EQ ? "t" : "f", file);
6351
cee98a59 6352 else
cafe096b 6353 switch (mips_classify_constant (&c, op))
cee98a59 6354 {
cafe096b
EC		 6355 case CONSTANT_NONE:
6356 case CONSTANT_SYMBOLIC:
6357 output_addr_const (file, op);
cee98a59
MM		 6358 break;
6359
cafe096b
EC		 6360 case CONSTANT_GP:
6361 fputs (reg_names[GP_REG_FIRST + 28], file);
910628b8
JW		 6362 break;
6363
cafe096b
EC		 6364 case CONSTANT_RELOC:
6365 fputs (mips_reloc_string (XINT (c.symbol, 1)), file);
6366 output_addr_const (file, plus_constant (XVECEXP (c.symbol, 0, 0),
6367 c.offset));
6368 fputc (')', file);
6369 break;
6370 }
6371}
6372\f
6373/* Return the assembly operator used for the given type of relocation. */
cee98a59 6374
cafe096b
EC		 6375static const char *
6376mips_reloc_string (reloc)
6377 int reloc;
6378{
6379 switch (reloc)
6380 {
6381 case RELOC_GPREL16: return (TARGET_MIPS16 ? "%gprel(" : "%gp_rel(");
6382 case RELOC_GOT_HI: return "%got_hi(";
6383 case RELOC_GOT_LO: return "%got_lo(";
6384 case RELOC_GOT_PAGE: return (TARGET_NEWABI ? "%got_page(" : "%got(");
6385 case RELOC_GOT_DISP: return (TARGET_NEWABI ? "%got_disp(" : "%got(");
6386 case RELOC_CALL16: return "%call16(";
6387 case RELOC_CALL_HI: return "%call_hi(";
6388 case RELOC_CALL_LO: return "%call_lo(";
6389 }
6390 abort ();
6391}
f5963e61 6392
cafe096b 6393/* Output address operand X to FILE. */
cee98a59 6394
cafe096b
EC		 6395void
6396print_operand_address (file, x)
6397 FILE *file;
6398 rtx x;
6399{
6400 struct mips_address_info addr;
cee98a59 6401
cafe096b
EC		 6402 switch (mips_classify_address (&addr, x, word_mode, 1, 1))
6403 {
6404 case ADDRESS_INVALID:
6405 abort ();
ab78d4a8 6406
cafe096b
EC		 6407 case ADDRESS_REG:
6408 print_operand (file, addr.offset, 0);
6409 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6410 return;
cee98a59 6411
cafe096b
EC		 6412 case ADDRESS_LO_SUM:
6413 print_operand (file, addr.offset, 'R');
6414 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6415 return;
f5963e61 6416
cafe096b
EC		 6417 case ADDRESS_CONST_INT:
6418 case ADDRESS_SYMBOLIC:
6419 output_addr_const (file, x);
6420 return;
cee98a59 6421 }
cafe096b 6422 abort ();
cee98a59 6423}
301d03af
RS		 6424\f
6425/* Target hook for assembling integer objects. It appears that the Irix
6426 6 assembler can't handle 64-bit decimal integers, so avoid printing
6427 such an integer here. */
cee98a59 6428
301d03af
RS		 6429static bool
6430mips_assemble_integer (x, size, aligned_p)
6431 rtx x;
6432 unsigned int size;
6433 int aligned_p;
6434{
6435 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
6436 {
6437 fputs ("\t.dword\t", asm_out_file);
6438 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
6439 output_addr_const (asm_out_file, x);
6440 else
6441 print_operand (asm_out_file, x, 'X');
6442 fputc ('\n', asm_out_file);
6443 return true;
6444 }
6445 return default_assemble_integer (x, size, aligned_p);
6446}
cee98a59 6447\f
f5963e61
JL		 6448/* If optimizing for the global pointer, keep track of all of the externs, so
6449 that at the end of the file, we can emit the appropriate .extern
6450 declaration for them, before writing out the text section. We assume all
6451 names passed to us are in the permanent obstack, so they will be valid at
6452 the end of the compilation.
6453
6454 If we have -G 0, or the extern size is unknown, or the object is in a user
6455 specified section that is not .sbss/.sdata, don't bother emitting the
a0ab749a 6456 .externs. In the case of user specified sections this behavior is
f5963e61 6457 required as otherwise GAS will think the object lives in .sbss/.sdata. */
cee98a59
MM		 6458
6459int
6460mips_output_external (file, decl, name)
38831dfe 6461 FILE *file ATTRIBUTE_UNUSED;
cee98a59 6462 tree decl;
bd9f1972 6463 const char *name;
cee98a59
MM		 6464{
6465 register struct extern_list *p;
6466 int len;
4144ff62 6467 tree section_name;
cee98a59
MM		 6468
6469 if (TARGET_GP_OPT
f5963e61 6470 && TREE_CODE (decl) != FUNCTION_DECL
ff48be5c 6471 && !DECL_COMDAT (decl)
f5963e61
JL		 6472 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
6473 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
4144ff62
DE		 6474 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
6475 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
cee98a59 6476 {
6d9f628e 6477 p = (struct extern_list *) xmalloc (sizeof (struct extern_list));
cee98a59
MM		 6478 p->next = extern_head;
6479 p->name = name;
6480 p->size = len;
6481 extern_head = p;
6482 }
5619cc87
JW		 6483
6484#ifdef ASM_OUTPUT_UNDEF_FUNCTION
dd947ed9
RK		 6485 if (TREE_CODE (decl) == FUNCTION_DECL
6486 /* ??? Don't include alloca, since gcc will always expand it
e5e809f4 6487 inline. If we don't do this, the C++ library fails to build. */
9f770b61
JW		 6488 && strcmp (name, "alloca")
6489 /* ??? Don't include __builtin_next_arg, because then gcc will not
6490 bootstrap under Irix 5.1. */
6491 && strcmp (name, "__builtin_next_arg"))
5619cc87 6492 {
6d9f628e 6493 p = (struct extern_list *) xmalloc (sizeof (struct extern_list));
5619cc87
JW		 6494 p->next = extern_head;
6495 p->name = name;
6496 p->size = -1;
6497 extern_head = p;
6498 }
6499#endif
6500
6501 return 0;
6502}
6503
6504#ifdef ASM_OUTPUT_UNDEF_FUNCTION
6505int
6506mips_output_external_libcall (file, name)
e59f7d3d 6507 FILE *file ATTRIBUTE_UNUSED;
bd9f1972 6508 const char *name;
5619cc87
JW		 6509{
6510 register struct extern_list *p;
6511
6d9f628e 6512 p = (struct extern_list *) xmalloc (sizeof (struct extern_list));
5619cc87
JW		 6513 p->next = extern_head;
6514 p->name = name;
6515 p->size = -1;
6516 extern_head = p;
6517
cee98a59
MM		 6518 return 0;
6519}
5619cc87 6520#endif
cee98a59 6521\f
cee98a59
MM		 6522/* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6523 for .file's that start within a function. If we are smuggling stabs, try to
6524 put out a MIPS ECOFF file and a stab. */
6525
6526void
6527mips_output_filename (stream, name)
6528 FILE *stream;
bd9f1972 6529 const char *name;
cee98a59 6530{
cee98a59
MM		 6531 char ltext_label_name[100];
6532
8b0397a6
DJ		 6533 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6534 directives. */
6535 if (write_symbols == DWARF2_DEBUG)
6536 return;
cafe096b 6537 else if (mips_output_filename_first_time)
cee98a59 6538 {
cafe096b 6539 mips_output_filename_first_time = 0;
cee98a59
MM		 6540 SET_FILE_NUMBER ();
6541 current_function_file = name;
33563487 6542 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
2bacb292 6543 /* This tells mips-tfile that stabs will follow. */
9987501f
MM		 6544 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
6545 fprintf (stream, "\t#@stabs\n");
cee98a59
MM		 6546 }
6547
2bacb292 6548 else if (write_symbols == DBX_DEBUG)
cee98a59
MM		 6549 {
6550 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
016c8440 6551 fprintf (stream, "%s", ASM_STABS_OP);
99107e86
PE		 6552 output_quoted_string (stream, name);
6553 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
cee98a59
MM		 6554 }
6555
6556 else if (name != current_function_file
6557 && strcmp (name, current_function_file) != 0)
6558 {
6559 if (inside_function && !TARGET_GAS)
6560 {
6561 if (!file_in_function_warning)
6562 {
f5963e61
JL		 6563 file_in_function_warning = 1;
6564 ignore_line_number = 1;
cee98a59
MM		 6565 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6566 }
cee98a59 6567 }
cee98a59
MM		 6568 else
6569 {
6570 SET_FILE_NUMBER ();
6571 current_function_file = name;
33563487 6572 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
cee98a59
MM		 6573 }
6574 }
6575}
cee98a59
MM		 6576\f
6577/* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6578 as well as a .loc, since it is possible that MIPS ECOFF might not be
6579 able to represent the location for inlines that come from a different
6580 file. */
6581
6582void
6583mips_output_lineno (stream, line)
6584 FILE *stream;
6585 int line;
6586{
2bacb292 6587 if (write_symbols == DBX_DEBUG)
cee98a59
MM		 6588 {
6589 ++sym_lineno;
016c8440 6590 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
dccc9e85
JW		 6591 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
6592 LOCAL_LABEL_PREFIX, sym_lineno);
cee98a59 6593 }
cee98a59
MM		 6594 else
6595 {
6596 fprintf (stream, "\n\t%s.loc\t%d %d\n",
6597 (ignore_line_number) ? "#" : "",
6598 num_source_filenames, line);
7dac2f89 6599
cee98a59
MM		 6600 LABEL_AFTER_LOC (stream);
6601 }
6602}
65437fe8 6603\f
b3276c7a
GK		 6604/* Output an ASCII string, in a space-saving way. */
6605
7dac2f89 6606void
b3276c7a
GK		 6607mips_output_ascii (stream, string_param, len)
6608 FILE *stream;
6609 const char *string_param;
6610 size_t len;
6611{
6612 size_t i;
6613 int cur_pos = 17;
6614 register const unsigned char *string =
6615 (const unsigned char *)string_param;
6616
7dac2f89
EC		 6617 fprintf (stream, "\t.ascii\t\"");
6618 for (i = 0; i < len; i++)
6619 {
6620 register int c = string[i];
6621
6622 switch (c)
6623 {
6624 case '\"':
6625 case '\\':
6626 putc ('\\', stream);
6627 putc (c, stream);
6628 cur_pos += 2;
6629 break;
6630
6631 case TARGET_NEWLINE:
6632 fputs ("\\n", stream);
6633 if (i+1 < len
6634 && (((c = string[i+1]) >= '\040' && c <= '~')
6635 || c == TARGET_TAB))
6636 cur_pos = 32767; /* break right here */
6637 else
6638 cur_pos += 2;
6639 break;
6640
6641 case TARGET_TAB:
6642 fputs ("\\t", stream);
6643 cur_pos += 2;
6644 break;
6645
6646 case TARGET_FF:
6647 fputs ("\\f", stream);
6648 cur_pos += 2;
6649 break;
6650
6651 case TARGET_BS:
6652 fputs ("\\b", stream);
6653 cur_pos += 2;
6654 break;
6655
6656 case TARGET_CR:
6657 fputs ("\\r", stream);
6658 cur_pos += 2;
6659 break;
6660
6661 default:
6662 if (c >= ' ' && c < 0177)
6663 {
6664 putc (c, stream);
6665 cur_pos++;
6666 }
6667 else
6668 {
6669 fprintf (stream, "\\%03o", c);
6670 cur_pos += 4;
6671 }
6672 }
6673
6674 if (cur_pos > 72 && i+1 < len)
6675 {
6676 cur_pos = 17;
6677 fprintf (stream, "\"\n\t.ascii\t\"");
6678 }
6679 }
6680 fprintf (stream, "\"\n");
b3276c7a
GK		 6681}
6682\f
f5963e61
JL		 6683/* If defined, a C statement to be executed just prior to the output of
6684 assembler code for INSN, to modify the extracted operands so they will be
6685 output differently.
65437fe8 6686
f5963e61
JL		 6687 Here the argument OPVEC is the vector containing the operands extracted
6688 from INSN, and NOPERANDS is the number of elements of the vector which
6689 contain meaningful data for this insn. The contents of this vector are
6690 what will be used to convert the insn template into assembler code, so you
6691 can change the assembler output by changing the contents of the vector.
65437fe8 6692
f5963e61
JL		 6693 We use it to check if the current insn needs a nop in front of it because
6694 of load delays, and also to update the delay slot statistics. */
65437fe8 6695
85098019
JW		 6696/* ??? There is no real need for this function, because it never actually
6697 emits a NOP anymore. */
6698
65437fe8
MM		 6699void
6700final_prescan_insn (insn, opvec, noperands)
6701 rtx insn;
38831dfe
KG		 6702 rtx opvec[] ATTRIBUTE_UNUSED;
6703 int noperands ATTRIBUTE_UNUSED;
65437fe8
MM		 6704{
6705 if (dslots_number_nops > 0)
6706 {
65437fe8
MM		 6707 rtx pattern = PATTERN (insn);
6708 int length = get_attr_length (insn);
6709
6710 /* Do we need to emit a NOP? */
6711 if (length == 0
f5963e61
JL		 6712 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
6713 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
6714 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
6715 || (mips_load_reg4 != 0
6716 && reg_mentioned_p (mips_load_reg4, pattern)))
85098019 6717 fputs ("\t#nop\n", asm_out_file);
65437fe8
MM		 6718
6719 else
6720 dslots_load_filled++;
6721
6722 while (--dslots_number_nops > 0)
85098019 6723 fputs ("\t#nop\n", asm_out_file);
65437fe8 6724
f5963e61
JL		 6725 mips_load_reg = 0;
6726 mips_load_reg2 = 0;
6727 mips_load_reg3 = 0;
6728 mips_load_reg4 = 0;
65437fe8
MM		 6729 }
6730
f5963e61
JL		 6731 if (TARGET_STATS
6732 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6733 dslots_jump_total++;
65437fe8 6734}
cee98a59
MM		 6735\f
6736/* Output at beginning of assembler file.
f5963e61
JL		 6737
6738 If we are optimizing to use the global pointer, create a temporary file to
6739 hold all of the text stuff, and write it out to the end. This is needed
6740 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6741 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6742 processed, it generates a two instruction sequence. */
cee98a59
MM		 6743
6744void
6745mips_asm_file_start (stream)
6746 FILE *stream;
6747{
6748 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6749
f5963e61
JL		 6750 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6751 inside of a .set noreorder section jumps to a label outside of the .set
6752 noreorder section. Revision 2.20 just set nobopt silently rather than
6753 fixing the bug. */
cee98a59
MM		 6754
6755 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6756 fprintf (stream, "\t.set\tnobopt\n");
6757
518b566f 6758 if (TARGET_GAS)
0e5a4ad8 6759 {
789b7de5 6760#if defined(OBJECT_FORMAT_ELF) && !(TARGET_IRIX5 || TARGET_IRIX6)
518b566f
EC		 6761 /* Generate a special section to describe the ABI switches used to
6762 produce the resultant binary. This used to be done by the assembler
6763 setting bits in the ELF header's flags field, but we have run out of
6764 bits. GDB needs this information in order to be able to correctly
789b7de5
RO		 6765 debug these binaries. See the function mips_gdbarch_init() in
6766 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6767 causes unnecessary IRIX 6 ld warnings. */
e59f7d3d 6768 const char * abi_string = NULL;
518b566f
EC		 6769
6770 switch (mips_abi)
6771 {
6772 case ABI_32: abi_string = "abi32"; break;
6773 case ABI_N32: abi_string = "abiN32"; break;
6774 case ABI_64: abi_string = "abi64"; break;
6775 case ABI_O64: abi_string = "abiO64"; break;
6776 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
518b566f
EC		 6777 default:
6778 abort ();
6779 }
6780 /* Note - we use fprintf directly rather than called named_section()
6781 because in this way we can avoid creating an allocated section. We
6782 do not want this section to take up any space in the running
6783 executable. */
6784 fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
6785
6786 /* Restore the default section. */
6787 fprintf (stream, "\t.previous\n");
0e5a4ad8 6788#endif
518b566f 6789 }
0e5a4ad8
EC		 6790
6791
6792
ffa9d0b1 6793 /* Generate the pseudo ops that System V.4 wants. */
c388a0c4 6794#ifndef ABICALLS_ASM_OP
78d057d8 6795#define ABICALLS_ASM_OP "\t.abicalls"
c388a0c4 6796#endif
cee98a59 6797 if (TARGET_ABICALLS)
ffa9d0b1 6798 /* ??? but do not want this (or want pic0) if -non-shared? */
016c8440 6799 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
cee98a59 6800
2bcb2ab3
GK		 6801 if (TARGET_MIPS16)
6802 fprintf (stream, "\t.set\tmips16\n");
6803
d7a58f30 6804 /* This code exists so that we can put all externs before all symbol
d46c6fce 6805 references. This is necessary for the MIPS assembler's global pointer
d7a58f30 6806 optimizations to work. */
f99ffb60 6807 if (TARGET_FILE_SWITCHING)
cee98a59
MM		 6808 {
6809 asm_out_data_file = stream;
920ae24b 6810 asm_out_text_file = tmpfile ();
cee98a59
MM		 6811 }
6812 else
6813 asm_out_data_file = asm_out_text_file = stream;
6814
2096c147 6815 if (flag_verbose_asm)
7dac2f89 6816 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
2096c147 6817 ASM_COMMENT_START,
a27fb29b 6818 mips_section_threshold, mips_arch_info->name, mips_isa);
cee98a59 6819}
cee98a59 6820\f
f5963e61
JL		 6821/* If we are optimizing the global pointer, emit the text section now and any
6822 small externs which did not have .comm, etc that are needed. Also, give a
6823 warning if the data area is more than 32K and -pic because 3 instructions
6824 are needed to reference the data pointers. */
cee98a59
MM		 6825
6826void
6827mips_asm_file_end (file)
6828 FILE *file;
6829{
cee98a59
MM		 6830 tree name_tree;
6831 struct extern_list *p;
842eb20e 6832
5619cc87 6833 if (extern_head)
cee98a59 6834 {
5619cc87 6835 fputs ("\n", file);
cee98a59
MM		 6836
6837 for (p = extern_head; p != 0; p = p->next)
6838 {
6839 name_tree = get_identifier (p->name);
c831afd5
MM		 6840
6841 /* Positively ensure only one .extern for any given symbol. */
6842 if (! TREE_ASM_WRITTEN (name_tree))
cee98a59 6843 {
c831afd5 6844 TREE_ASM_WRITTEN (name_tree) = 1;
5619cc87
JW		 6845#ifdef ASM_OUTPUT_UNDEF_FUNCTION
6846 if (p->size == -1)
6847 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6848 else
6849#endif
6850 {
6851 fputs ("\t.extern\t", file);
6852 assemble_name (file, p->name);
6853 fprintf (file, ", %d\n", p->size);
6854 }
cee98a59
MM		 6855 }
6856 }
5619cc87 6857 }
7dac2f89 6858
f99ffb60 6859 if (TARGET_FILE_SWITCHING)
5619cc87 6860 {
cee98a59 6861 fprintf (file, "\n\t.text\n");
920ae24b
RH		 6862 copy_file_data (file, asm_out_text_file);
6863 }
6864}
cee98a59 6865
920ae24b
RH		 6866static void
6867copy_file_data (to, from)
6868 FILE *to, *from;
6869{
6870 char buffer[8192];
6871 size_t len;
920ae24b
RH		 6872 rewind (from);
6873 if (ferror (from))
6874 fatal_io_error ("can't rewind temp file");
cee98a59 6875
920ae24b
RH		 6876 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6877 if (fwrite (buffer, 1, len, to) != len)
6878 fatal_io_error ("can't write to output file");
147255d8 6879
920ae24b
RH		 6880 if (ferror (from))
6881 fatal_io_error ("can't read from temp file");
6882
6883 if (fclose (from))
6884 fatal_io_error ("can't close temp file");
cee98a59
MM		 6885}
6886
f5963e61
JL		 6887/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6888 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
9987501f
MM		 6889
6890void
6891mips_declare_object (stream, name, init_string, final_string, size)
6892 FILE *stream;
bd9f1972
KG		 6893 const char *name;
6894 const char *init_string;
6895 const char *final_string;
9987501f
MM		 6896 int size;
6897{
6898 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6899 assemble_name (stream, name);
6900 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6901
147255d8 6902 if (TARGET_GP_OPT)
9987501f
MM		 6903 {
6904 tree name_tree = get_identifier (name);
6905 TREE_ASM_WRITTEN (name_tree) = 1;
6906 }
6907}
dbe9742d 6908\f
cee98a59
MM		 6909/* Return the bytes needed to compute the frame pointer from the current
6910 stack pointer.
6911
6912 Mips stack frames look like:
6913
6914 Before call After call
6915 +-----------------------+ +-----------------------+
6916 high | | | |
6917 mem. | | | |
6918 | caller's temps. | | caller's temps. |
6919 | | | |
6920 +-----------------------+ +-----------------------+
6921 | | | |
6922 | arguments on stack. | | arguments on stack. |
6923 | | | |
6924 +-----------------------+ +-----------------------+
6925 | 4 words to save | | 4 words to save |
6926 | arguments passed | | arguments passed |
6927 | in registers, even | | in registers, even |
ffa9d0b1 6928 SP->| if not passed. | VFP->| if not passed. |
cee98a59 6929 +-----------------------+ +-----------------------+
cee98a59
MM		 6930 | |
6931 | fp register save |
6932 | |
6933 +-----------------------+
6934 | |
6935 | gp register save |
6936 | |
6937 +-----------------------+
6938 | |
ab78d4a8
MM		 6939 | local variables |
6940 | |
6941 +-----------------------+
6942 | |
cee98a59
MM		 6943 | alloca allocations |
6944 | |
6945 +-----------------------+
6946 | |
ffa9d0b1
JW		 6947 | GP save for V.4 abi |
6948 | |
6949 +-----------------------+
6950 | |
cee98a59
MM		 6951 | arguments on stack |
6952 | |
6953 +-----------------------+
6954 | 4 words to save |
6955 | arguments passed |
6956 | in registers, even |
6957 low SP->| if not passed. |
6958 memory +-----------------------+
6959
6960*/
6961
f5963e61 6962HOST_WIDE_INT
cee98a59 6963compute_frame_size (size)
db4c1c35 6964 HOST_WIDE_INT size; /* # of var. bytes allocated */
cee98a59 6965{
c3d03e3a 6966 unsigned int regno;
f5963e61
JL		 6967 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6968 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6969 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6970 HOST_WIDE_INT extra_size; /* # extra bytes */
6971 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6972 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6973 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
7bea35e7
MM		 6974 long mask; /* mask of saved gp registers */
6975 long fmask; /* mask of saved fp registers */
3f26edaa 6976 tree return_type;
cee98a59 6977
f5963e61
JL		 6978 gp_reg_size = 0;
6979 fp_reg_size = 0;
6980 mask = 0;
6981 fmask = 0;
6982 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6983 var_size = MIPS_STACK_ALIGN (size);
6984 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
ab78d4a8
MM		 6985
6986 /* The MIPS 3.0 linker does not like functions that dynamically
6987 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6988 looks like we are trying to create a second frame pointer to the
6989 function, so allocate some stack space to make it happy. */
6990
6991 if (args_size == 0 && current_function_calls_alloca)
f5963e61 6992 args_size = 4 * UNITS_PER_WORD;
ab78d4a8
MM		 6993
6994 total_size = var_size + args_size + extra_size;
3f26edaa 6995 return_type = DECL_RESULT (current_function_decl);
cee98a59
MM		 6996
6997 /* Calculate space needed for gp registers. */
6998 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6999 {
2bcb2ab3
GK		 7000 /* $18 is a special case on the mips16. It may be used to call
7001 a function which returns a floating point value, but it is
7002 marked in call_used_regs. $31 is also a special case. When
7003 not using -mentry, it will be used to copy a return value
7004 into the floating point registers if the return value is
7005 floating point. */
7006 if (MUST_SAVE_REGISTER (regno)
7007 || (TARGET_MIPS16
7008 && regno == GP_REG_FIRST + 18
7009 && regs_ever_live[regno])
7010 || (TARGET_MIPS16
7011 && regno == GP_REG_FIRST + 31
7012 && mips16_hard_float
7013 && ! mips_entry
3f26edaa
RS		 7014 && ! aggregate_value_p (return_type)
7015 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7016 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE))
cee98a59 7017 {
bfed8dac 7018 gp_reg_size += GET_MODE_SIZE (gpr_mode);
7bea35e7 7019 mask |= 1L << (regno - GP_REG_FIRST);
2bcb2ab3
GK		 7020
7021 /* The entry and exit pseudo instructions can not save $17
7022 without also saving $16. */
7023 if (mips_entry
7024 && regno == GP_REG_FIRST + 17
7025 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
7026 {
7027 gp_reg_size += UNITS_PER_WORD;
7028 mask |= 1L << 16;
7029 }
cee98a59
MM		 7030 }
7031 }
7032
9e800206
RH		 7033 /* We need to restore these for the handler. */
7034 if (current_function_calls_eh_return)
7035 {
c3d03e3a 7036 unsigned int i;
9e800206
RH		 7037 for (i = 0; ; ++i)
7038 {
7039 regno = EH_RETURN_DATA_REGNO (i);
7040 if (regno == INVALID_REGNUM)
7041 break;
7042 gp_reg_size += GET_MODE_SIZE (gpr_mode);
7043 mask |= 1L << (regno - GP_REG_FIRST);
7044 }
7045 }
7046
d1d3a2df 7047 /* This loop must iterate over the same space as its companion in
282cb01b 7048 save_restore_insns. */
e6f884cd 7049 for (regno = (FP_REG_LAST - FP_INC + 1);
d1d3a2df 7050 regno >= FP_REG_FIRST;
e6f884cd 7051 regno -= FP_INC)
cee98a59
MM		 7052 {
7053 if (regs_ever_live[regno] && !call_used_regs[regno])
7054 {
e6f884cd
RS		 7055 fp_reg_size += FP_INC * UNITS_PER_FPREG;
7056 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
cee98a59
MM		 7057 }
7058 }
7059
7060 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
46299de9 7061 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
cee98a59 7062
33563487
JW		 7063 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
7064 for leaf routines (total_size == extra_size) to save the gp reg.
7065 The gp reg is callee saved in the 64 bit ABI, so all routines must
a944a4eb
JW		 7066 save the gp reg. This is not a leaf routine if -p, because of the
7067 call to mcount. */
7dac2f89 7068 if (total_size == extra_size
a53f72db 7069 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
70f4f91c 7070 && ! current_function_profile)
cee98a59 7071 total_size = extra_size = 0;
ffa9d0b1
JW		 7072 else if (TARGET_ABICALLS)
7073 {
7074 /* Add the context-pointer to the saved registers. */
7075 gp_reg_size += UNITS_PER_WORD;
7076 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
7077 total_size -= gp_reg_rounded;
7078 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
7079 total_size += gp_reg_rounded;
7080 }
cee98a59 7081
33563487
JW		 7082 /* Add in space reserved on the stack by the callee for storing arguments
7083 passed in registers. */
a53f72db 7084 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
33563487
JW		 7085 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
7086
2bcb2ab3
GK		 7087 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
7088 if (mips_entry && total_size > 0 && total_size < 32)
7089 total_size = 32;
7090
cee98a59 7091 /* Save other computed information. */
b2471838
RS		 7092 cfun->machine->frame.total_size = total_size;
7093 cfun->machine->frame.var_size = var_size;
7094 cfun->machine->frame.args_size = args_size;
7095 cfun->machine->frame.extra_size = extra_size;
7096 cfun->machine->frame.gp_reg_size = gp_reg_size;
7097 cfun->machine->frame.fp_reg_size = fp_reg_size;
7098 cfun->machine->frame.mask = mask;
7099 cfun->machine->frame.fmask = fmask;
7100 cfun->machine->frame.initialized = reload_completed;
7101 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
7102 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
cee98a59
MM		 7103
7104 if (mask)
7105 {
2bcb2ab3
GK		 7106 unsigned long offset;
7107
7108 /* When using mips_entry, the registers are always saved at the
7109 top of the stack. */
7110 if (! mips_entry)
7111 offset = (args_size + extra_size + var_size
bfed8dac 7112 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
2bcb2ab3 7113 else
bfed8dac
JL		 7114 offset = total_size - GET_MODE_SIZE (gpr_mode);
7115
b2471838
RS		 7116 cfun->machine->frame.gp_sp_offset = offset;
7117 cfun->machine->frame.gp_save_offset = offset - total_size;
cee98a59 7118 }
258d81a8
MM		 7119 else
7120 {
b2471838
RS		 7121 cfun->machine->frame.gp_sp_offset = 0;
7122 cfun->machine->frame.gp_save_offset = 0;
258d81a8
MM		 7123 }
7124
cee98a59
MM		 7125 if (fmask)
7126 {
147255d8
JW		 7127 unsigned long offset = (args_size + extra_size + var_size
7128 + gp_reg_rounded + fp_reg_size
e6f884cd 7129 - FP_INC * UNITS_PER_FPREG);
b2471838
RS		 7130 cfun->machine->frame.fp_sp_offset = offset;
7131 cfun->machine->frame.fp_save_offset = offset - total_size;
cee98a59 7132 }
258d81a8
MM		 7133 else
7134 {
b2471838
RS		 7135 cfun->machine->frame.fp_sp_offset = 0;
7136 cfun->machine->frame.fp_save_offset = 0;
258d81a8 7137 }
cee98a59
MM		 7138
7139 /* Ok, we're done. */
7140 return total_size;
7141}
cee98a59 7142\f
b2471838
RS		 7143/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
7144 pointer, argument pointer, or return address pointer. TO is either
7145 the stack pointer or hard frame pointer. */
7146
7147int
7148mips_initial_elimination_offset (from, to)
7149 int from, to;
7150{
7151 int offset;
7152
7153 /* Set OFFSET to the offset from the stack pointer. */
7154 switch (from)
7155 {
7156 case FRAME_POINTER_REGNUM:
7157 offset = 0;
7158 break;
7159
7160 case ARG_POINTER_REGNUM:
7161 compute_frame_size (get_frame_size ());
7162 offset = cfun->machine->frame.total_size;
cafe096b 7163 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
b2471838
RS		 7164 offset -= current_function_pretend_args_size;
7165 break;
7166
b2471838
RS		 7167 default:
7168 abort ();
7169 }
7170
7171 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
7172 offset -= current_function_outgoing_args_size;
7173
7174 return offset;
7175}
7176\f
7bea35e7
MM		 7177/* Common code to emit the insns (or to write the instructions to a file)
7178 to save/restore registers.
cee98a59 7179
7bea35e7
MM		 7180 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
7181 is not modified within save_restore_insns. */
7182
f5963e61 7183#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
7bea35e7 7184
cafe096b
EC		 7185/* Implement RETURN_ADDR_RTX. Note, we do not support moving
7186 back to a previous frame. */
7187rtx
7188mips_return_addr (count, frame)
7189 int count;
7190 rtx frame ATTRIBUTE_UNUSED;
7191{
7192 if (count != 0)
7193 return const0_rtx;
7194
7195 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
7196}
7197
7198
67070ffe 7199/* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
a8b4881f 7200 and return an rtl expression for the register.
67070ffe
RS		 7201
7202 This function is a subroutine of save_restore_insns. It is used when
7203 OFFSET is too large to add in a single instruction. */
7204
7205static rtx
a8b4881f 7206mips_add_large_offset_to_sp (offset)
67070ffe 7207 HOST_WIDE_INT offset;
67070ffe
RS		 7208{
7209 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
a8b4881f 7210 rtx offset_rtx = GEN_INT (offset);
67070ffe 7211
a8b4881f
RS		 7212 emit_move_insn (reg, offset_rtx);
7213 if (Pmode == DImode)
7214 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
67070ffe 7215 else
a8b4881f 7216 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
67070ffe
RS		 7217 return reg;
7218}
7219
5b0f0db6
RS		 7220/* Make the last instruction frame related and note that it performs
7221 the operation described by FRAME_PATTERN. */
67070ffe
RS		 7222
7223static void
5b0f0db6
RS		 7224mips_set_frame_expr (frame_pattern)
7225 rtx frame_pattern;
67070ffe 7226{
5b0f0db6
RS		 7227 rtx insn;
7228
7229 insn = get_last_insn ();
67070ffe
RS		 7230 RTX_FRAME_RELATED_P (insn) = 1;
7231 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
5b0f0db6 7232 frame_pattern,
67070ffe
RS		 7233 REG_NOTES (insn));
7234}
7235
5b0f0db6
RS		 7236/* Return a frame-related rtx that stores REG at (SP + OFFSET).
7237 REG must be a single register. */
1cbfdb1f
RS		 7238
7239static rtx
5b0f0db6
RS		 7240mips_frame_set (reg, offset)
7241 rtx reg;
1cbfdb1f
RS		 7242 int offset;
7243{
7244 rtx address = plus_constant (stack_pointer_rtx, offset);
5b0f0db6 7245 rtx set = gen_rtx_SET (VOIDmode, gen_rtx_MEM (GET_MODE (reg), address), reg);
1cbfdb1f
RS		 7246 RTX_FRAME_RELATED_P (set) = 1;
7247 return set;
7248}
7249
7250
67070ffe 7251/* Emit a move instruction that stores REG in MEM. Make the instruction
1cbfdb1f
RS		 7252 frame related and note that it stores REG at (SP + OFFSET). This
7253 function may be asked to store an FPR pair. */
67070ffe
RS		 7254
7255static void
7256mips_emit_frame_related_store (mem, reg, offset)
7257 rtx mem;
7258 rtx reg;
7259 HOST_WIDE_INT offset;
7260{
5b0f0db6
RS		 7261 if (GET_MODE (reg) == DFmode && mips_split_64bit_move_p (mem, reg))
7262 mips_split_64bit_move (mem, reg);
7263 else
7264 emit_move_insn (mem, reg);
67070ffe 7265
5b0f0db6 7266 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
1cbfdb1f 7267 {
5b0f0db6
RS		 7268 rtx x1, x2;
7269
1cbfdb1f 7270 /* Two registers are being stored, so the frame-related expression
5b0f0db6
RS		 7271 must be a PARALLEL rtx with one SET for each register. */
7272 x1 = mips_frame_set (mips_subword (reg, TARGET_BIG_ENDIAN), offset);
7273 x2 = mips_frame_set (mips_subword (reg, !TARGET_BIG_ENDIAN),
7274 offset + UNITS_PER_FPREG);
7275 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
1cbfdb1f
RS		 7276 }
7277 else
5b0f0db6 7278 mips_set_frame_expr (mips_frame_set (reg, offset));
67070ffe
RS		 7279}
7280
7bea35e7 7281static void
a8b4881f 7282save_restore_insns (store_p, large_reg, large_offset)
f5963e61
JL		 7283 int store_p; /* true if this is prologue */
7284 rtx large_reg; /* register holding large offset constant or NULL */
7285 long large_offset; /* large constant offset value */
cee98a59 7286{
b2471838
RS		 7287 long mask = cfun->machine->frame.mask;
7288 long fmask = cfun->machine->frame.fmask;
c8a14e0e 7289 long real_mask = mask;
cee98a59 7290 int regno;
7bea35e7 7291 rtx base_reg_rtx;
f5963e61
JL		 7292 HOST_WIDE_INT base_offset;
7293 HOST_WIDE_INT gp_offset;
7294 HOST_WIDE_INT fp_offset;
7295 HOST_WIDE_INT end_offset;
7bea35e7 7296
f5963e61 7297 if (frame_pointer_needed
1b15c5de 7298 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
7bea35e7 7299 abort ();
cee98a59 7300
c8a14e0e
RH		 7301 /* Do not restore GP under certain conditions. */
7302 if (! store_p
7303 && TARGET_ABICALLS
7304 && (mips_abi == ABI_32 || mips_abi == ABI_O64))
282cb01b 7305 mask &= ~(1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST));
c8a14e0e 7306
cee98a59
MM		 7307 if (mask == 0 && fmask == 0)
7308 return;
7309
f5963e61
JL		 7310 /* Save registers starting from high to low. The debuggers prefer at least
7311 the return register be stored at func+4, and also it allows us not to
7312 need a nop in the epilog if at least one register is reloaded in
7313 addition to return address. */
cee98a59 7314
7bea35e7
MM		 7315 /* Save GP registers if needed. */
7316 if (mask)
cee98a59 7317 {
f5963e61
JL		 7318 /* Pick which pointer to use as a base register. For small frames, just
7319 use the stack pointer. Otherwise, use a temporary register. Save 2
7320 cycles if the save area is near the end of a large frame, by reusing
7321 the constant created in the prologue/epilogue to adjust the stack
7322 frame. */
cee98a59 7323
b2471838 7324 gp_offset = cfun->machine->frame.gp_sp_offset;
f5963e61 7325 end_offset
b2471838 7326 = gp_offset - (cfun->machine->frame.gp_reg_size
bfed8dac 7327 - GET_MODE_SIZE (gpr_mode));
7bea35e7
MM		 7328
7329 if (gp_offset < 0 || end_offset < 0)
400500c4 7330 internal_error
c725bd79 7331 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
400500c4 7332 (long) gp_offset, (long) end_offset);
7bea35e7 7333
2bcb2ab3
GK		 7334 /* If we see a large frame in mips16 mode, we save the registers
7335 before adjusting the stack pointer, and load them afterward. */
7336 else if (TARGET_MIPS16 && large_offset > 32767)
f5963e61 7337 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
2bcb2ab3 7338
7bea35e7 7339 else if (gp_offset < 32768)
f5963e61 7340 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
cee98a59 7341
f5963e61
JL		 7342 else if (large_reg != 0
7343 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
7344 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7bea35e7 7345 {
c5c76735 7346 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61 7347 base_offset = large_offset;
a8b4881f 7348 if (Pmode == DImode)
4977bab6 7349 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
7bea35e7 7350 else
4977bab6 7351 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
7bea35e7 7352 }
7bea35e7 7353 else
cee98a59 7354 {
f5963e61 7355 base_offset = gp_offset;
a8b4881f 7356 base_reg_rtx = mips_add_large_offset_to_sp (base_offset);
cee98a59 7357 }
0fb5ac6f 7358
2bcb2ab3
GK		 7359 /* When we restore the registers in MIPS16 mode, then if we are
7360 using a frame pointer, and this is not a large frame, the
7361 current stack pointer will be offset by
7362 current_function_outgoing_args_size. Doing it this way lets
7363 us avoid offsetting the frame pointer before copying it into
7364 the stack pointer; there is no instruction to set the stack
7365 pointer to the sum of a register and a constant. */
7366 if (TARGET_MIPS16
7367 && ! store_p
7368 && frame_pointer_needed
7369 && large_offset <= 32767)
7370 base_offset += current_function_outgoing_args_size;
7371
7372 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
a8b4881f
RS		 7373 {
7374 if (BITSET_P (mask, regno - GP_REG_FIRST))
7375 {
7376 rtx reg_rtx;
7377 rtx mem_rtx
7378 = gen_rtx (MEM, gpr_mode,
7379 gen_rtx (PLUS, Pmode, base_reg_rtx,
7380 GEN_INT (gp_offset - base_offset)));
7381
7382 if (! current_function_calls_eh_return)
7383 RTX_UNCHANGING_P (mem_rtx) = 1;
7384
7385 /* The mips16 does not have an instruction to load
7386 $31, so we load $7 instead, and work things out
7387 in mips_expand_epilogue. */
7388 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
7389 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
7390 /* The mips16 sometimes needs to save $18. */
7391 else if (TARGET_MIPS16
7392 && regno != GP_REG_FIRST + 31
7393 && ! M16_REG_P (regno))
7394 {
7395 if (! store_p)
7396 reg_rtx = gen_rtx (REG, gpr_mode, 6);
7397 else
7398 {
7399 reg_rtx = gen_rtx (REG, gpr_mode, 3);
7400 emit_move_insn (reg_rtx,
7401 gen_rtx (REG, gpr_mode, regno));
7402 }
7403 }
7404 else
7405 reg_rtx = gen_rtx (REG, gpr_mode, regno);
7406
7407 if (store_p)
7408 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
7409 else
7410 {
7411 emit_move_insn (reg_rtx, mem_rtx);
7412 if (TARGET_MIPS16
7413 && regno != GP_REG_FIRST + 31
7414 && ! M16_REG_P (regno))
7415 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
7416 reg_rtx);
7417 }
7418 }
7419 /* If the restore is being supressed, still take into account
7420 the offset at which it is stored. */
7421 if (BITSET_P (real_mask, regno - GP_REG_FIRST))
c8a14e0e 7422 gp_offset -= GET_MODE_SIZE (gpr_mode);
a8b4881f 7423 }
0fb5ac6f 7424 }
7bea35e7 7425 else
f5963e61 7426 base_reg_rtx = 0, base_offset = 0;
0fb5ac6f 7427
7bea35e7 7428 /* Save floating point registers if needed. */
0fb5ac6f
MM		 7429 if (fmask)
7430 {
7bea35e7 7431 /* Pick which pointer to use as a base register. */
b2471838
RS		 7432 fp_offset = cfun->machine->frame.fp_sp_offset;
7433 end_offset = fp_offset - (cfun->machine->frame.fp_reg_size
8a381273 7434 - UNITS_PER_HWFPVALUE);
7bea35e7
MM		 7435
7436 if (fp_offset < 0 || end_offset < 0)
400500c4 7437 internal_error
c725bd79 7438 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
400500c4 7439 (long) fp_offset, (long) end_offset);
7bea35e7
MM		 7440
7441 else if (fp_offset < 32768)
f5963e61 7442 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
7bea35e7 7443
f5963e61
JL		 7444 else if (base_reg_rtx != 0
7445 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
7446 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
7447 ; /* already set up for gp registers above */
7bea35e7 7448
f5963e61
JL		 7449 else if (large_reg != 0
7450 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
7451 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7bea35e7 7452 {
c5c76735 7453 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61 7454 base_offset = large_offset;
a8b4881f 7455 if (Pmode == DImode)
4977bab6 7456 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
7bea35e7 7457 else
4977bab6 7458 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
7bea35e7 7459 }
7bea35e7
MM		 7460 else
7461 {
f5963e61 7462 base_offset = fp_offset;
a8b4881f 7463 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset);
7bea35e7
MM		 7464 }
7465
d1d3a2df
JL		 7466 /* This loop must iterate over the same space as its companion in
7467 compute_frame_size. */
3f26edaa 7468 for (regno = (FP_REG_LAST - FP_INC + 1);
d1d3a2df 7469 regno >= FP_REG_FIRST;
3f26edaa 7470 regno -= FP_INC)
f5963e61
JL		 7471 if (BITSET_P (fmask, regno - FP_REG_FIRST))
7472 {
a8b4881f
RS		 7473 enum machine_mode sz = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
7474 rtx reg_rtx = gen_rtx (REG, sz, regno);
7475 rtx mem_rtx = gen_rtx (MEM, sz,
7476 gen_rtx (PLUS, Pmode, base_reg_rtx,
7477 GEN_INT (fp_offset
7478 - base_offset)));
7479 if (! current_function_calls_eh_return)
7480 RTX_UNCHANGING_P (mem_rtx) = 1;
7481
7482 if (store_p)
7483 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
f5963e61 7484 else
a8b4881f 7485 emit_move_insn (reg_rtx, mem_rtx);
f5963e61 7486
8a381273 7487 fp_offset -= UNITS_PER_HWFPVALUE;
f5963e61 7488 }
0fb5ac6f
MM		 7489 }
7490}
cee98a59
MM		 7491\f
7492/* Set up the stack and frame (if desired) for the function. */
7493
08c148a8
NB		 7494static void
7495mips_output_function_prologue (file, size)
cee98a59 7496 FILE *file;
810c1b83 7497 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
cee98a59 7498{
6e92f4b6 7499#ifndef FUNCTION_NAME_ALREADY_DECLARED
bd9f1972 7500 const char *fnname;
6e92f4b6 7501#endif
b2471838 7502 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
cee98a59 7503
8b0397a6
DJ		 7504 /* ??? When is this really needed? At least the GNU assembler does not
7505 need the source filename more than once in the file, beyond what is
7506 emitted by the debug information. */
7507 if (!TARGET_GAS)
7508 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
8a2d2f90 7509
8bd8e198 7510#ifdef SDB_DEBUGGING_INFO
af173031 7511 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8a2d2f90 7512 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8bd8e198 7513#endif
cee98a59 7514
2bcb2ab3
GK		 7515 /* In mips16 mode, we may need to generate a 32 bit to handle
7516 floating point arguments. The linker will arrange for any 32 bit
7517 functions to call this stub, which will then jump to the 16 bit
7518 function proper. */
7519 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
7520 && current_function_args_info.fp_code != 0)
7521 build_mips16_function_stub (file);
7522
993cd990
JW		 7523 inside_function = 1;
7524
7525#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52
RK		 7526 /* Get the function name the same way that toplev.c does before calling
7527 assemble_start_function. This is needed so that the name used here
7528 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7529 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7530
e9a25f70
JL		 7531 if (!flag_inhibit_size_directive)
7532 {
7533 fputs ("\t.ent\t", file);
7534 assemble_name (file, fnname);
7535 fputs ("\n", file);
7536 }
7bea35e7 7537
10389f52 7538 assemble_name (file, fnname);
cee98a59 7539 fputs (":\n", file);
993cd990 7540#endif
cee98a59 7541
e9a25f70
JL		 7542 if (!flag_inhibit_size_directive)
7543 {
a50f2a09 7544 /* .frame FRAMEREG, FRAMESIZE, RETREG */
f5963e61
JL		 7545 fprintf (file,
7546 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7547 (reg_names[(frame_pointer_needed)
7548 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
a50f2a09 7549 ((frame_pointer_needed && TARGET_MIPS16)
009da785
EC		 7550 ? ((long) tsize - current_function_outgoing_args_size)
7551 : (long) tsize),
7552 reg_names[GP_REG_FIRST + 31],
b2471838
RS		 7553 cfun->machine->frame.var_size,
7554 cfun->machine->frame.num_gp,
7555 cfun->machine->frame.num_fp,
f5963e61 7556 current_function_outgoing_args_size,
b2471838 7557 cfun->machine->frame.extra_size);
e9a25f70 7558
a50f2a09 7559 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
3afaa6e8 7560 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
b2471838
RS		 7561 cfun->machine->frame.mask,
7562 cfun->machine->frame.gp_save_offset,
7563 cfun->machine->frame.fmask,
7564 cfun->machine->frame.fp_save_offset);
a50f2a09
AC		 7565
7566 /* Require:
7567 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
987ba558 7568 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
e9a25f70 7569 }
ffa9d0b1 7570
2bcb2ab3
GK		 7571 if (mips_entry && ! mips_can_use_return_insn ())
7572 {
b2471838
RS		 7573 int save16 = BITSET_P (cfun->machine->frame.mask, 16);
7574 int save17 = BITSET_P (cfun->machine->frame.mask, 17);
7575 int save31 = BITSET_P (cfun->machine->frame.mask, 31);
2bcb2ab3
GK		 7576 int savearg = 0;
7577 rtx insn;
7578
7579 /* Look through the initial insns to see if any of them store
7580 the function parameters into the incoming parameter storage
7581 area. If they do, we delete the insn, and save the register
7582 using the entry pseudo-instruction instead. We don't try to
7583 look past a label, jump, or call. */
7584 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
7585 {
7586 rtx note, set, src, dest, base, offset;
7587 int hireg;
7588
7589 if (GET_CODE (insn) == CODE_LABEL
7590 || GET_CODE (insn) == JUMP_INSN
7591 || GET_CODE (insn) == CALL_INSN)
7592 break;
7593 if (GET_CODE (insn) != INSN)
7594 continue;
7595 set = PATTERN (insn);
7596 if (GET_CODE (set) != SET)
7597 continue;
7598
7599 /* An insn storing a function parameter will still have a
7600 REG_EQUIV note on it mentioning the argument pointer. */
7601 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
7602 if (note == NULL_RTX)
7603 continue;
7604 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
7605 continue;
7606
7607 src = SET_SRC (set);
7608 if (GET_CODE (src) != REG
7609 || REGNO (src) < GP_REG_FIRST + 4
7610 || REGNO (src) > GP_REG_FIRST + 7)
7611 continue;
7612
7613 dest = SET_DEST (set);
7614 if (GET_CODE (dest) != MEM)
7615 continue;
0da9afa6 7616 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
2bcb2ab3 7617 ;
95adab8e 7618 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
2bcb2ab3
GK		 7619 && REGNO (src) < GP_REG_FIRST + 7)
7620 ;
7621 else
7622 continue;
7623 offset = const0_rtx;
7624 base = eliminate_constant_term (XEXP (dest, 0), &offset);
7625 if (GET_CODE (base) != REG
7626 || GET_CODE (offset) != CONST_INT)
7627 continue;
0da9afa6 7628 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
6b7d57c7 7629 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
2bcb2ab3 7630 ;
0da9afa6 7631 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
6b7d57c7 7632 && (INTVAL (offset)
2bcb2ab3
GK		 7633 == (tsize
7634 + (REGNO (src) - 4) * UNITS_PER_WORD
7635 - current_function_outgoing_args_size)))
7636 ;
7637 else
7638 continue;
7639
7640 /* This insn stores a parameter onto the stack, in the same
7641 location where the entry pseudo-instruction will put it.
7642 Delete the insn, and arrange to tell the entry
7643 instruction to save the register. */
7644 PUT_CODE (insn, NOTE);
7645 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7646 NOTE_SOURCE_FILE (insn) = 0;
7647
7648 hireg = (REGNO (src)
7649 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7650 - 1);
7651 if (hireg > savearg)
7652 savearg = hireg;
7653 }
7654
7655 /* If this is a varargs function, we need to save all the
7656 registers onto the stack anyhow. */
6c535c69 7657 if (current_function_stdarg)
2bcb2ab3
GK		 7658 savearg = GP_REG_FIRST + 7;
7659
7660 fprintf (file, "\tentry\t");
7661 if (savearg > 0)
7662 {
7663 if (savearg == GP_REG_FIRST + 4)
7664 fprintf (file, "%s", reg_names[savearg]);
7665 else
7666 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7667 reg_names[savearg]);
7668 }
7669 if (save16 || save17)
7670 {
7671 if (savearg > 0)
7672 fprintf (file, ",");
7673 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7674 if (save17)
7675 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7676 }
7677 if (save31)
7678 {
7679 if (savearg > 0 || save16 || save17)
7680 fprintf (file, ",");
7681 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7682 }
7683 fprintf (file, "\n");
7684 }
7685
a53f72db 7686 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
ffa9d0b1 7687 {
bd9f1972 7688 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
ffa9d0b1
JW		 7689
7690 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7691 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7692 if (tsize > 0)
7693 {
3afaa6e8 7694 fprintf (file, "\t%s\t%s,%s,%ld\n",
cafe096b 7695 (ptr_mode == DImode ? "dsubu" : "subu"),
2aae2cc7 7696 sp_str, sp_str, (long) tsize);
b2471838 7697 fprintf (file, "\t.cprestore %ld\n", cfun->machine->frame.args_size);
ffa9d0b1 7698 }
0021b564
JM		 7699
7700 if (dwarf2out_do_frame ())
7701 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
ffa9d0b1 7702 }
0fb5ac6f 7703}
0fb5ac6f
MM		 7704\f
7705/* Expand the prologue into a bunch of separate insns. */
7706
7707void
7708mips_expand_prologue ()
7709{
7710 int regno;
f5963e61
JL		 7711 HOST_WIDE_INT tsize;
7712 rtx tmp_rtx = 0;
4730fa4f 7713 int last_arg_is_vararg_marker = 0;
f5963e61
JL		 7714 tree fndecl = current_function_decl;
7715 tree fntype = TREE_TYPE (fndecl);
7716 tree fnargs = DECL_ARGUMENTS (fndecl);
3f1f8d8c
MM		 7717 rtx next_arg_reg;
7718 int i;
0fb5ac6f
MM		 7719 tree next_arg;
7720 tree cur_arg;
0fb5ac6f 7721 CUMULATIVE_ARGS args_so_far;
2bcb2ab3 7722 rtx reg_18_save = NULL_RTX;
9e5ac782
CP		 7723 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7724 && (! mips_entry || mips_can_use_return_insn ());
0fb5ac6f 7725
518e5ce8
JW		 7726 /* If struct value address is treated as the first argument, make it so. */
7727 if (aggregate_value_p (DECL_RESULT (fndecl))
7728 && ! current_function_returns_pcc_struct
7729 && struct_value_incoming_rtx == 0)
7730 {
7731 tree type = build_pointer_type (fntype);
7732 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
f5963e61 7733
518e5ce8
JW		 7734 DECL_ARG_TYPE (function_result_decl) = type;
7735 TREE_CHAIN (function_result_decl) = fnargs;
7736 fnargs = function_result_decl;
7737 }
7738
4730fa4f
GRK		 7739 /* For arguments passed in registers, find the register number
7740 of the first argument in the variable part of the argument list,
7dac2f89 7741 otherwise GP_ARG_LAST+1. Note also if the last argument is
4730fa4f 7742 the varargs special argument, and treat it as part of the
0da9afa6 7743 variable arguments.
7dac2f89 7744
987ba558 7745 This is only needed if store_args_on_stack is true. */
3f1f8d8c 7746
563a317a 7747 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, current_function_decl);
3f1f8d8c
MM		 7748 regno = GP_ARG_FIRST;
7749
f5963e61 7750 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
cee98a59 7751 {
6f673359
JW		 7752 tree passed_type = DECL_ARG_TYPE (cur_arg);
7753 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7754 rtx entry_parm;
7755
e0c228da 7756 if (TREE_ADDRESSABLE (passed_type))
6f673359
JW		 7757 {
7758 passed_type = build_pointer_type (passed_type);
7759 passed_mode = Pmode;
7760 }
7761
7762 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
3f1f8d8c 7763
4730fa4f
GRK		 7764 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7765 next_arg = TREE_CHAIN (cur_arg);
7766
9e5ac782 7767 if (entry_parm && store_args_on_stack)
3f1f8d8c 7768 {
4730fa4f
GRK		 7769 if (next_arg == 0
7770 && DECL_NAME (cur_arg)
7771 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7772 "__builtin_va_alist"))
7773 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7774 "va_alist"))))
7775 {
7776 last_arg_is_vararg_marker = 1;
918e70dd
AO		 7777 if (GET_CODE (entry_parm) == REG)
7778 regno = REGNO (entry_parm);
7779 else
7780 regno = GP_ARG_LAST + 1;
4730fa4f
GRK		 7781 break;
7782 }
3f1f8d8c 7783 else
4730fa4f
GRK		 7784 {
7785 int words;
9e5ac782
CP		 7786
7787 if (GET_CODE (entry_parm) != REG)
7788 abort ();
7789
4730fa4f
GRK		 7790 /* passed in a register, so will get homed automatically */
7791 if (GET_MODE (entry_parm) == BLKmode)
7792 words = (int_size_in_bytes (passed_type) + 3) / 4;
7793 else
7794 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
3f1f8d8c 7795
4730fa4f
GRK		 7796 regno = REGNO (entry_parm) + words - 1;
7797 }
3f1f8d8c
MM		 7798 }
7799 else
7800 {
7801 regno = GP_ARG_LAST+1;
7802 break;
7803 }
cee98a59
MM		 7804 }
7805
f5963e61
JL		 7806 /* In order to pass small structures by value in registers compatibly with
7807 the MIPS compiler, we need to shift the value into the high part of the
7808 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7809 adjustments to be made as the next_arg_reg variable, so we split up the
7810 insns, and emit them separately. */
cee98a59 7811
3f1f8d8c 7812 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
f5963e61 7813 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
3f1f8d8c
MM		 7814 {
7815 rtvec adjust = XVEC (next_arg_reg, 0);
7816 int num = GET_NUM_ELEM (adjust);
cee98a59 7817
3f1f8d8c 7818 for (i = 0; i < num; i++)
cee98a59 7819 {
71641c15
RH		 7820 rtx insn, pattern;
7821
7822 pattern = RTVEC_ELT (adjust, i);
3f1f8d8c
MM		 7823 if (GET_CODE (pattern) != SET
7824 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
c725bd79 7825 abort_with_insn (pattern, "insn is not a shift");
3f1f8d8c 7826 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
71641c15
RH		 7827
7828 insn = emit_insn (pattern);
7829
7830 /* Global life information isn't valid at this point, so we
7831 can't check whether these shifts are actually used. Mark
7832 them MAYBE_DEAD so that flow2 will remove them, and not
7833 complain about dead code in the prologue. */
7834 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7835 REG_NOTES (insn));
cee98a59 7836 }
3f1f8d8c 7837 }
cee98a59 7838
ffa9d0b1
JW		 7839 tsize = compute_frame_size (get_frame_size ());
7840
3f1f8d8c
MM		 7841 /* If this function is a varargs function, store any registers that
7842 would normally hold arguments ($4 - $7) on the stack. */
9e5ac782 7843 if (store_args_on_stack
33563487 7844 && ((TYPE_ARG_TYPES (fntype) != 0
f5963e61
JL		 7845 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7846 != void_type_node))
4730fa4f 7847 || last_arg_is_vararg_marker))
3f1f8d8c 7848 {
ffa9d0b1
JW		 7849 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7850 rtx ptr = stack_pointer_rtx;
7851
987ba558 7852 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
ade6c319 7853 if (TARGET_ABICALLS)
ffa9d0b1
JW		 7854 offset += tsize;
7855
0fb5ac6f 7856 for (; regno <= GP_ARG_LAST; regno++)
cee98a59 7857 {
ffa9d0b1
JW		 7858 if (offset != 0)
7859 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
bfed8dac
JL		 7860 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7861 gen_rtx (REG, gpr_mode, regno));
7862
7863 offset += GET_MODE_SIZE (gpr_mode);
cee98a59
MM		 7864 }
7865 }
7866
2bcb2ab3
GK		 7867 /* If we are using the entry pseudo instruction, it will
7868 automatically subtract 32 from the stack pointer, so we don't
7869 need to. The entry pseudo instruction is emitted by
7870 function_prologue. */
7871 if (mips_entry && ! mips_can_use_return_insn ())
7872 {
7873 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7874 {
7875 rtx insn;
7876
7877 /* If we are using a frame pointer with a small stack frame,
7878 we need to initialize it here since it won't be done
7879 below. */
7880 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7881 {
7882 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 7883 if (Pmode == DImode)
2bcb2ab3
GK		 7884 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7885 stack_pointer_rtx,
7886 incr));
7887 else
7888 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7889 stack_pointer_rtx,
7890 incr));
7891 }
1eeed24e 7892 else if (Pmode == DImode)
f5963e61
JL		 7893 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7894 stack_pointer_rtx));
2bcb2ab3 7895 else
f5963e61
JL		 7896 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7897 stack_pointer_rtx));
2bcb2ab3
GK		 7898
7899 RTX_FRAME_RELATED_P (insn) = 1;
7900 }
7901
7902 /* We may need to save $18, if it is used to call a function
7903 which may return a floating point value. Set up a sequence
7904 of instructions to do so. Later on we emit them at the right
7905 moment. */
b2471838 7906 if (TARGET_MIPS16 && BITSET_P (cfun->machine->frame.mask, 18))
2bcb2ab3 7907 {
bfed8dac 7908 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
2bcb2ab3
GK		 7909 long gp_offset, base_offset;
7910
b2471838
RS		 7911 gp_offset = cfun->machine->frame.gp_sp_offset;
7912 if (BITSET_P (cfun->machine->frame.mask, 16))
2bcb2ab3 7913 gp_offset -= UNITS_PER_WORD;
b2471838 7914 if (BITSET_P (cfun->machine->frame.mask, 17))
2bcb2ab3 7915 gp_offset -= UNITS_PER_WORD;
b2471838 7916 if (BITSET_P (cfun->machine->frame.mask, 31))
2bcb2ab3
GK		 7917 gp_offset -= UNITS_PER_WORD;
7918 if (tsize > 32767)
7919 base_offset = tsize;
7920 else
7921 base_offset = 0;
7922 start_sequence ();
7923 emit_move_insn (reg_rtx,
bfed8dac
JL		 7924 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7925 emit_move_insn (gen_rtx (MEM, gpr_mode,
2bcb2ab3
GK		 7926 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7927 GEN_INT (gp_offset
7928 - base_offset))),
7929 reg_rtx);
2f937369 7930 reg_18_save = get_insns ();
2bcb2ab3
GK		 7931 end_sequence ();
7932 }
7933
7934 if (tsize > 32)
7935 tsize -= 32;
7936 else
7937 {
7938 tsize = 0;
7939 if (reg_18_save != NULL_RTX)
7940 emit_insn (reg_18_save);
7941 }
7942 }
7943
cee98a59
MM		 7944 if (tsize > 0)
7945 {
0fb5ac6f 7946 rtx tsize_rtx = GEN_INT (tsize);
cee98a59 7947
2bcb2ab3
GK		 7948 /* If we are doing svr4-abi, sp move is done by
7949 function_prologue. In mips16 mode with a large frame, we
7950 save the registers before adjusting the stack. */
a53f72db 7951 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3 7952 && (!TARGET_MIPS16 || tsize <= 32767))
0fb5ac6f 7953 {
5b0f0db6 7954 rtx adjustment_rtx;
a94dbf2c 7955
ffa9d0b1
JW		 7956 if (tsize > 32767)
7957 {
67070ffe
RS		 7958 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7959 emit_move_insn (adjustment_rtx, tsize_rtx);
ffa9d0b1 7960 }
67070ffe
RS		 7961 else
7962 adjustment_rtx = tsize_rtx;
cee98a59 7963
1eeed24e 7964 if (Pmode == DImode)
5b0f0db6
RS		 7965 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7966 adjustment_rtx));
147255d8 7967 else
5b0f0db6
RS		 7968 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7969 adjustment_rtx));
a94dbf2c 7970
5b0f0db6
RS		 7971 mips_set_frame_expr
7972 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7973 plus_constant (stack_pointer_rtx, -tsize)));
ffa9d0b1 7974 }
cee98a59 7975
2bcb2ab3 7976 if (! mips_entry)
a8b4881f 7977 save_restore_insns (1, tmp_rtx, tsize);
2bcb2ab3
GK		 7978 else if (reg_18_save != NULL_RTX)
7979 emit_insn (reg_18_save);
cee98a59 7980
a53f72db 7981 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3
GK		 7982 && TARGET_MIPS16
7983 && tsize > 32767)
147255d8 7984 {
2bcb2ab3 7985 rtx reg_rtx;
a94dbf2c 7986
2bcb2ab3
GK		 7987 if (!frame_pointer_needed)
7988 abort ();
7989
c3499f00 7990 reg_rtx = gen_rtx (REG, Pmode, 3);
2bcb2ab3
GK		 7991 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7992 emit_move_insn (reg_rtx, tsize_rtx);
1eeed24e 7993 if (Pmode == DImode)
2bcb2ab3
GK		 7994 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7995 hard_frame_pointer_rtx,
7996 reg_rtx));
7997 else
7998 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7999 hard_frame_pointer_rtx,
8000 reg_rtx));
8001 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
8002 }
8003
8004 if (frame_pointer_needed)
8005 {
8006 rtx insn = 0;
8007
8008 /* On the mips16, we encourage the use of unextended
8009 instructions when using the frame pointer by pointing the
8010 frame pointer ahead of the argument space allocated on
8011 the stack. */
a53f72db 8012 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3
GK		 8013 && TARGET_MIPS16
8014 && tsize > 32767)
8015 {
8016 /* In this case, we have already copied the stack
8017 pointer into the frame pointer, above. We need only
8018 adjust for the outgoing argument size. */
8019 if (current_function_outgoing_args_size != 0)
8020 {
8021 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 8022 if (Pmode == DImode)
2bcb2ab3
GK		 8023 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8024 hard_frame_pointer_rtx,
8025 incr));
8026 else
8027 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
8028 hard_frame_pointer_rtx,
8029 incr));
8030 }
8031 }
8032 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
8033 {
8034 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 8035 if (Pmode == DImode)
2bcb2ab3
GK		 8036 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8037 stack_pointer_rtx,
8038 incr));
8039 else
8040 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
8041 stack_pointer_rtx,
8042 incr));
8043 }
1eeed24e 8044 else if (Pmode == DImode)
f5963e61
JL		 8045 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
8046 stack_pointer_rtx));
147255d8 8047 else
f5963e61
JL		 8048 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
8049 stack_pointer_rtx));
a94dbf2c 8050
8fa4e1b4
JL		 8051 if (insn)
8052 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 8053 }
33563487 8054
a53f72db 8055 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
e5e809f4 8056 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
c5c76735 8057 gen_rtx_REG (DImode, 25)));
cee98a59 8058 }
d8d5b1e1
MM		 8059
8060 /* If we are profiling, make sure no instructions are scheduled before
8061 the call to mcount. */
8062
70f4f91c 8063 if (current_function_profile)
d8d5b1e1 8064 emit_insn (gen_blockage ());
cee98a59 8065}
cee98a59 8066\f
f5963e61 8067/* Do any necessary cleanup after a function to restore stack, frame,
987ba558 8068 and regs. */
cee98a59 8069
3a6ee9f4 8070#define RA_MASK BITMASK_HIGH /* 1 << 31 */
4d889da9 8071#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
b5e9dd03 8072
08c148a8
NB		 8073static void
8074mips_output_function_epilogue (file, size)
38831dfe
KG		 8075 FILE *file ATTRIBUTE_UNUSED;
8076 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
cee98a59 8077{
08c148a8 8078 const char *fnname = ""; /* FIXME: Correct initialisation? */
366356d3 8079 rtx string;
cee98a59 8080
993cd990 8081#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52
RK		 8082 /* Get the function name the same way that toplev.c does before calling
8083 assemble_start_function. This is needed so that the name used here
8084 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8085 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8086
e9a25f70
JL		 8087 if (!flag_inhibit_size_directive)
8088 {
8089 fputs ("\t.end\t", file);
8090 assemble_name (file, fnname);
8091 fputs ("\n", file);
8092 }
993cd990 8093#endif
cee98a59
MM		 8094
8095 if (TARGET_STATS)
8096 {
b2471838
RS		 8097 int num_gp_regs = cfun->machine->frame.gp_reg_size / 4;
8098 int num_fp_regs = cfun->machine->frame.fp_reg_size / 8;
f5963e61 8099 int num_regs = num_gp_regs + num_fp_regs;
bd9f1972 8100 const char *name = fnname;
ab78d4a8
MM		 8101
8102 if (name[0] == '*')
8103 name++;
cee98a59
MM		 8104
8105 dslots_load_total += num_regs;
8106
cee98a59 8107 fprintf (stderr,
38831dfe 8108 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
f5963e61 8109 name, frame_pointer_needed ? 'y' : 'n',
b2471838 8110 (cfun->machine->frame.mask & RA_MASK) != 0 ? 'n' : 'y',
f5963e61
JL		 8111 current_function_calls_alloca ? 'y' : 'n',
8112 current_function_calls_setjmp ? 'y' : 'n',
b2471838 8113 cfun->machine->frame.total_size,
f5963e61 8114 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
cee98a59
MM		 8115 dslots_load_total, dslots_load_filled,
8116 dslots_jump_total, dslots_jump_filled,
8117 num_refs[0], num_refs[1], num_refs[2]);
ddd8ab48 8118
ddd8ab48 8119 fputc ('\n', stderr);
cee98a59
MM		 8120 }
8121
8122 /* Reset state info for each function. */
f5963e61
JL		 8123 inside_function = 0;
8124 ignore_line_number = 0;
8125 dslots_load_total = 0;
8126 dslots_jump_total = 0;
cee98a59
MM		 8127 dslots_load_filled = 0;
8128 dslots_jump_filled = 0;
f5963e61
JL		 8129 num_refs[0] = 0;
8130 num_refs[1] = 0;
8131 num_refs[2] = 0;
8132 mips_load_reg = 0;
8133 mips_load_reg2 = 0;
cee98a59 8134
2bcb2ab3
GK		 8135 while (string_constants != NULL)
8136 {
8137 struct string_constant *next;
8138
8139 next = string_constants->next;
8140 free (string_constants);
8141 string_constants = next;
8142 }
8143
366356d3
RS		 8144 /* If any following function uses the same strings as this one, force
8145 them to refer those strings indirectly. Nearby functions could
8146 refer them using pc-relative addressing, but it isn't safe in
8147 general. For instance, some functions may be placed in sections
8148 other than .text, and we don't know whether they be close enough
8149 to this one. In large files, even other .text functions can be
8150 too far away. */
8151 for (string = mips16_strings; string != 0; string = XEXP (string, 1))
8152 SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
8153 free_EXPR_LIST_list (&mips16_strings);
8154
cee98a59
MM		 8155 /* Restore the output file if optimizing the GP (optimizing the GP causes
8156 the text to be diverted to a tempfile, so that data decls come before
8157 references to the data). */
f99ffb60
RH		 8158 if (TARGET_FILE_SWITCHING)
8159 {
8160 asm_out_file = asm_out_data_file;
8161 data_section ();
8162 }
cee98a59 8163}
0fb5ac6f 8164\f
cafe096b
EC		 8165/* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
8166 if this epilogue precedes a sibling call, false if it is for a normal
8167 "epilogue" pattern. */
0fb5ac6f
MM		 8168
8169void
cafe096b
EC		 8170mips_expand_epilogue (sibcall_p)
8171 int sibcall_p;
0fb5ac6f 8172{
b2471838 8173 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
0fb5ac6f 8174 rtx tsize_rtx = GEN_INT (tsize);
7bea35e7 8175 rtx tmp_rtx = (rtx)0;
0fb5ac6f 8176
cafe096b 8177 if (!sibcall_p && mips_can_use_return_insn ())
1f2d8f51 8178 {
47eb2ca8 8179 emit_jump_insn (gen_return ());
1f2d8f51
JL		 8180 return;
8181 }
8182
2bcb2ab3
GK		 8183 if (mips_entry && ! mips_can_use_return_insn ())
8184 tsize -= 32;
8185
8186 if (tsize > 32767 && ! TARGET_MIPS16)
0fb5ac6f 8187 {
c5c76735 8188 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
0fb5ac6f
MM		 8189 emit_move_insn (tmp_rtx, tsize_rtx);
8190 tsize_rtx = tmp_rtx;
8191 }
8192
8193 if (tsize > 0)
8194 {
2bcb2ab3
GK		 8195 long orig_tsize = tsize;
8196
0fb5ac6f 8197 if (frame_pointer_needed)
147255d8 8198 {
1f2d8f51 8199 emit_insn (gen_blockage ());
2bcb2ab3
GK		 8200
8201 /* On the mips16, the frame pointer is offset from the stack
8202 pointer by current_function_outgoing_args_size. We
8203 account for that by changing tsize. Note that this can
8204 actually make tsize negative. */
8205 if (TARGET_MIPS16)
8206 {
8207 tsize -= current_function_outgoing_args_size;
8208
282cb01b 8209 /* If we have a large frame, it's easier to add to $6
2bcb2ab3
GK		 8210 than to $sp, since the mips16 has no instruction to
8211 add a register to $sp. */
8212 if (orig_tsize > 32767)
8213 {
c3499f00 8214 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
2bcb2ab3
GK		 8215
8216 emit_move_insn (g6_rtx, GEN_INT (tsize));
1eeed24e 8217 if (Pmode == DImode)
2bcb2ab3
GK		 8218 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8219 hard_frame_pointer_rtx,
8220 g6_rtx));
8221 else
8222 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
8223 hard_frame_pointer_rtx,
8224 g6_rtx));
8225 tsize = 0;
8226 }
7dac2f89 8227
a4dee8a5
GK		 8228 if (tsize && tsize != orig_tsize)
8229 tsize_rtx = GEN_INT (tsize);
2bcb2ab3
GK		 8230 }
8231
1eeed24e 8232 if (Pmode == DImode)
2bcb2ab3 8233 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
147255d8 8234 else
2bcb2ab3 8235 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
147255d8 8236 }
f5963e61 8237
ab00eb0a
JW		 8238 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
8239 are going to restore it, then we must emit a blockage insn to
8240 prevent the scheduler from moving the restore out of the epilogue. */
a53f72db 8241 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
b2471838 8242 && (cfun->machine->frame.mask
ab00eb0a
JW		 8243 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
8244 emit_insn (gen_blockage ());
0fb5ac6f 8245
a8b4881f 8246 save_restore_insns (0, tmp_rtx, orig_tsize);
0fb5ac6f 8247
2bcb2ab3
GK		 8248 /* In mips16 mode with a large frame, we adjust the stack
8249 pointer before restoring the registers. In this case, we
8250 should always be using a frame pointer, so everything should
8251 have been handled above. */
8252 if (tsize > 32767 && TARGET_MIPS16)
8253 abort ();
8254
9e800206
RH		 8255 if (current_function_calls_eh_return)
8256 {
8257 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
8258 if (Pmode == DImode)
8259 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
8260 else
8261 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
8262 tsize_rtx = eh_ofs;
8263 }
8264
1f2d8f51 8265 emit_insn (gen_blockage ());
9e800206
RH		 8266
8267 if (tsize != 0 || current_function_calls_eh_return)
8268 {
cafe096b 8269 if (!TARGET_MIPS16 || !current_function_calls_eh_return)
282cb01b
EC		 8270 {
8271 if (Pmode == DImode)
8272 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
8273 tsize_rtx));
8274 else
8275 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8276 tsize_rtx));
8277 }
9e800206 8278 else
282cb01b
EC		 8279 {
8280 /* We need to work around not being able to add a register
8281 to the stack pointer directly. Use register $6 as an
8282 intermediate step. */
8283
8284 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
8285
8286 if (Pmode == DImode)
8287 {
8288 emit_insn (gen_movdi (g6_rtx, stack_pointer_rtx));
8289 emit_insn (gen_adddi3 (g6_rtx, g6_rtx, tsize_rtx));
8290 emit_insn (gen_movdi (stack_pointer_rtx, g6_rtx));
8291 }
8292 else
8293 {
8294 emit_insn (gen_movsi (g6_rtx, stack_pointer_rtx));
8295 emit_insn (gen_addsi3 (g6_rtx, g6_rtx, tsize_rtx));
8296 emit_insn (gen_movsi (stack_pointer_rtx, g6_rtx));
8297 }
8298 }
8299
9e800206 8300 }
0fb5ac6f 8301 }
cafe096b
EC		 8302 if (!sibcall_p)
8303 {
8304 /* The mips16 loads the return address into $7, not $31. */
8305 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
8306 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
8307 GP_REG_FIRST + 7)));
8308 else
8309 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
8310 GP_REG_FIRST + 31)));
8311 }
cee98a59 8312}
cee98a59 8313\f
f5963e61 8314/* Return nonzero if this function is known to have a null epilogue.
cee98a59
MM		 8315 This allows the optimizer to omit jumps to jumps if no stack
8316 was created. */
8317
8318int
1f2d8f51 8319mips_can_use_return_insn ()
cee98a59 8320{
3f26edaa
RS		 8321 tree return_type;
8322
f5963e61 8323 if (! reload_completed)
cee98a59
MM		 8324 return 0;
8325
70f4f91c 8326 if (regs_ever_live[31] || current_function_profile)
1f2d8f51
JL		 8327 return 0;
8328
3f26edaa
RS		 8329 return_type = DECL_RESULT (current_function_decl);
8330
2bcb2ab3
GK		 8331 /* In mips16 mode, a function which returns a floating point value
8332 needs to arrange to copy the return value into the floating point
8333 registers. */
8334 if (TARGET_MIPS16
8335 && mips16_hard_float
3f26edaa
RS		 8336 && ! aggregate_value_p (return_type)
8337 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
8338 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
2bcb2ab3
GK		 8339 return 0;
8340
b2471838
RS		 8341 if (cfun->machine->frame.initialized)
8342 return cfun->machine->frame.total_size == 0;
cee98a59 8343
f5963e61 8344 return compute_frame_size (get_frame_size ()) == 0;
cee98a59 8345}
9753d4e4 8346\f
a0ab749a 8347/* Returns nonzero if X contains a SYMBOL_REF. */
d660677d
MM		 8348
8349static int
8350symbolic_expression_p (x)
8351 rtx x;
8352{
8353 if (GET_CODE (x) == SYMBOL_REF)
8354 return 1;
8355
8356 if (GET_CODE (x) == CONST)
8357 return symbolic_expression_p (XEXP (x, 0));
7dac2f89 8358
d660677d
MM		 8359 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
8360 return symbolic_expression_p (XEXP (x, 0));
8361
8362 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
8363 || GET_RTX_CLASS (GET_CODE (x)) == '2')
8364 return (symbolic_expression_p (XEXP (x, 0))
8365 || symbolic_expression_p (XEXP (x, 1)));
8366
8367 return 0;
8368}
8369
9753d4e4
JW		 8370/* Choose the section to use for the constant rtx expression X that has
8371 mode MODE. */
8372
b64a1b53
RH		 8373static void
8374mips_select_rtx_section (mode, x, align)
9753d4e4 8375 enum machine_mode mode;
b64a1b53
RH		 8376 rtx x;
8377 unsigned HOST_WIDE_INT align;
9753d4e4 8378{
2bcb2ab3
GK		 8379 if (TARGET_MIPS16)
8380 {
52ecdfda
JW		 8381 /* In mips16 mode, the constant table always goes in the same section
8382 as the function, so that constants can be loaded using PC relative
2bcb2ab3 8383 addressing. */
52ecdfda 8384 function_section (current_function_decl);
2bcb2ab3
GK		 8385 }
8386 else if (TARGET_EMBEDDED_DATA)
9753d4e4
JW		 8387 {
8388 /* For embedded applications, always put constants in read-only data,
8389 in order to reduce RAM usage. */
b64a1b53 8390 mergeable_constant_section (mode, align, 0);
9753d4e4
JW		 8391 }
8392 else
8393 {
8394 /* For hosted applications, always put constants in small data if
8395 possible, as this gives the best performance. */
b64a1b53 8396 /* ??? Consider using mergable small data sections. */
7dac2f89 8397
0da9afa6 8398 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
9753d4e4 8399 && mips_section_threshold > 0)
8bd8e198 8400 SMALL_DATA_SECTION ();
d660677d 8401 else if (flag_pic && symbolic_expression_p (x))
b64a1b53
RH		 8402 {
8403 if (targetm.have_named_sections)
8404 named_section (NULL_TREE, ".data.rel.ro", 3);
8405 else
8406 data_section ();
8407 }
9753d4e4 8408 else
b64a1b53 8409 mergeable_constant_section (mode, align, 0);
9753d4e4
JW		 8410 }
8411}
8412
8413/* Choose the section to use for DECL. RELOC is true if its value contains
5f680ab6
DD		 8414 any relocatable expression.
8415
fb49053f 8416 ??? This would be fixed by implementing targetm.is_small_data_p. */
9753d4e4 8417
ae46c4e0
RH		 8418static void
8419mips_select_section (decl, reloc, align)
9753d4e4
JW		 8420 tree decl;
8421 int reloc;
ae46c4e0 8422 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
9753d4e4
JW		 8423{
8424 int size = int_size_in_bytes (TREE_TYPE (decl));
8425
2bcb2ab3 8426 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
92544bdf
ILT		 8427 && TREE_CODE (decl) == STRING_CST
8428 && !flag_writable_strings)
f5963e61
JL		 8429 /* For embedded position independent code, put constant strings in the
8430 text section, because the data section is limited to 64K in size.
8431 For mips16 code, put strings in the text section so that a PC
8432 relative load instruction can be used to get their address. */
8433 text_section ();
92544bdf 8434 else if (TARGET_EMBEDDED_DATA)
9753d4e4
JW		 8435 {
8436 /* For embedded applications, always put an object in read-only data
8437 if possible, in order to reduce RAM usage. */
8438
1d306530
JW		 8439 if (((TREE_CODE (decl) == VAR_DECL
8440 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
9753d4e4
JW		 8441 && DECL_INITIAL (decl)
8442 && (DECL_INITIAL (decl) == error_mark_node
8443 || TREE_CONSTANT (DECL_INITIAL (decl))))
8444 /* Deal with calls from output_constant_def_contents. */
8445 || (TREE_CODE (decl) != VAR_DECL
8446 && (TREE_CODE (decl) != STRING_CST
8447 || !flag_writable_strings)))
8448 && ! (flag_pic && reloc))
d48bc59a 8449 readonly_data_section ();
9753d4e4 8450 else if (size > 0 && size <= mips_section_threshold)
8bd8e198 8451 SMALL_DATA_SECTION ();
9753d4e4
JW		 8452 else
8453 data_section ();
8454 }
8455 else
8456 {
8457 /* For hosted applications, always put an object in small data if
8458 possible, as this gives the best performance. */
8459
8460 if (size > 0 && size <= mips_section_threshold)
8bd8e198 8461 SMALL_DATA_SECTION ();
1d306530
JW		 8462 else if (((TREE_CODE (decl) == VAR_DECL
8463 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
9753d4e4
JW		 8464 && DECL_INITIAL (decl)
8465 && (DECL_INITIAL (decl) == error_mark_node
8466 || TREE_CONSTANT (DECL_INITIAL (decl))))
8467 /* Deal with calls from output_constant_def_contents. */
8468 || (TREE_CODE (decl) != VAR_DECL
8469 && (TREE_CODE (decl) != STRING_CST
8470 || !flag_writable_strings)))
8471 && ! (flag_pic && reloc))
d48bc59a 8472 readonly_data_section ();
9753d4e4
JW		 8473 else
8474 data_section ();
8475 }
8476}
fb49053f
RH		 8477
8478/* When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
8479 small objects.
8480
8481 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
8482 symbols which are not in the .text section.
8483
8484 When generating mips16 code, SYMBOL_REF_FLAG is set for string
8485 constants which are put in the .text section. We also record the
8486 total length of all such strings; this total is used to decide
8487 whether we need to split the constant table, and need not be
8488 precisely correct.
8489
8490 When not mips16 code nor embedded PIC, if a symbol is in a
a920aefe 8491 gp addressable section, SYMBOL_REF_FLAG is set prevent gcc from
fb49053f
RH		 8492 splitting the reference so that gas can generate a gp relative
8493 reference.
8494
8495 When TARGET_EMBEDDED_DATA is set, we assume that all const
8496 variables will be stored in ROM, which is too far from %gp to use
8497 %gprel addressing. Note that (1) we include "extern const"
8498 variables in this, which mips_select_section doesn't, and (2) we
8499 can't always tell if they're really const (they might be const C++
8500 objects with non-const constructors), so we err on the side of
8501 caution and won't use %gprel anyway (otherwise we'd have to defer
8502 this decision to the linker/loader). The handling of extern consts
8503 is why the DECL_INITIAL macros differ from mips_select_section. */
8504
8505static void
c6a2438a 8506mips_encode_section_info (decl, rtl, first)
fb49053f 8507 tree decl;
c6a2438a 8508 rtx rtl;
fb49053f
RH		 8509 int first;
8510{
cafe096b
EC		 8511 rtx symbol;
8512
8513 if (GET_CODE (rtl) != MEM)
8514 return;
8515
8516 symbol = XEXP (rtl, 0);
8517
8518 if (GET_CODE (symbol) != SYMBOL_REF)
8519 return;
8520
fb49053f
RH		 8521 if (TARGET_MIPS16)
8522 {
8523 if (first && TREE_CODE (decl) == STRING_CST
cafe096b
EC		 8524 && ! flag_writable_strings
8525 /* If this string is from a function, and the function will
8526 go in a gnu linkonce section, then we can't directly
8527 access the string. This gets an assembler error
8528 "unsupported PC relative reference to different section".
8529 If we modify SELECT_SECTION to put it in function_section
8530 instead of text_section, it still fails because
8531 DECL_SECTION_NAME isn't set until assemble_start_function.
8532 If we fix that, it still fails because strings are shared
8533 among multiple functions, and we have cross section
8534 references again. We force it to work by putting string
8535 addresses in the constant pool and indirecting. */
8536 && (! current_function_decl
8537 || ! DECL_ONE_ONLY (current_function_decl)))
8538 {
8539 mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
8540 SYMBOL_REF_FLAG (symbol) = 1;
8541 mips_string_length += TREE_STRING_LENGTH (decl);
8542 }
fb49053f
RH		 8543 }
8544
8545 if (TARGET_EMBEDDED_DATA
8546 && (TREE_CODE (decl) == VAR_DECL
cafe096b 8547 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl))
fb49053f 8548 && (!DECL_INITIAL (decl)
cafe096b 8549 || TREE_CONSTANT (DECL_INITIAL (decl))))
fb49053f 8550 {
cafe096b 8551 SYMBOL_REF_FLAG (symbol) = 0;
fb49053f
RH		 8552 }
8553
8554 else if (TARGET_EMBEDDED_PIC)
8555 {
8556 if (TREE_CODE (decl) == VAR_DECL)
cafe096b 8557 SYMBOL_REF_FLAG (symbol) = 1;
fb49053f 8558 else if (TREE_CODE (decl) == FUNCTION_DECL)
cafe096b 8559 SYMBOL_REF_FLAG (symbol) = 0;
fb49053f 8560 else if (TREE_CODE (decl) == STRING_CST
cafe096b
EC		 8561 && ! flag_writable_strings)
8562 SYMBOL_REF_FLAG (symbol) = 0;
8563 else
8564 SYMBOL_REF_FLAG (symbol) = 1;
8565 }
8566
8567 else if (TARGET_ABICALLS)
8568 {
8569 /* Mark the symbol if we should treat it as SYMBOL_GOT_LOCAL.
8570 There are three cases to consider:
8571
8572 - o32 PIC (either with or without explicit relocs)
8573 - n32/n64 PIC without explict relocs
8574 - n32/n64 PIC with explicit relocs
8575
8576 In the first case, both local and global accesses will use an
8577 R_MIPS_GOT16 relocation. We must correctly predict which of
8578 the two semantics (local or global) the assembler and linker
8579 will apply. The choice doesn't depend on the symbol's
8580 visibility, so we deliberately ignore decl_visiblity and
8581 binds_local_p here.
8582
8583 In the second case, the assembler will not use R_MIPS_GOT16
8584 relocations, but it chooses between local and global accessees
8585 in the same way as for o32 PIC.
8586
8587 In the third case we have more freedom since both forms of
8588 access will work for any kind of symbol. However, there seems
8589 little point in doing things differently. */
8590 if (DECL_P (decl) && TREE_PUBLIC (decl))
8591 SYMBOL_REF_FLAG (symbol) = 0;
fb49053f 8592 else
cafe096b 8593 SYMBOL_REF_FLAG (symbol) = 1;
fb49053f
RH		 8594 }
8595
8596 else if (TREE_CODE (decl) == VAR_DECL
cafe096b
EC		 8597 && DECL_SECTION_NAME (decl) != NULL_TREE
8598 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
8599 ".sdata")
8600 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
8601 ".sbss")))
fb49053f 8602 {
cafe096b 8603 SYMBOL_REF_FLAG (symbol) = 1;
fb49053f
RH		 8604 }
8605
8606 /* We can not perform GP optimizations on variables which are in
8607 specific sections, except for .sdata and .sbss which are
8608 handled above. */
8609 else if (TARGET_GP_OPT && TREE_CODE (decl) == VAR_DECL
cafe096b
EC		 8610 && DECL_SECTION_NAME (decl) == NULL_TREE
8611 && ! (TARGET_MIPS16 && TREE_PUBLIC (decl)
8612 && (DECL_COMMON (decl)
8613 || DECL_ONE_ONLY (decl)
8614 || DECL_WEAK (decl))))
fb49053f
RH		 8615 {
8616 int size = int_size_in_bytes (TREE_TYPE (decl));
8617
8618 if (size > 0 && size <= mips_section_threshold)
cafe096b 8619 SYMBOL_REF_FLAG (symbol) = 1;
fb49053f
RH		 8620 }
8621
fb49053f 8622}
cafe096b
EC		 8623
8624
33563487 8625\f
c6e6f5c1
RH		 8626/* Return register to use for a function return value with VALTYPE for
8627 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
33563487
JW		 8628
8629rtx
c6e6f5c1 8630mips_function_value (valtype, func, mode)
33563487 8631 tree valtype;
38831dfe 8632 tree func ATTRIBUTE_UNUSED;
c6e6f5c1 8633 enum machine_mode mode;
33563487
JW		 8634{
8635 int reg = GP_RETURN;
c6e6f5c1
RH		 8636 enum mode_class mclass;
8637 int unsignedp = 1;
8638
8639 if (valtype)
8640 {
8641 mode = TYPE_MODE (valtype);
8642 unsignedp = TREE_UNSIGNED (valtype);
05ed1296
RH		 8643
8644 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8645 the mode just as PROMOTE_MODE does. */
8646 mode = promote_mode (valtype, mode, &unsignedp, 1);
c6e6f5c1
RH		 8647 }
8648 mclass = GET_MODE_CLASS (mode);
2bcb2ab3 8649
8a381273 8650 if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
3f26edaa 8651 reg = FP_RETURN;
f5963e61 8652
8a381273
AO		 8653 else if (mclass == MODE_FLOAT && mode == TFmode)
8654 /* long doubles are really split between f0 and f2, not f1. Eek.
8655 Use DImode for each component, since GCC wants integer modes
8656 for subregs. */
8657 return gen_rtx_PARALLEL
8658 (VOIDmode,
8659 gen_rtvec (2,
8660 gen_rtx_EXPR_LIST (VOIDmode,
8661 gen_rtx_REG (DImode, FP_RETURN),
8662 GEN_INT (0)),
8663 gen_rtx_EXPR_LIST (VOIDmode,
8664 gen_rtx_REG (DImode, FP_RETURN + 2),
8665 GEN_INT (GET_MODE_SIZE (mode) / 2))));
cafe096b 8666
8a381273 8667
3f26edaa 8668 else if (mclass == MODE_COMPLEX_FLOAT
8a381273 8669 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
f9ad2367 8670 {
c6e6f5c1 8671 enum machine_mode cmode = GET_MODE_INNER (mode);
3f26edaa
RS		 8672
8673 return gen_rtx_PARALLEL
8674 (VOIDmode,
8675 gen_rtvec (2,
8676 gen_rtx_EXPR_LIST (VOIDmode,
8677 gen_rtx_REG (cmode, FP_RETURN),
8678 GEN_INT (0)),
8679 gen_rtx_EXPR_LIST (VOIDmode,
8680 gen_rtx_REG (cmode, FP_RETURN + FP_INC),
8681 GEN_INT (GET_MODE_SIZE (cmode)))));
f9ad2367
AH		 8682 }
8683
c6e6f5c1 8684 else if (valtype && TREE_CODE (valtype) == RECORD_TYPE
7dac2f89
EC		 8685 && mips_abi != ABI_32
8686 && mips_abi != ABI_O64
a53f72db 8687 && mips_abi != ABI_EABI)
33563487
JW		 8688 {
8689 /* A struct with only one or two floating point fields is returned in
8690 the floating point registers. */
320aba9c 8691 tree field, fields[2];
33563487
JW		 8692 int i;
8693
8694 for (i = 0, field = TYPE_FIELDS (valtype); field;
320aba9c 8695 field = TREE_CHAIN (field))
33563487 8696 {
320aba9c
JW		 8697 if (TREE_CODE (field) != FIELD_DECL)
8698 continue;
f5963e61 8699
33563487
JW		 8700 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
8701 break;
320aba9c
JW		 8702
8703 fields[i++] = field;
33563487 8704 }
7dac2f89 8705
1417e9bd 8706 /* Must check i, so that we reject structures with no elements. */
a20b7b05
JW		 8707 if (! field)
8708 {
8709 if (i == 1)
8710 {
320aba9c
JW		 8711 /* The structure has DImode, but we don't allow DImode values
8712 in FP registers, so we use a PARALLEL even though it isn't
8713 strictly necessary. */
8714 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
8715
c5c76735
JL		 8716 return gen_rtx_PARALLEL
8717 (mode,
8718 gen_rtvec (1,
8719 gen_rtx_EXPR_LIST (VOIDmode,
8720 gen_rtx_REG (field_mode,
8721 FP_RETURN),
8722 const0_rtx)));
a20b7b05 8723 }
f5963e61 8724
a20b7b05
JW		 8725 else if (i == 2)
8726 {
8727 enum machine_mode first_mode
320aba9c 8728 = TYPE_MODE (TREE_TYPE (fields[0]));
a20b7b05 8729 enum machine_mode second_mode
320aba9c 8730 = TYPE_MODE (TREE_TYPE (fields[1]));
75131237
RK		 8731 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
8732 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
a20b7b05 8733
c5c76735
JL		 8734 return gen_rtx_PARALLEL
8735 (mode,
8736 gen_rtvec (2,
8737 gen_rtx_EXPR_LIST (VOIDmode,
8738 gen_rtx_REG (first_mode,
8739 FP_RETURN),
75131237 8740 GEN_INT (first_offset)),
c5c76735
JL		 8741 gen_rtx_EXPR_LIST (VOIDmode,
8742 gen_rtx_REG (second_mode,
8743 FP_RETURN + 2),
75131237 8744 GEN_INT (second_offset))));
a20b7b05
JW		 8745 }
8746 }
33563487
JW		 8747 }
8748
c5c76735 8749 return gen_rtx_REG (mode, reg);
33563487 8750}
293a36eb
ILT		 8751
8752/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8753 nonzero when an argument must be passed by reference. */
8754
8755int
8756function_arg_pass_by_reference (cum, mode, type, named)
4d72536e 8757 const CUMULATIVE_ARGS *cum;
293a36eb
ILT		 8758 enum machine_mode mode;
8759 tree type;
38831dfe 8760 int named ATTRIBUTE_UNUSED;
293a36eb
ILT		 8761{
8762 int size;
8763
9445b814
AO		 8764 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
8765 return 0;
8766
c5c76735
JL		 8767 /* We must pass by reference if we would be both passing in registers
8768 and the stack. This is because any subsequent partial arg would be
8769 handled incorrectly in this case.
8770
8771 ??? This is really a kludge. We should either fix GCC so that such
8772 a situation causes an abort and then do something in the MIPS port
8773 to prevent it, or add code to function.c to properly handle the case. */
c9fc373c
JW		 8774 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8775 here hopefully is not relevant to mips_va_arg. */
0e5a4ad8 8776 if (cum && MUST_PASS_IN_STACK (mode, type)
4d72536e
RS		 8777 && FUNCTION_ARG (*cum, mode, type, named) != 0)
8778 return 1;
1e7a71c1 8779
c5c76735 8780 /* Otherwise, we only do this if EABI is selected. */
293a36eb
ILT		 8781 if (mips_abi != ABI_EABI)
8782 return 0;
8783
8784 /* ??? How should SCmode be handled? */
8785 if (type == NULL_TREE || mode == DImode || mode == DFmode)
8786 return 0;
8787
8788 size = int_size_in_bytes (type);
8789 return size == -1 || size > UNITS_PER_WORD;
8790}
46299de9 8791
cff9f8d5 8792/* Return the class of registers for which a mode change from FROM to TO
97ab1175
RS		 8793 is invalid.
8794
8795 In little-endian mode, the hi-lo registers are numbered backwards,
8796 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
8797 word as intended.
8798
8799 Similarly, when using paired floating-point registers, the first
8800 register holds the low word, regardless of endianness. So in big
8801 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
8802 as intended.
8803
8804 Also, loading a 32-bit value into a 64-bit floating-point register
8805 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8806 We can't allow 64-bit float registers to change from a 32-bit
8807 mode to a 64-bit mode. */
8808
b0c42aed
JH		 8809bool
8810mips_cannot_change_mode_class (from, to, class)
cff9f8d5 8811 enum machine_mode from, to;
b0c42aed 8812 enum reg_class class;
cff9f8d5
AH		 8813{
8814 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8815 {
8816 if (TARGET_BIG_ENDIAN)
b0c42aed 8817 return reg_classes_intersect_p (FP_REGS, class);
cff9f8d5 8818 if (TARGET_FLOAT64)
b0c42aed
JH		 8819 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
8820 return reg_classes_intersect_p (HI_REG, class);
cff9f8d5 8821 }
b0c42aed 8822 return false;
cff9f8d5
AH		 8823}
8824
225b8835
ILT		 8825/* This function returns the register class required for a secondary
8826 register when copying between one of the registers in CLASS, and X,
8827 using MODE. If IN_P is nonzero, the copy is going from X to the
8828 register, otherwise the register is the source. A return value of
8829 NO_REGS means that no secondary register is required. */
46299de9
ILT		 8830
8831enum reg_class
225b8835 8832mips_secondary_reload_class (class, mode, x, in_p)
46299de9
ILT		 8833 enum reg_class class;
8834 enum machine_mode mode;
8835 rtx x;
225b8835 8836 int in_p;
46299de9 8837{
2bcb2ab3 8838 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
225b8835 8839 int regno = -1;
2bcb2ab3 8840 int gp_reg_p;
46299de9 8841
2a0b0bf5
ILT		 8842 if (GET_CODE (x) == SIGN_EXTEND)
8843 {
8844 int off = 0;
8845
8846 x = XEXP (x, 0);
8847
8848 /* We may be called with reg_renumber NULL from regclass.
8849 ??? This is probably a bug. */
8850 if (reg_renumber)
8851 regno = true_regnum (x);
8852 else
8853 {
8854 while (GET_CODE (x) == SUBREG)
8855 {
ddef6bc7
JJ		 8856 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8857 GET_MODE (SUBREG_REG (x)),
8858 SUBREG_BYTE (x),
8859 GET_MODE (x));
2a0b0bf5
ILT		 8860 x = SUBREG_REG (x);
8861 }
f5963e61 8862
2a0b0bf5
ILT		 8863 if (GET_CODE (x) == REG)
8864 regno = REGNO (x) + off;
8865 }
8214bf98
RS		 8866
8867 /* 64-bit floating-point registers don't store 32-bit values
8868 in sign-extended form. The only way we can reload
8869 (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
8870 an integer register using a 32-bit move. */
8871 if (FP_REG_P (regno))
8872 return (class == GR_REGS ? NO_REGS : GR_REGS);
8873
8874 /* For the same reason, we can only reload (sign_extend:DI FOO) into
8875 a floating-point register when FOO is an integer register. */
8876 if (class == FP_REGS)
8877 return (GP_REG_P (regno) ? NO_REGS : GR_REGS);
2a0b0bf5 8878 }
f5963e61 8879
2a0b0bf5 8880 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
225b8835
ILT		 8881 regno = true_regnum (x);
8882
2bcb2ab3
GK		 8883 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8884
cafe096b
EC		 8885 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25)
8886 && DANGEROUS_FOR_LA25_P (x))
8887 return LEA_REGS;
8888
225b8835
ILT		 8889 /* We always require a general register when copying anything to
8890 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8891 to a general register, or when copying from register 0. */
8892 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
f5963e61 8893 return ((! in_p
33d7a521 8894 && gp_reg_p
f5963e61 8895 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
33d7a521 8896 ? NO_REGS : gr_regs);
f5963e61
JL		 8897 else if (regno == HILO_REGNUM)
8898 return ((in_p
33d7a521 8899 && class == gr_regs
f5963e61 8900 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
33d7a521 8901 ? NO_REGS : gr_regs);
46299de9 8902
225b8835
ILT		 8903 /* Copying from HI or LO to anywhere other than a general register
8904 requires a general register. */
8905 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8906 {
2bcb2ab3
GK		 8907 if (TARGET_MIPS16 && in_p)
8908 {
8909 /* We can't really copy to HI or LO at all in mips16 mode. */
8910 return M16_REGS;
8911 }
33d7a521 8912 return gp_reg_p ? NO_REGS : gr_regs;
225b8835
ILT		 8913 }
8914 if (MD_REG_P (regno))
8915 {
2bcb2ab3
GK		 8916 if (TARGET_MIPS16 && ! in_p)
8917 {
8918 /* We can't really copy to HI or LO at all in mips16 mode. */
8919 return M16_REGS;
8920 }
33d7a521 8921 return class == gr_regs ? NO_REGS : gr_regs;
46299de9
ILT		 8922 }
8923
b8eb88d0
ILT		 8924 /* We can only copy a value to a condition code register from a
8925 floating point register, and even then we require a scratch
8926 floating point register. We can only copy a value out of a
8927 condition code register into a general register. */
8928 if (class == ST_REGS)
8929 {
8930 if (in_p)
8931 return FP_REGS;
f5963e61 8932 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
b8eb88d0
ILT		 8933 }
8934 if (ST_REG_P (regno))
8935 {
8936 if (! in_p)
8937 return FP_REGS;
f5963e61 8938 return class == GR_REGS ? NO_REGS : GR_REGS;
b8eb88d0
ILT		 8939 }
8940
8214bf98
RS		 8941 if (class == FP_REGS)
8942 {
8943 if (GET_CODE (x) == MEM)
8944 {
8945 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8946 return NO_REGS;
8947 }
8948 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8949 {
8950 /* We can use the l.s and l.d macros to load floating-point
8951 constants. ??? For l.s, we could probably get better
8952 code by returning GR_REGS here. */
8953 return NO_REGS;
8954 }
8955 else if (GP_REG_P (regno) || x == CONST0_RTX (mode))
8956 {
8957 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8958 return NO_REGS;
8959 }
8960 else if (FP_REG_P (regno))
8961 {
8962 /* In this case we can use mov.s or mov.d. */
8963 return NO_REGS;
8964 }
8965 else
8966 {
8967 /* Otherwise, we need to reload through an integer register. */
8968 return GR_REGS;
8969 }
8970 }
8971
2bcb2ab3
GK		 8972 /* In mips16 mode, going between memory and anything but M16_REGS
8973 requires an M16_REG. */
8974 if (TARGET_MIPS16)
8975 {
8976 if (class != M16_REGS && class != M16_NA_REGS)
8977 {
8978 if (gp_reg_p)
8979 return NO_REGS;
8980 return M16_REGS;
8981 }
8982 if (! gp_reg_p)
8983 {
bf4f78ee
JW		 8984 /* The stack pointer isn't a valid operand to an add instruction,
8985 so we need to load it into M16_REGS first. This can happen as
8986 a result of register elimination and form_sum converting
8987 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8988 need an extra register if the dest is the same as the other
8989 register. In that case, we can't fix the problem by loading SP
8990 into the dest first. */
8991 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8992 && GET_CODE (XEXP (x, 1)) == REG
8993 && (XEXP (x, 0) == stack_pointer_rtx
8994 || XEXP (x, 1) == stack_pointer_rtx))
8995 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8996
2bcb2ab3
GK		 8997 if (class == M16_REGS || class == M16_NA_REGS)
8998 return NO_REGS;
8999 return M16_REGS;
9000 }
9001 }
9002
225b8835 9003 return NO_REGS;
46299de9 9004}
d604bca3
MH		 9005
9006/* This function returns the maximum number of consecutive registers
9007 needed to represent mode MODE in registers of class CLASS. */
9008
9009int
9010mips_class_max_nregs (class, mode)
9011 enum reg_class class;
9012 enum machine_mode mode;
9013{
9014 if (class == FP_REGS)
9015 return FP_INC;
9016 else
9017 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
9018}
4977bab6
ZW		 9019
9020bool
9021mips_valid_pointer_mode (mode)
9022 enum machine_mode mode;
9023{
9024 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9025}
9026
2bcb2ab3
GK		 9027\f
9028/* For each mips16 function which refers to GP relative symbols, we
9029 use a pseudo register, initialized at the start of the function, to
9030 hold the $gp value. */
9031
9032rtx
9033mips16_gp_pseudo_reg ()
9034{
c8d1b2b7 9035 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2bcb2ab3
GK		 9036 {
9037 rtx const_gp;
9038 rtx insn, scan;
9039
c8d1b2b7
AO		 9040 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
9041 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
2bcb2ab3
GK		 9042
9043 /* We want to initialize this to a value which gcc will believe
9044 is constant. */
9045 const_gp = gen_rtx (CONST, Pmode,
9046 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
9047
9048 start_sequence ();
c8d1b2b7
AO		 9049 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
9050 const_gp);
2f937369 9051 insn = get_insns ();
2bcb2ab3
GK		 9052 end_sequence ();
9053
9054 push_topmost_sequence ();
9055 /* We need to emit the initialization after the FUNCTION_BEG
9056 note, so that it will be integrated. */
9057 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
9058 if (GET_CODE (scan) == NOTE
9059 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
9060 break;
9061 if (scan == NULL_RTX)
9062 scan = get_insns ();
9063 insn = emit_insn_after (insn, scan);
9064 pop_topmost_sequence ();
9065 }
9066
c8d1b2b7 9067 return cfun->machine->mips16_gp_pseudo_rtx;
2bcb2ab3
GK		 9068}
9069
2bcb2ab3
GK		 9070/* Write out code to move floating point arguments in or out of
9071 general registers. Output the instructions to FILE. FP_CODE is
9072 the code describing which arguments are present (see the comment at
a0ab749a 9073 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
2bcb2ab3
GK		 9074 we are copying from the floating point registers. */
9075
9076static void
9077mips16_fp_args (file, fp_code, from_fp_p)
9078 FILE *file;
9079 int fp_code;
9080 int from_fp_p;
9081{
e2fe6aba 9082 const char *s;
2bcb2ab3
GK		 9083 int gparg, fparg;
9084 unsigned int f;
9085
a53f72db
GRK		 9086 /* This code only works for the original 32 bit ABI and the O64 ABI. */
9087 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
2bcb2ab3
GK		 9088 abort ();
9089
9090 if (from_fp_p)
9091 s = "mfc1";
9092 else
9093 s = "mtc1";
9094 gparg = GP_ARG_FIRST;
9095 fparg = FP_ARG_FIRST;
9096 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9097 {
9098 if ((f & 3) == 1)
9099 {
9100 if ((fparg & 1) != 0)
9101 ++fparg;
9102 fprintf (file, "\t%s\t%s,%s\n", s,
9103 reg_names[gparg], reg_names[fparg]);
9104 }
9105 else if ((f & 3) == 2)
9106 {
9107 if (TARGET_64BIT)
9108 fprintf (file, "\td%s\t%s,%s\n", s,
9109 reg_names[gparg], reg_names[fparg]);
9110 else
9111 {
9112 if ((fparg & 1) != 0)
9113 ++fparg;
a3bc83cc
AC		 9114 if (TARGET_BIG_ENDIAN)
9115 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
9116 reg_names[gparg], reg_names[fparg + 1], s,
9117 reg_names[gparg + 1], reg_names[fparg]);
9118 else
9119 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
9120 reg_names[gparg], reg_names[fparg], s,
9121 reg_names[gparg + 1], reg_names[fparg + 1]);
2bcb2ab3
GK		 9122 ++gparg;
9123 ++fparg;
9124 }
9125 }
9126 else
9127 abort ();
9128
9129 ++gparg;
9130 ++fparg;
9131 }
9132}
9133
9134/* Build a mips16 function stub. This is used for functions which
9135 take aruments in the floating point registers. It is 32 bit code
9136 that moves the floating point args into the general registers, and
9137 then jumps to the 16 bit code. */
9138
9139static void
9140build_mips16_function_stub (file)
9141 FILE *file;
9142{
bd9f1972 9143 const char *fnname;
2bcb2ab3
GK		 9144 char *secname, *stubname;
9145 tree stubid, stubdecl;
9146 int need_comma;
9147 unsigned int f;
9148
9149 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9150 secname = (char *) alloca (strlen (fnname) + 20);
9151 sprintf (secname, ".mips16.fn.%s", fnname);
9152 stubname = (char *) alloca (strlen (fnname) + 20);
9153 sprintf (stubname, "__fn_stub_%s", fnname);
9154 stubid = get_identifier (stubname);
9155 stubdecl = build_decl (FUNCTION_DECL, stubid,
9156 build_function_type (void_type_node, NULL_TREE));
9157 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9158
9159 fprintf (file, "\t# Stub function for %s (", current_function_name);
9160 need_comma = 0;
9161 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
9162 {
9163 fprintf (file, "%s%s",
9164 need_comma ? ", " : "",
9165 (f & 3) == 1 ? "float" : "double");
9166 need_comma = 1;
9167 }
9168 fprintf (file, ")\n");
9169
9170 fprintf (file, "\t.set\tnomips16\n");
9171 function_section (stubdecl);
9172 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
9173
9174 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
9175 within a .ent, and we can not emit another .ent. */
9176#ifndef FUNCTION_NAME_ALREADY_DECLARED
9177 fputs ("\t.ent\t", file);
9178 assemble_name (file, stubname);
9179 fputs ("\n", file);
9180#endif
9181
9182 assemble_name (file, stubname);
9183 fputs (":\n", file);
9184
9185 /* We don't want the assembler to insert any nops here. */
9186 fprintf (file, "\t.set\tnoreorder\n");
9187
9188 mips16_fp_args (file, current_function_args_info.fp_code, 1);
9189
9190 fprintf (asm_out_file, "\t.set\tnoat\n");
9191 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
9192 assemble_name (file, fnname);
9193 fprintf (file, "\n");
9194 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9195 fprintf (asm_out_file, "\t.set\tat\n");
9196
9197 /* Unfortunately, we can't fill the jump delay slot. We can't fill
9198 with one of the mfc1 instructions, because the result is not
9199 available for one instruction, so if the very first instruction
9200 in the function refers to the register, it will see the wrong
9201 value. */
9202 fprintf (file, "\tnop\n");
9203
9204 fprintf (file, "\t.set\treorder\n");
9205
9206#ifndef FUNCTION_NAME_ALREADY_DECLARED
9207 fputs ("\t.end\t", file);
9208 assemble_name (file, stubname);
9209 fputs ("\n", file);
9210#endif
9211
9212 fprintf (file, "\t.set\tmips16\n");
9213
9214 function_section (current_function_decl);
9215}
9216
9217/* We keep a list of functions for which we have already built stubs
9218 in build_mips16_call_stub. */
9219
9220struct mips16_stub
9221{
9222 struct mips16_stub *next;
9223 char *name;
9224 int fpret;
9225};
9226
9227static struct mips16_stub *mips16_stubs;
9228
9229/* Build a call stub for a mips16 call. A stub is needed if we are
9230 passing any floating point values which should go into the floating
9231 point registers. If we are, and the call turns out to be to a 32
9232 bit function, the stub will be used to move the values into the
9233 floating point registers before calling the 32 bit function. The
9234 linker will magically adjust the function call to either the 16 bit
9235 function or the 32 bit stub, depending upon where the function call
9236 is actually defined.
9237
9238 Similarly, we need a stub if the return value might come back in a
9239 floating point register.
9240
cafe096b
EC		 9241 RETVAL is the location of the return value, or null if this is
9242 a call rather than a call_value. FN is the address of the
9243 function and ARG_SIZE is the size of the arguments. FP_CODE
2bcb2ab3
GK		 9244 is the code built by function_arg. This function returns a nonzero
9245 value if it builds the call instruction itself. */
9246
9247int
cafe096b 9248build_mips16_call_stub (retval, fn, arg_size, fp_code)
2bcb2ab3 9249 rtx retval;
cafe096b 9250 rtx fn;
2bcb2ab3
GK		 9251 rtx arg_size;
9252 int fp_code;
9253{
9254 int fpret;
bd9f1972
KG		 9255 const char *fnname;
9256 char *secname, *stubname;
2bcb2ab3
GK		 9257 struct mips16_stub *l;
9258 tree stubid, stubdecl;
9259 int need_comma;
9260 unsigned int f;
9261
9262 /* We don't need to do anything if we aren't in mips16 mode, or if
9263 we were invoked with the -msoft-float option. */
9264 if (! TARGET_MIPS16 || ! mips16_hard_float)
9265 return 0;
9266
9267 /* Figure out whether the value might come back in a floating point
9268 register. */
9269 fpret = (retval != 0
9270 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
3f26edaa 9271 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
2bcb2ab3
GK		 9272
9273 /* We don't need to do anything if there were no floating point
9274 arguments and the value will not be returned in a floating point
9275 register. */
9276 if (fp_code == 0 && ! fpret)
9277 return 0;
9278
2bcb2ab3
GK		 9279 /* We don't need to do anything if this is a call to a special
9280 mips16 support function. */
9281 if (GET_CODE (fn) == SYMBOL_REF
9282 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
9283 return 0;
9284
7dac2f89 9285 /* This code will only work for o32 and o64 abis. The other ABI's
2bcb2ab3 9286 require more sophisticated support. */
a53f72db 9287 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
2bcb2ab3
GK		 9288 abort ();
9289
9290 /* We can only handle SFmode and DFmode floating point return
9291 values. */
9292 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
9293 abort ();
9294
9295 /* If we're calling via a function pointer, then we must always call
9296 via a stub. There are magic stubs provided in libgcc.a for each
9297 of the required cases. Each of them expects the function address
9298 to arrive in register $2. */
9299
9300 if (GET_CODE (fn) != SYMBOL_REF)
9301 {
9302 char buf[30];
9303 tree id;
cafe096b 9304 rtx stub_fn, insn;
2bcb2ab3
GK		 9305
9306 /* ??? If this code is modified to support other ABI's, we need
9307 to handle PARALLEL return values here. */
9308
9309 sprintf (buf, "__mips16_call_stub_%s%d",
9310 (fpret
9311 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
9312 : ""),
9313 fp_code);
9314 id = get_identifier (buf);
9315 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
2bcb2ab3
GK		 9316
9317 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
9318
9319 if (retval == NULL_RTX)
cafe096b 9320 insn = gen_call_internal (stub_fn, arg_size);
2bcb2ab3 9321 else
cafe096b 9322 insn = gen_call_value_internal (retval, stub_fn, arg_size);
2bcb2ab3
GK		 9323 insn = emit_call_insn (insn);
9324
9325 /* Put the register usage information on the CALL. */
9326 if (GET_CODE (insn) != CALL_INSN)
9327 abort ();
9328 CALL_INSN_FUNCTION_USAGE (insn) =
9329 gen_rtx (EXPR_LIST, VOIDmode,
9330 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
9331 CALL_INSN_FUNCTION_USAGE (insn));
9332
9333 /* If we are handling a floating point return value, we need to
9334 save $18 in the function prologue. Putting a note on the
9335 call will mean that regs_ever_live[$18] will be true if the
9336 call is not eliminated, and we can check that in the prologue
9337 code. */
9338 if (fpret)
9339 CALL_INSN_FUNCTION_USAGE (insn) =
9340 gen_rtx (EXPR_LIST, VOIDmode,
9341 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9342 CALL_INSN_FUNCTION_USAGE (insn));
9343
9344 /* Return 1 to tell the caller that we've generated the call
9345 insn. */
9346 return 1;
9347 }
9348
9349 /* We know the function we are going to call. If we have already
9350 built a stub, we don't need to do anything further. */
9351
9352 fnname = XSTR (fn, 0);
9353 for (l = mips16_stubs; l != NULL; l = l->next)
9354 if (strcmp (l->name, fnname) == 0)
9355 break;
9356
9357 if (l == NULL)
9358 {
9359 /* Build a special purpose stub. When the linker sees a
9360 function call in mips16 code, it will check where the target
9361 is defined. If the target is a 32 bit call, the linker will
9362 search for the section defined here. It can tell which
9363 symbol this section is associated with by looking at the
9364 relocation information (the name is unreliable, since this
9365 might be a static function). If such a section is found, the
9366 linker will redirect the call to the start of the magic
9367 section.
9368
9369 If the function does not return a floating point value, the
9370 special stub section is named
9371 .mips16.call.FNNAME
9372
9373 If the function does return a floating point value, the stub
9374 section is named
9375 .mips16.call.fp.FNNAME
9376 */
9377
9378 secname = (char *) alloca (strlen (fnname) + 40);
9379 sprintf (secname, ".mips16.call.%s%s",
9380 fpret ? "fp." : "",
9381 fnname);
9382 stubname = (char *) alloca (strlen (fnname) + 20);
9383 sprintf (stubname, "__call_stub_%s%s",
9384 fpret ? "fp_" : "",
9385 fnname);
9386 stubid = get_identifier (stubname);
9387 stubdecl = build_decl (FUNCTION_DECL, stubid,
9388 build_function_type (void_type_node, NULL_TREE));
9389 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9390
9391 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9392 (fpret
9393 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9394 : ""),
9395 fnname);
9396 need_comma = 0;
9397 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9398 {
9399 fprintf (asm_out_file, "%s%s",
9400 need_comma ? ", " : "",
9401 (f & 3) == 1 ? "float" : "double");
9402 need_comma = 1;
9403 }
9404 fprintf (asm_out_file, ")\n");
9405
9406 fprintf (asm_out_file, "\t.set\tnomips16\n");
9407 assemble_start_function (stubdecl, stubname);
9408
9409#ifndef FUNCTION_NAME_ALREADY_DECLARED
9410 fputs ("\t.ent\t", asm_out_file);
9411 assemble_name (asm_out_file, stubname);
9412 fputs ("\n", asm_out_file);
9413
9414 assemble_name (asm_out_file, stubname);
9415 fputs (":\n", asm_out_file);
9416#endif
9417
9418 /* We build the stub code by hand. That's the only way we can
9419 do it, since we can't generate 32 bit code during a 16 bit
987ba558 9420 compilation. */
2bcb2ab3
GK		 9421
9422 /* We don't want the assembler to insert any nops here. */
9423 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9424
9425 mips16_fp_args (asm_out_file, fp_code, 0);
9426
9427 if (! fpret)
9428 {
9429 fprintf (asm_out_file, "\t.set\tnoat\n");
9430 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9431 fnname);
9432 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9433 fprintf (asm_out_file, "\t.set\tat\n");
9434 /* Unfortunately, we can't fill the jump delay slot. We
9435 can't fill with one of the mtc1 instructions, because the
9436 result is not available for one instruction, so if the
9437 very first instruction in the function refers to the
9438 register, it will see the wrong value. */
9439 fprintf (asm_out_file, "\tnop\n");
9440 }
9441 else
9442 {
9443 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9444 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9445 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9446 /* As above, we can't fill the delay slot. */
9447 fprintf (asm_out_file, "\tnop\n");
9448 if (GET_MODE (retval) == SFmode)
9449 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9450 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9451 else
9452 {
a3bc83cc
AC		 9453 if (TARGET_BIG_ENDIAN)
9454 {
9455 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9456 reg_names[GP_REG_FIRST + 2],
9457 reg_names[FP_REG_FIRST + 1]);
9458 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9459 reg_names[GP_REG_FIRST + 3],
9460 reg_names[FP_REG_FIRST + 0]);
9461 }
9462 else
9463 {
9464 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9465 reg_names[GP_REG_FIRST + 2],
9466 reg_names[FP_REG_FIRST + 0]);
9467 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9468 reg_names[GP_REG_FIRST + 3],
9469 reg_names[FP_REG_FIRST + 1]);
9470 }
2bcb2ab3
GK		 9471 }
9472 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9473 /* As above, we can't fill the delay slot. */
9474 fprintf (asm_out_file, "\tnop\n");
9475 }
9476
9477 fprintf (asm_out_file, "\t.set\treorder\n");
9478
9479#ifdef ASM_DECLARE_FUNCTION_SIZE
9480 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9481#endif
9482
9483#ifndef FUNCTION_NAME_ALREADY_DECLARED
9484 fputs ("\t.end\t", asm_out_file);
9485 assemble_name (asm_out_file, stubname);
9486 fputs ("\n", asm_out_file);
9487#endif
9488
9489 fprintf (asm_out_file, "\t.set\tmips16\n");
9490
9491 /* Record this stub. */
9492 l = (struct mips16_stub *) xmalloc (sizeof *l);
ad85216e 9493 l->name = xstrdup (fnname);
2bcb2ab3
GK		 9494 l->fpret = fpret;
9495 l->next = mips16_stubs;
9496 mips16_stubs = l;
9497 }
9498
9499 /* If we expect a floating point return value, but we've built a
9500 stub which does not expect one, then we're in trouble. We can't
9501 use the existing stub, because it won't handle the floating point
9502 value. We can't build a new stub, because the linker won't know
9503 which stub to use for the various calls in this object file.
9504 Fortunately, this case is illegal, since it means that a function
9505 was declared in two different ways in a single compilation. */
9506 if (fpret && ! l->fpret)
9507 error ("can not handle inconsistent calls to `%s'", fnname);
9508
9509 /* If we are calling a stub which handles a floating point return
9510 value, we need to arrange to save $18 in the prologue. We do
9511 this by marking the function call as using the register. The
9512 prologue will later see that it is used, and emit code to save
9513 it. */
9514
9515 if (l->fpret)
9516 {
9517 rtx insn;
9518
9519 if (retval == NULL_RTX)
cafe096b 9520 insn = gen_call_internal (fn, arg_size);
2bcb2ab3 9521 else
cafe096b 9522 insn = gen_call_value_internal (retval, fn, arg_size);
2bcb2ab3
GK		 9523 insn = emit_call_insn (insn);
9524
9525 if (GET_CODE (insn) != CALL_INSN)
9526 abort ();
9527
9528 CALL_INSN_FUNCTION_USAGE (insn) =
9529 gen_rtx (EXPR_LIST, VOIDmode,
9530 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9531 CALL_INSN_FUNCTION_USAGE (insn));
9532
9533 /* Return 1 to tell the caller that we've generated the call
9534 insn. */
9535 return 1;
9536 }
9537
9538 /* Return 0 to let the caller generate the call insn. */
9539 return 0;
9540}
9541
9542/* This function looks through the code for a function, and tries to
9543 optimize the usage of the $gp register. We arrange to copy $gp
9544 into a pseudo-register, and then let gcc's normal reload handling
9545 deal with the pseudo-register. Unfortunately, if reload choose to
9546 put the pseudo-register into a call-clobbered register, it will
9547 emit saves and restores for that register around any function
9548 calls. We don't need the saves, and it's faster to copy $gp than
9549 to do an actual restore. ??? This still means that we waste a
9550 stack slot.
9551
9552 This is an optimization, and the code which gcc has actually
9553 generated is correct, so we do not need to catch all cases. */
9554
9555static void
9556mips16_optimize_gp (first)
9557 rtx first;
9558{
9559 rtx gpcopy, slot, insn;
9560
9561 /* Look through the instructions. Set GPCOPY to the register which
9562 holds a copy of $gp. Set SLOT to the stack slot where it is
9563 saved. If we find an instruction which sets GPCOPY to anything
9564 other than $gp or SLOT, then we can't use it. If we find an
9565 instruction which sets SLOT to anything other than GPCOPY, we
9566 can't use it. */
9567
9568 gpcopy = NULL_RTX;
9569 slot = NULL_RTX;
9570 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9571 {
9572 rtx set;
9573
2c3c49de 9574 if (! INSN_P (insn))
2bcb2ab3
GK		 9575 continue;
9576
9577 set = PATTERN (insn);
9578
9579 /* We know that all references to memory will be inside a SET,
9580 because there is no other way to access memory on the mips16.
9581 We don't have to worry about a PARALLEL here, because the
9582 mips.md file will never generate them for memory references. */
9583 if (GET_CODE (set) != SET)
9584 continue;
9585
9586 if (gpcopy == NULL_RTX
9587 && GET_CODE (SET_SRC (set)) == CONST
9588 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
9589 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
cafe096b 9590 && GET_CODE (SET_DEST (set)) == REG)
2bcb2ab3
GK		 9591 gpcopy = SET_DEST (set);
9592 else if (slot == NULL_RTX
9593 && gpcopy != NULL_RTX
9594 && GET_CODE (SET_DEST (set)) == MEM
9595 && GET_CODE (SET_SRC (set)) == REG
cafe096b 9596 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
2bcb2ab3
GK		 9597 {
9598 rtx base, offset;
9599
9600 offset = const0_rtx;
9601 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9602 if (GET_CODE (base) == REG
9603 && (REGNO (base) == STACK_POINTER_REGNUM
9604 || REGNO (base) == FRAME_POINTER_REGNUM))
9605 slot = SET_DEST (set);
9606 }
9607 else if (gpcopy != NULL_RTX
9608 && (GET_CODE (SET_DEST (set)) == REG
9609 || GET_CODE (SET_DEST (set)) == SUBREG)
9610 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
9611 && (GET_CODE (SET_DEST (set)) != REG
9612 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
2bcb2ab3
GK		 9613 || ((GET_CODE (SET_SRC (set)) != CONST
9614 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
9615 || (REGNO (XEXP (SET_SRC (set), 0))
9616 != GP_REG_FIRST + 28))
9617 && ! rtx_equal_p (SET_SRC (set), slot))))
9618 break;
9619 else if (slot != NULL_RTX
9620 && GET_CODE (SET_DEST (set)) == MEM
9621 && rtx_equal_p (SET_DEST (set), slot)
9622 && (GET_CODE (SET_SRC (set)) != REG
9623 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
9624 break;
9625 }
9626
9627 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9628 different optimization. Any time we find a copy of $28 into a
9629 register, followed by an add of a symbol_ref to that register, we
9630 convert it to load the value from the constant table instead.
9631 The copy and add will take six bytes, just as the load and
9632 constant table entry will take six bytes. However, it is
9633 possible that the constant table entry will be shared.
9634
9635 This could be a peephole optimization, but I don't know if the
9636 peephole code can call force_const_mem.
9637
9638 Using the same register for the copy of $28 and the add of the
9639 symbol_ref is actually pretty likely, since the add instruction
9640 requires the destination and the first addend to be the same
9641 register. */
9642
9643 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
9644 {
cafe096b
EC		 9645#if 0
9646 /* Used below in #if 0 area. */
2bcb2ab3 9647 rtx next;
cafe096b 9648#endif
2bcb2ab3
GK		 9649 /* This optimization is only reasonable if the constant table
9650 entries are only 4 bytes. */
9651 if (Pmode != SImode)
9652 return;
9653
cafe096b
EC		 9654#if 0
9655 /* ??? FIXME. Rewrite for new UNSPEC_RELOC stuff. */
2bcb2ab3
GK		 9656 for (insn = first; insn != NULL_RTX; insn = next)
9657 {
9658 rtx set1, set2;
9659
9660 next = insn;
9661 do
9662 {
9663 next = NEXT_INSN (next);
9664 }
9665 while (next != NULL_RTX
9666 && (GET_CODE (next) == NOTE
9667 || (GET_CODE (next) == INSN
9668 && (GET_CODE (PATTERN (next)) == USE
9669 || GET_CODE (PATTERN (next)) == CLOBBER))));
9670
9671 if (next == NULL_RTX)
9672 break;
9673
2c3c49de 9674 if (! INSN_P (insn))
2bcb2ab3
GK		 9675 continue;
9676
2c3c49de 9677 if (! INSN_P (next))
2bcb2ab3
GK		 9678 continue;
9679
9680 set1 = PATTERN (insn);
9681 if (GET_CODE (set1) != SET)
9682 continue;
9683 set2 = PATTERN (next);
9684 if (GET_CODE (set2) != SET)
9685 continue;
9686
9687 if (GET_CODE (SET_DEST (set1)) == REG
9688 && GET_CODE (SET_SRC (set1)) == CONST
9689 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
9690 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
9691 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
9692 && GET_CODE (SET_SRC (set2)) == PLUS
9693 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
9694 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
9695 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
9696 {
9697 rtx sym;
9698
9699 /* We've found a case we can change to load from the
9700 constant table. */
9701
9702 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
9703 if (GET_CODE (sym) != SYMBOL_REF)
9704 abort ();
9705 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
9706 force_const_mem (Pmode, sym)),
9707 next);
7dac2f89 9708
2bcb2ab3
GK		 9709 PUT_CODE (insn, NOTE);
9710 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9711 NOTE_SOURCE_FILE (insn) = 0;
9712
9713 PUT_CODE (next, NOTE);
9714 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9715 NOTE_SOURCE_FILE (next) = 0;
9716 }
9717 }
cafe096b 9718#endif
2bcb2ab3
GK		 9719
9720 return;
9721 }
2bcb2ab3
GK		 9722 /* We can safely remove all assignments to SLOT from GPCOPY, and
9723 replace all assignments from SLOT to GPCOPY with assignments from
9724 $28. */
9725
9726 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9727 {
9728 rtx set;
9729
2c3c49de 9730 if (! INSN_P (insn))
2bcb2ab3
GK		 9731 continue;
9732
9733 set = PATTERN (insn);
cafe096b 9734 if (GET_CODE (set) != SET)
2bcb2ab3
GK		 9735 continue;
9736
9737 if (GET_CODE (SET_DEST (set)) == MEM
9738 && rtx_equal_p (SET_DEST (set), slot)
9739 && GET_CODE (SET_SRC (set)) == REG
9740 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9741 {
9742 PUT_CODE (insn, NOTE);
9743 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9744 NOTE_SOURCE_FILE (insn) = 0;
9745 }
9746 else if (GET_CODE (SET_DEST (set)) == REG
9747 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9748 && GET_CODE (SET_SRC (set)) == MEM
9749 && rtx_equal_p (SET_SRC (set), slot))
9750 {
cafe096b
EC		 9751 enum machine_mode mode;
9752
9753 mode = GET_MODE (SET_DEST (set));
9754 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set),
9755 gen_rtx (CONST, mode,
9756 gen_rtx (REG, mode,
2bcb2ab3
GK		 9757 GP_REG_FIRST + 28))),
9758 insn);
9759 PUT_CODE (insn, NOTE);
9760 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9761 NOTE_SOURCE_FILE (insn) = 0;
9762 }
9763 }
9764}
9765
9766/* We keep a list of constants we which we have to add to internal
9767 constant tables in the middle of large functions. */
9768
9769struct constant
9770{
9771 struct constant *next;
9772 rtx value;
9773 rtx label;
9774 enum machine_mode mode;
9775};
9776
9777/* Add a constant to the list in *PCONSTANTS. */
9778
9779static rtx
9780add_constant (pconstants, val, mode)
9781 struct constant **pconstants;
9782 rtx val;
9783 enum machine_mode mode;
9784{
9785 struct constant *c;
9786
9787 for (c = *pconstants; c != NULL; c = c->next)
9788 if (mode == c->mode && rtx_equal_p (val, c->value))
9789 return c->label;
9790
9791 c = (struct constant *) xmalloc (sizeof *c);
9792 c->value = val;
9793 c->mode = mode;
9794 c->label = gen_label_rtx ();
9795 c->next = *pconstants;
9796 *pconstants = c;
9797 return c->label;
9798}
9799
9800/* Dump out the constants in CONSTANTS after INSN. */
9801
9802static void
9803dump_constants (constants, insn)
9804 struct constant *constants;
9805 rtx insn;
9806{
9807 struct constant *c;
9808 int align;
9809
9810 c = constants;
9811 align = 0;
9812 while (c != NULL)
9813 {
9814 rtx r;
9815 struct constant *next;
9816
9817 switch (GET_MODE_SIZE (c->mode))
9818 {
9819 case 1:
9820 align = 0;
9821 break;
9822 case 2:
9823 if (align < 1)
9824 insn = emit_insn_after (gen_align_2 (), insn);
9825 align = 1;
9826 break;
9827 case 4:
9828 if (align < 2)
9829 insn = emit_insn_after (gen_align_4 (), insn);
9830 align = 2;
9831 break;
9832 default:
9833 if (align < 3)
9834 insn = emit_insn_after (gen_align_8 (), insn);
9835 align = 3;
9836 break;
9837 }
9838
9839 insn = emit_label_after (c->label, insn);
9840
9841 switch (c->mode)
9842 {
9843 case QImode:
9844 r = gen_consttable_qi (c->value);
9845 break;
9846 case HImode:
9847 r = gen_consttable_hi (c->value);
9848 break;
9849 case SImode:
9850 r = gen_consttable_si (c->value);
9851 break;
9852 case SFmode:
9853 r = gen_consttable_sf (c->value);
9854 break;
9855 case DImode:
9856 r = gen_consttable_di (c->value);
9857 break;
9858 case DFmode:
9859 r = gen_consttable_df (c->value);
9860 break;
9861 default:
9862 abort ();
9863 }
9864
9865 insn = emit_insn_after (r, insn);
9866
9867 next = c->next;
9868 free (c);
9869 c = next;
9870 }
9871
9872 emit_barrier_after (insn);
9873}
9874
9875/* Find the symbol in an address expression. */
9876
9877static rtx
9878mips_find_symbol (addr)
9879 rtx addr;
9880{
9881 if (GET_CODE (addr) == MEM)
9882 addr = XEXP (addr, 0);
9883 while (GET_CODE (addr) == CONST)
9884 addr = XEXP (addr, 0);
9885 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9886 return addr;
9887 if (GET_CODE (addr) == PLUS)
9888 {
9889 rtx l1, l2;
9890
9891 l1 = mips_find_symbol (XEXP (addr, 0));
9892 l2 = mips_find_symbol (XEXP (addr, 1));
9893 if (l1 != NULL_RTX && l2 == NULL_RTX)
9894 return l1;
9895 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9896 return l2;
9897 }
9898 return NULL_RTX;
9899}
9900
9901/* Exported to toplev.c.
9902
9903 Do a final pass over the function, just before delayed branch
9904 scheduling. */
9905
9906void
9907machine_dependent_reorg (first)
9908 rtx first;
9909{
82305258 9910 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
2bcb2ab3
GK		 9911 rtx insn;
9912 struct constant *constants;
9913
9914 if (! TARGET_MIPS16)
9915 return;
9916
9917 /* If $gp is used, try to remove stores, and replace loads with
9918 copies from $gp. */
9919 if (optimize)
9920 mips16_optimize_gp (first);
9921
9922 /* Scan the function looking for PC relative loads which may be out
9923 of range. All such loads will either be from the constant table,
9924 or be getting the address of a constant string. If the size of
9925 the function plus the size of the constant table is less than
9926 0x8000, then all loads are in range. */
9927
9928 insns_len = 0;
9929 for (insn = first; insn; insn = NEXT_INSN (insn))
9930 {
0ff83799 9931 insns_len += get_attr_length (insn);
2bcb2ab3
GK		 9932
9933 /* ??? We put switch tables in .text, but we don't define
9934 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9935 compute their lengths correctly. */
9936 if (GET_CODE (insn) == JUMP_INSN)
9937 {
9938 rtx body;
9939
9940 body = PATTERN (insn);
9941 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9942 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9943 * GET_MODE_SIZE (GET_MODE (body)));
9944 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9945 }
9946 }
9947
b2471838 9948 /* Store the original value of insns_len in cfun->machine, so
2bcb2ab3 9949 that simple_memory_operand can look at it. */
b2471838 9950 cfun->machine->insns_len = insns_len;
2bcb2ab3
GK		 9951
9952 pool_size = get_pool_size ();
9953 if (insns_len + pool_size + mips_string_length < 0x8000)
9954 return;
9955
9956 /* Loop over the insns and figure out what the maximum internal pool
9957 size could be. */
9958 max_internal_pool_size = 0;
9959 for (insn = first; insn; insn = NEXT_INSN (insn))
9960 {
9961 if (GET_CODE (insn) == INSN
9962 && GET_CODE (PATTERN (insn)) == SET)
9963 {
9964 rtx src;
9965
9966 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9967 if (src == NULL_RTX)
9968 continue;
9969 if (CONSTANT_POOL_ADDRESS_P (src))
9970 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9971 else if (SYMBOL_REF_FLAG (src))
9972 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9973 }
9974 }
9975
9976 constants = NULL;
9977 addr = 0;
82305258 9978 first_constant_ref = -1;
2bcb2ab3
GK		 9979
9980 for (insn = first; insn; insn = NEXT_INSN (insn))
9981 {
9982 if (GET_CODE (insn) == INSN
9983 && GET_CODE (PATTERN (insn)) == SET)
9984 {
9985 rtx val, src;
404e4854 9986 enum machine_mode mode = VOIDmode;
2bcb2ab3
GK		 9987
9988 val = NULL_RTX;
9989 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9990 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9991 {
9992 /* ??? This is very conservative, which means that we
9993 will generate too many copies of the constant table.
9994 The only solution would seem to be some form of
9995 relaxing. */
9996 if (((insns_len - addr)
9997 + max_internal_pool_size
9998 + get_pool_offset (src))
9999 >= 0x8000)
10000 {
10001 val = get_pool_constant (src);
10002 mode = get_pool_mode (src);
10003 }
10004 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
10005 }
10006 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
10007 {
10008 /* Including all of mips_string_length is conservative,
10009 and so is including all of max_internal_pool_size. */
10010 if (((insns_len - addr)
10011 + max_internal_pool_size
10012 + pool_size
10013 + mips_string_length)
10014 >= 0x8000)
ddc22296
R		 10015 {
10016 val = src;
10017 mode = Pmode;
10018 }
2bcb2ab3
GK		 10019 max_internal_pool_size -= Pmode;
10020 }
10021
10022 if (val != NULL_RTX)
10023 {
10024 rtx lab, newsrc;
10025
10026 /* This PC relative load is out of range. ??? In the
10027 case of a string constant, we are only guessing that
10028 it is range, since we don't know the offset of a
10029 particular string constant. */
10030
10031 lab = add_constant (&constants, val, mode);
10032 newsrc = gen_rtx (MEM, mode,
10033 gen_rtx (LABEL_REF, VOIDmode, lab));
10034 RTX_UNCHANGING_P (newsrc) = 1;
10035 PATTERN (insn) = gen_rtx (SET, VOIDmode,
10036 SET_DEST (PATTERN (insn)),
10037 newsrc);
10038 INSN_CODE (insn) = -1;
82305258
AH		 10039
10040 if (first_constant_ref < 0)
10041 first_constant_ref = addr;
2bcb2ab3
GK		 10042 }
10043 }
10044
0ff83799 10045 addr += get_attr_length (insn);
2bcb2ab3
GK		 10046
10047 /* ??? We put switch tables in .text, but we don't define
10048 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
10049 compute their lengths correctly. */
10050 if (GET_CODE (insn) == JUMP_INSN)
10051 {
10052 rtx body;
10053
10054 body = PATTERN (insn);
10055 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
10056 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
10057 * GET_MODE_SIZE (GET_MODE (body)));
10058 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
10059 }
10060
10061 if (GET_CODE (insn) == BARRIER)
10062 {
10063 /* Output any constants we have accumulated. Note that we
10064 don't need to change ADDR, since its only use is
10065 subtraction from INSNS_LEN, and both would be changed by
10066 the same amount.
10067 ??? If the instructions up to the next barrier reuse a
10068 constant, it would often be better to continue
10069 accumulating. */
10070 if (constants != NULL)
10071 dump_constants (constants, insn);
10072 constants = NULL;
82305258 10073 first_constant_ref = -1;
2bcb2ab3 10074 }
7dac2f89 10075
82305258 10076 if (constants != NULL
7dac2f89
EC		 10077 && (NEXT_INSN (insn) == NULL
10078 || (first_constant_ref >= 0
82305258
AH		 10079 && (((addr - first_constant_ref)
10080 + 2 /* for alignment */
10081 + 2 /* for a short jump insn */
10082 + pool_size)
10083 >= 0x8000))))
10084 {
10085 /* If we haven't had a barrier within 0x8000 bytes of a
10086 constant reference or we are at the end of the function,
987ba558 10087 emit a barrier now. */
2bcb2ab3 10088
82305258 10089 rtx label, jump, barrier;
7dac2f89 10090
82305258
AH		 10091 label = gen_label_rtx ();
10092 jump = emit_jump_insn_after (gen_jump (label), insn);
10093 JUMP_LABEL (jump) = label;
10094 LABEL_NUSES (label) = 1;
10095 barrier = emit_barrier_after (jump);
10096 emit_label_after (label, barrier);
10097 first_constant_ref = -1;
10098 }
10099 }
2bcb2ab3
GK		 10100
10101 /* ??? If we output all references to a constant in internal
10102 constants table, we don't need to output the constant in the real
10103 constant table, but we have no way to prevent that. */
10104}
cb923660 10105
d604bca3
MH		 10106/* Return a number assessing the cost of moving a register in class
10107 FROM to class TO. The classes are expressed using the enumeration
10108 values such as `GENERAL_REGS'. A value of 2 is the default; other
10109 values are interpreted relative to that.
10110
10111 It is not required that the cost always equal 2 when FROM is the
10112 same as TO; on some machines it is expensive to move between
10113 registers if they are not general registers.
10114
10115 If reload sees an insn consisting of a single `set' between two
10116 hard registers, and if `REGISTER_MOVE_COST' applied to their
10117 classes returns a value of 2, reload does not check to ensure that
10118 the constraints of the insn are met. Setting a cost of other than
10119 2 will allow reload to verify that the constraints are met. You
10120 should do this if the `movM' pattern's constraints do not allow
10121 such copying.
10122
10123 ??? We make make the cost of moving from HI/LO/HILO/MD into general
10124 registers the same as for one of moving general registers to
10125 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
10126 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
10127 isn't clear if it is wise. And it might not work in all cases. We
10128 could solve the DImode LO reg problem by using a multiply, just
10129 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10130 problem by using divide instructions. divu puts the remainder in
10131 the HI reg, so doing a divide by -1 will move the value in the HI
10132 reg for all values except -1. We could handle that case by using a
10133 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10134 a compare/branch to test the input value to see which instruction
10135 we need to use. This gets pretty messy, but it is feasible. */
10136
10137int
10138mips_register_move_cost (mode, to, from)
a8b4881f 10139 enum machine_mode mode ATTRIBUTE_UNUSED;
d604bca3
MH		 10140 enum reg_class to, from;
10141{
10142 if (from == M16_REGS && GR_REG_CLASS_P (to))
10143 return 2;
10144 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
10145 return 2;
10146 else if (GR_REG_CLASS_P (from))
10147 {
10148 if (to == M16_REGS)
10149 return 2;
10150 else if (to == M16_NA_REGS)
10151 return 2;
10152 else if (GR_REG_CLASS_P (to))
10153 {
10154 if (TARGET_MIPS16)
10155 return 4;
10156 else
10157 return 2;
10158 }
10159 else if (to == FP_REGS)
10160 return 4;
10161 else if (to == HI_REG || to == LO_REG || to == MD_REGS
10162 || to == HILO_REG)
10163 {
10164 if (TARGET_MIPS16)
10165 return 12;
10166 else
10167 return 6;
10168 }
10169 else if (COP_REG_CLASS_P (to))
10170 {
10171 return 5;
10172 }
10173 } /* GR_REG_CLASS_P (from) */
10174 else if (from == FP_REGS)
10175 {
10176 if (GR_REG_CLASS_P (to))
10177 return 4;
10178 else if (to == FP_REGS)
10179 return 2;
10180 else if (to == ST_REGS)
10181 return 8;
10182 } /* from == FP_REGS */
10183 else if (from == HI_REG || from == LO_REG || from == MD_REGS
10184 || from == HILO_REG)
10185 {
10186 if (GR_REG_CLASS_P (to))
10187 {
10188 if (TARGET_MIPS16)
10189 return 12;
10190 else
10191 return 6;
10192 }
10193 } /* from == HI_REG, etc. */
10194 else if (from == ST_REGS && GR_REG_CLASS_P (to))
10195 return 4;
10196 else if (COP_REG_CLASS_P (from))
10197 {
10198 return 5;
10199 } /* COP_REG_CLASS_P (from) */
10200
10201 /* fallthru */
10202
10203 return 12;
10204}
10205
7dac2f89 10206/* Return the length of INSN. LENGTH is the initial length computed by
0ff83799
MM		 10207 attributes in the machine-description file. */
10208
10209int
10210mips_adjust_insn_length (insn, length)
10211 rtx insn;
10212 int length;
10213{
10214 /* A unconditional jump has an unfilled delay slot if it is not part
10215 of a sequence. A conditional jump normally has a delay slot, but
10216 does not on MIPS16. */
10217 if (simplejump_p (insn)
7dac2f89 10218 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
0ff83799
MM		 10219 || GET_CODE (insn) == CALL_INSN)))
10220 length += 4;
10221
10222 /* All MIPS16 instructions are a measly two bytes. */
10223 if (TARGET_MIPS16)
10224 length /= 2;
10225
10226 return length;
10227}
10228
7dac2f89 10229/* Output assembly instructions to peform a conditional branch.
0ff83799
MM		 10230
10231 INSN is the branch instruction. OPERANDS[0] is the condition.
10232 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
10233 of the first operand to the condition. If TWO_OPERANDS_P is
a0ab749a 10234 nonzero the comparison takes two operands; OPERANDS[3] will be the
0ff83799
MM		 10235 second operand.
10236
a0ab749a
KH		 10237 If INVERTED_P is nonzero we are to branch if the condition does
10238 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
0ff83799
MM		 10239
10240 LENGTH is the length (in bytes) of the sequence we are to generate.
10241 That tells us whether to generate a simple conditional branch, or a
10242 reversed conditional branch around a `jr' instruction. */
9b55553e 10243const char *
7dac2f89
EC		 10244mips_output_conditional_branch (insn,
10245 operands,
0ff83799
MM		 10246 two_operands_p,
10247 float_p,
10248 inverted_p,
10249 length)
10250 rtx insn;
10251 rtx *operands;
10252 int two_operands_p;
10253 int float_p;
10254 int inverted_p;
10255 int length;
10256{
10257 static char buffer[200];
10258 /* The kind of comparison we are doing. */
10259 enum rtx_code code = GET_CODE (operands[0]);
a0ab749a 10260 /* Nonzero if the opcode for the comparison needs a `z' indicating
0ff83799
MM		 10261 that it is a comparision against zero. */
10262 int need_z_p;
10263 /* A string to use in the assembly output to represent the first
10264 operand. */
bd9f1972 10265 const char *op1 = "%z2";
0ff83799
MM		 10266 /* A string to use in the assembly output to represent the second
10267 operand. Use the hard-wired zero register if there's no second
10268 operand. */
bd9f1972 10269 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
0ff83799 10270 /* The operand-printing string for the comparison. */
27c38fbe 10271 const char *const comp = (float_p ? "%F0" : "%C0");
0ff83799 10272 /* The operand-printing string for the inverted comparison. */
27c38fbe 10273 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
0ff83799
MM		 10274
10275 /* The MIPS processors (for levels of the ISA at least two), have
10276 "likely" variants of each branch instruction. These instructions
10277 annul the instruction in the delay slot if the branch is not
10278 taken. */
10279 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10280
10281 if (!two_operands_p)
10282 {
10283 /* To compute whether than A > B, for example, we normally
10284 subtract B from A and then look at the sign bit. But, if we
10285 are doing an unsigned comparison, and B is zero, we don't
10286 have to do the subtraction. Instead, we can just check to
a0ab749a 10287 see if A is nonzero. Thus, we change the CODE here to
0ff83799
MM		 10288 reflect the simpler comparison operation. */
10289 switch (code)
10290 {
10291 case GTU:
10292 code = NE;
10293 break;
10294
10295 case LEU:
10296 code = EQ;
10297 break;
10298
10299 case GEU:
10300 /* A condition which will always be true. */
10301 code = EQ;
10302 op1 = "%.";
10303 break;
10304
10305 case LTU:
987ba558 10306 /* A condition which will always be false. */
0ff83799
MM		 10307 code = NE;
10308 op1 = "%.";
10309 break;
10310
10311 default:
10312 /* Not a special case. */
c4e992ae 10313 break;
0ff83799
MM		 10314 }
10315 }
10316
10317 /* Relative comparisons are always done against zero. But
10318 equality comparisons are done between two operands, and therefore
10319 do not require a `z' in the assembly language output. */
10320 need_z_p = (!float_p && code != EQ && code != NE);
7dac2f89 10321 /* For comparisons against zero, the zero is not provided
0ff83799
MM		 10322 explicitly. */
10323 if (need_z_p)
10324 op2 = "";
10325
10326 /* Begin by terminating the buffer. That way we can always use
10327 strcat to add to it. */
10328 buffer[0] = '\0';
10329
7dac2f89 10330 switch (length)
0ff83799
MM		 10331 {
10332 case 4:
10333 case 8:
10334 /* Just a simple conditional branch. */
10335 if (float_p)
10336 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
10337 inverted_p ? inverted_comp : comp);
10338 else
10339 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
10340 inverted_p ? inverted_comp : comp,
10341 need_z_p ? "z" : "",
10342 op1,
10343 op2);
10344 return buffer;
10345
10346 case 12:
10347 case 16:
852dff61
AO		 10348 case 24:
10349 case 28:
0ff83799
MM		 10350 {
10351 /* Generate a reversed conditional branch around ` j'
10352 instruction:
10353
10354 .set noreorder
10355 .set nomacro
10356 bc l
852dff61 10357 delay_slot or #nop
0ff83799 10358 j target
852dff61
AO		 10359 #nop
10360 l:
0ff83799
MM		 10361 .set macro
10362 .set reorder
852dff61
AO		 10363
10364 If the original branch was a likely branch, the delay slot
10365 must be executed only if the branch is taken, so generate:
10366
10367 .set noreorder
10368 .set nomacro
10369 bc l
10370 #nop
10371 j target
10372 delay slot or #nop
0ff83799 10373 l:
852dff61
AO		 10374 .set macro
10375 .set reorder
cafe096b 10376
852dff61
AO		 10377 When generating non-embedded PIC, instead of:
10378
10379 j target
10380
10381 we emit:
0ff83799 10382
852dff61
AO		 10383 .set noat
10384 la $at, target
10385 jr $at
10386 .set at
53c12e8d
JE		 10387 */
10388
10389 rtx orig_target;
10390 rtx target = gen_label_rtx ();
10391
53c12e8d
JE		 10392 orig_target = operands[1];
10393 operands[1] = target;
10394 /* Generate the reversed comparison. This takes four
0ff83799
MM		 10395 bytes. */
10396 if (float_p)
53c12e8d
JE		 10397 sprintf (buffer, "%%*b%s\t%%Z2%%1",
10398 inverted_p ? comp : inverted_comp);
0ff83799 10399 else
53c12e8d 10400 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
0ff83799
MM		 10401 inverted_p ? comp : inverted_comp,
10402 need_z_p ? "z" : "",
10403 op1,
53c12e8d
JE		 10404 op2);
10405 output_asm_insn (buffer, operands);
53c12e8d 10406
852dff61
AO		 10407 if (length != 16 && length != 28 && ! mips_branch_likely)
10408 {
10409 /* Output delay slot instruction. */
10410 rtx insn = final_sequence;
10411 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
10412 optimize, 0, 1);
10413 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
10414 }
10415 else
10416 output_asm_insn ("%#", 0);
53c12e8d 10417
852dff61
AO		 10418 if (length <= 16)
10419 output_asm_insn ("j\t%0", &orig_target);
10420 else
10421 {
10422 if (Pmode == DImode)
10423 output_asm_insn ("%[dla\t%@,%0\n\tjr\t%@%]", &orig_target);
10424 else
10425 output_asm_insn ("%[la\t%@,%0\n\tjr\t%@%]", &orig_target);
10426 }
10427
10428 if (length != 16 && length != 28 && mips_branch_likely)
53c12e8d
JE		 10429 {
10430 /* Output delay slot instruction. */
10431 rtx insn = final_sequence;
10432 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
10433 optimize, 0, 1);
10434 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
10435 }
852dff61
AO		 10436 else
10437 output_asm_insn ("%#", 0);
10438
4977bab6 10439 (*targetm.asm_out.internal_label) (asm_out_file, "L",
53c12e8d 10440 CODE_LABEL_NUMBER (target));
852dff61 10441
53c12e8d 10442 return "";
0ff83799
MM		 10443 }
10444
10445 /* We do not currently use this code. It handles jumps to
10446 arbitrary locations, using `jr', even across a 256MB boundary.
10447 We could add a -mhuge switch, and then use this code instead of
10448 the `j' alternative above when -mhuge was used. */
10449#if 0
10450 case 16:
10451 case 20:
10452 {
10453 /* Generate a reversed conditional branch around a `jr'
10454 instruction:
10455
10456 .set noreorder
10457 .set nomacro
10458 .set noat
10459 bc l
10460 la $at, target
10461 jr $at
10462 .set at
10463 .set macro
10464 .set reorder
10465 l:
10466
10467 Not pretty, but allows a conditional branch anywhere in the
10468 32-bit address space. If the original branch is annulled,
10469 then the instruction in the delay slot should be executed
10470 only if the branch is taken. The la instruction is really
10471 a macro which will usually take eight bytes, but sometimes
10472 takes only four, if the instruction to which we're jumping
10473 gets its own entry in the global pointer table, which will
10474 happen if its a case label. The assembler will then
10475 generate only a four-byte sequence, rather than eight, and
10476 there seems to be no way to tell it not to. Thus, we can't
10477 just use a `.+x' addressing form; we don't know what value
7dac2f89 10478 to give for `x'.
0ff83799
MM		 10479
10480 So, we resort to using the explicit relocation syntax
10481 available in the assembler and do:
10482
10483 lw $at,%got_page(target)($gp)
10484 daddiu $at,$at,%got_ofst(target)
10485
10486 That way, this always takes up eight bytes, and we can use
10487 the `.+x' form. Of course, these explicit machinations
10488 with relocation will not work with old assemblers. Then
10489 again, neither do out-of-range branches, so we haven't lost
10490 anything. */
10491
10492 /* The target of the reversed branch. */
83182544 10493 const char *const target
0ff83799 10494 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
bd9f1972
KG		 10495 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
10496 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
0ff83799
MM		 10497 char *c;
10498
10499 strcpy (buffer, "%(%<%[");
10500 c = strchr (buffer, '\0');
7dac2f89 10501 /* Generate the reversed comparision. This takes four
0ff83799
MM		 10502 bytes. */
10503 if (float_p)
10504 sprintf (c, "%%*b%s\t%%Z2%s",
10505 inverted_p ? comp : inverted_comp,
10506 target);
10507 else
10508 sprintf (c, "%%*b%s%s\t%s%s,%s",
10509 inverted_p ? comp : inverted_comp,
10510 need_z_p ? "z" : "",
10511 op1,
10512 op2,
10513 target);
10514 c = strchr (buffer, '\0');
10515 /* Generate the load-address, and jump. This takes twelve
10516 bytes, for a total of 16. */
10517 sprintf (c,
10518 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10519 at_register,
10520 gp_register,
10521 at_register,
10522 at_register,
10523 at_register);
10524 if (length == 20)
10525 /* The delay slot was unfilled. Since we're inside
10526 .noreorder, the assembler will not fill in the NOP for
10527 us, so we must do it ourselves. */
10528 strcat (buffer, "\n\tnop");
10529 strcat (buffer, "%]%>%)");
10530 return buffer;
10531 }
10532#endif
10533
10534 default:
10535 abort ();
10536 }
10537
10538 /* NOTREACHED */
10539 return 0;
10540}
a27fb29b
RS		 10541\f
10542/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10543 with a final "000" replaced by "k". Ignore case.
10544
10545 Note: this function is shared between GCC and GAS. */
d07d525a 10546
a27fb29b
RS		 10547static bool
10548mips_strict_matching_cpu_name_p (canonical, given)
10549 const char *canonical, *given;
7dac2f89 10550{
a27fb29b
RS		 10551 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10552 given++, canonical++;
7dac2f89 10553
a27fb29b
RS		 10554 return ((*given == 0 && *canonical == 0)
10555 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10556}
7dac2f89 10557
f41a6bf1 10558
a27fb29b
RS		 10559/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10560 CPU name. We've traditionally allowed a lot of variation here.
7dac2f89 10561
a27fb29b 10562 Note: this function is shared between GCC and GAS. */
7dac2f89 10563
a27fb29b
RS		 10564static bool
10565mips_matching_cpu_name_p (canonical, given)
10566 const char *canonical, *given;
10567{
10568 /* First see if the name matches exactly, or with a final "000"
10569 turned into "k". */
10570 if (mips_strict_matching_cpu_name_p (canonical, given))
10571 return true;
7dac2f89 10572
a27fb29b
RS		 10573 /* If not, try comparing based on numerical designation alone.
10574 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10575 if (TOLOWER (*given) == 'r')
10576 given++;
10577 if (!ISDIGIT (*given))
10578 return false;
7dac2f89 10579
a27fb29b
RS		 10580 /* Skip over some well-known prefixes in the canonical name,
10581 hoping to find a number there too. */
10582 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10583 canonical += 2;
10584 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10585 canonical += 2;
10586 else if (TOLOWER (canonical[0]) == 'r')
10587 canonical += 1;
7dac2f89 10588
a27fb29b
RS		 10589 return mips_strict_matching_cpu_name_p (canonical, given);
10590}
7dac2f89 10591
7dac2f89 10592
a27fb29b
RS		 10593/* Parse an option that takes the name of a processor as its argument.
10594 OPTION is the name of the option and CPU_STRING is the argument.
10595 Return the corresponding processor enumeration if the CPU_STRING is
10596 recognized, otherwise report an error and return null.
7dac2f89 10597
a27fb29b
RS		 10598 A similar function exists in GAS. */
10599
10600static const struct mips_cpu_info *
10601mips_parse_cpu (option, cpu_string)
10602 const char *option, *cpu_string;
10603{
10604 const struct mips_cpu_info *p;
10605 const char *s;
7dac2f89 10606
a27fb29b
RS		 10607 /* In the past, we allowed upper-case CPU names, but it doesn't
10608 work well with the multilib machinery. */
10609 for (s = cpu_string; *s != 0; s++)
10610 if (ISUPPER (*s))
10611 {
10612 warning ("the cpu name must be lower case");
10613 break;
10614 }
7dac2f89 10615
a27fb29b
RS		 10616 /* 'from-abi' selects the most compatible architecture for the given
10617 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10618 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10619 version. Look first at the -mgp options, if given, otherwise base
10620 the choice on MASK_64BIT in TARGET_DEFAULT. */
10621 if (strcasecmp (cpu_string, "from-abi") == 0)
10622 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10623 : ABI_NEEDS_64BIT_REGS ? 3
10624 : (TARGET_64BIT ? 3 : 1));
10625
10626 /* 'default' has traditionally been a no-op. Probably not very useful. */
10627 if (strcasecmp (cpu_string, "default") == 0)
10628 return 0;
10629
10630 for (p = mips_cpu_info_table; p->name != 0; p++)
10631 if (mips_matching_cpu_name_p (p->name, cpu_string))
10632 return p;
10633
10634 error ("bad value (%s) for %s", cpu_string, option);
10635 return 0;
7dac2f89 10636}
7c262518 10637
a27fb29b
RS		 10638
10639/* Return the processor associated with the given ISA level, or null
10640 if the ISA isn't valid. */
10641
10642static const struct mips_cpu_info *
10643mips_cpu_info_from_isa (isa)
10644 int isa;
10645{
10646 const struct mips_cpu_info *p;
10647
10648 for (p = mips_cpu_info_table; p->name != 0; p++)
10649 if (p->isa == isa)
10650 return p;
10651
10652 return 0;
10653}
10654\f
c237e94a
ZW		 10655/* Adjust the cost of INSN based on the relationship between INSN that
10656 is dependent on DEP_INSN through the dependence LINK. The default
10657 is to make no adjustment to COST.
10658
10659 On the MIPS, ignore the cost of anti- and output-dependencies. */
10660static int
10661mips_adjust_cost (insn, link, dep, cost)
10662 rtx insn ATTRIBUTE_UNUSED;
10663 rtx link;
10664 rtx dep ATTRIBUTE_UNUSED;
10665 int cost;
10666{
10667 if (REG_NOTE_KIND (link) != 0)
10668 return 0; /* Anti or output dependence. */
10669 return cost;
10670}
10671
ae46c4e0
RH		 10672/* ??? This could be replaced with the default elf version if
10673 TARGET_IS_SMALL_DATA_P is set properly. */
b2bcb32d 10674
ae46c4e0 10675static void
b2bcb32d
L		 10676mips_unique_section (decl, reloc)
10677 tree decl;
10678 int reloc;
10679{
10680 int len, size, sec;
920ae24b
RH		 10681 const char *name, *prefix;
10682 char *string;
27c38fbe 10683 static const char *const prefixes[4][2] = {
b2bcb32d
L		 10684 { ".text.", ".gnu.linkonce.t." },
10685 { ".rodata.", ".gnu.linkonce.r." },
10686 { ".data.", ".gnu.linkonce.d." },
10687 { ".sdata.", ".gnu.linkonce.s." }
10688 };
10689
10690 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
772c5265 10691 name = (* targetm.strip_name_encoding) (name);
b2bcb32d
L		 10692 size = int_size_in_bytes (TREE_TYPE (decl));
10693
10694 /* Determine the base section we are interested in:
10695 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10696 if (TREE_CODE (decl) == FUNCTION_DECL)
10697 sec = 0;
10698 else if (DECL_INITIAL (decl) == 0
10699 || DECL_INITIAL (decl) == error_mark_node)
10700 sec = 2;
10701 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
10702 && TREE_CODE (decl) == STRING_CST
10703 && !flag_writable_strings)
10704 {
10705 /* For embedded position independent code, put constant
10706 strings in the text section, because the data section
10707 is limited to 64K in size. For mips16 code, put
10708 strings in the text section so that a PC relative load
10709 instruction can be used to get their address. */
10710 sec = 0;
10711 }
10712 else if (TARGET_EMBEDDED_DATA)
10713 {
10714 /* For embedded applications, always put an object in
10715 read-only data if possible, in order to reduce RAM
10716 usage. */
10717
4e4d733e 10718 if (decl_readonly_section (decl, reloc))
b2bcb32d
L		 10719 sec = 1;
10720 else if (size > 0 && size <= mips_section_threshold)
10721 sec = 3;
10722 else
10723 sec = 2;
10724 }
10725 else
10726 {
10727 /* For hosted applications, always put an object in
10728 small data if possible, as this gives the best
10729 performance. */
10730
10731 if (size > 0 && size <= mips_section_threshold)
10732 sec = 3;
4e4d733e 10733 else if (decl_readonly_section (decl, reloc))
b2bcb32d
L		 10734 sec = 1;
10735 else
10736 sec = 2;
10737 }
10738
10739 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
10740 len = strlen (name) + strlen (prefix);
10741 string = alloca (len + 1);
10742 sprintf (string, "%s%s", prefix, name);
10743
10744 DECL_SECTION_NAME (decl) = build_string (len, string);
10745}
c237e94a 10746
0e5a4ad8
EC		 10747unsigned int
10748mips_hard_regno_nregs (regno, mode)
10749 int regno;
10750 enum machine_mode mode;
10751{
10752 if (! FP_REG_P (regno))
10753 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10754 else
10755 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10756}
10757
54401342
EC		 10758int
10759mips_return_in_memory (type)
10760 tree type;
10761{
10762 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10763 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10764 structures are returned in a register. Objects with varying size
10765 must still be returned in memory, of course. */
10766
10767 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
10768 return (TYPE_MODE (type) == BLKmode);
10769 else
10770 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10771 || (int_size_in_bytes (type) == -1));
10772}
10773
b875d2ee
EC		 10774static int
10775mips_issue_rate ()
10776{
b875d2ee
EC		 10777 switch (mips_tune)
10778 {
5ce6f47b
EC		 10779 case PROCESSOR_R3000: return 1;
10780 case PROCESSOR_R5400: return 2;
10781 case PROCESSOR_R5500: return 2;
b875d2ee
EC		 10782
10783 default:
6d439235 10784 return 1;
b875d2ee 10785 }
54401342 10786
6d439235
EC		 10787 abort ();
10788
b875d2ee 10789}
54401342 10790
5ce6f47b
EC		 10791/* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
10792 processors that have a DFA pipeline description. */
10793
10794static int
10795mips_use_dfa_pipeline_interface ()
10796{
10797 switch (mips_tune)
10798 {
10799 case PROCESSOR_R5400:
10800 case PROCESSOR_R5500:
10801 case PROCESSOR_SR71000:
10802 return true;
10803
10804 default:
10805 return false;
10806 }
10807}
10808
10809
8f2e3902
EC		 10810const char *
10811mips_emit_prefetch (operands)
10812 rtx operands[];
10813{
10814 /* For the mips32/64 architectures the hint fields are arranged
10815 by operation (load/store) and locality (normal/streamed/retained).
10816 Irritatingly, numbers 2 and 3 are reserved leaving no simple
10817 algorithm for figuring the hint. */
10818
10819 int write = INTVAL (operands[1]);
10820 int locality = INTVAL (operands[2]);
10821
10822 static const char * const alt[2][4] = {
10823 {
8f2e3902 10824 "pref\t4,%a0",
1867b624
CD		 10825 "pref\t0,%a0",
10826 "pref\t0,%a0",
8f2e3902
EC		 10827 "pref\t6,%a0"
10828 },
10829 {
8f2e3902 10830 "pref\t5,%a0",
1867b624
CD		 10831 "pref\t1,%a0",
10832 "pref\t1,%a0",
8f2e3902
EC		 10833 "pref\t7,%a0"
10834 }
10835 };
10836
10837 return alt[write][locality];
10838}
10839
10840
920ae24b
RH		 10841\f
10842#ifdef TARGET_IRIX6
10843/* Output assembly to switch to section NAME with attribute FLAGS. */
10844
10845static void
10846iris6_asm_named_section_1 (name, flags, align)
10847 const char *name;
10848 unsigned int flags;
10849 unsigned int align;
10850{
10851 unsigned int sh_type, sh_flags, sh_entsize;
10852
10853 sh_flags = 0;
10854 if (!(flags & SECTION_DEBUG))
10855 sh_flags |= 2; /* SHF_ALLOC */
10856 if (flags & SECTION_WRITE)
10857 sh_flags |= 1; /* SHF_WRITE */
10858 if (flags & SECTION_CODE)
10859 sh_flags |= 4; /* SHF_EXECINSTR */
10860 if (flags & SECTION_SMALL)
10861 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
10862 if (strcmp (name, ".debug_frame") == 0)
10863 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
920ae24b
RH		 10864 if (flags & SECTION_DEBUG)
10865 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
10866 else if (flags & SECTION_BSS)
10867 sh_type = 8; /* SHT_NOBITS */
10868 else
10869 sh_type = 1; /* SHT_PROGBITS */
10870
10871 if (flags & SECTION_CODE)
10872 sh_entsize = 4;
10873 else
10874 sh_entsize = 0;
10875
10876 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
10877 name, sh_type, sh_flags, sh_entsize, align);
10878}
10879
10880static void
10881iris6_asm_named_section (name, flags)
10882 const char *name;
10883 unsigned int flags;
10884{
10885 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
10886 asm_out_file = asm_out_text_file;
10887 iris6_asm_named_section_1 (name, flags, 0);
10888}
10889
10890/* In addition to emitting a .align directive, record the maximum
10891 alignment requested for the current section. */
10892
cafe096b 10893struct GTY (()) iris_section_align_entry
920ae24b
RH		 10894{
10895 const char *name;
10896 unsigned int log;
10897 unsigned int flags;
10898};
10899
10900static htab_t iris_section_align_htab;
10901static FILE *iris_orig_asm_out_file;
10902
10903static int
10904iris_section_align_entry_eq (p1, p2)
10905 const PTR p1;
10906 const PTR p2;
10907{
10908 const struct iris_section_align_entry *old = p1;
10909 const char *new = p2;
10910
10911 return strcmp (old->name, new) == 0;
10912}
10913
10914static hashval_t
10915iris_section_align_entry_hash (p)
10916 const PTR p;
10917{
10918 const struct iris_section_align_entry *old = p;
10919 return htab_hash_string (old->name);
10920}
10921
10922void
10923iris6_asm_output_align (file, log)
10924 FILE *file;
10925 unsigned int log;
10926{
10927 const char *section = current_section_name ();
10928 struct iris_section_align_entry **slot, *entry;
10929
10930 if (! section)
10931 abort ();
10932
10933 slot = (struct iris_section_align_entry **)
10934 htab_find_slot_with_hash (iris_section_align_htab, section,
10935 htab_hash_string (section), INSERT);
10936 entry = *slot;
10937 if (! entry)
10938 {
10939 entry = (struct iris_section_align_entry *)
10940 xmalloc (sizeof (struct iris_section_align_entry));
10941 *slot = entry;
10942 entry->name = section;
10943 entry->log = log;
10944 entry->flags = current_section_flags ();
10945 }
10946 else if (entry->log < log)
10947 entry->log = log;
10948
10949 fprintf (file, "\t.align\t%u\n", log);
10950}
10951
10952/* The Iris assembler does not record alignment from .align directives,
10953 but takes it from the first .section directive seen. Play yet more
10954 file switching games so that we can emit a .section directive at the
10955 beginning of the file with the proper alignment attached. */
0e5a4ad8 10956
920ae24b
RH		 10957void
10958iris6_asm_file_start (stream)
10959 FILE *stream;
10960{
10961 mips_asm_file_start (stream);
10962
10963 iris_orig_asm_out_file = asm_out_file;
10964 stream = tmpfile ();
10965 asm_out_file = stream;
10966 asm_out_data_file = stream;
10967 if (! TARGET_FILE_SWITCHING)
10968 asm_out_text_file = stream;
10969
10970 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
10971 iris_section_align_entry_eq, NULL);
10972}
10973
10974static int
10975iris6_section_align_1 (slot, data)
10976 void **slot;
10977 void *data ATTRIBUTE_UNUSED;
10978{
10979 const struct iris_section_align_entry *entry
10980 = *(const struct iris_section_align_entry **) slot;
10981
10982 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10983 return 1;
10984}
10985
10986void
10987iris6_asm_file_end (stream)
10988 FILE *stream;
10989{
10990 /* Emit section directives with the proper alignment at the top of the
10991 real output file. */
10992 asm_out_file = iris_orig_asm_out_file;
10993 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10994
10995 /* Copy the data emitted to the temp file to the real output file. */
10996 copy_file_data (asm_out_file, stream);
10997
10998 mips_asm_file_end (stream);
10999}
11000#endif /* TARGET_IRIX6 */
e2500fed
GK		 11001
11002#include "gt-mips.h"
Mirror of https://gcc.gnu.org/git/gcc.git