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dfad12b5 | 1 | /* Subroutines used for MIPS code generation. |
23a5b65a | 2 | Copyright (C) 1989-2014 Free Software Foundation, Inc. |
cee98a59 | 3 | Contributed by A. Lichnewsky, lich@inria.inria.fr. |
b2a68403 | 4 | Changes by Michael Meissner, meissner@osf.org. |
85f65093 | 5 | 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and |
147255d8 | 6 | Brendan Eich, brendan@microunity.com. |
cee98a59 | 7 | |
7ec022b2 | 8 | This file is part of GCC. |
cee98a59 | 9 | |
7ec022b2 | 10 | GCC is free software; you can redistribute it and/or modify |
cee98a59 | 11 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
cee98a59 MM |
13 | any later version. |
14 | ||
7ec022b2 | 15 | GCC is distributed in the hope that it will be useful, |
cee98a59 MM |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
cee98a59 MM |
23 | |
24 | #include "config.h" | |
50b2596f | 25 | #include "system.h" |
4977bab6 ZW |
26 | #include "coretypes.h" |
27 | #include "tm.h" | |
cee98a59 MM |
28 | #include "rtl.h" |
29 | #include "regs.h" | |
30 | #include "hard-reg-set.h" | |
cee98a59 MM |
31 | #include "insn-config.h" |
32 | #include "conditions.h" | |
cee98a59 | 33 | #include "insn-attr.h" |
cee98a59 | 34 | #include "recog.h" |
c5c76735 | 35 | #include "output.h" |
cee98a59 | 36 | #include "tree.h" |
d8a2d370 DN |
37 | #include "varasm.h" |
38 | #include "stringpool.h" | |
39 | #include "stor-layout.h" | |
40 | #include "calls.h" | |
83685514 AM |
41 | #include "hashtab.h" |
42 | #include "hash-set.h" | |
43 | #include "vec.h" | |
44 | #include "machmode.h" | |
45 | #include "input.h" | |
49ad7cfa | 46 | #include "function.h" |
cee98a59 | 47 | #include "expr.h" |
c15c90bb | 48 | #include "optabs.h" |
e2ff10a9 | 49 | #include "libfuncs.h" |
cee98a59 | 50 | #include "flags.h" |
2bcb2ab3 | 51 | #include "reload.h" |
bd9f1972 | 52 | #include "tm_p.h" |
d07d525a | 53 | #include "ggc.h" |
7719ffbf | 54 | #include "gstab.h" |
3a4f280b | 55 | #include "hash-table.h" |
920ae24b | 56 | #include "debug.h" |
672a6f42 NB |
57 | #include "target.h" |
58 | #include "target-def.h" | |
3b601ca3 | 59 | #include "common/common-target.h" |
2743a50a | 60 | #include "langhooks.h" |
60393bbc AM |
61 | #include "dominance.h" |
62 | #include "cfg.h" | |
63 | #include "cfgrtl.h" | |
64 | #include "cfganal.h" | |
65 | #include "lcm.h" | |
66 | #include "cfgbuild.h" | |
67 | #include "cfgcleanup.h" | |
68 | #include "predict.h" | |
2fb9a547 | 69 | #include "basic-block.h" |
60393bbc | 70 | #include "sched-int.h" |
2fb9a547 AM |
71 | #include "tree-ssa-alias.h" |
72 | #include "internal-fn.h" | |
73 | #include "gimple-fold.h" | |
74 | #include "tree-eh.h" | |
75 | #include "gimple-expr.h" | |
76 | #include "is-a.h" | |
18f429e2 | 77 | #include "gimple.h" |
45b0be94 | 78 | #include "gimplify.h" |
912f2dac | 79 | #include "bitmap.h" |
566dfd71 | 80 | #include "diagnostic.h" |
5aa62249 | 81 | #include "target-globals.h" |
96e45421 | 82 | #include "opts.h" |
fb0d5c60 | 83 | #include "tree-pass.h" |
c5a12e26 | 84 | #include "context.h" |
c582198b AM |
85 | #include "hash-map.h" |
86 | #include "plugin-api.h" | |
87 | #include "ipa-ref.h" | |
11237229 | 88 | #include "cgraph.h" |
9b2b7279 | 89 | #include "builtins.h" |
187804d4 | 90 | #include "rtl-iter.h" |
cee98a59 | 91 | |
65239d20 | 92 | /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ |
108b61d5 RS |
93 | #define UNSPEC_ADDRESS_P(X) \ |
94 | (GET_CODE (X) == UNSPEC \ | |
95 | && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ | |
96 | && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) | |
97 | ||
98 | /* Extract the symbol or label from UNSPEC wrapper X. */ | |
99 | #define UNSPEC_ADDRESS(X) \ | |
100 | XVECEXP (X, 0, 0) | |
101 | ||
102 | /* Extract the symbol type from UNSPEC wrapper X. */ | |
103 | #define UNSPEC_ADDRESS_TYPE(X) \ | |
104 | ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) | |
105 | ||
be763023 | 106 | /* The maximum distance between the top of the stack frame and the |
e1260576 RS |
107 | value $sp has when we save and restore registers. |
108 | ||
109 | The value for normal-mode code must be a SMALL_OPERAND and must | |
110 | preserve the maximum stack alignment. We therefore use a value | |
111 | of 0x7ff0 in this case. | |
112 | ||
22c4c869 CM |
113 | microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff), |
114 | so we use a maximum of 0x7f0 for TARGET_MICROMIPS. | |
115 | ||
e1260576 RS |
116 | MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by |
117 | up to 0x7f8 bytes and can usually save or restore all the registers | |
118 | that we need to save or restore. (Note that we can only use these | |
119 | instructions for o32, for which the stack alignment is 8 bytes.) | |
120 | ||
121 | We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and | |
122 | RESTORE are not available. We can then use unextended instructions | |
123 | to save and restore registers, and to allocate and deallocate the top | |
124 | part of the frame. */ | |
125 | #define MIPS_MAX_FIRST_STACK_STEP \ | |
22c4c869 CM |
126 | (!TARGET_COMPRESSION ? 0x7ff0 \ |
127 | : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \ | |
e1260576 | 128 | : TARGET_64BIT ? 0x100 : 0x400) |
be763023 | 129 | |
dc884a86 | 130 | /* True if INSN is a mips.md pattern or asm statement. */ |
34f0d87a SB |
131 | /* ??? This test exists through the compiler, perhaps it should be |
132 | moved to rtl.h. */ | |
dc884a86 | 133 | #define USEFUL_INSN_P(INSN) \ |
006b29ab | 134 | (NONDEBUG_INSN_P (INSN) \ |
dc884a86 | 135 | && GET_CODE (PATTERN (INSN)) != USE \ |
34f0d87a | 136 | && GET_CODE (PATTERN (INSN)) != CLOBBER) |
dc884a86 RS |
137 | |
138 | /* If INSN is a delayed branch sequence, return the first instruction | |
139 | in the sequence, otherwise return INSN itself. */ | |
140 | #define SEQ_BEGIN(INSN) \ | |
141 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
c6f971f4 | 142 | ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \ |
dc884a86 RS |
143 | : (INSN)) |
144 | ||
145 | /* Likewise for the last instruction in a delayed branch sequence. */ | |
146 | #define SEQ_END(INSN) \ | |
147 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
c6f971f4 DM |
148 | ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \ |
149 | 0, \ | |
150 | XVECLEN (PATTERN (INSN), 0) - 1)) \ | |
dc884a86 RS |
151 | : (INSN)) |
152 | ||
153 | /* Execute the following loop body with SUBINSN set to each instruction | |
154 | between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */ | |
155 | #define FOR_EACH_SUBINSN(SUBINSN, INSN) \ | |
156 | for ((SUBINSN) = SEQ_BEGIN (INSN); \ | |
157 | (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \ | |
158 | (SUBINSN) = NEXT_INSN (SUBINSN)) | |
cafe096b | 159 | |
e1260576 RS |
160 | /* True if bit BIT is set in VALUE. */ |
161 | #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) | |
162 | ||
c640a3bd RS |
163 | /* Return the opcode for a ptr_mode load of the form: |
164 | ||
165 | l[wd] DEST, OFFSET(BASE). */ | |
166 | #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \ | |
167 | (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \ | |
168 | | ((BASE) << 21) \ | |
169 | | ((DEST) << 16) \ | |
170 | | (OFFSET)) | |
171 | ||
172 | /* Return the opcode to move register SRC into register DEST. */ | |
173 | #define MIPS_MOVE(DEST, SRC) \ | |
174 | ((TARGET_64BIT ? 0x2d : 0x21) \ | |
175 | | ((DEST) << 11) \ | |
176 | | ((SRC) << 21)) | |
177 | ||
178 | /* Return the opcode for: | |
179 | ||
180 | lui DEST, VALUE. */ | |
181 | #define MIPS_LUI(DEST, VALUE) \ | |
182 | ((0xf << 26) | ((DEST) << 16) | (VALUE)) | |
183 | ||
184 | /* Return the opcode to jump to register DEST. */ | |
185 | #define MIPS_JR(DEST) \ | |
186 | (((DEST) << 21) | 0x8) | |
187 | ||
188 | /* Return the opcode for: | |
189 | ||
190 | bal . + (1 + OFFSET) * 4. */ | |
191 | #define MIPS_BAL(OFFSET) \ | |
192 | ((0x1 << 26) | (0x11 << 16) | (OFFSET)) | |
193 | ||
194 | /* Return the usual opcode for a nop. */ | |
195 | #define MIPS_NOP 0 | |
196 | ||
cafe096b EC |
197 | /* Classifies an address. |
198 | ||
cafe096b EC |
199 | ADDRESS_REG |
200 | A natural register + offset address. The register satisfies | |
201 | mips_valid_base_register_p and the offset is a const_arith_operand. | |
202 | ||
203 | ADDRESS_LO_SUM | |
204 | A LO_SUM rtx. The first operand is a valid base register and | |
205 | the second operand is a symbolic address. | |
206 | ||
207 | ADDRESS_CONST_INT | |
208 | A signed 16-bit constant address. | |
209 | ||
210 | ADDRESS_SYMBOLIC: | |
65239d20 | 211 | A constant symbolic address. */ |
cafe096b | 212 | enum mips_address_type { |
cafe096b EC |
213 | ADDRESS_REG, |
214 | ADDRESS_LO_SUM, | |
215 | ADDRESS_CONST_INT, | |
216 | ADDRESS_SYMBOLIC | |
217 | }; | |
218 | ||
41030557 RS |
219 | /* Macros to create an enumeration identifier for a function prototype. */ |
220 | #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B | |
221 | #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C | |
222 | #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D | |
223 | #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E | |
224 | ||
65239d20 RS |
225 | /* Classifies the prototype of a built-in function. */ |
226 | enum mips_function_type { | |
41030557 RS |
227 | #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST, |
228 | #include "config/mips/mips-ftypes.def" | |
229 | #undef DEF_MIPS_FTYPE | |
4ca1f68f RS |
230 | MIPS_MAX_FTYPE_MAX |
231 | }; | |
232 | ||
65239d20 RS |
233 | /* Specifies how a built-in function should be converted into rtl. */ |
234 | enum mips_builtin_type { | |
235 | /* The function corresponds directly to an .md pattern. The return | |
4ca1f68f RS |
236 | value is mapped to operand 0 and the arguments are mapped to |
237 | operands 1 and above. */ | |
238 | MIPS_BUILTIN_DIRECT, | |
239 | ||
65239d20 | 240 | /* The function corresponds directly to an .md pattern. There is no return |
118ea793 CF |
241 | value and the arguments are mapped to operands 0 and above. */ |
242 | MIPS_BUILTIN_DIRECT_NO_TARGET, | |
243 | ||
65239d20 | 244 | /* The function corresponds to a comparison instruction followed by |
4ca1f68f RS |
245 | a mips_cond_move_tf_ps pattern. The first two arguments are the |
246 | values to compare and the second two arguments are the vector | |
247 | operands for the movt.ps or movf.ps instruction (in assembly order). */ | |
248 | MIPS_BUILTIN_MOVF, | |
249 | MIPS_BUILTIN_MOVT, | |
250 | ||
65239d20 | 251 | /* The function corresponds to a V2SF comparison instruction. Operand 0 |
4ca1f68f RS |
252 | of this instruction is the result of the comparison, which has mode |
253 | CCV2 or CCV4. The function arguments are mapped to operands 1 and | |
254 | above. The function's return value is an SImode boolean that is | |
255 | true under the following conditions: | |
256 | ||
257 | MIPS_BUILTIN_CMP_ANY: one of the registers is true | |
258 | MIPS_BUILTIN_CMP_ALL: all of the registers are true | |
259 | MIPS_BUILTIN_CMP_LOWER: the first register is true | |
260 | MIPS_BUILTIN_CMP_UPPER: the second register is true. */ | |
261 | MIPS_BUILTIN_CMP_ANY, | |
262 | MIPS_BUILTIN_CMP_ALL, | |
263 | MIPS_BUILTIN_CMP_UPPER, | |
264 | MIPS_BUILTIN_CMP_LOWER, | |
265 | ||
266 | /* As above, but the instruction only sets a single $fcc register. */ | |
118ea793 CF |
267 | MIPS_BUILTIN_CMP_SINGLE, |
268 | ||
269 | /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ | |
270 | MIPS_BUILTIN_BPOSGE32 | |
4ca1f68f RS |
271 | }; |
272 | ||
65239d20 | 273 | /* Invoke MACRO (COND) for each C.cond.fmt condition. */ |
308cd611 RS |
274 | #define MIPS_FP_CONDITIONS(MACRO) \ |
275 | MACRO (f), \ | |
276 | MACRO (un), \ | |
277 | MACRO (eq), \ | |
278 | MACRO (ueq), \ | |
279 | MACRO (olt), \ | |
280 | MACRO (ult), \ | |
281 | MACRO (ole), \ | |
282 | MACRO (ule), \ | |
283 | MACRO (sf), \ | |
284 | MACRO (ngle), \ | |
285 | MACRO (seq), \ | |
286 | MACRO (ngl), \ | |
287 | MACRO (lt), \ | |
288 | MACRO (nge), \ | |
289 | MACRO (le), \ | |
290 | MACRO (ngt) | |
291 | ||
292 | /* Enumerates the codes above as MIPS_FP_COND_<X>. */ | |
293 | #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X | |
294 | enum mips_fp_condition { | |
295 | MIPS_FP_CONDITIONS (DECLARE_MIPS_COND) | |
296 | }; | |
6d51cc90 | 297 | #undef DECLARE_MIPS_COND |
308cd611 RS |
298 | |
299 | /* Index X provides the string representation of MIPS_FP_COND_<X>. */ | |
300 | #define STRINGIFY(X) #X | |
301 | static const char *const mips_fp_conditions[] = { | |
302 | MIPS_FP_CONDITIONS (STRINGIFY) | |
303 | }; | |
6d51cc90 RS |
304 | #undef STRINGIFY |
305 | ||
306 | /* A class used to control a comdat-style stub that we output in each | |
307 | translation unit that needs it. */ | |
308 | class mips_one_only_stub { | |
309 | public: | |
310 | virtual ~mips_one_only_stub () {} | |
311 | ||
312 | /* Return the name of the stub. */ | |
313 | virtual const char *get_name () = 0; | |
314 | ||
315 | /* Output the body of the function to asm_out_file. */ | |
316 | virtual void output_body () = 0; | |
317 | }; | |
308cd611 | 318 | |
4670abb0 RS |
319 | /* Tuning information that is automatically derived from other sources |
320 | (such as the scheduler). */ | |
321 | static struct { | |
322 | /* The architecture and tuning settings that this structure describes. */ | |
323 | enum processor arch; | |
324 | enum processor tune; | |
325 | ||
326 | /* True if this structure describes MIPS16 settings. */ | |
327 | bool mips16_p; | |
328 | ||
329 | /* True if the structure has been initialized. */ | |
330 | bool initialized_p; | |
331 | ||
332 | /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0" | |
333 | when optimizing for speed. */ | |
334 | bool fast_mult_zero_zero_p; | |
335 | } mips_tuning_info; | |
336 | ||
16dc5c28 | 337 | /* Information about a function's frame layout. */ |
d1b38208 | 338 | struct GTY(()) mips_frame_info { |
37017f4d RS |
339 | /* The size of the frame in bytes. */ |
340 | HOST_WIDE_INT total_size; | |
341 | ||
342 | /* The number of bytes allocated to variables. */ | |
343 | HOST_WIDE_INT var_size; | |
344 | ||
345 | /* The number of bytes allocated to outgoing function arguments. */ | |
346 | HOST_WIDE_INT args_size; | |
347 | ||
348 | /* The number of bytes allocated to the .cprestore slot, or 0 if there | |
349 | is no such slot. */ | |
350 | HOST_WIDE_INT cprestore_size; | |
351 | ||
37017f4d RS |
352 | /* Bit X is set if the function saves or restores GPR X. */ |
353 | unsigned int mask; | |
354 | ||
355 | /* Likewise FPR X. */ | |
356 | unsigned int fmask; | |
357 | ||
e19da24c CF |
358 | /* Likewise doubleword accumulator X ($acX). */ |
359 | unsigned int acc_mask; | |
360 | ||
361 | /* The number of GPRs, FPRs, doubleword accumulators and COP0 | |
362 | registers saved. */ | |
37017f4d RS |
363 | unsigned int num_gp; |
364 | unsigned int num_fp; | |
e19da24c CF |
365 | unsigned int num_acc; |
366 | unsigned int num_cop0_regs; | |
37017f4d | 367 | |
e19da24c CF |
368 | /* The offset of the topmost GPR, FPR, accumulator and COP0-register |
369 | save slots from the top of the frame, or zero if no such slots are | |
370 | needed. */ | |
37017f4d RS |
371 | HOST_WIDE_INT gp_save_offset; |
372 | HOST_WIDE_INT fp_save_offset; | |
e19da24c CF |
373 | HOST_WIDE_INT acc_save_offset; |
374 | HOST_WIDE_INT cop0_save_offset; | |
37017f4d RS |
375 | |
376 | /* Likewise, but giving offsets from the bottom of the frame. */ | |
377 | HOST_WIDE_INT gp_sp_offset; | |
378 | HOST_WIDE_INT fp_sp_offset; | |
e19da24c CF |
379 | HOST_WIDE_INT acc_sp_offset; |
380 | HOST_WIDE_INT cop0_sp_offset; | |
37017f4d | 381 | |
c376dbfb DD |
382 | /* Similar, but the value passed to _mcount. */ |
383 | HOST_WIDE_INT ra_fp_offset; | |
384 | ||
ba6adec4 | 385 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ |
f374e413 RS |
386 | HOST_WIDE_INT arg_pointer_offset; |
387 | ||
ba6adec4 | 388 | /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ |
f374e413 | 389 | HOST_WIDE_INT hard_frame_pointer_offset; |
b2471838 RS |
390 | }; |
391 | ||
d1b38208 | 392 | struct GTY(()) machine_function { |
4b11e406 RS |
393 | /* The next floating-point condition-code register to allocate |
394 | for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */ | |
395 | unsigned int next_fcc; | |
396 | ||
65239d20 | 397 | /* The register returned by mips16_gp_pseudo_reg; see there for details. */ |
c8d1b2b7 | 398 | rtx mips16_gp_pseudo_rtx; |
b2471838 | 399 | |
4001cd89 RS |
400 | /* The number of extra stack bytes taken up by register varargs. |
401 | This area is allocated by the callee at the very top of the frame. */ | |
402 | int varargs_size; | |
403 | ||
65239d20 | 404 | /* The current frame information, calculated by mips_compute_frame_info. */ |
b2471838 RS |
405 | struct mips_frame_info frame; |
406 | ||
8d9d9172 RS |
407 | /* The register to use as the function's global pointer, or INVALID_REGNUM |
408 | if the function doesn't need one. */ | |
f833ffd4 | 409 | unsigned int global_pointer; |
6f2993e5 | 410 | |
0c433c31 RS |
411 | /* How many instructions it takes to load a label into $AT, or 0 if |
412 | this property hasn't yet been calculated. */ | |
5a486834 | 413 | unsigned int load_label_num_insns; |
0c433c31 | 414 | |
6f2993e5 RS |
415 | /* True if mips_adjust_insn_length should ignore an instruction's |
416 | hazard attribute. */ | |
417 | bool ignore_hazard_length_p; | |
418 | ||
419 | /* True if the whole function is suitable for .set noreorder and | |
420 | .set nomacro. */ | |
421 | bool all_noreorder_p; | |
108b61d5 | 422 | |
0c433c31 RS |
423 | /* True if the function has "inflexible" and "flexible" references |
424 | to the global pointer. See mips_cfun_has_inflexible_gp_ref_p | |
425 | and mips_cfun_has_flexible_gp_ref_p for details. */ | |
426 | bool has_inflexible_gp_insn_p; | |
427 | bool has_flexible_gp_insn_p; | |
428 | ||
429 | /* True if the function's prologue must load the global pointer | |
430 | value into pic_offset_table_rtx and store the same value in | |
431 | the function's cprestore slot (if any). Even if this value | |
432 | is currently false, we may decide to set it to true later; | |
433 | see mips_must_initialize_gp_p () for details. */ | |
434 | bool must_initialize_gp_p; | |
435 | ||
436 | /* True if the current function must restore $gp after any potential | |
437 | clobber. This value is only meaningful during the first post-epilogue | |
438 | split_insns pass; see mips_must_initialize_gp_p () for details. */ | |
439 | bool must_restore_gp_when_clobbered_p; | |
d6076cee | 440 | |
e19da24c CF |
441 | /* True if this is an interrupt handler. */ |
442 | bool interrupt_handler_p; | |
443 | ||
444 | /* True if this is an interrupt handler that uses shadow registers. */ | |
445 | bool use_shadow_register_set_p; | |
446 | ||
447 | /* True if this is an interrupt handler that should keep interrupts | |
448 | masked. */ | |
449 | bool keep_interrupts_masked_p; | |
450 | ||
451 | /* True if this is an interrupt handler that should use DERET | |
452 | instead of ERET. */ | |
453 | bool use_debug_exception_return_p; | |
c8d1b2b7 AO |
454 | }; |
455 | ||
4d72536e | 456 | /* Information about a single argument. */ |
65239d20 | 457 | struct mips_arg_info { |
4d72536e RS |
458 | /* True if the argument is passed in a floating-point register, or |
459 | would have been if we hadn't run out of registers. */ | |
460 | bool fpr_p; | |
461 | ||
4d72536e RS |
462 | /* The number of words passed in registers, rounded up. */ |
463 | unsigned int reg_words; | |
464 | ||
b11a9d5f RS |
465 | /* For EABI, the offset of the first register from GP_ARG_FIRST or |
466 | FP_ARG_FIRST. For other ABIs, the offset of the first register from | |
467 | the start of the ABI's argument structure (see the CUMULATIVE_ARGS | |
468 | comment for details). | |
469 | ||
470 | The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely | |
4d72536e RS |
471 | on the stack. */ |
472 | unsigned int reg_offset; | |
473 | ||
474 | /* The number of words that must be passed on the stack, rounded up. */ | |
475 | unsigned int stack_words; | |
476 | ||
477 | /* The offset from the start of the stack overflow area of the argument's | |
a0ab749a | 478 | first stack word. Only meaningful when STACK_WORDS is nonzero. */ |
4d72536e RS |
479 | unsigned int stack_offset; |
480 | }; | |
c8d1b2b7 | 481 | |
cafe096b EC |
482 | /* Information about an address described by mips_address_type. |
483 | ||
cafe096b EC |
484 | ADDRESS_CONST_INT |
485 | No fields are used. | |
486 | ||
487 | ADDRESS_REG | |
488 | REG is the base register and OFFSET is the constant offset. | |
489 | ||
490 | ADDRESS_LO_SUM | |
65239d20 RS |
491 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE |
492 | is the type of symbol it references. | |
cafe096b EC |
493 | |
494 | ADDRESS_SYMBOLIC | |
65239d20 RS |
495 | SYMBOL_TYPE is the type of symbol that the address references. */ |
496 | struct mips_address_info { | |
108b61d5 | 497 | enum mips_address_type type; |
cafe096b EC |
498 | rtx reg; |
499 | rtx offset; | |
108b61d5 | 500 | enum mips_symbol_type symbol_type; |
cafe096b EC |
501 | }; |
502 | ||
b259a9a6 RS |
503 | /* One stage in a constant building sequence. These sequences have |
504 | the form: | |
505 | ||
506 | A = VALUE[0] | |
507 | A = A CODE[1] VALUE[1] | |
508 | A = A CODE[2] VALUE[2] | |
509 | ... | |
510 | ||
511 | where A is an accumulator, each CODE[i] is a binary rtl operation | |
65239d20 | 512 | and each VALUE[i] is a constant integer. CODE[0] is undefined. */ |
b259a9a6 RS |
513 | struct mips_integer_op { |
514 | enum rtx_code code; | |
515 | unsigned HOST_WIDE_INT value; | |
516 | }; | |
517 | ||
b259a9a6 RS |
518 | /* The largest number of operations needed to load an integer constant. |
519 | The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. | |
520 | When the lowest bit is clear, we can try, but reject a sequence with | |
521 | an extra SLL at the end. */ | |
522 | #define MIPS_MAX_INTEGER_OPS 7 | |
523 | ||
e1260576 RS |
524 | /* Information about a MIPS16e SAVE or RESTORE instruction. */ |
525 | struct mips16e_save_restore_info { | |
526 | /* The number of argument registers saved by a SAVE instruction. | |
527 | 0 for RESTORE instructions. */ | |
528 | unsigned int nargs; | |
529 | ||
530 | /* Bit X is set if the instruction saves or restores GPR X. */ | |
531 | unsigned int mask; | |
532 | ||
533 | /* The total number of bytes to allocate. */ | |
534 | HOST_WIDE_INT size; | |
535 | }; | |
b259a9a6 | 536 | |
faa832a7 AS |
537 | /* Costs of various operations on the different architectures. */ |
538 | ||
539 | struct mips_rtx_cost_data | |
540 | { | |
541 | unsigned short fp_add; | |
542 | unsigned short fp_mult_sf; | |
543 | unsigned short fp_mult_df; | |
544 | unsigned short fp_div_sf; | |
545 | unsigned short fp_div_df; | |
546 | unsigned short int_mult_si; | |
547 | unsigned short int_mult_di; | |
548 | unsigned short int_div_si; | |
549 | unsigned short int_div_di; | |
550 | unsigned short branch_cost; | |
551 | unsigned short memory_latency; | |
552 | }; | |
553 | ||
cee98a59 MM |
554 | /* Global variables for machine-dependent things. */ |
555 | ||
65239d20 RS |
556 | /* The -G setting, or the configuration's default small-data limit if |
557 | no -G option is given. */ | |
558 | static unsigned int mips_small_data_threshold; | |
cee98a59 | 559 | |
65239d20 RS |
560 | /* The number of file directives written by mips_output_filename. */ |
561 | int num_source_filenames; | |
cee98a59 | 562 | |
65239d20 RS |
563 | /* The name that appeared in the last .file directive written by |
564 | mips_output_filename, or "" if mips_output_filename hasn't | |
565 | written anything yet. */ | |
ab77a036 RS |
566 | const char *current_function_file = ""; |
567 | ||
65239d20 | 568 | /* Arrays that map GCC register numbers to debugger register numbers. */ |
ab77a036 RS |
569 | int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; |
570 | int mips_dwarf_regno[FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 571 | |
3bd0817d RS |
572 | /* Information about the current function's epilogue, used only while |
573 | expanding it. */ | |
574 | static struct { | |
575 | /* A list of queued REG_CFA_RESTORE notes. */ | |
576 | rtx cfa_restores; | |
577 | ||
578 | /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */ | |
579 | rtx cfa_reg; | |
580 | HOST_WIDE_INT cfa_offset; | |
581 | ||
582 | /* The offset of the CFA from the stack pointer while restoring | |
583 | registers. */ | |
584 | HOST_WIDE_INT cfa_restore_sp_offset; | |
585 | } mips_epilogue; | |
586 | ||
65239d20 | 587 | /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */ |
cf5fb4b0 RS |
588 | struct mips_asm_switch mips_noreorder = { "reorder", 0 }; |
589 | struct mips_asm_switch mips_nomacro = { "macro", 0 }; | |
590 | struct mips_asm_switch mips_noat = { "at", 0 }; | |
cee98a59 | 591 | |
65239d20 RS |
592 | /* True if we're writing out a branch-likely instruction rather than a |
593 | normal branch. */ | |
594 | static bool mips_branch_likely; | |
cee98a59 | 595 | |
65239d20 | 596 | /* The current instruction-set architecture. */ |
24609606 | 597 | enum processor mips_arch; |
a27fb29b | 598 | const struct mips_cpu_info *mips_arch_info; |
7dac2f89 | 599 | |
65239d20 | 600 | /* The processor that we should tune the code for. */ |
24609606 | 601 | enum processor mips_tune; |
a27fb29b | 602 | const struct mips_cpu_info *mips_tune_info; |
7dac2f89 | 603 | |
65239d20 | 604 | /* The ISA level associated with mips_arch. */ |
cee98a59 MM |
605 | int mips_isa; |
606 | ||
ad782bc9 RS |
607 | /* The ISA revision level. This is 0 for MIPS I to V and N for |
608 | MIPS{32,64}rN. */ | |
609 | int mips_isa_rev; | |
610 | ||
65239d20 RS |
611 | /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */ |
612 | static const struct mips_cpu_info *mips_isa_option_info; | |
ab77a036 | 613 | |
65239d20 | 614 | /* Which cost information to use. */ |
faa832a7 | 615 | static const struct mips_rtx_cost_data *mips_cost; |
c1bd2d66 | 616 | |
65239d20 | 617 | /* The ambient target flags, excluding MASK_MIPS16. */ |
f9e4a411 | 618 | static int mips_base_target_flags; |
65239d20 | 619 | |
22c4c869 CM |
620 | /* The default compression mode. */ |
621 | unsigned int mips_base_compression_flags; | |
65239d20 RS |
622 | |
623 | /* The ambient values of other global variables. */ | |
f9e4a411 SL |
624 | static int mips_base_schedule_insns; /* flag_schedule_insns */ |
625 | static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */ | |
8d1d0dee | 626 | static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */ |
f9e4a411 SL |
627 | static int mips_base_align_loops; /* align_loops */ |
628 | static int mips_base_align_jumps; /* align_jumps */ | |
629 | static int mips_base_align_functions; /* align_functions */ | |
f9e4a411 | 630 | |
65239d20 RS |
631 | /* Index [M][R] is true if register R is allowed to hold a value of mode M. */ |
632 | bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 633 | |
65239d20 RS |
634 | /* Index C is true if character C is a valid PRINT_OPERAND punctation |
635 | character. */ | |
6e9e0126 | 636 | static bool mips_print_operand_punct[256]; |
cee98a59 | 637 | |
cafe096b EC |
638 | static GTY (()) int mips_output_filename_first_time = 1; |
639 | ||
108b61d5 | 640 | /* mips_split_p[X] is true if symbols of type X can be split by |
65239d20 | 641 | mips_split_symbol. */ |
ea462dd0 | 642 | bool mips_split_p[NUM_SYMBOL_TYPES]; |
108b61d5 | 643 | |
08d0963a RS |
644 | /* mips_split_hi_p[X] is true if the high parts of symbols of type X |
645 | can be split by mips_split_symbol. */ | |
646 | bool mips_split_hi_p[NUM_SYMBOL_TYPES]; | |
647 | ||
ddaf8125 RS |
648 | /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be |
649 | forced into a PC-relative constant pool. */ | |
650 | bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES]; | |
651 | ||
108b61d5 RS |
652 | /* mips_lo_relocs[X] is the relocation to use when a symbol of type X |
653 | appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or | |
654 | if they are matched by a special .md file pattern. */ | |
ddaf8125 | 655 | const char *mips_lo_relocs[NUM_SYMBOL_TYPES]; |
108b61d5 RS |
656 | |
657 | /* Likewise for HIGHs. */ | |
ddaf8125 | 658 | const char *mips_hi_relocs[NUM_SYMBOL_TYPES]; |
108b61d5 | 659 | |
5aa62249 RS |
660 | /* Target state for MIPS16. */ |
661 | struct target_globals *mips16_globals; | |
662 | ||
646e6f41 JZ |
663 | /* Cached value of can_issue_more. This is cached in mips_variable_issue hook |
664 | and returned from mips_sched_reorder2. */ | |
665 | static int cached_can_issue_more; | |
666 | ||
a90c0245 | 667 | /* The stubs for various MIPS16 support functions, if used. */ |
6d51cc90 | 668 | static mips_one_only_stub *mips16_rdhwr_stub; |
a90c0245 RS |
669 | static mips_one_only_stub *mips16_get_fcsr_stub; |
670 | static mips_one_only_stub *mips16_set_fcsr_stub; | |
78c27266 | 671 | |
65239d20 RS |
672 | /* Index R is the smallest register class that contains register R. */ |
673 | const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { | |
5e7d8b4c RS |
674 | LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG, |
675 | M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, | |
676 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
677 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
678 | M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS, | |
679 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
680 | T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, | |
a78cc314 | 681 | LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS, |
5e7d8b4c | 682 | |
cee98a59 MM |
683 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
684 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
685 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
686 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
687 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
688 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
689 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
690 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
48156a39 | 691 | MD0_REG, MD1_REG, NO_REGS, ST_REGS, |
b8eb88d0 | 692 | ST_REGS, ST_REGS, ST_REGS, ST_REGS, |
cafe096b | 693 | ST_REGS, ST_REGS, ST_REGS, NO_REGS, |
7314c7dd | 694 | NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS, |
d604bca3 MH |
695 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, |
696 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
697 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
698 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
699 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
700 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
701 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
702 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
703 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
704 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
705 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
706 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
707 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
708 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
709 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
710 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
711 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
712 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
713 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
714 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
715 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
716 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
717 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
118ea793 CF |
718 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, |
719 | DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, | |
720 | DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS, | |
721 | ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS | |
cee98a59 MM |
722 | }; |
723 | ||
65239d20 | 724 | /* The value of TARGET_ATTRIBUTE_TABLE. */ |
6bc7bc14 | 725 | static const struct attribute_spec mips_attribute_table[] = { |
62d784f7 KT |
726 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
727 | om_diagnostic } */ | |
728 | { "long_call", 0, 0, false, true, true, NULL, false }, | |
729 | { "far", 0, 0, false, true, true, NULL, false }, | |
730 | { "near", 0, 0, false, true, true, NULL, false }, | |
65239d20 RS |
731 | /* We would really like to treat "mips16" and "nomips16" as type |
732 | attributes, but GCC doesn't provide the hooks we need to support | |
733 | the right conversion rules. As declaration attributes, they affect | |
734 | code generation but don't carry other semantics. */ | |
62d784f7 KT |
735 | { "mips16", 0, 0, true, false, false, NULL, false }, |
736 | { "nomips16", 0, 0, true, false, false, NULL, false }, | |
22c4c869 CM |
737 | { "micromips", 0, 0, true, false, false, NULL, false }, |
738 | { "nomicromips", 0, 0, true, false, false, NULL, false }, | |
739 | { "nocompression", 0, 0, true, false, false, NULL, false }, | |
e19da24c | 740 | /* Allow functions to be specified as interrupt handlers */ |
62d784f7 KT |
741 | { "interrupt", 0, 0, false, true, true, NULL, false }, |
742 | { "use_shadow_register_set", 0, 0, false, true, true, NULL, false }, | |
743 | { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false }, | |
744 | { "use_debug_exception_return", 0, 0, false, true, true, NULL, false }, | |
745 | { NULL, 0, 0, false, false, false, NULL, false } | |
4dbdb061 | 746 | }; |
672a6f42 | 747 | \f |
d371df6f JM |
748 | /* A table describing all the processors GCC knows about; see |
749 | mips-cpus.def for details. */ | |
65239d20 | 750 | static const struct mips_cpu_info mips_cpu_info_table[] = { |
d371df6f JM |
751 | #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \ |
752 | { NAME, CPU, ISA, FLAGS }, | |
753 | #include "mips-cpus.def" | |
754 | #undef MIPS_CPU | |
a27fb29b | 755 | }; |
c1bd2d66 | 756 | |
65239d20 | 757 | /* Default costs. If these are used for a processor we should look |
ff5c4582 | 758 | up the actual costs. */ |
c1bd2d66 EC |
759 | #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ |
760 | COSTS_N_INSNS (7), /* fp_mult_sf */ \ | |
761 | COSTS_N_INSNS (8), /* fp_mult_df */ \ | |
762 | COSTS_N_INSNS (23), /* fp_div_sf */ \ | |
763 | COSTS_N_INSNS (36), /* fp_div_df */ \ | |
764 | COSTS_N_INSNS (10), /* int_mult_si */ \ | |
765 | COSTS_N_INSNS (10), /* int_mult_di */ \ | |
766 | COSTS_N_INSNS (69), /* int_div_si */ \ | |
767 | COSTS_N_INSNS (69), /* int_div_di */ \ | |
768 | 2, /* branch_cost */ \ | |
769 | 4 /* memory_latency */ | |
770 | ||
65239d20 RS |
771 | /* Floating-point costs for processors without an FPU. Just assume that |
772 | all floating-point libcalls are very expensive. */ | |
c1bd2d66 EC |
773 | #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ |
774 | COSTS_N_INSNS (256), /* fp_mult_sf */ \ | |
775 | COSTS_N_INSNS (256), /* fp_mult_df */ \ | |
776 | COSTS_N_INSNS (256), /* fp_div_sf */ \ | |
777 | COSTS_N_INSNS (256) /* fp_div_df */ | |
778 | ||
65239d20 RS |
779 | /* Costs to use when optimizing for size. */ |
780 | static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { | |
781 | COSTS_N_INSNS (1), /* fp_add */ | |
782 | COSTS_N_INSNS (1), /* fp_mult_sf */ | |
783 | COSTS_N_INSNS (1), /* fp_mult_df */ | |
784 | COSTS_N_INSNS (1), /* fp_div_sf */ | |
785 | COSTS_N_INSNS (1), /* fp_div_df */ | |
786 | COSTS_N_INSNS (1), /* int_mult_si */ | |
787 | COSTS_N_INSNS (1), /* int_mult_di */ | |
788 | COSTS_N_INSNS (1), /* int_div_si */ | |
789 | COSTS_N_INSNS (1), /* int_div_di */ | |
790 | 2, /* branch_cost */ | |
791 | 4 /* memory_latency */ | |
792 | }; | |
793 | ||
794 | /* Costs to use when optimizing for speed, indexed by processor. */ | |
24609606 RS |
795 | static const struct mips_rtx_cost_data |
796 | mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = { | |
65239d20 RS |
797 | { /* R3000 */ |
798 | COSTS_N_INSNS (2), /* fp_add */ | |
799 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
800 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
801 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
802 | COSTS_N_INSNS (19), /* fp_div_df */ | |
803 | COSTS_N_INSNS (12), /* int_mult_si */ | |
804 | COSTS_N_INSNS (12), /* int_mult_di */ | |
805 | COSTS_N_INSNS (35), /* int_div_si */ | |
806 | COSTS_N_INSNS (35), /* int_div_di */ | |
807 | 1, /* branch_cost */ | |
808 | 4 /* memory_latency */ | |
809 | }, | |
810 | { /* 4KC */ | |
811 | SOFT_FP_COSTS, | |
812 | COSTS_N_INSNS (6), /* int_mult_si */ | |
813 | COSTS_N_INSNS (6), /* int_mult_di */ | |
814 | COSTS_N_INSNS (36), /* int_div_si */ | |
815 | COSTS_N_INSNS (36), /* int_div_di */ | |
816 | 1, /* branch_cost */ | |
817 | 4 /* memory_latency */ | |
818 | }, | |
819 | { /* 4KP */ | |
820 | SOFT_FP_COSTS, | |
821 | COSTS_N_INSNS (36), /* int_mult_si */ | |
822 | COSTS_N_INSNS (36), /* int_mult_di */ | |
823 | COSTS_N_INSNS (37), /* int_div_si */ | |
824 | COSTS_N_INSNS (37), /* int_div_di */ | |
825 | 1, /* branch_cost */ | |
826 | 4 /* memory_latency */ | |
827 | }, | |
828 | { /* 5KC */ | |
829 | SOFT_FP_COSTS, | |
830 | COSTS_N_INSNS (4), /* int_mult_si */ | |
831 | COSTS_N_INSNS (11), /* int_mult_di */ | |
832 | COSTS_N_INSNS (36), /* int_div_si */ | |
833 | COSTS_N_INSNS (68), /* int_div_di */ | |
834 | 1, /* branch_cost */ | |
835 | 4 /* memory_latency */ | |
836 | }, | |
837 | { /* 5KF */ | |
838 | COSTS_N_INSNS (4), /* fp_add */ | |
839 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
840 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
841 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
842 | COSTS_N_INSNS (32), /* fp_div_df */ | |
843 | COSTS_N_INSNS (4), /* int_mult_si */ | |
844 | COSTS_N_INSNS (11), /* int_mult_di */ | |
845 | COSTS_N_INSNS (36), /* int_div_si */ | |
846 | COSTS_N_INSNS (68), /* int_div_di */ | |
847 | 1, /* branch_cost */ | |
848 | 4 /* memory_latency */ | |
849 | }, | |
850 | { /* 20KC */ | |
851 | COSTS_N_INSNS (4), /* fp_add */ | |
852 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
853 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
854 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
855 | COSTS_N_INSNS (32), /* fp_div_df */ | |
856 | COSTS_N_INSNS (4), /* int_mult_si */ | |
857 | COSTS_N_INSNS (7), /* int_mult_di */ | |
858 | COSTS_N_INSNS (42), /* int_div_si */ | |
859 | COSTS_N_INSNS (72), /* int_div_di */ | |
860 | 1, /* branch_cost */ | |
861 | 4 /* memory_latency */ | |
862 | }, | |
863 | { /* 24KC */ | |
864 | SOFT_FP_COSTS, | |
865 | COSTS_N_INSNS (5), /* int_mult_si */ | |
866 | COSTS_N_INSNS (5), /* int_mult_di */ | |
867 | COSTS_N_INSNS (41), /* int_div_si */ | |
868 | COSTS_N_INSNS (41), /* int_div_di */ | |
869 | 1, /* branch_cost */ | |
870 | 4 /* memory_latency */ | |
871 | }, | |
872 | { /* 24KF2_1 */ | |
873 | COSTS_N_INSNS (8), /* fp_add */ | |
874 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
875 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
876 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
877 | COSTS_N_INSNS (64), /* fp_div_df */ | |
878 | COSTS_N_INSNS (5), /* int_mult_si */ | |
879 | COSTS_N_INSNS (5), /* int_mult_di */ | |
880 | COSTS_N_INSNS (41), /* int_div_si */ | |
881 | COSTS_N_INSNS (41), /* int_div_di */ | |
882 | 1, /* branch_cost */ | |
883 | 4 /* memory_latency */ | |
884 | }, | |
885 | { /* 24KF1_1 */ | |
886 | COSTS_N_INSNS (4), /* fp_add */ | |
887 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
888 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
889 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
890 | COSTS_N_INSNS (32), /* fp_div_df */ | |
891 | COSTS_N_INSNS (5), /* int_mult_si */ | |
892 | COSTS_N_INSNS (5), /* int_mult_di */ | |
893 | COSTS_N_INSNS (41), /* int_div_si */ | |
894 | COSTS_N_INSNS (41), /* int_div_di */ | |
895 | 1, /* branch_cost */ | |
896 | 4 /* memory_latency */ | |
897 | }, | |
898 | { /* 74KC */ | |
899 | SOFT_FP_COSTS, | |
900 | COSTS_N_INSNS (5), /* int_mult_si */ | |
901 | COSTS_N_INSNS (5), /* int_mult_di */ | |
902 | COSTS_N_INSNS (41), /* int_div_si */ | |
903 | COSTS_N_INSNS (41), /* int_div_di */ | |
904 | 1, /* branch_cost */ | |
905 | 4 /* memory_latency */ | |
906 | }, | |
907 | { /* 74KF2_1 */ | |
908 | COSTS_N_INSNS (8), /* fp_add */ | |
909 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
910 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
911 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
912 | COSTS_N_INSNS (64), /* fp_div_df */ | |
913 | COSTS_N_INSNS (5), /* int_mult_si */ | |
914 | COSTS_N_INSNS (5), /* int_mult_di */ | |
915 | COSTS_N_INSNS (41), /* int_div_si */ | |
916 | COSTS_N_INSNS (41), /* int_div_di */ | |
917 | 1, /* branch_cost */ | |
918 | 4 /* memory_latency */ | |
919 | }, | |
920 | { /* 74KF1_1 */ | |
921 | COSTS_N_INSNS (4), /* fp_add */ | |
922 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
923 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
924 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
925 | COSTS_N_INSNS (32), /* fp_div_df */ | |
926 | COSTS_N_INSNS (5), /* int_mult_si */ | |
927 | COSTS_N_INSNS (5), /* int_mult_di */ | |
928 | COSTS_N_INSNS (41), /* int_div_si */ | |
929 | COSTS_N_INSNS (41), /* int_div_di */ | |
930 | 1, /* branch_cost */ | |
931 | 4 /* memory_latency */ | |
932 | }, | |
933 | { /* 74KF3_2 */ | |
934 | COSTS_N_INSNS (6), /* fp_add */ | |
935 | COSTS_N_INSNS (6), /* fp_mult_sf */ | |
936 | COSTS_N_INSNS (7), /* fp_mult_df */ | |
937 | COSTS_N_INSNS (25), /* fp_div_sf */ | |
938 | COSTS_N_INSNS (48), /* fp_div_df */ | |
939 | COSTS_N_INSNS (5), /* int_mult_si */ | |
940 | COSTS_N_INSNS (5), /* int_mult_di */ | |
941 | COSTS_N_INSNS (41), /* int_div_si */ | |
942 | COSTS_N_INSNS (41), /* int_div_di */ | |
943 | 1, /* branch_cost */ | |
944 | 4 /* memory_latency */ | |
945 | }, | |
33db2060 MS |
946 | { /* Loongson-2E */ |
947 | DEFAULT_COSTS | |
948 | }, | |
949 | { /* Loongson-2F */ | |
950 | DEFAULT_COSTS | |
951 | }, | |
98824c6f MS |
952 | { /* Loongson-3A */ |
953 | DEFAULT_COSTS | |
954 | }, | |
65239d20 RS |
955 | { /* M4k */ |
956 | DEFAULT_COSTS | |
d97e6aca AN |
957 | }, |
958 | /* Octeon */ | |
959 | { | |
960 | SOFT_FP_COSTS, | |
961 | COSTS_N_INSNS (5), /* int_mult_si */ | |
962 | COSTS_N_INSNS (5), /* int_mult_di */ | |
963 | COSTS_N_INSNS (72), /* int_div_si */ | |
964 | COSTS_N_INSNS (72), /* int_div_di */ | |
965 | 1, /* branch_cost */ | |
966 | 4 /* memory_latency */ | |
38a53a0e AP |
967 | }, |
968 | /* Octeon II */ | |
969 | { | |
970 | SOFT_FP_COSTS, | |
971 | COSTS_N_INSNS (6), /* int_mult_si */ | |
972 | COSTS_N_INSNS (6), /* int_mult_di */ | |
973 | COSTS_N_INSNS (18), /* int_div_si */ | |
974 | COSTS_N_INSNS (35), /* int_div_di */ | |
975 | 4, /* branch_cost */ | |
976 | 4 /* memory_latency */ | |
65239d20 RS |
977 | }, |
978 | { /* R3900 */ | |
979 | COSTS_N_INSNS (2), /* fp_add */ | |
980 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
981 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
982 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
983 | COSTS_N_INSNS (19), /* fp_div_df */ | |
984 | COSTS_N_INSNS (2), /* int_mult_si */ | |
985 | COSTS_N_INSNS (2), /* int_mult_di */ | |
986 | COSTS_N_INSNS (35), /* int_div_si */ | |
987 | COSTS_N_INSNS (35), /* int_div_di */ | |
988 | 1, /* branch_cost */ | |
989 | 4 /* memory_latency */ | |
990 | }, | |
991 | { /* R6000 */ | |
992 | COSTS_N_INSNS (3), /* fp_add */ | |
993 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
994 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
995 | COSTS_N_INSNS (15), /* fp_div_sf */ | |
996 | COSTS_N_INSNS (16), /* fp_div_df */ | |
997 | COSTS_N_INSNS (17), /* int_mult_si */ | |
998 | COSTS_N_INSNS (17), /* int_mult_di */ | |
999 | COSTS_N_INSNS (38), /* int_div_si */ | |
1000 | COSTS_N_INSNS (38), /* int_div_di */ | |
1001 | 2, /* branch_cost */ | |
1002 | 6 /* memory_latency */ | |
1003 | }, | |
1004 | { /* R4000 */ | |
1005 | COSTS_N_INSNS (6), /* fp_add */ | |
1006 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1007 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1008 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1009 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1010 | COSTS_N_INSNS (10), /* int_mult_si */ | |
1011 | COSTS_N_INSNS (10), /* int_mult_di */ | |
1012 | COSTS_N_INSNS (69), /* int_div_si */ | |
1013 | COSTS_N_INSNS (69), /* int_div_di */ | |
1014 | 2, /* branch_cost */ | |
1015 | 6 /* memory_latency */ | |
1016 | }, | |
1017 | { /* R4100 */ | |
1018 | DEFAULT_COSTS | |
1019 | }, | |
1020 | { /* R4111 */ | |
1021 | DEFAULT_COSTS | |
1022 | }, | |
1023 | { /* R4120 */ | |
1024 | DEFAULT_COSTS | |
1025 | }, | |
1026 | { /* R4130 */ | |
1027 | /* The only costs that appear to be updated here are | |
1028 | integer multiplication. */ | |
1029 | SOFT_FP_COSTS, | |
1030 | COSTS_N_INSNS (4), /* int_mult_si */ | |
1031 | COSTS_N_INSNS (6), /* int_mult_di */ | |
1032 | COSTS_N_INSNS (69), /* int_div_si */ | |
1033 | COSTS_N_INSNS (69), /* int_div_di */ | |
1034 | 1, /* branch_cost */ | |
1035 | 4 /* memory_latency */ | |
1036 | }, | |
1037 | { /* R4300 */ | |
1038 | DEFAULT_COSTS | |
1039 | }, | |
1040 | { /* R4600 */ | |
1041 | DEFAULT_COSTS | |
1042 | }, | |
1043 | { /* R4650 */ | |
1044 | DEFAULT_COSTS | |
1045 | }, | |
d58e7d69 MT |
1046 | { /* R4700 */ |
1047 | DEFAULT_COSTS | |
1048 | }, | |
65239d20 RS |
1049 | { /* R5000 */ |
1050 | COSTS_N_INSNS (6), /* fp_add */ | |
1051 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1052 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
1053 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1054 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1055 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1056 | COSTS_N_INSNS (5), /* int_mult_di */ | |
1057 | COSTS_N_INSNS (36), /* int_div_si */ | |
1058 | COSTS_N_INSNS (36), /* int_div_di */ | |
1059 | 1, /* branch_cost */ | |
1060 | 4 /* memory_latency */ | |
1061 | }, | |
1062 | { /* R5400 */ | |
1063 | COSTS_N_INSNS (6), /* fp_add */ | |
1064 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
1065 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
1066 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
1067 | COSTS_N_INSNS (59), /* fp_div_df */ | |
1068 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1069 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1070 | COSTS_N_INSNS (42), /* int_div_si */ | |
1071 | COSTS_N_INSNS (74), /* int_div_di */ | |
1072 | 1, /* branch_cost */ | |
1073 | 4 /* memory_latency */ | |
1074 | }, | |
1075 | { /* R5500 */ | |
1076 | COSTS_N_INSNS (6), /* fp_add */ | |
1077 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
1078 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
1079 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
1080 | COSTS_N_INSNS (59), /* fp_div_df */ | |
1081 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1082 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1083 | COSTS_N_INSNS (42), /* int_div_si */ | |
1084 | COSTS_N_INSNS (74), /* int_div_di */ | |
1085 | 1, /* branch_cost */ | |
1086 | 4 /* memory_latency */ | |
1087 | }, | |
107eea2c JU |
1088 | { /* R5900 */ |
1089 | COSTS_N_INSNS (4), /* fp_add */ | |
1090 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1091 | COSTS_N_INSNS (256), /* fp_mult_df */ | |
1092 | COSTS_N_INSNS (8), /* fp_div_sf */ | |
1093 | COSTS_N_INSNS (256), /* fp_div_df */ | |
1094 | COSTS_N_INSNS (4), /* int_mult_si */ | |
1095 | COSTS_N_INSNS (256), /* int_mult_di */ | |
1096 | COSTS_N_INSNS (37), /* int_div_si */ | |
1097 | COSTS_N_INSNS (256), /* int_div_di */ | |
1098 | 1, /* branch_cost */ | |
1099 | 4 /* memory_latency */ | |
1100 | }, | |
65239d20 RS |
1101 | { /* R7000 */ |
1102 | /* The only costs that are changed here are | |
1103 | integer multiplication. */ | |
1104 | COSTS_N_INSNS (6), /* fp_add */ | |
1105 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1106 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1107 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1108 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1109 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1110 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1111 | COSTS_N_INSNS (69), /* int_div_si */ | |
1112 | COSTS_N_INSNS (69), /* int_div_di */ | |
1113 | 1, /* branch_cost */ | |
1114 | 4 /* memory_latency */ | |
1115 | }, | |
1116 | { /* R8000 */ | |
1117 | DEFAULT_COSTS | |
1118 | }, | |
1119 | { /* R9000 */ | |
1120 | /* The only costs that are changed here are | |
1121 | integer multiplication. */ | |
1122 | COSTS_N_INSNS (6), /* fp_add */ | |
1123 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1124 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1125 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1126 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1127 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1128 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1129 | COSTS_N_INSNS (69), /* int_div_si */ | |
1130 | COSTS_N_INSNS (69), /* int_div_di */ | |
1131 | 1, /* branch_cost */ | |
1132 | 4 /* memory_latency */ | |
1133 | }, | |
7a3446ec JK |
1134 | { /* R1x000 */ |
1135 | COSTS_N_INSNS (2), /* fp_add */ | |
1136 | COSTS_N_INSNS (2), /* fp_mult_sf */ | |
1137 | COSTS_N_INSNS (2), /* fp_mult_df */ | |
1138 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
1139 | COSTS_N_INSNS (19), /* fp_div_df */ | |
1140 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1141 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1142 | COSTS_N_INSNS (34), /* int_div_si */ | |
1143 | COSTS_N_INSNS (66), /* int_div_di */ | |
1144 | 1, /* branch_cost */ | |
1145 | 4 /* memory_latency */ | |
1146 | }, | |
65239d20 RS |
1147 | { /* SB1 */ |
1148 | /* These costs are the same as the SB-1A below. */ | |
1149 | COSTS_N_INSNS (4), /* fp_add */ | |
1150 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1151 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1152 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1153 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1154 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1155 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1156 | COSTS_N_INSNS (36), /* int_div_si */ | |
1157 | COSTS_N_INSNS (68), /* int_div_di */ | |
1158 | 1, /* branch_cost */ | |
1159 | 4 /* memory_latency */ | |
1160 | }, | |
1161 | { /* SB1-A */ | |
1162 | /* These costs are the same as the SB-1 above. */ | |
1163 | COSTS_N_INSNS (4), /* fp_add */ | |
1164 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1165 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1166 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1167 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1168 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1169 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1170 | COSTS_N_INSNS (36), /* int_div_si */ | |
1171 | COSTS_N_INSNS (68), /* int_div_di */ | |
1172 | 1, /* branch_cost */ | |
1173 | 4 /* memory_latency */ | |
1174 | }, | |
1175 | { /* SR71000 */ | |
1176 | DEFAULT_COSTS | |
1177 | }, | |
d0ae31b0 | 1178 | { /* XLR */ |
0051ef59 | 1179 | SOFT_FP_COSTS, |
d0ae31b0 SM |
1180 | COSTS_N_INSNS (8), /* int_mult_si */ |
1181 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1182 | COSTS_N_INSNS (72), /* int_div_si */ | |
1183 | COSTS_N_INSNS (72), /* int_div_di */ | |
1184 | 1, /* branch_cost */ | |
1185 | 4 /* memory_latency */ | |
3fd03b93 MK |
1186 | }, |
1187 | { /* XLP */ | |
1188 | /* These costs are the same as 5KF above. */ | |
1189 | COSTS_N_INSNS (4), /* fp_add */ | |
1190 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1191 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
1192 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
1193 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1194 | COSTS_N_INSNS (4), /* int_mult_si */ | |
1195 | COSTS_N_INSNS (11), /* int_mult_di */ | |
1196 | COSTS_N_INSNS (36), /* int_div_si */ | |
1197 | COSTS_N_INSNS (68), /* int_div_di */ | |
1198 | 1, /* branch_cost */ | |
1199 | 4 /* memory_latency */ | |
aaaa9efc JP |
1200 | }, |
1201 | { /* P5600 */ | |
1202 | COSTS_N_INSNS (4), /* fp_add */ | |
1203 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
1204 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
1205 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
1206 | COSTS_N_INSNS (17), /* fp_div_df */ | |
1207 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1208 | COSTS_N_INSNS (5), /* int_mult_di */ | |
1209 | COSTS_N_INSNS (8), /* int_div_si */ | |
1210 | COSTS_N_INSNS (8), /* int_div_di */ | |
1211 | 2, /* branch_cost */ | |
1212 | 10 /* memory_latency */ | |
d0ae31b0 | 1213 | } |
65239d20 | 1214 | }; |
a27fb29b | 1215 | \f |
c6f971f4 | 1216 | static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool); |
ef4bddc2 | 1217 | static int mips_register_move_cost (machine_mode, reg_class_t, |
faa832a7 | 1218 | reg_class_t); |
ef4bddc2 | 1219 | static unsigned int mips_function_arg_boundary (machine_mode, const_tree); |
b53da244 | 1220 | \f |
2a22f99c | 1221 | struct mips16_flip_traits : default_hashmap_traits |
ab77a036 | 1222 | { |
2a22f99c TS |
1223 | static hashval_t hash (const char *s) { return htab_hash_string (s); } |
1224 | static bool | |
1225 | equal_keys (const char *a, const char *b) | |
1226 | { | |
1227 | return !strcmp (a, b); | |
1228 | } | |
1229 | }; | |
912f2dac | 1230 | |
2a22f99c TS |
1231 | /* This hash table keeps track of implicit "mips16" and "nomips16" attributes |
1232 | for -mflip_mips16. It maps decl names onto a boolean mode setting. */ | |
1233 | static GTY (()) hash_map<const char *, bool, mips16_flip_traits> * | |
1234 | mflip_mips16_htab; | |
ea462dd0 | 1235 | |
65239d20 RS |
1236 | /* True if -mflip-mips16 should next add an attribute for the default MIPS16 |
1237 | mode, false if it should next add an attribute for the opposite mode. */ | |
1238 | static GTY(()) bool mips16_flipper; | |
cd3a59b3 | 1239 | |
ab77a036 RS |
1240 | /* DECL is a function that needs a default "mips16" or "nomips16" attribute |
1241 | for -mflip-mips16. Return true if it should use "mips16" and false if | |
1242 | it should use "nomips16". */ | |
a44380d2 | 1243 | |
ab77a036 RS |
1244 | static bool |
1245 | mflip_mips16_use_mips16_p (tree decl) | |
1246 | { | |
ab77a036 | 1247 | const char *name; |
22c4c869 | 1248 | bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0; |
076a5ce6 | 1249 | |
ab77a036 RS |
1250 | /* Use the opposite of the command-line setting for anonymous decls. */ |
1251 | if (!DECL_NAME (decl)) | |
22c4c869 | 1252 | return !base_is_mips16; |
cd3a59b3 | 1253 | |
ab77a036 | 1254 | if (!mflip_mips16_htab) |
2a22f99c TS |
1255 | mflip_mips16_htab |
1256 | = hash_map<const char *, bool, mips16_flip_traits>::create_ggc (37); | |
cd3a59b3 | 1257 | |
ab77a036 | 1258 | name = IDENTIFIER_POINTER (DECL_NAME (decl)); |
2a22f99c TS |
1259 | |
1260 | bool existed; | |
1261 | bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed); | |
1262 | if (!existed) | |
ab77a036 RS |
1263 | { |
1264 | mips16_flipper = !mips16_flipper; | |
2a22f99c | 1265 | *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16; |
ab77a036 | 1266 | } |
2a22f99c | 1267 | return *slot; |
ab77a036 RS |
1268 | } |
1269 | \f | |
cd3a59b3 SL |
1270 | /* Predicates to test for presence of "near" and "far"/"long_call" |
1271 | attributes on the given TYPE. */ | |
1272 | ||
1273 | static bool | |
3101faab | 1274 | mips_near_type_p (const_tree type) |
cd3a59b3 SL |
1275 | { |
1276 | return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; | |
1277 | } | |
1278 | ||
1279 | static bool | |
3101faab | 1280 | mips_far_type_p (const_tree type) |
cd3a59b3 SL |
1281 | { |
1282 | return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL | |
1283 | || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); | |
1284 | } | |
1285 | ||
1286 | ||
e19da24c CF |
1287 | /* Check if the interrupt attribute is set for a function. */ |
1288 | ||
1289 | static bool | |
1290 | mips_interrupt_type_p (tree type) | |
1291 | { | |
1292 | return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; | |
1293 | } | |
1294 | ||
1295 | /* Check if the attribute to use shadow register set is set for a function. */ | |
1296 | ||
1297 | static bool | |
1298 | mips_use_shadow_register_set_p (tree type) | |
1299 | { | |
1300 | return lookup_attribute ("use_shadow_register_set", | |
1301 | TYPE_ATTRIBUTES (type)) != NULL; | |
1302 | } | |
1303 | ||
1304 | /* Check if the attribute to keep interrupts masked is set for a function. */ | |
1305 | ||
1306 | static bool | |
1307 | mips_keep_interrupts_masked_p (tree type) | |
1308 | { | |
1309 | return lookup_attribute ("keep_interrupts_masked", | |
1310 | TYPE_ATTRIBUTES (type)) != NULL; | |
1311 | } | |
1312 | ||
1313 | /* Check if the attribute to use debug exception return is set for | |
1314 | a function. */ | |
1315 | ||
1316 | static bool | |
1317 | mips_use_debug_exception_return_p (tree type) | |
1318 | { | |
1319 | return lookup_attribute ("use_debug_exception_return", | |
1320 | TYPE_ATTRIBUTES (type)) != NULL; | |
1321 | } | |
1322 | ||
22c4c869 CM |
1323 | /* Return the set of compression modes that are explicitly required |
1324 | by the attributes in ATTRIBUTES. */ | |
6941b508 | 1325 | |
22c4c869 CM |
1326 | static unsigned int |
1327 | mips_get_compress_on_flags (tree attributes) | |
1328 | { | |
1329 | unsigned int flags = 0; | |
1330 | ||
1331 | if (lookup_attribute ("mips16", attributes) != NULL) | |
1332 | flags |= MASK_MIPS16; | |
1333 | ||
1334 | if (lookup_attribute ("micromips", attributes) != NULL) | |
1335 | flags |= MASK_MICROMIPS; | |
1336 | ||
1337 | return flags; | |
1338 | } | |
1339 | ||
1340 | /* Return the set of compression modes that are explicitly forbidden | |
1341 | by the attributes in ATTRIBUTES. */ | |
1342 | ||
1343 | static unsigned int | |
1344 | mips_get_compress_off_flags (tree attributes) | |
6941b508 | 1345 | { |
22c4c869 CM |
1346 | unsigned int flags = 0; |
1347 | ||
1348 | if (lookup_attribute ("nocompression", attributes) != NULL) | |
1349 | flags |= MASK_MIPS16 | MASK_MICROMIPS; | |
1350 | ||
1351 | if (lookup_attribute ("nomips16", attributes) != NULL) | |
1352 | flags |= MASK_MIPS16; | |
1353 | ||
1354 | if (lookup_attribute ("nomicromips", attributes) != NULL) | |
1355 | flags |= MASK_MICROMIPS; | |
1356 | ||
1357 | return flags; | |
1358 | } | |
1359 | ||
1360 | /* Return the compression mode that should be used for function DECL. | |
1361 | Return the ambient setting if DECL is null. */ | |
1362 | ||
1363 | static unsigned int | |
1364 | mips_get_compress_mode (tree decl) | |
1365 | { | |
1366 | unsigned int flags, force_on; | |
1367 | ||
1368 | flags = mips_base_compression_flags; | |
ab77a036 RS |
1369 | if (decl) |
1370 | { | |
1371 | /* Nested functions must use the same frame pointer as their | |
1372 | parent and must therefore use the same ISA mode. */ | |
1373 | tree parent = decl_function_context (decl); | |
1374 | if (parent) | |
1375 | decl = parent; | |
22c4c869 CM |
1376 | force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)); |
1377 | if (force_on) | |
1378 | return force_on; | |
1379 | flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)); | |
ab77a036 | 1380 | } |
22c4c869 CM |
1381 | return flags; |
1382 | } | |
1383 | ||
1384 | /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS | |
1385 | flags FLAGS. */ | |
1386 | ||
1387 | static const char * | |
1388 | mips_get_compress_on_name (unsigned int flags) | |
1389 | { | |
1390 | if (flags == MASK_MIPS16) | |
1391 | return "mips16"; | |
1392 | return "micromips"; | |
1393 | } | |
1394 | ||
1395 | /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS | |
1396 | flags FLAGS. */ | |
1397 | ||
1398 | static const char * | |
1399 | mips_get_compress_off_name (unsigned int flags) | |
1400 | { | |
1401 | if (flags == MASK_MIPS16) | |
1402 | return "nomips16"; | |
1403 | if (flags == MASK_MICROMIPS) | |
1404 | return "nomicromips"; | |
1405 | return "nocompression"; | |
ab77a036 RS |
1406 | } |
1407 | ||
65239d20 | 1408 | /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ |
ab77a036 RS |
1409 | |
1410 | static int | |
1411 | mips_comp_type_attributes (const_tree type1, const_tree type2) | |
1412 | { | |
cd3a59b3 SL |
1413 | /* Disallow mixed near/far attributes. */ |
1414 | if (mips_far_type_p (type1) && mips_near_type_p (type2)) | |
1415 | return 0; | |
1416 | if (mips_near_type_p (type1) && mips_far_type_p (type2)) | |
1417 | return 0; | |
cd3a59b3 SL |
1418 | return 1; |
1419 | } | |
ab77a036 RS |
1420 | |
1421 | /* Implement TARGET_INSERT_ATTRIBUTES. */ | |
1422 | ||
1423 | static void | |
1424 | mips_insert_attributes (tree decl, tree *attributes) | |
1425 | { | |
1426 | const char *name; | |
22c4c869 | 1427 | unsigned int compression_flags, nocompression_flags; |
ab77a036 RS |
1428 | |
1429 | /* Check for "mips16" and "nomips16" attributes. */ | |
22c4c869 CM |
1430 | compression_flags = mips_get_compress_on_flags (*attributes); |
1431 | nocompression_flags = mips_get_compress_off_flags (*attributes); | |
1432 | ||
ab77a036 RS |
1433 | if (TREE_CODE (decl) != FUNCTION_DECL) |
1434 | { | |
22c4c869 CM |
1435 | if (nocompression_flags) |
1436 | error ("%qs attribute only applies to functions", | |
1437 | mips_get_compress_off_name (nocompression_flags)); | |
1438 | ||
1439 | if (compression_flags) | |
1440 | error ("%qs attribute only applies to functions", | |
1441 | mips_get_compress_on_name (nocompression_flags)); | |
ab77a036 RS |
1442 | } |
1443 | else | |
1444 | { | |
22c4c869 CM |
1445 | compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)); |
1446 | nocompression_flags |= | |
1447 | mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)); | |
1448 | ||
1449 | if (compression_flags && nocompression_flags) | |
1450 | error ("%qE cannot have both %qs and %qs attributes", | |
1451 | DECL_NAME (decl), mips_get_compress_on_name (compression_flags), | |
1452 | mips_get_compress_off_name (nocompression_flags)); | |
1453 | ||
1454 | if (compression_flags & MASK_MIPS16 | |
1455 | && compression_flags & MASK_MICROMIPS) | |
1456 | error ("%qE cannot have both %qs and %qs attributes", | |
1457 | DECL_NAME (decl), "mips16", "micromips"); | |
1458 | ||
1459 | if (TARGET_FLIP_MIPS16 | |
1460 | && !DECL_ARTIFICIAL (decl) | |
1461 | && compression_flags == 0 | |
1462 | && nocompression_flags == 0) | |
ab77a036 RS |
1463 | { |
1464 | /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a | |
1465 | "mips16" attribute, arbitrarily pick one. We must pick the same | |
1466 | setting for duplicate declarations of a function. */ | |
1467 | name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16"; | |
1468 | *attributes = tree_cons (get_identifier (name), NULL, *attributes); | |
22c4c869 CM |
1469 | name = "nomicromips"; |
1470 | *attributes = tree_cons (get_identifier (name), NULL, *attributes); | |
ab77a036 RS |
1471 | } |
1472 | } | |
1473 | } | |
1474 | ||
1475 | /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ | |
1476 | ||
1477 | static tree | |
1478 | mips_merge_decl_attributes (tree olddecl, tree newdecl) | |
1479 | { | |
22c4c869 CM |
1480 | unsigned int diff; |
1481 | ||
1482 | diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl)) | |
1483 | ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl))); | |
1484 | if (diff) | |
29d08eba | 1485 | error ("%qE redeclared with conflicting %qs attributes", |
22c4c869 CM |
1486 | DECL_NAME (newdecl), mips_get_compress_on_name (diff)); |
1487 | ||
1488 | diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl)) | |
1489 | ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl))); | |
1490 | if (diff) | |
29d08eba | 1491 | error ("%qE redeclared with conflicting %qs attributes", |
22c4c869 | 1492 | DECL_NAME (newdecl), mips_get_compress_off_name (diff)); |
ab77a036 RS |
1493 | |
1494 | return merge_attributes (DECL_ATTRIBUTES (olddecl), | |
1495 | DECL_ATTRIBUTES (newdecl)); | |
1496 | } | |
c979d5f5 RS |
1497 | |
1498 | /* Implement TARGET_CAN_INLINE_P. */ | |
1499 | ||
1500 | static bool | |
1501 | mips_can_inline_p (tree caller, tree callee) | |
1502 | { | |
1503 | if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller)) | |
1504 | return false; | |
1505 | return default_target_can_inline_p (caller, callee); | |
1506 | } | |
cee98a59 | 1507 | \f |
e1260576 RS |
1508 | /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR |
1509 | and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */ | |
1510 | ||
1511 | static void | |
1512 | mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr) | |
1513 | { | |
47ac44d6 | 1514 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
e1260576 RS |
1515 | { |
1516 | *base_ptr = XEXP (x, 0); | |
1517 | *offset_ptr = INTVAL (XEXP (x, 1)); | |
1518 | } | |
1519 | else | |
1520 | { | |
1521 | *base_ptr = x; | |
1522 | *offset_ptr = 0; | |
1523 | } | |
1524 | } | |
1525 | \f | |
ab77a036 RS |
1526 | static unsigned int mips_build_integer (struct mips_integer_op *, |
1527 | unsigned HOST_WIDE_INT); | |
1528 | ||
65239d20 | 1529 | /* A subroutine of mips_build_integer, with the same interface. |
ab77a036 RS |
1530 | Assume that the final action in the sequence should be a left shift. */ |
1531 | ||
1532 | static unsigned int | |
1533 | mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value) | |
1534 | { | |
1535 | unsigned int i, shift; | |
1536 | ||
1537 | /* Shift VALUE right until its lowest bit is set. Shift arithmetically | |
1538 | since signed numbers are easier to load than unsigned ones. */ | |
1539 | shift = 0; | |
1540 | while ((value & 1) == 0) | |
1541 | value /= 2, shift++; | |
1542 | ||
1543 | i = mips_build_integer (codes, value); | |
1544 | codes[i].code = ASHIFT; | |
1545 | codes[i].value = shift; | |
1546 | return i + 1; | |
1547 | } | |
1548 | ||
ab77a036 RS |
1549 | /* As for mips_build_shift, but assume that the final action will be |
1550 | an IOR or PLUS operation. */ | |
1551 | ||
1552 | static unsigned int | |
1553 | mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) | |
1554 | { | |
1555 | unsigned HOST_WIDE_INT high; | |
1556 | unsigned int i; | |
1557 | ||
1558 | high = value & ~(unsigned HOST_WIDE_INT) 0xffff; | |
1559 | if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000) | |
1560 | { | |
65239d20 RS |
1561 | /* The constant is too complex to load with a simple LUI/ORI pair, |
1562 | so we want to give the recursive call as many trailing zeros as | |
1563 | possible. In this case, we know bit 16 is set and that the | |
1564 | low 16 bits form a negative number. If we subtract that number | |
1565 | from VALUE, we will clear at least the lowest 17 bits, maybe more. */ | |
ab77a036 RS |
1566 | i = mips_build_integer (codes, CONST_HIGH_PART (value)); |
1567 | codes[i].code = PLUS; | |
1568 | codes[i].value = CONST_LOW_PART (value); | |
1569 | } | |
1570 | else | |
1571 | { | |
65239d20 RS |
1572 | /* Either this is a simple LUI/ORI pair, or clearing the lowest 16 |
1573 | bits gives a value with at least 17 trailing zeros. */ | |
ab77a036 RS |
1574 | i = mips_build_integer (codes, high); |
1575 | codes[i].code = IOR; | |
1576 | codes[i].value = value & 0xffff; | |
1577 | } | |
1578 | return i + 1; | |
1579 | } | |
1580 | ||
ab77a036 RS |
1581 | /* Fill CODES with a sequence of rtl operations to load VALUE. |
1582 | Return the number of operations needed. */ | |
1583 | ||
1584 | static unsigned int | |
1585 | mips_build_integer (struct mips_integer_op *codes, | |
1586 | unsigned HOST_WIDE_INT value) | |
1587 | { | |
1588 | if (SMALL_OPERAND (value) | |
1589 | || SMALL_OPERAND_UNSIGNED (value) | |
1590 | || LUI_OPERAND (value)) | |
1591 | { | |
1592 | /* The value can be loaded with a single instruction. */ | |
1593 | codes[0].code = UNKNOWN; | |
1594 | codes[0].value = value; | |
1595 | return 1; | |
1596 | } | |
1597 | else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value))) | |
1598 | { | |
1599 | /* Either the constant is a simple LUI/ORI combination or its | |
1600 | lowest bit is set. We don't want to shift in this case. */ | |
1601 | return mips_build_lower (codes, value); | |
1602 | } | |
1603 | else if ((value & 0xffff) == 0) | |
1604 | { | |
1605 | /* The constant will need at least three actions. The lowest | |
1606 | 16 bits are clear, so the final action will be a shift. */ | |
1607 | return mips_build_shift (codes, value); | |
1608 | } | |
1609 | else | |
1610 | { | |
1611 | /* The final action could be a shift, add or inclusive OR. | |
1612 | Rather than use a complex condition to select the best | |
1613 | approach, try both mips_build_shift and mips_build_lower | |
1614 | and pick the one that gives the shortest sequence. | |
1615 | Note that this case is only used once per constant. */ | |
1616 | struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS]; | |
1617 | unsigned int cost, alt_cost; | |
1618 | ||
1619 | cost = mips_build_shift (codes, value); | |
1620 | alt_cost = mips_build_lower (alt_codes, value); | |
1621 | if (alt_cost < cost) | |
1622 | { | |
1623 | memcpy (codes, alt_codes, alt_cost * sizeof (codes[0])); | |
1624 | cost = alt_cost; | |
1625 | } | |
1626 | return cost; | |
1627 | } | |
1628 | } | |
1629 | \f | |
1a627b35 RS |
1630 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
1631 | ||
1632 | static bool | |
ef4bddc2 | 1633 | mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
1a627b35 RS |
1634 | { |
1635 | return mips_const_insns (x) > 0; | |
1636 | } | |
1637 | \f | |
ddaf8125 RS |
1638 | /* Return a SYMBOL_REF for a MIPS16 function called NAME. */ |
1639 | ||
1640 | static rtx | |
1641 | mips16_stub_function (const char *name) | |
1642 | { | |
1643 | rtx x; | |
1644 | ||
1645 | x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
1646 | SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION); | |
1647 | return x; | |
1648 | } | |
6d51cc90 RS |
1649 | |
1650 | /* Return a legitimate call address for STUB, given that STUB is a MIPS16 | |
1651 | support function. */ | |
1652 | ||
1653 | static rtx | |
1654 | mips16_stub_call_address (mips_one_only_stub *stub) | |
1655 | { | |
1656 | rtx fn = mips16_stub_function (stub->get_name ()); | |
1657 | SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL; | |
1658 | if (!call_insn_operand (fn, VOIDmode)) | |
1659 | fn = force_reg (Pmode, fn); | |
1660 | return fn; | |
1661 | } | |
1662 | \f | |
1663 | /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */ | |
1664 | ||
1665 | class mips16_rdhwr_one_only_stub : public mips_one_only_stub | |
1666 | { | |
1667 | virtual const char *get_name (); | |
1668 | virtual void output_body (); | |
1669 | }; | |
1670 | ||
1671 | const char * | |
1672 | mips16_rdhwr_one_only_stub::get_name () | |
1673 | { | |
1674 | return "__mips16_rdhwr"; | |
1675 | } | |
1676 | ||
1677 | void | |
1678 | mips16_rdhwr_one_only_stub::output_body () | |
1679 | { | |
1680 | fprintf (asm_out_file, | |
1681 | "\t.set\tpush\n" | |
1682 | "\t.set\tmips32r2\n" | |
1683 | "\t.set\tnoreorder\n" | |
1684 | "\trdhwr\t$3,$29\n" | |
1685 | "\t.set\tpop\n" | |
1686 | "\tj\t$31\n"); | |
1687 | } | |
a90c0245 RS |
1688 | |
1689 | /* A stub for moving the FCSR into GET_FCSR_REGNUM. */ | |
1690 | class mips16_get_fcsr_one_only_stub : public mips_one_only_stub | |
1691 | { | |
1692 | virtual const char *get_name (); | |
1693 | virtual void output_body (); | |
1694 | }; | |
1695 | ||
1696 | const char * | |
1697 | mips16_get_fcsr_one_only_stub::get_name () | |
1698 | { | |
1699 | return "__mips16_get_fcsr"; | |
1700 | } | |
1701 | ||
1702 | void | |
1703 | mips16_get_fcsr_one_only_stub::output_body () | |
1704 | { | |
1705 | fprintf (asm_out_file, | |
1706 | "\tcfc1\t%s,$31\n" | |
1707 | "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]); | |
1708 | } | |
1709 | ||
1710 | /* A stub for moving SET_FCSR_REGNUM into the FCSR. */ | |
1711 | class mips16_set_fcsr_one_only_stub : public mips_one_only_stub | |
1712 | { | |
1713 | virtual const char *get_name (); | |
1714 | virtual void output_body (); | |
1715 | }; | |
1716 | ||
1717 | const char * | |
1718 | mips16_set_fcsr_one_only_stub::get_name () | |
1719 | { | |
1720 | return "__mips16_set_fcsr"; | |
1721 | } | |
1722 | ||
1723 | void | |
1724 | mips16_set_fcsr_one_only_stub::output_body () | |
1725 | { | |
1726 | fprintf (asm_out_file, | |
1727 | "\tctc1\t%s,$31\n" | |
1728 | "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]); | |
1729 | } | |
ddaf8125 | 1730 | \f |
08d0963a RS |
1731 | /* Return true if symbols of type TYPE require a GOT access. */ |
1732 | ||
1733 | static bool | |
1734 | mips_got_symbol_type_p (enum mips_symbol_type type) | |
1735 | { | |
1736 | switch (type) | |
1737 | { | |
1738 | case SYMBOL_GOT_PAGE_OFST: | |
1739 | case SYMBOL_GOT_DISP: | |
1740 | return true; | |
1741 | ||
1742 | default: | |
1743 | return false; | |
1744 | } | |
1745 | } | |
1746 | ||
ab77a036 RS |
1747 | /* Return true if X is a thread-local symbol. */ |
1748 | ||
1749 | static bool | |
65239d20 | 1750 | mips_tls_symbol_p (rtx x) |
ab77a036 RS |
1751 | { |
1752 | return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
1753 | } | |
1754 | ||
08e7ceb3 RS |
1755 | /* Return true if SYMBOL_REF X is associated with a global symbol |
1756 | (in the STB_GLOBAL sense). */ | |
1757 | ||
1758 | static bool | |
3101faab | 1759 | mips_global_symbol_p (const_rtx x) |
08e7ceb3 | 1760 | { |
65239d20 | 1761 | const_tree decl = SYMBOL_REF_DECL (x); |
08e7ceb3 | 1762 | |
08e7ceb3 | 1763 | if (!decl) |
08d0963a | 1764 | return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x); |
08e7ceb3 RS |
1765 | |
1766 | /* Weakref symbols are not TREE_PUBLIC, but their targets are global | |
1767 | or weak symbols. Relocations in the object file will be against | |
1768 | the target symbol, so it's that symbol's binding that matters here. */ | |
1769 | return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl)); | |
1770 | } | |
1771 | ||
08d0963a RS |
1772 | /* Return true if function X is a libgcc MIPS16 stub function. */ |
1773 | ||
1774 | static bool | |
1775 | mips16_stub_function_p (const_rtx x) | |
1776 | { | |
1777 | return (GET_CODE (x) == SYMBOL_REF | |
1778 | && strncmp (XSTR (x, 0), "__mips16_", 9) == 0); | |
1779 | } | |
1780 | ||
1781 | /* Return true if function X is a locally-defined and locally-binding | |
1782 | MIPS16 function. */ | |
1783 | ||
1784 | static bool | |
1785 | mips16_local_function_p (const_rtx x) | |
1786 | { | |
1787 | return (GET_CODE (x) == SYMBOL_REF | |
1788 | && SYMBOL_REF_LOCAL_P (x) | |
1789 | && !SYMBOL_REF_EXTERNAL_P (x) | |
22c4c869 | 1790 | && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16)); |
08d0963a RS |
1791 | } |
1792 | ||
08e7ceb3 RS |
1793 | /* Return true if SYMBOL_REF X binds locally. */ |
1794 | ||
1795 | static bool | |
3101faab | 1796 | mips_symbol_binds_local_p (const_rtx x) |
08e7ceb3 RS |
1797 | { |
1798 | return (SYMBOL_REF_DECL (x) | |
1799 | ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) | |
1800 | : SYMBOL_REF_LOCAL_P (x)); | |
1801 | } | |
1802 | ||
a318179e RS |
1803 | /* Return true if rtx constants of mode MODE should be put into a small |
1804 | data section. */ | |
1805 | ||
1806 | static bool | |
ef4bddc2 | 1807 | mips_rtx_constant_in_small_data_p (machine_mode mode) |
a318179e RS |
1808 | { |
1809 | return (!TARGET_EMBEDDED_DATA | |
1810 | && TARGET_LOCAL_SDATA | |
65239d20 | 1811 | && GET_MODE_SIZE (mode) <= mips_small_data_threshold); |
a318179e RS |
1812 | } |
1813 | ||
ab77a036 RS |
1814 | /* Return true if X should not be moved directly into register $25. |
1815 | We need this because many versions of GAS will treat "la $25,foo" as | |
1816 | part of a call sequence and so allow a global "foo" to be lazily bound. */ | |
1817 | ||
1818 | bool | |
1819 | mips_dangerous_for_la25_p (rtx x) | |
1820 | { | |
1821 | return (!TARGET_EXPLICIT_RELOCS | |
1822 | && TARGET_USE_GOT | |
1823 | && GET_CODE (x) == SYMBOL_REF | |
1824 | && mips_global_symbol_p (x)); | |
1825 | } | |
1826 | ||
08d0963a RS |
1827 | /* Return true if calls to X might need $25 to be valid on entry. */ |
1828 | ||
1829 | bool | |
1830 | mips_use_pic_fn_addr_reg_p (const_rtx x) | |
1831 | { | |
1832 | if (!TARGET_USE_PIC_FN_ADDR_REG) | |
1833 | return false; | |
1834 | ||
1835 | /* MIPS16 stub functions are guaranteed not to use $25. */ | |
1836 | if (mips16_stub_function_p (x)) | |
1837 | return false; | |
1838 | ||
e21d5757 DJ |
1839 | if (GET_CODE (x) == SYMBOL_REF) |
1840 | { | |
1841 | /* If PLTs and copy relocations are available, the static linker | |
1842 | will make sure that $25 is valid on entry to the target function. */ | |
1843 | if (TARGET_ABICALLS_PIC0) | |
1844 | return false; | |
1845 | ||
1846 | /* Locally-defined functions use absolute accesses to set up | |
1847 | the global pointer. */ | |
1848 | if (TARGET_ABSOLUTE_ABICALLS | |
1849 | && mips_symbol_binds_local_p (x) | |
1850 | && !SYMBOL_REF_EXTERNAL_P (x)) | |
1851 | return false; | |
1852 | } | |
08d0963a RS |
1853 | |
1854 | return true; | |
1855 | } | |
1856 | ||
280fcbfa RS |
1857 | /* Return the method that should be used to access SYMBOL_REF or |
1858 | LABEL_REF X in context CONTEXT. */ | |
cafe096b EC |
1859 | |
1860 | static enum mips_symbol_type | |
3101faab | 1861 | mips_classify_symbol (const_rtx x, enum mips_symbol_context context) |
cee98a59 | 1862 | { |
8cb6400c RS |
1863 | if (TARGET_RTP_PIC) |
1864 | return SYMBOL_GOT_DISP; | |
1865 | ||
cafe096b | 1866 | if (GET_CODE (x) == LABEL_REF) |
76cbf5bf | 1867 | { |
4377fad9 RS |
1868 | /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16 |
1869 | code and if we know that the label is in the current function's | |
1870 | text section. LABEL_REFs are used for jump tables as well as | |
1871 | text labels, so we must check whether jump tables live in the | |
1872 | text section. */ | |
1873 | if (TARGET_MIPS16_SHORT_JUMP_TABLES | |
1874 | && !LABEL_REF_NONLOCAL_P (x)) | |
67da85da | 1875 | return SYMBOL_PC_RELATIVE; |
65239d20 | 1876 | |
d9870b7e | 1877 | if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) |
08e7ceb3 | 1878 | return SYMBOL_GOT_PAGE_OFST; |
65239d20 | 1879 | |
67da85da | 1880 | return SYMBOL_ABSOLUTE; |
76cbf5bf | 1881 | } |
cee98a59 | 1882 | |
7ad769fe | 1883 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
2bcb2ab3 | 1884 | |
69229b81 DJ |
1885 | if (SYMBOL_REF_TLS_MODEL (x)) |
1886 | return SYMBOL_TLS; | |
1887 | ||
cafe096b EC |
1888 | if (CONSTANT_POOL_ADDRESS_P (x)) |
1889 | { | |
c93c5160 RS |
1890 | if (TARGET_MIPS16_TEXT_LOADS) |
1891 | return SYMBOL_PC_RELATIVE; | |
1892 | ||
1893 | if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM) | |
67da85da | 1894 | return SYMBOL_PC_RELATIVE; |
cee98a59 | 1895 | |
a318179e | 1896 | if (mips_rtx_constant_in_small_data_p (get_pool_mode (x))) |
67da85da | 1897 | return SYMBOL_GP_RELATIVE; |
cafe096b EC |
1898 | } |
1899 | ||
3ac25120 RS |
1900 | /* Do not use small-data accesses for weak symbols; they may end up |
1901 | being zero. */ | |
65239d20 | 1902 | if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x)) |
67da85da | 1903 | return SYMBOL_GP_RELATIVE; |
b8898790 | 1904 | |
e06e2776 RS |
1905 | /* Don't use GOT accesses for locally-binding symbols when -mno-shared |
1906 | is in effect. */ | |
e21d5757 | 1907 | if (TARGET_ABICALLS_PIC2 |
e06e2776 | 1908 | && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))) |
f6149877 | 1909 | { |
08e7ceb3 RS |
1910 | /* There are three cases to consider: |
1911 | ||
1912 | - o32 PIC (either with or without explicit relocs) | |
1913 | - n32/n64 PIC without explicit relocs | |
1914 | - n32/n64 PIC with explicit relocs | |
1915 | ||
1916 | In the first case, both local and global accesses will use an | |
1917 | R_MIPS_GOT16 relocation. We must correctly predict which of | |
1918 | the two semantics (local or global) the assembler and linker | |
1919 | will apply. The choice depends on the symbol's binding rather | |
1920 | than its visibility. | |
f6149877 | 1921 | |
08e7ceb3 RS |
1922 | In the second case, the assembler will not use R_MIPS_GOT16 |
1923 | relocations, but it chooses between local and global accesses | |
1924 | in the same way as for o32 PIC. | |
1925 | ||
1926 | In the third case we have more freedom since both forms of | |
1927 | access will work for any kind of symbol. However, there seems | |
1928 | little point in doing things differently. */ | |
1929 | if (mips_global_symbol_p (x)) | |
1930 | return SYMBOL_GOT_DISP; | |
1931 | ||
1932 | return SYMBOL_GOT_PAGE_OFST; | |
f6149877 | 1933 | } |
cafe096b | 1934 | |
67da85da | 1935 | return SYMBOL_ABSOLUTE; |
cee98a59 MM |
1936 | } |
1937 | ||
65239d20 RS |
1938 | /* Classify the base of symbolic expression X, given that X appears in |
1939 | context CONTEXT. */ | |
6d992de0 RS |
1940 | |
1941 | static enum mips_symbol_type | |
1942 | mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context) | |
1943 | { | |
1944 | rtx offset; | |
1945 | ||
1946 | split_const (x, &x, &offset); | |
1947 | if (UNSPEC_ADDRESS_P (x)) | |
1948 | return UNSPEC_ADDRESS_TYPE (x); | |
1949 | ||
1950 | return mips_classify_symbol (x, context); | |
1951 | } | |
1952 | ||
6de36441 | 1953 | /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN |
65239d20 | 1954 | is the alignment in bytes of SYMBOL_REF X. */ |
8b5fb3a3 DD |
1955 | |
1956 | static bool | |
1957 | mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset) | |
1958 | { | |
65239d20 | 1959 | HOST_WIDE_INT align; |
8b5fb3a3 | 1960 | |
65239d20 RS |
1961 | align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1; |
1962 | return IN_RANGE (offset, 0, align - 1); | |
8b5fb3a3 DD |
1963 | } |
1964 | ||
280fcbfa RS |
1965 | /* Return true if X is a symbolic constant that can be used in context |
1966 | CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ | |
108b61d5 | 1967 | |
96a30b18 | 1968 | bool |
280fcbfa RS |
1969 | mips_symbolic_constant_p (rtx x, enum mips_symbol_context context, |
1970 | enum mips_symbol_type *symbol_type) | |
108b61d5 | 1971 | { |
7ffb5e78 | 1972 | rtx offset; |
108b61d5 | 1973 | |
7ffb5e78 | 1974 | split_const (x, &x, &offset); |
108b61d5 | 1975 | if (UNSPEC_ADDRESS_P (x)) |
8b5fb3a3 DD |
1976 | { |
1977 | *symbol_type = UNSPEC_ADDRESS_TYPE (x); | |
1978 | x = UNSPEC_ADDRESS (x); | |
1979 | } | |
108b61d5 | 1980 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) |
69229b81 | 1981 | { |
280fcbfa | 1982 | *symbol_type = mips_classify_symbol (x, context); |
69229b81 DJ |
1983 | if (*symbol_type == SYMBOL_TLS) |
1984 | return false; | |
1985 | } | |
108b61d5 RS |
1986 | else |
1987 | return false; | |
1988 | ||
7ffb5e78 | 1989 | if (offset == const0_rtx) |
108b61d5 RS |
1990 | return true; |
1991 | ||
1992 | /* Check whether a nonzero offset is valid for the underlying | |
1993 | relocations. */ | |
1994 | switch (*symbol_type) | |
1995 | { | |
67da85da | 1996 | case SYMBOL_ABSOLUTE: |
e245bd81 RS |
1997 | case SYMBOL_64_HIGH: |
1998 | case SYMBOL_64_MID: | |
1999 | case SYMBOL_64_LOW: | |
62973ffe RS |
2000 | /* If the target has 64-bit pointers and the object file only |
2001 | supports 32-bit symbols, the values of those symbols will be | |
2002 | sign-extended. In this case we can't allow an arbitrary offset | |
2003 | in case the 32-bit value X + OFFSET has a different sign from X. */ | |
2004 | if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS) | |
7ffb5e78 | 2005 | return offset_within_block_p (x, INTVAL (offset)); |
62973ffe RS |
2006 | |
2007 | /* In other cases the relocations can handle any offset. */ | |
108b61d5 RS |
2008 | return true; |
2009 | ||
67da85da | 2010 | case SYMBOL_PC_RELATIVE: |
76cbf5bf RS |
2011 | /* Allow constant pool references to be converted to LABEL+CONSTANT. |
2012 | In this case, we no longer have access to the underlying constant, | |
2013 | but the original symbol-based access was known to be valid. */ | |
2014 | if (GET_CODE (x) == LABEL_REF) | |
2015 | return true; | |
2016 | ||
2017 | /* Fall through. */ | |
2018 | ||
67da85da | 2019 | case SYMBOL_GP_RELATIVE: |
62973ffe | 2020 | /* Make sure that the offset refers to something within the |
7ffb5e78 | 2021 | same object block. This should guarantee that the final |
62973ffe | 2022 | PC- or GP-relative offset is within the 16-bit limit. */ |
7ffb5e78 | 2023 | return offset_within_block_p (x, INTVAL (offset)); |
108b61d5 | 2024 | |
08e7ceb3 | 2025 | case SYMBOL_GOT_PAGE_OFST: |
108b61d5 | 2026 | case SYMBOL_GOTOFF_PAGE: |
08e7ceb3 RS |
2027 | /* If the symbol is global, the GOT entry will contain the symbol's |
2028 | address, and we will apply a 16-bit offset after loading it. | |
2029 | If the symbol is local, the linker should provide enough local | |
2030 | GOT entries for a 16-bit offset, but larger offsets may lead | |
2031 | to GOT overflow. */ | |
7ffb5e78 | 2032 | return SMALL_INT (offset); |
108b61d5 | 2033 | |
8b5fb3a3 DD |
2034 | case SYMBOL_TPREL: |
2035 | case SYMBOL_DTPREL: | |
2036 | /* There is no carry between the HI and LO REL relocations, so the | |
2037 | offset is only valid if we know it won't lead to such a carry. */ | |
2038 | return mips_offset_within_alignment_p (x, INTVAL (offset)); | |
2039 | ||
08e7ceb3 RS |
2040 | case SYMBOL_GOT_DISP: |
2041 | case SYMBOL_GOTOFF_DISP: | |
108b61d5 RS |
2042 | case SYMBOL_GOTOFF_CALL: |
2043 | case SYMBOL_GOTOFF_LOADGP: | |
69229b81 DJ |
2044 | case SYMBOL_TLSGD: |
2045 | case SYMBOL_TLSLDM: | |
69229b81 DJ |
2046 | case SYMBOL_GOTTPREL: |
2047 | case SYMBOL_TLS: | |
8cb6400c | 2048 | case SYMBOL_HALF: |
108b61d5 RS |
2049 | return false; |
2050 | } | |
7ad769fe | 2051 | gcc_unreachable (); |
108b61d5 | 2052 | } |
ab77a036 RS |
2053 | \f |
2054 | /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a | |
2055 | single instruction. We rely on the fact that, in the worst case, | |
2056 | all instructions involved in a MIPS16 address calculation are usually | |
2057 | extended ones. */ | |
108b61d5 | 2058 | |
ab77a036 | 2059 | static int |
ef4bddc2 | 2060 | mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode) |
cee98a59 | 2061 | { |
ddaf8125 RS |
2062 | if (mips_use_pcrel_pool_p[(int) type]) |
2063 | { | |
2064 | if (mode == MAX_MACHINE_MODE) | |
2065 | /* LEAs will be converted into constant-pool references by | |
2066 | mips_reorg. */ | |
2067 | type = SYMBOL_PC_RELATIVE; | |
2068 | else | |
2069 | /* The constant must be loaded and then dereferenced. */ | |
2070 | return 0; | |
2071 | } | |
2072 | ||
ab77a036 | 2073 | switch (type) |
bcbc6b7f | 2074 | { |
ab77a036 RS |
2075 | case SYMBOL_ABSOLUTE: |
2076 | /* When using 64-bit symbols, we need 5 preparatory instructions, | |
2077 | such as: | |
bcbc6b7f | 2078 | |
ab77a036 RS |
2079 | lui $at,%highest(symbol) |
2080 | daddiu $at,$at,%higher(symbol) | |
2081 | dsll $at,$at,16 | |
2082 | daddiu $at,$at,%hi(symbol) | |
2083 | dsll $at,$at,16 | |
bcbc6b7f | 2084 | |
ab77a036 | 2085 | The final address is then $at + %lo(symbol). With 32-bit |
65239d20 RS |
2086 | symbols we just need a preparatory LUI for normal mode and |
2087 | a preparatory LI and SLL for MIPS16. */ | |
ab77a036 | 2088 | return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; |
bcbc6b7f | 2089 | |
ab77a036 RS |
2090 | case SYMBOL_GP_RELATIVE: |
2091 | /* Treat GP-relative accesses as taking a single instruction on | |
2092 | MIPS16 too; the copy of $gp can often be shared. */ | |
2093 | return 1; | |
b8eb88d0 | 2094 | |
67da85da | 2095 | case SYMBOL_PC_RELATIVE: |
65239d20 RS |
2096 | /* PC-relative constants can be only be used with ADDIUPC, |
2097 | DADDIUPC, LWPC and LDPC. */ | |
fbb96ac5 RS |
2098 | if (mode == MAX_MACHINE_MODE |
2099 | || GET_MODE_SIZE (mode) == 4 | |
2100 | || GET_MODE_SIZE (mode) == 8) | |
2101 | return 1; | |
2102 | ||
65239d20 | 2103 | /* The constant must be loaded using ADDIUPC or DADDIUPC first. */ |
fbb96ac5 | 2104 | return 0; |
b8eb88d0 | 2105 | |
08e7ceb3 | 2106 | case SYMBOL_GOT_DISP: |
fbb96ac5 RS |
2107 | /* The constant will have to be loaded from the GOT before it |
2108 | is used in an address. */ | |
2109 | if (mode != MAX_MACHINE_MODE) | |
2110 | return 0; | |
2111 | ||
2112 | /* Fall through. */ | |
2113 | ||
2114 | case SYMBOL_GOT_PAGE_OFST: | |
65239d20 RS |
2115 | /* Unless -funit-at-a-time is in effect, we can't be sure whether the |
2116 | local/global classification is accurate. The worst cases are: | |
2bcb2ab3 | 2117 | |
f6149877 RS |
2118 | (1) For local symbols when generating o32 or o64 code. The assembler |
2119 | will use: | |
108b61d5 | 2120 | |
f6149877 RS |
2121 | lw $at,%got(symbol) |
2122 | nop | |
108b61d5 | 2123 | |
f6149877 | 2124 | ...and the final address will be $at + %lo(symbol). |
108b61d5 | 2125 | |
f6149877 RS |
2126 | (2) For global symbols when -mxgot. The assembler will use: |
2127 | ||
2128 | lui $at,%got_hi(symbol) | |
2129 | (d)addu $at,$at,$gp | |
2130 | ||
2131 | ...and the final address will be $at + %got_lo(symbol). */ | |
2132 | return 3; | |
108b61d5 RS |
2133 | |
2134 | case SYMBOL_GOTOFF_PAGE: | |
08e7ceb3 | 2135 | case SYMBOL_GOTOFF_DISP: |
108b61d5 RS |
2136 | case SYMBOL_GOTOFF_CALL: |
2137 | case SYMBOL_GOTOFF_LOADGP: | |
e245bd81 RS |
2138 | case SYMBOL_64_HIGH: |
2139 | case SYMBOL_64_MID: | |
2140 | case SYMBOL_64_LOW: | |
69229b81 DJ |
2141 | case SYMBOL_TLSGD: |
2142 | case SYMBOL_TLSLDM: | |
2143 | case SYMBOL_DTPREL: | |
2144 | case SYMBOL_GOTTPREL: | |
2145 | case SYMBOL_TPREL: | |
fbb96ac5 RS |
2146 | case SYMBOL_HALF: |
2147 | /* A 16-bit constant formed by a single relocation, or a 32-bit | |
2148 | constant formed from a high 16-bit relocation and a low 16-bit | |
65239d20 RS |
2149 | relocation. Use mips_split_p to determine which. 32-bit |
2150 | constants need an "lui; addiu" sequence for normal mode and | |
2151 | an "li; sll; addiu" sequence for MIPS16 mode. */ | |
c93c5160 | 2152 | return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2; |
69229b81 DJ |
2153 | |
2154 | case SYMBOL_TLS: | |
2155 | /* We don't treat a bare TLS symbol as a constant. */ | |
2156 | return 0; | |
2bcb2ab3 | 2157 | } |
7ad769fe | 2158 | gcc_unreachable (); |
cafe096b | 2159 | } |
2bcb2ab3 | 2160 | |
fbb96ac5 RS |
2161 | /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed |
2162 | to load symbols of type TYPE into a register. Return 0 if the given | |
2163 | type of symbol cannot be used as an immediate operand. | |
2164 | ||
2165 | Otherwise, return the number of instructions needed to load or store | |
2166 | values of mode MODE to or from addresses of type TYPE. Return 0 if | |
2167 | the given type of symbol is not valid in addresses. | |
2168 | ||
da734fa1 | 2169 | In both cases, instruction counts are based off BASE_INSN_LENGTH. */ |
fbb96ac5 RS |
2170 | |
2171 | static int | |
ef4bddc2 | 2172 | mips_symbol_insns (enum mips_symbol_type type, machine_mode mode) |
fbb96ac5 RS |
2173 | { |
2174 | return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1); | |
2175 | } | |
65239d20 | 2176 | \f |
65239d20 | 2177 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
cee98a59 | 2178 | |
cafe096b | 2179 | static bool |
ef4bddc2 | 2180 | mips_cannot_force_const_mem (machine_mode mode, rtx x) |
cee98a59 | 2181 | { |
08d0963a | 2182 | enum mips_symbol_type type; |
ab77a036 RS |
2183 | rtx base, offset; |
2184 | ||
08d0963a RS |
2185 | /* There is no assembler syntax for expressing an address-sized |
2186 | high part. */ | |
2187 | if (GET_CODE (x) == HIGH) | |
2188 | return true; | |
2189 | ||
2190 | /* As an optimization, reject constants that mips_legitimize_move | |
2191 | can expand inline. | |
2192 | ||
2193 | Suppose we have a multi-instruction sequence that loads constant C | |
2194 | into register R. If R does not get allocated a hard register, and | |
2195 | R is used in an operand that allows both registers and memory | |
2196 | references, reload will consider forcing C into memory and using | |
2197 | one of the instruction's memory alternatives. Returning false | |
2198 | here will force it to use an input reload instead. */ | |
1a627b35 | 2199 | if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x)) |
08d0963a | 2200 | return true; |
ab77a036 | 2201 | |
08d0963a | 2202 | split_const (x, &base, &offset); |
ddaf8125 | 2203 | if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)) |
08d0963a | 2204 | { |
ddaf8125 RS |
2205 | /* See whether we explicitly want these symbols in the pool. */ |
2206 | if (mips_use_pcrel_pool_p[(int) type]) | |
2207 | return false; | |
2208 | ||
08d0963a RS |
2209 | /* The same optimization as for CONST_INT. */ |
2210 | if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0) | |
ab77a036 RS |
2211 | return true; |
2212 | ||
08d0963a RS |
2213 | /* If MIPS16 constant pools live in the text section, they should |
2214 | not refer to anything that might need run-time relocation. */ | |
2215 | if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type)) | |
ab77a036 | 2216 | return true; |
cafe096b | 2217 | } |
ab77a036 | 2218 | |
65239d20 | 2219 | /* TLS symbols must be computed by mips_legitimize_move. */ |
093a6c99 | 2220 | if (tls_referenced_p (x)) |
ab77a036 RS |
2221 | return true; |
2222 | ||
cafe096b EC |
2223 | return false; |
2224 | } | |
cee98a59 | 2225 | |
ab77a036 RS |
2226 | /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for |
2227 | constants when we're using a per-function constant pool. */ | |
cee98a59 | 2228 | |
ab77a036 | 2229 | static bool |
ef4bddc2 | 2230 | mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED, |
ab77a036 RS |
2231 | const_rtx x ATTRIBUTE_UNUSED) |
2232 | { | |
2233 | return !TARGET_MIPS16_PCREL_LOADS; | |
2234 | } | |
2235 | \f | |
65239d20 RS |
2236 | /* Return true if register REGNO is a valid base register for mode MODE. |
2237 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
cee98a59 | 2238 | |
cafe096b | 2239 | int |
ef4bddc2 | 2240 | mips_regno_mode_ok_for_base_p (int regno, machine_mode mode, |
65239d20 | 2241 | bool strict_p) |
cafe096b | 2242 | { |
ab77a036 RS |
2243 | if (!HARD_REGISTER_NUM_P (regno)) |
2244 | { | |
65239d20 | 2245 | if (!strict_p) |
ab77a036 RS |
2246 | return true; |
2247 | regno = reg_renumber[regno]; | |
2248 | } | |
cafe096b | 2249 | |
ab77a036 RS |
2250 | /* These fake registers will be eliminated to either the stack or |
2251 | hard frame pointer, both of which are usually valid base registers. | |
2252 | Reload deals with the cases where the eliminated form isn't valid. */ | |
2253 | if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) | |
2254 | return true; | |
2255 | ||
65239d20 | 2256 | /* In MIPS16 mode, the stack pointer can only address word and doubleword |
a78cc314 | 2257 | values, nothing smaller. */ |
ab77a036 | 2258 | if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) |
a78cc314 | 2259 | return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; |
ab77a036 RS |
2260 | |
2261 | return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); | |
2262 | } | |
2263 | ||
65239d20 RS |
2264 | /* Return true if X is a valid base register for mode MODE. |
2265 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
ab77a036 RS |
2266 | |
2267 | static bool | |
ef4bddc2 | 2268 | mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p) |
ab77a036 | 2269 | { |
65239d20 | 2270 | if (!strict_p && GET_CODE (x) == SUBREG) |
ab77a036 RS |
2271 | x = SUBREG_REG (x); |
2272 | ||
2273 | return (REG_P (x) | |
65239d20 | 2274 | && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); |
ab77a036 RS |
2275 | } |
2276 | ||
fa21a761 RS |
2277 | /* Return true if, for every base register BASE_REG, (plus BASE_REG X) |
2278 | can address a value of mode MODE. */ | |
2279 | ||
2280 | static bool | |
ef4bddc2 | 2281 | mips_valid_offset_p (rtx x, machine_mode mode) |
fa21a761 RS |
2282 | { |
2283 | /* Check that X is a signed 16-bit number. */ | |
2284 | if (!const_arith_operand (x, Pmode)) | |
2285 | return false; | |
2286 | ||
2287 | /* We may need to split multiword moves, so make sure that every word | |
2288 | is accessible. */ | |
2289 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2290 | && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) | |
2291 | return false; | |
2292 | ||
2293 | return true; | |
2294 | } | |
2295 | ||
2296 | /* Return true if a LO_SUM can address a value of mode MODE when the | |
2297 | LO_SUM symbol has type SYMBOL_TYPE. */ | |
2298 | ||
2299 | static bool | |
ef4bddc2 | 2300 | mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, machine_mode mode) |
fa21a761 RS |
2301 | { |
2302 | /* Check that symbols of type SYMBOL_TYPE can be used to access values | |
2303 | of mode MODE. */ | |
2304 | if (mips_symbol_insns (symbol_type, mode) == 0) | |
2305 | return false; | |
2306 | ||
2307 | /* Check that there is a known low-part relocation. */ | |
2308 | if (mips_lo_relocs[symbol_type] == NULL) | |
2309 | return false; | |
2310 | ||
2311 | /* We may need to split multiword moves, so make sure that each word | |
2312 | can be accessed without inducing a carry. This is mainly needed | |
2313 | for o64, which has historically only guaranteed 64-bit alignment | |
2314 | for 128-bit types. */ | |
2315 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2316 | && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) | |
2317 | return false; | |
2318 | ||
2319 | return true; | |
2320 | } | |
2321 | ||
ab77a036 | 2322 | /* Return true if X is a valid address for machine mode MODE. If it is, |
65239d20 RS |
2323 | fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in |
2324 | effect. */ | |
ab77a036 RS |
2325 | |
2326 | static bool | |
2327 | mips_classify_address (struct mips_address_info *info, rtx x, | |
ef4bddc2 | 2328 | machine_mode mode, bool strict_p) |
ab77a036 RS |
2329 | { |
2330 | switch (GET_CODE (x)) | |
2331 | { | |
2332 | case REG: | |
2333 | case SUBREG: | |
2334 | info->type = ADDRESS_REG; | |
2335 | info->reg = x; | |
2336 | info->offset = const0_rtx; | |
65239d20 | 2337 | return mips_valid_base_register_p (info->reg, mode, strict_p); |
ab77a036 RS |
2338 | |
2339 | case PLUS: | |
2340 | info->type = ADDRESS_REG; | |
2341 | info->reg = XEXP (x, 0); | |
2342 | info->offset = XEXP (x, 1); | |
65239d20 | 2343 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2344 | && mips_valid_offset_p (info->offset, mode)); |
ab77a036 RS |
2345 | |
2346 | case LO_SUM: | |
2347 | info->type = ADDRESS_LO_SUM; | |
2348 | info->reg = XEXP (x, 0); | |
2349 | info->offset = XEXP (x, 1); | |
2350 | /* We have to trust the creator of the LO_SUM to do something vaguely | |
2351 | sane. Target-independent code that creates a LO_SUM should also | |
2352 | create and verify the matching HIGH. Target-independent code that | |
2353 | adds an offset to a LO_SUM must prove that the offset will not | |
2354 | induce a carry. Failure to do either of these things would be | |
2355 | a bug, and we are not required to check for it here. The MIPS | |
2356 | backend itself should only create LO_SUMs for valid symbolic | |
2357 | constants, with the high part being either a HIGH or a copy | |
2358 | of _gp. */ | |
2359 | info->symbol_type | |
2360 | = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM); | |
65239d20 | 2361 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2362 | && mips_valid_lo_sum_p (info->symbol_type, mode)); |
ab77a036 RS |
2363 | |
2364 | case CONST_INT: | |
2365 | /* Small-integer addresses don't occur very often, but they | |
2366 | are legitimate if $0 is a valid base register. */ | |
2367 | info->type = ADDRESS_CONST_INT; | |
2368 | return !TARGET_MIPS16 && SMALL_INT (x); | |
2369 | ||
2370 | case CONST: | |
2371 | case LABEL_REF: | |
2372 | case SYMBOL_REF: | |
2373 | info->type = ADDRESS_SYMBOLIC; | |
2374 | return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM, | |
2375 | &info->symbol_type) | |
2376 | && mips_symbol_insns (info->symbol_type, mode) > 0 | |
2377 | && !mips_split_p[info->symbol_type]); | |
2378 | ||
2379 | default: | |
2380 | return false; | |
2381 | } | |
2382 | } | |
2383 | ||
c6c3dba9 | 2384 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ |
ab77a036 | 2385 | |
c6c3dba9 | 2386 | static bool |
ef4bddc2 | 2387 | mips_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) |
ab77a036 RS |
2388 | { |
2389 | struct mips_address_info addr; | |
2390 | ||
65239d20 | 2391 | return mips_classify_address (&addr, x, mode, strict_p); |
ab77a036 RS |
2392 | } |
2393 | ||
2394 | /* Return true if X is a legitimate $sp-based address for mode MDOE. */ | |
2395 | ||
2396 | bool | |
ef4bddc2 | 2397 | mips_stack_address_p (rtx x, machine_mode mode) |
ab77a036 RS |
2398 | { |
2399 | struct mips_address_info addr; | |
2400 | ||
2401 | return (mips_classify_address (&addr, x, mode, false) | |
2402 | && addr.type == ADDRESS_REG | |
2403 | && addr.reg == stack_pointer_rtx); | |
2404 | } | |
2405 | ||
65239d20 RS |
2406 | /* Return true if ADDR matches the pattern for the LWXS load scaled indexed |
2407 | address instruction. Note that such addresses are not considered | |
331d9186 | 2408 | legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use |
65239d20 | 2409 | is so restricted. */ |
ab77a036 RS |
2410 | |
2411 | static bool | |
2412 | mips_lwxs_address_p (rtx addr) | |
2413 | { | |
2414 | if (ISA_HAS_LWXS | |
2415 | && GET_CODE (addr) == PLUS | |
2416 | && REG_P (XEXP (addr, 1))) | |
2417 | { | |
2418 | rtx offset = XEXP (addr, 0); | |
2419 | if (GET_CODE (offset) == MULT | |
2420 | && REG_P (XEXP (offset, 0)) | |
47ac44d6 | 2421 | && CONST_INT_P (XEXP (offset, 1)) |
ab77a036 RS |
2422 | && INTVAL (XEXP (offset, 1)) == 4) |
2423 | return true; | |
2424 | } | |
2425 | return false; | |
2426 | } | |
770da00a AP |
2427 | |
2428 | /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load | |
2429 | indexed address instruction. Note that such addresses are | |
2430 | not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P | |
2431 | sense, because their use is so restricted. */ | |
2432 | ||
2433 | static bool | |
ef4bddc2 | 2434 | mips_lx_address_p (rtx addr, machine_mode mode) |
770da00a AP |
2435 | { |
2436 | if (GET_CODE (addr) != PLUS | |
2437 | || !REG_P (XEXP (addr, 0)) | |
2438 | || !REG_P (XEXP (addr, 1))) | |
2439 | return false; | |
2440 | if (ISA_HAS_LBX && mode == QImode) | |
2441 | return true; | |
2442 | if (ISA_HAS_LHX && mode == HImode) | |
2443 | return true; | |
2444 | if (ISA_HAS_LWX && mode == SImode) | |
2445 | return true; | |
2446 | if (ISA_HAS_LDX && mode == DImode) | |
2447 | return true; | |
2448 | return false; | |
2449 | } | |
65239d20 RS |
2450 | \f |
2451 | /* Return true if a value at OFFSET bytes from base register BASE can be | |
2452 | accessed using an unextended MIPS16 instruction. MODE is the mode of | |
2453 | the value. | |
ab77a036 RS |
2454 | |
2455 | Usually the offset in an unextended instruction is a 5-bit field. | |
65239d20 RS |
2456 | The offset is unsigned and shifted left once for LH and SH, twice |
2457 | for LW and SW, and so on. An exception is LWSP and SWSP, which have | |
2458 | an 8-bit immediate field that's shifted left twice. */ | |
ab77a036 RS |
2459 | |
2460 | static bool | |
ef4bddc2 | 2461 | mips16_unextended_reference_p (machine_mode mode, rtx base, |
65239d20 | 2462 | unsigned HOST_WIDE_INT offset) |
ab77a036 | 2463 | { |
fd2d6b1b | 2464 | if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0) |
ab77a036 RS |
2465 | { |
2466 | if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) | |
65239d20 RS |
2467 | return offset < 256U * GET_MODE_SIZE (mode); |
2468 | return offset < 32U * GET_MODE_SIZE (mode); | |
ab77a036 RS |
2469 | } |
2470 | return false; | |
2471 | } | |
2472 | ||
ab77a036 | 2473 | /* Return the number of instructions needed to load or store a value |
da734fa1 RS |
2474 | of mode MODE at address X, assuming that BASE_INSN_LENGTH is the |
2475 | length of one instruction. Return 0 if X isn't valid for MODE. | |
65239d20 RS |
2476 | Assume that multiword moves may need to be split into word moves |
2477 | if MIGHT_SPLIT_P, otherwise assume that a single load or store is | |
da734fa1 | 2478 | enough. */ |
ab77a036 RS |
2479 | |
2480 | int | |
ef4bddc2 | 2481 | mips_address_insns (rtx x, machine_mode mode, bool might_split_p) |
ab77a036 RS |
2482 | { |
2483 | struct mips_address_info addr; | |
2484 | int factor; | |
2485 | ||
2486 | /* BLKmode is used for single unaligned loads and stores and should | |
2487 | not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty | |
2488 | meaningless, so we have to single it out as a special case one way | |
2489 | or the other.) */ | |
5955b0a3 | 2490 | if (mode != BLKmode && might_split_p) |
656f37ee | 2491 | factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
5955b0a3 RS |
2492 | else |
2493 | factor = 1; | |
656f37ee | 2494 | |
108b61d5 RS |
2495 | if (mips_classify_address (&addr, x, mode, false)) |
2496 | switch (addr.type) | |
2497 | { | |
2498 | case ADDRESS_REG: | |
2499 | if (TARGET_MIPS16 | |
65239d20 RS |
2500 | && !mips16_unextended_reference_p (mode, addr.reg, |
2501 | UINTVAL (addr.offset))) | |
108b61d5 RS |
2502 | return factor * 2; |
2503 | return factor; | |
cafe096b | 2504 | |
108b61d5 | 2505 | case ADDRESS_LO_SUM: |
65239d20 | 2506 | return TARGET_MIPS16 ? factor * 2 : factor; |
4fef83a7 | 2507 | |
108b61d5 RS |
2508 | case ADDRESS_CONST_INT: |
2509 | return factor; | |
cafe096b | 2510 | |
108b61d5 | 2511 | case ADDRESS_SYMBOLIC: |
fbb96ac5 | 2512 | return factor * mips_symbol_insns (addr.symbol_type, mode); |
108b61d5 RS |
2513 | } |
2514 | return 0; | |
cafe096b EC |
2515 | } |
2516 | ||
03a7dddb CM |
2517 | /* Return true if X fits within an unsigned field of BITS bits that is |
2518 | shifted left SHIFT bits before being used. */ | |
2519 | ||
2520 | bool | |
2521 | mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0) | |
2522 | { | |
2523 | return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits)); | |
2524 | } | |
2525 | ||
2526 | /* Return true if X fits within a signed field of BITS bits that is | |
2527 | shifted left SHIFT bits before being used. */ | |
2528 | ||
2529 | bool | |
2530 | mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0) | |
2531 | { | |
2532 | x += 1 << (bits + shift - 1); | |
2533 | return mips_unsigned_immediate_p (x, bits, shift); | |
2534 | } | |
2535 | ||
2536 | /* Return true if X is legitimate for accessing values of mode MODE, | |
2537 | if it is based on a MIPS16 register, and if the offset satisfies | |
2538 | OFFSET_PREDICATE. */ | |
2539 | ||
2540 | bool | |
ef4bddc2 | 2541 | m16_based_address_p (rtx x, machine_mode mode, |
03a7dddb CM |
2542 | insn_operand_predicate_fn offset_predicate) |
2543 | { | |
2544 | struct mips_address_info addr; | |
2545 | ||
2546 | return (mips_classify_address (&addr, x, mode, false) | |
2547 | && addr.type == ADDRESS_REG | |
2548 | && M16_REG_P (REGNO (addr.reg)) | |
2549 | && offset_predicate (addr.offset, mode)); | |
2550 | } | |
2551 | ||
2552 | /* Return true if X is a legitimate address that conforms to the requirements | |
2553 | for a microMIPS LWSP or SWSP insn. */ | |
2554 | ||
2555 | bool | |
ef4bddc2 | 2556 | lwsp_swsp_address_p (rtx x, machine_mode mode) |
03a7dddb CM |
2557 | { |
2558 | struct mips_address_info addr; | |
2559 | ||
2560 | return (mips_classify_address (&addr, x, mode, false) | |
2561 | && addr.type == ADDRESS_REG | |
2562 | && REGNO (addr.reg) == STACK_POINTER_REGNUM | |
2563 | && uw5_operand (addr.offset, mode)); | |
2564 | } | |
2565 | ||
22c4c869 CM |
2566 | /* Return true if X is a legitimate address with a 12-bit offset. |
2567 | MODE is the mode of the value being accessed. */ | |
2568 | ||
2569 | bool | |
ef4bddc2 | 2570 | umips_12bit_offset_address_p (rtx x, machine_mode mode) |
22c4c869 CM |
2571 | { |
2572 | struct mips_address_info addr; | |
2573 | ||
2574 | return (mips_classify_address (&addr, x, mode, false) | |
2575 | && addr.type == ADDRESS_REG | |
2576 | && CONST_INT_P (addr.offset) | |
2577 | && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset))); | |
2578 | } | |
2579 | ||
da734fa1 RS |
2580 | /* Return the number of instructions needed to load constant X, |
2581 | assuming that BASE_INSN_LENGTH is the length of one instruction. | |
65239d20 | 2582 | Return 0 if X isn't a valid constant. */ |
cafe096b EC |
2583 | |
2584 | int | |
b4966b1b | 2585 | mips_const_insns (rtx x) |
cafe096b | 2586 | { |
b259a9a6 | 2587 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; |
108b61d5 | 2588 | enum mips_symbol_type symbol_type; |
7ffb5e78 | 2589 | rtx offset; |
cafe096b EC |
2590 | |
2591 | switch (GET_CODE (x)) | |
2592 | { | |
cafe096b | 2593 | case HIGH: |
c93c5160 RS |
2594 | if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA, |
2595 | &symbol_type) | |
108b61d5 RS |
2596 | || !mips_split_p[symbol_type]) |
2597 | return 0; | |
2598 | ||
65239d20 RS |
2599 | /* This is simply an LUI for normal mode. It is an extended |
2600 | LI followed by an extended SLL for MIPS16. */ | |
c93c5160 | 2601 | return TARGET_MIPS16 ? 4 : 1; |
cee98a59 MM |
2602 | |
2603 | case CONST_INT: | |
2bcb2ab3 | 2604 | if (TARGET_MIPS16) |
cafe096b EC |
2605 | /* Unsigned 8-bit constants can be loaded using an unextended |
2606 | LI instruction. Unsigned 16-bit constants can be loaded | |
2607 | using an extended LI. Negative constants must be loaded | |
2608 | using LI and then negated. */ | |
65239d20 | 2609 | return (IN_RANGE (INTVAL (x), 0, 255) ? 1 |
cafe096b | 2610 | : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 |
65239d20 | 2611 | : IN_RANGE (-INTVAL (x), 0, 255) ? 2 |
cafe096b EC |
2612 | : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 |
2613 | : 0); | |
2614 | ||
b259a9a6 | 2615 | return mips_build_integer (codes, INTVAL (x)); |
cee98a59 | 2616 | |
cafe096b | 2617 | case CONST_DOUBLE: |
06a4ab70 | 2618 | case CONST_VECTOR: |
65239d20 RS |
2619 | /* Allow zeros for normal mode, where we can use $0. */ |
2620 | return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; | |
cee98a59 | 2621 | |
108b61d5 RS |
2622 | case CONST: |
2623 | if (CONST_GP_P (x)) | |
2624 | return 1; | |
2625 | ||
2626 | /* See if we can refer to X directly. */ | |
280fcbfa | 2627 | if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type)) |
fbb96ac5 | 2628 | return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE); |
108b61d5 RS |
2629 | |
2630 | /* Otherwise try splitting the constant into a base and offset. | |
08d0963a RS |
2631 | If the offset is a 16-bit value, we can load the base address |
2632 | into a register and then use (D)ADDIU to add in the offset. | |
2633 | If the offset is larger, we can load the base and offset | |
2634 | into separate registers and add them together with (D)ADDU. | |
2635 | However, the latter is only possible before reload; during | |
2636 | and after reload, we must have the option of forcing the | |
2637 | constant into the pool instead. */ | |
7ffb5e78 | 2638 | split_const (x, &x, &offset); |
108b61d5 | 2639 | if (offset != 0) |
cafe096b | 2640 | { |
108b61d5 RS |
2641 | int n = mips_const_insns (x); |
2642 | if (n != 0) | |
2643 | { | |
7ffb5e78 | 2644 | if (SMALL_INT (offset)) |
108b61d5 | 2645 | return n + 1; |
fbbf66e7 | 2646 | else if (!targetm.cannot_force_const_mem (GET_MODE (x), x)) |
7ffb5e78 | 2647 | return n + 1 + mips_build_integer (codes, INTVAL (offset)); |
108b61d5 RS |
2648 | } |
2649 | } | |
2650 | return 0; | |
cee98a59 | 2651 | |
108b61d5 RS |
2652 | case SYMBOL_REF: |
2653 | case LABEL_REF: | |
fbb96ac5 RS |
2654 | return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA), |
2655 | MAX_MACHINE_MODE); | |
cee98a59 | 2656 | |
108b61d5 RS |
2657 | default: |
2658 | return 0; | |
cafe096b EC |
2659 | } |
2660 | } | |
cee98a59 | 2661 | |
c5cb5d18 RS |
2662 | /* X is a doubleword constant that can be handled by splitting it into |
2663 | two words and loading each word separately. Return the number of | |
da734fa1 RS |
2664 | instructions required to do this, assuming that BASE_INSN_LENGTH |
2665 | is the length of one instruction. */ | |
c5cb5d18 RS |
2666 | |
2667 | int | |
2668 | mips_split_const_insns (rtx x) | |
2669 | { | |
2670 | unsigned int low, high; | |
2671 | ||
2672 | low = mips_const_insns (mips_subword (x, false)); | |
2673 | high = mips_const_insns (mips_subword (x, true)); | |
2674 | gcc_assert (low > 0 && high > 0); | |
2675 | return low + high; | |
2676 | } | |
2677 | ||
5955b0a3 | 2678 | /* Return the number of instructions needed to implement INSN, |
da734fa1 RS |
2679 | given that it loads from or stores to MEM. Assume that |
2680 | BASE_INSN_LENGTH is the length of one instruction. */ | |
f5963e61 | 2681 | |
cafe096b | 2682 | int |
e8a54173 | 2683 | mips_load_store_insns (rtx mem, rtx_insn *insn) |
cafe096b | 2684 | { |
ef4bddc2 | 2685 | machine_mode mode; |
5955b0a3 RS |
2686 | bool might_split_p; |
2687 | rtx set; | |
2688 | ||
2689 | gcc_assert (MEM_P (mem)); | |
2690 | mode = GET_MODE (mem); | |
2691 | ||
2692 | /* Try to prove that INSN does not need to be split. */ | |
4670abb0 RS |
2693 | might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD; |
2694 | if (might_split_p) | |
5955b0a3 RS |
2695 | { |
2696 | set = single_set (insn); | |
4670abb0 | 2697 | if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn)) |
5955b0a3 RS |
2698 | might_split_p = false; |
2699 | } | |
2700 | ||
2701 | return mips_address_insns (XEXP (mem, 0), mode, might_split_p); | |
cafe096b | 2702 | } |
2bcb2ab3 | 2703 | |
da734fa1 RS |
2704 | /* Return the number of instructions needed for an integer division, |
2705 | assuming that BASE_INSN_LENGTH is the length of one instruction. */ | |
46490403 MR |
2706 | |
2707 | int | |
2708 | mips_idiv_insns (void) | |
2709 | { | |
2710 | int count; | |
2711 | ||
2712 | count = 1; | |
2713 | if (TARGET_CHECK_ZERO_DIV) | |
9f0df97a DD |
2714 | { |
2715 | if (GENERATE_DIVIDE_TRAPS) | |
2716 | count++; | |
2717 | else | |
2718 | count += 2; | |
2719 | } | |
66083422 | 2720 | |
6ba7b547 | 2721 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) |
46490403 MR |
2722 | count++; |
2723 | return count; | |
2724 | } | |
50d32cf6 | 2725 | \f |
51e7252a RS |
2726 | /* Emit a move from SRC to DEST. Assume that the move expanders can |
2727 | handle all moves if !can_create_pseudo_p (). The distinction is | |
2728 | important because, unlike emit_move_insn, the move expanders know | |
2729 | how to force Pmode objects into the constant pool even when the | |
2730 | constant pool address is not itself legitimate. */ | |
2731 | ||
c6f971f4 | 2732 | rtx_insn * |
51e7252a RS |
2733 | mips_emit_move (rtx dest, rtx src) |
2734 | { | |
2735 | return (can_create_pseudo_p () | |
2736 | ? emit_move_insn (dest, src) | |
2737 | : emit_move_insn_1 (dest, src)); | |
2738 | } | |
108b61d5 | 2739 | |
4670abb0 RS |
2740 | /* Emit a move from SRC to DEST, splitting compound moves into individual |
2741 | instructions. SPLIT_TYPE is the type of split to perform. */ | |
2742 | ||
2743 | static void | |
2744 | mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type) | |
2745 | { | |
2746 | if (mips_split_move_p (dest, src, split_type)) | |
2747 | mips_split_move (dest, src, split_type); | |
2748 | else | |
2749 | mips_emit_move (dest, src); | |
2750 | } | |
2751 | ||
d48a3196 CF |
2752 | /* Emit an instruction of the form (set TARGET (CODE OP0)). */ |
2753 | ||
2754 | static void | |
2755 | mips_emit_unary (enum rtx_code code, rtx target, rtx op0) | |
2756 | { | |
2757 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2758 | gen_rtx_fmt_e (code, GET_MODE (op0), op0))); | |
2759 | } | |
2760 | ||
2761 | /* Compute (CODE OP0) and store the result in a new register of mode MODE. | |
2762 | Return that new register. */ | |
2763 | ||
2764 | static rtx | |
ef4bddc2 | 2765 | mips_force_unary (machine_mode mode, enum rtx_code code, rtx op0) |
d48a3196 CF |
2766 | { |
2767 | rtx reg; | |
2768 | ||
2769 | reg = gen_reg_rtx (mode); | |
2770 | mips_emit_unary (code, reg, op0); | |
2771 | return reg; | |
2772 | } | |
2773 | ||
ab77a036 RS |
2774 | /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ |
2775 | ||
a2ccf3c2 | 2776 | void |
ab77a036 RS |
2777 | mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) |
2778 | { | |
2779 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2780 | gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); | |
2781 | } | |
2782 | ||
49bce30a RS |
2783 | /* Compute (CODE OP0 OP1) and store the result in a new register |
2784 | of mode MODE. Return that new register. */ | |
2785 | ||
2786 | static rtx | |
ef4bddc2 | 2787 | mips_force_binary (machine_mode mode, enum rtx_code code, rtx op0, rtx op1) |
49bce30a RS |
2788 | { |
2789 | rtx reg; | |
2790 | ||
2791 | reg = gen_reg_rtx (mode); | |
2792 | mips_emit_binary (code, reg, op0, op1); | |
2793 | return reg; | |
2794 | } | |
2795 | ||
65239d20 | 2796 | /* Copy VALUE to a register and return that register. If new pseudos |
108b61d5 RS |
2797 | are allowed, copy it into a new register, otherwise use DEST. */ |
2798 | ||
2799 | static rtx | |
2800 | mips_force_temporary (rtx dest, rtx value) | |
2801 | { | |
b3a13419 | 2802 | if (can_create_pseudo_p ()) |
108b61d5 RS |
2803 | return force_reg (Pmode, value); |
2804 | else | |
2805 | { | |
65239d20 | 2806 | mips_emit_move (dest, value); |
108b61d5 RS |
2807 | return dest; |
2808 | } | |
cafe096b | 2809 | } |
dbc90b65 RS |
2810 | |
2811 | /* Emit a call sequence with call pattern PATTERN and return the call | |
2812 | instruction itself (which is not necessarily the last instruction | |
08d0963a RS |
2813 | emitted). ORIG_ADDR is the original, unlegitimized address, |
2814 | ADDR is the legitimized form, and LAZY_P is true if the call | |
2815 | address is lazily-bound. */ | |
dbc90b65 | 2816 | |
c6f971f4 | 2817 | static rtx_insn * |
08d0963a | 2818 | mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p) |
dbc90b65 | 2819 | { |
c6f971f4 DM |
2820 | rtx_insn *insn; |
2821 | rtx reg; | |
dbc90b65 RS |
2822 | |
2823 | insn = emit_call_insn (pattern); | |
2824 | ||
08d0963a RS |
2825 | if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr)) |
2826 | { | |
2827 | /* MIPS16 JALRs only take MIPS16 registers. If the target | |
2828 | function requires $25 to be valid on entry, we must copy it | |
2829 | there separately. The move instruction can be put in the | |
2830 | call's delay slot. */ | |
2831 | reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
2832 | emit_insn_before (gen_move_insn (reg, addr), insn); | |
2833 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
2834 | } | |
2835 | ||
dbc90b65 | 2836 | if (lazy_p) |
08d0963a | 2837 | /* Lazy-binding stubs require $gp to be valid on entry. */ |
dbc90b65 RS |
2838 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2839 | ||
2840 | if (TARGET_USE_GOT) | |
2841 | { | |
2842 | /* See the comment above load_call<mode> for details. */ | |
2843 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2844 | gen_rtx_REG (Pmode, GOT_VERSION_REGNUM)); | |
2845 | emit_insn (gen_update_got_version ()); | |
2846 | } | |
c2db3f3d RO |
2847 | |
2848 | if (TARGET_MIPS16 | |
2849 | && TARGET_EXPLICIT_RELOCS | |
2850 | && TARGET_CALL_CLOBBERED_GP) | |
2851 | { | |
2852 | rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); | |
2853 | clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg); | |
2854 | } | |
2855 | ||
dbc90b65 RS |
2856 | return insn; |
2857 | } | |
65239d20 | 2858 | \f |
7462a715 RS |
2859 | /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, |
2860 | then add CONST_INT OFFSET to the result. */ | |
2861 | ||
2862 | static rtx | |
2863 | mips_unspec_address_offset (rtx base, rtx offset, | |
2864 | enum mips_symbol_type symbol_type) | |
2865 | { | |
2866 | base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), | |
2867 | UNSPEC_ADDRESS_FIRST + symbol_type); | |
2868 | if (offset != const0_rtx) | |
2869 | base = gen_rtx_PLUS (Pmode, base, offset); | |
2870 | return gen_rtx_CONST (Pmode, base); | |
2871 | } | |
2872 | ||
2873 | /* Return an UNSPEC address with underlying address ADDRESS and symbol | |
2874 | type SYMBOL_TYPE. */ | |
2875 | ||
2876 | rtx | |
2877 | mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) | |
2878 | { | |
2879 | rtx base, offset; | |
2880 | ||
2881 | split_const (address, &base, &offset); | |
2882 | return mips_unspec_address_offset (base, offset, symbol_type); | |
2883 | } | |
2884 | ||
b53da244 AN |
2885 | /* If OP is an UNSPEC address, return the address to which it refers, |
2886 | otherwise return OP itself. */ | |
2887 | ||
36be1dee | 2888 | rtx |
b53da244 AN |
2889 | mips_strip_unspec_address (rtx op) |
2890 | { | |
2891 | rtx base, offset; | |
2892 | ||
2893 | split_const (op, &base, &offset); | |
2894 | if (UNSPEC_ADDRESS_P (base)) | |
0a81f074 | 2895 | op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset)); |
b53da244 AN |
2896 | return op; |
2897 | } | |
2898 | ||
7462a715 RS |
2899 | /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the |
2900 | high part to BASE and return the result. Just return BASE otherwise. | |
2901 | TEMP is as for mips_force_temporary. | |
2902 | ||
2903 | The returned expression can be used as the first operand to a LO_SUM. */ | |
2904 | ||
2905 | static rtx | |
2906 | mips_unspec_offset_high (rtx temp, rtx base, rtx addr, | |
2907 | enum mips_symbol_type symbol_type) | |
2908 | { | |
2909 | if (mips_split_p[symbol_type]) | |
2910 | { | |
2911 | addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); | |
2912 | addr = mips_force_temporary (temp, addr); | |
2913 | base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base)); | |
2914 | } | |
2915 | return base; | |
2916 | } | |
2917 | \f | |
5ca3d30c RS |
2918 | /* Return an instruction that copies $gp into register REG. We want |
2919 | GCC to treat the register's value as constant, so that its value | |
2920 | can be rematerialized on demand. */ | |
2921 | ||
2922 | static rtx | |
2923 | gen_load_const_gp (rtx reg) | |
2924 | { | |
81a478c8 | 2925 | return PMODE_INSN (gen_load_const_gp, (reg)); |
5ca3d30c RS |
2926 | } |
2927 | ||
65239d20 RS |
2928 | /* Return a pseudo register that contains the value of $gp throughout |
2929 | the current function. Such registers are needed by MIPS16 functions, | |
2930 | for which $gp itself is not a valid base register or addition operand. */ | |
ab77a036 RS |
2931 | |
2932 | static rtx | |
2933 | mips16_gp_pseudo_reg (void) | |
2934 | { | |
2935 | if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) | |
ab77a036 | 2936 | { |
c6f971f4 | 2937 | rtx_insn *scan; |
08d0963a | 2938 | |
8a7a250d RS |
2939 | cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); |
2940 | ||
08d0963a RS |
2941 | push_topmost_sequence (); |
2942 | ||
2943 | scan = get_insns (); | |
2944 | while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan))) | |
2945 | scan = NEXT_INSN (scan); | |
ab77a036 | 2946 | |
a1950df3 DM |
2947 | rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); |
2948 | rtx_insn *insn = emit_insn_after (set, scan); | |
9d12bc68 | 2949 | INSN_LOCATION (insn) = 0; |
ab77a036 | 2950 | |
ab77a036 | 2951 | pop_topmost_sequence (); |
ab77a036 RS |
2952 | } |
2953 | ||
2954 | return cfun->machine->mips16_gp_pseudo_rtx; | |
2955 | } | |
cafe096b | 2956 | |
08d0963a RS |
2957 | /* Return a base register that holds pic_offset_table_rtx. |
2958 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2959 | ||
2960 | rtx | |
2961 | mips_pic_base_register (rtx temp) | |
2962 | { | |
2963 | if (!TARGET_MIPS16) | |
2964 | return pic_offset_table_rtx; | |
2965 | ||
8a7a250d | 2966 | if (currently_expanding_to_rtl) |
08d0963a RS |
2967 | return mips16_gp_pseudo_reg (); |
2968 | ||
8a7a250d RS |
2969 | if (can_create_pseudo_p ()) |
2970 | temp = gen_reg_rtx (Pmode); | |
2971 | ||
08d0963a RS |
2972 | if (TARGET_USE_GOT) |
2973 | /* The first post-reload split exposes all references to $gp | |
2974 | (both uses and definitions). All references must remain | |
2975 | explicit after that point. | |
2976 | ||
2977 | It is safe to introduce uses of $gp at any time, so for | |
2978 | simplicity, we do that before the split too. */ | |
2979 | mips_emit_move (temp, pic_offset_table_rtx); | |
2980 | else | |
2981 | emit_insn (gen_load_const_gp (temp)); | |
2982 | return temp; | |
2983 | } | |
2984 | ||
b53da244 AN |
2985 | /* Return the RHS of a load_call<mode> insn. */ |
2986 | ||
2987 | static rtx | |
2988 | mips_unspec_call (rtx reg, rtx symbol) | |
2989 | { | |
2990 | rtvec vec; | |
2991 | ||
2992 | vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM)); | |
2993 | return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL); | |
2994 | } | |
2995 | ||
2996 | /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol | |
2997 | reference. Return NULL_RTX otherwise. */ | |
2998 | ||
2999 | static rtx | |
3000 | mips_strip_unspec_call (rtx src) | |
3001 | { | |
3002 | if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL) | |
3003 | return mips_strip_unspec_address (XVECEXP (src, 0, 1)); | |
3004 | return NULL_RTX; | |
3005 | } | |
3006 | ||
08d0963a RS |
3007 | /* Create and return a GOT reference of type TYPE for address ADDR. |
3008 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
3009 | ||
3010 | rtx | |
3011 | mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type) | |
3012 | { | |
3013 | rtx base, high, lo_sum_symbol; | |
3014 | ||
3015 | base = mips_pic_base_register (temp); | |
3016 | ||
3017 | /* If we used the temporary register to load $gp, we can't use | |
3018 | it for the high part as well. */ | |
3019 | if (temp != NULL && reg_overlap_mentioned_p (base, temp)) | |
3020 | temp = NULL; | |
3021 | ||
3022 | high = mips_unspec_offset_high (temp, base, addr, type); | |
3023 | lo_sum_symbol = mips_unspec_address (addr, type); | |
3024 | ||
3025 | if (type == SYMBOL_GOTOFF_CALL) | |
b53da244 | 3026 | return mips_unspec_call (high, lo_sum_symbol); |
08d0963a | 3027 | else |
81a478c8 | 3028 | return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol)); |
08d0963a RS |
3029 | } |
3030 | ||
390ea488 RS |
3031 | /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise |
3032 | it appears in a MEM of that mode. Return true if ADDR is a legitimate | |
08d0963a RS |
3033 | constant in that context and can be split into high and low parts. |
3034 | If so, and if LOW_OUT is nonnull, emit the high part and store the | |
3035 | low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. | |
cafe096b | 3036 | |
390ea488 | 3037 | TEMP is as for mips_force_temporary and is used to load the high |
08d0963a RS |
3038 | part into a register. |
3039 | ||
3040 | When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be | |
3041 | a legitimize SET_SRC for an .md pattern, otherwise the low part | |
3042 | is guaranteed to be a legitimate address for mode MODE. */ | |
390ea488 RS |
3043 | |
3044 | bool | |
ef4bddc2 | 3045 | mips_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) |
cafe096b | 3046 | { |
390ea488 RS |
3047 | enum mips_symbol_context context; |
3048 | enum mips_symbol_type symbol_type; | |
108b61d5 | 3049 | rtx high; |
cafe096b | 3050 | |
390ea488 RS |
3051 | context = (mode == MAX_MACHINE_MODE |
3052 | ? SYMBOL_CONTEXT_LEA | |
3053 | : SYMBOL_CONTEXT_MEM); | |
08d0963a | 3054 | if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA) |
1732457d | 3055 | { |
08d0963a RS |
3056 | addr = XEXP (addr, 0); |
3057 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
3058 | && mips_symbol_insns (symbol_type, mode) > 0 | |
3059 | && mips_split_hi_p[symbol_type]) | |
390ea488 | 3060 | { |
08d0963a RS |
3061 | if (low_out) |
3062 | switch (symbol_type) | |
3063 | { | |
3064 | case SYMBOL_GOT_PAGE_OFST: | |
3065 | /* The high part of a page/ofst pair is loaded from the GOT. */ | |
3066 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE); | |
3067 | break; | |
3068 | ||
3069 | default: | |
3070 | gcc_unreachable (); | |
3071 | } | |
3072 | return true; | |
390ea488 | 3073 | } |
08d0963a RS |
3074 | } |
3075 | else | |
3076 | { | |
3077 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
3078 | && mips_symbol_insns (symbol_type, mode) > 0 | |
3079 | && mips_split_p[symbol_type]) | |
390ea488 | 3080 | { |
08d0963a RS |
3081 | if (low_out) |
3082 | switch (symbol_type) | |
3083 | { | |
3084 | case SYMBOL_GOT_DISP: | |
3085 | /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */ | |
3086 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP); | |
3087 | break; | |
3088 | ||
3089 | case SYMBOL_GP_RELATIVE: | |
3090 | high = mips_pic_base_register (temp); | |
3091 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
3092 | break; | |
3093 | ||
3094 | default: | |
3095 | high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); | |
3096 | high = mips_force_temporary (temp, high); | |
3097 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
3098 | break; | |
3099 | } | |
3100 | return true; | |
390ea488 | 3101 | } |
1732457d | 3102 | } |
08d0963a | 3103 | return false; |
cafe096b EC |
3104 | } |
3105 | ||
b73ce23b RS |
3106 | /* Return a legitimate address for REG + OFFSET. TEMP is as for |
3107 | mips_force_temporary; it is only needed when OFFSET is not a | |
3108 | SMALL_OPERAND. */ | |
cafe096b | 3109 | |
108b61d5 | 3110 | static rtx |
b73ce23b | 3111 | mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) |
cafe096b | 3112 | { |
108b61d5 | 3113 | if (!SMALL_OPERAND (offset)) |
b73ce23b RS |
3114 | { |
3115 | rtx high; | |
65239d20 | 3116 | |
b73ce23b RS |
3117 | if (TARGET_MIPS16) |
3118 | { | |
3119 | /* Load the full offset into a register so that we can use | |
3120 | an unextended instruction for the address itself. */ | |
3121 | high = GEN_INT (offset); | |
3122 | offset = 0; | |
3123 | } | |
3124 | else | |
3125 | { | |
6d8f135b JW |
3126 | /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. |
3127 | The addition inside the macro CONST_HIGH_PART may cause an | |
3128 | overflow, so we need to force a sign-extension check. */ | |
3129 | high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); | |
b73ce23b RS |
3130 | offset = CONST_LOW_PART (offset); |
3131 | } | |
3132 | high = mips_force_temporary (temp, high); | |
3133 | reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); | |
3134 | } | |
0a81f074 | 3135 | return plus_constant (Pmode, reg, offset); |
cafe096b | 3136 | } |
65239d20 RS |
3137 | \f |
3138 | /* The __tls_get_attr symbol. */ | |
69229b81 DJ |
3139 | static GTY(()) rtx mips_tls_symbol; |
3140 | ||
65239d20 RS |
3141 | /* Return an instruction sequence that calls __tls_get_addr. SYM is |
3142 | the TLS symbol we are referencing and TYPE is the symbol type to use | |
3143 | (either global dynamic or local dynamic). V0 is an RTX for the | |
3144 | return value location. */ | |
3145 | ||
69229b81 DJ |
3146 | static rtx |
3147 | mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0) | |
3148 | { | |
dbc90b65 | 3149 | rtx insn, loc, a0; |
69229b81 DJ |
3150 | |
3151 | a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); | |
3152 | ||
3153 | if (!mips_tls_symbol) | |
3154 | mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
3155 | ||
3156 | loc = mips_unspec_address (sym, type); | |
3157 | ||
3158 | start_sequence (); | |
3159 | ||
3160 | emit_insn (gen_rtx_SET (Pmode, a0, | |
3161 | gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); | |
08d0963a RS |
3162 | insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol, |
3163 | const0_rtx, NULL_RTX, false); | |
becfd6e5 | 3164 | RTL_CONST_CALL_P (insn) = 1; |
69229b81 DJ |
3165 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); |
3166 | insn = get_insns (); | |
3167 | ||
3168 | end_sequence (); | |
3169 | ||
3170 | return insn; | |
3171 | } | |
3172 | ||
256f27f1 RS |
3173 | /* Return a pseudo register that contains the current thread pointer. */ |
3174 | ||
f959607b CLT |
3175 | rtx |
3176 | mips_expand_thread_pointer (rtx tp) | |
256f27f1 | 3177 | { |
f959607b | 3178 | rtx fn; |
256f27f1 | 3179 | |
ddaf8125 RS |
3180 | if (TARGET_MIPS16) |
3181 | { | |
6d51cc90 RS |
3182 | if (!mips16_rdhwr_stub) |
3183 | mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub (); | |
3184 | fn = mips16_stub_call_address (mips16_rdhwr_stub); | |
ddaf8125 RS |
3185 | emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn))); |
3186 | } | |
256f27f1 | 3187 | else |
ddaf8125 | 3188 | emit_insn (PMODE_INSN (gen_tls_get_tp, (tp))); |
256f27f1 RS |
3189 | return tp; |
3190 | } | |
3191 | ||
f959607b CLT |
3192 | static rtx |
3193 | mips_get_tp (void) | |
3194 | { | |
3195 | return mips_expand_thread_pointer (gen_reg_rtx (Pmode)); | |
3196 | } | |
3197 | ||
65239d20 RS |
3198 | /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return |
3199 | its address. The return value will be both a valid address and a valid | |
3200 | SET_SRC (either a REG or a LO_SUM). */ | |
69229b81 DJ |
3201 | |
3202 | static rtx | |
3203 | mips_legitimize_tls_address (rtx loc) | |
3204 | { | |
ddaf8125 | 3205 | rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset; |
69229b81 DJ |
3206 | enum tls_model model; |
3207 | ||
69229b81 | 3208 | model = SYMBOL_REF_TLS_MODEL (loc); |
4afa41f1 RS |
3209 | /* Only TARGET_ABICALLS code can have more than one module; other |
3210 | code must be be static and should not use a GOT. All TLS models | |
3211 | reduce to local exec in this situation. */ | |
3212 | if (!TARGET_ABICALLS) | |
3213 | model = TLS_MODEL_LOCAL_EXEC; | |
69229b81 DJ |
3214 | |
3215 | switch (model) | |
3216 | { | |
3217 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
65239d20 | 3218 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
3219 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0); |
3220 | dest = gen_reg_rtx (Pmode); | |
3221 | emit_libcall_block (insn, dest, v0, loc); | |
3222 | break; | |
3223 | ||
3224 | case TLS_MODEL_LOCAL_DYNAMIC: | |
65239d20 | 3225 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
3226 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0); |
3227 | tmp1 = gen_reg_rtx (Pmode); | |
3228 | ||
3229 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
3230 | share the LDM result with other LD model accesses. */ | |
3231 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3232 | UNSPEC_TLS_LDM); | |
3233 | emit_libcall_block (insn, tmp1, v0, eqv); | |
3234 | ||
ddaf8125 RS |
3235 | offset = mips_unspec_address (loc, SYMBOL_DTPREL); |
3236 | if (mips_split_p[SYMBOL_DTPREL]) | |
3237 | { | |
3238 | tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL); | |
3239 | dest = gen_rtx_LO_SUM (Pmode, tmp2, offset); | |
3240 | } | |
3241 | else | |
3242 | dest = expand_binop (Pmode, add_optab, tmp1, offset, | |
3243 | 0, 0, OPTAB_DIRECT); | |
69229b81 DJ |
3244 | break; |
3245 | ||
3246 | case TLS_MODEL_INITIAL_EXEC: | |
256f27f1 | 3247 | tp = mips_get_tp (); |
69229b81 DJ |
3248 | tmp1 = gen_reg_rtx (Pmode); |
3249 | tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); | |
3250 | if (Pmode == DImode) | |
256f27f1 | 3251 | emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 3252 | else |
256f27f1 | 3253 | emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 3254 | dest = gen_reg_rtx (Pmode); |
256f27f1 | 3255 | emit_insn (gen_add3_insn (dest, tmp1, tp)); |
69229b81 DJ |
3256 | break; |
3257 | ||
3258 | case TLS_MODEL_LOCAL_EXEC: | |
ddaf8125 RS |
3259 | tmp1 = mips_get_tp (); |
3260 | offset = mips_unspec_address (loc, SYMBOL_TPREL); | |
3261 | if (mips_split_p[SYMBOL_TPREL]) | |
3262 | { | |
3263 | tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL); | |
3264 | dest = gen_rtx_LO_SUM (Pmode, tmp2, offset); | |
3265 | } | |
3266 | else | |
3267 | dest = expand_binop (Pmode, add_optab, tmp1, offset, | |
3268 | 0, 0, OPTAB_DIRECT); | |
69229b81 DJ |
3269 | break; |
3270 | ||
3271 | default: | |
107a4b41 | 3272 | gcc_unreachable (); |
69229b81 | 3273 | } |
69229b81 DJ |
3274 | return dest; |
3275 | } | |
65239d20 | 3276 | \f |
a90c0245 RS |
3277 | /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16, |
3278 | using a stub. */ | |
3279 | ||
3280 | void | |
3281 | mips16_expand_get_fcsr (rtx target) | |
3282 | { | |
3283 | if (!mips16_get_fcsr_stub) | |
3284 | mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub (); | |
3285 | rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub); | |
3286 | emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn))); | |
3287 | emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM)); | |
3288 | } | |
3289 | ||
3290 | /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */ | |
3291 | ||
3292 | void | |
3293 | mips16_expand_set_fcsr (rtx newval) | |
3294 | { | |
3295 | if (!mips16_set_fcsr_stub) | |
3296 | mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub (); | |
3297 | rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub); | |
3298 | emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval); | |
3299 | emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn))); | |
3300 | } | |
3301 | \f | |
fa21a761 RS |
3302 | /* If X is not a valid address for mode MODE, force it into a register. */ |
3303 | ||
3304 | static rtx | |
ef4bddc2 | 3305 | mips_force_address (rtx x, machine_mode mode) |
fa21a761 RS |
3306 | { |
3307 | if (!mips_legitimate_address_p (mode, x, false)) | |
3308 | x = force_reg (Pmode, x); | |
3309 | return x; | |
3310 | } | |
3311 | ||
506d7b68 | 3312 | /* This function is used to implement LEGITIMIZE_ADDRESS. If X can |
cafe096b | 3313 | be legitimized in a way that the generic machinery might not expect, |
506d7b68 | 3314 | return a new address, otherwise return NULL. MODE is the mode of |
cafe096b | 3315 | the memory being accessed. */ |
910628b8 | 3316 | |
506d7b68 PB |
3317 | static rtx |
3318 | mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
ef4bddc2 | 3319 | machine_mode mode) |
7dac2f89 | 3320 | { |
fa21a761 | 3321 | rtx base, addr; |
65239d20 RS |
3322 | HOST_WIDE_INT offset; |
3323 | ||
506d7b68 PB |
3324 | if (mips_tls_symbol_p (x)) |
3325 | return mips_legitimize_tls_address (x); | |
69229b81 | 3326 | |
108b61d5 | 3327 | /* See if the address can split into a high part and a LO_SUM. */ |
506d7b68 PB |
3328 | if (mips_split_symbol (NULL, x, mode, &addr)) |
3329 | return mips_force_address (addr, mode); | |
910628b8 | 3330 | |
65239d20 | 3331 | /* Handle BASE + OFFSET using mips_add_offset. */ |
506d7b68 | 3332 | mips_split_plus (x, &base, &offset); |
65239d20 | 3333 | if (offset != 0) |
cafe096b | 3334 | { |
65239d20 RS |
3335 | if (!mips_valid_base_register_p (base, mode, false)) |
3336 | base = copy_to_mode_reg (Pmode, base); | |
fa21a761 | 3337 | addr = mips_add_offset (NULL, base, offset); |
506d7b68 | 3338 | return mips_force_address (addr, mode); |
cafe096b | 3339 | } |
506d7b68 PB |
3340 | |
3341 | return x; | |
50c0000c | 3342 | } |
c94c9817 | 3343 | |
65239d20 | 3344 | /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */ |
b259a9a6 | 3345 | |
ea462dd0 | 3346 | void |
65239d20 | 3347 | mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) |
b259a9a6 RS |
3348 | { |
3349 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; | |
ef4bddc2 | 3350 | machine_mode mode; |
65239d20 | 3351 | unsigned int i, num_ops; |
b259a9a6 RS |
3352 | rtx x; |
3353 | ||
3354 | mode = GET_MODE (dest); | |
65239d20 | 3355 | num_ops = mips_build_integer (codes, value); |
b259a9a6 RS |
3356 | |
3357 | /* Apply each binary operation to X. Invariant: X is a legitimate | |
3358 | source operand for a SET pattern. */ | |
3359 | x = GEN_INT (codes[0].value); | |
65239d20 | 3360 | for (i = 1; i < num_ops; i++) |
b259a9a6 | 3361 | { |
b3a13419 | 3362 | if (!can_create_pseudo_p ()) |
ea462dd0 RS |
3363 | { |
3364 | emit_insn (gen_rtx_SET (VOIDmode, temp, x)); | |
3365 | x = temp; | |
3366 | } | |
b259a9a6 RS |
3367 | else |
3368 | x = force_reg (mode, x); | |
3369 | x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); | |
3370 | } | |
3371 | ||
3372 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
3373 | } | |
3374 | ||
cafe096b EC |
3375 | /* Subroutine of mips_legitimize_move. Move constant SRC into register |
3376 | DEST given that SRC satisfies immediate_operand but doesn't satisfy | |
3377 | move_operand. */ | |
3378 | ||
3379 | static void | |
ef4bddc2 | 3380 | mips_legitimize_const_move (machine_mode mode, rtx dest, rtx src) |
c94c9817 | 3381 | { |
7ffb5e78 | 3382 | rtx base, offset; |
cafe096b | 3383 | |
ea462dd0 RS |
3384 | /* Split moves of big integers into smaller pieces. */ |
3385 | if (splittable_const_int_operand (src, mode)) | |
b259a9a6 | 3386 | { |
ea462dd0 | 3387 | mips_move_integer (dest, dest, INTVAL (src)); |
b259a9a6 RS |
3388 | return; |
3389 | } | |
3390 | ||
ea462dd0 | 3391 | /* Split moves of symbolic constants into high/low pairs. */ |
390ea488 | 3392 | if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) |
69229b81 | 3393 | { |
390ea488 | 3394 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); |
69229b81 DJ |
3395 | return; |
3396 | } | |
3397 | ||
65239d20 RS |
3398 | /* Generate the appropriate access sequences for TLS symbols. */ |
3399 | if (mips_tls_symbol_p (src)) | |
cafe096b | 3400 | { |
51e7252a | 3401 | mips_emit_move (dest, mips_legitimize_tls_address (src)); |
cafe096b EC |
3402 | return; |
3403 | } | |
3404 | ||
edede024 SL |
3405 | /* If we have (const (plus symbol offset)), and that expression cannot |
3406 | be forced into memory, load the symbol first and add in the offset. | |
3407 | In non-MIPS16 mode, prefer to do this even if the constant _can_ be | |
3408 | forced into memory, as it usually produces better code. */ | |
7ffb5e78 | 3409 | split_const (src, &base, &offset); |
edede024 | 3410 | if (offset != const0_rtx |
fbbf66e7 | 3411 | && (targetm.cannot_force_const_mem (mode, src) |
edede024 | 3412 | || (!TARGET_MIPS16 && can_create_pseudo_p ()))) |
cafe096b | 3413 | { |
108b61d5 | 3414 | base = mips_force_temporary (dest, base); |
65239d20 | 3415 | mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset))); |
cafe096b EC |
3416 | return; |
3417 | } | |
3418 | ||
3419 | src = force_const_mem (mode, src); | |
3420 | ||
3421 | /* When using explicit relocs, constant pool references are sometimes | |
108b61d5 | 3422 | not legitimate addresses. */ |
390ea488 | 3423 | mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); |
51e7252a | 3424 | mips_emit_move (dest, src); |
c94c9817 MM |
3425 | } |
3426 | ||
65239d20 | 3427 | /* If (set DEST SRC) is not a valid move instruction, emit an equivalent |
cafe096b EC |
3428 | sequence that is valid. */ |
3429 | ||
3430 | bool | |
ef4bddc2 | 3431 | mips_legitimize_move (machine_mode mode, rtx dest, rtx src) |
c94c9817 | 3432 | { |
cafe096b | 3433 | if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) |
7dac2f89 | 3434 | { |
51e7252a | 3435 | mips_emit_move (dest, force_reg (mode, src)); |
cafe096b | 3436 | return true; |
7dac2f89 EC |
3437 | } |
3438 | ||
fc31c7ca | 3439 | /* We need to deal with constants that would be legitimate |
65239d20 | 3440 | immediate_operands but aren't legitimate move_operands. */ |
fc31c7ca | 3441 | if (CONSTANT_P (src) && !move_operand (src, mode)) |
cafe096b EC |
3442 | { |
3443 | mips_legitimize_const_move (mode, dest, src); | |
3444 | set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); | |
3445 | return true; | |
3446 | } | |
3447 | return false; | |
3448 | } | |
cee98a59 | 3449 | \f |
65239d20 RS |
3450 | /* Return true if value X in context CONTEXT is a small-data address |
3451 | that can be rewritten as a LO_SUM. */ | |
ab77a036 RS |
3452 | |
3453 | static bool | |
3454 | mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context) | |
3455 | { | |
3456 | enum mips_symbol_type symbol_type; | |
3457 | ||
08d0963a RS |
3458 | return (mips_lo_relocs[SYMBOL_GP_RELATIVE] |
3459 | && !mips_split_p[SYMBOL_GP_RELATIVE] | |
ab77a036 RS |
3460 | && mips_symbolic_constant_p (x, context, &symbol_type) |
3461 | && symbol_type == SYMBOL_GP_RELATIVE); | |
3462 | } | |
3463 | ||
187804d4 RS |
3464 | /* Return true if OP refers to small data symbols directly, not through |
3465 | a LO_SUM. CONTEXT is the context in which X appears. */ | |
ab77a036 RS |
3466 | |
3467 | static int | |
187804d4 | 3468 | mips_small_data_pattern_1 (rtx x, enum mips_symbol_context context) |
ab77a036 | 3469 | { |
187804d4 RS |
3470 | subrtx_var_iterator::array_type array; |
3471 | FOR_EACH_SUBRTX_VAR (iter, array, x, ALL) | |
ab77a036 | 3472 | { |
187804d4 RS |
3473 | rtx x = *iter; |
3474 | ||
3475 | /* Ignore things like "g" constraints in asms. We make no particular | |
3476 | guarantee about which symbolic constants are acceptable as asm operands | |
3477 | versus which must be forced into a GPR. */ | |
3478 | if (GET_CODE (x) == LO_SUM || GET_CODE (x) == ASM_OPERANDS) | |
3479 | iter.skip_subrtxes (); | |
3480 | else if (MEM_P (x)) | |
3481 | { | |
3482 | if (mips_small_data_pattern_1 (XEXP (x, 0), SYMBOL_CONTEXT_MEM)) | |
3483 | return true; | |
3484 | iter.skip_subrtxes (); | |
3485 | } | |
3486 | else if (mips_rewrite_small_data_p (x, context)) | |
3487 | return true; | |
ab77a036 | 3488 | } |
187804d4 | 3489 | return false; |
ab77a036 RS |
3490 | } |
3491 | ||
3492 | /* Return true if OP refers to small data symbols directly, not through | |
3493 | a LO_SUM. */ | |
3494 | ||
3495 | bool | |
3496 | mips_small_data_pattern_p (rtx op) | |
3497 | { | |
187804d4 | 3498 | return mips_small_data_pattern_1 (op, SYMBOL_CONTEXT_LEA); |
ab77a036 | 3499 | } |
65239d20 | 3500 | |
3854efe8 RS |
3501 | /* Rewrite *LOC so that it refers to small data using explicit |
3502 | relocations. CONTEXT is the context in which *LOC appears. */ | |
ab77a036 | 3503 | |
3854efe8 RS |
3504 | static void |
3505 | mips_rewrite_small_data_1 (rtx *loc, enum mips_symbol_context context) | |
ab77a036 | 3506 | { |
3854efe8 RS |
3507 | subrtx_ptr_iterator::array_type array; |
3508 | FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL) | |
ab77a036 | 3509 | { |
3854efe8 RS |
3510 | rtx *loc = *iter; |
3511 | if (MEM_P (*loc)) | |
3512 | { | |
3513 | mips_rewrite_small_data_1 (&XEXP (*loc, 0), SYMBOL_CONTEXT_MEM); | |
3514 | iter.skip_subrtxes (); | |
3515 | } | |
3516 | else if (mips_rewrite_small_data_p (*loc, context)) | |
3517 | { | |
3518 | *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc); | |
3519 | iter.skip_subrtxes (); | |
3520 | } | |
3521 | else if (GET_CODE (*loc) == LO_SUM) | |
3522 | iter.skip_subrtxes (); | |
ab77a036 | 3523 | } |
ab77a036 RS |
3524 | } |
3525 | ||
65239d20 RS |
3526 | /* Rewrite instruction pattern PATTERN so that it refers to small data |
3527 | using explicit relocations. */ | |
ab77a036 RS |
3528 | |
3529 | rtx | |
65239d20 | 3530 | mips_rewrite_small_data (rtx pattern) |
ab77a036 | 3531 | { |
65239d20 | 3532 | pattern = copy_insn (pattern); |
3854efe8 | 3533 | mips_rewrite_small_data_1 (&pattern, SYMBOL_CONTEXT_LEA); |
65239d20 | 3534 | return pattern; |
ab77a036 RS |
3535 | } |
3536 | \f | |
8144a1a8 RS |
3537 | /* The cost of loading values from the constant pool. It should be |
3538 | larger than the cost of any constant we want to synthesize inline. */ | |
8144a1a8 RS |
3539 | #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8) |
3540 | ||
3541 | /* Return the cost of X when used as an operand to the MIPS16 instruction | |
3542 | that implements CODE. Return -1 if there is no such instruction, or if | |
3543 | X is not a valid immediate operand for it. */ | |
3544 | ||
3545 | static int | |
3546 | mips16_constant_cost (int code, HOST_WIDE_INT x) | |
3547 | { | |
3548 | switch (code) | |
3549 | { | |
3550 | case ASHIFT: | |
3551 | case ASHIFTRT: | |
3552 | case LSHIFTRT: | |
3553 | /* Shifts by between 1 and 8 bits (inclusive) are unextended, | |
3554 | other shifts are extended. The shift patterns truncate the shift | |
3555 | count to the right size, so there are no out-of-range values. */ | |
3556 | if (IN_RANGE (x, 1, 8)) | |
3557 | return 0; | |
3558 | return COSTS_N_INSNS (1); | |
3559 | ||
3560 | case PLUS: | |
3561 | if (IN_RANGE (x, -128, 127)) | |
3562 | return 0; | |
3563 | if (SMALL_OPERAND (x)) | |
3564 | return COSTS_N_INSNS (1); | |
3565 | return -1; | |
3566 | ||
3567 | case LEU: | |
3568 | /* Like LE, but reject the always-true case. */ | |
3569 | if (x == -1) | |
3570 | return -1; | |
3571 | case LE: | |
3572 | /* We add 1 to the immediate and use SLT. */ | |
3573 | x += 1; | |
3574 | case XOR: | |
3575 | /* We can use CMPI for an xor with an unsigned 16-bit X. */ | |
3576 | case LT: | |
3577 | case LTU: | |
3578 | if (IN_RANGE (x, 0, 255)) | |
3579 | return 0; | |
3580 | if (SMALL_OPERAND_UNSIGNED (x)) | |
3581 | return COSTS_N_INSNS (1); | |
3582 | return -1; | |
3583 | ||
3584 | case EQ: | |
3585 | case NE: | |
3586 | /* Equality comparisons with 0 are cheap. */ | |
3587 | if (x == 0) | |
3588 | return 0; | |
3589 | return -1; | |
3590 | ||
3591 | default: | |
3592 | return -1; | |
3593 | } | |
3594 | } | |
3595 | ||
3596 | /* Return true if there is a non-MIPS16 instruction that implements CODE | |
3597 | and if that instruction accepts X as an immediate operand. */ | |
3598 | ||
3599 | static int | |
3600 | mips_immediate_operand_p (int code, HOST_WIDE_INT x) | |
3601 | { | |
3602 | switch (code) | |
3603 | { | |
3604 | case ASHIFT: | |
3605 | case ASHIFTRT: | |
3606 | case LSHIFTRT: | |
3607 | /* All shift counts are truncated to a valid constant. */ | |
3608 | return true; | |
3609 | ||
3610 | case ROTATE: | |
3611 | case ROTATERT: | |
3612 | /* Likewise rotates, if the target supports rotates at all. */ | |
3613 | return ISA_HAS_ROR; | |
3614 | ||
3615 | case AND: | |
3616 | case IOR: | |
3617 | case XOR: | |
3618 | /* These instructions take 16-bit unsigned immediates. */ | |
3619 | return SMALL_OPERAND_UNSIGNED (x); | |
3620 | ||
3621 | case PLUS: | |
3622 | case LT: | |
3623 | case LTU: | |
3624 | /* These instructions take 16-bit signed immediates. */ | |
3625 | return SMALL_OPERAND (x); | |
3626 | ||
3627 | case EQ: | |
3628 | case NE: | |
3629 | case GT: | |
3630 | case GTU: | |
3631 | /* The "immediate" forms of these instructions are really | |
3632 | implemented as comparisons with register 0. */ | |
3633 | return x == 0; | |
3634 | ||
3635 | case GE: | |
3636 | case GEU: | |
3637 | /* Likewise, meaning that the only valid immediate operand is 1. */ | |
3638 | return x == 1; | |
3639 | ||
3640 | case LE: | |
3641 | /* We add 1 to the immediate and use SLT. */ | |
3642 | return SMALL_OPERAND (x + 1); | |
3643 | ||
3644 | case LEU: | |
3645 | /* Likewise SLTU, but reject the always-true case. */ | |
3646 | return SMALL_OPERAND (x + 1) && x + 1 != 0; | |
3647 | ||
3648 | case SIGN_EXTRACT: | |
3649 | case ZERO_EXTRACT: | |
3650 | /* The bit position and size are immediate operands. */ | |
3651 | return ISA_HAS_EXT_INS; | |
3652 | ||
3653 | default: | |
3654 | /* By default assume that $0 can be used for 0. */ | |
3655 | return x == 0; | |
3656 | } | |
3657 | } | |
3658 | ||
3659 | /* Return the cost of binary operation X, given that the instruction | |
3660 | sequence for a word-sized or smaller operation has cost SINGLE_COST | |
53d66977 AN |
3661 | and that the sequence of a double-word operation has cost DOUBLE_COST. |
3662 | If SPEED is true, optimize for speed otherwise optimize for size. */ | |
8144a1a8 RS |
3663 | |
3664 | static int | |
53d66977 | 3665 | mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) |
8144a1a8 RS |
3666 | { |
3667 | int cost; | |
3668 | ||
3669 | if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) | |
3670 | cost = double_cost; | |
3671 | else | |
3672 | cost = single_cost; | |
3673 | return (cost | |
5e8f01f4 | 3674 | + set_src_cost (XEXP (x, 0), speed) |
68f932c4 | 3675 | + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed)); |
8144a1a8 RS |
3676 | } |
3677 | ||
3678 | /* Return the cost of floating-point multiplications of mode MODE. */ | |
3679 | ||
3680 | static int | |
ef4bddc2 | 3681 | mips_fp_mult_cost (machine_mode mode) |
8144a1a8 RS |
3682 | { |
3683 | return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; | |
3684 | } | |
3685 | ||
3686 | /* Return the cost of floating-point divisions of mode MODE. */ | |
3687 | ||
3688 | static int | |
ef4bddc2 | 3689 | mips_fp_div_cost (machine_mode mode) |
8144a1a8 RS |
3690 | { |
3691 | return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; | |
3692 | } | |
3693 | ||
3694 | /* Return the cost of sign-extending OP to mode MODE, not including the | |
3695 | cost of OP itself. */ | |
3696 | ||
3697 | static int | |
ef4bddc2 | 3698 | mips_sign_extend_cost (machine_mode mode, rtx op) |
8144a1a8 RS |
3699 | { |
3700 | if (MEM_P (op)) | |
3701 | /* Extended loads are as cheap as unextended ones. */ | |
3702 | return 0; | |
3703 | ||
3704 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3705 | /* A sign extension from SImode to DImode in 64-bit mode is free. */ | |
3706 | return 0; | |
3707 | ||
3708 | if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E) | |
3709 | /* We can use SEB or SEH. */ | |
3710 | return COSTS_N_INSNS (1); | |
3711 | ||
3712 | /* We need to use a shift left and a shift right. */ | |
3713 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3714 | } | |
3715 | ||
3716 | /* Return the cost of zero-extending OP to mode MODE, not including the | |
3717 | cost of OP itself. */ | |
3718 | ||
3719 | static int | |
ef4bddc2 | 3720 | mips_zero_extend_cost (machine_mode mode, rtx op) |
8144a1a8 RS |
3721 | { |
3722 | if (MEM_P (op)) | |
3723 | /* Extended loads are as cheap as unextended ones. */ | |
3724 | return 0; | |
3725 | ||
3726 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3727 | /* We need a shift left by 32 bits and a shift right by 32 bits. */ | |
3728 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3729 | ||
3730 | if (GENERATE_MIPS16E) | |
3731 | /* We can use ZEB or ZEH. */ | |
3732 | return COSTS_N_INSNS (1); | |
3733 | ||
3734 | if (TARGET_MIPS16) | |
3735 | /* We need to load 0xff or 0xffff into a register and use AND. */ | |
3736 | return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3); | |
3737 | ||
3738 | /* We can use ANDI. */ | |
3739 | return COSTS_N_INSNS (1); | |
3740 | } | |
3741 | ||
91000c66 RS |
3742 | /* Return the cost of moving between two registers of mode MODE, |
3743 | assuming that the move will be in pieces of at most UNITS bytes. */ | |
3744 | ||
3745 | static int | |
ef4bddc2 | 3746 | mips_set_reg_reg_piece_cost (machine_mode mode, unsigned int units) |
91000c66 RS |
3747 | { |
3748 | return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units); | |
3749 | } | |
3750 | ||
3751 | /* Return the cost of moving between two registers of mode MODE. */ | |
3752 | ||
3753 | static int | |
ef4bddc2 | 3754 | mips_set_reg_reg_cost (machine_mode mode) |
91000c66 RS |
3755 | { |
3756 | switch (GET_MODE_CLASS (mode)) | |
3757 | { | |
3758 | case MODE_CC: | |
3759 | return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode)); | |
3760 | ||
3761 | case MODE_FLOAT: | |
3762 | case MODE_COMPLEX_FLOAT: | |
3763 | case MODE_VECTOR_FLOAT: | |
3764 | if (TARGET_HARD_FLOAT) | |
3765 | return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE); | |
3766 | /* Fall through */ | |
3767 | ||
3768 | default: | |
3769 | return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD); | |
3770 | } | |
3771 | } | |
3772 | ||
8144a1a8 RS |
3773 | /* Implement TARGET_RTX_COSTS. */ |
3774 | ||
cafe096b | 3775 | static bool |
68f932c4 RS |
3776 | mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
3777 | int *total, bool speed) | |
cafe096b | 3778 | { |
ef4bddc2 | 3779 | machine_mode mode = GET_MODE (x); |
c1bd2d66 | 3780 | bool float_mode_p = FLOAT_MODE_P (mode); |
8144a1a8 RS |
3781 | int cost; |
3782 | rtx addr; | |
3783 | ||
3784 | /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't | |
3785 | appear in the instruction stream, and the cost of a comparison is | |
3786 | really the cost of the branch or scc condition. At the time of | |
65239d20 | 3787 | writing, GCC only uses an explicit outer COMPARE code when optabs |
8144a1a8 RS |
3788 | is testing whether a constant is expensive enough to force into a |
3789 | register. We want optabs to pass such constants through the MIPS | |
3790 | expanders instead, so make all constants very cheap here. */ | |
3791 | if (outer_code == COMPARE) | |
3792 | { | |
3793 | gcc_assert (CONSTANT_P (x)); | |
3794 | *total = 0; | |
3795 | return true; | |
3796 | } | |
c1bd2d66 | 3797 | |
cafe096b EC |
3798 | switch (code) |
3799 | { | |
3800 | case CONST_INT: | |
8144a1a8 RS |
3801 | /* Treat *clear_upper32-style ANDs as having zero cost in the |
3802 | second operand. The cost is entirely in the first operand. | |
3803 | ||
3804 | ??? This is needed because we would otherwise try to CSE | |
3805 | the constant operand. Although that's the right thing for | |
3806 | instructions that continue to be a register operation throughout | |
3807 | compilation, it is disastrous for instructions that could | |
3808 | later be converted into a memory operation. */ | |
3809 | if (TARGET_64BIT | |
3810 | && outer_code == AND | |
3811 | && UINTVAL (x) == 0xffffffff) | |
3812 | { | |
3813 | *total = 0; | |
3814 | return true; | |
3815 | } | |
cafe096b | 3816 | |
8144a1a8 RS |
3817 | if (TARGET_MIPS16) |
3818 | { | |
3819 | cost = mips16_constant_cost (outer_code, INTVAL (x)); | |
3820 | if (cost >= 0) | |
c1bd2d66 | 3821 | { |
8144a1a8 | 3822 | *total = cost; |
c1bd2d66 EC |
3823 | return true; |
3824 | } | |
8144a1a8 RS |
3825 | } |
3826 | else | |
3827 | { | |
3828 | /* When not optimizing for size, we care more about the cost | |
3829 | of hot code, and hot code is often in a loop. If a constant | |
3830 | operand needs to be forced into a register, we will often be | |
3831 | able to hoist the constant load out of the loop, so the load | |
3832 | should not contribute to the cost. */ | |
53d66977 | 3833 | if (speed || mips_immediate_operand_p (outer_code, INTVAL (x))) |
c1bd2d66 EC |
3834 | { |
3835 | *total = 0; | |
3836 | return true; | |
3837 | } | |
3838 | } | |
8144a1a8 | 3839 | /* Fall through. */ |
cafe096b EC |
3840 | |
3841 | case CONST: | |
3842 | case SYMBOL_REF: | |
3843 | case LABEL_REF: | |
3844 | case CONST_DOUBLE: | |
206c2d7a RS |
3845 | if (force_to_mem_operand (x, VOIDmode)) |
3846 | { | |
3847 | *total = COSTS_N_INSNS (1); | |
3848 | return true; | |
3849 | } | |
8144a1a8 RS |
3850 | cost = mips_const_insns (x); |
3851 | if (cost > 0) | |
108b61d5 | 3852 | { |
8144a1a8 RS |
3853 | /* If the constant is likely to be stored in a GPR, SETs of |
3854 | single-insn constants are as cheap as register sets; we | |
3855 | never want to CSE them. | |
3856 | ||
3857 | Don't reduce the cost of storing a floating-point zero in | |
3858 | FPRs. If we have a zero in an FPR for other reasons, we | |
3859 | can get better cfg-cleanup and delayed-branch results by | |
3860 | using it consistently, rather than using $0 sometimes and | |
3861 | an FPR at other times. Also, moves between floating-point | |
3862 | registers are sometimes cheaper than (D)MTC1 $0. */ | |
3863 | if (cost == 1 | |
3864 | && outer_code == SET | |
3865 | && !(float_mode_p && TARGET_HARD_FLOAT)) | |
3866 | cost = 0; | |
3867 | /* When non-MIPS16 code loads a constant N>1 times, we rarely | |
3868 | want to CSE the constant itself. It is usually better to | |
3869 | have N copies of the last operation in the sequence and one | |
3870 | shared copy of the other operations. (Note that this is | |
3871 | not true for MIPS16 code, where the final operation in the | |
3872 | sequence is often an extended instruction.) | |
3873 | ||
3874 | Also, if we have a CONST_INT, we don't know whether it is | |
3875 | for a word or doubleword operation, so we cannot rely on | |
3876 | the result of mips_build_integer. */ | |
3877 | else if (!TARGET_MIPS16 | |
3878 | && (outer_code == SET || mode == VOIDmode)) | |
3879 | cost = 1; | |
3880 | *total = COSTS_N_INSNS (cost); | |
108b61d5 RS |
3881 | return true; |
3882 | } | |
8144a1a8 RS |
3883 | /* The value will need to be fetched from the constant pool. */ |
3884 | *total = CONSTANT_POOL_COST; | |
3885 | return true; | |
3886 | ||
3887 | case MEM: | |
3888 | /* If the address is legitimate, return the number of | |
3889 | instructions it needs. */ | |
3890 | addr = XEXP (x, 0); | |
3891 | cost = mips_address_insns (addr, mode, true); | |
3892 | if (cost > 0) | |
108b61d5 | 3893 | { |
8144a1a8 | 3894 | *total = COSTS_N_INSNS (cost + 1); |
108b61d5 RS |
3895 | return true; |
3896 | } | |
8144a1a8 | 3897 | /* Check for a scaled indexed address. */ |
770da00a AP |
3898 | if (mips_lwxs_address_p (addr) |
3899 | || mips_lx_address_p (addr, mode)) | |
8144a1a8 RS |
3900 | { |
3901 | *total = COSTS_N_INSNS (2); | |
3902 | return true; | |
3903 | } | |
3904 | /* Otherwise use the default handling. */ | |
3905 | return false; | |
cafe096b EC |
3906 | |
3907 | case FFS: | |
3908 | *total = COSTS_N_INSNS (6); | |
8144a1a8 | 3909 | return false; |
cafe096b EC |
3910 | |
3911 | case NOT: | |
8144a1a8 RS |
3912 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); |
3913 | return false; | |
cafe096b EC |
3914 | |
3915 | case AND: | |
8144a1a8 RS |
3916 | /* Check for a *clear_upper32 pattern and treat it like a zero |
3917 | extension. See the pattern's comment for details. */ | |
3918 | if (TARGET_64BIT | |
3919 | && mode == DImode | |
3920 | && CONST_INT_P (XEXP (x, 1)) | |
3921 | && UINTVAL (XEXP (x, 1)) == 0xffffffff) | |
3922 | { | |
3923 | *total = (mips_zero_extend_cost (mode, XEXP (x, 0)) | |
5e8f01f4 | 3924 | + set_src_cost (XEXP (x, 0), speed)); |
8144a1a8 RS |
3925 | return true; |
3926 | } | |
1209ab5e RS |
3927 | if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1))) |
3928 | { | |
3929 | rtx op = XEXP (x, 0); | |
3930 | if (GET_CODE (op) == ASHIFT | |
3931 | && CONST_INT_P (XEXP (op, 1)) | |
3932 | && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32)) | |
3933 | { | |
3934 | *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed); | |
3935 | return true; | |
3936 | } | |
3937 | } | |
ade97eb1 SE |
3938 | /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in |
3939 | a single instruction. */ | |
3940 | if (!TARGET_MIPS16 | |
3941 | && GET_CODE (XEXP (x, 0)) == NOT | |
3942 | && GET_CODE (XEXP (x, 1)) == NOT) | |
3943 | { | |
3944 | cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1; | |
3945 | *total = (COSTS_N_INSNS (cost) | |
3946 | + set_src_cost (XEXP (XEXP (x, 0), 0), speed) | |
3947 | + set_src_cost (XEXP (XEXP (x, 1), 0), speed)); | |
3948 | return true; | |
3949 | } | |
1209ab5e | 3950 | |
8144a1a8 RS |
3951 | /* Fall through. */ |
3952 | ||
cafe096b EC |
3953 | case IOR: |
3954 | case XOR: | |
8144a1a8 | 3955 | /* Double-word operations use two single-word operations. */ |
53d66977 AN |
3956 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2), |
3957 | speed); | |
8144a1a8 | 3958 | return true; |
cafe096b EC |
3959 | |
3960 | case ASHIFT: | |
3961 | case ASHIFTRT: | |
3962 | case LSHIFTRT: | |
8144a1a8 RS |
3963 | case ROTATE: |
3964 | case ROTATERT: | |
3965 | if (CONSTANT_P (XEXP (x, 1))) | |
53d66977 AN |
3966 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3967 | speed); | |
8144a1a8 | 3968 | else |
53d66977 AN |
3969 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12), |
3970 | speed); | |
8144a1a8 | 3971 | return true; |
cafe096b EC |
3972 | |
3973 | case ABS: | |
c1bd2d66 | 3974 | if (float_mode_p) |
8144a1a8 | 3975 | *total = mips_cost->fp_add; |
cafe096b EC |
3976 | else |
3977 | *total = COSTS_N_INSNS (4); | |
8144a1a8 | 3978 | return false; |
cafe096b EC |
3979 | |
3980 | case LO_SUM: | |
8144a1a8 RS |
3981 | /* Low-part immediates need an extended MIPS16 instruction. */ |
3982 | *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1) | |
5e8f01f4 | 3983 | + set_src_cost (XEXP (x, 0), speed)); |
8144a1a8 RS |
3984 | return true; |
3985 | ||
3986 | case LT: | |
3987 | case LTU: | |
3988 | case LE: | |
3989 | case LEU: | |
3990 | case GT: | |
3991 | case GTU: | |
3992 | case GE: | |
3993 | case GEU: | |
3994 | case EQ: | |
3995 | case NE: | |
3996 | case UNORDERED: | |
3997 | case LTGT: | |
3998 | /* Branch comparisons have VOIDmode, so use the first operand's | |
3999 | mode instead. */ | |
4000 | mode = GET_MODE (XEXP (x, 0)); | |
4001 | if (FLOAT_MODE_P (mode)) | |
4002 | { | |
4003 | *total = mips_cost->fp_add; | |
4004 | return false; | |
4005 | } | |
53d66977 AN |
4006 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
4007 | speed); | |
cafe096b EC |
4008 | return true; |
4009 | ||
cafe096b | 4010 | case MINUS: |
8144a1a8 | 4011 | if (float_mode_p |
f900a982 | 4012 | && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3) |
8144a1a8 RS |
4013 | && TARGET_FUSED_MADD |
4014 | && !HONOR_NANS (mode) | |
4015 | && !HONOR_SIGNED_ZEROS (mode)) | |
4016 | { | |
4017 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
4018 | associated patterns. */ | |
4019 | rtx op0 = XEXP (x, 0); | |
4020 | rtx op1 = XEXP (x, 1); | |
4021 | if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) | |
4022 | { | |
4023 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
4024 | + set_src_cost (XEXP (XEXP (op0, 0), 0), speed) |
4025 | + set_src_cost (XEXP (op0, 1), speed) | |
4026 | + set_src_cost (op1, speed)); | |
8144a1a8 RS |
4027 | return true; |
4028 | } | |
4029 | if (GET_CODE (op1) == MULT) | |
4030 | { | |
4031 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
4032 | + set_src_cost (op0, speed) |
4033 | + set_src_cost (XEXP (op1, 0), speed) | |
4034 | + set_src_cost (XEXP (op1, 1), speed)); | |
8144a1a8 RS |
4035 | return true; |
4036 | } | |
4037 | } | |
4038 | /* Fall through. */ | |
4039 | ||
4040 | case PLUS: | |
c1bd2d66 EC |
4041 | if (float_mode_p) |
4042 | { | |
65239d20 RS |
4043 | /* If this is part of a MADD or MSUB, treat the PLUS as |
4044 | being free. */ | |
f900a982 | 4045 | if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3) |
8144a1a8 RS |
4046 | && TARGET_FUSED_MADD |
4047 | && GET_CODE (XEXP (x, 0)) == MULT) | |
4048 | *total = 0; | |
4049 | else | |
4050 | *total = mips_cost->fp_add; | |
4051 | return false; | |
c1bd2d66 EC |
4052 | } |
4053 | ||
8144a1a8 RS |
4054 | /* Double-word operations require three single-word operations and |
4055 | an SLTU. The MIPS16 version then needs to move the result of | |
4056 | the SLTU from $24 to a MIPS16 register. */ | |
4057 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), | |
53d66977 AN |
4058 | COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4), |
4059 | speed); | |
8144a1a8 | 4060 | return true; |
cafe096b EC |
4061 | |
4062 | case NEG: | |
8144a1a8 | 4063 | if (float_mode_p |
f900a982 | 4064 | && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3) |
8144a1a8 RS |
4065 | && TARGET_FUSED_MADD |
4066 | && !HONOR_NANS (mode) | |
4067 | && HONOR_SIGNED_ZEROS (mode)) | |
4068 | { | |
4069 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
4070 | associated patterns. */ | |
4071 | rtx op = XEXP (x, 0); | |
4072 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) | |
4073 | && GET_CODE (XEXP (op, 0)) == MULT) | |
4074 | { | |
4075 | *total = (mips_fp_mult_cost (mode) | |
5e8f01f4 RS |
4076 | + set_src_cost (XEXP (XEXP (op, 0), 0), speed) |
4077 | + set_src_cost (XEXP (XEXP (op, 0), 1), speed) | |
4078 | + set_src_cost (XEXP (op, 1), speed)); | |
8144a1a8 RS |
4079 | return true; |
4080 | } | |
4081 | } | |
4082 | ||
4083 | if (float_mode_p) | |
4084 | *total = mips_cost->fp_add; | |
4085 | else | |
4086 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); | |
cafe096b EC |
4087 | return false; |
4088 | ||
4089 | case MULT: | |
8144a1a8 RS |
4090 | if (float_mode_p) |
4091 | *total = mips_fp_mult_cost (mode); | |
4092 | else if (mode == DImode && !TARGET_64BIT) | |
4093 | /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions, | |
4094 | where the mulsidi3 always includes an MFHI and an MFLO. */ | |
53d66977 AN |
4095 | *total = (speed |
4096 | ? mips_cost->int_mult_si * 3 + 6 | |
4097 | : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)); | |
4098 | else if (!speed) | |
ceb2d59f | 4099 | *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1; |
8144a1a8 | 4100 | else if (mode == DImode) |
c1bd2d66 | 4101 | *total = mips_cost->int_mult_di; |
8144a1a8 RS |
4102 | else |
4103 | *total = mips_cost->int_mult_si; | |
4104 | return false; | |
cafe096b EC |
4105 | |
4106 | case DIV: | |
8144a1a8 | 4107 | /* Check for a reciprocal. */ |
a1569a0e | 4108 | if (float_mode_p |
287c5d38 | 4109 | && ISA_HAS_FP_RECIP_RSQRT (mode) |
a1569a0e RS |
4110 | && flag_unsafe_math_optimizations |
4111 | && XEXP (x, 0) == CONST1_RTX (mode)) | |
8144a1a8 | 4112 | { |
a1569a0e RS |
4113 | if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) |
4114 | /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the | |
4115 | division as being free. */ | |
5e8f01f4 | 4116 | *total = set_src_cost (XEXP (x, 1), speed); |
a1569a0e | 4117 | else |
bbbbb16a | 4118 | *total = (mips_fp_div_cost (mode) |
5e8f01f4 | 4119 | + set_src_cost (XEXP (x, 1), speed)); |
a1569a0e | 4120 | return true; |
8144a1a8 RS |
4121 | } |
4122 | /* Fall through. */ | |
4123 | ||
4124 | case SQRT: | |
cafe096b | 4125 | case MOD: |
c1bd2d66 EC |
4126 | if (float_mode_p) |
4127 | { | |
8144a1a8 RS |
4128 | *total = mips_fp_div_cost (mode); |
4129 | return false; | |
c1bd2d66 | 4130 | } |
031a26c5 | 4131 | /* Fall through. */ |
cafe096b EC |
4132 | |
4133 | case UDIV: | |
4134 | case UMOD: | |
53d66977 | 4135 | if (!speed) |
8144a1a8 RS |
4136 | { |
4137 | /* It is our responsibility to make division by a power of 2 | |
4138 | as cheap as 2 register additions if we want the division | |
4139 | expanders to be used for such operations; see the setting | |
4140 | of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16 | |
4141 | should always produce shorter code than using | |
4142 | expand_sdiv2_pow2. */ | |
4143 | if (TARGET_MIPS16 | |
4144 | && CONST_INT_P (XEXP (x, 1)) | |
4145 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
4146 | { | |
5e8f01f4 | 4147 | *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed); |
8144a1a8 RS |
4148 | return true; |
4149 | } | |
4150 | *total = COSTS_N_INSNS (mips_idiv_insns ()); | |
4151 | } | |
4152 | else if (mode == DImode) | |
c1bd2d66 | 4153 | *total = mips_cost->int_div_di; |
cafe096b | 4154 | else |
c1bd2d66 | 4155 | *total = mips_cost->int_div_si; |
8144a1a8 | 4156 | return false; |
cafe096b EC |
4157 | |
4158 | case SIGN_EXTEND: | |
8144a1a8 RS |
4159 | *total = mips_sign_extend_cost (mode, XEXP (x, 0)); |
4160 | return false; | |
cafe096b EC |
4161 | |
4162 | case ZERO_EXTEND: | |
a1c48edc RS |
4163 | if (outer_code == SET |
4164 | && ISA_HAS_BADDU | |
3f140f32 RS |
4165 | && (GET_CODE (XEXP (x, 0)) == TRUNCATE |
4166 | || GET_CODE (XEXP (x, 0)) == SUBREG) | |
a1c48edc | 4167 | && GET_MODE (XEXP (x, 0)) == QImode |
3f140f32 | 4168 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) |
a1c48edc | 4169 | { |
3f140f32 | 4170 | *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); |
a1c48edc RS |
4171 | return true; |
4172 | } | |
8144a1a8 RS |
4173 | *total = mips_zero_extend_cost (mode, XEXP (x, 0)); |
4174 | return false; | |
cafe096b | 4175 | |
c1bd2d66 EC |
4176 | case FLOAT: |
4177 | case UNSIGNED_FLOAT: | |
4178 | case FIX: | |
4179 | case FLOAT_EXTEND: | |
4180 | case FLOAT_TRUNCATE: | |
c1bd2d66 | 4181 | *total = mips_cost->fp_add; |
8144a1a8 | 4182 | return false; |
c1bd2d66 | 4183 | |
91000c66 RS |
4184 | case SET: |
4185 | if (register_operand (SET_DEST (x), VOIDmode) | |
4186 | && reg_or_0_operand (SET_SRC (x), VOIDmode)) | |
4187 | { | |
4188 | *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x))); | |
4189 | return true; | |
4190 | } | |
4191 | return false; | |
4192 | ||
cafe096b EC |
4193 | default: |
4194 | return false; | |
4195 | } | |
4196 | } | |
4197 | ||
65239d20 | 4198 | /* Implement TARGET_ADDRESS_COST. */ |
cafe096b EC |
4199 | |
4200 | static int | |
ef4bddc2 | 4201 | mips_address_cost (rtx addr, machine_mode mode, |
b413068c OE |
4202 | addr_space_t as ATTRIBUTE_UNUSED, |
4203 | bool speed ATTRIBUTE_UNUSED) | |
cafe096b | 4204 | { |
b413068c | 4205 | return mips_address_insns (addr, mode, false); |
cafe096b | 4206 | } |
cee98a59 | 4207 | \f |
6f5a62e9 RS |
4208 | /* Information about a single instruction in a multi-instruction |
4209 | asm sequence. */ | |
4210 | struct mips_multi_member { | |
4211 | /* True if this is a label, false if it is code. */ | |
4212 | bool is_label_p; | |
4213 | ||
4214 | /* The output_asm_insn format of the instruction. */ | |
4215 | const char *format; | |
4216 | ||
4217 | /* The operands to the instruction. */ | |
4218 | rtx operands[MAX_RECOG_OPERANDS]; | |
4219 | }; | |
4220 | typedef struct mips_multi_member mips_multi_member; | |
4221 | ||
6f5a62e9 | 4222 | /* The instructions that make up the current multi-insn sequence. */ |
9771b263 | 4223 | static vec<mips_multi_member> mips_multi_members; |
6f5a62e9 RS |
4224 | |
4225 | /* How many instructions (as opposed to labels) are in the current | |
4226 | multi-insn sequence. */ | |
4227 | static unsigned int mips_multi_num_insns; | |
4228 | ||
4229 | /* Start a new multi-insn sequence. */ | |
4230 | ||
4231 | static void | |
4232 | mips_multi_start (void) | |
4233 | { | |
9771b263 | 4234 | mips_multi_members.truncate (0); |
6f5a62e9 RS |
4235 | mips_multi_num_insns = 0; |
4236 | } | |
4237 | ||
4238 | /* Add a new, uninitialized member to the current multi-insn sequence. */ | |
4239 | ||
4240 | static struct mips_multi_member * | |
4241 | mips_multi_add (void) | |
4242 | { | |
f32682ca | 4243 | mips_multi_member empty; |
9771b263 | 4244 | return mips_multi_members.safe_push (empty); |
6f5a62e9 RS |
4245 | } |
4246 | ||
4247 | /* Add a normal insn with the given asm format to the current multi-insn | |
4248 | sequence. The other arguments are a null-terminated list of operands. */ | |
4249 | ||
4250 | static void | |
4251 | mips_multi_add_insn (const char *format, ...) | |
4252 | { | |
4253 | struct mips_multi_member *member; | |
4254 | va_list ap; | |
4255 | unsigned int i; | |
4256 | rtx op; | |
4257 | ||
4258 | member = mips_multi_add (); | |
4259 | member->is_label_p = false; | |
4260 | member->format = format; | |
4261 | va_start (ap, format); | |
4262 | i = 0; | |
4263 | while ((op = va_arg (ap, rtx))) | |
4264 | member->operands[i++] = op; | |
4265 | va_end (ap); | |
4266 | mips_multi_num_insns++; | |
4267 | } | |
4268 | ||
4269 | /* Add the given label definition to the current multi-insn sequence. | |
4270 | The definition should include the colon. */ | |
4271 | ||
4272 | static void | |
4273 | mips_multi_add_label (const char *label) | |
4274 | { | |
4275 | struct mips_multi_member *member; | |
4276 | ||
4277 | member = mips_multi_add (); | |
4278 | member->is_label_p = true; | |
4279 | member->format = label; | |
4280 | } | |
4281 | ||
4282 | /* Return the index of the last member of the current multi-insn sequence. */ | |
4283 | ||
4284 | static unsigned int | |
4285 | mips_multi_last_index (void) | |
4286 | { | |
9771b263 | 4287 | return mips_multi_members.length () - 1; |
6f5a62e9 RS |
4288 | } |
4289 | ||
4290 | /* Add a copy of an existing instruction to the current multi-insn | |
4291 | sequence. I is the index of the instruction that should be copied. */ | |
4292 | ||
4293 | static void | |
4294 | mips_multi_copy_insn (unsigned int i) | |
4295 | { | |
4296 | struct mips_multi_member *member; | |
4297 | ||
4298 | member = mips_multi_add (); | |
9771b263 | 4299 | memcpy (member, &mips_multi_members[i], sizeof (*member)); |
6f5a62e9 RS |
4300 | gcc_assert (!member->is_label_p); |
4301 | } | |
4302 | ||
4303 | /* Change the operand of an existing instruction in the current | |
4304 | multi-insn sequence. I is the index of the instruction, | |
4305 | OP is the index of the operand, and X is the new value. */ | |
4306 | ||
4307 | static void | |
4308 | mips_multi_set_operand (unsigned int i, unsigned int op, rtx x) | |
4309 | { | |
9771b263 | 4310 | mips_multi_members[i].operands[op] = x; |
6f5a62e9 RS |
4311 | } |
4312 | ||
4313 | /* Write out the asm code for the current multi-insn sequence. */ | |
4314 | ||
4315 | static void | |
4316 | mips_multi_write (void) | |
4317 | { | |
4318 | struct mips_multi_member *member; | |
4319 | unsigned int i; | |
4320 | ||
9771b263 | 4321 | FOR_EACH_VEC_ELT (mips_multi_members, i, member) |
6f5a62e9 RS |
4322 | if (member->is_label_p) |
4323 | fprintf (asm_out_file, "%s\n", member->format); | |
4324 | else | |
4325 | output_asm_insn (member->format, member->operands); | |
4326 | } | |
4327 | \f | |
5b0f0db6 RS |
4328 | /* Return one word of double-word value OP, taking into account the fixed |
4329 | endianness of certain registers. HIGH_P is true to select the high part, | |
4330 | false to select the low part. */ | |
92544bdf | 4331 | |
5b0f0db6 | 4332 | rtx |
65239d20 | 4333 | mips_subword (rtx op, bool high_p) |
5b0f0db6 | 4334 | { |
0064fbe9 | 4335 | unsigned int byte, offset; |
ef4bddc2 | 4336 | machine_mode mode; |
cee98a59 | 4337 | |
5b0f0db6 RS |
4338 | mode = GET_MODE (op); |
4339 | if (mode == VOIDmode) | |
21dfc6dc | 4340 | mode = TARGET_64BIT ? TImode : DImode; |
cee98a59 | 4341 | |
5b0f0db6 RS |
4342 | if (TARGET_BIG_ENDIAN ? !high_p : high_p) |
4343 | byte = UNITS_PER_WORD; | |
4344 | else | |
4345 | byte = 0; | |
cee98a59 | 4346 | |
48156a39 | 4347 | if (FP_REG_RTX_P (op)) |
0064fbe9 RS |
4348 | { |
4349 | /* Paired FPRs are always ordered little-endian. */ | |
4350 | offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0); | |
4351 | return gen_rtx_REG (word_mode, REGNO (op) + offset); | |
4352 | } | |
cee98a59 | 4353 | |
66083422 | 4354 | if (MEM_P (op)) |
108b61d5 | 4355 | return mips_rewrite_small_data (adjust_address (op, word_mode, byte)); |
b8eb88d0 | 4356 | |
5b0f0db6 RS |
4357 | return simplify_gen_subreg (word_mode, op, mode, byte); |
4358 | } | |
cee98a59 | 4359 | |
4670abb0 RS |
4360 | /* Return true if SRC should be moved into DEST using "MULT $0, $0". |
4361 | SPLIT_TYPE is the condition under which moves should be split. */ | |
4362 | ||
4363 | static bool | |
4364 | mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type) | |
4365 | { | |
4366 | return ((split_type != SPLIT_FOR_SPEED | |
4367 | || mips_tuning_info.fast_mult_zero_zero_p) | |
4368 | && src == const0_rtx | |
4369 | && REG_P (dest) | |
4370 | && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD | |
4371 | && (ISA_HAS_DSP_MULT | |
4372 | ? ACC_REG_P (REGNO (dest)) | |
4373 | : MD_REG_P (REGNO (dest)))); | |
4374 | } | |
4375 | ||
4376 | /* Return true if a move from SRC to DEST should be split into two. | |
4377 | SPLIT_TYPE describes the split condition. */ | |
cee98a59 | 4378 | |
5b0f0db6 | 4379 | bool |
4670abb0 | 4380 | mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type) |
5b0f0db6 | 4381 | { |
4670abb0 RS |
4382 | /* Check whether the move can be done using some variant of MULT $0,$0. */ |
4383 | if (mips_mult_move_p (dest, src, split_type)) | |
5b0f0db6 | 4384 | return false; |
cee98a59 | 4385 | |
65239d20 RS |
4386 | /* FPR-to-FPR moves can be done in a single instruction, if they're |
4387 | allowed at all. */ | |
4670abb0 RS |
4388 | unsigned int size = GET_MODE_SIZE (GET_MODE (dest)); |
4389 | if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) | |
5b0f0db6 | 4390 | return false; |
cee98a59 | 4391 | |
f457938f | 4392 | /* Check for floating-point loads and stores. */ |
4670abb0 | 4393 | if (size == 8 && ISA_HAS_LDC1_SDC1) |
5b0f0db6 | 4394 | { |
66083422 | 4395 | if (FP_REG_RTX_P (dest) && MEM_P (src)) |
5b0f0db6 | 4396 | return false; |
66083422 | 4397 | if (FP_REG_RTX_P (src) && MEM_P (dest)) |
5b0f0db6 RS |
4398 | return false; |
4399 | } | |
4670abb0 RS |
4400 | |
4401 | /* Otherwise split all multiword moves. */ | |
4402 | return size > UNITS_PER_WORD; | |
5b0f0db6 | 4403 | } |
b8eb88d0 | 4404 | |
4670abb0 RS |
4405 | /* Split a move from SRC to DEST, given that mips_split_move_p holds. |
4406 | SPLIT_TYPE describes the split condition. */ | |
cee98a59 | 4407 | |
5b0f0db6 | 4408 | void |
4670abb0 | 4409 | mips_split_move (rtx dest, rtx src, enum mips_split_type split_type) |
5b0f0db6 | 4410 | { |
21dfc6dc RS |
4411 | rtx low_dest; |
4412 | ||
4670abb0 | 4413 | gcc_checking_assert (mips_split_move_p (dest, src, split_type)); |
0064fbe9 | 4414 | if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) |
5b0f0db6 | 4415 | { |
0064fbe9 RS |
4416 | if (!TARGET_64BIT && GET_MODE (dest) == DImode) |
4417 | emit_insn (gen_move_doubleword_fprdi (dest, src)); | |
4418 | else if (!TARGET_64BIT && GET_MODE (dest) == DFmode) | |
4419 | emit_insn (gen_move_doubleword_fprdf (dest, src)); | |
e5a2b69d RS |
4420 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode) |
4421 | emit_insn (gen_move_doubleword_fprv2sf (dest, src)); | |
93581857 MS |
4422 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode) |
4423 | emit_insn (gen_move_doubleword_fprv2si (dest, src)); | |
4424 | else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode) | |
4425 | emit_insn (gen_move_doubleword_fprv4hi (dest, src)); | |
4426 | else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode) | |
4427 | emit_insn (gen_move_doubleword_fprv8qi (dest, src)); | |
0064fbe9 RS |
4428 | else if (TARGET_64BIT && GET_MODE (dest) == TFmode) |
4429 | emit_insn (gen_move_doubleword_fprtf (dest, src)); | |
6f428062 | 4430 | else |
0064fbe9 | 4431 | gcc_unreachable (); |
5b0f0db6 | 4432 | } |
21dfc6dc RS |
4433 | else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) |
4434 | { | |
4435 | low_dest = mips_subword (dest, false); | |
4436 | mips_emit_move (low_dest, mips_subword (src, false)); | |
4437 | if (TARGET_64BIT) | |
4438 | emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); | |
4439 | else | |
4440 | emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); | |
4441 | } | |
4442 | else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) | |
4443 | { | |
4444 | mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); | |
4445 | if (TARGET_64BIT) | |
4446 | emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); | |
4447 | else | |
4448 | emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); | |
4449 | } | |
5b0f0db6 RS |
4450 | else |
4451 | { | |
4452 | /* The operation can be split into two normal moves. Decide in | |
4453 | which order to do them. */ | |
65239d20 | 4454 | low_dest = mips_subword (dest, false); |
66083422 | 4455 | if (REG_P (low_dest) |
5b0f0db6 | 4456 | && reg_overlap_mentioned_p (low_dest, src)) |
cee98a59 | 4457 | { |
65239d20 RS |
4458 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); |
4459 | mips_emit_move (low_dest, mips_subword (src, false)); | |
cee98a59 | 4460 | } |
5b0f0db6 | 4461 | else |
cee98a59 | 4462 | { |
65239d20 RS |
4463 | mips_emit_move (low_dest, mips_subword (src, false)); |
4464 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); | |
cee98a59 | 4465 | } |
5b0f0db6 RS |
4466 | } |
4467 | } | |
4670abb0 RS |
4468 | |
4469 | /* Return the split type for instruction INSN. */ | |
4470 | ||
4471 | static enum mips_split_type | |
4472 | mips_insn_split_type (rtx insn) | |
4473 | { | |
4474 | basic_block bb = BLOCK_FOR_INSN (insn); | |
4475 | if (bb) | |
4476 | { | |
4477 | if (optimize_bb_for_speed_p (bb)) | |
4478 | return SPLIT_FOR_SPEED; | |
4479 | else | |
4480 | return SPLIT_FOR_SIZE; | |
4481 | } | |
4482 | /* Once CFG information has been removed, we should trust the optimization | |
4483 | decisions made by previous passes and only split where necessary. */ | |
4484 | return SPLIT_IF_NECESSARY; | |
4485 | } | |
4486 | ||
4487 | /* Return true if a move from SRC to DEST in INSN should be split. */ | |
4488 | ||
4489 | bool | |
4490 | mips_split_move_insn_p (rtx dest, rtx src, rtx insn) | |
4491 | { | |
4492 | return mips_split_move_p (dest, src, mips_insn_split_type (insn)); | |
4493 | } | |
4494 | ||
4495 | /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p | |
4496 | holds. */ | |
4497 | ||
4498 | void | |
4499 | mips_split_move_insn (rtx dest, rtx src, rtx insn) | |
4500 | { | |
4501 | mips_split_move (dest, src, mips_insn_split_type (insn)); | |
4502 | } | |
5b0f0db6 RS |
4503 | \f |
4504 | /* Return the appropriate instructions to move SRC into DEST. Assume | |
4505 | that SRC is operand 1 and DEST is operand 0. */ | |
cee98a59 | 4506 | |
5b0f0db6 | 4507 | const char * |
b4966b1b | 4508 | mips_output_move (rtx dest, rtx src) |
5b0f0db6 RS |
4509 | { |
4510 | enum rtx_code dest_code, src_code; | |
ef4bddc2 | 4511 | machine_mode mode; |
c93c5160 | 4512 | enum mips_symbol_type symbol_type; |
5b0f0db6 | 4513 | bool dbl_p; |
cee98a59 | 4514 | |
5b0f0db6 RS |
4515 | dest_code = GET_CODE (dest); |
4516 | src_code = GET_CODE (src); | |
65239d20 RS |
4517 | mode = GET_MODE (dest); |
4518 | dbl_p = (GET_MODE_SIZE (mode) == 8); | |
cee98a59 | 4519 | |
4670abb0 | 4520 | if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY)) |
5b0f0db6 | 4521 | return "#"; |
910628b8 | 4522 | |
5b0f0db6 | 4523 | if ((src_code == REG && GP_REG_P (REGNO (src))) |
65239d20 | 4524 | || (!TARGET_MIPS16 && src == CONST0_RTX (mode))) |
5b0f0db6 RS |
4525 | { |
4526 | if (dest_code == REG) | |
910628b8 | 4527 | { |
5b0f0db6 | 4528 | if (GP_REG_P (REGNO (dest))) |
245115a4 | 4529 | return "move\t%0,%z1"; |
cafe096b | 4530 | |
4670abb0 RS |
4531 | if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY)) |
4532 | { | |
4533 | if (ISA_HAS_DSP_MULT) | |
4534 | return "mult\t%q0,%.,%."; | |
4535 | else | |
4536 | return "mult\t%.,%."; | |
4537 | } | |
4538 | ||
21dfc6dc RS |
4539 | /* Moves to HI are handled by special .md insns. */ |
4540 | if (REGNO (dest) == LO_REGNUM) | |
4541 | return "mtlo\t%z1"; | |
cafe096b | 4542 | |
118ea793 CF |
4543 | if (DSP_ACC_REG_P (REGNO (dest))) |
4544 | { | |
4545 | static char retval[] = "mt__\t%z1,%q0"; | |
65239d20 | 4546 | |
118ea793 CF |
4547 | retval[2] = reg_names[REGNO (dest)][4]; |
4548 | retval[3] = reg_names[REGNO (dest)][5]; | |
4549 | return retval; | |
4550 | } | |
4551 | ||
5b0f0db6 | 4552 | if (FP_REG_P (REGNO (dest))) |
65239d20 | 4553 | return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0"; |
cafe096b | 4554 | |
5b0f0db6 RS |
4555 | if (ALL_COP_REG_P (REGNO (dest))) |
4556 | { | |
4557 | static char retval[] = "dmtc_\t%z1,%0"; | |
cafe096b | 4558 | |
5b0f0db6 | 4559 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); |
65239d20 | 4560 | return dbl_p ? retval : retval + 1; |
5b0f0db6 RS |
4561 | } |
4562 | } | |
4563 | if (dest_code == MEM) | |
21dfc6dc RS |
4564 | switch (GET_MODE_SIZE (mode)) |
4565 | { | |
4566 | case 1: return "sb\t%z1,%0"; | |
4567 | case 2: return "sh\t%z1,%0"; | |
4568 | case 4: return "sw\t%z1,%0"; | |
4569 | case 8: return "sd\t%z1,%0"; | |
4570 | } | |
cee98a59 | 4571 | } |
5b0f0db6 | 4572 | if (dest_code == REG && GP_REG_P (REGNO (dest))) |
cee98a59 | 4573 | { |
5b0f0db6 | 4574 | if (src_code == REG) |
cee98a59 | 4575 | { |
21dfc6dc RS |
4576 | /* Moves from HI are handled by special .md insns. */ |
4577 | if (REGNO (src) == LO_REGNUM) | |
4578 | { | |
4579 | /* When generating VR4120 or VR4130 code, we use MACC and | |
4580 | DMACC instead of MFLO. This avoids both the normal | |
4581 | MIPS III HI/LO hazards and the errata related to | |
4582 | -mfix-vr4130. */ | |
4583 | if (ISA_HAS_MACCHI) | |
4584 | return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; | |
4585 | return "mflo\t%0"; | |
4586 | } | |
65239d20 | 4587 | |
118ea793 CF |
4588 | if (DSP_ACC_REG_P (REGNO (src))) |
4589 | { | |
4590 | static char retval[] = "mf__\t%0,%q1"; | |
65239d20 | 4591 | |
118ea793 CF |
4592 | retval[2] = reg_names[REGNO (src)][4]; |
4593 | retval[3] = reg_names[REGNO (src)][5]; | |
4594 | return retval; | |
4595 | } | |
4596 | ||
5b0f0db6 | 4597 | if (FP_REG_P (REGNO (src))) |
65239d20 | 4598 | return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1"; |
cee98a59 | 4599 | |
5b0f0db6 | 4600 | if (ALL_COP_REG_P (REGNO (src))) |
d604bca3 | 4601 | { |
5b0f0db6 | 4602 | static char retval[] = "dmfc_\t%0,%1"; |
d604bca3 | 4603 | |
5b0f0db6 | 4604 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); |
65239d20 | 4605 | return dbl_p ? retval : retval + 1; |
d604bca3 | 4606 | } |
cee98a59 MM |
4607 | } |
4608 | ||
5b0f0db6 | 4609 | if (src_code == MEM) |
21dfc6dc RS |
4610 | switch (GET_MODE_SIZE (mode)) |
4611 | { | |
4612 | case 1: return "lbu\t%0,%1"; | |
4613 | case 2: return "lhu\t%0,%1"; | |
4614 | case 4: return "lw\t%0,%1"; | |
4615 | case 8: return "ld\t%0,%1"; | |
4616 | } | |
cee98a59 | 4617 | |
5b0f0db6 | 4618 | if (src_code == CONST_INT) |
cee98a59 | 4619 | { |
65239d20 RS |
4620 | /* Don't use the X format for the operand itself, because that |
4621 | will give out-of-range numbers for 64-bit hosts and 32-bit | |
4622 | targets. */ | |
5b0f0db6 RS |
4623 | if (!TARGET_MIPS16) |
4624 | return "li\t%0,%1\t\t\t# %X1"; | |
4625 | ||
65239d20 | 4626 | if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) |
5b0f0db6 RS |
4627 | return "li\t%0,%1"; |
4628 | ||
65239d20 | 4629 | if (SMALL_OPERAND_UNSIGNED (-INTVAL (src))) |
bb732af8 | 4630 | return "#"; |
cee98a59 MM |
4631 | } |
4632 | ||
5b0f0db6 | 4633 | if (src_code == HIGH) |
c93c5160 | 4634 | return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; |
5b0f0db6 | 4635 | |
108b61d5 RS |
4636 | if (CONST_GP_P (src)) |
4637 | return "move\t%0,%1"; | |
7dac2f89 | 4638 | |
c93c5160 RS |
4639 | if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type) |
4640 | && mips_lo_relocs[symbol_type] != 0) | |
4641 | { | |
4642 | /* A signed 16-bit constant formed by applying a relocation | |
4643 | operator to a symbolic address. */ | |
4644 | gcc_assert (!mips_split_p[symbol_type]); | |
4645 | return "li\t%0,%R1"; | |
4646 | } | |
4647 | ||
108b61d5 | 4648 | if (symbolic_operand (src, VOIDmode)) |
c93c5160 RS |
4649 | { |
4650 | gcc_assert (TARGET_MIPS16 | |
4651 | ? TARGET_MIPS16_TEXT_LOADS | |
4652 | : !TARGET_EXPLICIT_RELOCS); | |
65239d20 | 4653 | return dbl_p ? "dla\t%0,%1" : "la\t%0,%1"; |
c93c5160 | 4654 | } |
cee98a59 | 4655 | } |
5b0f0db6 RS |
4656 | if (src_code == REG && FP_REG_P (REGNO (src))) |
4657 | { | |
4658 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
06a4ab70 CF |
4659 | { |
4660 | if (GET_MODE (dest) == V2SFmode) | |
4661 | return "mov.ps\t%0,%1"; | |
4662 | else | |
65239d20 | 4663 | return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1"; |
06a4ab70 | 4664 | } |
cee98a59 | 4665 | |
5b0f0db6 | 4666 | if (dest_code == MEM) |
65239d20 | 4667 | return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0"; |
5b0f0db6 RS |
4668 | } |
4669 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
cee98a59 | 4670 | { |
5b0f0db6 | 4671 | if (src_code == MEM) |
65239d20 | 4672 | return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1"; |
cee98a59 | 4673 | } |
5b0f0db6 RS |
4674 | if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM) |
4675 | { | |
4676 | static char retval[] = "l_c_\t%0,%1"; | |
cee98a59 | 4677 | |
5b0f0db6 RS |
4678 | retval[1] = (dbl_p ? 'd' : 'w'); |
4679 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); | |
4680 | return retval; | |
4681 | } | |
4682 | if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src))) | |
4683 | { | |
4684 | static char retval[] = "s_c_\t%1,%0"; | |
cee98a59 | 4685 | |
5b0f0db6 RS |
4686 | retval[1] = (dbl_p ? 'd' : 'w'); |
4687 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); | |
4688 | return retval; | |
4689 | } | |
7ad769fe | 4690 | gcc_unreachable (); |
cee98a59 | 4691 | } |
b2471838 | 4692 | \f |
65239d20 RS |
4693 | /* Return true if CMP1 is a suitable second operand for integer ordering |
4694 | test CODE. See also the *sCC patterns in mips.md. */ | |
34b650b3 | 4695 | |
a012718f | 4696 | static bool |
65239d20 | 4697 | mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) |
a012718f RS |
4698 | { |
4699 | switch (code) | |
34b650b3 | 4700 | { |
a012718f RS |
4701 | case GT: |
4702 | case GTU: | |
4703 | return reg_or_0_operand (cmp1, VOIDmode); | |
34b650b3 | 4704 | |
a012718f RS |
4705 | case GE: |
4706 | case GEU: | |
4707 | return !TARGET_MIPS16 && cmp1 == const1_rtx; | |
34b650b3 | 4708 | |
a012718f RS |
4709 | case LT: |
4710 | case LTU: | |
4711 | return arith_operand (cmp1, VOIDmode); | |
34b650b3 | 4712 | |
a012718f RS |
4713 | case LE: |
4714 | return sle_operand (cmp1, VOIDmode); | |
34b650b3 | 4715 | |
a012718f RS |
4716 | case LEU: |
4717 | return sleu_operand (cmp1, VOIDmode); | |
34b650b3 | 4718 | |
a012718f | 4719 | default: |
7ad769fe | 4720 | gcc_unreachable (); |
34b650b3 | 4721 | } |
a012718f | 4722 | } |
34b650b3 | 4723 | |
65239d20 RS |
4724 | /* Return true if *CMP1 (of mode MODE) is a valid second operand for |
4725 | integer ordering test *CODE, or if an equivalent combination can | |
4726 | be formed by adjusting *CODE and *CMP1. When returning true, update | |
4727 | *CODE and *CMP1 with the chosen code and operand, otherwise leave | |
4728 | them alone. */ | |
ecd48505 EC |
4729 | |
4730 | static bool | |
65239d20 | 4731 | mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, |
ef4bddc2 | 4732 | machine_mode mode) |
ecd48505 | 4733 | { |
213ce6f2 | 4734 | HOST_WIDE_INT plus_one; |
ecd48505 | 4735 | |
65239d20 | 4736 | if (mips_int_order_operand_ok_p (*code, *cmp1)) |
213ce6f2 | 4737 | return true; |
d8934cf1 | 4738 | |
47ac44d6 | 4739 | if (CONST_INT_P (*cmp1)) |
213ce6f2 RS |
4740 | switch (*code) |
4741 | { | |
4742 | case LE: | |
4743 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4744 | if (INTVAL (*cmp1) < plus_one) | |
4745 | { | |
4746 | *code = LT; | |
4747 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4748 | return true; | |
4749 | } | |
4750 | break; | |
4751 | ||
4752 | case LEU: | |
4753 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4754 | if (plus_one != 0) | |
4755 | { | |
4756 | *code = LTU; | |
4757 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4758 | return true; | |
4759 | } | |
4760 | break; | |
4761 | ||
4762 | default: | |
4763 | break; | |
4764 | } | |
ecd48505 | 4765 | return false; |
ecd48505 EC |
4766 | } |
4767 | ||
65239d20 | 4768 | /* Compare CMP0 and CMP1 using ordering test CODE and store the result |
5fb79e4c AN |
4769 | in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR |
4770 | is nonnull, it's OK to set TARGET to the inverse of the result and | |
4771 | flip *INVERT_PTR instead. */ | |
f5963e61 | 4772 | |
a012718f | 4773 | static void |
65239d20 | 4774 | mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, |
a012718f RS |
4775 | rtx target, rtx cmp0, rtx cmp1) |
4776 | { | |
ef4bddc2 | 4777 | machine_mode mode; |
65239d20 | 4778 | |
213ce6f2 RS |
4779 | /* First see if there is a MIPS instruction that can do this operation. |
4780 | If not, try doing the same for the inverse operation. If that also | |
4781 | fails, force CMP1 into a register and try again. */ | |
5fb79e4c | 4782 | mode = GET_MODE (cmp0); |
65239d20 | 4783 | if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) |
ecd48505 | 4784 | mips_emit_binary (code, target, cmp0, cmp1); |
bbdb5552 MM |
4785 | else |
4786 | { | |
a012718f | 4787 | enum rtx_code inv_code = reverse_condition (code); |
65239d20 | 4788 | if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode)) |
a012718f | 4789 | { |
65239d20 RS |
4790 | cmp1 = force_reg (mode, cmp1); |
4791 | mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); | |
a012718f RS |
4792 | } |
4793 | else if (invert_ptr == 0) | |
2bcb2ab3 | 4794 | { |
49bce30a RS |
4795 | rtx inv_target; |
4796 | ||
4797 | inv_target = mips_force_binary (GET_MODE (target), | |
4798 | inv_code, cmp0, cmp1); | |
a012718f | 4799 | mips_emit_binary (XOR, target, inv_target, const1_rtx); |
2bcb2ab3 GK |
4800 | } |
4801 | else | |
4802 | { | |
a012718f RS |
4803 | *invert_ptr = !*invert_ptr; |
4804 | mips_emit_binary (inv_code, target, cmp0, cmp1); | |
2bcb2ab3 | 4805 | } |
34b650b3 | 4806 | } |
a012718f | 4807 | } |
34b650b3 | 4808 | |
a012718f RS |
4809 | /* Return a register that is zero iff CMP0 and CMP1 are equal. |
4810 | The register will have the same mode as CMP0. */ | |
34b650b3 | 4811 | |
a012718f RS |
4812 | static rtx |
4813 | mips_zero_if_equal (rtx cmp0, rtx cmp1) | |
4814 | { | |
4815 | if (cmp1 == const0_rtx) | |
4816 | return cmp0; | |
2bcb2ab3 | 4817 | |
f1286257 RS |
4818 | if (uns_arith_operand (cmp1, VOIDmode)) |
4819 | return expand_binop (GET_MODE (cmp0), xor_optab, | |
4820 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); | |
4821 | ||
4822 | return expand_binop (GET_MODE (cmp0), sub_optab, | |
a012718f RS |
4823 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); |
4824 | } | |
4825 | ||
ec4fc7ed | 4826 | /* Convert *CODE into a code that can be used in a floating-point |
65239d20 | 4827 | scc instruction (C.cond.fmt). Return true if the values of |
ec4fc7ed RS |
4828 | the condition code registers will be inverted, with 0 indicating |
4829 | that the condition holds. */ | |
4830 | ||
4831 | static bool | |
65239d20 | 4832 | mips_reversed_fp_cond (enum rtx_code *code) |
ec4fc7ed RS |
4833 | { |
4834 | switch (*code) | |
4835 | { | |
4836 | case NE: | |
4837 | case LTGT: | |
4838 | case ORDERED: | |
4839 | *code = reverse_condition_maybe_unordered (*code); | |
4840 | return true; | |
4841 | ||
4842 | default: | |
4843 | return false; | |
4844 | } | |
4845 | } | |
4846 | ||
4b11e406 RS |
4847 | /* Allocate a floating-point condition-code register of mode MODE. |
4848 | ||
4849 | These condition code registers are used for certain kinds | |
4850 | of compound operation, such as compare and branches, vconds, | |
4851 | and built-in functions. At expand time, their use is entirely | |
4852 | controlled by MIPS-specific code and is entirely internal | |
4853 | to these compound operations. | |
4854 | ||
4855 | We could (and did in the past) expose condition-code values | |
4856 | as pseudo registers and leave the register allocator to pick | |
4857 | appropriate registers. The problem is that it is not practically | |
4858 | possible for the rtl optimizers to guarantee that no spills will | |
4859 | be needed, even when AVOID_CCMODE_COPIES is defined. We would | |
4860 | therefore need spill and reload sequences to handle the worst case. | |
4861 | ||
4862 | Although such sequences do exist, they are very expensive and are | |
4863 | not something we'd want to use. This is especially true of CCV2 and | |
4864 | CCV4, where all the shuffling would greatly outweigh whatever benefit | |
4865 | the vectorization itself provides. | |
4866 | ||
4867 | The main benefit of having more than one condition-code register | |
4868 | is to allow the pipelining of operations, especially those involving | |
4869 | comparisons and conditional moves. We don't really expect the | |
4870 | registers to be live for long periods, and certainly never want | |
4871 | them to be live across calls. | |
4872 | ||
4873 | Also, there should be no penalty attached to using all the available | |
4874 | registers. They are simply bits in the same underlying FPU control | |
4875 | register. | |
4876 | ||
4877 | We therefore expose the hardware registers from the outset and use | |
4878 | a simple round-robin allocation scheme. */ | |
4879 | ||
4880 | static rtx | |
ef4bddc2 | 4881 | mips_allocate_fcc (machine_mode mode) |
4b11e406 RS |
4882 | { |
4883 | unsigned int regno, count; | |
4884 | ||
4885 | gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC); | |
4886 | ||
4887 | if (mode == CCmode) | |
4888 | count = 1; | |
4889 | else if (mode == CCV2mode) | |
4890 | count = 2; | |
4891 | else if (mode == CCV4mode) | |
4892 | count = 4; | |
4893 | else | |
4894 | gcc_unreachable (); | |
4895 | ||
4896 | cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1); | |
4897 | if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST) | |
4898 | cfun->machine->next_fcc = 0; | |
4899 | regno = ST_REG_FIRST + cfun->machine->next_fcc; | |
4900 | cfun->machine->next_fcc += count; | |
4901 | return gen_rtx_REG (mode, regno); | |
4902 | } | |
4903 | ||
bb592806 | 4904 | /* Convert a comparison into something that can be used in a branch or |
f90b7a5a PB |
4905 | conditional move. On entry, *OP0 and *OP1 are the values being |
4906 | compared and *CODE is the code used to compare them. | |
bb592806 RS |
4907 | |
4908 | Update *CODE, *OP0 and *OP1 so that they describe the final comparison. | |
65239d20 | 4909 | If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible, |
bb592806 RS |
4910 | otherwise any standard branch condition can be used. The standard branch |
4911 | conditions are: | |
4912 | ||
65239d20 | 4913 | - EQ or NE between two registers. |
bb592806 RS |
4914 | - any comparison between a register and zero. */ |
4915 | ||
4916 | static void | |
4917 | mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) | |
4918 | { | |
f90b7a5a PB |
4919 | rtx cmp_op0 = *op0; |
4920 | rtx cmp_op1 = *op1; | |
4921 | ||
4922 | if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) | |
bb592806 | 4923 | { |
f90b7a5a PB |
4924 | if (!need_eq_ne_p && *op1 == const0_rtx) |
4925 | ; | |
bb592806 RS |
4926 | else if (*code == EQ || *code == NE) |
4927 | { | |
4928 | if (need_eq_ne_p) | |
4929 | { | |
f90b7a5a | 4930 | *op0 = mips_zero_if_equal (cmp_op0, cmp_op1); |
bb592806 RS |
4931 | *op1 = const0_rtx; |
4932 | } | |
4933 | else | |
f90b7a5a | 4934 | *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); |
bb592806 RS |
4935 | } |
4936 | else | |
4937 | { | |
4938 | /* The comparison needs a separate scc instruction. Store the | |
4939 | result of the scc in *OP0 and compare it against zero. */ | |
4940 | bool invert = false; | |
f90b7a5a PB |
4941 | *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); |
4942 | mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1); | |
bb592806 | 4943 | *code = (invert ? EQ : NE); |
65239d20 | 4944 | *op1 = const0_rtx; |
bb592806 RS |
4945 | } |
4946 | } | |
f90b7a5a | 4947 | else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0))) |
9fc777ad CF |
4948 | { |
4949 | *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM); | |
f90b7a5a | 4950 | mips_emit_binary (*code, *op0, cmp_op0, cmp_op1); |
9fc777ad CF |
4951 | *code = NE; |
4952 | *op1 = const0_rtx; | |
4953 | } | |
bb592806 RS |
4954 | else |
4955 | { | |
4956 | enum rtx_code cmp_code; | |
4957 | ||
65239d20 | 4958 | /* Floating-point tests use a separate C.cond.fmt comparison to |
bb592806 RS |
4959 | set a condition code register. The branch or conditional move |
4960 | will then compare that register against zero. | |
4961 | ||
4962 | Set CMP_CODE to the code of the comparison instruction and | |
4963 | *CODE to the code that the branch or move should use. */ | |
ec4fc7ed | 4964 | cmp_code = *code; |
65239d20 | 4965 | *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; |
bb592806 | 4966 | *op0 = (ISA_HAS_8CC |
4b11e406 | 4967 | ? mips_allocate_fcc (CCmode) |
bb592806 RS |
4968 | : gen_rtx_REG (CCmode, FPSW_REGNUM)); |
4969 | *op1 = const0_rtx; | |
f90b7a5a | 4970 | mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); |
bb592806 RS |
4971 | } |
4972 | } | |
4973 | \f | |
f90b7a5a PB |
4974 | /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] |
4975 | and OPERAND[3]. Store the result in OPERANDS[0]. | |
a012718f | 4976 | |
f90b7a5a PB |
4977 | On 64-bit targets, the mode of the comparison and target will always be |
4978 | SImode, thus possibly narrower than that of the comparison's operands. */ | |
34b650b3 | 4979 | |
f90b7a5a PB |
4980 | void |
4981 | mips_expand_scc (rtx operands[]) | |
a012718f | 4982 | { |
f90b7a5a PB |
4983 | rtx target = operands[0]; |
4984 | enum rtx_code code = GET_CODE (operands[1]); | |
4985 | rtx op0 = operands[2]; | |
4986 | rtx op1 = operands[3]; | |
4987 | ||
4988 | gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); | |
a012718f | 4989 | |
a012718f RS |
4990 | if (code == EQ || code == NE) |
4991 | { | |
5299815b | 4992 | if (ISA_HAS_SEQ_SNE |
f90b7a5a PB |
4993 | && reg_imm10_operand (op1, GET_MODE (op1))) |
4994 | mips_emit_binary (code, target, op0, op1); | |
5299815b AN |
4995 | else |
4996 | { | |
f90b7a5a | 4997 | rtx zie = mips_zero_if_equal (op0, op1); |
5299815b AN |
4998 | mips_emit_binary (code, target, zie, const0_rtx); |
4999 | } | |
a012718f RS |
5000 | } |
5001 | else | |
f90b7a5a | 5002 | mips_emit_int_order_test (code, 0, target, op0, op1); |
34b650b3 | 5003 | } |
8ab907e8 | 5004 | |
f90b7a5a PB |
5005 | /* Compare OPERANDS[1] with OPERANDS[2] using comparison code |
5006 | CODE and jump to OPERANDS[3] if the condition holds. */ | |
cee98a59 MM |
5007 | |
5008 | void | |
f90b7a5a | 5009 | mips_expand_conditional_branch (rtx *operands) |
cee98a59 | 5010 | { |
f90b7a5a PB |
5011 | enum rtx_code code = GET_CODE (operands[0]); |
5012 | rtx op0 = operands[1]; | |
5013 | rtx op1 = operands[2]; | |
5014 | rtx condition; | |
f5963e61 | 5015 | |
bb592806 | 5016 | mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16); |
a8c1d5f8 | 5017 | condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
f90b7a5a | 5018 | emit_jump_insn (gen_condjump (condition, operands[3])); |
b8eb88d0 | 5019 | } |
34b650b3 | 5020 | |
ec4fc7ed RS |
5021 | /* Implement: |
5022 | ||
5023 | (set temp (COND:CCV2 CMP_OP0 CMP_OP1)) | |
5024 | (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */ | |
5025 | ||
5026 | void | |
5027 | mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src, | |
5028 | enum rtx_code cond, rtx cmp_op0, rtx cmp_op1) | |
5029 | { | |
5030 | rtx cmp_result; | |
5031 | bool reversed_p; | |
5032 | ||
65239d20 | 5033 | reversed_p = mips_reversed_fp_cond (&cond); |
4b11e406 | 5034 | cmp_result = mips_allocate_fcc (CCV2mode); |
ec4fc7ed RS |
5035 | emit_insn (gen_scc_ps (cmp_result, |
5036 | gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1))); | |
5037 | if (reversed_p) | |
5038 | emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src, | |
5039 | cmp_result)); | |
5040 | else | |
5041 | emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src, | |
5042 | cmp_result)); | |
5043 | } | |
5044 | ||
f90b7a5a PB |
5045 | /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] |
5046 | if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */ | |
cee98a59 | 5047 | |
b8eb88d0 | 5048 | void |
65239d20 | 5049 | mips_expand_conditional_move (rtx *operands) |
b8eb88d0 | 5050 | { |
f90b7a5a PB |
5051 | rtx cond; |
5052 | enum rtx_code code = GET_CODE (operands[1]); | |
5053 | rtx op0 = XEXP (operands[1], 0); | |
5054 | rtx op1 = XEXP (operands[1], 1); | |
c5c76735 | 5055 | |
bb592806 | 5056 | mips_emit_compare (&code, &op0, &op1, true); |
f90b7a5a | 5057 | cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); |
bb592806 | 5058 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
65239d20 | 5059 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond, |
c5c76735 | 5060 | operands[2], operands[3]))); |
b8eb88d0 | 5061 | } |
a0b6cdee | 5062 | |
f90b7a5a | 5063 | /* Perform the comparison in COMPARISON, then trap if the condition holds. */ |
a0b6cdee GM |
5064 | |
5065 | void | |
f90b7a5a | 5066 | mips_expand_conditional_trap (rtx comparison) |
a0b6cdee GM |
5067 | { |
5068 | rtx op0, op1; | |
ef4bddc2 | 5069 | machine_mode mode; |
f90b7a5a | 5070 | enum rtx_code code; |
a0b6cdee | 5071 | |
65239d20 RS |
5072 | /* MIPS conditional trap instructions don't have GT or LE flavors, |
5073 | so we must swap the operands and convert to LT and GE respectively. */ | |
f90b7a5a | 5074 | code = GET_CODE (comparison); |
65239d20 | 5075 | switch (code) |
a0b6cdee | 5076 | { |
65239d20 RS |
5077 | case GT: |
5078 | case LE: | |
5079 | case GTU: | |
5080 | case LEU: | |
5081 | code = swap_condition (code); | |
f90b7a5a PB |
5082 | op0 = XEXP (comparison, 1); |
5083 | op1 = XEXP (comparison, 0); | |
65239d20 RS |
5084 | break; |
5085 | ||
5086 | default: | |
f90b7a5a PB |
5087 | op0 = XEXP (comparison, 0); |
5088 | op1 = XEXP (comparison, 1); | |
65239d20 | 5089 | break; |
a0b6cdee | 5090 | } |
65239d20 | 5091 | |
f90b7a5a | 5092 | mode = GET_MODE (XEXP (comparison, 0)); |
886ce862 RS |
5093 | op0 = force_reg (mode, op0); |
5094 | if (!arith_operand (op1, mode)) | |
a0b6cdee GM |
5095 | op1 = force_reg (mode, op1); |
5096 | ||
5097 | emit_insn (gen_rtx_TRAP_IF (VOIDmode, | |
65239d20 RS |
5098 | gen_rtx_fmt_ee (code, mode, op0, op1), |
5099 | const0_rtx)); | |
a0b6cdee | 5100 | } |
cee98a59 | 5101 | \f |
65239d20 | 5102 | /* Initialize *CUM for a call to a function of type FNTYPE. */ |
ab77a036 RS |
5103 | |
5104 | void | |
65239d20 | 5105 | mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype) |
9a6dfb47 | 5106 | { |
65239d20 RS |
5107 | memset (cum, 0, sizeof (*cum)); |
5108 | cum->prototype = (fntype && prototype_p (fntype)); | |
5109 | cum->gp_reg_found = (cum->prototype && stdarg_p (fntype)); | |
9a6dfb47 RS |
5110 | } |
5111 | ||
ab77a036 RS |
5112 | /* Fill INFO with information about a single argument. CUM is the |
5113 | cumulative state for earlier arguments. MODE is the mode of this | |
5114 | argument and TYPE is its type (if known). NAMED is true if this | |
5115 | is a named (fixed) argument rather than a variable one. */ | |
5116 | ||
5117 | static void | |
65239d20 | 5118 | mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum, |
ef4bddc2 | 5119 | machine_mode mode, const_tree type, bool named) |
08e7ceb3 | 5120 | { |
ab77a036 RS |
5121 | bool doubleword_aligned_p; |
5122 | unsigned int num_bytes, num_words, max_regs; | |
08e7ceb3 | 5123 | |
ab77a036 RS |
5124 | /* Work out the size of the argument. */ |
5125 | num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
5126 | num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
b85aed9e | 5127 | |
ab77a036 RS |
5128 | /* Decide whether it should go in a floating-point register, assuming |
5129 | one is free. Later code checks for availability. | |
b85aed9e | 5130 | |
ab77a036 RS |
5131 | The checks against UNITS_PER_FPVALUE handle the soft-float and |
5132 | single-float cases. */ | |
5133 | switch (mips_abi) | |
e8b7a137 | 5134 | { |
ab77a036 RS |
5135 | case ABI_EABI: |
5136 | /* The EABI conventions have traditionally been defined in terms | |
5137 | of TYPE_MODE, regardless of the actual type. */ | |
5138 | info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
7dab511c | 5139 | || mode == V2SFmode) |
ab77a036 RS |
5140 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); |
5141 | break; | |
b85aed9e | 5142 | |
ab77a036 RS |
5143 | case ABI_32: |
5144 | case ABI_O64: | |
5145 | /* Only leading floating-point scalars are passed in | |
5146 | floating-point registers. We also handle vector floats the same | |
5147 | say, which is OK because they are not covered by the standard ABI. */ | |
5148 | info->fpr_p = (!cum->gp_reg_found | |
5149 | && cum->arg_number < 2 | |
65239d20 RS |
5150 | && (type == 0 |
5151 | || SCALAR_FLOAT_TYPE_P (type) | |
ab77a036 RS |
5152 | || VECTOR_FLOAT_TYPE_P (type)) |
5153 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7dab511c | 5154 | || mode == V2SFmode) |
ab77a036 RS |
5155 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); |
5156 | break; | |
cafe096b | 5157 | |
ab77a036 RS |
5158 | case ABI_N32: |
5159 | case ABI_64: | |
65239d20 RS |
5160 | /* Scalar, complex and vector floating-point types are passed in |
5161 | floating-point registers, as long as this is a named rather | |
5162 | than a variable argument. */ | |
ab77a036 RS |
5163 | info->fpr_p = (named |
5164 | && (type == 0 || FLOAT_TYPE_P (type)) | |
5165 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5166 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
7dab511c | 5167 | || mode == V2SFmode) |
ab77a036 | 5168 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); |
3c53850d | 5169 | |
ab77a036 RS |
5170 | /* ??? According to the ABI documentation, the real and imaginary |
5171 | parts of complex floats should be passed in individual registers. | |
5172 | The real and imaginary parts of stack arguments are supposed | |
5173 | to be contiguous and there should be an extra word of padding | |
5174 | at the end. | |
cafe096b | 5175 | |
ab77a036 RS |
5176 | This has two problems. First, it makes it impossible to use a |
5177 | single "void *" va_list type, since register and stack arguments | |
5178 | are passed differently. (At the time of writing, MIPSpro cannot | |
5179 | handle complex float varargs correctly.) Second, it's unclear | |
5180 | what should happen when there is only one register free. | |
3c53850d | 5181 | |
ab77a036 RS |
5182 | For now, we assume that named complex floats should go into FPRs |
5183 | if there are two FPRs free, otherwise they should be passed in the | |
5184 | same way as a struct containing two floats. */ | |
5185 | if (info->fpr_p | |
5186 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
5187 | && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) | |
5188 | { | |
5189 | if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) | |
5190 | info->fpr_p = false; | |
5191 | else | |
5192 | num_words = 2; | |
5193 | } | |
5194 | break; | |
cafe096b | 5195 | |
ab77a036 RS |
5196 | default: |
5197 | gcc_unreachable (); | |
cafe096b | 5198 | } |
3c53850d | 5199 | |
ab77a036 | 5200 | /* See whether the argument has doubleword alignment. */ |
c2ed6cf8 NF |
5201 | doubleword_aligned_p = (mips_function_arg_boundary (mode, type) |
5202 | > BITS_PER_WORD); | |
3c53850d | 5203 | |
ab77a036 RS |
5204 | /* Set REG_OFFSET to the register count we're interested in. |
5205 | The EABI allocates the floating-point registers separately, | |
5206 | but the other ABIs allocate them like integer registers. */ | |
5207 | info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p | |
5208 | ? cum->num_fprs | |
5209 | : cum->num_gprs); | |
cafe096b | 5210 | |
ab77a036 RS |
5211 | /* Advance to an even register if the argument is doubleword-aligned. */ |
5212 | if (doubleword_aligned_p) | |
5213 | info->reg_offset += info->reg_offset & 1; | |
cafe096b | 5214 | |
ab77a036 RS |
5215 | /* Work out the offset of a stack argument. */ |
5216 | info->stack_offset = cum->stack_words; | |
5217 | if (doubleword_aligned_p) | |
5218 | info->stack_offset += info->stack_offset & 1; | |
cafe096b | 5219 | |
ab77a036 | 5220 | max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; |
f9e4a411 | 5221 | |
ab77a036 RS |
5222 | /* Partition the argument between registers and stack. */ |
5223 | info->reg_words = MIN (num_words, max_regs); | |
5224 | info->stack_words = num_words - info->reg_words; | |
5225 | } | |
f9e4a411 | 5226 | |
65239d20 RS |
5227 | /* INFO describes a register argument that has the normal format for the |
5228 | argument's mode. Return the register it uses, assuming that FPRs are | |
5229 | available if HARD_FLOAT_P. */ | |
1ec3b87b | 5230 | |
ab77a036 RS |
5231 | static unsigned int |
5232 | mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p) | |
5233 | { | |
5234 | if (!info->fpr_p || !hard_float_p) | |
5235 | return GP_ARG_FIRST + info->reg_offset; | |
5236 | else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0) | |
5237 | /* In o32, the second argument is always passed in $f14 | |
5238 | for TARGET_DOUBLE_FLOAT, regardless of whether the | |
5239 | first argument was a word or doubleword. */ | |
5240 | return FP_ARG_FIRST + 2; | |
5241 | else | |
5242 | return FP_ARG_FIRST + info->reg_offset; | |
cafe096b | 5243 | } |
d12b8c85 | 5244 | |
65239d20 RS |
5245 | /* Implement TARGET_STRICT_ARGUMENT_NAMING. */ |
5246 | ||
ab77a036 | 5247 | static bool |
d5cc9181 | 5248 | mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) |
ab77a036 RS |
5249 | { |
5250 | return !TARGET_OLDABI; | |
5251 | } | |
d12b8c85 | 5252 | |
c8717ea3 | 5253 | /* Implement TARGET_FUNCTION_ARG. */ |
d12b8c85 | 5254 | |
c8717ea3 | 5255 | static rtx |
ef4bddc2 | 5256 | mips_function_arg (cumulative_args_t cum_v, machine_mode mode, |
c8717ea3 | 5257 | const_tree type, bool named) |
d12b8c85 | 5258 | { |
d5cc9181 | 5259 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
ab77a036 | 5260 | struct mips_arg_info info; |
d12b8c85 | 5261 | |
ab77a036 | 5262 | /* We will be called with a mode of VOIDmode after the last argument |
65239d20 RS |
5263 | has been seen. Whatever we return will be passed to the call expander. |
5264 | If we need a MIPS16 fp_code, return a REG with the code stored as | |
5265 | the mode. */ | |
ab77a036 RS |
5266 | if (mode == VOIDmode) |
5267 | { | |
5268 | if (TARGET_MIPS16 && cum->fp_code != 0) | |
ef4bddc2 | 5269 | return gen_rtx_REG ((machine_mode) cum->fp_code, 0); |
ab77a036 | 5270 | else |
65239d20 | 5271 | return NULL; |
ab77a036 | 5272 | } |
d12b8c85 | 5273 | |
65239d20 | 5274 | mips_get_arg_info (&info, cum, mode, type, named); |
b2471838 | 5275 | |
ab77a036 RS |
5276 | /* Return straight away if the whole argument is passed on the stack. */ |
5277 | if (info.reg_offset == MAX_ARGS_IN_REGISTERS) | |
65239d20 | 5278 | return NULL; |
b2471838 | 5279 | |
65239d20 RS |
5280 | /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure |
5281 | contains a double in its entirety, then that 64-bit chunk is passed | |
5282 | in a floating-point register. */ | |
5283 | if (TARGET_NEWABI | |
5284 | && TARGET_HARD_FLOAT | |
5285 | && named | |
5286 | && type != 0 | |
ab77a036 | 5287 | && TREE_CODE (type) == RECORD_TYPE |
ab77a036 | 5288 | && TYPE_SIZE_UNIT (type) |
cc269bb6 | 5289 | && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type))) |
ab77a036 | 5290 | { |
ab77a036 | 5291 | tree field; |
b2471838 | 5292 | |
ab77a036 | 5293 | /* First check to see if there is any such field. */ |
910ad8de | 5294 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
ab77a036 | 5295 | if (TREE_CODE (field) == FIELD_DECL |
65239d20 | 5296 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 | 5297 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD |
9541ffee | 5298 | && tree_fits_shwi_p (bit_position (field)) |
ab77a036 RS |
5299 | && int_bit_position (field) % BITS_PER_WORD == 0) |
5300 | break; | |
cee98a59 | 5301 | |
ab77a036 RS |
5302 | if (field != 0) |
5303 | { | |
5304 | /* Now handle the special case by returning a PARALLEL | |
5305 | indicating where each 64-bit chunk goes. INFO.REG_WORDS | |
5306 | chunks are passed in registers. */ | |
5307 | unsigned int i; | |
5308 | HOST_WIDE_INT bitpos; | |
5309 | rtx ret; | |
730cf822 | 5310 | |
ab77a036 RS |
5311 | /* assign_parms checks the mode of ENTRY_PARM, so we must |
5312 | use the actual mode here. */ | |
5313 | ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); | |
cee98a59 | 5314 | |
ab77a036 RS |
5315 | bitpos = 0; |
5316 | field = TYPE_FIELDS (type); | |
5317 | for (i = 0; i < info.reg_words; i++) | |
5318 | { | |
5319 | rtx reg; | |
cee98a59 | 5320 | |
910ad8de | 5321 | for (; field; field = DECL_CHAIN (field)) |
ab77a036 RS |
5322 | if (TREE_CODE (field) == FIELD_DECL |
5323 | && int_bit_position (field) >= bitpos) | |
5324 | break; | |
cee98a59 | 5325 | |
ab77a036 RS |
5326 | if (field |
5327 | && int_bit_position (field) == bitpos | |
65239d20 | 5328 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
5329 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) |
5330 | reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); | |
5331 | else | |
5332 | reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); | |
5333 | ||
5334 | XVECEXP (ret, 0, i) | |
5335 | = gen_rtx_EXPR_LIST (VOIDmode, reg, | |
5336 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
5337 | ||
5338 | bitpos += BITS_PER_WORD; | |
5339 | } | |
5340 | return ret; | |
5341 | } | |
5342 | } | |
5343 | ||
5344 | /* Handle the n32/n64 conventions for passing complex floating-point | |
5345 | arguments in FPR pairs. The real part goes in the lower register | |
5346 | and the imaginary part goes in the upper register. */ | |
5347 | if (TARGET_NEWABI | |
5348 | && info.fpr_p | |
5349 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
cee98a59 | 5350 | { |
ab77a036 | 5351 | rtx real, imag; |
ef4bddc2 | 5352 | machine_mode inner; |
65239d20 | 5353 | unsigned int regno; |
ab77a036 RS |
5354 | |
5355 | inner = GET_MODE_INNER (mode); | |
65239d20 | 5356 | regno = FP_ARG_FIRST + info.reg_offset; |
ab77a036 RS |
5357 | if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) |
5358 | { | |
5359 | /* Real part in registers, imaginary part on stack. */ | |
5360 | gcc_assert (info.stack_words == info.reg_words); | |
65239d20 | 5361 | return gen_rtx_REG (inner, regno); |
ab77a036 | 5362 | } |
e0ec4c3b RS |
5363 | else |
5364 | { | |
ab77a036 RS |
5365 | gcc_assert (info.stack_words == 0); |
5366 | real = gen_rtx_EXPR_LIST (VOIDmode, | |
65239d20 | 5367 | gen_rtx_REG (inner, regno), |
ab77a036 RS |
5368 | const0_rtx); |
5369 | imag = gen_rtx_EXPR_LIST (VOIDmode, | |
5370 | gen_rtx_REG (inner, | |
65239d20 | 5371 | regno + info.reg_words / 2), |
ab77a036 RS |
5372 | GEN_INT (GET_MODE_SIZE (inner))); |
5373 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); | |
e0ec4c3b | 5374 | } |
730cf822 | 5375 | } |
f5963e61 | 5376 | |
ab77a036 | 5377 | return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); |
cee98a59 | 5378 | } |
cee98a59 | 5379 | |
c8717ea3 | 5380 | /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ |
cee98a59 | 5381 | |
c8717ea3 | 5382 | static void |
ef4bddc2 | 5383 | mips_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
c8717ea3 | 5384 | const_tree type, bool named) |
842eb20e | 5385 | { |
d5cc9181 | 5386 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
ab77a036 | 5387 | struct mips_arg_info info; |
842eb20e | 5388 | |
65239d20 | 5389 | mips_get_arg_info (&info, cum, mode, type, named); |
842eb20e | 5390 | |
ab77a036 RS |
5391 | if (!info.fpr_p) |
5392 | cum->gp_reg_found = true; | |
910628b8 | 5393 | |
65239d20 RS |
5394 | /* See the comment above the CUMULATIVE_ARGS structure in mips.h for |
5395 | an explanation of what this code does. It assumes that we're using | |
5396 | either the o32 or the o64 ABI, both of which pass at most 2 arguments | |
5397 | in FPRs. */ | |
ab77a036 RS |
5398 | if (cum->arg_number < 2 && info.fpr_p) |
5399 | cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2); | |
910628b8 | 5400 | |
65239d20 RS |
5401 | /* Advance the register count. This has the effect of setting |
5402 | num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned | |
5403 | argument required us to skip the final GPR and pass the whole | |
5404 | argument on the stack. */ | |
ab77a036 RS |
5405 | if (mips_abi != ABI_EABI || !info.fpr_p) |
5406 | cum->num_gprs = info.reg_offset + info.reg_words; | |
5407 | else if (info.reg_words > 0) | |
5408 | cum->num_fprs += MAX_FPRS_PER_FMT; | |
910628b8 | 5409 | |
65239d20 | 5410 | /* Advance the stack word count. */ |
ab77a036 RS |
5411 | if (info.stack_words > 0) |
5412 | cum->stack_words = info.stack_offset + info.stack_words; | |
842eb20e | 5413 | |
ab77a036 RS |
5414 | cum->arg_number++; |
5415 | } | |
842eb20e | 5416 | |
ab77a036 | 5417 | /* Implement TARGET_ARG_PARTIAL_BYTES. */ |
842eb20e | 5418 | |
ab77a036 | 5419 | static int |
d5cc9181 | 5420 | mips_arg_partial_bytes (cumulative_args_t cum, |
ef4bddc2 | 5421 | machine_mode mode, tree type, bool named) |
ab77a036 RS |
5422 | { |
5423 | struct mips_arg_info info; | |
f5963e61 | 5424 | |
d5cc9181 | 5425 | mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named); |
ab77a036 RS |
5426 | return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; |
5427 | } | |
147255d8 | 5428 | |
c2ed6cf8 NF |
5429 | /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at |
5430 | least PARM_BOUNDARY bits of alignment, but will be given anything up | |
ab77a036 | 5431 | to STACK_BOUNDARY bits if the type requires it. */ |
f5963e61 | 5432 | |
c2ed6cf8 | 5433 | static unsigned int |
ef4bddc2 | 5434 | mips_function_arg_boundary (machine_mode mode, const_tree type) |
ab77a036 RS |
5435 | { |
5436 | unsigned int alignment; | |
5437 | ||
5438 | alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
5439 | if (alignment < PARM_BOUNDARY) | |
5440 | alignment = PARM_BOUNDARY; | |
5441 | if (alignment > STACK_BOUNDARY) | |
5442 | alignment = STACK_BOUNDARY; | |
5443 | return alignment; | |
730cf822 | 5444 | } |
df770e04 | 5445 | |
ab77a036 RS |
5446 | /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return |
5447 | upward rather than downward. In other words, return true if the | |
5448 | first byte of the stack slot has useful data, false if the last | |
5449 | byte does. */ | |
df770e04 | 5450 | |
ab77a036 | 5451 | bool |
ef4bddc2 | 5452 | mips_pad_arg_upward (machine_mode mode, const_tree type) |
df770e04 | 5453 | { |
ab77a036 RS |
5454 | /* On little-endian targets, the first byte of every stack argument |
5455 | is passed in the first byte of the stack slot. */ | |
5456 | if (!BYTES_BIG_ENDIAN) | |
5457 | return true; | |
df770e04 | 5458 | |
ab77a036 RS |
5459 | /* Otherwise, integral types are padded downward: the last byte of a |
5460 | stack argument is passed in the last byte of the stack slot. */ | |
5461 | if (type != 0 | |
5462 | ? (INTEGRAL_TYPE_P (type) | |
5463 | || POINTER_TYPE_P (type) | |
5464 | || FIXED_POINT_TYPE_P (type)) | |
65239d20 | 5465 | : (SCALAR_INT_MODE_P (mode) |
ab77a036 RS |
5466 | || ALL_SCALAR_FIXED_POINT_MODE_P (mode))) |
5467 | return false; | |
df770e04 | 5468 | |
ab77a036 RS |
5469 | /* Big-endian o64 pads floating-point arguments downward. */ |
5470 | if (mips_abi == ABI_O64) | |
5471 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5472 | return false; | |
df770e04 | 5473 | |
ab77a036 RS |
5474 | /* Other types are padded upward for o32, o64, n32 and n64. */ |
5475 | if (mips_abi != ABI_EABI) | |
5476 | return true; | |
df770e04 | 5477 | |
ab77a036 RS |
5478 | /* Arguments smaller than a stack slot are padded downward. */ |
5479 | if (mode != BLKmode) | |
65239d20 | 5480 | return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY; |
ab77a036 | 5481 | else |
65239d20 | 5482 | return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT); |
ab77a036 | 5483 | } |
df770e04 | 5484 | |
ab77a036 RS |
5485 | /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN |
5486 | if the least significant byte of the register has useful data. Return | |
5487 | the opposite if the most significant byte does. */ | |
0cebb05d | 5488 | |
730cf822 | 5489 | bool |
ef4bddc2 | 5490 | mips_pad_reg_upward (machine_mode mode, tree type) |
730cf822 | 5491 | { |
ab77a036 RS |
5492 | /* No shifting is required for floating-point arguments. */ |
5493 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5494 | return !BYTES_BIG_ENDIAN; | |
5495 | ||
5496 | /* Otherwise, apply the same padding to register arguments as we do | |
5497 | to stack arguments. */ | |
5498 | return mips_pad_arg_upward (mode, type); | |
842eb20e | 5499 | } |
cee98a59 | 5500 | |
ab77a036 | 5501 | /* Return nonzero when an argument must be passed by reference. */ |
cee98a59 | 5502 | |
ab77a036 | 5503 | static bool |
d5cc9181 | 5504 | mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ef4bddc2 | 5505 | machine_mode mode, const_tree type, |
ab77a036 RS |
5506 | bool named ATTRIBUTE_UNUSED) |
5507 | { | |
5508 | if (mips_abi == ABI_EABI) | |
5509 | { | |
5510 | int size; | |
cee98a59 | 5511 | |
ab77a036 RS |
5512 | /* ??? How should SCmode be handled? */ |
5513 | if (mode == DImode || mode == DFmode | |
5514 | || mode == DQmode || mode == UDQmode | |
5515 | || mode == DAmode || mode == UDAmode) | |
5516 | return 0; | |
cee98a59 | 5517 | |
ab77a036 RS |
5518 | size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); |
5519 | return size == -1 || size > UNITS_PER_WORD; | |
5520 | } | |
5521 | else | |
cee98a59 | 5522 | { |
ab77a036 RS |
5523 | /* If we have a variable-sized parameter, we have no choice. */ |
5524 | return targetm.calls.must_pass_in_stack (mode, type); | |
cee98a59 | 5525 | } |
cee98a59 MM |
5526 | } |
5527 | ||
65239d20 RS |
5528 | /* Implement TARGET_CALLEE_COPIES. */ |
5529 | ||
ab77a036 | 5530 | static bool |
d5cc9181 | 5531 | mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ef4bddc2 | 5532 | machine_mode mode ATTRIBUTE_UNUSED, |
ab77a036 RS |
5533 | const_tree type ATTRIBUTE_UNUSED, bool named) |
5534 | { | |
5535 | return mips_abi == ABI_EABI && named; | |
5536 | } | |
5537 | \f | |
5538 | /* See whether VALTYPE is a record whose fields should be returned in | |
5539 | floating-point registers. If so, return the number of fields and | |
5540 | list them in FIELDS (which should have two elements). Return 0 | |
5541 | otherwise. | |
b4966b1b | 5542 | |
ab77a036 RS |
5543 | For n32 & n64, a structure with one or two fields is returned in |
5544 | floating-point registers as long as every field has a floating-point | |
5545 | type. */ | |
b4966b1b | 5546 | |
ab77a036 RS |
5547 | static int |
5548 | mips_fpr_return_fields (const_tree valtype, tree *fields) | |
4d72536e | 5549 | { |
ab77a036 RS |
5550 | tree field; |
5551 | int i; | |
4d72536e | 5552 | |
ab77a036 RS |
5553 | if (!TARGET_NEWABI) |
5554 | return 0; | |
4d72536e | 5555 | |
ab77a036 RS |
5556 | if (TREE_CODE (valtype) != RECORD_TYPE) |
5557 | return 0; | |
4d72536e | 5558 | |
ab77a036 | 5559 | i = 0; |
910ad8de | 5560 | for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field)) |
ae043003 | 5561 | { |
ab77a036 RS |
5562 | if (TREE_CODE (field) != FIELD_DECL) |
5563 | continue; | |
ae043003 | 5564 | |
a3d97724 | 5565 | if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) |
ab77a036 | 5566 | return 0; |
ae043003 | 5567 | |
ab77a036 RS |
5568 | if (i == 2) |
5569 | return 0; | |
ae043003 | 5570 | |
ab77a036 RS |
5571 | fields[i++] = field; |
5572 | } | |
5573 | return i; | |
5574 | } | |
ae043003 | 5575 | |
ab77a036 RS |
5576 | /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return |
5577 | a value in the most significant part of $2/$3 if: | |
ae043003 | 5578 | |
ab77a036 | 5579 | - the target is big-endian; |
ae043003 | 5580 | |
ab77a036 RS |
5581 | - the value has a structure or union type (we generalize this to |
5582 | cover aggregates from other languages too); and | |
4d72536e | 5583 | |
ab77a036 | 5584 | - the structure is not returned in floating-point registers. */ |
4d72536e | 5585 | |
ab77a036 RS |
5586 | static bool |
5587 | mips_return_in_msb (const_tree valtype) | |
5588 | { | |
5589 | tree fields[2]; | |
4d72536e | 5590 | |
ab77a036 RS |
5591 | return (TARGET_NEWABI |
5592 | && TARGET_BIG_ENDIAN | |
5593 | && AGGREGATE_TYPE_P (valtype) | |
5594 | && mips_fpr_return_fields (valtype, fields) == 0); | |
4d72536e RS |
5595 | } |
5596 | ||
ab77a036 RS |
5597 | /* Return true if the function return value MODE will get returned in a |
5598 | floating-point register. */ | |
a38e0142 | 5599 | |
ab77a036 | 5600 | static bool |
ef4bddc2 | 5601 | mips_return_mode_in_fpr_p (machine_mode mode) |
a38e0142 | 5602 | { |
ab77a036 | 5603 | return ((GET_MODE_CLASS (mode) == MODE_FLOAT |
7dab511c | 5604 | || mode == V2SFmode |
ab77a036 RS |
5605 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
5606 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); | |
a38e0142 SL |
5607 | } |
5608 | ||
fd0d4c1f RS |
5609 | /* Return the representation of an FPR return register when the |
5610 | value being returned in FP_RETURN has mode VALUE_MODE and the | |
5611 | return type itself has mode TYPE_MODE. On NewABI targets, | |
5612 | the two modes may be different for structures like: | |
5613 | ||
5614 | struct __attribute__((packed)) foo { float f; } | |
5615 | ||
5616 | where we return the SFmode value of "f" in FP_RETURN, but where | |
5617 | the structure itself has mode BLKmode. */ | |
5618 | ||
5619 | static rtx | |
ef4bddc2 RS |
5620 | mips_return_fpr_single (machine_mode type_mode, |
5621 | machine_mode value_mode) | |
fd0d4c1f RS |
5622 | { |
5623 | rtx x; | |
5624 | ||
5625 | x = gen_rtx_REG (value_mode, FP_RETURN); | |
5626 | if (type_mode != value_mode) | |
5627 | { | |
5628 | x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); | |
5629 | x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); | |
5630 | } | |
5631 | return x; | |
5632 | } | |
5633 | ||
ab77a036 RS |
5634 | /* Return a composite value in a pair of floating-point registers. |
5635 | MODE1 and OFFSET1 are the mode and byte offset for the first value, | |
5636 | likewise MODE2 and OFFSET2 for the second. MODE is the mode of the | |
5637 | complete value. | |
cee98a59 | 5638 | |
ab77a036 RS |
5639 | For n32 & n64, $f0 always holds the first value and $f2 the second. |
5640 | Otherwise the values are packed together as closely as possible. */ | |
cee98a59 | 5641 | |
ab77a036 | 5642 | static rtx |
ef4bddc2 RS |
5643 | mips_return_fpr_pair (machine_mode mode, |
5644 | machine_mode mode1, HOST_WIDE_INT offset1, | |
5645 | machine_mode mode2, HOST_WIDE_INT offset2) | |
ab77a036 RS |
5646 | { |
5647 | int inc; | |
cee98a59 | 5648 | |
ab77a036 RS |
5649 | inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT); |
5650 | return gen_rtx_PARALLEL | |
5651 | (mode, | |
5652 | gen_rtvec (2, | |
5653 | gen_rtx_EXPR_LIST (VOIDmode, | |
5654 | gen_rtx_REG (mode1, FP_RETURN), | |
5655 | GEN_INT (offset1)), | |
5656 | gen_rtx_EXPR_LIST (VOIDmode, | |
5657 | gen_rtx_REG (mode2, FP_RETURN + inc), | |
5658 | GEN_INT (offset2)))); | |
cee98a59 | 5659 | |
cee98a59 MM |
5660 | } |
5661 | ||
47be3d6d AS |
5662 | /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE. |
5663 | For normal calls, VALTYPE is the return type and MODE is VOIDmode. | |
5664 | For libcalls, VALTYPE is null and MODE is the mode of the return value. */ | |
cee98a59 | 5665 | |
47be3d6d AS |
5666 | static rtx |
5667 | mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type, | |
ef4bddc2 | 5668 | machine_mode mode) |
ab77a036 RS |
5669 | { |
5670 | if (valtype) | |
cee98a59 | 5671 | { |
ab77a036 | 5672 | tree fields[2]; |
65239d20 | 5673 | int unsigned_p; |
47be3d6d AS |
5674 | const_tree func; |
5675 | ||
5676 | if (fn_decl_or_type && DECL_P (fn_decl_or_type)) | |
5677 | func = fn_decl_or_type; | |
5678 | else | |
5679 | func = NULL; | |
cee98a59 | 5680 | |
ab77a036 | 5681 | mode = TYPE_MODE (valtype); |
65239d20 | 5682 | unsigned_p = TYPE_UNSIGNED (valtype); |
4d72536e | 5683 | |
cde0f3fd PB |
5684 | /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, |
5685 | return values, promote the mode here too. */ | |
5686 | mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); | |
0e5a4ad8 | 5687 | |
ab77a036 RS |
5688 | /* Handle structures whose fields are returned in $f0/$f2. */ |
5689 | switch (mips_fpr_return_fields (valtype, fields)) | |
a20b7b05 | 5690 | { |
ab77a036 | 5691 | case 1: |
fd0d4c1f RS |
5692 | return mips_return_fpr_single (mode, |
5693 | TYPE_MODE (TREE_TYPE (fields[0]))); | |
4d72536e | 5694 | |
ab77a036 RS |
5695 | case 2: |
5696 | return mips_return_fpr_pair (mode, | |
5697 | TYPE_MODE (TREE_TYPE (fields[0])), | |
5698 | int_byte_position (fields[0]), | |
5699 | TYPE_MODE (TREE_TYPE (fields[1])), | |
5700 | int_byte_position (fields[1])); | |
5701 | } | |
4d72536e | 5702 | |
ab77a036 RS |
5703 | /* If a value is passed in the most significant part of a register, see |
5704 | whether we have to round the mode up to a whole number of words. */ | |
5705 | if (mips_return_in_msb (valtype)) | |
5706 | { | |
5707 | HOST_WIDE_INT size = int_size_in_bytes (valtype); | |
5708 | if (size % UNITS_PER_WORD != 0) | |
a20b7b05 | 5709 | { |
ab77a036 RS |
5710 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; |
5711 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4d72536e | 5712 | } |
3f1f8d8c | 5713 | } |
ab77a036 RS |
5714 | |
5715 | /* For EABI, the class of return register depends entirely on MODE. | |
5716 | For example, "struct { some_type x; }" and "union { some_type x; }" | |
5717 | are returned in the same way as a bare "some_type" would be. | |
5718 | Other ABIs only use FPRs for scalar, complex or vector types. */ | |
5719 | if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype)) | |
5720 | return gen_rtx_REG (mode, GP_RETURN); | |
3f1f8d8c MM |
5721 | } |
5722 | ||
ab77a036 | 5723 | if (!TARGET_MIPS16) |
ae043003 | 5724 | { |
ab77a036 RS |
5725 | /* Handle long doubles for n32 & n64. */ |
5726 | if (mode == TFmode) | |
5727 | return mips_return_fpr_pair (mode, | |
5728 | DImode, 0, | |
5729 | DImode, GET_MODE_SIZE (mode) / 2); | |
ae043003 | 5730 | |
ab77a036 | 5731 | if (mips_return_mode_in_fpr_p (mode)) |
0882b52e | 5732 | { |
ab77a036 RS |
5733 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
5734 | return mips_return_fpr_pair (mode, | |
5735 | GET_MODE_INNER (mode), 0, | |
5736 | GET_MODE_INNER (mode), | |
5737 | GET_MODE_SIZE (mode) / 2); | |
5738 | else | |
5739 | return gen_rtx_REG (mode, FP_RETURN); | |
0882b52e | 5740 | } |
ae043003 RS |
5741 | } |
5742 | ||
ab77a036 | 5743 | return gen_rtx_REG (mode, GP_RETURN); |
cee98a59 MM |
5744 | } |
5745 | ||
47be3d6d AS |
5746 | /* Implement TARGET_FUNCTION_VALUE. */ |
5747 | ||
5748 | static rtx | |
5749 | mips_function_value (const_tree valtype, const_tree fn_decl_or_type, | |
5750 | bool outgoing ATTRIBUTE_UNUSED) | |
5751 | { | |
5752 | return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode); | |
5753 | } | |
5754 | ||
5755 | /* Implement TARGET_LIBCALL_VALUE. */ | |
5756 | ||
5757 | static rtx | |
ef4bddc2 | 5758 | mips_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) |
47be3d6d AS |
5759 | { |
5760 | return mips_function_value_1 (NULL_TREE, NULL_TREE, mode); | |
5761 | } | |
5762 | ||
5763 | /* Implement TARGET_FUNCTION_VALUE_REGNO_P. | |
5764 | ||
5765 | On the MIPS, R2 R3 and F0 F2 are the only register thus used. | |
5766 | Currently, R2 and F0 are only implemented here (C has no complex type). */ | |
5767 | ||
5768 | static bool | |
5769 | mips_function_value_regno_p (const unsigned int regno) | |
5770 | { | |
5771 | if (regno == GP_RETURN | |
5772 | || regno == FP_RETURN | |
5773 | || (LONG_DOUBLE_TYPE_SIZE == 128 | |
5774 | && FP_RETURN != GP_RETURN | |
5775 | && regno == FP_RETURN + 2)) | |
5776 | return true; | |
5777 | ||
5778 | return false; | |
5779 | } | |
5780 | ||
65239d20 RS |
5781 | /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs, |
5782 | all BLKmode objects are returned in memory. Under the n32, n64 | |
5783 | and embedded ABIs, small structures are returned in a register. | |
ab77a036 RS |
5784 | Objects with varying size must still be returned in memory, of |
5785 | course. */ | |
b4966b1b | 5786 | |
ab77a036 RS |
5787 | static bool |
5788 | mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) | |
648bb159 | 5789 | { |
65239d20 RS |
5790 | return (TARGET_OLDABI |
5791 | ? TYPE_MODE (type) == BLKmode | |
5792 | : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD)); | |
648bb159 | 5793 | } |
4d72536e | 5794 | \f |
65239d20 RS |
5795 | /* Implement TARGET_SETUP_INCOMING_VARARGS. */ |
5796 | ||
0c8da560 | 5797 | static void |
ef4bddc2 | 5798 | mips_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode, |
4001cd89 RS |
5799 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5800 | int no_rtl) | |
4d72536e RS |
5801 | { |
5802 | CUMULATIVE_ARGS local_cum; | |
5803 | int gp_saved, fp_saved; | |
cee98a59 | 5804 | |
4d72536e RS |
5805 | /* The caller has advanced CUM up to, but not beyond, the last named |
5806 | argument. Advance a local copy of CUM past the last "real" named | |
6c535c69 | 5807 | argument, to find out how many registers are left over. */ |
d5cc9181 JR |
5808 | local_cum = *get_cumulative_args (cum); |
5809 | mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, | |
5810 | true); | |
4d72536e RS |
5811 | |
5812 | /* Found out how many registers we need to save. */ | |
bb63e5a0 | 5813 | gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; |
4d72536e | 5814 | fp_saved = (EABI_FLOAT_VARARGS_P |
bb63e5a0 | 5815 | ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs |
4d72536e | 5816 | : 0); |
cee98a59 | 5817 | |
4d72536e | 5818 | if (!no_rtl) |
cee98a59 | 5819 | { |
4d72536e RS |
5820 | if (gp_saved > 0) |
5821 | { | |
5822 | rtx ptr, mem; | |
5823 | ||
0a81f074 | 5824 | ptr = plus_constant (Pmode, virtual_incoming_args_rtx, |
4001cd89 RS |
5825 | REG_PARM_STACK_SPACE (cfun->decl) |
5826 | - gp_saved * UNITS_PER_WORD); | |
8d0e1e43 | 5827 | mem = gen_frame_mem (BLKmode, ptr); |
520d96c6 | 5828 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
4d72536e | 5829 | |
520d96c6 RS |
5830 | move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, |
5831 | mem, gp_saved); | |
4d72536e RS |
5832 | } |
5833 | if (fp_saved > 0) | |
5834 | { | |
5835 | /* We can't use move_block_from_reg, because it will use | |
031a26c5 | 5836 | the wrong mode. */ |
ef4bddc2 | 5837 | machine_mode mode; |
4d72536e | 5838 | int off, i; |
cee98a59 | 5839 | |
4d72536e | 5840 | /* Set OFF to the offset from virtual_incoming_args_rtx of |
71cc389b | 5841 | the first float register. The FP save area lies below |
4d72536e | 5842 | the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */ |
65239d20 | 5843 | off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE; |
4d72536e | 5844 | off -= fp_saved * UNITS_PER_FPREG; |
cee98a59 | 5845 | |
4d72536e RS |
5846 | mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; |
5847 | ||
e8ab09c1 SL |
5848 | for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; |
5849 | i += MAX_FPRS_PER_FMT) | |
4d72536e | 5850 | { |
520d96c6 RS |
5851 | rtx ptr, mem; |
5852 | ||
0a81f074 | 5853 | ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off); |
8d0e1e43 | 5854 | mem = gen_frame_mem (mode, ptr); |
520d96c6 | 5855 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
51e7252a | 5856 | mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i)); |
8a381273 | 5857 | off += UNITS_PER_HWFPVALUE; |
4d72536e RS |
5858 | } |
5859 | } | |
5860 | } | |
4001cd89 RS |
5861 | if (REG_PARM_STACK_SPACE (cfun->decl) == 0) |
5862 | cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD | |
5863 | + fp_saved * UNITS_PER_FPREG); | |
cee98a59 | 5864 | } |
4d72536e | 5865 | |
65239d20 | 5866 | /* Implement TARGET_BUILTIN_VA_LIST. */ |
4fe12442 | 5867 | |
c35d187f RH |
5868 | static tree |
5869 | mips_build_builtin_va_list (void) | |
5d3f2bd5 | 5870 | { |
4d72536e | 5871 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5872 | { |
65239d20 RS |
5873 | /* We keep 3 pointers, and two offsets. |
5874 | ||
5875 | Two pointers are to the overflow area, which starts at the CFA. | |
5876 | One of these is constant, for addressing into the GPR save area | |
5877 | below it. The other is advanced up the stack through the | |
5878 | overflow region. | |
5879 | ||
5880 | The third pointer is to the bottom of the GPR save area. | |
5881 | Since the FPR save area is just below it, we can address | |
5882 | FPR slots off this pointer. | |
5883 | ||
5884 | We also keep two one-byte offsets, which are to be subtracted | |
5885 | from the constant pointers to yield addresses in the GPR and | |
5886 | FPR save areas. These are downcounted as float or non-float | |
5887 | arguments are used, and when they get to zero, the argument | |
5888 | must be obtained from the overflow region. */ | |
7a0ec607 CD |
5889 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record; |
5890 | tree array, index; | |
5d3f2bd5 | 5891 | |
65239d20 | 5892 | record = lang_hooks.types.make_type (RECORD_TYPE); |
5d3f2bd5 | 5893 | |
4c4bde29 AH |
5894 | f_ovfl = build_decl (BUILTINS_LOCATION, |
5895 | FIELD_DECL, get_identifier ("__overflow_argptr"), | |
65239d20 | 5896 | ptr_type_node); |
4c4bde29 AH |
5897 | f_gtop = build_decl (BUILTINS_LOCATION, |
5898 | FIELD_DECL, get_identifier ("__gpr_top"), | |
65239d20 | 5899 | ptr_type_node); |
4c4bde29 AH |
5900 | f_ftop = build_decl (BUILTINS_LOCATION, |
5901 | FIELD_DECL, get_identifier ("__fpr_top"), | |
65239d20 | 5902 | ptr_type_node); |
4c4bde29 AH |
5903 | f_goff = build_decl (BUILTINS_LOCATION, |
5904 | FIELD_DECL, get_identifier ("__gpr_offset"), | |
65239d20 | 5905 | unsigned_char_type_node); |
4c4bde29 AH |
5906 | f_foff = build_decl (BUILTINS_LOCATION, |
5907 | FIELD_DECL, get_identifier ("__fpr_offset"), | |
65239d20 | 5908 | unsigned_char_type_node); |
7a0ec607 CD |
5909 | /* Explicitly pad to the size of a pointer, so that -Wpadded won't |
5910 | warn on every user file. */ | |
7d60be94 | 5911 | index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1); |
7a0ec607 CD |
5912 | array = build_array_type (unsigned_char_type_node, |
5913 | build_index_type (index)); | |
4c4bde29 AH |
5914 | f_res = build_decl (BUILTINS_LOCATION, |
5915 | FIELD_DECL, get_identifier ("__reserved"), array); | |
5d3f2bd5 | 5916 | |
4fe12442 DL |
5917 | DECL_FIELD_CONTEXT (f_ovfl) = record; |
5918 | DECL_FIELD_CONTEXT (f_gtop) = record; | |
5919 | DECL_FIELD_CONTEXT (f_ftop) = record; | |
5920 | DECL_FIELD_CONTEXT (f_goff) = record; | |
5921 | DECL_FIELD_CONTEXT (f_foff) = record; | |
7a0ec607 | 5922 | DECL_FIELD_CONTEXT (f_res) = record; |
5d3f2bd5 | 5923 | |
4fe12442 | 5924 | TYPE_FIELDS (record) = f_ovfl; |
910ad8de NF |
5925 | DECL_CHAIN (f_ovfl) = f_gtop; |
5926 | DECL_CHAIN (f_gtop) = f_ftop; | |
5927 | DECL_CHAIN (f_ftop) = f_goff; | |
5928 | DECL_CHAIN (f_goff) = f_foff; | |
5929 | DECL_CHAIN (f_foff) = f_res; | |
5d3f2bd5 | 5930 | |
4fe12442 | 5931 | layout_type (record); |
5d3f2bd5 RH |
5932 | return record; |
5933 | } | |
5934 | else | |
4f1cad00 RH |
5935 | /* Otherwise, we use 'void *'. */ |
5936 | return ptr_type_node; | |
5d3f2bd5 RH |
5937 | } |
5938 | ||
d7bd8aeb | 5939 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ |
5d3f2bd5 | 5940 | |
d7bd8aeb | 5941 | static void |
b4966b1b | 5942 | mips_va_start (tree valist, rtx nextarg) |
5d3f2bd5 | 5943 | { |
4001cd89 | 5944 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5945 | { |
4001cd89 RS |
5946 | const CUMULATIVE_ARGS *cum; |
5947 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; | |
5948 | tree ovfl, gtop, ftop, goff, foff; | |
5949 | tree t; | |
4fe12442 | 5950 | int gpr_save_area_size; |
4001cd89 RS |
5951 | int fpr_save_area_size; |
5952 | int fpr_offset; | |
4fe12442 | 5953 | |
38173d38 | 5954 | cum = &crtl->args.info; |
4d72536e | 5955 | gpr_save_area_size |
bb63e5a0 | 5956 | = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD; |
4001cd89 RS |
5957 | fpr_save_area_size |
5958 | = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG; | |
4d72536e | 5959 | |
4001cd89 | 5960 | f_ovfl = TYPE_FIELDS (va_list_type_node); |
910ad8de NF |
5961 | f_gtop = DECL_CHAIN (f_ovfl); |
5962 | f_ftop = DECL_CHAIN (f_gtop); | |
5963 | f_goff = DECL_CHAIN (f_ftop); | |
5964 | f_foff = DECL_CHAIN (f_goff); | |
4001cd89 | 5965 | |
47a25a46 RG |
5966 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5967 | NULL_TREE); | |
5968 | gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, | |
5969 | NULL_TREE); | |
5970 | ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, | |
5971 | NULL_TREE); | |
5972 | goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, | |
5973 | NULL_TREE); | |
5974 | foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, | |
5975 | NULL_TREE); | |
4001cd89 RS |
5976 | |
5977 | /* Emit code to initialize OVFL, which points to the next varargs | |
5978 | stack argument. CUM->STACK_WORDS gives the number of stack | |
5979 | words used by named arguments. */ | |
5980 | t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); | |
5981 | if (cum->stack_words > 0) | |
5d49b6a7 | 5982 | t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD); |
726a989a | 5983 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); |
4001cd89 RS |
5984 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5985 | ||
5986 | /* Emit code to initialize GTOP, the top of the GPR save area. */ | |
5987 | t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); | |
726a989a | 5988 | t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); |
4001cd89 RS |
5989 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5990 | ||
5991 | /* Emit code to initialize FTOP, the top of the FPR save area. | |
5992 | This address is gpr_save_area_bytes below GTOP, rounded | |
5993 | down to the next fp-aligned boundary. */ | |
5994 | t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); | |
5995 | fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1; | |
65239d20 | 5996 | fpr_offset &= -UNITS_PER_FPVALUE; |
4001cd89 | 5997 | if (fpr_offset) |
5d49b6a7 | 5998 | t = fold_build_pointer_plus_hwi (t, -fpr_offset); |
726a989a | 5999 | t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t); |
4001cd89 RS |
6000 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
6001 | ||
6002 | /* Emit code to initialize GOFF, the offset from GTOP of the | |
6003 | next GPR argument. */ | |
726a989a | 6004 | t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff, |
e0681eaa | 6005 | build_int_cst (TREE_TYPE (goff), gpr_save_area_size)); |
4001cd89 RS |
6006 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
6007 | ||
6008 | /* Likewise emit code to initialize FOFF, the offset from FTOP | |
6009 | of the next FPR argument. */ | |
726a989a | 6010 | t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff, |
e0681eaa | 6011 | build_int_cst (TREE_TYPE (foff), fpr_save_area_size)); |
4001cd89 | 6012 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5d3f2bd5 RH |
6013 | } |
6014 | else | |
4001cd89 | 6015 | { |
0a81f074 | 6016 | nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size); |
4001cd89 RS |
6017 | std_expand_builtin_va_start (valist, nextarg); |
6018 | } | |
5d3f2bd5 | 6019 | } |
65239d20 | 6020 | |
4566de10 RS |
6021 | /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized |
6022 | types as well. */ | |
6023 | ||
6024 | static tree | |
6025 | mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, | |
6026 | gimple_seq *post_p) | |
6027 | { | |
6028 | tree addr, t, type_size, rounded_size, valist_tmp; | |
6029 | unsigned HOST_WIDE_INT align, boundary; | |
6030 | bool indirect; | |
6031 | ||
6032 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); | |
6033 | if (indirect) | |
6034 | type = build_pointer_type (type); | |
6035 | ||
6036 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
6037 | boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type); | |
6038 | ||
6039 | /* When we align parameter on stack for caller, if the parameter | |
6040 | alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be | |
6041 | aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee | |
6042 | here with caller. */ | |
6043 | if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT) | |
6044 | boundary = MAX_SUPPORTED_STACK_ALIGNMENT; | |
6045 | ||
6046 | boundary /= BITS_PER_UNIT; | |
6047 | ||
6048 | /* Hoist the valist value into a temporary for the moment. */ | |
6049 | valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL); | |
6050 | ||
6051 | /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually | |
6052 | requires greater alignment, we must perform dynamic alignment. */ | |
6053 | if (boundary > align) | |
6054 | { | |
6055 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, | |
6056 | fold_build_pointer_plus_hwi (valist_tmp, boundary - 1)); | |
6057 | gimplify_and_add (t, pre_p); | |
6058 | ||
6059 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, | |
6060 | fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist), | |
6061 | valist_tmp, | |
6062 | build_int_cst (TREE_TYPE (valist), -boundary))); | |
6063 | gimplify_and_add (t, pre_p); | |
6064 | } | |
6065 | else | |
6066 | boundary = align; | |
6067 | ||
6068 | /* If the actual alignment is less than the alignment of the type, | |
6069 | adjust the type accordingly so that we don't assume strict alignment | |
6070 | when dereferencing the pointer. */ | |
6071 | boundary *= BITS_PER_UNIT; | |
6072 | if (boundary < TYPE_ALIGN (type)) | |
6073 | { | |
6074 | type = build_variant_type_copy (type); | |
6075 | TYPE_ALIGN (type) = boundary; | |
6076 | } | |
6077 | ||
6078 | /* Compute the rounded size of the type. */ | |
6079 | type_size = size_in_bytes (type); | |
6080 | rounded_size = round_up (type_size, align); | |
6081 | ||
6082 | /* Reduce rounded_size so it's sharable with the postqueue. */ | |
6083 | gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue); | |
6084 | ||
6085 | /* Get AP. */ | |
6086 | addr = valist_tmp; | |
6087 | if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size)) | |
6088 | { | |
6089 | /* Small args are padded downward. */ | |
6090 | t = fold_build2_loc (input_location, GT_EXPR, sizetype, | |
6091 | rounded_size, size_int (align)); | |
6092 | t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node, | |
6093 | size_binop (MINUS_EXPR, rounded_size, type_size)); | |
6094 | addr = fold_build_pointer_plus (addr, t); | |
6095 | } | |
6096 | ||
6097 | /* Compute new value for AP. */ | |
6098 | t = fold_build_pointer_plus (valist_tmp, rounded_size); | |
6099 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
6100 | gimplify_and_add (t, pre_p); | |
6101 | ||
6102 | addr = fold_convert (build_pointer_type (type), addr); | |
6103 | ||
6104 | if (indirect) | |
6105 | addr = build_va_arg_indirect_ref (addr); | |
6106 | ||
6107 | return build_va_arg_indirect_ref (addr); | |
6108 | } | |
6109 | ||
65239d20 | 6110 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ |
5d3f2bd5 | 6111 | |
0310e537 | 6112 | static tree |
726a989a RB |
6113 | mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
6114 | gimple_seq *post_p) | |
5d3f2bd5 | 6115 | { |
0310e537 | 6116 | tree addr; |
65239d20 | 6117 | bool indirect_p; |
0310e537 | 6118 | |
65239d20 RS |
6119 | indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
6120 | if (indirect_p) | |
0310e537 | 6121 | type = build_pointer_type (type); |
5d3f2bd5 | 6122 | |
65239d20 | 6123 | if (!EABI_FLOAT_VARARGS_P) |
4566de10 | 6124 | addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
0310e537 | 6125 | else |
5d3f2bd5 | 6126 | { |
0310e537 RH |
6127 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; |
6128 | tree ovfl, top, off, align; | |
65239d20 | 6129 | HOST_WIDE_INT size, rsize, osize; |
0310e537 RH |
6130 | tree t, u; |
6131 | ||
6132 | f_ovfl = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
6133 | f_gtop = DECL_CHAIN (f_ovfl); |
6134 | f_ftop = DECL_CHAIN (f_gtop); | |
6135 | f_goff = DECL_CHAIN (f_ftop); | |
6136 | f_foff = DECL_CHAIN (f_goff); | |
0310e537 | 6137 | |
65239d20 | 6138 | /* Let: |
0310e537 | 6139 | |
65239d20 | 6140 | TOP be the top of the GPR or FPR save area; |
0310e537 RH |
6141 | OFF be the offset from TOP of the next register; |
6142 | ADDR_RTX be the address of the argument; | |
65239d20 | 6143 | SIZE be the number of bytes in the argument type; |
0310e537 | 6144 | RSIZE be the number of bytes used to store the argument |
65239d20 | 6145 | when it's in the register save area; and |
0310e537 | 6146 | OSIZE be the number of bytes used to store it when it's |
65239d20 | 6147 | in the stack overflow area. |
0310e537 RH |
6148 | |
6149 | The code we want is: | |
6150 | ||
6151 | 1: off &= -rsize; // round down | |
6152 | 2: if (off != 0) | |
6153 | 3: { | |
65239d20 RS |
6154 | 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0); |
6155 | 5: off -= rsize; | |
0310e537 RH |
6156 | 6: } |
6157 | 7: else | |
6158 | 8: { | |
65239d20 RS |
6159 | 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize; |
6160 | 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0); | |
6161 | 11: ovfl += osize; | |
6162 | 14: } | |
0310e537 RH |
6163 | |
6164 | [1] and [9] can sometimes be optimized away. */ | |
6165 | ||
47a25a46 RG |
6166 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
6167 | NULL_TREE); | |
65239d20 | 6168 | size = int_size_in_bytes (type); |
0310e537 RH |
6169 | |
6170 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT | |
6171 | && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE) | |
5d3f2bd5 | 6172 | { |
6d8d5435 RS |
6173 | top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), |
6174 | unshare_expr (valist), f_ftop, NULL_TREE); | |
6175 | off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), | |
6176 | unshare_expr (valist), f_foff, NULL_TREE); | |
0310e537 | 6177 | |
65239d20 RS |
6178 | /* When va_start saves FPR arguments to the stack, each slot |
6179 | takes up UNITS_PER_HWFPVALUE bytes, regardless of the | |
6180 | argument's precision. */ | |
0310e537 RH |
6181 | rsize = UNITS_PER_HWFPVALUE; |
6182 | ||
6183 | /* Overflow arguments are padded to UNITS_PER_WORD bytes | |
6184 | (= PARM_BOUNDARY bits). This can be different from RSIZE | |
6185 | in two cases: | |
6186 | ||
6187 | (1) On 32-bit targets when TYPE is a structure such as: | |
6188 | ||
6189 | struct s { float f; }; | |
6190 | ||
6191 | Such structures are passed in paired FPRs, so RSIZE | |
6192 | will be 8 bytes. However, the structure only takes | |
6193 | up 4 bytes of memory, so OSIZE will only be 4. | |
6194 | ||
6195 | (2) In combinations such as -mgp64 -msingle-float | |
65239d20 RS |
6196 | -fshort-double. Doubles passed in registers will then take |
6197 | up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the | |
6198 | stack take up UNITS_PER_WORD bytes. */ | |
0310e537 | 6199 | osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD); |
5d3f2bd5 | 6200 | } |
4d72536e RS |
6201 | else |
6202 | { | |
6d8d5435 RS |
6203 | top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), |
6204 | unshare_expr (valist), f_gtop, NULL_TREE); | |
6205 | off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), | |
6206 | unshare_expr (valist), f_goff, NULL_TREE); | |
65239d20 | 6207 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; |
0310e537 | 6208 | if (rsize > UNITS_PER_WORD) |
4fe12442 | 6209 | { |
0310e537 | 6210 | /* [1] Emit code for: off &= -rsize. */ |
6d8d5435 | 6211 | t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off), |
3179cf8c | 6212 | build_int_cst (TREE_TYPE (off), -rsize)); |
6d8d5435 | 6213 | gimplify_assign (unshare_expr (off), t, pre_p); |
4d72536e | 6214 | } |
0310e537 RH |
6215 | osize = rsize; |
6216 | } | |
a85cd407 | 6217 | |
0310e537 | 6218 | /* [2] Emit code to branch if off == 0. */ |
1ab9ec7b | 6219 | t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off), |
47a25a46 RG |
6220 | build_int_cst (TREE_TYPE (off), 0)); |
6221 | addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); | |
0310e537 RH |
6222 | |
6223 | /* [5] Emit code for: off -= rsize. We do this as a form of | |
65239d20 | 6224 | post-decrement not available to C. */ |
7d60be94 | 6225 | t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize)); |
47a25a46 | 6226 | t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t); |
65239d20 RS |
6227 | |
6228 | /* [4] Emit code for: | |
6229 | addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */ | |
0310e537 | 6230 | t = fold_convert (sizetype, t); |
5be014d5 | 6231 | t = fold_build1 (NEGATE_EXPR, sizetype, t); |
5d49b6a7 | 6232 | t = fold_build_pointer_plus (top, t); |
0310e537 | 6233 | if (BYTES_BIG_ENDIAN && rsize > size) |
5d49b6a7 | 6234 | t = fold_build_pointer_plus_hwi (t, rsize - size); |
0310e537 | 6235 | COND_EXPR_THEN (addr) = t; |
a85cd407 | 6236 | |
0310e537 RH |
6237 | if (osize > UNITS_PER_WORD) |
6238 | { | |
65239d20 | 6239 | /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */ |
5d49b6a7 RG |
6240 | t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1); |
6241 | u = build_int_cst (TREE_TYPE (t), -osize); | |
1ab9ec7b | 6242 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u); |
6d8d5435 RS |
6243 | align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), |
6244 | unshare_expr (ovfl), t); | |
4d72536e | 6245 | } |
0310e537 RH |
6246 | else |
6247 | align = NULL; | |
6248 | ||
65239d20 RS |
6249 | /* [10, 11] Emit code for: |
6250 | addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0) | |
6251 | ovfl += osize. */ | |
6252 | u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize)); | |
47a25a46 | 6253 | t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u); |
0310e537 | 6254 | if (BYTES_BIG_ENDIAN && osize > size) |
5d49b6a7 | 6255 | t = fold_build_pointer_plus_hwi (t, osize - size); |
5d3f2bd5 | 6256 | |
65239d20 | 6257 | /* String [9] and [10, 11] together. */ |
0310e537 | 6258 | if (align) |
47a25a46 | 6259 | t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t); |
0310e537 | 6260 | COND_EXPR_ELSE (addr) = t; |
5d3f2bd5 | 6261 | |
0310e537 | 6262 | addr = fold_convert (build_pointer_type (type), addr); |
d6e9821f | 6263 | addr = build_va_arg_indirect_ref (addr); |
0310e537 | 6264 | } |
e72ed4a7 | 6265 | |
65239d20 | 6266 | if (indirect_p) |
d6e9821f | 6267 | addr = build_va_arg_indirect_ref (addr); |
5d3f2bd5 | 6268 | |
0310e537 | 6269 | return addr; |
5d3f2bd5 RH |
6270 | } |
6271 | \f | |
78c27266 RS |
6272 | /* Declare a unique, locally-binding function called NAME, then start |
6273 | its definition. */ | |
6274 | ||
6275 | static void | |
6276 | mips_start_unique_function (const char *name) | |
6277 | { | |
6278 | tree decl; | |
6279 | ||
6280 | decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, | |
6281 | get_identifier (name), | |
6282 | build_function_type_list (void_type_node, NULL_TREE)); | |
6283 | DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL, | |
6284 | NULL_TREE, void_type_node); | |
6285 | TREE_PUBLIC (decl) = 1; | |
6286 | TREE_STATIC (decl) = 1; | |
6287 | ||
51705ec1 | 6288 | cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl)); |
78c27266 RS |
6289 | |
6290 | targetm.asm_out.unique_section (decl, 0); | |
6291 | switch_to_section (get_named_section (decl, NULL, 0)); | |
6292 | ||
6293 | targetm.asm_out.globalize_label (asm_out_file, name); | |
6294 | fputs ("\t.hidden\t", asm_out_file); | |
6295 | assemble_name (asm_out_file, name); | |
6296 | putc ('\n', asm_out_file); | |
6297 | } | |
6298 | ||
b2b61607 RS |
6299 | /* Start a definition of function NAME. MIPS16_P indicates whether the |
6300 | function contains MIPS16 code. */ | |
6301 | ||
6302 | static void | |
6303 | mips_start_function_definition (const char *name, bool mips16_p) | |
6304 | { | |
6305 | if (mips16_p) | |
6306 | fprintf (asm_out_file, "\t.set\tmips16\n"); | |
6307 | else | |
6308 | fprintf (asm_out_file, "\t.set\tnomips16\n"); | |
6309 | ||
22c4c869 CM |
6310 | if (TARGET_MICROMIPS) |
6311 | fprintf (asm_out_file, "\t.set\tmicromips\n"); | |
6312 | #ifdef HAVE_GAS_MICROMIPS | |
6313 | else | |
6314 | fprintf (asm_out_file, "\t.set\tnomicromips\n"); | |
6315 | #endif | |
6316 | ||
b2b61607 RS |
6317 | if (!flag_inhibit_size_directive) |
6318 | { | |
6319 | fputs ("\t.ent\t", asm_out_file); | |
6320 | assemble_name (asm_out_file, name); | |
6321 | fputs ("\n", asm_out_file); | |
6322 | } | |
6323 | ||
6324 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function"); | |
6325 | ||
6326 | /* Start the definition proper. */ | |
6327 | assemble_name (asm_out_file, name); | |
6328 | fputs (":\n", asm_out_file); | |
6329 | } | |
6330 | ||
6331 | /* End a function definition started by mips_start_function_definition. */ | |
6332 | ||
6333 | static void | |
6334 | mips_end_function_definition (const char *name) | |
6335 | { | |
6336 | if (!flag_inhibit_size_directive) | |
6337 | { | |
6338 | fputs ("\t.end\t", asm_out_file); | |
6339 | assemble_name (asm_out_file, name); | |
6340 | fputs ("\n", asm_out_file); | |
6341 | } | |
6342 | } | |
6d51cc90 RS |
6343 | |
6344 | /* If *STUB_PTR points to a stub, output a comdat-style definition for it, | |
6345 | then free *STUB_PTR. */ | |
78c27266 RS |
6346 | |
6347 | static void | |
6d51cc90 | 6348 | mips_finish_stub (mips_one_only_stub **stub_ptr) |
78c27266 | 6349 | { |
6d51cc90 RS |
6350 | mips_one_only_stub *stub = *stub_ptr; |
6351 | if (!stub) | |
6352 | return; | |
78c27266 | 6353 | |
6d51cc90 | 6354 | const char *name = stub->get_name (); |
78c27266 RS |
6355 | mips_start_unique_function (name); |
6356 | mips_start_function_definition (name, false); | |
6d51cc90 | 6357 | stub->output_body (); |
78c27266 | 6358 | mips_end_function_definition (name); |
6d51cc90 RS |
6359 | delete stub; |
6360 | *stub_ptr = 0; | |
78c27266 RS |
6361 | } |
6362 | \f | |
7462a715 RS |
6363 | /* Return true if calls to X can use R_MIPS_CALL* relocations. */ |
6364 | ||
6365 | static bool | |
6366 | mips_ok_for_lazy_binding_p (rtx x) | |
6367 | { | |
6368 | return (TARGET_USE_GOT | |
6369 | && GET_CODE (x) == SYMBOL_REF | |
08d0963a | 6370 | && !SYMBOL_REF_BIND_NOW_P (x) |
7462a715 RS |
6371 | && !mips_symbol_binds_local_p (x)); |
6372 | } | |
6373 | ||
08d0963a RS |
6374 | /* Load function address ADDR into register DEST. TYPE is as for |
6375 | mips_expand_call. Return true if we used an explicit lazy-binding | |
6376 | sequence. */ | |
7462a715 RS |
6377 | |
6378 | static bool | |
08d0963a | 6379 | mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr) |
7462a715 RS |
6380 | { |
6381 | /* If we're generating PIC, and this call is to a global function, | |
6382 | try to allow its address to be resolved lazily. This isn't | |
6383 | possible for sibcalls when $gp is call-saved because the value | |
6384 | of $gp on entry to the stub would be our caller's gp, not ours. */ | |
6385 | if (TARGET_EXPLICIT_RELOCS | |
08d0963a | 6386 | && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP) |
7462a715 RS |
6387 | && mips_ok_for_lazy_binding_p (addr)) |
6388 | { | |
08d0963a RS |
6389 | addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL); |
6390 | emit_insn (gen_rtx_SET (VOIDmode, dest, addr)); | |
7462a715 RS |
6391 | return true; |
6392 | } | |
6393 | else | |
6394 | { | |
6395 | mips_emit_move (dest, addr); | |
6396 | return false; | |
6397 | } | |
6398 | } | |
6399 | \f | |
2a22f99c TS |
6400 | struct local_alias_traits : default_hashmap_traits |
6401 | { | |
6402 | static hashval_t hash (rtx); | |
6403 | static bool equal_keys (rtx, rtx); | |
6404 | }; | |
6405 | ||
08d0963a RS |
6406 | /* Each locally-defined hard-float MIPS16 function has a local symbol |
6407 | associated with it. This hash table maps the function symbol (FUNC) | |
6408 | to the local symbol (LOCAL). */ | |
2a22f99c | 6409 | static GTY (()) hash_map<rtx, rtx, local_alias_traits> *mips16_local_aliases; |
08d0963a RS |
6410 | |
6411 | /* Hash table callbacks for mips16_local_aliases. */ | |
6412 | ||
2a22f99c TS |
6413 | hashval_t |
6414 | local_alias_traits::hash (rtx func) | |
08d0963a | 6415 | { |
2a22f99c | 6416 | return htab_hash_string (XSTR (func, 0)); |
08d0963a RS |
6417 | } |
6418 | ||
2a22f99c TS |
6419 | bool |
6420 | local_alias_traits::equal_keys (rtx func1, rtx func2) | |
08d0963a | 6421 | { |
2a22f99c | 6422 | return rtx_equal_p (func1, func2); |
08d0963a RS |
6423 | } |
6424 | ||
6425 | /* FUNC is the symbol for a locally-defined hard-float MIPS16 function. | |
6426 | Return a local alias for it, creating a new one if necessary. */ | |
6427 | ||
6428 | static rtx | |
6429 | mips16_local_alias (rtx func) | |
6430 | { | |
08d0963a RS |
6431 | /* Create the hash table if this is the first call. */ |
6432 | if (mips16_local_aliases == NULL) | |
2a22f99c TS |
6433 | mips16_local_aliases |
6434 | = hash_map<rtx, rtx, local_alias_traits>::create_ggc (37); | |
08d0963a RS |
6435 | |
6436 | /* Look up the function symbol, creating a new entry if need be. */ | |
2a22f99c TS |
6437 | bool existed; |
6438 | rtx *slot = &mips16_local_aliases->get_or_insert (func, &existed); | |
08d0963a RS |
6439 | gcc_assert (slot != NULL); |
6440 | ||
2a22f99c | 6441 | if (!existed) |
08d0963a RS |
6442 | { |
6443 | const char *func_name, *local_name; | |
6444 | rtx local; | |
6445 | ||
6446 | /* Create a new SYMBOL_REF for the local symbol. The choice of | |
6447 | __fn_local_* is based on the __fn_stub_* names that we've | |
6448 | traditionally used for the non-MIPS16 stub. */ | |
6449 | func_name = targetm.strip_name_encoding (XSTR (func, 0)); | |
6450 | local_name = ACONCAT (("__fn_local_", func_name, NULL)); | |
6451 | local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name)); | |
6452 | SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL; | |
6453 | ||
6454 | /* Create a new structure to represent the mapping. */ | |
2a22f99c | 6455 | *slot = local; |
08d0963a | 6456 | } |
2a22f99c | 6457 | return *slot; |
08d0963a RS |
6458 | } |
6459 | \f | |
65239d20 RS |
6460 | /* A chained list of functions for which mips16_build_call_stub has already |
6461 | generated a stub. NAME is the name of the function and FP_RET_P is true | |
6462 | if the function returns a value in floating-point registers. */ | |
6463 | struct mips16_stub { | |
ab77a036 RS |
6464 | struct mips16_stub *next; |
6465 | char *name; | |
65239d20 | 6466 | bool fp_ret_p; |
ab77a036 | 6467 | }; |
ab77a036 | 6468 | static struct mips16_stub *mips16_stubs; |
b4966b1b | 6469 | |
65239d20 RS |
6470 | /* Return the two-character string that identifies floating-point |
6471 | return mode MODE in the name of a MIPS16 function stub. */ | |
b4966b1b | 6472 | |
ab77a036 | 6473 | static const char * |
ef4bddc2 | 6474 | mips16_call_stub_mode_suffix (machine_mode mode) |
ab77a036 RS |
6475 | { |
6476 | if (mode == SFmode) | |
6477 | return "sf"; | |
6478 | else if (mode == DFmode) | |
6479 | return "df"; | |
6480 | else if (mode == SCmode) | |
6481 | return "sc"; | |
6482 | else if (mode == DCmode) | |
6483 | return "dc"; | |
6484 | else if (mode == V2SFmode) | |
6485 | return "df"; | |
6486 | else | |
6487 | gcc_unreachable (); | |
6488 | } | |
b4966b1b | 6489 | |
5b372d33 RS |
6490 | /* Write instructions to move a 32-bit value between general register |
6491 | GPREG and floating-point register FPREG. DIRECTION is 't' to move | |
6492 | from GPREG to FPREG and 'f' to move in the opposite direction. */ | |
6493 | ||
6494 | static void | |
6495 | mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
6496 | { | |
6497 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6498 | reg_names[gpreg], reg_names[fpreg]); | |
6499 | } | |
6500 | ||
6501 | /* Likewise for 64-bit values. */ | |
6502 | ||
6503 | static void | |
6504 | mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
6505 | { | |
6506 | if (TARGET_64BIT) | |
6507 | fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction, | |
6508 | reg_names[gpreg], reg_names[fpreg]); | |
6509 | else if (TARGET_FLOAT64) | |
6510 | { | |
6511 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6512 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
6513 | fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction, | |
6514 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]); | |
6515 | } | |
6516 | else | |
6517 | { | |
6518 | /* Move the least-significant word. */ | |
6519 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6520 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
6521 | /* ...then the most significant word. */ | |
6522 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
6523 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]); | |
6524 | } | |
6525 | } | |
6526 | ||
6527 | /* Write out code to move floating-point arguments into or out of | |
23fdf75c | 6528 | general registers. FP_CODE is the code describing which arguments |
5b372d33 RS |
6529 | are present (see the comment above the definition of CUMULATIVE_ARGS |
6530 | in mips.h). DIRECTION is as for mips_output_32bit_xfer. */ | |
b4966b1b | 6531 | |
ab77a036 | 6532 | static void |
5b372d33 | 6533 | mips_output_args_xfer (int fp_code, char direction) |
ab77a036 | 6534 | { |
5b372d33 | 6535 | unsigned int gparg, fparg, f; |
ab77a036 | 6536 | CUMULATIVE_ARGS cum; |
b4966b1b | 6537 | |
65239d20 | 6538 | /* This code only works for o32 and o64. */ |
ab77a036 | 6539 | gcc_assert (TARGET_OLDABI); |
b4966b1b | 6540 | |
65239d20 | 6541 | mips_init_cumulative_args (&cum, NULL); |
b4966b1b | 6542 | |
ab77a036 RS |
6543 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
6544 | { | |
ef4bddc2 | 6545 | machine_mode mode; |
ab77a036 | 6546 | struct mips_arg_info info; |
b4966b1b | 6547 | |
ab77a036 RS |
6548 | if ((f & 3) == 1) |
6549 | mode = SFmode; | |
6550 | else if ((f & 3) == 2) | |
6551 | mode = DFmode; | |
6552 | else | |
6553 | gcc_unreachable (); | |
b4966b1b | 6554 | |
65239d20 | 6555 | mips_get_arg_info (&info, &cum, mode, NULL, true); |
ab77a036 RS |
6556 | gparg = mips_arg_regno (&info, false); |
6557 | fparg = mips_arg_regno (&info, true); | |
b4966b1b | 6558 | |
ab77a036 | 6559 | if (mode == SFmode) |
5b372d33 | 6560 | mips_output_32bit_xfer (direction, gparg, fparg); |
ab77a036 | 6561 | else |
5b372d33 | 6562 | mips_output_64bit_xfer (direction, gparg, fparg); |
b4966b1b | 6563 | |
d5cc9181 | 6564 | mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true); |
b4966b1b | 6565 | } |
b4966b1b RS |
6566 | } |
6567 | ||
65239d20 RS |
6568 | /* Write a MIPS16 stub for the current function. This stub is used |
6569 | for functions which take arguments in the floating-point registers. | |
6570 | It is normal-mode code that moves the floating-point arguments | |
6571 | into the general registers and then jumps to the MIPS16 code. */ | |
b4966b1b | 6572 | |
ab77a036 | 6573 | static void |
65239d20 | 6574 | mips16_build_function_stub (void) |
b4966b1b | 6575 | { |
08d0963a | 6576 | const char *fnname, *alias_name, *separator; |
ab77a036 | 6577 | char *secname, *stubname; |
65239d20 | 6578 | tree stubdecl; |
ab77a036 | 6579 | unsigned int f; |
08d0963a | 6580 | rtx symbol, alias; |
b4966b1b | 6581 | |
65239d20 | 6582 | /* Create the name of the stub, and its unique section. */ |
08d0963a RS |
6583 | symbol = XEXP (DECL_RTL (current_function_decl), 0); |
6584 | alias = mips16_local_alias (symbol); | |
6585 | ||
6586 | fnname = targetm.strip_name_encoding (XSTR (symbol, 0)); | |
6587 | alias_name = targetm.strip_name_encoding (XSTR (alias, 0)); | |
65239d20 RS |
6588 | secname = ACONCAT ((".mips16.fn.", fnname, NULL)); |
6589 | stubname = ACONCAT (("__fn_stub_", fnname, NULL)); | |
6590 | ||
6591 | /* Build a decl for the stub. */ | |
4c4bde29 AH |
6592 | stubdecl = build_decl (BUILTINS_LOCATION, |
6593 | FUNCTION_DECL, get_identifier (stubname), | |
b861891b | 6594 | build_function_type_list (void_type_node, NULL_TREE)); |
f961457f | 6595 | set_decl_section_name (stubdecl, secname); |
4c4bde29 AH |
6596 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6597 | RESULT_DECL, NULL_TREE, void_type_node); | |
b4966b1b | 6598 | |
65239d20 | 6599 | /* Output a comment. */ |
23fdf75c RS |
6600 | fprintf (asm_out_file, "\t# Stub function for %s (", |
6601 | current_function_name ()); | |
65239d20 | 6602 | separator = ""; |
38173d38 | 6603 | for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2) |
b4966b1b | 6604 | { |
65239d20 | 6605 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6606 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6607 | separator = ", "; |
b4966b1b | 6608 | } |
23fdf75c | 6609 | fprintf (asm_out_file, ")\n"); |
9226543b | 6610 | |
b2b61607 RS |
6611 | /* Start the function definition. */ |
6612 | assemble_start_function (stubdecl, stubname); | |
6613 | mips_start_function_definition (stubname, false); | |
e689b870 | 6614 | |
e21d5757 DJ |
6615 | /* If generating pic2 code, either set up the global pointer or |
6616 | switch to pic0. */ | |
6617 | if (TARGET_ABICALLS_PIC2) | |
08d0963a | 6618 | { |
e21d5757 DJ |
6619 | if (TARGET_ABSOLUTE_ABICALLS) |
6620 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
6621 | else | |
6622 | { | |
6623 | output_asm_insn ("%(.cpload\t%^%)", NULL); | |
6624 | /* Emit an R_MIPS_NONE relocation to tell the linker what the | |
6625 | target function is. Use a local GOT access when loading the | |
6626 | symbol, to cut down on the number of unnecessary GOT entries | |
6627 | for stubs that aren't needed. */ | |
6628 | output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol); | |
6629 | symbol = alias; | |
6630 | } | |
08d0963a RS |
6631 | } |
6632 | ||
e21d5757 | 6633 | /* Load the address of the MIPS16 function into $25. Do this first so |
6a68a258 RS |
6634 | that targets with coprocessor interlocks can use an MFC1 to fill the |
6635 | delay slot. */ | |
e21d5757 | 6636 | output_asm_insn ("la\t%^,%0", &symbol); |
e689b870 | 6637 | |
65239d20 | 6638 | /* Move the arguments from floating-point registers to general registers. */ |
38173d38 | 6639 | mips_output_args_xfer (crtl->args.info.fp_code, 'f'); |
e689b870 | 6640 | |
65239d20 | 6641 | /* Jump to the MIPS16 function. */ |
e21d5757 | 6642 | output_asm_insn ("jr\t%^", NULL); |
d8934cf1 | 6643 | |
e21d5757 | 6644 | if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS) |
08d0963a RS |
6645 | fprintf (asm_out_file, "\t.option\tpic2\n"); |
6646 | ||
b2b61607 | 6647 | mips_end_function_definition (stubname); |
e689b870 | 6648 | |
08d0963a RS |
6649 | /* If the linker needs to create a dynamic symbol for the target |
6650 | function, it will associate the symbol with the stub (which, | |
6651 | unlike the target function, follows the proper calling conventions). | |
6652 | It is therefore useful to have a local alias for the target function, | |
6653 | so that it can still be identified as MIPS16 code. As an optimization, | |
6654 | this symbol can also be used for indirect MIPS16 references from | |
6655 | within this file. */ | |
6656 | ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname); | |
6657 | ||
ab77a036 | 6658 | switch_to_section (function_section (current_function_decl)); |
e689b870 DU |
6659 | } |
6660 | ||
5f5fe6d9 RS |
6661 | /* The current function is a MIPS16 function that returns a value in an FPR. |
6662 | Copy the return value from its soft-float to its hard-float location. | |
6663 | libgcc2 has special non-MIPS16 helper functions for each case. */ | |
6664 | ||
6665 | static void | |
6666 | mips16_copy_fpr_return_value (void) | |
6667 | { | |
08d0963a RS |
6668 | rtx fn, insn, retval; |
6669 | tree return_type; | |
ef4bddc2 | 6670 | machine_mode return_mode; |
08d0963a | 6671 | const char *name; |
5f5fe6d9 RS |
6672 | |
6673 | return_type = DECL_RESULT (current_function_decl); | |
6674 | return_mode = DECL_MODE (return_type); | |
6675 | ||
08d0963a RS |
6676 | name = ACONCAT (("__mips16_ret_", |
6677 | mips16_call_stub_mode_suffix (return_mode), | |
6678 | NULL)); | |
6679 | fn = mips16_stub_function (name); | |
6680 | ||
6681 | /* The function takes arguments in $2 (and possibly $3), so calls | |
6682 | to it cannot be lazily bound. */ | |
6683 | SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW; | |
6684 | ||
6685 | /* Model the call as something that takes the GPR return value as | |
6686 | argument and returns an "updated" value. */ | |
6687 | retval = gen_rtx_REG (return_mode, GP_RETURN); | |
6688 | insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn, | |
6689 | const0_rtx, NULL_RTX, false); | |
6690 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval); | |
5f5fe6d9 RS |
6691 | } |
6692 | ||
08d0963a | 6693 | /* Consider building a stub for a MIPS16 call to function *FN_PTR. |
65239d20 RS |
6694 | RETVAL is the location of the return value, or null if this is |
6695 | a "call" rather than a "call_value". ARGS_SIZE is the size of the | |
6696 | arguments and FP_CODE is the code built by mips_function_arg; | |
b53da244 | 6697 | see the comment before the fp_code field in CUMULATIVE_ARGS for details. |
d33289b2 | 6698 | |
08d0963a RS |
6699 | There are three alternatives: |
6700 | ||
6701 | - If a stub was needed, emit the call and return the call insn itself. | |
6702 | ||
6703 | - If we can avoid using a stub by redirecting the call, set *FN_PTR | |
6704 | to the new target and return null. | |
6705 | ||
6706 | - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR | |
6707 | unmodified. | |
f9e4a411 | 6708 | |
65239d20 RS |
6709 | A stub is needed for calls to functions that, in normal mode, |
6710 | receive arguments in FPRs or return values in FPRs. The stub | |
6711 | copies the arguments from their soft-float positions to their | |
6712 | hard-float positions, calls the real function, then copies the | |
6713 | return value from its hard-float position to its soft-float | |
6714 | position. | |
f9e4a411 | 6715 | |
08d0963a RS |
6716 | We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub. |
6717 | If *FN_PTR turns out to be to a non-MIPS16 function, the linker | |
6718 | automatically redirects the JAL to the stub, otherwise the JAL | |
6719 | continues to call FN directly. */ | |
65239d20 | 6720 | |
c6f971f4 | 6721 | static rtx_insn * |
08d0963a | 6722 | mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code) |
f9e4a411 | 6723 | { |
ab77a036 | 6724 | const char *fnname; |
65239d20 | 6725 | bool fp_ret_p; |
ab77a036 | 6726 | struct mips16_stub *l; |
c6f971f4 DM |
6727 | rtx_insn *insn; |
6728 | rtx pattern, fn; | |
f9e4a411 | 6729 | |
65239d20 | 6730 | /* We don't need to do anything if we aren't in MIPS16 mode, or if |
ab77a036 RS |
6731 | we were invoked with the -msoft-float option. */ |
6732 | if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI) | |
c6f971f4 | 6733 | return NULL; |
f9e4a411 | 6734 | |
65239d20 | 6735 | /* Figure out whether the value might come back in a floating-point |
ab77a036 | 6736 | register. */ |
65239d20 | 6737 | fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval)); |
f9e4a411 | 6738 | |
65239d20 RS |
6739 | /* We don't need to do anything if there were no floating-point |
6740 | arguments and the value will not be returned in a floating-point | |
ab77a036 | 6741 | register. */ |
65239d20 | 6742 | if (fp_code == 0 && !fp_ret_p) |
c6f971f4 | 6743 | return NULL; |
f9e4a411 | 6744 | |
ab77a036 | 6745 | /* We don't need to do anything if this is a call to a special |
65239d20 | 6746 | MIPS16 support function. */ |
08d0963a RS |
6747 | fn = *fn_ptr; |
6748 | if (mips16_stub_function_p (fn)) | |
c6f971f4 | 6749 | return NULL; |
f9e4a411 | 6750 | |
62835cee RS |
6751 | /* If we're calling a locally-defined MIPS16 function, we know that |
6752 | it will return values in both the "soft-float" and "hard-float" | |
6753 | registers. There is no need to use a stub to move the latter | |
6754 | to the former. */ | |
6755 | if (fp_code == 0 && mips16_local_function_p (fn)) | |
c6f971f4 | 6756 | return NULL; |
62835cee | 6757 | |
ab77a036 RS |
6758 | /* This code will only work for o32 and o64 abis. The other ABI's |
6759 | require more sophisticated support. */ | |
6760 | gcc_assert (TARGET_OLDABI); | |
f9e4a411 | 6761 | |
65239d20 RS |
6762 | /* If we're calling via a function pointer, use one of the magic |
6763 | libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination. | |
6764 | Each stub expects the function address to arrive in register $2. */ | |
08d0963a RS |
6765 | if (GET_CODE (fn) != SYMBOL_REF |
6766 | || !call_insn_operand (fn, VOIDmode)) | |
f9e4a411 | 6767 | { |
ab77a036 | 6768 | char buf[30]; |
c6f971f4 DM |
6769 | rtx stub_fn, addr; |
6770 | rtx_insn *insn; | |
08d0963a RS |
6771 | bool lazy_p; |
6772 | ||
6773 | /* If this is a locally-defined and locally-binding function, | |
6774 | avoid the stub by calling the local alias directly. */ | |
6775 | if (mips16_local_function_p (fn)) | |
6776 | { | |
6777 | *fn_ptr = mips16_local_alias (fn); | |
c6f971f4 | 6778 | return NULL; |
08d0963a | 6779 | } |
f9e4a411 | 6780 | |
65239d20 RS |
6781 | /* Create a SYMBOL_REF for the libgcc.a function. */ |
6782 | if (fp_ret_p) | |
ab77a036 RS |
6783 | sprintf (buf, "__mips16_call_stub_%s_%d", |
6784 | mips16_call_stub_mode_suffix (GET_MODE (retval)), | |
6785 | fp_code); | |
f9e4a411 | 6786 | else |
65239d20 | 6787 | sprintf (buf, "__mips16_call_stub_%d", fp_code); |
08d0963a RS |
6788 | stub_fn = mips16_stub_function (buf); |
6789 | ||
6790 | /* The function uses $2 as an argument, so calls to it | |
6791 | cannot be lazily bound. */ | |
6792 | SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW; | |
f9e4a411 | 6793 | |
65239d20 | 6794 | /* Load the target function into $2. */ |
08d0963a RS |
6795 | addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); |
6796 | lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn); | |
f9e4a411 | 6797 | |
65239d20 | 6798 | /* Emit the call. */ |
08d0963a RS |
6799 | insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn, |
6800 | args_size, NULL_RTX, lazy_p); | |
f9e4a411 | 6801 | |
65239d20 | 6802 | /* Tell GCC that this call does indeed use the value of $2. */ |
08d0963a | 6803 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr); |
f9e4a411 | 6804 | |
65239d20 | 6805 | /* If we are handling a floating-point return value, we need to |
ab77a036 RS |
6806 | save $18 in the function prologue. Putting a note on the |
6807 | call will mean that df_regs_ever_live_p ($18) will be true if the | |
6808 | call is not eliminated, and we can check that in the prologue | |
6809 | code. */ | |
65239d20 | 6810 | if (fp_ret_p) |
ab77a036 RS |
6811 | CALL_INSN_FUNCTION_USAGE (insn) = |
6812 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6813 | gen_rtx_CLOBBER (VOIDmode, |
6814 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6815 | CALL_INSN_FUNCTION_USAGE (insn)); |
f9e4a411 | 6816 | |
dbc90b65 | 6817 | return insn; |
ab77a036 | 6818 | } |
f9e4a411 | 6819 | |
ab77a036 RS |
6820 | /* We know the function we are going to call. If we have already |
6821 | built a stub, we don't need to do anything further. */ | |
ab77a036 RS |
6822 | fnname = targetm.strip_name_encoding (XSTR (fn, 0)); |
6823 | for (l = mips16_stubs; l != NULL; l = l->next) | |
6824 | if (strcmp (l->name, fnname) == 0) | |
6825 | break; | |
d33289b2 | 6826 | |
ab77a036 | 6827 | if (l == NULL) |
f9e4a411 | 6828 | { |
65239d20 RS |
6829 | const char *separator; |
6830 | char *secname, *stubname; | |
6831 | tree stubid, stubdecl; | |
6832 | unsigned int f; | |
8d1d0dee | 6833 | |
65239d20 | 6834 | /* If the function does not return in FPRs, the special stub |
ab77a036 | 6835 | section is named |
65239d20 RS |
6836 | .mips16.call.FNNAME |
6837 | ||
6838 | If the function does return in FPRs, the stub section is named | |
ab77a036 | 6839 | .mips16.call.fp.FNNAME |
f9e4a411 | 6840 | |
65239d20 RS |
6841 | Build a decl for the stub. */ |
6842 | secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "", | |
6843 | fnname, NULL)); | |
6844 | stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "", | |
6845 | fnname, NULL)); | |
ab77a036 | 6846 | stubid = get_identifier (stubname); |
4c4bde29 AH |
6847 | stubdecl = build_decl (BUILTINS_LOCATION, |
6848 | FUNCTION_DECL, stubid, | |
b861891b NF |
6849 | build_function_type_list (void_type_node, |
6850 | NULL_TREE)); | |
f961457f | 6851 | set_decl_section_name (stubdecl, secname); |
4c4bde29 AH |
6852 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6853 | RESULT_DECL, NULL_TREE, | |
65239d20 | 6854 | void_type_node); |
9a6dfb47 | 6855 | |
65239d20 | 6856 | /* Output a comment. */ |
ab77a036 | 6857 | fprintf (asm_out_file, "\t# Stub function to call %s%s (", |
65239d20 | 6858 | (fp_ret_p |
ab77a036 RS |
6859 | ? (GET_MODE (retval) == SFmode ? "float " : "double ") |
6860 | : ""), | |
6861 | fnname); | |
65239d20 | 6862 | separator = ""; |
ab77a036 RS |
6863 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
6864 | { | |
65239d20 | 6865 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6866 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6867 | separator = ", "; |
ab77a036 RS |
6868 | } |
6869 | fprintf (asm_out_file, ")\n"); | |
f9e4a411 | 6870 | |
b2b61607 | 6871 | /* Start the function definition. */ |
ab77a036 | 6872 | assemble_start_function (stubdecl, stubname); |
b2b61607 | 6873 | mips_start_function_definition (stubname, false); |
8ce4afa3 | 6874 | |
5adeb246 RS |
6875 | if (fp_ret_p) |
6876 | { | |
6877 | fprintf (asm_out_file, "\t.cfi_startproc\n"); | |
6878 | ||
6879 | /* Create a fake CFA 4 bytes below the stack pointer. | |
6880 | This works around unwinders (like libgcc's) that expect | |
6881 | the CFA for non-signal frames to be unique. */ | |
6882 | fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n"); | |
6883 | ||
6884 | /* "Save" $sp in itself so we don't use the fake CFA. | |
6885 | This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */ | |
6886 | fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n"); | |
6887 | } | |
6888 | else | |
ab77a036 | 6889 | { |
e21d5757 | 6890 | /* Load the address of the MIPS16 function into $25. Do this |
6a68a258 RS |
6891 | first so that targets with coprocessor interlocks can use |
6892 | an MFC1 to fill the delay slot. */ | |
08d0963a RS |
6893 | if (TARGET_EXPLICIT_RELOCS) |
6894 | { | |
6895 | output_asm_insn ("lui\t%^,%%hi(%0)", &fn); | |
6896 | output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn); | |
6897 | } | |
6898 | else | |
6899 | output_asm_insn ("la\t%^,%0", &fn); | |
6a68a258 RS |
6900 | } |
6901 | ||
65239d20 RS |
6902 | /* Move the arguments from general registers to floating-point |
6903 | registers. */ | |
6a68a258 RS |
6904 | mips_output_args_xfer (fp_code, 't'); |
6905 | ||
5adeb246 | 6906 | if (fp_ret_p) |
ab77a036 | 6907 | { |
65239d20 RS |
6908 | /* Save the return address in $18 and call the non-MIPS16 function. |
6909 | The stub's caller knows that $18 might be clobbered, even though | |
6910 | $18 is usually a call-saved register. */ | |
ab77a036 | 6911 | fprintf (asm_out_file, "\tmove\t%s,%s\n", |
293593b1 | 6912 | reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]); |
b53da244 | 6913 | output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn); |
5adeb246 | 6914 | fprintf (asm_out_file, "\t.cfi_register 31,18\n"); |
65239d20 RS |
6915 | |
6916 | /* Move the result from floating-point registers to | |
6917 | general registers. */ | |
ab77a036 RS |
6918 | switch (GET_MODE (retval)) |
6919 | { | |
6920 | case SCmode: | |
93f63c68 RS |
6921 | mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN, |
6922 | TARGET_BIG_ENDIAN | |
6923 | ? FP_REG_FIRST + MAX_FPRS_PER_FMT | |
6924 | : FP_REG_FIRST); | |
6925 | mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN, | |
6926 | TARGET_LITTLE_ENDIAN | |
6927 | ? FP_REG_FIRST + MAX_FPRS_PER_FMT | |
6928 | : FP_REG_FIRST); | |
ab77a036 RS |
6929 | if (GET_MODE (retval) == SCmode && TARGET_64BIT) |
6930 | { | |
6931 | /* On 64-bit targets, complex floats are returned in | |
6932 | a single GPR, such that "sd" on a suitably-aligned | |
6933 | target would store the value correctly. */ | |
93f63c68 RS |
6934 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", |
6935 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN], | |
6936 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); | |
ab77a036 | 6937 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", |
5b372d33 RS |
6938 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN], |
6939 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]); | |
93f63c68 RS |
6940 | fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n", |
6941 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN], | |
6942 | reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); | |
ab77a036 | 6943 | fprintf (asm_out_file, "\tor\t%s,%s,%s\n", |
5b372d33 RS |
6944 | reg_names[GP_RETURN], |
6945 | reg_names[GP_RETURN], | |
6946 | reg_names[GP_RETURN + 1]); | |
ab77a036 RS |
6947 | } |
6948 | break; | |
f9e4a411 | 6949 | |
93f63c68 RS |
6950 | case SFmode: |
6951 | mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST); | |
6952 | break; | |
6953 | ||
ab77a036 | 6954 | case DCmode: |
5b372d33 RS |
6955 | mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD), |
6956 | FP_REG_FIRST + MAX_FPRS_PER_FMT); | |
ab77a036 RS |
6957 | /* Fall though. */ |
6958 | case DFmode: | |
6959 | case V2SFmode: | |
5b372d33 | 6960 | mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST); |
ab77a036 | 6961 | break; |
9a6dfb47 | 6962 | |
ab77a036 RS |
6963 | default: |
6964 | gcc_unreachable (); | |
6965 | } | |
65239d20 | 6966 | fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]); |
5adeb246 RS |
6967 | fprintf (asm_out_file, "\t.cfi_endproc\n"); |
6968 | } | |
6969 | else | |
6970 | { | |
6971 | /* Jump to the previously-loaded address. */ | |
6972 | output_asm_insn ("jr\t%^", NULL); | |
ab77a036 | 6973 | } |
9a6dfb47 | 6974 | |
ab77a036 RS |
6975 | #ifdef ASM_DECLARE_FUNCTION_SIZE |
6976 | ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); | |
6977 | #endif | |
9a6dfb47 | 6978 | |
b2b61607 | 6979 | mips_end_function_definition (stubname); |
9a6dfb47 | 6980 | |
ab77a036 | 6981 | /* Record this stub. */ |
65239d20 | 6982 | l = XNEW (struct mips16_stub); |
ab77a036 | 6983 | l->name = xstrdup (fnname); |
65239d20 | 6984 | l->fp_ret_p = fp_ret_p; |
ab77a036 RS |
6985 | l->next = mips16_stubs; |
6986 | mips16_stubs = l; | |
6987 | } | |
9a6dfb47 | 6988 | |
65239d20 | 6989 | /* If we expect a floating-point return value, but we've built a |
ab77a036 | 6990 | stub which does not expect one, then we're in trouble. We can't |
65239d20 | 6991 | use the existing stub, because it won't handle the floating-point |
ab77a036 RS |
6992 | value. We can't build a new stub, because the linker won't know |
6993 | which stub to use for the various calls in this object file. | |
6994 | Fortunately, this case is illegal, since it means that a function | |
6995 | was declared in two different ways in a single compilation. */ | |
65239d20 | 6996 | if (fp_ret_p && !l->fp_ret_p) |
ab77a036 | 6997 | error ("cannot handle inconsistent calls to %qs", fnname); |
9a6dfb47 | 6998 | |
ab77a036 | 6999 | if (retval == NULL_RTX) |
c6f971f4 | 7000 | pattern = gen_call_internal_direct (fn, args_size); |
ab77a036 | 7001 | else |
c6f971f4 DM |
7002 | pattern = gen_call_value_internal_direct (retval, fn, args_size); |
7003 | insn = mips_emit_call_insn (pattern, fn, fn, false); | |
9a6dfb47 | 7004 | |
65239d20 RS |
7005 | /* If we are calling a stub which handles a floating-point return |
7006 | value, we need to arrange to save $18 in the prologue. We do this | |
7007 | by marking the function call as using the register. The prologue | |
7008 | will later see that it is used, and emit code to save it. */ | |
7009 | if (fp_ret_p) | |
ab77a036 RS |
7010 | CALL_INSN_FUNCTION_USAGE (insn) = |
7011 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
7012 | gen_rtx_CLOBBER (VOIDmode, |
7013 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 7014 | CALL_INSN_FUNCTION_USAGE (insn)); |
9a6dfb47 | 7015 | |
dbc90b65 | 7016 | return insn; |
9a6dfb47 | 7017 | } |
ab77a036 | 7018 | \f |
08d0963a RS |
7019 | /* Expand a call of type TYPE. RESULT is where the result will go (null |
7020 | for "call"s and "sibcall"s), ADDR is the address of the function, | |
7021 | ARGS_SIZE is the size of the arguments and AUX is the value passed | |
7022 | to us by mips_function_arg. LAZY_P is true if this call already | |
7023 | involves a lazily-bound function address (such as when calling | |
7024 | functions through a MIPS16 hard-float stub). | |
f9e4a411 | 7025 | |
dbc90b65 RS |
7026 | Return the call itself. */ |
7027 | ||
c6f971f4 | 7028 | rtx_insn * |
08d0963a RS |
7029 | mips_expand_call (enum mips_call_type type, rtx result, rtx addr, |
7030 | rtx args_size, rtx aux, bool lazy_p) | |
f9e4a411 | 7031 | { |
c6f971f4 DM |
7032 | rtx orig_addr, pattern; |
7033 | rtx_insn *insn; | |
08d0963a | 7034 | int fp_code; |
d522e7a2 | 7035 | |
08d0963a RS |
7036 | fp_code = aux == 0 ? 0 : (int) GET_MODE (aux); |
7037 | insn = mips16_build_call_stub (result, &addr, args_size, fp_code); | |
7038 | if (insn) | |
7039 | { | |
7040 | gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL); | |
7041 | return insn; | |
7042 | } | |
da582d46 | 7043 | |
ab77a036 | 7044 | orig_addr = addr; |
ab77a036 | 7045 | if (!call_insn_operand (addr, VOIDmode)) |
d522e7a2 | 7046 | { |
08d0963a RS |
7047 | if (type == MIPS_CALL_EPILOGUE) |
7048 | addr = MIPS_EPILOGUE_TEMP (Pmode); | |
7049 | else | |
7050 | addr = gen_reg_rtx (Pmode); | |
7051 | lazy_p |= mips_load_call_address (type, addr, orig_addr); | |
ab77a036 | 7052 | } |
d522e7a2 | 7053 | |
08d0963a | 7054 | if (result == 0) |
65239d20 | 7055 | { |
08d0963a | 7056 | rtx (*fn) (rtx, rtx); |
d522e7a2 | 7057 | |
0c433c31 | 7058 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
7059 | fn = gen_sibcall_internal; |
7060 | else | |
7061 | fn = gen_call_internal; | |
7062 | ||
7063 | pattern = fn (addr, args_size); | |
7064 | } | |
ab77a036 RS |
7065 | else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) |
7066 | { | |
fd0d4c1f | 7067 | /* Handle return values created by mips_return_fpr_pair. */ |
08d0963a | 7068 | rtx (*fn) (rtx, rtx, rtx, rtx); |
ab77a036 | 7069 | rtx reg1, reg2; |
d522e7a2 | 7070 | |
0c433c31 | 7071 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
7072 | fn = gen_sibcall_value_multiple_internal; |
7073 | else | |
7074 | fn = gen_call_value_multiple_internal; | |
7075 | ||
ab77a036 RS |
7076 | reg1 = XEXP (XVECEXP (result, 0, 0), 0); |
7077 | reg2 = XEXP (XVECEXP (result, 0, 1), 0); | |
08d0963a | 7078 | pattern = fn (reg1, addr, args_size, reg2); |
ab77a036 RS |
7079 | } |
7080 | else | |
fd0d4c1f | 7081 | { |
08d0963a RS |
7082 | rtx (*fn) (rtx, rtx, rtx); |
7083 | ||
0c433c31 | 7084 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
7085 | fn = gen_sibcall_value_internal; |
7086 | else | |
7087 | fn = gen_call_value_internal; | |
7088 | ||
fd0d4c1f RS |
7089 | /* Handle return values created by mips_return_fpr_single. */ |
7090 | if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) | |
7091 | result = XEXP (XVECEXP (result, 0, 0), 0); | |
08d0963a | 7092 | pattern = fn (result, addr, args_size); |
fd0d4c1f | 7093 | } |
d522e7a2 | 7094 | |
08d0963a RS |
7095 | return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p); |
7096 | } | |
7097 | ||
7098 | /* Split call instruction INSN into a $gp-clobbering call and | |
7099 | (where necessary) an instruction to restore $gp from its save slot. | |
7100 | CALL_PATTERN is the pattern of the new call. */ | |
7101 | ||
7102 | void | |
7103 | mips_split_call (rtx insn, rtx call_pattern) | |
7104 | { | |
82220036 | 7105 | emit_call_insn (call_pattern); |
08d0963a | 7106 | if (!find_reg_note (insn, REG_NORETURN, 0)) |
c2db3f3d RO |
7107 | mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, |
7108 | POST_CALL_TMP_REG)); | |
d522e7a2 | 7109 | } |
a27fb29b | 7110 | |
22c4c869 CM |
7111 | /* Return true if a call to DECL may need to use JALX. */ |
7112 | ||
7113 | static bool | |
7114 | mips_call_may_need_jalx_p (tree decl) | |
7115 | { | |
7116 | /* If the current translation unit would use a different mode for DECL, | |
7117 | assume that the call needs JALX. */ | |
7118 | if (mips_get_compress_mode (decl) != TARGET_COMPRESSION) | |
7119 | return true; | |
7120 | ||
7121 | /* mips_get_compress_mode is always accurate for locally-binding | |
7122 | functions in the current translation unit. */ | |
7123 | if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl)) | |
7124 | return false; | |
7125 | ||
7126 | /* When -minterlink-compressed is in effect, assume that functions | |
7127 | could use a different encoding mode unless an attribute explicitly | |
7128 | tells us otherwise. */ | |
7129 | if (TARGET_INTERLINK_COMPRESSED) | |
7130 | { | |
7131 | if (!TARGET_COMPRESSION | |
7132 | && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0) | |
7133 | return true; | |
7134 | if (TARGET_COMPRESSION | |
7135 | && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0) | |
7136 | return true; | |
7137 | } | |
7138 | ||
7139 | return false; | |
7140 | } | |
7141 | ||
ab77a036 RS |
7142 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ |
7143 | ||
7144 | static bool | |
7145 | mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) | |
cee98a59 | 7146 | { |
ab77a036 RS |
7147 | if (!TARGET_SIBCALLS) |
7148 | return false; | |
cee98a59 | 7149 | |
e19da24c CF |
7150 | /* Interrupt handlers need special epilogue code and therefore can't |
7151 | use sibcalls. */ | |
7152 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
7153 | return false; | |
7154 | ||
22c4c869 CM |
7155 | /* Direct Js are only possible to functions that use the same ISA encoding. |
7156 | There is no JX counterpoart of JALX. */ | |
cf900097 | 7157 | if (decl |
22c4c869 CM |
7158 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode) |
7159 | && mips_call_may_need_jalx_p (decl)) | |
ab77a036 | 7160 | return false; |
cee98a59 | 7161 | |
e299a383 RS |
7162 | /* Sibling calls should not prevent lazy binding. Lazy-binding stubs |
7163 | require $gp to be valid on entry, so sibcalls can only use stubs | |
7164 | if $gp is call-clobbered. */ | |
7165 | if (decl | |
7166 | && TARGET_CALL_SAVED_GP | |
7167 | && !TARGET_ABICALLS_PIC0 | |
7168 | && !targetm.binds_local_p (decl)) | |
7169 | return false; | |
7170 | ||
ab77a036 RS |
7171 | /* Otherwise OK. */ |
7172 | return true; | |
7173 | } | |
7174 | \f | |
0d8f5d62 RS |
7175 | /* Implement MOVE_BY_PIECES_P. */ |
7176 | ||
7177 | bool | |
7178 | mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) | |
7179 | { | |
7180 | if (HAVE_movmemsi) | |
7181 | { | |
7182 | /* movmemsi is meant to generate code that is at least as good as | |
7183 | move_by_pieces. However, movmemsi effectively uses a by-pieces | |
7184 | implementation both for moves smaller than a word and for | |
7185 | word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT | |
7186 | bytes. We should allow the tree-level optimisers to do such | |
7187 | moves by pieces, as it often exposes other optimization | |
7188 | opportunities. We might as well continue to use movmemsi at | |
7189 | the rtl level though, as it produces better code when | |
7190 | scheduling is disabled (such as at -O). */ | |
7191 | if (currently_expanding_to_rtl) | |
7192 | return false; | |
7193 | if (align < BITS_PER_WORD) | |
7194 | return size < UNITS_PER_WORD; | |
7195 | return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT; | |
7196 | } | |
7197 | /* The default value. If this becomes a target hook, we should | |
7198 | call the default definition instead. */ | |
7199 | return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1) | |
7200 | < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ())); | |
7201 | } | |
7202 | ||
7203 | /* Implement STORE_BY_PIECES_P. */ | |
7204 | ||
7205 | bool | |
7206 | mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) | |
7207 | { | |
7208 | /* Storing by pieces involves moving constants into registers | |
7209 | of size MIN (ALIGN, BITS_PER_WORD), then storing them. | |
7210 | We need to decide whether it is cheaper to load the address of | |
7211 | constant data into a register and use a block move instead. */ | |
7212 | ||
7213 | /* If the data is only byte aligned, then: | |
7214 | ||
7215 | (a1) A block move of less than 4 bytes would involve three 3 LBs and | |
7216 | 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs | |
7217 | instead. | |
7218 | ||
7219 | (a2) A block move of 4 bytes from aligned source data can use an | |
7220 | LW/SWL/SWR sequence. This is often better than the 4 LIs and | |
7221 | 4 SBs that we would generate when storing by pieces. */ | |
7222 | if (align <= BITS_PER_UNIT) | |
7223 | return size < 4; | |
7224 | ||
7225 | /* If the data is 2-byte aligned, then: | |
7226 | ||
7227 | (b1) A block move of less than 4 bytes would use a combination of LBs, | |
7228 | LHs, SBs and SHs. We get better code by using single-instruction | |
7229 | LIs, SBs and SHs instead. | |
7230 | ||
7231 | (b2) A block move of 4 bytes from aligned source data would again use | |
7232 | an LW/SWL/SWR sequence. In most cases, loading the address of | |
7233 | the source data would require at least one extra instruction. | |
7234 | It is often more efficient to use 2 single-instruction LIs and | |
7235 | 2 SHs instead. | |
7236 | ||
7237 | (b3) A block move of up to 3 additional bytes would be like (b1). | |
7238 | ||
7239 | (b4) A block move of 8 bytes from aligned source data can use two | |
7240 | LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both | |
7241 | sequences are better than the 4 LIs and 4 SHs that we'd generate | |
7242 | when storing by pieces. | |
7243 | ||
7244 | The reasoning for higher alignments is similar: | |
7245 | ||
7246 | (c1) A block move of less than 4 bytes would be the same as (b1). | |
7247 | ||
7248 | (c2) A block move of 4 bytes would use an LW/SW sequence. Again, | |
7249 | loading the address of the source data would typically require | |
7250 | at least one extra instruction. It is generally better to use | |
7251 | LUI/ORI/SW instead. | |
7252 | ||
7253 | (c3) A block move of up to 3 additional bytes would be like (b1). | |
7254 | ||
7255 | (c4) A block move of 8 bytes can use two LW/SW sequences or a single | |
7256 | LD/SD sequence, and in these cases we've traditionally preferred | |
7257 | the memory copy over the more bulky constant moves. */ | |
7258 | return size < 8; | |
7259 | } | |
7260 | ||
ab77a036 RS |
7261 | /* Emit straight-line code to move LENGTH bytes from SRC to DEST. |
7262 | Assume that the areas do not overlap. */ | |
7dac2f89 | 7263 | |
ab77a036 RS |
7264 | static void |
7265 | mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) | |
7266 | { | |
7267 | HOST_WIDE_INT offset, delta; | |
7268 | unsigned HOST_WIDE_INT bits; | |
7269 | int i; | |
ef4bddc2 | 7270 | machine_mode mode; |
ab77a036 RS |
7271 | rtx *regs; |
7272 | ||
7273 | /* Work out how many bits to move at a time. If both operands have | |
7274 | half-word alignment, it is usually better to move in half words. | |
7275 | For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr | |
7276 | and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr. | |
7277 | Otherwise move word-sized chunks. */ | |
7278 | if (MEM_ALIGN (src) == BITS_PER_WORD / 2 | |
7279 | && MEM_ALIGN (dest) == BITS_PER_WORD / 2) | |
7280 | bits = BITS_PER_WORD / 2; | |
d81ecf52 | 7281 | else |
ab77a036 | 7282 | bits = BITS_PER_WORD; |
c1bd2d66 | 7283 | |
ab77a036 RS |
7284 | mode = mode_for_size (bits, MODE_INT, 0); |
7285 | delta = bits / BITS_PER_UNIT; | |
a05bea76 | 7286 | |
ab77a036 | 7287 | /* Allocate a buffer for the temporary registers. */ |
5ead67f6 | 7288 | regs = XALLOCAVEC (rtx, length / delta); |
ab77a036 RS |
7289 | |
7290 | /* Load as many BITS-sized chunks as possible. Use a normal load if | |
7291 | the source has enough alignment, otherwise use left/right pairs. */ | |
7292 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
cee98a59 | 7293 | { |
ab77a036 RS |
7294 | regs[i] = gen_reg_rtx (mode); |
7295 | if (MEM_ALIGN (src) >= bits) | |
7296 | mips_emit_move (regs[i], adjust_address (src, mode, offset)); | |
7dac2f89 | 7297 | else |
ab77a036 RS |
7298 | { |
7299 | rtx part = adjust_address (src, BLKmode, offset); | |
d2eeb2d1 | 7300 | set_mem_size (part, delta); |
aea21190 | 7301 | if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0)) |
ab77a036 RS |
7302 | gcc_unreachable (); |
7303 | } | |
a27fb29b | 7304 | } |
cee98a59 | 7305 | |
ab77a036 RS |
7306 | /* Copy the chunks to the destination. */ |
7307 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
7308 | if (MEM_ALIGN (dest) >= bits) | |
7309 | mips_emit_move (adjust_address (dest, mode, offset), regs[i]); | |
7310 | else | |
7311 | { | |
7312 | rtx part = adjust_address (dest, BLKmode, offset); | |
d2eeb2d1 | 7313 | set_mem_size (part, delta); |
65239d20 | 7314 | if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0)) |
ab77a036 RS |
7315 | gcc_unreachable (); |
7316 | } | |
7317 | ||
7318 | /* Mop up any left-over bytes. */ | |
7319 | if (offset < length) | |
a27fb29b | 7320 | { |
ab77a036 RS |
7321 | src = adjust_address (src, BLKmode, offset); |
7322 | dest = adjust_address (dest, BLKmode, offset); | |
7323 | move_by_pieces (dest, src, length - offset, | |
7324 | MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); | |
cee98a59 | 7325 | } |
ab77a036 | 7326 | } |
f8151871 | 7327 | |
ab77a036 RS |
7328 | /* Helper function for doing a loop-based block operation on memory |
7329 | reference MEM. Each iteration of the loop will operate on LENGTH | |
7330 | bytes of MEM. | |
cee98a59 | 7331 | |
ab77a036 RS |
7332 | Create a new base register for use within the loop and point it to |
7333 | the start of MEM. Create a new memory reference that uses this | |
7334 | register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ | |
33563487 | 7335 | |
ab77a036 RS |
7336 | static void |
7337 | mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, | |
7338 | rtx *loop_reg, rtx *loop_mem) | |
7339 | { | |
7340 | *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); | |
af34e51e | 7341 | |
ab77a036 RS |
7342 | /* Although the new mem does not refer to a known location, |
7343 | it does keep up to LENGTH bytes of alignment. */ | |
7344 | *loop_mem = change_address (mem, BLKmode, *loop_reg); | |
7345 | set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); | |
7346 | } | |
142ee136 | 7347 | |
a1c6b246 RS |
7348 | /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER |
7349 | bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that | |
7350 | the memory regions do not overlap. */ | |
d9870b7e | 7351 | |
ab77a036 | 7352 | static void |
a1c6b246 RS |
7353 | mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, |
7354 | HOST_WIDE_INT bytes_per_iter) | |
ab77a036 | 7355 | { |
c6f971f4 DM |
7356 | rtx_code_label *label; |
7357 | rtx src_reg, dest_reg, final_src, test; | |
ab77a036 | 7358 | HOST_WIDE_INT leftover; |
8cb6400c | 7359 | |
a1c6b246 | 7360 | leftover = length % bytes_per_iter; |
ab77a036 | 7361 | length -= leftover; |
dc884a86 | 7362 | |
ab77a036 | 7363 | /* Create registers and memory references for use within the loop. */ |
a1c6b246 RS |
7364 | mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); |
7365 | mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); | |
cfa31150 | 7366 | |
ab77a036 RS |
7367 | /* Calculate the value that SRC_REG should have after the last iteration |
7368 | of the loop. */ | |
7369 | final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), | |
7370 | 0, 0, OPTAB_WIDEN); | |
7371 | ||
7372 | /* Emit the start of the loop. */ | |
7373 | label = gen_label_rtx (); | |
7374 | emit_label (label); | |
7375 | ||
7376 | /* Emit the loop body. */ | |
a1c6b246 | 7377 | mips_block_move_straight (dest, src, bytes_per_iter); |
ab77a036 RS |
7378 | |
7379 | /* Move on to the next block. */ | |
0a81f074 RS |
7380 | mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); |
7381 | mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); | |
ab77a036 RS |
7382 | |
7383 | /* Emit the loop condition. */ | |
f90b7a5a | 7384 | test = gen_rtx_NE (VOIDmode, src_reg, final_src); |
ab77a036 | 7385 | if (Pmode == DImode) |
f90b7a5a | 7386 | emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); |
ab77a036 | 7387 | else |
f90b7a5a | 7388 | emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); |
ab77a036 RS |
7389 | |
7390 | /* Mop up any left-over bytes. */ | |
7391 | if (leftover) | |
7392 | mips_block_move_straight (dest, src, leftover); | |
7393 | } | |
7394 | ||
65239d20 RS |
7395 | /* Expand a movmemsi instruction, which copies LENGTH bytes from |
7396 | memory reference SRC to memory reference DEST. */ | |
ab77a036 RS |
7397 | |
7398 | bool | |
7399 | mips_expand_block_move (rtx dest, rtx src, rtx length) | |
7400 | { | |
47ac44d6 | 7401 | if (CONST_INT_P (length)) |
a318179e | 7402 | { |
a1c6b246 | 7403 | if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT) |
a318179e | 7404 | { |
ab77a036 RS |
7405 | mips_block_move_straight (dest, src, INTVAL (length)); |
7406 | return true; | |
a318179e | 7407 | } |
ab77a036 | 7408 | else if (optimize) |
a318179e | 7409 | { |
a1c6b246 RS |
7410 | mips_block_move_loop (dest, src, INTVAL (length), |
7411 | MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); | |
ab77a036 | 7412 | return true; |
a318179e RS |
7413 | } |
7414 | } | |
ab77a036 RS |
7415 | return false; |
7416 | } | |
7417 | \f | |
ab77a036 | 7418 | /* Expand a loop of synci insns for the address range [BEGIN, END). */ |
cafe096b | 7419 | |
ab77a036 RS |
7420 | void |
7421 | mips_expand_synci_loop (rtx begin, rtx end) | |
7422 | { | |
c6f971f4 DM |
7423 | rtx inc, cmp_result, mask, length; |
7424 | rtx_code_label *label, *end_label; | |
d48a3196 CF |
7425 | |
7426 | /* Create end_label. */ | |
7427 | end_label = gen_label_rtx (); | |
7428 | ||
7429 | /* Check if begin equals end. */ | |
7430 | cmp_result = gen_rtx_EQ (VOIDmode, begin, end); | |
7431 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
06a4ab70 | 7432 | |
65239d20 | 7433 | /* Load INC with the cache line size (rdhwr INC,$1). */ |
9d50ba21 | 7434 | inc = gen_reg_rtx (Pmode); |
81a478c8 | 7435 | emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc))); |
06a4ab70 | 7436 | |
d48a3196 CF |
7437 | /* Check if inc is 0. */ |
7438 | cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx); | |
7439 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
7440 | ||
7441 | /* Calculate mask. */ | |
7442 | mask = mips_force_unary (Pmode, NEG, inc); | |
7443 | ||
7444 | /* Mask out begin by mask. */ | |
7445 | begin = mips_force_binary (Pmode, AND, begin, mask); | |
7446 | ||
7447 | /* Calculate length. */ | |
7448 | length = mips_force_binary (Pmode, MINUS, end, begin); | |
7449 | ||
ab77a036 | 7450 | /* Loop back to here. */ |
19f8b229 | 7451 | label = gen_label_rtx (); |
ab77a036 | 7452 | emit_label (label); |
06a4ab70 | 7453 | |
ab77a036 | 7454 | emit_insn (gen_synci (begin)); |
06a4ab70 | 7455 | |
d48a3196 CF |
7456 | /* Update length. */ |
7457 | mips_emit_binary (MINUS, length, length, inc); | |
32041385 | 7458 | |
d48a3196 | 7459 | /* Update begin. */ |
ab77a036 | 7460 | mips_emit_binary (PLUS, begin, begin, inc); |
cee98a59 | 7461 | |
d48a3196 CF |
7462 | /* Check if length is greater than 0. */ |
7463 | cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx); | |
ab77a036 | 7464 | emit_jump_insn (gen_condjump (cmp_result, label)); |
d48a3196 CF |
7465 | |
7466 | emit_label (end_label); | |
ab77a036 RS |
7467 | } |
7468 | \f | |
06d19617 DD |
7469 | /* Expand a QI or HI mode atomic memory operation. |
7470 | ||
7471 | GENERATOR contains a pointer to the gen_* function that generates | |
7472 | the SI mode underlying atomic operation using masks that we | |
7473 | calculate. | |
7474 | ||
7475 | RESULT is the return register for the operation. Its value is NULL | |
7476 | if unused. | |
7477 | ||
7478 | MEM is the location of the atomic access. | |
7479 | ||
7480 | OLDVAL is the first operand for the operation. | |
7481 | ||
7482 | NEWVAL is the optional second operand for the operation. Its value | |
7483 | is NULL if unused. */ | |
49bce30a RS |
7484 | |
7485 | void | |
06d19617 DD |
7486 | mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator, |
7487 | rtx result, rtx mem, rtx oldval, rtx newval) | |
49bce30a RS |
7488 | { |
7489 | rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask; | |
06d19617 DD |
7490 | rtx unshifted_mask_reg, mask, inverted_mask, si_op; |
7491 | rtx res = NULL; | |
ef4bddc2 | 7492 | machine_mode mode; |
977502ff DD |
7493 | |
7494 | mode = GET_MODE (mem); | |
49bce30a RS |
7495 | |
7496 | /* Compute the address of the containing SImode value. */ | |
7497 | orig_addr = force_reg (Pmode, XEXP (mem, 0)); | |
7498 | memsi_addr = mips_force_binary (Pmode, AND, orig_addr, | |
7499 | force_reg (Pmode, GEN_INT (-4))); | |
7500 | ||
7501 | /* Create a memory reference for it. */ | |
7502 | memsi = gen_rtx_MEM (SImode, memsi_addr); | |
7503 | set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); | |
7504 | MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); | |
7505 | ||
7506 | /* Work out the byte offset of the QImode or HImode value, | |
7507 | counting from the least significant byte. */ | |
7508 | shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3)); | |
7509 | if (TARGET_BIG_ENDIAN) | |
977502ff | 7510 | mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2)); |
49bce30a RS |
7511 | |
7512 | /* Multiply by eight to convert the shift value from bytes to bits. */ | |
7513 | mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3)); | |
7514 | ||
7515 | /* Make the final shift an SImode value, so that it can be used in | |
7516 | SImode operations. */ | |
7517 | shiftsi = force_reg (SImode, gen_lowpart (SImode, shift)); | |
7518 | ||
7519 | /* Set MASK to an inclusive mask of the QImode or HImode value. */ | |
977502ff DD |
7520 | unshifted_mask = GEN_INT (GET_MODE_MASK (mode)); |
7521 | unshifted_mask_reg = force_reg (SImode, unshifted_mask); | |
7522 | mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi); | |
49bce30a RS |
7523 | |
7524 | /* Compute the equivalent exclusive mask. */ | |
7525 | inverted_mask = gen_reg_rtx (SImode); | |
7526 | emit_insn (gen_rtx_SET (VOIDmode, inverted_mask, | |
7527 | gen_rtx_NOT (SImode, mask))); | |
7528 | ||
7529 | /* Shift the old value into place. */ | |
977502ff DD |
7530 | if (oldval != const0_rtx) |
7531 | { | |
7532 | oldval = convert_modes (SImode, mode, oldval, true); | |
7533 | oldval = force_reg (SImode, oldval); | |
7534 | oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi); | |
7535 | } | |
49bce30a RS |
7536 | |
7537 | /* Do the same for the new value. */ | |
06d19617 | 7538 | if (newval && newval != const0_rtx) |
977502ff DD |
7539 | { |
7540 | newval = convert_modes (SImode, mode, newval, true); | |
7541 | newval = force_reg (SImode, newval); | |
7542 | newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi); | |
7543 | } | |
49bce30a RS |
7544 | |
7545 | /* Do the SImode atomic access. */ | |
06d19617 DD |
7546 | if (result) |
7547 | res = gen_reg_rtx (SImode); | |
7548 | if (newval) | |
7549 | si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval); | |
7550 | else if (result) | |
7551 | si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval); | |
7552 | else | |
7553 | si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval); | |
7554 | ||
7555 | emit_insn (si_op); | |
7556 | ||
7557 | if (result) | |
7558 | { | |
7559 | /* Shift and convert the result. */ | |
7560 | mips_emit_binary (AND, res, res, mask); | |
7561 | mips_emit_binary (LSHIFTRT, res, res, shiftsi); | |
7562 | mips_emit_move (result, gen_lowpart (GET_MODE (result), res)); | |
7563 | } | |
49bce30a RS |
7564 | } |
7565 | ||
ab77a036 | 7566 | /* Return true if it is possible to use left/right accesses for a |
d2eeb2d1 RS |
7567 | bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP. |
7568 | When returning true, update *LEFT and *RIGHT as follows: | |
cee98a59 | 7569 | |
ab77a036 RS |
7570 | *LEFT is a QImode reference to the first byte if big endian or |
7571 | the last byte if little endian. This address can be used in the | |
65239d20 | 7572 | left-side instructions (LWL, SWL, LDL, SDL). |
cee98a59 | 7573 | |
ab77a036 RS |
7574 | *RIGHT is a QImode reference to the opposite end of the field and |
7575 | can be used in the patterning right-side instruction. */ | |
cee98a59 | 7576 | |
ab77a036 | 7577 | static bool |
d2eeb2d1 | 7578 | mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos, |
ab77a036 RS |
7579 | rtx *left, rtx *right) |
7580 | { | |
7581 | rtx first, last; | |
77d4f3a4 | 7582 | |
ab77a036 RS |
7583 | /* Check that the size is valid. */ |
7584 | if (width != 32 && (!TARGET_64BIT || width != 64)) | |
7585 | return false; | |
cee98a59 | 7586 | |
ab77a036 RS |
7587 | /* We can only access byte-aligned values. Since we are always passed |
7588 | a reference to the first byte of the field, it is not necessary to | |
7589 | do anything with BITPOS after this check. */ | |
7590 | if (bitpos % BITS_PER_UNIT != 0) | |
7591 | return false; | |
34b650b3 | 7592 | |
ab77a036 RS |
7593 | /* Reject aligned bitfields: we want to use a normal load or store |
7594 | instead of a left/right pair. */ | |
d2eeb2d1 | 7595 | if (MEM_ALIGN (op) >= width) |
ab77a036 | 7596 | return false; |
06a4ab70 | 7597 | |
d2eeb2d1 RS |
7598 | /* Get references to both ends of the field. */ |
7599 | first = adjust_address (op, QImode, 0); | |
7600 | last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1); | |
cee98a59 | 7601 | |
ab77a036 | 7602 | /* Allocate to LEFT and RIGHT according to endianness. LEFT should |
65239d20 | 7603 | correspond to the MSB and RIGHT to the LSB. */ |
ab77a036 RS |
7604 | if (TARGET_BIG_ENDIAN) |
7605 | *left = first, *right = last; | |
7606 | else | |
7607 | *left = last, *right = first; | |
cee98a59 | 7608 | |
ab77a036 RS |
7609 | return true; |
7610 | } | |
cee98a59 | 7611 | |
65239d20 RS |
7612 | /* Try to use left/right loads to expand an "extv" or "extzv" pattern. |
7613 | DEST, SRC, WIDTH and BITPOS are the operands passed to the expander; | |
7614 | the operation is the equivalent of: | |
7615 | ||
7616 | (set DEST (*_extract SRC WIDTH BITPOS)) | |
cee98a59 | 7617 | |
65239d20 | 7618 | Return true on success. */ |
cee98a59 | 7619 | |
ab77a036 | 7620 | bool |
65239d20 | 7621 | mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width, |
aea21190 | 7622 | HOST_WIDE_INT bitpos, bool unsigned_p) |
ab77a036 RS |
7623 | { |
7624 | rtx left, right, temp; | |
aea21190 | 7625 | rtx dest1 = NULL_RTX; |
ab77a036 | 7626 | |
aea21190 AP |
7627 | /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will |
7628 | be a DImode, create a new temp and emit a zero extend at the end. */ | |
7629 | if (GET_MODE (dest) == DImode | |
7630 | && REG_P (dest) | |
7631 | && GET_MODE_BITSIZE (SImode) == width) | |
7632 | { | |
7633 | dest1 = dest; | |
7634 | dest = gen_reg_rtx (SImode); | |
7635 | } | |
7636 | ||
d2eeb2d1 | 7637 | if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right)) |
ab77a036 RS |
7638 | return false; |
7639 | ||
7640 | temp = gen_reg_rtx (GET_MODE (dest)); | |
7641 | if (GET_MODE (dest) == DImode) | |
7642 | { | |
7643 | emit_insn (gen_mov_ldl (temp, src, left)); | |
7644 | emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp)); | |
7645 | } | |
7646 | else | |
7647 | { | |
7648 | emit_insn (gen_mov_lwl (temp, src, left)); | |
7649 | emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); | |
cee98a59 | 7650 | } |
aea21190 AP |
7651 | |
7652 | /* If we were loading 32bits and the original register was DI then | |
7653 | sign/zero extend into the orignal dest. */ | |
7654 | if (dest1) | |
7655 | { | |
7656 | if (unsigned_p) | |
7657 | emit_insn (gen_zero_extendsidi2 (dest1, dest)); | |
7658 | else | |
7659 | emit_insn (gen_extendsidi2 (dest1, dest)); | |
7660 | } | |
ab77a036 RS |
7661 | return true; |
7662 | } | |
bfed8dac | 7663 | |
65239d20 RS |
7664 | /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH, |
7665 | BITPOS and SRC are the operands passed to the expander; the operation | |
7666 | is the equivalent of: | |
7667 | ||
7668 | (set (zero_extract DEST WIDTH BITPOS) SRC) | |
efa3896a | 7669 | |
65239d20 | 7670 | Return true on success. */ |
cafe096b | 7671 | |
ab77a036 | 7672 | bool |
65239d20 RS |
7673 | mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, |
7674 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
7675 | { |
7676 | rtx left, right; | |
ef4bddc2 | 7677 | machine_mode mode; |
6ba7b547 | 7678 | |
d2eeb2d1 | 7679 | if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right)) |
ab77a036 | 7680 | return false; |
f9e4a411 | 7681 | |
ab77a036 RS |
7682 | mode = mode_for_size (width, MODE_INT, 0); |
7683 | src = gen_lowpart (mode, src); | |
ab77a036 RS |
7684 | if (mode == DImode) |
7685 | { | |
7686 | emit_insn (gen_mov_sdl (dest, src, left)); | |
7687 | emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); | |
7688 | } | |
7689 | else | |
7690 | { | |
7691 | emit_insn (gen_mov_swl (dest, src, left)); | |
7692 | emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); | |
7693 | } | |
7694 | return true; | |
c8d1b2b7 AO |
7695 | } |
7696 | ||
ab77a036 | 7697 | /* Return true if X is a MEM with the same size as MODE. */ |
48156a39 | 7698 | |
ab77a036 | 7699 | bool |
ef4bddc2 | 7700 | mips_mem_fits_mode_p (machine_mode mode, rtx x) |
48156a39 | 7701 | { |
f5541398 RS |
7702 | return (MEM_P (x) |
7703 | && MEM_SIZE_KNOWN_P (x) | |
7704 | && MEM_SIZE (x) == GET_MODE_SIZE (mode)); | |
48156a39 NS |
7705 | } |
7706 | ||
65239d20 | 7707 | /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the |
ab77a036 RS |
7708 | source of an "ext" instruction or the destination of an "ins" |
7709 | instruction. OP must be a register operand and the following | |
7710 | conditions must hold: | |
ac8ab9fe | 7711 | |
65239d20 RS |
7712 | 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op)) |
7713 | 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
7714 | 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
ab77a036 RS |
7715 | |
7716 | Also reject lengths equal to a word as they are better handled | |
7717 | by the move patterns. */ | |
7718 | ||
7719 | bool | |
65239d20 | 7720 | mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) |
ac8ab9fe | 7721 | { |
ab77a036 RS |
7722 | if (!ISA_HAS_EXT_INS |
7723 | || !register_operand (op, VOIDmode) | |
7724 | || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) | |
7725 | return false; | |
ac8ab9fe | 7726 | |
65239d20 RS |
7727 | if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1)) |
7728 | return false; | |
ac8ab9fe | 7729 | |
65239d20 | 7730 | if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op))) |
ab77a036 RS |
7731 | return false; |
7732 | ||
7733 | return true; | |
ac8ab9fe | 7734 | } |
49912bcd AN |
7735 | |
7736 | /* Check if MASK and SHIFT are valid in mask-low-and-shift-left | |
7737 | operation if MAXLEN is the maxium length of consecutive bits that | |
7738 | can make up MASK. MODE is the mode of the operation. See | |
7739 | mask_low_and_shift_len for the actual definition. */ | |
7740 | ||
7741 | bool | |
ef4bddc2 | 7742 | mask_low_and_shift_p (machine_mode mode, rtx mask, rtx shift, int maxlen) |
49912bcd AN |
7743 | { |
7744 | return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen); | |
7745 | } | |
7746 | ||
b2c9d70f AN |
7747 | /* Return true iff OP1 and OP2 are valid operands together for the |
7748 | *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider, | |
7749 | see the table in the comment before the pattern. */ | |
7750 | ||
7751 | bool | |
ef4bddc2 | 7752 | and_operands_ok (machine_mode mode, rtx op1, rtx op2) |
b2c9d70f AN |
7753 | { |
7754 | return (memory_operand (op1, mode) | |
7755 | ? and_load_operand (op2, mode) | |
7756 | : and_reg_operand (op2, mode)); | |
7757 | } | |
7758 | ||
49912bcd AN |
7759 | /* The canonical form of a mask-low-and-shift-left operation is |
7760 | (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits | |
7761 | cleared. Thus we need to shift MASK to the right before checking if it | |
7762 | is a valid mask value. MODE is the mode of the operation. If true | |
7763 | return the length of the mask, otherwise return -1. */ | |
7764 | ||
7765 | int | |
ef4bddc2 | 7766 | mask_low_and_shift_len (machine_mode mode, rtx mask, rtx shift) |
49912bcd AN |
7767 | { |
7768 | HOST_WIDE_INT shval; | |
7769 | ||
7770 | shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1); | |
7771 | return exact_log2 ((UINTVAL (mask) >> shval) + 1); | |
7772 | } | |
ab77a036 | 7773 | \f |
65239d20 | 7774 | /* Return true if -msplit-addresses is selected and should be honored. |
ac8ab9fe | 7775 | |
65239d20 RS |
7776 | -msplit-addresses is a half-way house between explicit relocations |
7777 | and the traditional assembler macros. It can split absolute 32-bit | |
7778 | symbolic constants into a high/lo_sum pair but uses macros for other | |
7779 | sorts of access. | |
ab77a036 RS |
7780 | |
7781 | Like explicit relocation support for REL targets, it relies | |
7782 | on GNU extensions in the assembler and the linker. | |
7783 | ||
7784 | Although this code should work for -O0, it has traditionally | |
7785 | been treated as an optimization. */ | |
7786 | ||
65239d20 RS |
7787 | static bool |
7788 | mips_split_addresses_p (void) | |
c8d1b2b7 | 7789 | { |
65239d20 RS |
7790 | return (TARGET_SPLIT_ADDRESSES |
7791 | && optimize | |
7792 | && !TARGET_MIPS16 | |
7793 | && !flag_pic | |
7794 | && !ABI_HAS_64BIT_SYMBOLS); | |
cee98a59 MM |
7795 | } |
7796 | ||
65239d20 | 7797 | /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */ |
2bcb2ab3 | 7798 | |
ab77a036 RS |
7799 | static void |
7800 | mips_init_relocs (void) | |
2bcb2ab3 | 7801 | { |
ab77a036 | 7802 | memset (mips_split_p, '\0', sizeof (mips_split_p)); |
08d0963a | 7803 | memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p)); |
ddaf8125 | 7804 | memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p)); |
ab77a036 RS |
7805 | memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs)); |
7806 | memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs)); | |
2bcb2ab3 | 7807 | |
ddaf8125 RS |
7808 | if (TARGET_MIPS16_PCREL_LOADS) |
7809 | mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true; | |
7810 | else | |
ab77a036 | 7811 | { |
ddaf8125 | 7812 | if (ABI_HAS_64BIT_SYMBOLS) |
ab77a036 | 7813 | { |
ddaf8125 RS |
7814 | if (TARGET_EXPLICIT_RELOCS) |
7815 | { | |
7816 | mips_split_p[SYMBOL_64_HIGH] = true; | |
7817 | mips_hi_relocs[SYMBOL_64_HIGH] = "%highest("; | |
7818 | mips_lo_relocs[SYMBOL_64_HIGH] = "%higher("; | |
ab77a036 | 7819 | |
ddaf8125 RS |
7820 | mips_split_p[SYMBOL_64_MID] = true; |
7821 | mips_hi_relocs[SYMBOL_64_MID] = "%higher("; | |
7822 | mips_lo_relocs[SYMBOL_64_MID] = "%hi("; | |
ab77a036 | 7823 | |
ddaf8125 RS |
7824 | mips_split_p[SYMBOL_64_LOW] = true; |
7825 | mips_hi_relocs[SYMBOL_64_LOW] = "%hi("; | |
7826 | mips_lo_relocs[SYMBOL_64_LOW] = "%lo("; | |
ab77a036 | 7827 | |
ddaf8125 RS |
7828 | mips_split_p[SYMBOL_ABSOLUTE] = true; |
7829 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7830 | } | |
ab77a036 | 7831 | } |
ddaf8125 | 7832 | else |
ab77a036 | 7833 | { |
ddaf8125 RS |
7834 | if (TARGET_EXPLICIT_RELOCS |
7835 | || mips_split_addresses_p () | |
7836 | || TARGET_MIPS16) | |
7837 | { | |
7838 | mips_split_p[SYMBOL_ABSOLUTE] = true; | |
7839 | mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; | |
7840 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7841 | } | |
ab77a036 RS |
7842 | } |
7843 | } | |
2bcb2ab3 GK |
7844 | |
7845 | if (TARGET_MIPS16) | |
7846 | { | |
ab77a036 RS |
7847 | /* The high part is provided by a pseudo copy of $gp. */ |
7848 | mips_split_p[SYMBOL_GP_RELATIVE] = true; | |
7849 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel("; | |
2bcb2ab3 | 7850 | } |
08d0963a RS |
7851 | else if (TARGET_EXPLICIT_RELOCS) |
7852 | /* Small data constants are kept whole until after reload, | |
7853 | then lowered by mips_rewrite_small_data. */ | |
7854 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel("; | |
2bcb2ab3 | 7855 | |
ab77a036 RS |
7856 | if (TARGET_EXPLICIT_RELOCS) |
7857 | { | |
ab77a036 RS |
7858 | mips_split_p[SYMBOL_GOT_PAGE_OFST] = true; |
7859 | if (TARGET_NEWABI) | |
7860 | { | |
7861 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page("; | |
7862 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst("; | |
7863 | } | |
7864 | else | |
7865 | { | |
7866 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got("; | |
7867 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo("; | |
7868 | } | |
08d0963a RS |
7869 | if (TARGET_MIPS16) |
7870 | /* Expose the use of $28 as soon as possible. */ | |
7871 | mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true; | |
cee98a59 | 7872 | |
ab77a036 RS |
7873 | if (TARGET_XGOT) |
7874 | { | |
7875 | /* The HIGH and LO_SUM are matched by special .md patterns. */ | |
7876 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
cee98a59 | 7877 | |
ab77a036 RS |
7878 | mips_split_p[SYMBOL_GOTOFF_DISP] = true; |
7879 | mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi("; | |
7880 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo("; | |
c831afd5 | 7881 | |
ab77a036 RS |
7882 | mips_split_p[SYMBOL_GOTOFF_CALL] = true; |
7883 | mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi("; | |
7884 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo("; | |
7885 | } | |
7886 | else | |
7887 | { | |
7888 | if (TARGET_NEWABI) | |
7889 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp("; | |
7890 | else | |
7891 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got("; | |
7892 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16("; | |
08d0963a RS |
7893 | if (TARGET_MIPS16) |
7894 | /* Expose the use of $28 as soon as possible. */ | |
7895 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
ab77a036 RS |
7896 | } |
7897 | } | |
a50f2a09 | 7898 | |
ab77a036 RS |
7899 | if (TARGET_NEWABI) |
7900 | { | |
7901 | mips_split_p[SYMBOL_GOTOFF_LOADGP] = true; | |
7902 | mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel("; | |
7903 | mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel("; | |
c831afd5 | 7904 | } |
f5963e61 | 7905 | |
ab77a036 RS |
7906 | mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd("; |
7907 | mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm("; | |
65239d20 | 7908 | |
ddaf8125 RS |
7909 | if (TARGET_MIPS16_PCREL_LOADS) |
7910 | { | |
7911 | mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true; | |
7912 | mips_use_pcrel_pool_p[SYMBOL_TPREL] = true; | |
7913 | } | |
7914 | else | |
7915 | { | |
7916 | mips_split_p[SYMBOL_DTPREL] = true; | |
7917 | mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi("; | |
7918 | mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo("; | |
65239d20 | 7919 | |
ddaf8125 RS |
7920 | mips_split_p[SYMBOL_TPREL] = true; |
7921 | mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi("; | |
7922 | mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo("; | |
7923 | } | |
cee98a59 | 7924 | |
ddaf8125 | 7925 | mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel("; |
ab77a036 | 7926 | mips_lo_relocs[SYMBOL_HALF] = "%half("; |
cee98a59 | 7927 | } |
ab77a036 | 7928 | |
ab77a036 RS |
7929 | /* Print symbolic operand OP, which is part of a HIGH or LO_SUM |
7930 | in context CONTEXT. RELOCS is the array of relocations to use. */ | |
7931 | ||
7932 | static void | |
65239d20 RS |
7933 | mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context, |
7934 | const char **relocs) | |
ab77a036 RS |
7935 | { |
7936 | enum mips_symbol_type symbol_type; | |
7937 | const char *p; | |
7938 | ||
7939 | symbol_type = mips_classify_symbolic_expression (op, context); | |
65239d20 | 7940 | gcc_assert (relocs[symbol_type]); |
ab77a036 RS |
7941 | |
7942 | fputs (relocs[symbol_type], file); | |
7943 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7944 | for (p = relocs[symbol_type]; *p != 0; p++) | |
7945 | if (*p == '(') | |
7946 | fputc (')', file); | |
7947 | } | |
7948 | ||
cf5fb4b0 RS |
7949 | /* Start a new block with the given asm switch enabled. If we need |
7950 | to print a directive, emit PREFIX before it and SUFFIX after it. */ | |
7951 | ||
7952 | static void | |
7953 | mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7954 | const char *prefix, const char *suffix) | |
7955 | { | |
7956 | if (asm_switch->nesting_level == 0) | |
7957 | fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix); | |
7958 | asm_switch->nesting_level++; | |
7959 | } | |
7960 | ||
7961 | /* Likewise, but end a block. */ | |
7962 | ||
7963 | static void | |
7964 | mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7965 | const char *prefix, const char *suffix) | |
7966 | { | |
7967 | gcc_assert (asm_switch->nesting_level); | |
7968 | asm_switch->nesting_level--; | |
7969 | if (asm_switch->nesting_level == 0) | |
7970 | fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix); | |
7971 | } | |
7972 | ||
7973 | /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1 | |
7974 | that either print a complete line or print nothing. */ | |
7975 | ||
7976 | void | |
7977 | mips_push_asm_switch (struct mips_asm_switch *asm_switch) | |
7978 | { | |
7979 | mips_push_asm_switch_1 (asm_switch, "\t", "\n"); | |
7980 | } | |
7981 | ||
7982 | void | |
7983 | mips_pop_asm_switch (struct mips_asm_switch *asm_switch) | |
7984 | { | |
7985 | mips_pop_asm_switch_1 (asm_switch, "\t", "\n"); | |
7986 | } | |
7987 | ||
07045266 | 7988 | /* Print the text for PRINT_OPERAND punctation character CH to FILE. |
dfad12b5 RS |
7989 | The punctuation characters are: |
7990 | ||
07045266 RS |
7991 | '(' Start a nested ".set noreorder" block. |
7992 | ')' End a nested ".set noreorder" block. | |
7993 | '[' Start a nested ".set noat" block. | |
7994 | ']' End a nested ".set noat" block. | |
7995 | '<' Start a nested ".set nomacro" block. | |
7996 | '>' End a nested ".set nomacro" block. | |
7997 | '*' Behave like %(%< if generating a delayed-branch sequence. | |
7998 | '#' Print a nop if in a ".set noreorder" block. | |
7999 | '/' Like '#', but do nothing within a delayed-branch sequence. | |
8000 | '?' Print "l" if mips_branch_likely is true | |
ee9a72e5 | 8001 | '~' Print a nop if mips_branch_likely is true |
ffa9d0b1 | 8002 | '.' Print the name of the register with a hard-wired zero (zero or $0). |
07045266 | 8003 | '@' Print the name of the assembler temporary register (at or $1). |
2bcb2ab3 | 8004 | '^' Print the name of the pic call-through register (t9 or $25). |
f833ffd4 | 8005 | '+' Print the name of the gp register (usually gp or $28). |
07045266 | 8006 | '$' Print the name of the stack pointer register (sp or $29). |
22c4c869 CM |
8007 | ':' Print "c" to use the compact version if the delay slot is a nop. |
8008 | '!' Print "s" to use the short version if the delay slot contains a | |
8009 | 16-bit instruction. | |
cee98a59 | 8010 | |
07045266 | 8011 | See also mips_init_print_operand_pucnt. */ |
cee98a59 | 8012 | |
07045266 RS |
8013 | static void |
8014 | mips_print_operand_punctuation (FILE *file, int ch) | |
8015 | { | |
8016 | switch (ch) | |
cee98a59 | 8017 | { |
07045266 | 8018 | case '(': |
cf5fb4b0 | 8019 | mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t"); |
07045266 | 8020 | break; |
cee98a59 | 8021 | |
07045266 | 8022 | case ')': |
cf5fb4b0 | 8023 | mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", ""); |
07045266 | 8024 | break; |
cee98a59 | 8025 | |
07045266 | 8026 | case '[': |
cf5fb4b0 | 8027 | mips_push_asm_switch_1 (&mips_noat, "", "\n\t"); |
07045266 | 8028 | break; |
ffa9d0b1 | 8029 | |
07045266 | 8030 | case ']': |
cf5fb4b0 | 8031 | mips_pop_asm_switch_1 (&mips_noat, "\n\t", ""); |
07045266 | 8032 | break; |
cee98a59 | 8033 | |
07045266 | 8034 | case '<': |
cf5fb4b0 | 8035 | mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t"); |
07045266 | 8036 | break; |
2bcb2ab3 | 8037 | |
07045266 | 8038 | case '>': |
cf5fb4b0 | 8039 | mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", ""); |
07045266 | 8040 | break; |
2bcb2ab3 | 8041 | |
07045266 RS |
8042 | case '*': |
8043 | if (final_sequence != 0) | |
8044 | { | |
8045 | mips_print_operand_punctuation (file, '('); | |
8046 | mips_print_operand_punctuation (file, '<'); | |
8047 | } | |
8048 | break; | |
cee98a59 | 8049 | |
07045266 | 8050 | case '#': |
cf5fb4b0 | 8051 | if (mips_noreorder.nesting_level > 0) |
07045266 RS |
8052 | fputs ("\n\tnop", file); |
8053 | break; | |
cee98a59 | 8054 | |
07045266 RS |
8055 | case '/': |
8056 | /* Print an extra newline so that the delayed insn is separated | |
8057 | from the following ones. This looks neater and is consistent | |
8058 | with non-nop delayed sequences. */ | |
cf5fb4b0 | 8059 | if (mips_noreorder.nesting_level > 0 && final_sequence == 0) |
07045266 RS |
8060 | fputs ("\n\tnop\n", file); |
8061 | break; | |
cee98a59 | 8062 | |
07045266 RS |
8063 | case '?': |
8064 | if (mips_branch_likely) | |
8065 | putc ('l', file); | |
8066 | break; | |
cee98a59 | 8067 | |
ee9a72e5 JK |
8068 | case '~': |
8069 | if (mips_branch_likely) | |
8070 | fputs ("\n\tnop", file); | |
8071 | break; | |
8072 | ||
07045266 RS |
8073 | case '.': |
8074 | fputs (reg_names[GP_REG_FIRST + 0], file); | |
8075 | break; | |
cee98a59 | 8076 | |
07045266 | 8077 | case '@': |
293593b1 | 8078 | fputs (reg_names[AT_REGNUM], file); |
07045266 | 8079 | break; |
6f2993e5 | 8080 | |
07045266 RS |
8081 | case '^': |
8082 | fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file); | |
8083 | break; | |
cee98a59 | 8084 | |
07045266 RS |
8085 | case '+': |
8086 | fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); | |
8087 | break; | |
cee98a59 | 8088 | |
07045266 RS |
8089 | case '$': |
8090 | fputs (reg_names[STACK_POINTER_REGNUM], file); | |
8091 | break; | |
cee98a59 | 8092 | |
22c4c869 CM |
8093 | case ':': |
8094 | /* When final_sequence is 0, the delay slot will be a nop. We can | |
8095 | use the compact version for microMIPS. */ | |
8096 | if (final_sequence == 0) | |
8097 | putc ('c', file); | |
8098 | break; | |
8099 | ||
8100 | case '!': | |
03a7dddb CM |
8101 | /* If the delay slot instruction is short, then use the |
8102 | compact version. */ | |
8103 | if (final_sequence == 0 | |
84034c69 | 8104 | || get_attr_length (final_sequence->insn (1)) == 2) |
22c4c869 CM |
8105 | putc ('s', file); |
8106 | break; | |
8107 | ||
07045266 RS |
8108 | default: |
8109 | gcc_unreachable (); | |
8110 | break; | |
8111 | } | |
8112 | } | |
cee98a59 | 8113 | |
07045266 | 8114 | /* Initialize mips_print_operand_punct. */ |
cee98a59 | 8115 | |
07045266 RS |
8116 | static void |
8117 | mips_init_print_operand_punct (void) | |
8118 | { | |
8119 | const char *p; | |
cee98a59 | 8120 | |
22c4c869 | 8121 | for (p = "()[]<>*#/?~.@^+$:!"; *p; p++) |
07045266 RS |
8122 | mips_print_operand_punct[(unsigned char) *p] = true; |
8123 | } | |
cee98a59 | 8124 | |
07045266 RS |
8125 | /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction |
8126 | associated with condition CODE. Print the condition part of the | |
8127 | opcode to FILE. */ | |
cee98a59 | 8128 | |
07045266 RS |
8129 | static void |
8130 | mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter) | |
8131 | { | |
8132 | switch (code) | |
8133 | { | |
8134 | case EQ: | |
8135 | case NE: | |
8136 | case GT: | |
8137 | case GE: | |
8138 | case LT: | |
8139 | case LE: | |
8140 | case GTU: | |
8141 | case GEU: | |
8142 | case LTU: | |
8143 | case LEU: | |
8144 | /* Conveniently, the MIPS names for these conditions are the same | |
8145 | as their RTL equivalents. */ | |
8146 | fputs (GET_RTX_NAME (code), file); | |
8147 | break; | |
cee98a59 | 8148 | |
07045266 RS |
8149 | default: |
8150 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
8151 | break; | |
8152 | } | |
8153 | } | |
cee98a59 | 8154 | |
07045266 | 8155 | /* Likewise floating-point branches. */ |
f5963e61 | 8156 | |
07045266 RS |
8157 | static void |
8158 | mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter) | |
8159 | { | |
8160 | switch (code) | |
8161 | { | |
8162 | case EQ: | |
8163 | fputs ("c1f", file); | |
8164 | break; | |
efa3896a | 8165 | |
07045266 RS |
8166 | case NE: |
8167 | fputs ("c1t", file); | |
8168 | break; | |
66471b47 | 8169 | |
07045266 RS |
8170 | default: |
8171 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
8172 | break; | |
8173 | } | |
8174 | } | |
66471b47 | 8175 | |
6e9e0126 NF |
8176 | /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
8177 | ||
8178 | static bool | |
8179 | mips_print_operand_punct_valid_p (unsigned char code) | |
8180 | { | |
8181 | return mips_print_operand_punct[code]; | |
8182 | } | |
8183 | ||
8184 | /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are: | |
f5963e61 | 8185 | |
07045266 RS |
8186 | 'X' Print CONST_INT OP in hexadecimal format. |
8187 | 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format. | |
8188 | 'd' Print CONST_INT OP in decimal. | |
49912bcd | 8189 | 'm' Print one less than CONST_INT OP in decimal. |
07045266 RS |
8190 | 'h' Print the high-part relocation associated with OP, after stripping |
8191 | any outermost HIGH. | |
8192 | 'R' Print the low-part relocation associated with OP. | |
8193 | 'C' Print the integer branch condition for comparison OP. | |
8194 | 'N' Print the inverse of the integer branch condition for comparison OP. | |
8195 | 'F' Print the FPU branch condition for comparison OP. | |
8196 | 'W' Print the inverse of the FPU branch condition for comparison OP. | |
8197 | 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...), | |
8198 | 'z' for (eq:?I ...), 'n' for (ne:?I ...). | |
8199 | 't' Like 'T', but with the EQ/NE cases reversed | |
8200 | 'Y' Print mips_fp_conditions[INTVAL (OP)] | |
8201 | 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing. | |
8202 | 'q' Print a DSP accumulator register. | |
8203 | 'D' Print the second part of a double-word register or memory operand. | |
8204 | 'L' Print the low-order register in a double-word register operand. | |
8205 | 'M' Print high-order register in a double-word register operand. | |
6399761a TV |
8206 | 'z' Print $0 if OP is zero, otherwise print OP normally. |
8207 | 'b' Print the address of a memory operand, without offset. */ | |
07045266 | 8208 | |
6e9e0126 | 8209 | static void |
65239d20 | 8210 | mips_print_operand (FILE *file, rtx op, int letter) |
07045266 RS |
8211 | { |
8212 | enum rtx_code code; | |
cee98a59 | 8213 | |
6e9e0126 | 8214 | if (mips_print_operand_punct_valid_p (letter)) |
cee98a59 | 8215 | { |
07045266 | 8216 | mips_print_operand_punctuation (file, letter); |
cee98a59 MM |
8217 | return; |
8218 | } | |
8219 | ||
07045266 | 8220 | gcc_assert (op); |
cee98a59 | 8221 | code = GET_CODE (op); |
2a0b0bf5 | 8222 | |
07045266 RS |
8223 | switch (letter) |
8224 | { | |
8225 | case 'X': | |
47ac44d6 | 8226 | if (CONST_INT_P (op)) |
07045266 RS |
8227 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); |
8228 | else | |
8229 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
8230 | break; | |
cee98a59 | 8231 | |
07045266 | 8232 | case 'x': |
47ac44d6 | 8233 | if (CONST_INT_P (op)) |
07045266 RS |
8234 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff); |
8235 | else | |
8236 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
8237 | break; | |
0ff83799 | 8238 | |
07045266 | 8239 | case 'd': |
47ac44d6 | 8240 | if (CONST_INT_P (op)) |
07045266 RS |
8241 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op)); |
8242 | else | |
8243 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
8244 | break; | |
0ff83799 | 8245 | |
49912bcd | 8246 | case 'm': |
47ac44d6 | 8247 | if (CONST_INT_P (op)) |
49912bcd AN |
8248 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1); |
8249 | else | |
8250 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
8251 | break; | |
8252 | ||
07045266 RS |
8253 | case 'h': |
8254 | if (code == HIGH) | |
108b61d5 | 8255 | op = XEXP (op, 0); |
65239d20 | 8256 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs); |
07045266 RS |
8257 | break; |
8258 | ||
8259 | case 'R': | |
65239d20 | 8260 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs); |
07045266 | 8261 | break; |
108b61d5 | 8262 | |
07045266 RS |
8263 | case 'C': |
8264 | mips_print_int_branch_condition (file, code, letter); | |
8265 | break; | |
108b61d5 | 8266 | |
07045266 RS |
8267 | case 'N': |
8268 | mips_print_int_branch_condition (file, reverse_condition (code), letter); | |
8269 | break; | |
8270 | ||
8271 | case 'F': | |
8272 | mips_print_float_branch_condition (file, code, letter); | |
8273 | break; | |
8274 | ||
8275 | case 'W': | |
8276 | mips_print_float_branch_condition (file, reverse_condition (code), | |
8277 | letter); | |
8278 | break; | |
8279 | ||
8280 | case 'T': | |
8281 | case 't': | |
8282 | { | |
8283 | int truth = (code == NE) == (letter == 'T'); | |
3b9c787b | 8284 | fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file); |
07045266 RS |
8285 | } |
8286 | break; | |
8287 | ||
8288 | case 'Y': | |
8289 | if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions)) | |
8290 | fputs (mips_fp_conditions[UINTVAL (op)], file); | |
308cd611 | 8291 | else |
07045266 RS |
8292 | output_operand_lossage ("'%%%c' is not a valid operand prefix", |
8293 | letter); | |
8294 | break; | |
06a4ab70 | 8295 | |
07045266 | 8296 | case 'Z': |
308cd611 RS |
8297 | if (ISA_HAS_8CC) |
8298 | { | |
65239d20 | 8299 | mips_print_operand (file, op, 0); |
308cd611 RS |
8300 | fputc (',', file); |
8301 | } | |
07045266 | 8302 | break; |
118ea793 | 8303 | |
07045266 RS |
8304 | case 'q': |
8305 | if (code == REG && MD_REG_P (REGNO (op))) | |
118ea793 | 8306 | fprintf (file, "$ac0"); |
07045266 RS |
8307 | else if (code == REG && DSP_ACC_REG_P (REGNO (op))) |
8308 | fprintf (file, "$ac%c", reg_names[REGNO (op)][3]); | |
51c6b247 | 8309 | else |
07045266 RS |
8310 | output_operand_lossage ("invalid use of '%%%c'", letter); |
8311 | break; | |
cee98a59 | 8312 | |
07045266 RS |
8313 | default: |
8314 | switch (code) | |
8315 | { | |
8316 | case REG: | |
8317 | { | |
8318 | unsigned int regno = REGNO (op); | |
8319 | if ((letter == 'M' && TARGET_LITTLE_ENDIAN) | |
8320 | || (letter == 'L' && TARGET_BIG_ENDIAN) | |
8321 | || letter == 'D') | |
8322 | regno++; | |
b0907a6c AN |
8323 | else if (letter && letter != 'z' && letter != 'M' && letter != 'L') |
8324 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
e19da24c CF |
8325 | /* We need to print $0 .. $31 for COP0 registers. */ |
8326 | if (COP0_REG_P (regno)) | |
8327 | fprintf (file, "$%s", ®_names[regno][4]); | |
8328 | else | |
8329 | fprintf (file, "%s", reg_names[regno]); | |
07045266 RS |
8330 | } |
8331 | break; | |
cee98a59 | 8332 | |
07045266 RS |
8333 | case MEM: |
8334 | if (letter == 'D') | |
0a81f074 | 8335 | output_address (plus_constant (Pmode, XEXP (op, 0), 4)); |
6399761a TV |
8336 | else if (letter == 'b') |
8337 | { | |
8338 | gcc_assert (REG_P (XEXP (op, 0))); | |
8339 | mips_print_operand (file, XEXP (op, 0), 0); | |
8340 | } | |
b0907a6c AN |
8341 | else if (letter && letter != 'z') |
8342 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
8343 | else |
8344 | output_address (XEXP (op, 0)); | |
8345 | break; | |
cee98a59 | 8346 | |
07045266 RS |
8347 | default: |
8348 | if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) | |
8349 | fputs (reg_names[GP_REG_FIRST], file); | |
b0907a6c AN |
8350 | else if (letter && letter != 'z') |
8351 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
8352 | else if (CONST_GP_P (op)) |
8353 | fputs (reg_names[GLOBAL_POINTER_REGNUM], file); | |
8354 | else | |
8355 | output_addr_const (file, mips_strip_unspec_address (op)); | |
8356 | break; | |
8357 | } | |
b3c90666 | 8358 | } |
108b61d5 | 8359 | } |
07045266 | 8360 | |
6e9e0126 | 8361 | /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ |
cee98a59 | 8362 | |
6e9e0126 | 8363 | static void |
65239d20 | 8364 | mips_print_operand_address (FILE *file, rtx x) |
cafe096b EC |
8365 | { |
8366 | struct mips_address_info addr; | |
cee98a59 | 8367 | |
108b61d5 RS |
8368 | if (mips_classify_address (&addr, x, word_mode, true)) |
8369 | switch (addr.type) | |
8370 | { | |
8371 | case ADDRESS_REG: | |
65239d20 | 8372 | mips_print_operand (file, addr.offset, 0); |
108b61d5 RS |
8373 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
8374 | return; | |
8375 | ||
8376 | case ADDRESS_LO_SUM: | |
65239d20 RS |
8377 | mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM, |
8378 | mips_lo_relocs); | |
108b61d5 RS |
8379 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
8380 | return; | |
8381 | ||
8382 | case ADDRESS_CONST_INT: | |
4767c570 | 8383 | output_addr_const (file, x); |
65239d20 | 8384 | fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); |
4767c570 RS |
8385 | return; |
8386 | ||
108b61d5 | 8387 | case ADDRESS_SYMBOLIC: |
c93c5160 | 8388 | output_addr_const (file, mips_strip_unspec_address (x)); |
108b61d5 RS |
8389 | return; |
8390 | } | |
7ad769fe | 8391 | gcc_unreachable (); |
cee98a59 | 8392 | } |
301d03af | 8393 | \f |
65239d20 | 8394 | /* Implement TARGET_ENCODE_SECTION_INFO. */ |
ab77a036 RS |
8395 | |
8396 | static void | |
8397 | mips_encode_section_info (tree decl, rtx rtl, int first) | |
8398 | { | |
8399 | default_encode_section_info (decl, rtl, first); | |
8400 | ||
8401 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8402 | { | |
8403 | rtx symbol = XEXP (rtl, 0); | |
8404 | tree type = TREE_TYPE (decl); | |
8405 | ||
65239d20 | 8406 | /* Encode whether the symbol is short or long. */ |
ab77a036 RS |
8407 | if ((TARGET_LONG_CALLS && !mips_near_type_p (type)) |
8408 | || mips_far_type_p (type)) | |
8409 | SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; | |
8410 | } | |
8411 | } | |
8412 | ||
8413 | /* Implement TARGET_SELECT_RTX_SECTION. */ | |
8414 | ||
8415 | static section * | |
ef4bddc2 | 8416 | mips_select_rtx_section (machine_mode mode, rtx x, |
ab77a036 RS |
8417 | unsigned HOST_WIDE_INT align) |
8418 | { | |
8419 | /* ??? Consider using mergeable small data sections. */ | |
8420 | if (mips_rtx_constant_in_small_data_p (mode)) | |
8421 | return get_named_section (NULL, ".sdata", 0); | |
8422 | ||
8423 | return default_elf_select_rtx_section (mode, x, align); | |
8424 | } | |
8425 | ||
8426 | /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. | |
8427 | ||
8428 | The complication here is that, with the combination TARGET_ABICALLS | |
e21d5757 DJ |
8429 | && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use |
8430 | absolute addresses, and should therefore not be included in the | |
8431 | read-only part of a DSO. Handle such cases by selecting a normal | |
8432 | data section instead of a read-only one. The logic apes that in | |
8433 | default_function_rodata_section. */ | |
ab77a036 RS |
8434 | |
8435 | static section * | |
8436 | mips_function_rodata_section (tree decl) | |
8437 | { | |
e21d5757 | 8438 | if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD) |
ab77a036 RS |
8439 | return default_function_rodata_section (decl); |
8440 | ||
8441 | if (decl && DECL_SECTION_NAME (decl)) | |
8442 | { | |
f961457f | 8443 | const char *name = DECL_SECTION_NAME (decl); |
cf288ed3 | 8444 | if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0) |
ab77a036 RS |
8445 | { |
8446 | char *rname = ASTRDUP (name); | |
8447 | rname[14] = 'd'; | |
8448 | return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl); | |
8449 | } | |
65239d20 RS |
8450 | else if (flag_function_sections |
8451 | && flag_data_sections | |
ab77a036 RS |
8452 | && strncmp (name, ".text.", 6) == 0) |
8453 | { | |
8454 | char *rname = ASTRDUP (name); | |
8455 | memcpy (rname + 1, "data", 4); | |
8456 | return get_section (rname, SECTION_WRITE, decl); | |
8457 | } | |
8458 | } | |
8459 | return data_section; | |
8460 | } | |
8461 | ||
65239d20 | 8462 | /* Implement TARGET_IN_SMALL_DATA_P. */ |
ab77a036 RS |
8463 | |
8464 | static bool | |
8465 | mips_in_small_data_p (const_tree decl) | |
8466 | { | |
65239d20 | 8467 | unsigned HOST_WIDE_INT size; |
ab77a036 RS |
8468 | |
8469 | if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL) | |
8470 | return false; | |
8471 | ||
65239d20 RS |
8472 | /* We don't yet generate small-data references for -mabicalls |
8473 | or VxWorks RTP code. See the related -G handling in | |
525c561d | 8474 | mips_option_override. */ |
ab77a036 RS |
8475 | if (TARGET_ABICALLS || TARGET_VXWORKS_RTP) |
8476 | return false; | |
8477 | ||
8478 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) | |
8479 | { | |
8480 | const char *name; | |
8481 | ||
8482 | /* Reject anything that isn't in a known small-data section. */ | |
f961457f | 8483 | name = DECL_SECTION_NAME (decl); |
ab77a036 RS |
8484 | if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) |
8485 | return false; | |
8486 | ||
8487 | /* If a symbol is defined externally, the assembler will use the | |
8488 | usual -G rules when deciding how to implement macros. */ | |
8489 | if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl)) | |
8490 | return true; | |
8491 | } | |
8492 | else if (TARGET_EMBEDDED_DATA) | |
8493 | { | |
8494 | /* Don't put constants into the small data section: we want them | |
8495 | to be in ROM rather than RAM. */ | |
8496 | if (TREE_CODE (decl) != VAR_DECL) | |
8497 | return false; | |
8498 | ||
8499 | if (TREE_READONLY (decl) | |
8500 | && !TREE_SIDE_EFFECTS (decl) | |
8501 | && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl)))) | |
8502 | return false; | |
8503 | } | |
8504 | ||
8505 | /* Enforce -mlocal-sdata. */ | |
8506 | if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl)) | |
8507 | return false; | |
8508 | ||
8509 | /* Enforce -mextern-sdata. */ | |
8510 | if (!TARGET_EXTERN_SDATA && DECL_P (decl)) | |
8511 | { | |
8512 | if (DECL_EXTERNAL (decl)) | |
8513 | return false; | |
8514 | if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL) | |
8515 | return false; | |
8516 | } | |
8517 | ||
2a4430a6 RS |
8518 | /* We have traditionally not treated zero-sized objects as small data, |
8519 | so this is now effectively part of the ABI. */ | |
ab77a036 | 8520 | size = int_size_in_bytes (TREE_TYPE (decl)); |
2a4430a6 | 8521 | return size > 0 && size <= mips_small_data_threshold; |
ab77a036 RS |
8522 | } |
8523 | ||
8524 | /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use | |
8525 | anchors for small data: the GP register acts as an anchor in that | |
8526 | case. We also don't want to use them for PC-relative accesses, | |
8527 | where the PC acts as an anchor. */ | |
8528 | ||
8529 | static bool | |
8530 | mips_use_anchors_for_symbol_p (const_rtx symbol) | |
8531 | { | |
8532 | switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM)) | |
8533 | { | |
8534 | case SYMBOL_PC_RELATIVE: | |
8535 | case SYMBOL_GP_RELATIVE: | |
8536 | return false; | |
8537 | ||
8538 | default: | |
8539 | return default_use_anchors_for_symbol_p (symbol); | |
8540 | } | |
8541 | } | |
8542 | \f | |
8543 | /* The MIPS debug format wants all automatic variables and arguments | |
8544 | to be in terms of the virtual frame pointer (stack pointer before | |
8545 | any adjustment in the function), while the MIPS 3.0 linker wants | |
8546 | the frame pointer to be the stack pointer after the initial | |
8547 | adjustment. So, we do the adjustment here. The arg pointer (which | |
8548 | is eliminated) points to the virtual frame pointer, while the frame | |
8549 | pointer (which may be eliminated) points to the stack pointer after | |
8550 | the initial adjustments. */ | |
8551 | ||
8552 | HOST_WIDE_INT | |
8553 | mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) | |
8554 | { | |
8555 | rtx offset2 = const0_rtx; | |
8556 | rtx reg = eliminate_constant_term (addr, &offset2); | |
8557 | ||
8558 | if (offset == 0) | |
8559 | offset = INTVAL (offset2); | |
8560 | ||
65239d20 RS |
8561 | if (reg == stack_pointer_rtx |
8562 | || reg == frame_pointer_rtx | |
ab77a036 RS |
8563 | || reg == hard_frame_pointer_rtx) |
8564 | { | |
f374e413 RS |
8565 | offset -= cfun->machine->frame.total_size; |
8566 | if (reg == hard_frame_pointer_rtx) | |
8567 | offset += cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
8568 | } |
8569 | ||
ab77a036 RS |
8570 | return offset; |
8571 | } | |
8572 | \f | |
65239d20 | 8573 | /* Implement ASM_OUTPUT_EXTERNAL. */ |
cee98a59 | 8574 | |
f8fdb503 L |
8575 | void |
8576 | mips_output_external (FILE *file, tree decl, const char *name) | |
5619cc87 | 8577 | { |
f8fdb503 | 8578 | default_elf_asm_output_external (file, decl, name); |
5619cc87 | 8579 | |
f8fdb503 L |
8580 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
8581 | set in order to avoid putting out names that are never really | |
8582 | used. */ | |
8583 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
6773a41c | 8584 | { |
f8fdb503 L |
8585 | if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl)) |
8586 | { | |
65239d20 RS |
8587 | /* When using assembler macros, emit .extern directives for |
8588 | all small-data externs so that the assembler knows how | |
8589 | big they are. | |
8590 | ||
8591 | In most cases it would be safe (though pointless) to emit | |
8592 | .externs for other symbols too. One exception is when an | |
8593 | object is within the -G limit but declared by the user to | |
8594 | be in a section other than .sbss or .sdata. */ | |
f8fdb503 L |
8595 | fputs ("\t.extern\t", file); |
8596 | assemble_name (file, name); | |
8597 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n", | |
8598 | int_size_in_bytes (TREE_TYPE (decl))); | |
8599 | } | |
6773a41c | 8600 | } |
cee98a59 | 8601 | } |
65239d20 | 8602 | |
b5f5d41d | 8603 | /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */ |
cee98a59 | 8604 | |
b5f5d41d | 8605 | static void |
b4966b1b | 8606 | mips_output_filename (FILE *stream, const char *name) |
cee98a59 | 8607 | { |
8b0397a6 DJ |
8608 | /* If we are emitting DWARF-2, let dwarf2out handle the ".file" |
8609 | directives. */ | |
8610 | if (write_symbols == DWARF2_DEBUG) | |
8611 | return; | |
cafe096b | 8612 | else if (mips_output_filename_first_time) |
cee98a59 | 8613 | { |
cafe096b | 8614 | mips_output_filename_first_time = 0; |
82563d35 | 8615 | num_source_filenames += 1; |
cee98a59 | 8616 | current_function_file = name; |
3e487b21 ZW |
8617 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
8618 | output_quoted_string (stream, name); | |
8619 | putc ('\n', stream); | |
cee98a59 | 8620 | } |
3e487b21 ZW |
8621 | /* If we are emitting stabs, let dbxout.c handle this (except for |
8622 | the mips_output_filename_first_time case). */ | |
2bacb292 | 8623 | else if (write_symbols == DBX_DEBUG) |
3e487b21 | 8624 | return; |
cee98a59 | 8625 | else if (name != current_function_file |
d82783b6 | 8626 | && strcmp (name, current_function_file) != 0) |
cee98a59 | 8627 | { |
82563d35 | 8628 | num_source_filenames += 1; |
d82783b6 | 8629 | current_function_file = name; |
3e487b21 ZW |
8630 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
8631 | output_quoted_string (stream, name); | |
8632 | putc ('\n', stream); | |
cee98a59 MM |
8633 | } |
8634 | } | |
ab77a036 | 8635 | |
65239d20 | 8636 | /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
ab77a036 | 8637 | |
9a4a025a | 8638 | static void ATTRIBUTE_UNUSED |
ab77a036 RS |
8639 | mips_output_dwarf_dtprel (FILE *file, int size, rtx x) |
8640 | { | |
8641 | switch (size) | |
8642 | { | |
8643 | case 4: | |
8644 | fputs ("\t.dtprelword\t", file); | |
8645 | break; | |
8646 | ||
8647 | case 8: | |
8648 | fputs ("\t.dtpreldword\t", file); | |
8649 | break; | |
8650 | ||
8651 | default: | |
8652 | gcc_unreachable (); | |
8653 | } | |
8654 | output_addr_const (file, x); | |
8655 | fputs ("+0x8000", file); | |
8656 | } | |
8657 | ||
8658 | /* Implement TARGET_DWARF_REGISTER_SPAN. */ | |
8659 | ||
8660 | static rtx | |
8661 | mips_dwarf_register_span (rtx reg) | |
8662 | { | |
8663 | rtx high, low; | |
ef4bddc2 | 8664 | machine_mode mode; |
ab77a036 RS |
8665 | |
8666 | /* By default, GCC maps increasing register numbers to increasing | |
8667 | memory locations, but paired FPRs are always little-endian, | |
8668 | regardless of the prevailing endianness. */ | |
8669 | mode = GET_MODE (reg); | |
8670 | if (FP_REG_P (REGNO (reg)) | |
8671 | && TARGET_BIG_ENDIAN | |
8672 | && MAX_FPRS_PER_FMT > 1 | |
8673 | && GET_MODE_SIZE (mode) > UNITS_PER_FPREG) | |
8674 | { | |
8675 | gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE); | |
8676 | high = mips_subword (reg, true); | |
8677 | low = mips_subword (reg, false); | |
8678 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low)); | |
8679 | } | |
8680 | ||
8681 | return NULL_RTX; | |
8682 | } | |
65239d20 | 8683 | |
ef2e5300 SL |
8684 | /* DSP ALU can bypass data with no delays for the following pairs. */ |
8685 | enum insn_code dspalu_bypass_table[][2] = | |
8686 | { | |
8687 | {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc}, | |
8688 | {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb}, | |
8689 | {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb}, | |
8690 | {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb}, | |
8691 | {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph}, | |
8692 | {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph}, | |
8693 | {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph}, | |
8694 | {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv} | |
8695 | }; | |
8696 | ||
8697 | int | |
8698 | mips_dspalu_bypass_p (rtx out_insn, rtx in_insn) | |
8699 | { | |
8700 | int i; | |
8701 | int num_bypass = ARRAY_SIZE (dspalu_bypass_table); | |
8702 | enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn); | |
8703 | enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn); | |
8704 | ||
8705 | for (i = 0; i < num_bypass; i++) | |
8706 | { | |
8707 | if (out_icode == dspalu_bypass_table[i][0] | |
8708 | && in_icode == dspalu_bypass_table[i][1]) | |
8709 | return true; | |
8710 | } | |
8711 | ||
8712 | return false; | |
8713 | } | |
65239d20 | 8714 | /* Implement ASM_OUTPUT_ASCII. */ |
b3276c7a | 8715 | |
7dac2f89 | 8716 | void |
65239d20 | 8717 | mips_output_ascii (FILE *stream, const char *string, size_t len) |
b3276c7a GK |
8718 | { |
8719 | size_t i; | |
65239d20 | 8720 | int cur_pos; |
b3276c7a | 8721 | |
65239d20 RS |
8722 | cur_pos = 17; |
8723 | fprintf (stream, "\t.ascii\t\""); | |
7dac2f89 EC |
8724 | for (i = 0; i < len; i++) |
8725 | { | |
65239d20 | 8726 | int c; |
7dac2f89 | 8727 | |
65239d20 | 8728 | c = (unsigned char) string[i]; |
c5ff069d | 8729 | if (ISPRINT (c)) |
7dac2f89 | 8730 | { |
c5ff069d | 8731 | if (c == '\\' || c == '\"') |
7dac2f89 | 8732 | { |
c5ff069d | 8733 | putc ('\\', stream); |
7dac2f89 EC |
8734 | cur_pos++; |
8735 | } | |
c5ff069d ZW |
8736 | putc (c, stream); |
8737 | cur_pos++; | |
8738 | } | |
8739 | else | |
8740 | { | |
8741 | fprintf (stream, "\\%03o", c); | |
8742 | cur_pos += 4; | |
7dac2f89 EC |
8743 | } |
8744 | ||
8745 | if (cur_pos > 72 && i+1 < len) | |
8746 | { | |
8747 | cur_pos = 17; | |
65239d20 | 8748 | fprintf (stream, "\"\n\t.ascii\t\""); |
7dac2f89 EC |
8749 | } |
8750 | } | |
8751 | fprintf (stream, "\"\n"); | |
b3276c7a | 8752 | } |
65239d20 | 8753 | |
ddaf8125 RS |
8754 | /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR. |
8755 | Update *ADDR with the operand that should be printed. */ | |
8756 | ||
8757 | const char * | |
8758 | mips_output_tls_reloc_directive (rtx *addr) | |
8759 | { | |
8760 | enum mips_symbol_type type; | |
8761 | ||
8762 | type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA); | |
8763 | *addr = mips_strip_unspec_address (*addr); | |
8764 | switch (type) | |
8765 | { | |
8766 | case SYMBOL_DTPREL: | |
8767 | return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0"; | |
8768 | ||
8769 | case SYMBOL_TPREL: | |
8770 | return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0"; | |
8771 | ||
8772 | default: | |
8773 | gcc_unreachable (); | |
8774 | } | |
8775 | } | |
8776 | ||
ab77a036 | 8777 | /* Emit either a label, .comm, or .lcomm directive. When using assembler |
65239d20 RS |
8778 | macros, mark the symbol as written so that mips_asm_output_external |
8779 | won't emit an .extern for it. STREAM is the output file, NAME is the | |
8780 | name of the symbol, INIT_STRING is the string that should be written | |
8781 | before the symbol and FINAL_STRING is the string that should be | |
8782 | written after it. FINAL_STRING is a printf format that consumes the | |
8783 | remaining arguments. */ | |
35f5add9 RS |
8784 | |
8785 | void | |
ab77a036 RS |
8786 | mips_declare_object (FILE *stream, const char *name, const char *init_string, |
8787 | const char *final_string, ...) | |
35f5add9 | 8788 | { |
ab77a036 | 8789 | va_list ap; |
35f5add9 | 8790 | |
ab77a036 RS |
8791 | fputs (init_string, stream); |
8792 | assemble_name (stream, name); | |
8793 | va_start (ap, final_string); | |
8794 | vfprintf (stream, final_string, ap); | |
8795 | va_end (ap); | |
8796 | ||
8797 | if (!TARGET_EXPLICIT_RELOCS) | |
8798 | { | |
8799 | tree name_tree = get_identifier (name); | |
8800 | TREE_ASM_WRITTEN (name_tree) = 1; | |
35f5add9 | 8801 | } |
48b2e0a7 RS |
8802 | } |
8803 | ||
8804 | /* Declare a common object of SIZE bytes using asm directive INIT_STRING. | |
8805 | NAME is the name of the object and ALIGN is the required alignment | |
8806 | in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third | |
8807 | alignment argument. */ | |
8808 | ||
8809 | void | |
8810 | mips_declare_common_object (FILE *stream, const char *name, | |
8811 | const char *init_string, | |
8812 | unsigned HOST_WIDE_INT size, | |
8813 | unsigned int align, bool takes_alignment_p) | |
8814 | { | |
8815 | if (!takes_alignment_p) | |
35f5add9 | 8816 | { |
35f5add9 RS |
8817 | size += (align / BITS_PER_UNIT) - 1; |
8818 | size -= size % (align / BITS_PER_UNIT); | |
48b2e0a7 | 8819 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
8820 | "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size); |
8821 | } | |
8822 | else | |
48b2e0a7 | 8823 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
8824 | "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n", |
8825 | size, align / BITS_PER_UNIT); | |
8826 | } | |
8827 | ||
ab77a036 RS |
8828 | /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the |
8829 | elfos.h version, but we also need to handle -muninit-const-in-rodata. */ | |
9987501f MM |
8830 | |
8831 | void | |
ab77a036 RS |
8832 | mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name, |
8833 | unsigned HOST_WIDE_INT size, | |
8834 | unsigned int align) | |
9987501f | 8835 | { |
ab77a036 RS |
8836 | /* If the target wants uninitialized const declarations in |
8837 | .rdata then don't put them in .comm. */ | |
65239d20 RS |
8838 | if (TARGET_EMBEDDED_DATA |
8839 | && TARGET_UNINIT_CONST_IN_RODATA | |
8840 | && TREE_CODE (decl) == VAR_DECL | |
8841 | && TREE_READONLY (decl) | |
ab77a036 | 8842 | && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) |
9987501f | 8843 | { |
ab77a036 RS |
8844 | if (TREE_PUBLIC (decl) && DECL_NAME (decl)) |
8845 | targetm.asm_out.globalize_label (stream, name); | |
8846 | ||
8847 | switch_to_section (readonly_data_section); | |
8848 | ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); | |
8849 | mips_declare_object (stream, name, "", | |
8850 | ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", | |
8851 | size); | |
9987501f | 8852 | } |
ab77a036 RS |
8853 | else |
8854 | mips_declare_common_object (stream, name, "\n\t.comm\t", | |
8855 | size, align, true); | |
9987501f | 8856 | } |
c1115ccd RS |
8857 | |
8858 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8859 | extern int size_directive_output; | |
8860 | ||
8861 | /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF | |
65239d20 | 8862 | definitions except that it uses mips_declare_object to emit the label. */ |
c1115ccd RS |
8863 | |
8864 | void | |
b4966b1b RS |
8865 | mips_declare_object_name (FILE *stream, const char *name, |
8866 | tree decl ATTRIBUTE_UNUSED) | |
c1115ccd RS |
8867 | { |
8868 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
82563d35 | 8869 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); |
c1115ccd RS |
8870 | #endif |
8871 | ||
82563d35 RS |
8872 | size_directive_output = 0; |
8873 | if (!flag_inhibit_size_directive && DECL_SIZE (decl)) | |
8874 | { | |
8875 | HOST_WIDE_INT size; | |
c1115ccd | 8876 | |
82563d35 RS |
8877 | size_directive_output = 1; |
8878 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8879 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
c1115ccd RS |
8880 | } |
8881 | ||
99a3237a | 8882 | mips_declare_object (stream, name, "", ":\n"); |
c1115ccd RS |
8883 | } |
8884 | ||
8885 | /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */ | |
8886 | ||
8887 | void | |
b4966b1b | 8888 | mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end) |
c1115ccd RS |
8889 | { |
8890 | const char *name; | |
8891 | ||
8892 | name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
82563d35 | 8893 | if (!flag_inhibit_size_directive |
c1115ccd | 8894 | && DECL_SIZE (decl) != 0 |
65239d20 RS |
8895 | && !at_end |
8896 | && top_level | |
c1115ccd RS |
8897 | && DECL_INITIAL (decl) == error_mark_node |
8898 | && !size_directive_output) | |
8899 | { | |
8900 | HOST_WIDE_INT size; | |
8901 | ||
8902 | size_directive_output = 1; | |
8903 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8904 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8905 | } | |
8906 | } | |
8907 | #endif | |
dbe9742d | 8908 | \f |
5f5fe6d9 RS |
8909 | /* Return the FOO in the name of the ".mdebug.FOO" section associated |
8910 | with the current ABI. */ | |
8911 | ||
8912 | static const char * | |
8913 | mips_mdebug_abi_name (void) | |
8914 | { | |
8915 | switch (mips_abi) | |
8916 | { | |
8917 | case ABI_32: | |
8918 | return "abi32"; | |
8919 | case ABI_O64: | |
8920 | return "abiO64"; | |
8921 | case ABI_N32: | |
8922 | return "abiN32"; | |
8923 | case ABI_64: | |
63553059 | 8924 | return "abi64"; |
5f5fe6d9 RS |
8925 | case ABI_EABI: |
8926 | return TARGET_64BIT ? "eabi64" : "eabi32"; | |
8927 | default: | |
8928 | gcc_unreachable (); | |
8929 | } | |
8930 | } | |
8931 | ||
ab77a036 | 8932 | /* Implement TARGET_ASM_FILE_START. */ |
108b61d5 | 8933 | |
ab77a036 RS |
8934 | static void |
8935 | mips_file_start (void) | |
108b61d5 | 8936 | { |
ab77a036 | 8937 | default_file_start (); |
108b61d5 | 8938 | |
65239d20 | 8939 | /* Generate a special section to describe the ABI switches used to |
b24513a1 RO |
8940 | produce the resultant binary. */ |
8941 | ||
8942 | /* Record the ABI itself. Modern versions of binutils encode | |
8943 | this information in the ELF header flags, but GDB needs the | |
8944 | information in order to correctly debug binaries produced by | |
8945 | older binutils. See the function mips_gdbarch_init in | |
8946 | gdb/mips-tdep.c. */ | |
8947 | fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n", | |
8948 | mips_mdebug_abi_name ()); | |
8949 | ||
8950 | /* There is no ELF header flag to distinguish long32 forms of the | |
8951 | EABI from long64 forms. Emit a special section to help tools | |
8952 | such as GDB. Do the same for o64, which is sometimes used with | |
8953 | -mlong64. */ | |
8954 | if (mips_abi == ABI_EABI || mips_abi == ABI_O64) | |
8955 | fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n" | |
8956 | "\t.previous\n", TARGET_LONG64 ? 64 : 32); | |
108b61d5 | 8957 | |
ff3f3951 MR |
8958 | /* Record the NaN encoding. */ |
8959 | if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT) | |
8960 | fprintf (asm_out_file, "\t.nan\t%s\n", | |
8961 | mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy"); | |
8962 | ||
ab77a036 | 8963 | #ifdef HAVE_AS_GNU_ATTRIBUTE |
b24513a1 RO |
8964 | { |
8965 | int attr; | |
8966 | ||
8967 | /* No floating-point operations, -mno-float. */ | |
8968 | if (TARGET_NO_FLOAT) | |
8969 | attr = 0; | |
8970 | /* Soft-float code, -msoft-float. */ | |
8971 | else if (!TARGET_HARD_FLOAT_ABI) | |
8972 | attr = 3; | |
8973 | /* Single-float code, -msingle-float. */ | |
8974 | else if (!TARGET_DOUBLE_FLOAT) | |
8975 | attr = 2; | |
8976 | /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */ | |
8977 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
8978 | attr = 4; | |
8979 | /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */ | |
8980 | else | |
8981 | attr = 1; | |
8982 | ||
8983 | fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr); | |
8984 | } | |
ab77a036 | 8985 | #endif |
280fcbfa | 8986 | |
65239d20 | 8987 | /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */ |
ab77a036 | 8988 | if (TARGET_ABICALLS) |
e21d5757 DJ |
8989 | { |
8990 | fprintf (asm_out_file, "\t.abicalls\n"); | |
8991 | if (TARGET_ABICALLS_PIC0) | |
8992 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
8993 | } | |
108b61d5 | 8994 | |
ab77a036 RS |
8995 | if (flag_verbose_asm) |
8996 | fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", | |
8997 | ASM_COMMENT_START, | |
65239d20 | 8998 | mips_small_data_threshold, mips_arch_info->name, mips_isa); |
108b61d5 | 8999 | } |
78c27266 RS |
9000 | |
9001 | /* Implement TARGET_ASM_CODE_END. */ | |
9002 | ||
9003 | static void | |
9004 | mips_code_end (void) | |
9005 | { | |
6d51cc90 | 9006 | mips_finish_stub (&mips16_rdhwr_stub); |
a90c0245 RS |
9007 | mips_finish_stub (&mips16_get_fcsr_stub); |
9008 | mips_finish_stub (&mips16_set_fcsr_stub); | |
78c27266 | 9009 | } |
108b61d5 | 9010 | \f |
65239d20 | 9011 | /* Make the last instruction frame-related and note that it performs |
ab77a036 | 9012 | the operation described by FRAME_PATTERN. */ |
108b61d5 | 9013 | |
ab77a036 RS |
9014 | static void |
9015 | mips_set_frame_expr (rtx frame_pattern) | |
108b61d5 | 9016 | { |
c6f971f4 | 9017 | rtx_insn *insn; |
280fcbfa | 9018 | |
ab77a036 RS |
9019 | insn = get_last_insn (); |
9020 | RTX_FRAME_RELATED_P (insn) = 1; | |
9021 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
9022 | frame_pattern, | |
9023 | REG_NOTES (insn)); | |
9024 | } | |
280fcbfa | 9025 | |
ab77a036 RS |
9026 | /* Return a frame-related rtx that stores REG at MEM. |
9027 | REG must be a single register. */ | |
108b61d5 | 9028 | |
ab77a036 RS |
9029 | static rtx |
9030 | mips_frame_set (rtx mem, rtx reg) | |
9031 | { | |
9032 | rtx set; | |
108b61d5 | 9033 | |
ab77a036 RS |
9034 | set = gen_rtx_SET (VOIDmode, mem, reg); |
9035 | RTX_FRAME_RELATED_P (set) = 1; | |
a38e0142 | 9036 | |
ab77a036 | 9037 | return set; |
a38e0142 | 9038 | } |
a7449961 BS |
9039 | |
9040 | /* Record that the epilogue has restored call-saved register REG. */ | |
9041 | ||
9042 | static void | |
9043 | mips_add_cfa_restore (rtx reg) | |
9044 | { | |
9045 | mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, | |
9046 | mips_epilogue.cfa_restores); | |
9047 | } | |
ab77a036 RS |
9048 | \f |
9049 | /* If a MIPS16e SAVE or RESTORE instruction saves or restores register | |
9050 | mips16e_s2_s8_regs[X], it must also save the registers in indexes | |
9051 | X + 1 onwards. Likewise mips16e_a0_a3_regs. */ | |
9052 | static const unsigned char mips16e_s2_s8_regs[] = { | |
9053 | 30, 23, 22, 21, 20, 19, 18 | |
9054 | }; | |
9055 | static const unsigned char mips16e_a0_a3_regs[] = { | |
9056 | 4, 5, 6, 7 | |
9057 | }; | |
a38e0142 | 9058 | |
ab77a036 RS |
9059 | /* A list of the registers that can be saved by the MIPS16e SAVE instruction, |
9060 | ordered from the uppermost in memory to the lowest in memory. */ | |
9061 | static const unsigned char mips16e_save_restore_regs[] = { | |
9062 | 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4 | |
9063 | }; | |
f833ffd4 | 9064 | |
e1260576 RS |
9065 | /* Return the index of the lowest X in the range [0, SIZE) for which |
9066 | bit REGS[X] is set in MASK. Return SIZE if there is no such X. */ | |
9067 | ||
9068 | static unsigned int | |
9069 | mips16e_find_first_register (unsigned int mask, const unsigned char *regs, | |
9070 | unsigned int size) | |
9071 | { | |
9072 | unsigned int i; | |
9073 | ||
9074 | for (i = 0; i < size; i++) | |
9075 | if (BITSET_P (mask, regs[i])) | |
9076 | break; | |
9077 | ||
9078 | return i; | |
9079 | } | |
9080 | ||
37017f4d RS |
9081 | /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR |
9082 | is the number of set bits. If *MASK_PTR contains REGS[X] for some X | |
9083 | in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same | |
9084 | is true for all indexes (X, SIZE). */ | |
e1260576 RS |
9085 | |
9086 | static void | |
9087 | mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs, | |
37017f4d | 9088 | unsigned int size, unsigned int *num_regs_ptr) |
e1260576 RS |
9089 | { |
9090 | unsigned int i; | |
9091 | ||
9092 | i = mips16e_find_first_register (*mask_ptr, regs, size); | |
9093 | for (i++; i < size; i++) | |
9094 | if (!BITSET_P (*mask_ptr, regs[i])) | |
9095 | { | |
37017f4d | 9096 | *num_regs_ptr += 1; |
e1260576 RS |
9097 | *mask_ptr |= 1 << regs[i]; |
9098 | } | |
9099 | } | |
f833ffd4 | 9100 | |
ab77a036 RS |
9101 | /* Return a simplified form of X using the register values in REG_VALUES. |
9102 | REG_VALUES[R] is the last value assigned to hard register R, or null | |
9103 | if R has not been modified. | |
cee98a59 | 9104 | |
ab77a036 | 9105 | This function is rather limited, but is good enough for our purposes. */ |
cee98a59 | 9106 | |
ab77a036 RS |
9107 | static rtx |
9108 | mips16e_collect_propagate_value (rtx x, rtx *reg_values) | |
cee98a59 | 9109 | { |
ab77a036 | 9110 | x = avoid_constant_pool_reference (x); |
cee98a59 | 9111 | |
ab77a036 | 9112 | if (UNARY_P (x)) |
9e800206 | 9113 | { |
65239d20 | 9114 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
ab77a036 RS |
9115 | return simplify_gen_unary (GET_CODE (x), GET_MODE (x), |
9116 | x0, GET_MODE (XEXP (x, 0))); | |
9e800206 RH |
9117 | } |
9118 | ||
ab77a036 | 9119 | if (ARITHMETIC_P (x)) |
e1260576 | 9120 | { |
65239d20 RS |
9121 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
9122 | rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values); | |
ab77a036 | 9123 | return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1); |
e1260576 RS |
9124 | } |
9125 | ||
ab77a036 RS |
9126 | if (REG_P (x) |
9127 | && reg_values[REGNO (x)] | |
9128 | && !rtx_unstable_p (reg_values[REGNO (x)])) | |
9129 | return reg_values[REGNO (x)]; | |
cee98a59 | 9130 | |
ab77a036 RS |
9131 | return x; |
9132 | } | |
33563487 | 9133 | |
ab77a036 RS |
9134 | /* Return true if (set DEST SRC) stores an argument register into its |
9135 | caller-allocated save slot, storing the number of that argument | |
9136 | register in *REGNO_PTR if so. REG_VALUES is as for | |
9137 | mips16e_collect_propagate_value. */ | |
cee98a59 | 9138 | |
ab77a036 RS |
9139 | static bool |
9140 | mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values, | |
9141 | unsigned int *regno_ptr) | |
9142 | { | |
9143 | unsigned int argno, regno; | |
9144 | HOST_WIDE_INT offset, required_offset; | |
9145 | rtx addr, base; | |
2bcb2ab3 | 9146 | |
ab77a036 RS |
9147 | /* Check that this is a word-mode store. */ |
9148 | if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode) | |
9149 | return false; | |
258d81a8 | 9150 | |
ab77a036 RS |
9151 | /* Check that the register being saved is an unmodified argument |
9152 | register. */ | |
9153 | regno = REGNO (src); | |
65239d20 | 9154 | if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno]) |
ab77a036 RS |
9155 | return false; |
9156 | argno = regno - GP_ARG_FIRST; | |
e88fb323 | 9157 | |
65239d20 RS |
9158 | /* Check whether the address is an appropriate stack-pointer or |
9159 | frame-pointer access. */ | |
ab77a036 RS |
9160 | addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values); |
9161 | mips_split_plus (addr, &base, &offset); | |
9162 | required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD; | |
9163 | if (base == hard_frame_pointer_rtx) | |
f374e413 | 9164 | required_offset -= cfun->machine->frame.hard_frame_pointer_offset; |
ab77a036 RS |
9165 | else if (base != stack_pointer_rtx) |
9166 | return false; | |
9167 | if (offset != required_offset) | |
9168 | return false; | |
cee98a59 | 9169 | |
ab77a036 RS |
9170 | *regno_ptr = regno; |
9171 | return true; | |
cee98a59 | 9172 | } |
b2471838 | 9173 | |
ab77a036 RS |
9174 | /* A subroutine of mips_expand_prologue, called only when generating |
9175 | MIPS16e SAVE instructions. Search the start of the function for any | |
9176 | instructions that save argument registers into their caller-allocated | |
9177 | save slots. Delete such instructions and return a value N such that | |
9178 | saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted | |
9179 | instructions redundant. */ | |
b2471838 | 9180 | |
ab77a036 RS |
9181 | static unsigned int |
9182 | mips16e_collect_argument_saves (void) | |
9183 | { | |
9184 | rtx reg_values[FIRST_PSEUDO_REGISTER]; | |
c6f971f4 DM |
9185 | rtx_insn *insn, *next; |
9186 | rtx set, dest, src; | |
ab77a036 | 9187 | unsigned int nargs, regno; |
84879759 | 9188 | |
ab77a036 RS |
9189 | push_topmost_sequence (); |
9190 | nargs = 0; | |
9191 | memset (reg_values, 0, sizeof (reg_values)); | |
9192 | for (insn = get_insns (); insn; insn = next) | |
b2471838 | 9193 | { |
ab77a036 | 9194 | next = NEXT_INSN (insn); |
006b29ab | 9195 | if (NOTE_P (insn) || DEBUG_INSN_P (insn)) |
ab77a036 | 9196 | continue; |
b2471838 | 9197 | |
ab77a036 RS |
9198 | if (!INSN_P (insn)) |
9199 | break; | |
b2471838 | 9200 | |
ab77a036 RS |
9201 | set = PATTERN (insn); |
9202 | if (GET_CODE (set) != SET) | |
9203 | break; | |
9204 | ||
9205 | dest = SET_DEST (set); | |
9206 | src = SET_SRC (set); | |
9207 | if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no)) | |
9208 | { | |
9209 | if (!BITSET_P (cfun->machine->frame.mask, regno)) | |
9210 | { | |
9211 | delete_insn (insn); | |
9212 | nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1); | |
9213 | } | |
9214 | } | |
9215 | else if (REG_P (dest) && GET_MODE (dest) == word_mode) | |
9216 | reg_values[REGNO (dest)] | |
9217 | = mips16e_collect_propagate_value (src, reg_values); | |
9218 | else | |
9219 | break; | |
b2471838 | 9220 | } |
ab77a036 | 9221 | pop_topmost_sequence (); |
b2471838 | 9222 | |
ab77a036 RS |
9223 | return nargs; |
9224 | } | |
b2471838 | 9225 | |
ab77a036 | 9226 | /* Return a move between register REGNO and memory location SP + OFFSET. |
42ae51f4 RS |
9227 | REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE. |
9228 | Make the move a load if RESTORE_P, otherwise make it a store. */ | |
67070ffe | 9229 | |
ab77a036 | 9230 | static rtx |
42ae51f4 RS |
9231 | mips16e_save_restore_reg (bool restore_p, bool reg_parm_p, |
9232 | HOST_WIDE_INT offset, unsigned int regno) | |
67070ffe | 9233 | { |
ab77a036 | 9234 | rtx reg, mem; |
1cbfdb1f | 9235 | |
0a81f074 RS |
9236 | mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx, |
9237 | offset)); | |
ab77a036 | 9238 | reg = gen_rtx_REG (SImode, regno); |
42ae51f4 | 9239 | if (restore_p) |
3bd0817d | 9240 | { |
a7449961 | 9241 | mips_add_cfa_restore (reg); |
3bd0817d RS |
9242 | return gen_rtx_SET (VOIDmode, reg, mem); |
9243 | } | |
42ae51f4 RS |
9244 | if (reg_parm_p) |
9245 | return gen_rtx_SET (VOIDmode, mem, reg); | |
9246 | return mips_frame_set (mem, reg); | |
1cbfdb1f RS |
9247 | } |
9248 | ||
ab77a036 RS |
9249 | /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which. |
9250 | The instruction must: | |
1cbfdb1f | 9251 | |
ab77a036 RS |
9252 | - Allocate or deallocate SIZE bytes in total; SIZE is known |
9253 | to be nonzero. | |
cee98a59 | 9254 | |
ab77a036 RS |
9255 | - Save or restore as many registers in *MASK_PTR as possible. |
9256 | The instruction saves the first registers at the top of the | |
9257 | allocated area, with the other registers below it. | |
cee98a59 | 9258 | |
ab77a036 | 9259 | - Save NARGS argument registers above the allocated area. |
b85aed9e | 9260 | |
ab77a036 | 9261 | (NARGS is always zero if RESTORE_P.) |
b85aed9e | 9262 | |
ab77a036 RS |
9263 | The SAVE and RESTORE instructions cannot save and restore all general |
9264 | registers, so there may be some registers left over for the caller to | |
9265 | handle. Destructively modify *MASK_PTR so that it contains the registers | |
9266 | that still need to be saved or restored. The caller can save these | |
9267 | registers in the memory immediately below *OFFSET_PTR, which is a | |
9268 | byte offset from the bottom of the allocated stack area. */ | |
d9870b7e | 9269 | |
ab77a036 RS |
9270 | static rtx |
9271 | mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr, | |
9272 | HOST_WIDE_INT *offset_ptr, unsigned int nargs, | |
9273 | HOST_WIDE_INT size) | |
d9870b7e | 9274 | { |
ab77a036 RS |
9275 | rtx pattern, set; |
9276 | HOST_WIDE_INT offset, top_offset; | |
9277 | unsigned int i, regno; | |
9278 | int n; | |
8cb6400c | 9279 | |
ddc4af9c | 9280 | gcc_assert (cfun->machine->frame.num_fp == 0); |
d9870b7e | 9281 | |
ab77a036 RS |
9282 | /* Calculate the number of elements in the PARALLEL. We need one element |
9283 | for the stack adjustment, one for each argument register save, and one | |
9284 | for each additional register move. */ | |
9285 | n = 1 + nargs; | |
9286 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
9287 | if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i])) | |
9288 | n++; | |
d9870b7e | 9289 | |
ab77a036 RS |
9290 | /* Create the final PARALLEL. */ |
9291 | pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n)); | |
9292 | n = 0; | |
d9870b7e | 9293 | |
ab77a036 RS |
9294 | /* Add the stack pointer adjustment. */ |
9295 | set = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
0a81f074 | 9296 | plus_constant (Pmode, stack_pointer_rtx, |
ab77a036 RS |
9297 | restore_p ? size : -size)); |
9298 | RTX_FRAME_RELATED_P (set) = 1; | |
9299 | XVECEXP (pattern, 0, n++) = set; | |
d9870b7e | 9300 | |
ab77a036 RS |
9301 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
9302 | top_offset = restore_p ? size : 0; | |
b85aed9e | 9303 | |
ab77a036 RS |
9304 | /* Save the arguments. */ |
9305 | for (i = 0; i < nargs; i++) | |
9306 | { | |
6e75e6e3 | 9307 | offset = top_offset + i * UNITS_PER_WORD; |
42ae51f4 RS |
9308 | set = mips16e_save_restore_reg (restore_p, true, offset, |
9309 | GP_ARG_FIRST + i); | |
ab77a036 RS |
9310 | XVECEXP (pattern, 0, n++) = set; |
9311 | } | |
d9870b7e | 9312 | |
ab77a036 RS |
9313 | /* Then fill in the other register moves. */ |
9314 | offset = top_offset; | |
9315 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
b85aed9e | 9316 | { |
ab77a036 RS |
9317 | regno = mips16e_save_restore_regs[i]; |
9318 | if (BITSET_P (*mask_ptr, regno)) | |
d9870b7e | 9319 | { |
ab77a036 | 9320 | offset -= UNITS_PER_WORD; |
42ae51f4 | 9321 | set = mips16e_save_restore_reg (restore_p, false, offset, regno); |
ab77a036 RS |
9322 | XVECEXP (pattern, 0, n++) = set; |
9323 | *mask_ptr &= ~(1 << regno); | |
d9870b7e | 9324 | } |
ab77a036 | 9325 | } |
b85aed9e | 9326 | |
ab77a036 | 9327 | /* Tell the caller what offset it should use for the remaining registers. */ |
b87bc4e8 | 9328 | *offset_ptr = size + (offset - top_offset); |
d9870b7e | 9329 | |
ab77a036 | 9330 | gcc_assert (n == XVECLEN (pattern, 0)); |
8cb6400c | 9331 | |
ab77a036 | 9332 | return pattern; |
b85aed9e RS |
9333 | } |
9334 | ||
ab77a036 RS |
9335 | /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack |
9336 | pointer. Return true if PATTERN matches the kind of instruction | |
9337 | generated by mips16e_build_save_restore. If INFO is nonnull, | |
9338 | initialize it when returning true. */ | |
cee98a59 | 9339 | |
ab77a036 RS |
9340 | bool |
9341 | mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust, | |
9342 | struct mips16e_save_restore_info *info) | |
cee98a59 | 9343 | { |
37017f4d RS |
9344 | unsigned int i, nargs, mask, extra; |
9345 | HOST_WIDE_INT top_offset, save_offset, offset; | |
ab77a036 RS |
9346 | rtx set, reg, mem, base; |
9347 | int n; | |
cee98a59 | 9348 | |
ab77a036 RS |
9349 | if (!GENERATE_MIPS16E_SAVE_RESTORE) |
9350 | return false; | |
2bcb2ab3 | 9351 | |
ab77a036 RS |
9352 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
9353 | top_offset = adjust > 0 ? adjust : 0; | |
f9e4a411 | 9354 | |
ab77a036 | 9355 | /* Interpret all other members of the PARALLEL. */ |
6e75e6e3 | 9356 | save_offset = top_offset - UNITS_PER_WORD; |
ab77a036 RS |
9357 | mask = 0; |
9358 | nargs = 0; | |
9359 | i = 0; | |
9360 | for (n = 1; n < XVECLEN (pattern, 0); n++) | |
e9a25f70 | 9361 | { |
ab77a036 RS |
9362 | /* Check that we have a SET. */ |
9363 | set = XVECEXP (pattern, 0, n); | |
9364 | if (GET_CODE (set) != SET) | |
9365 | return false; | |
3c7404d3 | 9366 | |
ab77a036 RS |
9367 | /* Check that the SET is a load (if restoring) or a store |
9368 | (if saving). */ | |
9369 | mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set); | |
9370 | if (!MEM_P (mem)) | |
9371 | return false; | |
3c7404d3 | 9372 | |
ab77a036 RS |
9373 | /* Check that the address is the sum of the stack pointer and a |
9374 | possibly-zero constant offset. */ | |
9375 | mips_split_plus (XEXP (mem, 0), &base, &offset); | |
9376 | if (base != stack_pointer_rtx) | |
9377 | return false; | |
82563d35 | 9378 | |
ab77a036 RS |
9379 | /* Check that SET's other operand is a register. */ |
9380 | reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set); | |
9381 | if (!REG_P (reg)) | |
9382 | return false; | |
e9a25f70 | 9383 | |
ab77a036 | 9384 | /* Check for argument saves. */ |
6e75e6e3 | 9385 | if (offset == top_offset + nargs * UNITS_PER_WORD |
ab77a036 RS |
9386 | && REGNO (reg) == GP_ARG_FIRST + nargs) |
9387 | nargs++; | |
9388 | else if (offset == save_offset) | |
9389 | { | |
9390 | while (mips16e_save_restore_regs[i++] != REGNO (reg)) | |
9391 | if (i == ARRAY_SIZE (mips16e_save_restore_regs)) | |
9392 | return false; | |
a50f2a09 | 9393 | |
ab77a036 | 9394 | mask |= 1 << REGNO (reg); |
6e75e6e3 | 9395 | save_offset -= UNITS_PER_WORD; |
ab77a036 RS |
9396 | } |
9397 | else | |
9398 | return false; | |
e9a25f70 | 9399 | } |
ffa9d0b1 | 9400 | |
ab77a036 RS |
9401 | /* Check that the restrictions on register ranges are met. */ |
9402 | extra = 0; | |
9403 | mips16e_mask_registers (&mask, mips16e_s2_s8_regs, | |
9404 | ARRAY_SIZE (mips16e_s2_s8_regs), &extra); | |
9405 | mips16e_mask_registers (&mask, mips16e_a0_a3_regs, | |
9406 | ARRAY_SIZE (mips16e_a0_a3_regs), &extra); | |
9407 | if (extra != 0) | |
9408 | return false; | |
9409 | ||
9410 | /* Make sure that the topmost argument register is not saved twice. | |
9411 | The checks above ensure that the same is then true for the other | |
9412 | argument registers. */ | |
9413 | if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1)) | |
9414 | return false; | |
9415 | ||
9416 | /* Pass back information, if requested. */ | |
9417 | if (info) | |
6f2993e5 | 9418 | { |
ab77a036 RS |
9419 | info->nargs = nargs; |
9420 | info->mask = mask; | |
9421 | info->size = (adjust > 0 ? adjust : -adjust); | |
6f2993e5 | 9422 | } |
b85aed9e | 9423 | |
ab77a036 | 9424 | return true; |
f833ffd4 | 9425 | } |
be763023 | 9426 | |
ab77a036 RS |
9427 | /* Add a MIPS16e SAVE or RESTORE register-range argument to string S |
9428 | for the register range [MIN_REG, MAX_REG]. Return a pointer to | |
9429 | the null terminator. */ | |
be763023 | 9430 | |
ab77a036 RS |
9431 | static char * |
9432 | mips16e_add_register_range (char *s, unsigned int min_reg, | |
9433 | unsigned int max_reg) | |
9434 | { | |
9435 | if (min_reg != max_reg) | |
9436 | s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]); | |
9437 | else | |
9438 | s += sprintf (s, ",%s", reg_names[min_reg]); | |
9439 | return s; | |
be763023 RS |
9440 | } |
9441 | ||
ab77a036 RS |
9442 | /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction. |
9443 | PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */ | |
be763023 | 9444 | |
ab77a036 RS |
9445 | const char * |
9446 | mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust) | |
be763023 | 9447 | { |
ab77a036 | 9448 | static char buffer[300]; |
1de2bc2a | 9449 | |
ab77a036 RS |
9450 | struct mips16e_save_restore_info info; |
9451 | unsigned int i, end; | |
9452 | char *s; | |
1de2bc2a | 9453 | |
ab77a036 RS |
9454 | /* Parse the pattern. */ |
9455 | if (!mips16e_save_restore_pattern_p (pattern, adjust, &info)) | |
9456 | gcc_unreachable (); | |
be763023 | 9457 | |
ab77a036 RS |
9458 | /* Add the mnemonic. */ |
9459 | s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t"); | |
9460 | s += strlen (s); | |
be763023 | 9461 | |
ab77a036 RS |
9462 | /* Save the arguments. */ |
9463 | if (info.nargs > 1) | |
9464 | s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST], | |
9465 | reg_names[GP_ARG_FIRST + info.nargs - 1]); | |
9466 | else if (info.nargs == 1) | |
9467 | s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]); | |
be763023 | 9468 | |
ab77a036 RS |
9469 | /* Emit the amount of stack space to allocate or deallocate. */ |
9470 | s += sprintf (s, "%d", (int) info.size); | |
be763023 | 9471 | |
ab77a036 RS |
9472 | /* Save or restore $16. */ |
9473 | if (BITSET_P (info.mask, 16)) | |
9474 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]); | |
936b1317 | 9475 | |
ab77a036 RS |
9476 | /* Save or restore $17. */ |
9477 | if (BITSET_P (info.mask, 17)) | |
9478 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]); | |
be763023 | 9479 | |
ab77a036 RS |
9480 | /* Save or restore registers in the range $s2...$s8, which |
9481 | mips16e_s2_s8_regs lists in decreasing order. Note that this | |
9482 | is a software register range; the hardware registers are not | |
9483 | numbered consecutively. */ | |
9484 | end = ARRAY_SIZE (mips16e_s2_s8_regs); | |
9485 | i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end); | |
9486 | if (i < end) | |
9487 | s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1], | |
9488 | mips16e_s2_s8_regs[i]); | |
be763023 | 9489 | |
ab77a036 RS |
9490 | /* Save or restore registers in the range $a0...$a3. */ |
9491 | end = ARRAY_SIZE (mips16e_a0_a3_regs); | |
9492 | i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end); | |
9493 | if (i < end) | |
9494 | s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i], | |
9495 | mips16e_a0_a3_regs[end - 1]); | |
e1260576 | 9496 | |
ab77a036 | 9497 | /* Save or restore $31. */ |
293593b1 RS |
9498 | if (BITSET_P (info.mask, RETURN_ADDR_REGNUM)) |
9499 | s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]); | |
e1260576 | 9500 | |
ab77a036 | 9501 | return buffer; |
e1260576 | 9502 | } |
ab77a036 | 9503 | \f |
0c433c31 RS |
9504 | /* Return true if the current function returns its value in a floating-point |
9505 | register in MIPS16 mode. */ | |
e1260576 | 9506 | |
ab77a036 | 9507 | static bool |
0c433c31 | 9508 | mips16_cfun_returns_in_fpr_p (void) |
ab77a036 | 9509 | { |
0c433c31 RS |
9510 | tree return_type = DECL_RESULT (current_function_decl); |
9511 | return (TARGET_MIPS16 | |
9512 | && TARGET_HARD_FLOAT_ABI | |
9513 | && !aggregate_value_p (return_type, current_function_decl) | |
9514 | && mips_return_mode_in_fpr_p (DECL_MODE (return_type))); | |
9515 | } | |
e1260576 | 9516 | |
0c433c31 RS |
9517 | /* Return true if predicate PRED is true for at least one instruction. |
9518 | Cache the result in *CACHE, and assume that the result is true | |
9519 | if *CACHE is already true. */ | |
9520 | ||
9521 | static bool | |
c6f971f4 | 9522 | mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *)) |
0c433c31 | 9523 | { |
c6f971f4 | 9524 | rtx_insn *insn; |
0c433c31 RS |
9525 | |
9526 | if (!*cache) | |
9527 | { | |
ab77a036 RS |
9528 | push_topmost_sequence (); |
9529 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
0c433c31 | 9530 | if (USEFUL_INSN_P (insn) && pred (insn)) |
65239d20 | 9531 | { |
0c433c31 | 9532 | *cache = true; |
65239d20 RS |
9533 | break; |
9534 | } | |
ab77a036 | 9535 | pop_topmost_sequence (); |
ab77a036 | 9536 | } |
0c433c31 | 9537 | return *cache; |
ab77a036 | 9538 | } |
e1260576 | 9539 | |
0c433c31 RS |
9540 | /* Return true if INSN refers to the global pointer in an "inflexible" way. |
9541 | See mips_cfun_has_inflexible_gp_ref_p for details. */ | |
7462a715 RS |
9542 | |
9543 | static bool | |
c6f971f4 | 9544 | mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn) |
7462a715 | 9545 | { |
0c433c31 RS |
9546 | /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE |
9547 | indicate that the target could be a traditional MIPS | |
9548 | lazily-binding stub. */ | |
9549 | return find_reg_fusage (insn, USE, pic_offset_table_rtx); | |
9550 | } | |
9551 | ||
9552 | /* Return true if the current function refers to the global pointer | |
9553 | in a way that forces $28 to be valid. This means that we can't | |
9554 | change the choice of global pointer, even for NewABI code. | |
9555 | ||
9556 | One example of this (and one which needs several checks) is that | |
9557 | $28 must be valid when calling traditional MIPS lazy-binding stubs. | |
9558 | (This restriction does not apply to PLTs.) */ | |
9559 | ||
9560 | static bool | |
9561 | mips_cfun_has_inflexible_gp_ref_p (void) | |
9562 | { | |
9563 | /* If the function has a nonlocal goto, $28 must hold the correct | |
9564 | global pointer for the target function. That is, the target | |
9565 | of the goto implicitly uses $28. */ | |
9566 | if (crtl->has_nonlocal_goto) | |
9567 | return true; | |
9568 | ||
9569 | if (TARGET_ABICALLS_PIC2) | |
9570 | { | |
9571 | /* Symbolic accesses implicitly use the global pointer unless | |
9572 | -mexplicit-relocs is in effect. JAL macros to symbolic addresses | |
9573 | might go to traditional MIPS lazy-binding stubs. */ | |
9574 | if (!TARGET_EXPLICIT_RELOCS) | |
9575 | return true; | |
9576 | ||
9577 | /* FUNCTION_PROFILER includes a JAL to _mcount, which again | |
9578 | can be lazily-bound. */ | |
9579 | if (crtl->profile) | |
9580 | return true; | |
9581 | ||
9582 | /* MIPS16 functions that return in FPRs need to call an | |
9583 | external libgcc routine. This call is only made explict | |
9584 | during mips_expand_epilogue, and it too might be lazily bound. */ | |
9585 | if (mips16_cfun_returns_in_fpr_p ()) | |
9586 | return true; | |
9587 | } | |
9588 | ||
9589 | return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p, | |
9590 | mips_insn_has_inflexible_gp_ref_p); | |
9591 | } | |
9592 | ||
9593 | /* Return true if INSN refers to the global pointer in a "flexible" way. | |
9594 | See mips_cfun_has_flexible_gp_ref_p for details. */ | |
9595 | ||
9596 | static bool | |
c6f971f4 | 9597 | mips_insn_has_flexible_gp_ref_p (rtx_insn *insn) |
0c433c31 RS |
9598 | { |
9599 | return (get_attr_got (insn) != GOT_UNSET | |
9600 | || mips_small_data_pattern_p (PATTERN (insn)) | |
9601 | || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn))); | |
9602 | } | |
9603 | ||
9604 | /* Return true if the current function references the global pointer, | |
9605 | but if those references do not inherently require the global pointer | |
9606 | to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */ | |
9607 | ||
9608 | static bool | |
9609 | mips_cfun_has_flexible_gp_ref_p (void) | |
9610 | { | |
9611 | /* Reload can sometimes introduce constant pool references | |
9612 | into a function that otherwise didn't need them. For example, | |
9613 | suppose we have an instruction like: | |
9614 | ||
9615 | (set (reg:DF R1) (float:DF (reg:SI R2))) | |
9616 | ||
9617 | If R2 turns out to be a constant such as 1, the instruction may | |
9618 | have a REG_EQUAL note saying that R1 == 1.0. Reload then has | |
9619 | the option of using this constant if R2 doesn't get allocated | |
9620 | to a register. | |
9621 | ||
9622 | In cases like these, reload will have added the constant to the | |
9623 | pool but no instruction will yet refer to it. */ | |
9624 | if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool) | |
9625 | return true; | |
9626 | ||
9627 | return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p, | |
9628 | mips_insn_has_flexible_gp_ref_p); | |
7462a715 RS |
9629 | } |
9630 | ||
ab77a036 | 9631 | /* Return the register that should be used as the global pointer |
8d9d9172 RS |
9632 | within this function. Return INVALID_REGNUM if the function |
9633 | doesn't need a global pointer. */ | |
e1260576 | 9634 | |
ab77a036 RS |
9635 | static unsigned int |
9636 | mips_global_pointer (void) | |
e1260576 | 9637 | { |
ab77a036 | 9638 | unsigned int regno; |
e1260576 | 9639 | |
ab77a036 RS |
9640 | /* $gp is always available unless we're using a GOT. */ |
9641 | if (!TARGET_USE_GOT) | |
9642 | return GLOBAL_POINTER_REGNUM; | |
e1260576 | 9643 | |
0c433c31 RS |
9644 | /* If there are inflexible references to $gp, we must use the |
9645 | standard register. */ | |
9646 | if (mips_cfun_has_inflexible_gp_ref_p ()) | |
ab77a036 | 9647 | return GLOBAL_POINTER_REGNUM; |
e1260576 | 9648 | |
0c433c31 RS |
9649 | /* If there are no current references to $gp, then the only uses |
9650 | we can introduce later are those involved in long branches. */ | |
9651 | if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ()) | |
9652 | return INVALID_REGNUM; | |
e21d5757 | 9653 | |
0c433c31 RS |
9654 | /* If the global pointer is call-saved, try to use a call-clobbered |
9655 | alternative. */ | |
416ff32e | 9656 | if (TARGET_CALL_SAVED_GP && crtl->is_leaf) |
ab77a036 RS |
9657 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) |
9658 | if (!df_regs_ever_live_p (regno) | |
9659 | && call_really_used_regs[regno] | |
9660 | && !fixed_regs[regno] | |
9661 | && regno != PIC_FUNCTION_ADDR_REGNUM) | |
9662 | return regno; | |
e1260576 | 9663 | |
ab77a036 | 9664 | return GLOBAL_POINTER_REGNUM; |
e1260576 RS |
9665 | } |
9666 | ||
293593b1 | 9667 | /* Return true if the current function's prologue must load the global |
0c433c31 RS |
9668 | pointer value into pic_offset_table_rtx and store the same value in |
9669 | the function's cprestore slot (if any). | |
9670 | ||
9671 | One problem we have to deal with is that, when emitting GOT-based | |
9672 | position independent code, long-branch sequences will need to load | |
9673 | the address of the branch target from the GOT. We don't know until | |
9674 | the very end of compilation whether (and where) the function needs | |
9675 | long branches, so we must ensure that _any_ branch can access the | |
9676 | global pointer in some form. However, we do not want to pessimize | |
9677 | the usual case in which all branches are short. | |
9678 | ||
9679 | We handle this as follows: | |
9680 | ||
9681 | (1) During reload, we set cfun->machine->global_pointer to | |
9682 | INVALID_REGNUM if we _know_ that the current function | |
9683 | doesn't need a global pointer. This is only valid if | |
9684 | long branches don't need the GOT. | |
9685 | ||
9686 | Otherwise, we assume that we might need a global pointer | |
9687 | and pick an appropriate register. | |
9688 | ||
9689 | (2) If cfun->machine->global_pointer != INVALID_REGNUM, | |
9690 | we ensure that the global pointer is available at every | |
9691 | block boundary bar entry and exit. We do this in one of two ways: | |
9692 | ||
9693 | - If the function has a cprestore slot, we ensure that this | |
9694 | slot is valid at every branch. However, as explained in | |
9695 | point (6) below, there is no guarantee that pic_offset_table_rtx | |
9696 | itself is valid if new uses of the global pointer are introduced | |
9697 | after the first post-epilogue split. | |
9698 | ||
9699 | We guarantee that the cprestore slot is valid by loading it | |
9700 | into a fake register, CPRESTORE_SLOT_REGNUM. We then make | |
9701 | this register live at every block boundary bar function entry | |
9702 | and exit. It is then invalid to move the load (and thus the | |
9703 | preceding store) across a block boundary. | |
9704 | ||
9705 | - If the function has no cprestore slot, we guarantee that | |
9706 | pic_offset_table_rtx itself is valid at every branch. | |
9707 | ||
9708 | See mips_eh_uses for the handling of the register liveness. | |
9709 | ||
9710 | (3) During prologue and epilogue generation, we emit "ghost" | |
9711 | placeholder instructions to manipulate the global pointer. | |
9712 | ||
9713 | (4) During prologue generation, we set cfun->machine->must_initialize_gp_p | |
9714 | and cfun->machine->must_restore_gp_when_clobbered_p if we already know | |
9715 | that the function needs a global pointer. (There is no need to set | |
9716 | them earlier than this, and doing it as late as possible leads to | |
9717 | fewer false positives.) | |
9718 | ||
9719 | (5) If cfun->machine->must_initialize_gp_p is true during a | |
9720 | split_insns pass, we split the ghost instructions into real | |
9721 | instructions. These split instructions can then be optimized in | |
9722 | the usual way. Otherwise, we keep the ghost instructions intact, | |
9723 | and optimize for the case where they aren't needed. We still | |
9724 | have the option of splitting them later, if we need to introduce | |
9725 | new uses of the global pointer. | |
9726 | ||
9727 | For example, the scheduler ignores a ghost instruction that | |
9728 | stores $28 to the stack, but it handles the split form of | |
9729 | the ghost instruction as an ordinary store. | |
9730 | ||
9731 | (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p | |
9732 | is true during the first post-epilogue split_insns pass, we split | |
9733 | calls and restore_gp patterns into instructions that explicitly | |
9734 | load pic_offset_table_rtx from the cprestore slot. Otherwise, | |
9735 | we split these patterns into instructions that _don't_ load from | |
9736 | the cprestore slot. | |
9737 | ||
9738 | If cfun->machine->must_restore_gp_when_clobbered_p is true at the | |
9739 | time of the split, then any instructions that exist at that time | |
9740 | can make free use of pic_offset_table_rtx. However, if we want | |
9741 | to introduce new uses of the global pointer after the split, | |
9742 | we must explicitly load the value from the cprestore slot, since | |
9743 | pic_offset_table_rtx itself might not be valid at a given point | |
9744 | in the function. | |
9745 | ||
9746 | The idea is that we want to be able to delete redundant | |
9747 | loads from the cprestore slot in the usual case where no | |
9748 | long branches are needed. | |
9749 | ||
9750 | (7) If cfun->machine->must_initialize_gp_p is still false at the end | |
9751 | of md_reorg, we decide whether the global pointer is needed for | |
9752 | long branches. If so, we set cfun->machine->must_initialize_gp_p | |
9753 | to true and split the ghost instructions into real instructions | |
9754 | at that stage. | |
9755 | ||
9756 | Note that the ghost instructions must have a zero length for three reasons: | |
9757 | ||
9758 | - Giving the length of the underlying $gp sequence might cause | |
9759 | us to use long branches in cases where they aren't really needed. | |
9760 | ||
9761 | - They would perturb things like alignment calculations. | |
9762 | ||
9763 | - More importantly, the hazard detection in md_reorg relies on | |
9764 | empty instructions having a zero length. | |
9765 | ||
9766 | If we find a long branch and split the ghost instructions at the | |
9767 | end of md_reorg, the split could introduce more long branches. | |
9768 | That isn't a problem though, because we still do the split before | |
9769 | the final shorten_branches pass. | |
9770 | ||
9771 | This is extremely ugly, but it seems like the best compromise between | |
9772 | correctness and efficiency. */ | |
9773 | ||
9774 | bool | |
9775 | mips_must_initialize_gp_p (void) | |
9776 | { | |
9777 | return cfun->machine->must_initialize_gp_p; | |
9778 | } | |
9779 | ||
e19da24c CF |
9780 | /* Return true if REGNO is a register that is ordinarily call-clobbered |
9781 | but must nevertheless be preserved by an interrupt handler. */ | |
9782 | ||
9783 | static bool | |
9784 | mips_interrupt_extra_call_saved_reg_p (unsigned int regno) | |
9785 | { | |
9786 | if (MD_REG_P (regno)) | |
9787 | return true; | |
9788 | ||
9789 | if (TARGET_DSP && DSP_ACC_REG_P (regno)) | |
9790 | return true; | |
9791 | ||
9792 | if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p) | |
9793 | { | |
9794 | /* $0 is hard-wired. */ | |
9795 | if (regno == GP_REG_FIRST) | |
9796 | return false; | |
9797 | ||
9798 | /* The interrupt handler can treat kernel registers as | |
9799 | scratch registers. */ | |
9800 | if (KERNEL_REG_P (regno)) | |
9801 | return false; | |
9802 | ||
9803 | /* The function will return the stack pointer to its original value | |
9804 | anyway. */ | |
9805 | if (regno == STACK_POINTER_REGNUM) | |
9806 | return false; | |
9807 | ||
9808 | /* Otherwise, return true for registers that aren't ordinarily | |
9809 | call-clobbered. */ | |
9810 | return call_really_used_regs[regno]; | |
9811 | } | |
9812 | ||
9813 | return false; | |
9814 | } | |
9815 | ||
7cc003b5 RS |
9816 | /* Return true if the current function should treat register REGNO |
9817 | as call-saved. */ | |
e1260576 | 9818 | |
ab77a036 | 9819 | static bool |
7cc003b5 RS |
9820 | mips_cfun_call_saved_reg_p (unsigned int regno) |
9821 | { | |
b14ee6c9 RS |
9822 | /* If the user makes an ordinarily-call-saved register global, |
9823 | that register is no longer call-saved. */ | |
9824 | if (global_regs[regno]) | |
9825 | return false; | |
9826 | ||
e19da24c CF |
9827 | /* Interrupt handlers need to save extra registers. */ |
9828 | if (cfun->machine->interrupt_handler_p | |
9829 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
9830 | return true; | |
9831 | ||
7cc003b5 RS |
9832 | /* call_insns preserve $28 unless they explicitly say otherwise, |
9833 | so call_really_used_regs[] treats $28 as call-saved. However, | |
9834 | we want the ABI property rather than the default call_insn | |
9835 | property here. */ | |
9836 | return (regno == GLOBAL_POINTER_REGNUM | |
9837 | ? TARGET_CALL_SAVED_GP | |
9838 | : !call_really_used_regs[regno]); | |
9839 | } | |
9840 | ||
9841 | /* Return true if the function body might clobber register REGNO. | |
9842 | We know that REGNO is call-saved. */ | |
9843 | ||
9844 | static bool | |
9845 | mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno) | |
ab77a036 | 9846 | { |
7cc003b5 RS |
9847 | /* Some functions should be treated as clobbering all call-saved |
9848 | registers. */ | |
9849 | if (crtl->saves_all_registers) | |
4817c43b | 9850 | return true; |
e1260576 | 9851 | |
7cc003b5 RS |
9852 | /* DF handles cases where a register is explicitly referenced in |
9853 | the rtl. Incoming values are passed in call-clobbered registers, | |
9854 | so we can assume that any live call-saved register is set within | |
9855 | the function. */ | |
9856 | if (df_regs_ever_live_p (regno)) | |
ab77a036 | 9857 | return true; |
e1260576 | 9858 | |
7cc003b5 RS |
9859 | /* Check for registers that are clobbered by FUNCTION_PROFILER. |
9860 | These clobbers are not explicit in the rtl. */ | |
9861 | if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno)) | |
9862 | return true; | |
9863 | ||
9864 | /* If we're using a call-saved global pointer, the function's | |
9865 | prologue will need to set it up. */ | |
9866 | if (cfun->machine->global_pointer == regno) | |
ab77a036 | 9867 | return true; |
106b3d40 | 9868 | |
7cc003b5 RS |
9869 | /* The function's prologue will need to set the frame pointer if |
9870 | frame_pointer_needed. */ | |
ab77a036 RS |
9871 | if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) |
9872 | return true; | |
e1260576 | 9873 | |
7cc003b5 RS |
9874 | /* If a MIPS16 function returns a value in FPRs, its epilogue |
9875 | will need to call an external libgcc routine. This yet-to-be | |
9876 | generated call_insn will clobber $31. */ | |
293593b1 | 9877 | if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ()) |
ab77a036 | 9878 | return true; |
e1260576 | 9879 | |
e19da24c CF |
9880 | /* If REGNO is ordinarily call-clobbered, we must assume that any |
9881 | called function could modify it. */ | |
9882 | if (cfun->machine->interrupt_handler_p | |
416ff32e | 9883 | && !crtl->is_leaf |
e19da24c CF |
9884 | && mips_interrupt_extra_call_saved_reg_p (regno)) |
9885 | return true; | |
9886 | ||
7cc003b5 RS |
9887 | return false; |
9888 | } | |
9889 | ||
9890 | /* Return true if the current function must save register REGNO. */ | |
9891 | ||
9892 | static bool | |
9893 | mips_save_reg_p (unsigned int regno) | |
9894 | { | |
9895 | if (mips_cfun_call_saved_reg_p (regno)) | |
9896 | { | |
9897 | if (mips_cfun_might_clobber_call_saved_reg_p (regno)) | |
9898 | return true; | |
9899 | ||
9900 | /* Save both registers in an FPR pair if either one is used. This is | |
9901 | needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd | |
9902 | register to be used without the even register. */ | |
9903 | if (FP_REG_P (regno) | |
9904 | && MAX_FPRS_PER_FMT == 2 | |
9905 | && mips_cfun_might_clobber_call_saved_reg_p (regno + 1)) | |
9906 | return true; | |
9907 | } | |
9908 | ||
9909 | /* We need to save the incoming return address if __builtin_eh_return | |
9910 | is being used to set a different return address. */ | |
293593b1 | 9911 | if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) |
ab77a036 | 9912 | return true; |
e1260576 | 9913 | |
ab77a036 | 9914 | return false; |
e1260576 RS |
9915 | } |
9916 | ||
16dc5c28 | 9917 | /* Populate the current function's mips_frame_info structure. |
e1260576 | 9918 | |
ab77a036 | 9919 | MIPS stack frames look like: |
e1260576 | 9920 | |
37017f4d RS |
9921 | +-------------------------------+ |
9922 | | | | |
9923 | | incoming stack arguments | | |
9924 | | | | |
9925 | +-------------------------------+ | |
9926 | | | | |
9927 | | caller-allocated save area | | |
9928 | A | for register arguments | | |
9929 | | | | |
9930 | +-------------------------------+ <-- incoming stack pointer | |
9931 | | | | |
9932 | | callee-allocated save area | | |
9933 | B | for arguments that are | | |
9934 | | split between registers and | | |
9935 | | the stack | | |
9936 | | | | |
9937 | +-------------------------------+ <-- arg_pointer_rtx | |
9938 | | | | |
9939 | C | callee-allocated save area | | |
9940 | | for register varargs | | |
9941 | | | | |
e19da24c CF |
9942 | +-------------------------------+ <-- frame_pointer_rtx |
9943 | | | + cop0_sp_offset | |
9944 | | COP0 reg save area | + UNITS_PER_WORD | |
9945 | | | | |
9946 | +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset | |
9947 | | | + UNITS_PER_WORD | |
9948 | | accumulator save area | | |
9949 | | | | |
ba6adec4 | 9950 | +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset |
37017f4d RS |
9951 | | | + UNITS_PER_HWFPVALUE |
9952 | | FPR save area | | |
9953 | | | | |
ba6adec4 | 9954 | +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset |
37017f4d RS |
9955 | | | + UNITS_PER_WORD |
9956 | | GPR save area | | |
9957 | | | | |
ba6adec4 AN |
9958 | +-------------------------------+ <-- frame_pointer_rtx with |
9959 | | | \ -fstack-protector | |
37017f4d RS |
9960 | | local variables | | var_size |
9961 | | | / | |
9962 | +-------------------------------+ | |
9963 | | | \ | |
9964 | | $gp save area | | cprestore_size | |
9965 | | | / | |
9966 | P +-------------------------------+ <-- hard_frame_pointer_rtx for | |
ba6adec4 AN |
9967 | | | \ MIPS16 code |
9968 | | outgoing stack arguments | | | |
9969 | | | | | |
9970 | +-------------------------------+ | args_size | |
9971 | | | | | |
9972 | | caller-allocated save area | | | |
9973 | | for register arguments | | | |
9974 | | | / | |
37017f4d | 9975 | +-------------------------------+ <-- stack_pointer_rtx |
ba6adec4 AN |
9976 | frame_pointer_rtx without |
9977 | -fstack-protector | |
37017f4d RS |
9978 | hard_frame_pointer_rtx for |
9979 | non-MIPS16 code. | |
9980 | ||
9981 | At least two of A, B and C will be empty. | |
9982 | ||
9983 | Dynamic stack allocations such as alloca insert data at point P. | |
9984 | They decrease stack_pointer_rtx but leave frame_pointer_rtx and | |
9985 | hard_frame_pointer_rtx unchanged. */ | |
e1260576 | 9986 | |
16dc5c28 RS |
9987 | static void |
9988 | mips_compute_frame_info (void) | |
ab77a036 | 9989 | { |
37017f4d | 9990 | struct mips_frame_info *frame; |
16dc5c28 | 9991 | HOST_WIDE_INT offset, size; |
37017f4d | 9992 | unsigned int regno, i; |
e1260576 | 9993 | |
e19da24c CF |
9994 | /* Set this function's interrupt properties. */ |
9995 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
9996 | { | |
2b3bd040 AB |
9997 | if (mips_isa_rev < 2) |
9998 | error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater"); | |
e19da24c CF |
9999 | else if (TARGET_HARD_FLOAT) |
10000 | error ("the %<interrupt%> attribute requires %<-msoft-float%>"); | |
10001 | else if (TARGET_MIPS16) | |
10002 | error ("interrupt handlers cannot be MIPS16 functions"); | |
10003 | else | |
10004 | { | |
10005 | cfun->machine->interrupt_handler_p = true; | |
10006 | cfun->machine->use_shadow_register_set_p = | |
10007 | mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl)); | |
10008 | cfun->machine->keep_interrupts_masked_p = | |
10009 | mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl)); | |
10010 | cfun->machine->use_debug_exception_return_p = | |
10011 | mips_use_debug_exception_return_p (TREE_TYPE | |
10012 | (current_function_decl)); | |
10013 | } | |
10014 | } | |
10015 | ||
37017f4d RS |
10016 | frame = &cfun->machine->frame; |
10017 | memset (frame, 0, sizeof (*frame)); | |
16dc5c28 | 10018 | size = get_frame_size (); |
e1260576 | 10019 | |
37017f4d | 10020 | cfun->machine->global_pointer = mips_global_pointer (); |
e1260576 | 10021 | |
ba6adec4 AN |
10022 | /* The first two blocks contain the outgoing argument area and the $gp save |
10023 | slot. This area isn't needed in leaf functions, but if the | |
10024 | target-independent frame size is nonzero, we have already committed to | |
10025 | allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */ | |
416ff32e | 10026 | if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf) |
37017f4d RS |
10027 | { |
10028 | /* The MIPS 3.0 linker does not like functions that dynamically | |
10029 | allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it | |
10030 | looks like we are trying to create a second frame pointer to the | |
10031 | function, so allocate some stack space to make it happy. */ | |
e3b5732b | 10032 | if (cfun->calls_alloca) |
37017f4d RS |
10033 | frame->args_size = REG_PARM_STACK_SPACE (cfun->decl); |
10034 | else | |
10035 | frame->args_size = 0; | |
10036 | frame->cprestore_size = 0; | |
10037 | } | |
10038 | else | |
10039 | { | |
38173d38 | 10040 | frame->args_size = crtl->outgoing_args_size; |
ba6adec4 | 10041 | frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE; |
37017f4d RS |
10042 | } |
10043 | offset = frame->args_size + frame->cprestore_size; | |
e1260576 | 10044 | |
37017f4d RS |
10045 | /* Move above the local variables. */ |
10046 | frame->var_size = MIPS_STACK_ALIGN (size); | |
10047 | offset += frame->var_size; | |
e1260576 | 10048 | |
37017f4d | 10049 | /* Find out which GPRs we need to save. */ |
ab77a036 RS |
10050 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) |
10051 | if (mips_save_reg_p (regno)) | |
10052 | { | |
37017f4d RS |
10053 | frame->num_gp++; |
10054 | frame->mask |= 1 << (regno - GP_REG_FIRST); | |
ab77a036 | 10055 | } |
e1260576 | 10056 | |
37017f4d RS |
10057 | /* If this function calls eh_return, we must also save and restore the |
10058 | EH data registers. */ | |
e3b5732b | 10059 | if (crtl->calls_eh_return) |
37017f4d RS |
10060 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) |
10061 | { | |
10062 | frame->num_gp++; | |
10063 | frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); | |
10064 | } | |
e1260576 | 10065 | |
ab77a036 RS |
10066 | /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers: |
10067 | $a3-$a0 and $s2-$s8. If we save one register in the range, we must | |
10068 | save all later registers too. */ | |
10069 | if (GENERATE_MIPS16E_SAVE_RESTORE) | |
10070 | { | |
37017f4d RS |
10071 | mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs, |
10072 | ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp); | |
10073 | mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs, | |
10074 | ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp); | |
10075 | } | |
10076 | ||
10077 | /* Move above the GPR save area. */ | |
10078 | if (frame->num_gp > 0) | |
10079 | { | |
ddc4af9c | 10080 | offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD); |
37017f4d | 10081 | frame->gp_sp_offset = offset - UNITS_PER_WORD; |
ab77a036 | 10082 | } |
e1260576 | 10083 | |
37017f4d | 10084 | /* Find out which FPRs we need to save. This loop must iterate over |
e19da24c | 10085 | the same space as its companion in mips_for_each_saved_gpr_and_fpr. */ |
ab77a036 | 10086 | if (TARGET_HARD_FLOAT) |
37017f4d | 10087 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT) |
ab77a036 RS |
10088 | if (mips_save_reg_p (regno)) |
10089 | { | |
37017f4d RS |
10090 | frame->num_fp += MAX_FPRS_PER_FMT; |
10091 | frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST); | |
ab77a036 | 10092 | } |
e1260576 | 10093 | |
37017f4d RS |
10094 | /* Move above the FPR save area. */ |
10095 | if (frame->num_fp > 0) | |
e1260576 | 10096 | { |
ddc4af9c | 10097 | offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG); |
37017f4d | 10098 | frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; |
e1260576 RS |
10099 | } |
10100 | ||
e19da24c CF |
10101 | /* Add in space for the interrupt context information. */ |
10102 | if (cfun->machine->interrupt_handler_p) | |
10103 | { | |
10104 | /* Check HI/LO. */ | |
10105 | if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM)) | |
10106 | { | |
10107 | frame->num_acc++; | |
10108 | frame->acc_mask |= (1 << 0); | |
10109 | } | |
10110 | ||
10111 | /* Check accumulators 1, 2, 3. */ | |
10112 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
10113 | if (mips_save_reg_p (i) || mips_save_reg_p (i + 1)) | |
10114 | { | |
10115 | frame->num_acc++; | |
10116 | frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1); | |
10117 | } | |
10118 | ||
10119 | /* All interrupt context functions need space to preserve STATUS. */ | |
10120 | frame->num_cop0_regs++; | |
10121 | ||
10122 | /* If we don't keep interrupts masked, we need to save EPC. */ | |
10123 | if (!cfun->machine->keep_interrupts_masked_p) | |
10124 | frame->num_cop0_regs++; | |
10125 | } | |
10126 | ||
10127 | /* Move above the accumulator save area. */ | |
10128 | if (frame->num_acc > 0) | |
10129 | { | |
10130 | /* Each accumulator needs 2 words. */ | |
10131 | offset += frame->num_acc * 2 * UNITS_PER_WORD; | |
10132 | frame->acc_sp_offset = offset - UNITS_PER_WORD; | |
10133 | } | |
10134 | ||
10135 | /* Move above the COP0 register save area. */ | |
10136 | if (frame->num_cop0_regs > 0) | |
10137 | { | |
10138 | offset += frame->num_cop0_regs * UNITS_PER_WORD; | |
10139 | frame->cop0_sp_offset = offset - UNITS_PER_WORD; | |
10140 | } | |
10141 | ||
37017f4d RS |
10142 | /* Move above the callee-allocated varargs save area. */ |
10143 | offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size); | |
f374e413 | 10144 | frame->arg_pointer_offset = offset; |
e1260576 | 10145 | |
37017f4d | 10146 | /* Move above the callee-allocated area for pretend stack arguments. */ |
38173d38 | 10147 | offset += crtl->args.pretend_args_size; |
37017f4d RS |
10148 | frame->total_size = offset; |
10149 | ||
10150 | /* Work out the offsets of the save areas from the top of the frame. */ | |
10151 | if (frame->gp_sp_offset > 0) | |
10152 | frame->gp_save_offset = frame->gp_sp_offset - offset; | |
10153 | if (frame->fp_sp_offset > 0) | |
10154 | frame->fp_save_offset = frame->fp_sp_offset - offset; | |
e19da24c CF |
10155 | if (frame->acc_sp_offset > 0) |
10156 | frame->acc_save_offset = frame->acc_sp_offset - offset; | |
10157 | if (frame->num_cop0_regs > 0) | |
10158 | frame->cop0_save_offset = frame->cop0_sp_offset - offset; | |
ab77a036 | 10159 | |
f374e413 RS |
10160 | /* MIPS16 code offsets the frame pointer by the size of the outgoing |
10161 | arguments. This tends to increase the chances of using unextended | |
10162 | instructions for local variables and incoming arguments. */ | |
10163 | if (TARGET_MIPS16) | |
10164 | frame->hard_frame_pointer_offset = frame->args_size; | |
e1260576 RS |
10165 | } |
10166 | ||
ab77a036 RS |
10167 | /* Return the style of GP load sequence that is being used for the |
10168 | current function. */ | |
e1260576 | 10169 | |
ab77a036 RS |
10170 | enum mips_loadgp_style |
10171 | mips_current_loadgp_style (void) | |
e1260576 | 10172 | { |
8d9d9172 | 10173 | if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM) |
ab77a036 | 10174 | return LOADGP_NONE; |
e1260576 | 10175 | |
ab77a036 RS |
10176 | if (TARGET_RTP_PIC) |
10177 | return LOADGP_RTP; | |
e1260576 | 10178 | |
ab77a036 RS |
10179 | if (TARGET_ABSOLUTE_ABICALLS) |
10180 | return LOADGP_ABSOLUTE; | |
e1260576 | 10181 | |
ab77a036 RS |
10182 | return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; |
10183 | } | |
65239d20 | 10184 | |
b52b1749 | 10185 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
29c4d304 | 10186 | |
b52b1749 | 10187 | static bool |
29c4d304 RS |
10188 | mips_frame_pointer_required (void) |
10189 | { | |
10190 | /* If the function contains dynamic stack allocations, we need to | |
10191 | use the frame pointer to access the static parts of the frame. */ | |
e3b5732b | 10192 | if (cfun->calls_alloca) |
29c4d304 RS |
10193 | return true; |
10194 | ||
10195 | /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise, | |
10196 | reload may be unable to compute the address of a local variable, | |
10197 | since there is no way to add a large constant to the stack pointer | |
10198 | without using a second temporary register. */ | |
10199 | if (TARGET_MIPS16) | |
10200 | { | |
16dc5c28 | 10201 | mips_compute_frame_info (); |
29c4d304 RS |
10202 | if (!SMALL_OPERAND (cfun->machine->frame.total_size)) |
10203 | return true; | |
10204 | } | |
10205 | ||
10206 | return false; | |
10207 | } | |
10208 | ||
7b5cbb57 AS |
10209 | /* Make sure that we're not trying to eliminate to the wrong hard frame |
10210 | pointer. */ | |
10211 | ||
10212 | static bool | |
10213 | mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
10214 | { | |
10215 | return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); | |
10216 | } | |
10217 | ||
65239d20 RS |
10218 | /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer |
10219 | or argument pointer. TO is either the stack pointer or hard frame | |
10220 | pointer. */ | |
e1260576 | 10221 | |
ab77a036 RS |
10222 | HOST_WIDE_INT |
10223 | mips_initial_elimination_offset (int from, int to) | |
10224 | { | |
10225 | HOST_WIDE_INT offset; | |
10226 | ||
16dc5c28 | 10227 | mips_compute_frame_info (); |
ab77a036 | 10228 | |
ba6adec4 | 10229 | /* Set OFFSET to the offset from the end-of-prologue stack pointer. */ |
ab77a036 RS |
10230 | switch (from) |
10231 | { | |
10232 | case FRAME_POINTER_REGNUM: | |
ba6adec4 AN |
10233 | if (FRAME_GROWS_DOWNWARD) |
10234 | offset = (cfun->machine->frame.args_size | |
10235 | + cfun->machine->frame.cprestore_size | |
10236 | + cfun->machine->frame.var_size); | |
10237 | else | |
10238 | offset = 0; | |
ab77a036 RS |
10239 | break; |
10240 | ||
10241 | case ARG_POINTER_REGNUM: | |
f374e413 | 10242 | offset = cfun->machine->frame.arg_pointer_offset; |
ab77a036 RS |
10243 | break; |
10244 | ||
10245 | default: | |
10246 | gcc_unreachable (); | |
10247 | } | |
10248 | ||
f374e413 RS |
10249 | if (to == HARD_FRAME_POINTER_REGNUM) |
10250 | offset -= cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
10251 | |
10252 | return offset; | |
e1260576 | 10253 | } |
ab77a036 | 10254 | \f |
dbc90b65 | 10255 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */ |
e1260576 | 10256 | |
ab77a036 RS |
10257 | static void |
10258 | mips_extra_live_on_entry (bitmap regs) | |
10259 | { | |
dbc90b65 RS |
10260 | if (TARGET_USE_GOT) |
10261 | { | |
10262 | /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up | |
10263 | the global pointer. */ | |
10264 | if (!TARGET_ABSOLUTE_ABICALLS) | |
10265 | bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM); | |
10266 | ||
08d0963a RS |
10267 | /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of |
10268 | the global pointer. */ | |
10269 | if (TARGET_MIPS16) | |
10270 | bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM); | |
10271 | ||
dbc90b65 RS |
10272 | /* See the comment above load_call<mode> for details. */ |
10273 | bitmap_set_bit (regs, GOT_VERSION_REGNUM); | |
10274 | } | |
ab77a036 | 10275 | } |
e1260576 | 10276 | |
65239d20 RS |
10277 | /* Implement RETURN_ADDR_RTX. We do not support moving back to a |
10278 | previous frame. */ | |
ab77a036 RS |
10279 | |
10280 | rtx | |
10281 | mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) | |
e1260576 | 10282 | { |
ab77a036 RS |
10283 | if (count != 0) |
10284 | return const0_rtx; | |
e1260576 | 10285 | |
293593b1 | 10286 | return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); |
ab77a036 | 10287 | } |
e1260576 | 10288 | |
ab77a036 RS |
10289 | /* Emit code to change the current function's return address to |
10290 | ADDRESS. SCRATCH is available as a scratch register, if needed. | |
10291 | ADDRESS and SCRATCH are both word-mode GPRs. */ | |
e1260576 | 10292 | |
ab77a036 RS |
10293 | void |
10294 | mips_set_return_address (rtx address, rtx scratch) | |
10295 | { | |
10296 | rtx slot_address; | |
e1260576 | 10297 | |
293593b1 | 10298 | gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); |
ab77a036 RS |
10299 | slot_address = mips_add_offset (scratch, stack_pointer_rtx, |
10300 | cfun->machine->frame.gp_sp_offset); | |
8d0e1e43 | 10301 | mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); |
e1260576 | 10302 | } |
be763023 | 10303 | |
0c433c31 | 10304 | /* Return true if the current function has a cprestore slot. */ |
0fb5ac6f | 10305 | |
0c433c31 RS |
10306 | bool |
10307 | mips_cfun_has_cprestore_slot_p (void) | |
10308 | { | |
10309 | return (cfun->machine->global_pointer != INVALID_REGNUM | |
10310 | && cfun->machine->frame.cprestore_size > 0); | |
10311 | } | |
10312 | ||
10313 | /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the | |
10314 | cprestore slot. LOAD_P is true if the caller wants to load from | |
10315 | the cprestore slot; it is false if the caller wants to store to | |
10316 | the slot. */ | |
10317 | ||
10318 | static void | |
10319 | mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset, | |
10320 | bool load_p) | |
0fb5ac6f | 10321 | { |
08d0963a | 10322 | const struct mips_frame_info *frame; |
0fb5ac6f | 10323 | |
08d0963a | 10324 | frame = &cfun->machine->frame; |
0c433c31 RS |
10325 | /* .cprestore always uses the stack pointer instead of the frame pointer. |
10326 | We have a free choice for direct stores for non-MIPS16 functions, | |
10327 | and for MIPS16 functions whose cprestore slot is in range of the | |
10328 | stack pointer. Using the stack pointer would sometimes give more | |
10329 | (early) scheduling freedom, but using the frame pointer would | |
10330 | sometimes give more (late) scheduling freedom. It's hard to | |
10331 | predict which applies to a given function, so let's keep things | |
10332 | simple. | |
10333 | ||
10334 | Loads must always use the frame pointer in functions that call | |
10335 | alloca, and there's little benefit to using the stack pointer | |
10336 | otherwise. */ | |
10337 | if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p)) | |
10338 | { | |
10339 | *base = hard_frame_pointer_rtx; | |
10340 | *offset = frame->args_size - frame->hard_frame_pointer_offset; | |
08d0963a RS |
10341 | } |
10342 | else | |
10343 | { | |
0c433c31 RS |
10344 | *base = stack_pointer_rtx; |
10345 | *offset = frame->args_size; | |
08d0963a | 10346 | } |
0c433c31 RS |
10347 | } |
10348 | ||
10349 | /* Return true if X is the load or store address of the cprestore slot; | |
10350 | LOAD_P says which. */ | |
10351 | ||
10352 | bool | |
10353 | mips_cprestore_address_p (rtx x, bool load_p) | |
10354 | { | |
10355 | rtx given_base, required_base; | |
10356 | HOST_WIDE_INT given_offset, required_offset; | |
10357 | ||
10358 | mips_split_plus (x, &given_base, &given_offset); | |
10359 | mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p); | |
10360 | return given_base == required_base && given_offset == required_offset; | |
10361 | } | |
10362 | ||
10363 | /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are | |
10364 | going to load from it, false if we are going to store to it. | |
10365 | Use TEMP as a temporary register if need be. */ | |
10366 | ||
10367 | static rtx | |
10368 | mips_cprestore_slot (rtx temp, bool load_p) | |
10369 | { | |
10370 | rtx base; | |
10371 | HOST_WIDE_INT offset; | |
10372 | ||
10373 | mips_get_cprestore_base_and_offset (&base, &offset, load_p); | |
08d0963a RS |
10374 | return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset)); |
10375 | } | |
10376 | ||
0c433c31 RS |
10377 | /* Emit instructions to save global pointer value GP into cprestore |
10378 | slot MEM. OFFSET is the offset that MEM applies to the base register. | |
10379 | ||
10380 | MEM may not be a legitimate address. If it isn't, TEMP is a | |
10381 | temporary register that can be used, otherwise it is a SCRATCH. */ | |
10382 | ||
10383 | void | |
10384 | mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp) | |
10385 | { | |
10386 | if (TARGET_CPRESTORE_DIRECTIVE) | |
10387 | { | |
10388 | gcc_assert (gp == pic_offset_table_rtx); | |
81a478c8 | 10389 | emit_insn (PMODE_INSN (gen_cprestore, (mem, offset))); |
0c433c31 RS |
10390 | } |
10391 | else | |
10392 | mips_emit_move (mips_cprestore_slot (temp, false), gp); | |
10393 | } | |
10394 | ||
08d0963a | 10395 | /* Restore $gp from its save slot, using TEMP as a temporary base register |
0c433c31 RS |
10396 | if need be. This function is for o32 and o64 abicalls only. |
10397 | ||
10398 | See mips_must_initialize_gp_p for details about how we manage the | |
10399 | global pointer. */ | |
08d0963a RS |
10400 | |
10401 | void | |
0c433c31 | 10402 | mips_restore_gp_from_cprestore_slot (rtx temp) |
08d0963a | 10403 | { |
0c433c31 | 10404 | gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed); |
f833ffd4 | 10405 | |
0c433c31 | 10406 | if (!cfun->machine->must_restore_gp_when_clobbered_p) |
c870c233 RS |
10407 | { |
10408 | emit_note (NOTE_INSN_DELETED); | |
10409 | return; | |
10410 | } | |
e21d5757 | 10411 | |
08d0963a RS |
10412 | if (TARGET_MIPS16) |
10413 | { | |
0c433c31 | 10414 | mips_emit_move (temp, mips_cprestore_slot (temp, true)); |
08d0963a RS |
10415 | mips_emit_move (pic_offset_table_rtx, temp); |
10416 | } | |
10417 | else | |
0c433c31 | 10418 | mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true)); |
ab77a036 RS |
10419 | if (!TARGET_EXPLICIT_RELOCS) |
10420 | emit_insn (gen_blockage ()); | |
10421 | } | |
10422 | \f | |
10423 | /* A function to save or store a register. The first argument is the | |
10424 | register and the second is the stack slot. */ | |
10425 | typedef void (*mips_save_restore_fn) (rtx, rtx); | |
cee98a59 | 10426 | |
ab77a036 RS |
10427 | /* Use FN to save or restore register REGNO. MODE is the register's |
10428 | mode and OFFSET is the offset of its save slot from the current | |
10429 | stack pointer. */ | |
e1260576 | 10430 | |
ab77a036 | 10431 | static void |
ef4bddc2 | 10432 | mips_save_restore_reg (machine_mode mode, int regno, |
ab77a036 RS |
10433 | HOST_WIDE_INT offset, mips_save_restore_fn fn) |
10434 | { | |
10435 | rtx mem; | |
e1260576 | 10436 | |
0a81f074 RS |
10437 | mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, |
10438 | offset)); | |
ab77a036 RS |
10439 | fn (gen_rtx_REG (mode, regno), mem); |
10440 | } | |
e1260576 | 10441 | |
e19da24c CF |
10442 | /* Call FN for each accumlator that is saved by the current function. |
10443 | SP_OFFSET is the offset of the current stack pointer from the start | |
10444 | of the frame. */ | |
10445 | ||
10446 | static void | |
10447 | mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn) | |
10448 | { | |
10449 | HOST_WIDE_INT offset; | |
10450 | int regno; | |
10451 | ||
10452 | offset = cfun->machine->frame.acc_sp_offset - sp_offset; | |
10453 | if (BITSET_P (cfun->machine->frame.acc_mask, 0)) | |
10454 | { | |
10455 | mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn); | |
10456 | offset -= UNITS_PER_WORD; | |
10457 | mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn); | |
10458 | offset -= UNITS_PER_WORD; | |
10459 | } | |
10460 | ||
10461 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) | |
10462 | if (BITSET_P (cfun->machine->frame.acc_mask, | |
10463 | ((regno - DSP_ACC_REG_FIRST) / 2) + 1)) | |
10464 | { | |
10465 | mips_save_restore_reg (word_mode, regno, offset, fn); | |
10466 | offset -= UNITS_PER_WORD; | |
10467 | } | |
10468 | } | |
10469 | ||
22c4c869 CM |
10470 | /* Save register REG to MEM. Make the instruction frame-related. */ |
10471 | ||
10472 | static void | |
10473 | mips_save_reg (rtx reg, rtx mem) | |
10474 | { | |
10475 | if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) | |
10476 | { | |
10477 | rtx x1, x2; | |
10478 | ||
10479 | mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY); | |
10480 | ||
10481 | x1 = mips_frame_set (mips_subword (mem, false), | |
10482 | mips_subword (reg, false)); | |
10483 | x2 = mips_frame_set (mips_subword (mem, true), | |
10484 | mips_subword (reg, true)); | |
10485 | mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2))); | |
10486 | } | |
10487 | else | |
10488 | mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg))); | |
10489 | } | |
10490 | ||
10491 | /* Capture the register combinations that are allowed in a SWM or LWM | |
10492 | instruction. The entries are ordered by number of registers set in | |
10493 | the mask. We also ignore the single register encodings because a | |
10494 | normal SW/LW is preferred. */ | |
10495 | ||
10496 | static const unsigned int umips_swm_mask[17] = { | |
10497 | 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000, | |
10498 | 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000, | |
10499 | 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000, | |
10500 | 0x000f0000, 0x80030000, 0x00070000, 0x80010000, | |
10501 | 0x00030000 | |
10502 | }; | |
10503 | ||
10504 | static const unsigned int umips_swm_encoding[17] = { | |
10505 | 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2 | |
10506 | }; | |
10507 | ||
10508 | /* Try to use a microMIPS LWM or SWM instruction to save or restore | |
10509 | as many GPRs in *MASK as possible. *OFFSET is the offset from the | |
10510 | stack pointer of the topmost save slot. | |
10511 | ||
10512 | Remove from *MASK all registers that were handled using LWM and SWM. | |
10513 | Update *OFFSET so that it points to the first unused save slot. */ | |
10514 | ||
10515 | static bool | |
10516 | umips_build_save_restore (mips_save_restore_fn fn, | |
10517 | unsigned *mask, HOST_WIDE_INT *offset) | |
10518 | { | |
10519 | int nregs; | |
10520 | unsigned int i, j; | |
10521 | rtx pattern, set, reg, mem; | |
10522 | HOST_WIDE_INT this_offset; | |
10523 | rtx this_base; | |
10524 | ||
10525 | /* Try matching $16 to $31 (s0 to ra). */ | |
10526 | for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++) | |
10527 | if ((*mask & 0xffff0000) == umips_swm_mask[i]) | |
10528 | break; | |
10529 | ||
10530 | if (i == ARRAY_SIZE (umips_swm_mask)) | |
10531 | return false; | |
10532 | ||
10533 | /* Get the offset of the lowest save slot. */ | |
10534 | nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4); | |
10535 | this_offset = *offset - UNITS_PER_WORD * (nregs - 1); | |
10536 | ||
10537 | /* LWM/SWM can only support offsets from -2048 to 2047. */ | |
10538 | if (!UMIPS_12BIT_OFFSET_P (this_offset)) | |
10539 | return false; | |
10540 | ||
10541 | /* Create the final PARALLEL. */ | |
10542 | pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); | |
10543 | this_base = stack_pointer_rtx; | |
10544 | ||
10545 | /* For registers $16-$23 and $30. */ | |
10546 | for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++) | |
10547 | { | |
10548 | HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD; | |
10549 | mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset)); | |
10550 | unsigned int regno = (j != 8) ? 16 + j : 30; | |
10551 | *mask &= ~(1 << regno); | |
10552 | reg = gen_rtx_REG (SImode, regno); | |
10553 | if (fn == mips_save_reg) | |
10554 | set = mips_frame_set (mem, reg); | |
10555 | else | |
10556 | { | |
10557 | set = gen_rtx_SET (VOIDmode, reg, mem); | |
10558 | mips_add_cfa_restore (reg); | |
10559 | } | |
10560 | XVECEXP (pattern, 0, j) = set; | |
10561 | } | |
10562 | ||
10563 | /* For register $31. */ | |
10564 | if (umips_swm_encoding[i] >> 4) | |
10565 | { | |
10566 | HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD; | |
10567 | *mask &= ~(1 << 31); | |
10568 | mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset)); | |
10569 | reg = gen_rtx_REG (SImode, 31); | |
10570 | if (fn == mips_save_reg) | |
10571 | set = mips_frame_set (mem, reg); | |
10572 | else | |
10573 | { | |
10574 | set = gen_rtx_SET (VOIDmode, reg, mem); | |
10575 | mips_add_cfa_restore (reg); | |
10576 | } | |
10577 | XVECEXP (pattern, 0, j) = set; | |
10578 | } | |
10579 | ||
10580 | pattern = emit_insn (pattern); | |
10581 | if (fn == mips_save_reg) | |
10582 | RTX_FRAME_RELATED_P (pattern) = 1; | |
10583 | ||
10584 | /* Adjust the last offset. */ | |
10585 | *offset -= UNITS_PER_WORD * nregs; | |
10586 | ||
10587 | return true; | |
10588 | } | |
10589 | ||
ab77a036 RS |
10590 | /* Call FN for each register that is saved by the current function. |
10591 | SP_OFFSET is the offset of the current stack pointer from the start | |
10592 | of the frame. */ | |
a94dbf2c | 10593 | |
ab77a036 | 10594 | static void |
e19da24c CF |
10595 | mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, |
10596 | mips_save_restore_fn fn) | |
ab77a036 | 10597 | { |
ef4bddc2 | 10598 | machine_mode fpr_mode; |
6d65e8f1 | 10599 | int regno; |
22c4c869 CM |
10600 | const struct mips_frame_info *frame = &cfun->machine->frame; |
10601 | HOST_WIDE_INT offset; | |
10602 | unsigned int mask; | |
2bcb2ab3 | 10603 | |
ab77a036 RS |
10604 | /* Save registers starting from high to low. The debuggers prefer at least |
10605 | the return register be stored at func+4, and also it allows us not to | |
10606 | need a nop in the epilogue if at least one register is reloaded in | |
10607 | addition to return address. */ | |
22c4c869 CM |
10608 | offset = frame->gp_sp_offset - sp_offset; |
10609 | mask = frame->mask; | |
10610 | ||
10611 | if (TARGET_MICROMIPS) | |
10612 | umips_build_save_restore (fn, &mask, &offset); | |
10613 | ||
ab77a036 | 10614 | for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) |
22c4c869 | 10615 | if (BITSET_P (mask, regno - GP_REG_FIRST)) |
ab77a036 | 10616 | { |
c376dbfb DD |
10617 | /* Record the ra offset for use by mips_function_profiler. */ |
10618 | if (regno == RETURN_ADDR_REGNUM) | |
10619 | cfun->machine->frame.ra_fp_offset = offset + sp_offset; | |
6e75e6e3 RS |
10620 | mips_save_restore_reg (word_mode, regno, offset, fn); |
10621 | offset -= UNITS_PER_WORD; | |
ab77a036 RS |
10622 | } |
10623 | ||
10624 | /* This loop must iterate over the same space as its companion in | |
16dc5c28 | 10625 | mips_compute_frame_info. */ |
ab77a036 RS |
10626 | offset = cfun->machine->frame.fp_sp_offset - sp_offset; |
10627 | fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); | |
65239d20 | 10628 | for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; |
ab77a036 RS |
10629 | regno >= FP_REG_FIRST; |
10630 | regno -= MAX_FPRS_PER_FMT) | |
10631 | if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) | |
10632 | { | |
10633 | mips_save_restore_reg (fpr_mode, regno, offset, fn); | |
10634 | offset -= GET_MODE_SIZE (fpr_mode); | |
10635 | } | |
10636 | } | |
0c433c31 RS |
10637 | |
10638 | /* Return true if a move between register REGNO and its save slot (MEM) | |
10639 | can be done in a single move. LOAD_P is true if we are loading | |
10640 | from the slot, false if we are storing to it. */ | |
10641 | ||
10642 | static bool | |
10643 | mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p) | |
10644 | { | |
10645 | /* There is a specific MIPS16 instruction for saving $31 to the stack. */ | |
293593b1 | 10646 | if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM) |
0c433c31 RS |
10647 | return false; |
10648 | ||
10649 | return mips_secondary_reload_class (REGNO_REG_CLASS (regno), | |
10650 | GET_MODE (mem), mem, load_p) == NO_REGS; | |
10651 | } | |
10652 | ||
10653 | /* Emit a move from SRC to DEST, given that one of them is a register | |
10654 | save slot and that the other is a register. TEMP is a temporary | |
10655 | GPR of the same mode that is available if need be. */ | |
10656 | ||
10657 | void | |
10658 | mips_emit_save_slot_move (rtx dest, rtx src, rtx temp) | |
10659 | { | |
10660 | unsigned int regno; | |
10661 | rtx mem; | |
10662 | ||
10663 | if (REG_P (src)) | |
10664 | { | |
10665 | regno = REGNO (src); | |
10666 | mem = dest; | |
10667 | } | |
10668 | else | |
10669 | { | |
10670 | regno = REGNO (dest); | |
10671 | mem = src; | |
10672 | } | |
10673 | ||
10674 | if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ()) | |
10675 | { | |
10676 | /* We don't yet know whether we'll need this instruction or not. | |
10677 | Postpone the decision by emitting a ghost move. This move | |
10678 | is specifically not frame-related; only the split version is. */ | |
10679 | if (TARGET_64BIT) | |
10680 | emit_insn (gen_move_gpdi (dest, src)); | |
10681 | else | |
10682 | emit_insn (gen_move_gpsi (dest, src)); | |
10683 | return; | |
10684 | } | |
10685 | ||
10686 | if (regno == HI_REGNUM) | |
10687 | { | |
10688 | if (REG_P (dest)) | |
10689 | { | |
10690 | mips_emit_move (temp, src); | |
10691 | if (TARGET_64BIT) | |
10692 | emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST), | |
10693 | temp, gen_rtx_REG (DImode, LO_REGNUM))); | |
10694 | else | |
10695 | emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST), | |
10696 | temp, gen_rtx_REG (SImode, LO_REGNUM))); | |
10697 | } | |
10698 | else | |
10699 | { | |
10700 | if (TARGET_64BIT) | |
10701 | emit_insn (gen_mfhidi_ti (temp, | |
10702 | gen_rtx_REG (TImode, MD_REG_FIRST))); | |
10703 | else | |
10704 | emit_insn (gen_mfhisi_di (temp, | |
10705 | gen_rtx_REG (DImode, MD_REG_FIRST))); | |
10706 | mips_emit_move (dest, temp); | |
10707 | } | |
10708 | } | |
10709 | else if (mips_direct_save_slot_move_p (regno, mem, mem == src)) | |
10710 | mips_emit_move (dest, src); | |
10711 | else | |
10712 | { | |
10713 | gcc_assert (!reg_overlap_mentioned_p (dest, temp)); | |
10714 | mips_emit_move (temp, src); | |
10715 | mips_emit_move (dest, temp); | |
10716 | } | |
10717 | if (MEM_P (dest)) | |
10718 | mips_set_frame_expr (mips_frame_set (dest, src)); | |
10719 | } | |
ab77a036 RS |
10720 | \f |
10721 | /* If we're generating n32 or n64 abicalls, and the current function | |
10722 | does not use $28 as its global pointer, emit a cplocal directive. | |
10723 | Use pic_offset_table_rtx as the argument to the directive. */ | |
10724 | ||
10725 | static void | |
10726 | mips_output_cplocal (void) | |
10727 | { | |
10728 | if (!TARGET_EXPLICIT_RELOCS | |
0c433c31 | 10729 | && mips_must_initialize_gp_p () |
ab77a036 RS |
10730 | && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM) |
10731 | output_asm_insn (".cplocal %+", 0); | |
10732 | } | |
10733 | ||
65239d20 | 10734 | /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */ |
ab77a036 RS |
10735 | |
10736 | static void | |
10737 | mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
10738 | { | |
10739 | const char *fnname; | |
ab77a036 | 10740 | |
65239d20 RS |
10741 | /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle |
10742 | floating-point arguments. */ | |
ab77a036 RS |
10743 | if (TARGET_MIPS16 |
10744 | && TARGET_HARD_FLOAT_ABI | |
38173d38 | 10745 | && crtl->args.info.fp_code != 0) |
65239d20 | 10746 | mips16_build_function_stub (); |
ab77a036 | 10747 | |
b2b61607 RS |
10748 | /* Get the function name the same way that toplev.c does before calling |
10749 | assemble_start_function. This is needed so that the name used here | |
10750 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
10751 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
10752 | mips_start_function_definition (fnname, TARGET_MIPS16); | |
f833ffd4 | 10753 | |
65239d20 | 10754 | /* Output MIPS-specific frame information. */ |
ab77a036 RS |
10755 | if (!flag_inhibit_size_directive) |
10756 | { | |
65239d20 RS |
10757 | const struct mips_frame_info *frame; |
10758 | ||
10759 | frame = &cfun->machine->frame; | |
10760 | ||
10761 | /* .frame FRAMEREG, FRAMESIZE, RETREG. */ | |
ab77a036 RS |
10762 | fprintf (file, |
10763 | "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t" | |
65239d20 RS |
10764 | "# vars= " HOST_WIDE_INT_PRINT_DEC |
10765 | ", regs= %d/%d" | |
ab77a036 RS |
10766 | ", args= " HOST_WIDE_INT_PRINT_DEC |
10767 | ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", | |
65239d20 RS |
10768 | reg_names[frame_pointer_needed |
10769 | ? HARD_FRAME_POINTER_REGNUM | |
10770 | : STACK_POINTER_REGNUM], | |
f374e413 | 10771 | (frame_pointer_needed |
65239d20 RS |
10772 | ? frame->total_size - frame->hard_frame_pointer_offset |
10773 | : frame->total_size), | |
293593b1 | 10774 | reg_names[RETURN_ADDR_REGNUM], |
65239d20 RS |
10775 | frame->var_size, |
10776 | frame->num_gp, frame->num_fp, | |
10777 | frame->args_size, | |
10778 | frame->cprestore_size); | |
be763023 | 10779 | |
65239d20 | 10780 | /* .mask MASK, OFFSET. */ |
ab77a036 | 10781 | fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", |
65239d20 | 10782 | frame->mask, frame->gp_save_offset); |
d8d5b1e1 | 10783 | |
65239d20 RS |
10784 | /* .fmask MASK, OFFSET. */ |
10785 | fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", | |
10786 | frame->fmask, frame->fp_save_offset); | |
ab77a036 RS |
10787 | } |
10788 | ||
65239d20 RS |
10789 | /* Handle the initialization of $gp for SVR4 PIC, if applicable. |
10790 | Also emit the ".set noreorder; .set nomacro" sequence for functions | |
10791 | that need it. */ | |
0c433c31 RS |
10792 | if (mips_must_initialize_gp_p () |
10793 | && mips_current_loadgp_style () == LOADGP_OLDABI) | |
ab77a036 | 10794 | { |
08d0963a RS |
10795 | if (TARGET_MIPS16) |
10796 | { | |
10797 | /* This is a fixed-form sequence. The position of the | |
10798 | first two instructions is important because of the | |
10799 | way _gp_disp is defined. */ | |
10800 | output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); | |
10801 | output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); | |
10802 | output_asm_insn ("sll\t$2,16", 0); | |
10803 | output_asm_insn ("addu\t$2,$3", 0); | |
10804 | } | |
ab77a036 | 10805 | else |
cf5fb4b0 RS |
10806 | { |
10807 | /* .cpload must be in a .set noreorder but not a | |
10808 | .set nomacro block. */ | |
10809 | mips_push_asm_switch (&mips_noreorder); | |
10810 | output_asm_insn (".cpload\t%^", 0); | |
10811 | if (!cfun->machine->all_noreorder_p) | |
10812 | mips_pop_asm_switch (&mips_noreorder); | |
10813 | else | |
10814 | mips_push_asm_switch (&mips_nomacro); | |
10815 | } | |
ab77a036 RS |
10816 | } |
10817 | else if (cfun->machine->all_noreorder_p) | |
cf5fb4b0 RS |
10818 | { |
10819 | mips_push_asm_switch (&mips_noreorder); | |
10820 | mips_push_asm_switch (&mips_nomacro); | |
10821 | } | |
ab77a036 RS |
10822 | |
10823 | /* Tell the assembler which register we're using as the global | |
10824 | pointer. This is needed for thunks, since they can use either | |
10825 | explicit relocs or assembler macros. */ | |
10826 | mips_output_cplocal (); | |
cee98a59 | 10827 | } |
ab77a036 | 10828 | |
65239d20 | 10829 | /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */ |
b5e9dd03 | 10830 | |
08c148a8 | 10831 | static void |
b4966b1b RS |
10832 | mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
10833 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
cee98a59 | 10834 | { |
b2b61607 RS |
10835 | const char *fnname; |
10836 | ||
b85aed9e | 10837 | /* Reinstate the normal $gp. */ |
6fb5fa3c | 10838 | SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM); |
b85aed9e RS |
10839 | mips_output_cplocal (); |
10840 | ||
6f2993e5 RS |
10841 | if (cfun->machine->all_noreorder_p) |
10842 | { | |
cf5fb4b0 RS |
10843 | mips_pop_asm_switch (&mips_nomacro); |
10844 | mips_pop_asm_switch (&mips_noreorder); | |
6f2993e5 RS |
10845 | } |
10846 | ||
b2b61607 RS |
10847 | /* Get the function name the same way that toplev.c does before calling |
10848 | assemble_start_function. This is needed so that the name used here | |
10849 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
10850 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
10851 | mips_end_function_definition (fnname); | |
cee98a59 | 10852 | } |
0fb5ac6f | 10853 | \f |
d9b59f56 RS |
10854 | /* Emit an optimisation barrier for accesses to the current frame. */ |
10855 | ||
10856 | static void | |
10857 | mips_frame_barrier (void) | |
10858 | { | |
10859 | emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx)); | |
10860 | } | |
10861 | ||
be763023 | 10862 | |
ab77a036 | 10863 | /* The __gnu_local_gp symbol. */ |
be763023 | 10864 | |
ab77a036 | 10865 | static GTY(()) rtx mips_gnu_local_gp; |
0fb5ac6f | 10866 | |
ab77a036 RS |
10867 | /* If we're generating n32 or n64 abicalls, emit instructions |
10868 | to set up the global pointer. */ | |
0fb5ac6f | 10869 | |
ab77a036 RS |
10870 | static void |
10871 | mips_emit_loadgp (void) | |
10872 | { | |
5557aad2 | 10873 | rtx addr, offset, incoming_address, base, index, pic_reg; |
d33289b2 | 10874 | |
08d0963a | 10875 | pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; |
ab77a036 | 10876 | switch (mips_current_loadgp_style ()) |
a38e0142 | 10877 | { |
ab77a036 RS |
10878 | case LOADGP_ABSOLUTE: |
10879 | if (mips_gnu_local_gp == NULL) | |
10880 | { | |
10881 | mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); | |
10882 | SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; | |
10883 | } | |
81a478c8 RS |
10884 | emit_insn (PMODE_INSN (gen_loadgp_absolute, |
10885 | (pic_reg, mips_gnu_local_gp))); | |
ab77a036 | 10886 | break; |
a38e0142 | 10887 | |
08d0963a RS |
10888 | case LOADGP_OLDABI: |
10889 | /* Added by mips_output_function_prologue. */ | |
10890 | break; | |
10891 | ||
ab77a036 RS |
10892 | case LOADGP_NEWABI: |
10893 | addr = XEXP (DECL_RTL (current_function_decl), 0); | |
10894 | offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP); | |
10895 | incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
81a478c8 RS |
10896 | emit_insn (PMODE_INSN (gen_loadgp_newabi, |
10897 | (pic_reg, offset, incoming_address))); | |
ab77a036 | 10898 | break; |
a38e0142 | 10899 | |
ab77a036 RS |
10900 | case LOADGP_RTP: |
10901 | base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE)); | |
10902 | index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX)); | |
81a478c8 | 10903 | emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index))); |
ab77a036 RS |
10904 | break; |
10905 | ||
10906 | default: | |
de9f679d | 10907 | return; |
ab77a036 | 10908 | } |
08d0963a RS |
10909 | |
10910 | if (TARGET_MIPS16) | |
81a478c8 RS |
10911 | emit_insn (PMODE_INSN (gen_copygp_mips16, |
10912 | (pic_offset_table_rtx, pic_reg))); | |
08d0963a | 10913 | |
de9f679d RS |
10914 | /* Emit a blockage if there are implicit uses of the GP register. |
10915 | This includes profiled functions, because FUNCTION_PROFILE uses | |
10916 | a jal macro. */ | |
10917 | if (!TARGET_EXPLICIT_RELOCS || crtl->profile) | |
10918 | emit_insn (gen_loadgp_blockage ()); | |
ab77a036 RS |
10919 | } |
10920 | ||
3b601ca3 EB |
10921 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) |
10922 | ||
10923 | #if PROBE_INTERVAL > 32768 | |
10924 | #error Cannot use indexed addressing mode for stack probing | |
10925 | #endif | |
10926 | ||
10927 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
10928 | inclusive. These are offsets from the current stack pointer. */ | |
10929 | ||
10930 | static void | |
10931 | mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) | |
10932 | { | |
10933 | if (TARGET_MIPS16) | |
10934 | sorry ("-fstack-check=specific not implemented for MIPS16"); | |
10935 | ||
10936 | /* See if we have a constant small number of probes to generate. If so, | |
10937 | that's the easy case. */ | |
10938 | if (first + size <= 32768) | |
10939 | { | |
10940 | HOST_WIDE_INT i; | |
10941 | ||
10942 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until | |
10943 | it exceeds SIZE. If only one probe is needed, this will not | |
10944 | generate any code. Then probe at FIRST + SIZE. */ | |
10945 | for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
10946 | emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, | |
10947 | -(first + i))); | |
10948 | ||
10949 | emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, | |
10950 | -(first + size))); | |
10951 | } | |
10952 | ||
10953 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
10954 | extra careful with variables wrapping around because we might be at | |
10955 | the very top (or the very bottom) of the address space and we have | |
10956 | to be able to handle this case properly; in particular, we use an | |
10957 | equality test for the loop condition. */ | |
10958 | else | |
10959 | { | |
10960 | HOST_WIDE_INT rounded_size; | |
10961 | rtx r3 = MIPS_PROLOGUE_TEMP (Pmode); | |
10962 | rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode); | |
10963 | ||
10964 | /* Sanity check for the addressing mode we're going to use. */ | |
10965 | gcc_assert (first <= 32768); | |
10966 | ||
10967 | ||
10968 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
10969 | ||
10970 | rounded_size = size & -PROBE_INTERVAL; | |
10971 | ||
10972 | ||
10973 | /* Step 2: compute initial and final value of the loop counter. */ | |
10974 | ||
10975 | /* TEST_ADDR = SP + FIRST. */ | |
10976 | emit_insn (gen_rtx_SET (VOIDmode, r3, | |
10977 | plus_constant (Pmode, stack_pointer_rtx, | |
10978 | -first))); | |
10979 | ||
10980 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
10981 | if (rounded_size > 32768) | |
10982 | { | |
10983 | emit_move_insn (r12, GEN_INT (rounded_size)); | |
10984 | emit_insn (gen_rtx_SET (VOIDmode, r12, | |
10985 | gen_rtx_MINUS (Pmode, r3, r12))); | |
10986 | } | |
10987 | else | |
10988 | emit_insn (gen_rtx_SET (VOIDmode, r12, | |
10989 | plus_constant (Pmode, r3, -rounded_size))); | |
10990 | ||
10991 | ||
10992 | /* Step 3: the loop | |
10993 | ||
10994 | while (TEST_ADDR != LAST_ADDR) | |
10995 | { | |
10996 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
10997 | probe at TEST_ADDR | |
10998 | } | |
10999 | ||
11000 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
11001 | until it is equal to ROUNDED_SIZE. */ | |
11002 | ||
11003 | emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12))); | |
11004 | ||
11005 | ||
11006 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
11007 | that SIZE is equal to ROUNDED_SIZE. */ | |
11008 | ||
11009 | if (size != rounded_size) | |
11010 | emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size)); | |
11011 | } | |
11012 | ||
11013 | /* Make sure nothing is scheduled before we are done. */ | |
11014 | emit_insn (gen_blockage ()); | |
11015 | } | |
11016 | ||
11017 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
11018 | absolute addresses. */ | |
11019 | ||
11020 | const char * | |
11021 | mips_output_probe_stack_range (rtx reg1, rtx reg2) | |
11022 | { | |
11023 | static int labelno = 0; | |
11024 | char loop_lab[32], end_lab[32], tmp[64]; | |
11025 | rtx xops[2]; | |
11026 | ||
11027 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno); | |
11028 | ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++); | |
11029 | ||
11030 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); | |
11031 | ||
11032 | /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */ | |
11033 | xops[0] = reg1; | |
11034 | xops[1] = reg2; | |
11035 | strcpy (tmp, "%(%<beq\t%0,%1,"); | |
11036 | output_asm_insn (strcat (tmp, &end_lab[1]), xops); | |
11037 | ||
11038 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ | |
11039 | xops[1] = GEN_INT (-PROBE_INTERVAL); | |
11040 | if (TARGET_64BIT && TARGET_LONG64) | |
11041 | output_asm_insn ("daddiu\t%0,%0,%1", xops); | |
11042 | else | |
11043 | output_asm_insn ("addiu\t%0,%0,%1", xops); | |
11044 | ||
11045 | /* Probe at TEST_ADDR and branch. */ | |
11046 | fprintf (asm_out_file, "\tb\t"); | |
11047 | assemble_name_raw (asm_out_file, loop_lab); | |
11048 | fputc ('\n', asm_out_file); | |
11049 | if (TARGET_64BIT) | |
11050 | output_asm_insn ("sd\t$0,0(%0)%)", xops); | |
11051 | else | |
11052 | output_asm_insn ("sw\t$0,0(%0)%)", xops); | |
11053 | ||
11054 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab); | |
11055 | ||
11056 | return ""; | |
11057 | } | |
11058 | ||
eacbf7bd | 11059 | /* Return true if X contains a kernel register. */ |
e19da24c | 11060 | |
eacbf7bd RS |
11061 | static bool |
11062 | mips_refers_to_kernel_reg_p (const_rtx x) | |
e19da24c | 11063 | { |
eacbf7bd RS |
11064 | subrtx_iterator::array_type array; |
11065 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
11066 | if (REG_P (*iter) && KERNEL_REG_P (REGNO (*iter))) | |
11067 | return true; | |
11068 | return false; | |
e19da24c CF |
11069 | } |
11070 | ||
65239d20 | 11071 | /* Expand the "prologue" pattern. */ |
ab77a036 RS |
11072 | |
11073 | void | |
11074 | mips_expand_prologue (void) | |
11075 | { | |
65239d20 | 11076 | const struct mips_frame_info *frame; |
ab77a036 RS |
11077 | HOST_WIDE_INT size; |
11078 | unsigned int nargs; | |
ab77a036 | 11079 | |
8d9d9172 | 11080 | if (cfun->machine->global_pointer != INVALID_REGNUM) |
0c433c31 RS |
11081 | { |
11082 | /* Check whether an insn uses pic_offset_table_rtx, either explicitly | |
11083 | or implicitly. If so, we can commit to using a global pointer | |
11084 | straight away, otherwise we need to defer the decision. */ | |
11085 | if (mips_cfun_has_inflexible_gp_ref_p () | |
11086 | || mips_cfun_has_flexible_gp_ref_p ()) | |
11087 | { | |
11088 | cfun->machine->must_initialize_gp_p = true; | |
11089 | cfun->machine->must_restore_gp_when_clobbered_p = true; | |
11090 | } | |
11091 | ||
11092 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); | |
11093 | } | |
ab77a036 | 11094 | |
65239d20 RS |
11095 | frame = &cfun->machine->frame; |
11096 | size = frame->total_size; | |
ab77a036 | 11097 | |
a11e0df4 | 11098 | if (flag_stack_usage_info) |
d3c12306 EB |
11099 | current_function_static_stack_size = size; |
11100 | ||
0dca9cd8 EB |
11101 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) |
11102 | { | |
11103 | if (crtl->is_leaf && !cfun->calls_alloca) | |
11104 | { | |
11105 | if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) | |
11106 | mips_emit_probe_stack_range (STACK_CHECK_PROTECT, | |
11107 | size - STACK_CHECK_PROTECT); | |
11108 | } | |
11109 | else if (size > 0) | |
11110 | mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size); | |
11111 | } | |
3b601ca3 | 11112 | |
ab77a036 RS |
11113 | /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP |
11114 | bytes beforehand; this is enough to cover the register save area | |
11115 | without going out of range. */ | |
e19da24c CF |
11116 | if (((frame->mask | frame->fmask | frame->acc_mask) != 0) |
11117 | || frame->num_cop0_regs > 0) | |
ab77a036 RS |
11118 | { |
11119 | HOST_WIDE_INT step1; | |
11120 | ||
11121 | step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); | |
ab77a036 RS |
11122 | if (GENERATE_MIPS16E_SAVE_RESTORE) |
11123 | { | |
11124 | HOST_WIDE_INT offset; | |
11125 | unsigned int mask, regno; | |
11126 | ||
11127 | /* Try to merge argument stores into the save instruction. */ | |
11128 | nargs = mips16e_collect_argument_saves (); | |
11129 | ||
11130 | /* Build the save instruction. */ | |
65239d20 | 11131 | mask = frame->mask; |
b32d5189 DM |
11132 | rtx insn = mips16e_build_save_restore (false, &mask, &offset, |
11133 | nargs, step1); | |
ab77a036 | 11134 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; |
d9b59f56 | 11135 | mips_frame_barrier (); |
ab77a036 RS |
11136 | size -= step1; |
11137 | ||
11138 | /* Check if we need to save other registers. */ | |
11139 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
11140 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
11141 | { | |
6e75e6e3 RS |
11142 | offset -= UNITS_PER_WORD; |
11143 | mips_save_restore_reg (word_mode, regno, | |
11144 | offset, mips_save_reg); | |
ab77a036 RS |
11145 | } |
11146 | } | |
11147 | else | |
11148 | { | |
e19da24c CF |
11149 | if (cfun->machine->interrupt_handler_p) |
11150 | { | |
11151 | HOST_WIDE_INT offset; | |
11152 | rtx mem; | |
11153 | ||
11154 | /* If this interrupt is using a shadow register set, we need to | |
11155 | get the stack pointer from the previous register set. */ | |
11156 | if (cfun->machine->use_shadow_register_set_p) | |
11157 | emit_insn (gen_mips_rdpgpr (stack_pointer_rtx, | |
11158 | stack_pointer_rtx)); | |
11159 | ||
11160 | if (!cfun->machine->keep_interrupts_masked_p) | |
11161 | { | |
11162 | /* Move from COP0 Cause to K0. */ | |
11163 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM), | |
11164 | gen_rtx_REG (SImode, | |
11165 | COP0_CAUSE_REG_NUM))); | |
11166 | /* Move from COP0 EPC to K1. */ | |
11167 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
11168 | gen_rtx_REG (SImode, | |
11169 | COP0_EPC_REG_NUM))); | |
11170 | } | |
11171 | ||
11172 | /* Allocate the first part of the frame. */ | |
b32d5189 DM |
11173 | rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, |
11174 | GEN_INT (-step1)); | |
e19da24c | 11175 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; |
d9b59f56 | 11176 | mips_frame_barrier (); |
e19da24c CF |
11177 | size -= step1; |
11178 | ||
11179 | /* Start at the uppermost location for saving. */ | |
11180 | offset = frame->cop0_sp_offset - size; | |
11181 | if (!cfun->machine->keep_interrupts_masked_p) | |
11182 | { | |
11183 | /* Push EPC into its stack slot. */ | |
11184 | mem = gen_frame_mem (word_mode, | |
0a81f074 | 11185 | plus_constant (Pmode, stack_pointer_rtx, |
e19da24c CF |
11186 | offset)); |
11187 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
11188 | offset -= UNITS_PER_WORD; | |
11189 | } | |
11190 | ||
11191 | /* Move from COP0 Status to K1. */ | |
11192 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
11193 | gen_rtx_REG (SImode, | |
11194 | COP0_STATUS_REG_NUM))); | |
11195 | ||
11196 | /* Right justify the RIPL in k0. */ | |
11197 | if (!cfun->machine->keep_interrupts_masked_p) | |
11198 | emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), | |
11199 | gen_rtx_REG (SImode, K0_REG_NUM), | |
11200 | GEN_INT (CAUSE_IPL))); | |
11201 | ||
11202 | /* Push Status into its stack slot. */ | |
11203 | mem = gen_frame_mem (word_mode, | |
0a81f074 RS |
11204 | plus_constant (Pmode, stack_pointer_rtx, |
11205 | offset)); | |
e19da24c CF |
11206 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); |
11207 | offset -= UNITS_PER_WORD; | |
11208 | ||
11209 | /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ | |
11210 | if (!cfun->machine->keep_interrupts_masked_p) | |
11211 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
11212 | GEN_INT (6), | |
11213 | GEN_INT (SR_IPL), | |
11214 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
11215 | ||
11216 | if (!cfun->machine->keep_interrupts_masked_p) | |
11217 | /* Enable interrupts by clearing the KSU ERL and EXL bits. | |
11218 | IE is already the correct value, so we don't have to do | |
11219 | anything explicit. */ | |
11220 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
11221 | GEN_INT (4), | |
11222 | GEN_INT (SR_EXL), | |
11223 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
11224 | else | |
11225 | /* Disable interrupts by clearing the KSU, ERL, EXL, | |
11226 | and IE bits. */ | |
11227 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
11228 | GEN_INT (5), | |
11229 | GEN_INT (SR_IE), | |
11230 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
11231 | } | |
11232 | else | |
11233 | { | |
b32d5189 DM |
11234 | rtx insn = gen_add3_insn (stack_pointer_rtx, |
11235 | stack_pointer_rtx, | |
11236 | GEN_INT (-step1)); | |
e19da24c | 11237 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; |
d9b59f56 | 11238 | mips_frame_barrier (); |
e19da24c CF |
11239 | size -= step1; |
11240 | } | |
11241 | mips_for_each_saved_acc (size, mips_save_reg); | |
11242 | mips_for_each_saved_gpr_and_fpr (size, mips_save_reg); | |
ab77a036 RS |
11243 | } |
11244 | } | |
11245 | ||
11246 | /* Allocate the rest of the frame. */ | |
11247 | if (size > 0) | |
11248 | { | |
11249 | if (SMALL_OPERAND (-size)) | |
11250 | RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, | |
11251 | stack_pointer_rtx, | |
11252 | GEN_INT (-size)))) = 1; | |
11253 | else | |
11254 | { | |
11255 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size)); | |
11256 | if (TARGET_MIPS16) | |
11257 | { | |
11258 | /* There are no instructions to add or subtract registers | |
11259 | from the stack pointer, so use the frame pointer as a | |
11260 | temporary. We should always be using a frame pointer | |
11261 | in this case anyway. */ | |
11262 | gcc_assert (frame_pointer_needed); | |
11263 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
11264 | emit_insn (gen_sub3_insn (hard_frame_pointer_rtx, | |
11265 | hard_frame_pointer_rtx, | |
11266 | MIPS_PROLOGUE_TEMP (Pmode))); | |
11267 | mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx); | |
11268 | } | |
11269 | else | |
11270 | emit_insn (gen_sub3_insn (stack_pointer_rtx, | |
11271 | stack_pointer_rtx, | |
11272 | MIPS_PROLOGUE_TEMP (Pmode))); | |
11273 | ||
11274 | /* Describe the combined effect of the previous instructions. */ | |
11275 | mips_set_frame_expr | |
11276 | (gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
0a81f074 | 11277 | plus_constant (Pmode, stack_pointer_rtx, -size))); |
ab77a036 | 11278 | } |
d9b59f56 | 11279 | mips_frame_barrier (); |
ab77a036 RS |
11280 | } |
11281 | ||
f374e413 | 11282 | /* Set up the frame pointer, if we're using one. */ |
ab77a036 RS |
11283 | if (frame_pointer_needed) |
11284 | { | |
f374e413 RS |
11285 | HOST_WIDE_INT offset; |
11286 | ||
65239d20 | 11287 | offset = frame->hard_frame_pointer_offset; |
f374e413 | 11288 | if (offset == 0) |
ab77a036 | 11289 | { |
b32d5189 | 11290 | rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); |
f374e413 RS |
11291 | RTX_FRAME_RELATED_P (insn) = 1; |
11292 | } | |
11293 | else if (SMALL_OPERAND (offset)) | |
11294 | { | |
b32d5189 DM |
11295 | rtx insn = gen_add3_insn (hard_frame_pointer_rtx, |
11296 | stack_pointer_rtx, GEN_INT (offset)); | |
f374e413 | 11297 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; |
ab77a036 RS |
11298 | } |
11299 | else | |
f374e413 RS |
11300 | { |
11301 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset)); | |
11302 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
11303 | emit_insn (gen_add3_insn (hard_frame_pointer_rtx, | |
11304 | hard_frame_pointer_rtx, | |
11305 | MIPS_PROLOGUE_TEMP (Pmode))); | |
11306 | mips_set_frame_expr | |
11307 | (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, | |
0a81f074 | 11308 | plus_constant (Pmode, stack_pointer_rtx, offset))); |
f374e413 | 11309 | } |
ab77a036 RS |
11310 | } |
11311 | ||
11312 | mips_emit_loadgp (); | |
11313 | ||
65239d20 | 11314 | /* Initialize the $gp save slot. */ |
0c433c31 | 11315 | if (mips_cfun_has_cprestore_slot_p ()) |
08d0963a | 11316 | { |
0c433c31 RS |
11317 | rtx base, mem, gp, temp; |
11318 | HOST_WIDE_INT offset; | |
11319 | ||
11320 | mips_get_cprestore_base_and_offset (&base, &offset, false); | |
0a81f074 | 11321 | mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset)); |
0c433c31 RS |
11322 | gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; |
11323 | temp = (SMALL_OPERAND (offset) | |
11324 | ? gen_rtx_SCRATCH (Pmode) | |
11325 | : MIPS_PROLOGUE_TEMP (Pmode)); | |
81a478c8 RS |
11326 | emit_insn (PMODE_INSN (gen_potential_cprestore, |
11327 | (mem, GEN_INT (offset), gp, temp))); | |
0c433c31 RS |
11328 | |
11329 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
0a81f074 | 11330 | mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset)); |
81a478c8 | 11331 | emit_insn (PMODE_INSN (gen_use_cprestore, (mem))); |
08d0963a | 11332 | } |
ab77a036 | 11333 | |
e19da24c CF |
11334 | /* We need to search back to the last use of K0 or K1. */ |
11335 | if (cfun->machine->interrupt_handler_p) | |
11336 | { | |
b32d5189 | 11337 | rtx_insn *insn; |
e19da24c CF |
11338 | for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn)) |
11339 | if (INSN_P (insn) | |
eacbf7bd | 11340 | && mips_refers_to_kernel_reg_p (PATTERN (insn))) |
e19da24c CF |
11341 | break; |
11342 | /* Emit a move from K1 to COP0 Status after insn. */ | |
11343 | gcc_assert (insn != NULL_RTX); | |
11344 | emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
11345 | gen_rtx_REG (SImode, K1_REG_NUM)), | |
11346 | insn); | |
11347 | } | |
11348 | ||
ab77a036 RS |
11349 | /* If we are profiling, make sure no instructions are scheduled before |
11350 | the call to mcount. */ | |
e3b5732b | 11351 | if (crtl->profile) |
ab77a036 RS |
11352 | emit_insn (gen_blockage ()); |
11353 | } | |
11354 | \f | |
3bd0817d RS |
11355 | /* Attach all pending register saves to the previous instruction. |
11356 | Return that instruction. */ | |
11357 | ||
c6f971f4 | 11358 | static rtx_insn * |
3bd0817d RS |
11359 | mips_epilogue_emit_cfa_restores (void) |
11360 | { | |
c6f971f4 | 11361 | rtx_insn *insn; |
3bd0817d RS |
11362 | |
11363 | insn = get_last_insn (); | |
11364 | gcc_assert (insn && !REG_NOTES (insn)); | |
11365 | if (mips_epilogue.cfa_restores) | |
11366 | { | |
11367 | RTX_FRAME_RELATED_P (insn) = 1; | |
11368 | REG_NOTES (insn) = mips_epilogue.cfa_restores; | |
11369 | mips_epilogue.cfa_restores = 0; | |
11370 | } | |
11371 | return insn; | |
11372 | } | |
11373 | ||
11374 | /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is | |
11375 | now at REG + OFFSET. */ | |
11376 | ||
11377 | static void | |
11378 | mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset) | |
11379 | { | |
c6f971f4 | 11380 | rtx_insn *insn; |
3bd0817d RS |
11381 | |
11382 | insn = mips_epilogue_emit_cfa_restores (); | |
11383 | if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset) | |
11384 | { | |
11385 | RTX_FRAME_RELATED_P (insn) = 1; | |
11386 | REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, | |
0a81f074 | 11387 | plus_constant (Pmode, reg, offset), |
3bd0817d RS |
11388 | REG_NOTES (insn)); |
11389 | mips_epilogue.cfa_reg = reg; | |
11390 | mips_epilogue.cfa_offset = offset; | |
11391 | } | |
11392 | } | |
11393 | ||
11394 | /* Emit instructions to restore register REG from slot MEM. Also update | |
11395 | the cfa_restores list. */ | |
ab77a036 RS |
11396 | |
11397 | static void | |
11398 | mips_restore_reg (rtx reg, rtx mem) | |
11399 | { | |
65239d20 | 11400 | /* There's no MIPS16 instruction to load $31 directly. Load into |
ab77a036 | 11401 | $7 instead and adjust the return insn appropriately. */ |
293593b1 | 11402 | if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM) |
65239d20 | 11403 | reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7); |
a7449961 BS |
11404 | else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) |
11405 | { | |
11406 | mips_add_cfa_restore (mips_subword (reg, true)); | |
11407 | mips_add_cfa_restore (mips_subword (reg, false)); | |
11408 | } | |
3bd0817d | 11409 | else |
a7449961 | 11410 | mips_add_cfa_restore (reg); |
ab77a036 | 11411 | |
0c433c31 | 11412 | mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg))); |
3bd0817d RS |
11413 | if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg)) |
11414 | /* The CFA is currently defined in terms of the register whose | |
11415 | value we have just restored. Redefine the CFA in terms of | |
11416 | the stack pointer. */ | |
11417 | mips_epilogue_set_cfa (stack_pointer_rtx, | |
11418 | mips_epilogue.cfa_restore_sp_offset); | |
ab77a036 RS |
11419 | } |
11420 | ||
d9b59f56 RS |
11421 | /* Emit code to set the stack pointer to BASE + OFFSET, given that |
11422 | BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame. | |
11423 | BASE, if not the stack pointer, is available as a temporary. */ | |
11424 | ||
11425 | static void | |
11426 | mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size) | |
11427 | { | |
11428 | if (base == stack_pointer_rtx && offset == const0_rtx) | |
11429 | return; | |
11430 | ||
11431 | mips_frame_barrier (); | |
11432 | if (offset == const0_rtx) | |
11433 | { | |
11434 | emit_move_insn (stack_pointer_rtx, base); | |
11435 | mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size); | |
11436 | } | |
11437 | else if (TARGET_MIPS16 && base != stack_pointer_rtx) | |
11438 | { | |
11439 | emit_insn (gen_add3_insn (base, base, offset)); | |
11440 | mips_epilogue_set_cfa (base, new_frame_size); | |
11441 | emit_move_insn (stack_pointer_rtx, base); | |
11442 | } | |
11443 | else | |
11444 | { | |
11445 | emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset)); | |
11446 | mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size); | |
11447 | } | |
11448 | } | |
11449 | ||
2f7e2abb RS |
11450 | /* Emit any instructions needed before a return. */ |
11451 | ||
11452 | void | |
11453 | mips_expand_before_return (void) | |
11454 | { | |
11455 | /* When using a call-clobbered gp, we start out with unified call | |
11456 | insns that include instructions to restore the gp. We then split | |
11457 | these unified calls after reload. These split calls explicitly | |
11458 | clobber gp, so there is no need to define | |
11459 | PIC_OFFSET_TABLE_REG_CALL_CLOBBERED. | |
11460 | ||
11461 | For consistency, we should also insert an explicit clobber of $28 | |
11462 | before return insns, so that the post-reload optimizers know that | |
11463 | the register is not live on exit. */ | |
11464 | if (TARGET_CALL_CLOBBERED_GP) | |
11465 | emit_clobber (pic_offset_table_rtx); | |
11466 | } | |
11467 | ||
65239d20 RS |
11468 | /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P |
11469 | says which. */ | |
ab77a036 RS |
11470 | |
11471 | void | |
65239d20 | 11472 | mips_expand_epilogue (bool sibcall_p) |
ab77a036 | 11473 | { |
65239d20 | 11474 | const struct mips_frame_info *frame; |
ab77a036 | 11475 | HOST_WIDE_INT step1, step2; |
c6f971f4 DM |
11476 | rtx base, adjust; |
11477 | rtx_insn *insn; | |
83082391 | 11478 | bool use_jraddiusp_p = false; |
ab77a036 RS |
11479 | |
11480 | if (!sibcall_p && mips_can_use_return_insn ()) | |
11481 | { | |
11482 | emit_jump_insn (gen_return ()); | |
11483 | return; | |
11484 | } | |
11485 | ||
65239d20 | 11486 | /* In MIPS16 mode, if the return value should go into a floating-point |
ab77a036 RS |
11487 | register, we need to call a helper routine to copy it over. */ |
11488 | if (mips16_cfun_returns_in_fpr_p ()) | |
5f5fe6d9 | 11489 | mips16_copy_fpr_return_value (); |
1f2d8f51 | 11490 | |
be763023 RS |
11491 | /* Split the frame into two. STEP1 is the amount of stack we should |
11492 | deallocate before restoring the registers. STEP2 is the amount we | |
11493 | should deallocate afterwards. | |
11494 | ||
11495 | Start off by assuming that no registers need to be restored. */ | |
65239d20 RS |
11496 | frame = &cfun->machine->frame; |
11497 | step1 = frame->total_size; | |
be763023 RS |
11498 | step2 = 0; |
11499 | ||
f374e413 | 11500 | /* Work out which register holds the frame address. */ |
be763023 RS |
11501 | if (!frame_pointer_needed) |
11502 | base = stack_pointer_rtx; | |
11503 | else | |
0fb5ac6f | 11504 | { |
be763023 | 11505 | base = hard_frame_pointer_rtx; |
65239d20 | 11506 | step1 -= frame->hard_frame_pointer_offset; |
0fb5ac6f | 11507 | } |
3bd0817d RS |
11508 | mips_epilogue.cfa_reg = base; |
11509 | mips_epilogue.cfa_offset = step1; | |
11510 | mips_epilogue.cfa_restores = NULL_RTX; | |
0fb5ac6f | 11511 | |
be763023 RS |
11512 | /* If we need to restore registers, deallocate as much stack as |
11513 | possible in the second step without going out of range. */ | |
e19da24c CF |
11514 | if ((frame->mask | frame->fmask | frame->acc_mask) != 0 |
11515 | || frame->num_cop0_regs > 0) | |
0fb5ac6f | 11516 | { |
be763023 RS |
11517 | step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP); |
11518 | step1 -= step2; | |
11519 | } | |
f5963e61 | 11520 | |
d9b59f56 RS |
11521 | /* Get an rtx for STEP1 that we can add to BASE. */ |
11522 | adjust = GEN_INT (step1); | |
11523 | if (!SMALL_OPERAND (step1)) | |
be763023 | 11524 | { |
d9b59f56 RS |
11525 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust); |
11526 | adjust = MIPS_EPILOGUE_TEMP (Pmode); | |
be763023 | 11527 | } |
d9b59f56 | 11528 | mips_deallocate_stack (base, adjust, step2); |
282cb01b | 11529 | |
14976818 RS |
11530 | /* If we're using addressing macros, $gp is implicitly used by all |
11531 | SYMBOL_REFs. We must emit a blockage insn before restoring $gp | |
11532 | from the stack. */ | |
11533 | if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS) | |
be763023 | 11534 | emit_insn (gen_blockage ()); |
282cb01b | 11535 | |
3bd0817d | 11536 | mips_epilogue.cfa_restore_sp_offset = step2; |
65239d20 | 11537 | if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0) |
e1260576 RS |
11538 | { |
11539 | unsigned int regno, mask; | |
11540 | HOST_WIDE_INT offset; | |
11541 | rtx restore; | |
11542 | ||
11543 | /* Generate the restore instruction. */ | |
65239d20 | 11544 | mask = frame->mask; |
e1260576 RS |
11545 | restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2); |
11546 | ||
11547 | /* Restore any other registers manually. */ | |
11548 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
11549 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
11550 | { | |
6e75e6e3 RS |
11551 | offset -= UNITS_PER_WORD; |
11552 | mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg); | |
e1260576 | 11553 | } |
be763023 | 11554 | |
e1260576 RS |
11555 | /* Restore the remaining registers and deallocate the final bit |
11556 | of the frame. */ | |
d9b59f56 | 11557 | mips_frame_barrier (); |
e1260576 | 11558 | emit_insn (restore); |
3bd0817d | 11559 | mips_epilogue_set_cfa (stack_pointer_rtx, 0); |
e1260576 RS |
11560 | } |
11561 | else | |
11562 | { | |
11563 | /* Restore the registers. */ | |
e19da24c CF |
11564 | mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg); |
11565 | mips_for_each_saved_gpr_and_fpr (frame->total_size - step2, | |
11566 | mips_restore_reg); | |
e1260576 | 11567 | |
e19da24c CF |
11568 | if (cfun->machine->interrupt_handler_p) |
11569 | { | |
11570 | HOST_WIDE_INT offset; | |
11571 | rtx mem; | |
11572 | ||
11573 | offset = frame->cop0_sp_offset - (frame->total_size - step2); | |
11574 | if (!cfun->machine->keep_interrupts_masked_p) | |
11575 | { | |
11576 | /* Restore the original EPC. */ | |
11577 | mem = gen_frame_mem (word_mode, | |
0a81f074 RS |
11578 | plus_constant (Pmode, stack_pointer_rtx, |
11579 | offset)); | |
e19da24c CF |
11580 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); |
11581 | offset -= UNITS_PER_WORD; | |
11582 | ||
11583 | /* Move to COP0 EPC. */ | |
11584 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM), | |
11585 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
11586 | } | |
11587 | ||
11588 | /* Restore the original Status. */ | |
11589 | mem = gen_frame_mem (word_mode, | |
0a81f074 RS |
11590 | plus_constant (Pmode, stack_pointer_rtx, |
11591 | offset)); | |
e19da24c CF |
11592 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); |
11593 | offset -= UNITS_PER_WORD; | |
11594 | ||
22c4c869 | 11595 | /* If we don't use shadow register set, we need to update SP. */ |
d9b59f56 RS |
11596 | if (!cfun->machine->use_shadow_register_set_p) |
11597 | mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0); | |
3bd0817d RS |
11598 | else |
11599 | /* The choice of position is somewhat arbitrary in this case. */ | |
11600 | mips_epilogue_emit_cfa_restores (); | |
e19da24c CF |
11601 | |
11602 | /* Move to COP0 Status. */ | |
11603 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
11604 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
11605 | } | |
83082391 CM |
11606 | else if (TARGET_MICROMIPS |
11607 | && !crtl->calls_eh_return | |
11608 | && !sibcall_p | |
11609 | && step2 > 0 | |
11610 | && mips_unsigned_immediate_p (step2, 5, 2)) | |
11611 | use_jraddiusp_p = true; | |
e19da24c | 11612 | else |
d9b59f56 RS |
11613 | /* Deallocate the final bit of the frame. */ |
11614 | mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0); | |
e1260576 | 11615 | } |
22c4c869 | 11616 | |
83082391 CM |
11617 | if (!use_jraddiusp_p) |
11618 | gcc_assert (!mips_epilogue.cfa_restores); | |
91e01231 | 11619 | |
71cc389b | 11620 | /* Add in the __builtin_eh_return stack adjustment. We need to |
65239d20 | 11621 | use a temporary in MIPS16 code. */ |
e3b5732b | 11622 | if (crtl->calls_eh_return) |
be763023 RS |
11623 | { |
11624 | if (TARGET_MIPS16) | |
11625 | { | |
51e7252a | 11626 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx); |
be763023 RS |
11627 | emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode), |
11628 | MIPS_EPILOGUE_TEMP (Pmode), | |
11629 | EH_RETURN_STACKADJ_RTX)); | |
51e7252a | 11630 | mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode)); |
9e800206 | 11631 | } |
be763023 RS |
11632 | else |
11633 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
11634 | stack_pointer_rtx, | |
11635 | EH_RETURN_STACKADJ_RTX)); | |
0fb5ac6f | 11636 | } |
be763023 | 11637 | |
cafe096b EC |
11638 | if (!sibcall_p) |
11639 | { | |
2f7e2abb | 11640 | mips_expand_before_return (); |
e19da24c CF |
11641 | if (cfun->machine->interrupt_handler_p) |
11642 | { | |
11643 | /* Interrupt handlers generate eret or deret. */ | |
11644 | if (cfun->machine->use_debug_exception_return_p) | |
11645 | emit_jump_insn (gen_mips_deret ()); | |
11646 | else | |
11647 | emit_jump_insn (gen_mips_eret ()); | |
11648 | } | |
11649 | else | |
11650 | { | |
35511751 | 11651 | rtx pat; |
e19da24c CF |
11652 | |
11653 | /* When generating MIPS16 code, the normal | |
11654 | mips_for_each_saved_gpr_and_fpr path will restore the return | |
11655 | address into $7 rather than $31. */ | |
11656 | if (TARGET_MIPS16 | |
11657 | && !GENERATE_MIPS16E_SAVE_RESTORE | |
293593b1 | 11658 | && BITSET_P (frame->mask, RETURN_ADDR_REGNUM)) |
35511751 BS |
11659 | { |
11660 | /* simple_returns cannot rely on values that are only available | |
11661 | on paths through the epilogue (because return paths that do | |
11662 | not pass through the epilogue may nevertheless reuse a | |
11663 | simple_return that occurs at the end of the epilogue). | |
11664 | Use a normal return here instead. */ | |
11665 | rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7); | |
11666 | pat = gen_return_internal (reg); | |
11667 | } | |
83082391 CM |
11668 | else if (use_jraddiusp_p) |
11669 | pat = gen_jraddiusp (GEN_INT (step2)); | |
e19da24c | 11670 | else |
35511751 BS |
11671 | { |
11672 | rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); | |
11673 | pat = gen_simple_return_internal (reg); | |
11674 | } | |
11675 | emit_jump_insn (pat); | |
83082391 CM |
11676 | if (use_jraddiusp_p) |
11677 | mips_epilogue_set_cfa (stack_pointer_rtx, step2); | |
e19da24c CF |
11678 | } |
11679 | } | |
11680 | ||
11681 | /* Search from the beginning to the first use of K0 or K1. */ | |
11682 | if (cfun->machine->interrupt_handler_p | |
11683 | && !cfun->machine->keep_interrupts_masked_p) | |
11684 | { | |
11685 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
11686 | if (INSN_P (insn) | |
eacbf7bd | 11687 | && mips_refers_to_kernel_reg_p (PATTERN (insn))) |
e19da24c CF |
11688 | break; |
11689 | gcc_assert (insn != NULL_RTX); | |
11690 | /* Insert disable interrupts before the first use of K0 or K1. */ | |
11691 | emit_insn_before (gen_mips_di (), insn); | |
11692 | emit_insn_before (gen_mips_ehb (), insn); | |
cafe096b | 11693 | } |
cee98a59 | 11694 | } |
cee98a59 | 11695 | \f |
f5963e61 | 11696 | /* Return nonzero if this function is known to have a null epilogue. |
cee98a59 MM |
11697 | This allows the optimizer to omit jumps to jumps if no stack |
11698 | was created. */ | |
11699 | ||
65239d20 | 11700 | bool |
b4966b1b | 11701 | mips_can_use_return_insn (void) |
cee98a59 | 11702 | { |
e19da24c CF |
11703 | /* Interrupt handlers need to go through the epilogue. */ |
11704 | if (cfun->machine->interrupt_handler_p) | |
11705 | return false; | |
11706 | ||
65239d20 RS |
11707 | if (!reload_completed) |
11708 | return false; | |
cee98a59 | 11709 | |
e3b5732b | 11710 | if (crtl->profile) |
65239d20 | 11711 | return false; |
1f2d8f51 | 11712 | |
65239d20 RS |
11713 | /* In MIPS16 mode, a function that returns a floating-point value |
11714 | needs to arrange to copy the return value into the floating-point | |
2bcb2ab3 | 11715 | registers. */ |
a38e0142 | 11716 | if (mips16_cfun_returns_in_fpr_p ()) |
65239d20 | 11717 | return false; |
2bcb2ab3 | 11718 | |
16dc5c28 | 11719 | return cfun->machine->frame.total_size == 0; |
cee98a59 | 11720 | } |
9753d4e4 | 11721 | \f |
5f5fe6d9 RS |
11722 | /* Return true if register REGNO can store a value of mode MODE. |
11723 | The result of this function is cached in mips_hard_regno_mode_ok. */ | |
11724 | ||
11725 | static bool | |
ef4bddc2 | 11726 | mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode) |
5f5fe6d9 RS |
11727 | { |
11728 | unsigned int size; | |
0a2aaacc | 11729 | enum mode_class mclass; |
5f5fe6d9 RS |
11730 | |
11731 | if (mode == CCV2mode) | |
11732 | return (ISA_HAS_8CC | |
11733 | && ST_REG_P (regno) | |
11734 | && (regno - ST_REG_FIRST) % 2 == 0); | |
11735 | ||
11736 | if (mode == CCV4mode) | |
11737 | return (ISA_HAS_8CC | |
11738 | && ST_REG_P (regno) | |
11739 | && (regno - ST_REG_FIRST) % 4 == 0); | |
11740 | ||
11741 | if (mode == CCmode) | |
4b11e406 | 11742 | return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM; |
5f5fe6d9 RS |
11743 | |
11744 | size = GET_MODE_SIZE (mode); | |
0a2aaacc | 11745 | mclass = GET_MODE_CLASS (mode); |
5f5fe6d9 RS |
11746 | |
11747 | if (GP_REG_P (regno)) | |
11748 | return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; | |
11749 | ||
11750 | if (FP_REG_P (regno) | |
11751 | && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0 | |
11752 | || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG))) | |
11753 | { | |
93581857 MS |
11754 | /* Allow 64-bit vector modes for Loongson-2E/2F. */ |
11755 | if (TARGET_LOONGSON_VECTORS | |
11756 | && (mode == V2SImode | |
11757 | || mode == V4HImode | |
11758 | || mode == V8QImode | |
11759 | || mode == DImode)) | |
11760 | return true; | |
11761 | ||
0a2aaacc KG |
11762 | if (mclass == MODE_FLOAT |
11763 | || mclass == MODE_COMPLEX_FLOAT | |
11764 | || mclass == MODE_VECTOR_FLOAT) | |
5f5fe6d9 RS |
11765 | return size <= UNITS_PER_FPVALUE; |
11766 | ||
11767 | /* Allow integer modes that fit into a single register. We need | |
11768 | to put integers into FPRs when using instructions like CVT | |
11769 | and TRUNC. There's no point allowing sizes smaller than a word, | |
11770 | because the FPU has no appropriate load/store instructions. */ | |
0a2aaacc | 11771 | if (mclass == MODE_INT) |
5f5fe6d9 RS |
11772 | return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG; |
11773 | } | |
11774 | ||
11775 | if (ACC_REG_P (regno) | |
11776 | && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) | |
11777 | { | |
21dfc6dc RS |
11778 | if (MD_REG_P (regno)) |
11779 | { | |
11780 | /* After a multiplication or division, clobbering HI makes | |
11781 | the value of LO unpredictable, and vice versa. This means | |
11782 | that, for all interesting cases, HI and LO are effectively | |
11783 | a single register. | |
11784 | ||
11785 | We model this by requiring that any value that uses HI | |
11786 | also uses LO. */ | |
11787 | if (size <= UNITS_PER_WORD * 2) | |
11788 | return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); | |
11789 | } | |
11790 | else | |
11791 | { | |
11792 | /* DSP accumulators do not have the same restrictions as | |
11793 | HI and LO, so we can treat them as normal doubleword | |
11794 | registers. */ | |
11795 | if (size <= UNITS_PER_WORD) | |
11796 | return true; | |
5f5fe6d9 | 11797 | |
21dfc6dc RS |
11798 | if (size <= UNITS_PER_WORD * 2 |
11799 | && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) | |
11800 | return true; | |
11801 | } | |
5f5fe6d9 RS |
11802 | } |
11803 | ||
11804 | if (ALL_COP_REG_P (regno)) | |
0a2aaacc | 11805 | return mclass == MODE_INT && size <= UNITS_PER_WORD; |
5f5fe6d9 | 11806 | |
dbc90b65 RS |
11807 | if (regno == GOT_VERSION_REGNUM) |
11808 | return mode == SImode; | |
11809 | ||
5f5fe6d9 RS |
11810 | return false; |
11811 | } | |
11812 | ||
c862c910 | 11813 | /* Implement HARD_REGNO_NREGS. */ |
b85aed9e | 11814 | |
ab77a036 | 11815 | unsigned int |
ef4bddc2 | 11816 | mips_hard_regno_nregs (int regno, machine_mode mode) |
b85aed9e | 11817 | { |
ab77a036 | 11818 | if (ST_REG_P (regno)) |
c862c910 RS |
11819 | /* The size of FP status registers is always 4, because they only hold |
11820 | CCmode values, and CCmode is always considered to be 4 bytes wide. */ | |
11821 | return (GET_MODE_SIZE (mode) + 3) / 4; | |
b85aed9e | 11822 | |
c862c910 RS |
11823 | if (FP_REG_P (regno)) |
11824 | return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; | |
e440de0e | 11825 | |
c862c910 RS |
11826 | /* All other registers are word-sized. */ |
11827 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
11828 | } | |
6fb5fa3c | 11829 | |
c862c910 RS |
11830 | /* Implement CLASS_MAX_NREGS, taking the maximum of the cases |
11831 | in mips_hard_regno_nregs. */ | |
f5678792 | 11832 | |
ab77a036 | 11833 | int |
ef4bddc2 | 11834 | mips_class_max_nregs (enum reg_class rclass, machine_mode mode) |
ab77a036 | 11835 | { |
c862c910 RS |
11836 | int size; |
11837 | HARD_REG_SET left; | |
11838 | ||
11839 | size = 0x8000; | |
0a2aaacc | 11840 | COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); |
c862c910 RS |
11841 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) |
11842 | { | |
894113c3 RS |
11843 | if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode)) |
11844 | size = MIN (size, 4); | |
c862c910 RS |
11845 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); |
11846 | } | |
11847 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) | |
11848 | { | |
894113c3 RS |
11849 | if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode)) |
11850 | size = MIN (size, UNITS_PER_FPREG); | |
c862c910 RS |
11851 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); |
11852 | } | |
11853 | if (!hard_reg_set_empty_p (left)) | |
11854 | size = MIN (size, UNITS_PER_WORD); | |
11855 | return (GET_MODE_SIZE (mode) + size - 1) / size; | |
ab77a036 | 11856 | } |
b85aed9e | 11857 | |
65239d20 | 11858 | /* Implement CANNOT_CHANGE_MODE_CLASS. */ |
b85aed9e | 11859 | |
ab77a036 | 11860 | bool |
ef4bddc2 RS |
11861 | mips_cannot_change_mode_class (machine_mode from, |
11862 | machine_mode to, | |
0a2aaacc | 11863 | enum reg_class rclass) |
ab77a036 | 11864 | { |
7dab511c RH |
11865 | /* Allow conversions between different Loongson integer vectors, |
11866 | and between those vectors and DImode. */ | |
11867 | if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8 | |
11868 | && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to)) | |
11869 | return false; | |
11870 | ||
11871 | /* Otherwise, there are several problems with changing the modes of | |
11872 | values in floating-point registers: | |
b85aed9e | 11873 | |
ab77a036 | 11874 | - When a multi-word value is stored in paired floating-point |
dd5a833e MS |
11875 | registers, the first register always holds the low word. We |
11876 | therefore can't allow FPRs to change between single-word and | |
11877 | multi-word modes on big-endian targets. | |
b85aed9e | 11878 | |
dd5a833e MS |
11879 | - GCC assumes that each word of a multiword register can be |
11880 | accessed individually using SUBREGs. This is not true for | |
11881 | floating-point registers if they are bigger than a word. | |
b85aed9e | 11882 | |
ab77a036 | 11883 | - Loading a 32-bit value into a 64-bit floating-point register |
dd5a833e MS |
11884 | will not sign-extend the value, despite what LOAD_EXTEND_OP |
11885 | says. We can't allow FPRs to change from SImode to a wider | |
11886 | mode on 64-bit targets. | |
b85aed9e | 11887 | |
dd5a833e MS |
11888 | - If the FPU has already interpreted a value in one format, we |
11889 | must not ask it to treat the value as having a different | |
11890 | format. | |
b85aed9e | 11891 | |
43029c10 | 11892 | We therefore disallow all mode changes involving FPRs. */ |
7dab511c | 11893 | |
0a2aaacc | 11894 | return reg_classes_intersect_p (FP_REGS, rclass); |
ab77a036 | 11895 | } |
b85aed9e | 11896 | |
42db504c SB |
11897 | /* Implement target hook small_register_classes_for_mode_p. */ |
11898 | ||
11899 | static bool | |
ef4bddc2 | 11900 | mips_small_register_classes_for_mode_p (machine_mode mode |
42db504c SB |
11901 | ATTRIBUTE_UNUSED) |
11902 | { | |
11903 | return TARGET_MIPS16; | |
11904 | } | |
11905 | ||
ab77a036 | 11906 | /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */ |
b85aed9e | 11907 | |
ab77a036 | 11908 | static bool |
ef4bddc2 | 11909 | mips_mode_ok_for_mov_fmt_p (machine_mode mode) |
ab77a036 RS |
11910 | { |
11911 | switch (mode) | |
b85aed9e | 11912 | { |
ab77a036 RS |
11913 | case SFmode: |
11914 | return TARGET_HARD_FLOAT; | |
b85aed9e | 11915 | |
ab77a036 RS |
11916 | case DFmode: |
11917 | return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT; | |
b85aed9e | 11918 | |
ab77a036 RS |
11919 | case V2SFmode: |
11920 | return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT; | |
b85aed9e | 11921 | |
ab77a036 RS |
11922 | default: |
11923 | return false; | |
b85aed9e | 11924 | } |
b85aed9e | 11925 | } |
9753d4e4 | 11926 | |
e5a2b69d RS |
11927 | /* Implement MODES_TIEABLE_P. */ |
11928 | ||
11929 | bool | |
ef4bddc2 | 11930 | mips_modes_tieable_p (machine_mode mode1, machine_mode mode2) |
e5a2b69d RS |
11931 | { |
11932 | /* FPRs allow no mode punning, so it's not worth tying modes if we'd | |
11933 | prefer to put one of them in FPRs. */ | |
11934 | return (mode1 == mode2 | |
11935 | || (!mips_mode_ok_for_mov_fmt_p (mode1) | |
11936 | && !mips_mode_ok_for_mov_fmt_p (mode2))); | |
11937 | } | |
11938 | ||
ef78aed6 | 11939 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
7dac2f89 | 11940 | |
ef78aed6 AS |
11941 | static reg_class_t |
11942 | mips_preferred_reload_class (rtx x, reg_class_t rclass) | |
ab77a036 | 11943 | { |
0a2aaacc | 11944 | if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass)) |
ab77a036 | 11945 | return LEA_REGS; |
9753d4e4 | 11946 | |
0a2aaacc | 11947 | if (reg_class_subset_p (FP_REGS, rclass) |
ab77a036 RS |
11948 | && mips_mode_ok_for_mov_fmt_p (GET_MODE (x))) |
11949 | return FP_REGS; | |
94b9aa66 | 11950 | |
0a2aaacc KG |
11951 | if (reg_class_subset_p (GR_REGS, rclass)) |
11952 | rclass = GR_REGS; | |
94b9aa66 | 11953 | |
0a2aaacc KG |
11954 | if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass)) |
11955 | rclass = M16_REGS; | |
d6b5193b | 11956 | |
0a2aaacc | 11957 | return rclass; |
94b9aa66 RS |
11958 | } |
11959 | ||
aea8cb37 RS |
11960 | /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. |
11961 | Return a "canonical" class to represent it in later calculations. */ | |
91455597 | 11962 | |
faa832a7 AS |
11963 | static reg_class_t |
11964 | mips_canonicalize_move_class (reg_class_t rclass) | |
ab77a036 | 11965 | { |
aea8cb37 RS |
11966 | /* All moves involving accumulator registers have the same cost. */ |
11967 | if (reg_class_subset_p (rclass, ACC_REGS)) | |
11968 | rclass = ACC_REGS; | |
11969 | ||
11970 | /* Likewise promote subclasses of general registers to the most | |
11971 | interesting containing class. */ | |
11972 | if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS)) | |
11973 | rclass = M16_REGS; | |
11974 | else if (reg_class_subset_p (rclass, GENERAL_REGS)) | |
11975 | rclass = GENERAL_REGS; | |
11976 | ||
11977 | return rclass; | |
11978 | } | |
11979 | ||
82db17cb RS |
11980 | /* Return the cost of moving a value from a register of class FROM to a GPR. |
11981 | Return 0 for classes that are unions of other classes handled by this | |
11982 | function. */ | |
aea8cb37 RS |
11983 | |
11984 | static int | |
82db17cb | 11985 | mips_move_to_gpr_cost (reg_class_t from) |
aea8cb37 RS |
11986 | { |
11987 | switch (from) | |
9753d4e4 | 11988 | { |
ca376eb8 | 11989 | case M16_REGS: |
aea8cb37 RS |
11990 | case GENERAL_REGS: |
11991 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
11992 | return 2; | |
11993 | ||
11994 | case ACC_REGS: | |
11995 | /* MFLO and MFHI. */ | |
11996 | return 6; | |
11997 | ||
11998 | case FP_REGS: | |
11999 | /* MFC1, etc. */ | |
12000 | return 4; | |
12001 | ||
aea8cb37 RS |
12002 | case COP0_REGS: |
12003 | case COP2_REGS: | |
12004 | case COP3_REGS: | |
12005 | /* This choice of value is historical. */ | |
12006 | return 5; | |
12007 | ||
12008 | default: | |
12009 | return 0; | |
9753d4e4 | 12010 | } |
aea8cb37 RS |
12011 | } |
12012 | ||
82db17cb RS |
12013 | /* Return the cost of moving a value from a GPR to a register of class TO. |
12014 | Return 0 for classes that are unions of other classes handled by this | |
12015 | function. */ | |
aea8cb37 RS |
12016 | |
12017 | static int | |
82db17cb | 12018 | mips_move_from_gpr_cost (reg_class_t to) |
aea8cb37 RS |
12019 | { |
12020 | switch (to) | |
9753d4e4 | 12021 | { |
ca376eb8 | 12022 | case M16_REGS: |
aea8cb37 RS |
12023 | case GENERAL_REGS: |
12024 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
12025 | return 2; | |
12026 | ||
12027 | case ACC_REGS: | |
12028 | /* MTLO and MTHI. */ | |
12029 | return 6; | |
12030 | ||
12031 | case FP_REGS: | |
12032 | /* MTC1, etc. */ | |
12033 | return 4; | |
12034 | ||
aea8cb37 RS |
12035 | case COP0_REGS: |
12036 | case COP2_REGS: | |
12037 | case COP3_REGS: | |
12038 | /* This choice of value is historical. */ | |
12039 | return 5; | |
12040 | ||
12041 | default: | |
12042 | return 0; | |
9753d4e4 | 12043 | } |
aea8cb37 RS |
12044 | } |
12045 | ||
faa832a7 | 12046 | /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the |
aea8cb37 RS |
12047 | maximum of the move costs for subclasses; regclass will work out |
12048 | the maximum for us. */ | |
12049 | ||
faa832a7 | 12050 | static int |
ef4bddc2 | 12051 | mips_register_move_cost (machine_mode mode, |
faa832a7 | 12052 | reg_class_t from, reg_class_t to) |
aea8cb37 | 12053 | { |
faa832a7 | 12054 | reg_class_t dregs; |
aea8cb37 RS |
12055 | int cost1, cost2; |
12056 | ||
12057 | from = mips_canonicalize_move_class (from); | |
12058 | to = mips_canonicalize_move_class (to); | |
12059 | ||
12060 | /* Handle moves that can be done without using general-purpose registers. */ | |
12061 | if (from == FP_REGS) | |
a318179e | 12062 | { |
aea8cb37 RS |
12063 | if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode)) |
12064 | /* MOV.FMT. */ | |
ab77a036 | 12065 | return 4; |
ab77a036 | 12066 | } |
aea8cb37 RS |
12067 | |
12068 | /* Handle cases in which only one class deviates from the ideal. */ | |
12069 | dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS; | |
12070 | if (from == dregs) | |
82db17cb | 12071 | return mips_move_from_gpr_cost (to); |
aea8cb37 | 12072 | if (to == dregs) |
82db17cb | 12073 | return mips_move_to_gpr_cost (from); |
aea8cb37 RS |
12074 | |
12075 | /* Handles cases that require a GPR temporary. */ | |
82db17cb | 12076 | cost1 = mips_move_to_gpr_cost (from); |
aea8cb37 | 12077 | if (cost1 != 0) |
ab77a036 | 12078 | { |
82db17cb | 12079 | cost2 = mips_move_from_gpr_cost (to); |
aea8cb37 RS |
12080 | if (cost2 != 0) |
12081 | return cost1 + cost2; | |
a318179e RS |
12082 | } |
12083 | ||
aea8cb37 | 12084 | return 0; |
9753d4e4 | 12085 | } |
ea462dd0 | 12086 | |
a78cc314 RS |
12087 | /* Implement TARGET_REGISTER_PRIORITY. */ |
12088 | ||
12089 | static int | |
12090 | mips_register_priority (int hard_regno) | |
12091 | { | |
12092 | /* Treat MIPS16 registers with higher priority than other regs. */ | |
12093 | if (TARGET_MIPS16 | |
12094 | && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno)) | |
12095 | return 1; | |
12096 | return 0; | |
12097 | } | |
12098 | ||
faa832a7 AS |
12099 | /* Implement TARGET_MEMORY_MOVE_COST. */ |
12100 | ||
12101 | static int | |
ef4bddc2 | 12102 | mips_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) |
faa832a7 AS |
12103 | { |
12104 | return (mips_cost->memory_latency | |
12105 | + memory_move_secondary_cost (mode, rclass, in)); | |
12106 | } | |
12107 | ||
65239d20 | 12108 | /* Return the register class required for a secondary register when |
0a2aaacc | 12109 | copying between one of the registers in RCLASS and value X, which |
65239d20 RS |
12110 | has mode MODE. X is the source of the move if IN_P, otherwise it |
12111 | is the destination. Return NO_REGS if no secondary register is | |
12112 | needed. */ | |
ea462dd0 | 12113 | |
ab77a036 | 12114 | enum reg_class |
0a2aaacc | 12115 | mips_secondary_reload_class (enum reg_class rclass, |
ef4bddc2 | 12116 | machine_mode mode, rtx x, bool) |
ea462dd0 | 12117 | { |
ab77a036 | 12118 | int regno; |
ea462dd0 | 12119 | |
ab77a036 RS |
12120 | /* If X is a constant that cannot be loaded into $25, it must be loaded |
12121 | into some other GPR. No other register class allows a direct move. */ | |
12122 | if (mips_dangerous_for_la25_p (x)) | |
0a2aaacc | 12123 | return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS; |
c988af2b | 12124 | |
ab77a036 RS |
12125 | regno = true_regnum (x); |
12126 | if (TARGET_MIPS16) | |
12127 | { | |
12128 | /* In MIPS16 mode, every move must involve a member of M16_REGS. */ | |
0a2aaacc | 12129 | if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno)) |
ab77a036 | 12130 | return M16_REGS; |
c988af2b | 12131 | |
ab77a036 RS |
12132 | return NO_REGS; |
12133 | } | |
c988af2b | 12134 | |
ab77a036 RS |
12135 | /* Copying from accumulator registers to anywhere other than a general |
12136 | register requires a temporary general register. */ | |
0a2aaacc | 12137 | if (reg_class_subset_p (rclass, ACC_REGS)) |
ab77a036 RS |
12138 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; |
12139 | if (ACC_REG_P (regno)) | |
0a2aaacc | 12140 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
c988af2b | 12141 | |
0a2aaacc | 12142 | if (reg_class_subset_p (rclass, FP_REGS)) |
ab77a036 | 12143 | { |
99a5c6b0 MF |
12144 | if (regno < 0 |
12145 | || (MEM_P (x) | |
12146 | && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))) | |
ab77a036 RS |
12147 | /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use |
12148 | pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */ | |
12149 | return NO_REGS; | |
c988af2b | 12150 | |
ab77a036 RS |
12151 | if (GP_REG_P (regno) || x == CONST0_RTX (mode)) |
12152 | /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */ | |
12153 | return NO_REGS; | |
c988af2b | 12154 | |
fbbf66e7 | 12155 | if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x)) |
ab77a036 RS |
12156 | /* We can force the constant to memory and use lwc1 |
12157 | and ldc1. As above, we will use pairs of lwc1s if | |
12158 | ldc1 is not supported. */ | |
12159 | return NO_REGS; | |
12160 | ||
12161 | if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode)) | |
12162 | /* In this case we can use mov.fmt. */ | |
12163 | return NO_REGS; | |
12164 | ||
12165 | /* Otherwise, we need to reload through an integer register. */ | |
12166 | return GR_REGS; | |
c988af2b | 12167 | } |
ab77a036 | 12168 | if (FP_REG_P (regno)) |
0a2aaacc | 12169 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 RS |
12170 | |
12171 | return NO_REGS; | |
c988af2b RS |
12172 | } |
12173 | ||
65239d20 | 12174 | /* Implement TARGET_MODE_REP_EXTENDED. */ |
c988af2b | 12175 | |
ab77a036 | 12176 | static int |
ef4bddc2 | 12177 | mips_mode_rep_extended (machine_mode mode, machine_mode mode_rep) |
ab77a036 | 12178 | { |
65239d20 | 12179 | /* On 64-bit targets, SImode register values are sign-extended to DImode. */ |
ab77a036 RS |
12180 | if (TARGET_64BIT && mode == SImode && mode_rep == DImode) |
12181 | return SIGN_EXTEND; | |
c988af2b | 12182 | |
ab77a036 RS |
12183 | return UNKNOWN; |
12184 | } | |
65239d20 RS |
12185 | \f |
12186 | /* Implement TARGET_VALID_POINTER_MODE. */ | |
c988af2b | 12187 | |
ab77a036 | 12188 | static bool |
ef4bddc2 | 12189 | mips_valid_pointer_mode (machine_mode mode) |
ab77a036 | 12190 | { |
65239d20 | 12191 | return mode == SImode || (TARGET_64BIT && mode == DImode); |
ab77a036 | 12192 | } |
c988af2b | 12193 | |
65239d20 | 12194 | /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */ |
c988af2b RS |
12195 | |
12196 | static bool | |
ef4bddc2 | 12197 | mips_vector_mode_supported_p (machine_mode mode) |
c988af2b | 12198 | { |
ab77a036 RS |
12199 | switch (mode) |
12200 | { | |
12201 | case V2SFmode: | |
12202 | return TARGET_PAIRED_SINGLE_FLOAT; | |
c988af2b | 12203 | |
ab77a036 RS |
12204 | case V2HImode: |
12205 | case V4QImode: | |
12206 | case V2HQmode: | |
12207 | case V2UHQmode: | |
12208 | case V2HAmode: | |
12209 | case V2UHAmode: | |
12210 | case V4QQmode: | |
12211 | case V4UQQmode: | |
12212 | return TARGET_DSP; | |
c988af2b | 12213 | |
93581857 MS |
12214 | case V2SImode: |
12215 | case V4HImode: | |
12216 | case V8QImode: | |
12217 | return TARGET_LOONGSON_VECTORS; | |
12218 | ||
ab77a036 RS |
12219 | default: |
12220 | return false; | |
12221 | } | |
12222 | } | |
c988af2b | 12223 | |
ab77a036 | 12224 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ |
c988af2b | 12225 | |
ab77a036 | 12226 | static bool |
ef4bddc2 | 12227 | mips_scalar_mode_supported_p (machine_mode mode) |
c988af2b | 12228 | { |
ab77a036 RS |
12229 | if (ALL_FIXED_POINT_MODE_P (mode) |
12230 | && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) | |
12231 | return true; | |
c988af2b | 12232 | |
ab77a036 | 12233 | return default_scalar_mode_supported_p (mode); |
c988af2b | 12234 | } |
65239d20 | 12235 | \f |
cc4b5170 | 12236 | /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ |
26983c22 | 12237 | |
ef4bddc2 RS |
12238 | static machine_mode |
12239 | mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED) | |
26983c22 | 12240 | { |
cc4b5170 RG |
12241 | if (TARGET_PAIRED_SINGLE_FLOAT |
12242 | && mode == SFmode) | |
12243 | return V2SFmode; | |
12244 | return word_mode; | |
26983c22 L |
12245 | } |
12246 | ||
65239d20 | 12247 | /* Implement TARGET_INIT_LIBFUNCS. */ |
c988af2b | 12248 | |
ab77a036 RS |
12249 | static void |
12250 | mips_init_libfuncs (void) | |
33563487 | 12251 | { |
ab77a036 | 12252 | if (TARGET_FIX_VR4120) |
c6e6f5c1 | 12253 | { |
65239d20 RS |
12254 | /* Register the special divsi3 and modsi3 functions needed to work |
12255 | around VR4120 division errata. */ | |
ab77a036 RS |
12256 | set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); |
12257 | set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); | |
33563487 JW |
12258 | } |
12259 | ||
ab77a036 | 12260 | if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI) |
a38e0142 | 12261 | { |
65239d20 | 12262 | /* Register the MIPS16 -mhard-float stubs. */ |
ab77a036 RS |
12263 | set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3"); |
12264 | set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3"); | |
12265 | set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3"); | |
12266 | set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3"); | |
c988af2b | 12267 | |
ab77a036 RS |
12268 | set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2"); |
12269 | set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2"); | |
12270 | set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2"); | |
12271 | set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2"); | |
12272 | set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2"); | |
12273 | set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2"); | |
12274 | set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2"); | |
c988af2b | 12275 | |
ab77a036 RS |
12276 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi"); |
12277 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf"); | |
12278 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf"); | |
293a36eb | 12279 | |
ab77a036 RS |
12280 | if (TARGET_DOUBLE_FLOAT) |
12281 | { | |
12282 | set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3"); | |
12283 | set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3"); | |
12284 | set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3"); | |
12285 | set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3"); | |
293a36eb | 12286 | |
ab77a036 RS |
12287 | set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2"); |
12288 | set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2"); | |
12289 | set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2"); | |
12290 | set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2"); | |
12291 | set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2"); | |
12292 | set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2"); | |
12293 | set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2"); | |
293a36eb | 12294 | |
65239d20 RS |
12295 | set_conv_libfunc (sext_optab, DFmode, SFmode, |
12296 | "__mips16_extendsfdf2"); | |
12297 | set_conv_libfunc (trunc_optab, SFmode, DFmode, | |
12298 | "__mips16_truncdfsf2"); | |
12299 | set_conv_libfunc (sfix_optab, SImode, DFmode, | |
12300 | "__mips16_fix_truncdfsi"); | |
12301 | set_conv_libfunc (sfloat_optab, DFmode, SImode, | |
12302 | "__mips16_floatsidf"); | |
12303 | set_conv_libfunc (ufloat_optab, DFmode, SImode, | |
12304 | "__mips16_floatunsidf"); | |
ab77a036 | 12305 | } |
0310e537 | 12306 | } |
e2ff10a9 RS |
12307 | |
12308 | /* The MIPS16 ISA does not have an encoding for "sync", so we rely | |
722d8b7b RH |
12309 | on an external non-MIPS16 routine to implement __sync_synchronize. |
12310 | Similarly for the rest of the ll/sc libfuncs. */ | |
e2ff10a9 | 12311 | if (TARGET_MIPS16) |
722d8b7b RH |
12312 | { |
12313 | synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); | |
12314 | init_sync_libfuncs (UNITS_PER_WORD); | |
12315 | } | |
6cdd5672 RH |
12316 | } |
12317 | ||
0c433c31 RS |
12318 | /* Build up a multi-insn sequence that loads label TARGET into $AT. */ |
12319 | ||
12320 | static void | |
12321 | mips_process_load_label (rtx target) | |
12322 | { | |
12323 | rtx base, gp, intop; | |
12324 | HOST_WIDE_INT offset; | |
12325 | ||
12326 | mips_multi_start (); | |
12327 | switch (mips_abi) | |
12328 | { | |
12329 | case ABI_N32: | |
12330 | mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0); | |
12331 | mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
12332 | break; | |
12333 | ||
12334 | case ABI_64: | |
12335 | mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0); | |
12336 | mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
12337 | break; | |
12338 | ||
12339 | default: | |
12340 | gp = pic_offset_table_rtx; | |
12341 | if (mips_cfun_has_cprestore_slot_p ()) | |
12342 | { | |
12343 | gp = gen_rtx_REG (Pmode, AT_REGNUM); | |
12344 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
12345 | if (!SMALL_OPERAND (offset)) | |
12346 | { | |
12347 | intop = GEN_INT (CONST_HIGH_PART (offset)); | |
12348 | mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0); | |
12349 | mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0); | |
12350 | ||
12351 | base = gp; | |
12352 | offset = CONST_LOW_PART (offset); | |
12353 | } | |
12354 | intop = GEN_INT (offset); | |
12355 | if (ISA_HAS_LOAD_DELAY) | |
12356 | mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0); | |
12357 | else | |
12358 | mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0); | |
12359 | } | |
12360 | if (ISA_HAS_LOAD_DELAY) | |
12361 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0); | |
12362 | else | |
12363 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0); | |
12364 | mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0); | |
12365 | break; | |
12366 | } | |
12367 | } | |
12368 | ||
12369 | /* Return the number of instructions needed to load a label into $AT. */ | |
12370 | ||
12371 | static unsigned int | |
5a486834 | 12372 | mips_load_label_num_insns (void) |
0c433c31 | 12373 | { |
5a486834 | 12374 | if (cfun->machine->load_label_num_insns == 0) |
0c433c31 RS |
12375 | { |
12376 | mips_process_load_label (pc_rtx); | |
5a486834 | 12377 | cfun->machine->load_label_num_insns = mips_multi_num_insns; |
0c433c31 | 12378 | } |
5a486834 | 12379 | return cfun->machine->load_label_num_insns; |
0c433c31 RS |
12380 | } |
12381 | ||
12382 | /* Emit an asm sequence to start a noat block and load the address | |
12383 | of a label into $1. */ | |
12384 | ||
12385 | void | |
12386 | mips_output_load_label (rtx target) | |
12387 | { | |
12388 | mips_push_asm_switch (&mips_noat); | |
12389 | if (TARGET_EXPLICIT_RELOCS) | |
12390 | { | |
12391 | mips_process_load_label (target); | |
12392 | mips_multi_write (); | |
12393 | } | |
12394 | else | |
12395 | { | |
12396 | if (Pmode == DImode) | |
12397 | output_asm_insn ("dla\t%@,%0", &target); | |
12398 | else | |
12399 | output_asm_insn ("la\t%@,%0", &target); | |
12400 | } | |
12401 | } | |
12402 | ||
ab77a036 RS |
12403 | /* Return the length of INSN. LENGTH is the initial length computed by |
12404 | attributes in the machine-description file. */ | |
97ab1175 | 12405 | |
ab77a036 | 12406 | int |
c6f971f4 | 12407 | mips_adjust_insn_length (rtx_insn *insn, int length) |
cff9f8d5 | 12408 | { |
0c433c31 RS |
12409 | /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length |
12410 | of a PIC long-branch sequence. Substitute the correct value. */ | |
12411 | if (length == MAX_PIC_BRANCH_LENGTH | |
cfbf3ee8 | 12412 | && JUMP_P (insn) |
0c433c31 RS |
12413 | && INSN_CODE (insn) >= 0 |
12414 | && get_attr_type (insn) == TYPE_BRANCH) | |
12415 | { | |
12416 | /* Add the branch-over instruction and its delay slot, if this | |
12417 | is a conditional branch. */ | |
12418 | length = simplejump_p (insn) ? 0 : 8; | |
12419 | ||
da734fa1 RS |
12420 | /* Add the size of a load into $AT. */ |
12421 | length += BASE_INSN_LENGTH * mips_load_label_num_insns (); | |
12422 | ||
12423 | /* Add the length of an indirect jump, ignoring the delay slot. */ | |
12424 | length += TARGET_COMPRESSION ? 2 : 4; | |
0c433c31 RS |
12425 | } |
12426 | ||
ab77a036 RS |
12427 | /* A unconditional jump has an unfilled delay slot if it is not part |
12428 | of a sequence. A conditional jump normally has a delay slot, but | |
12429 | does not on MIPS16. */ | |
12430 | if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn))) | |
da734fa1 | 12431 | length += TARGET_MIPS16 ? 2 : 4; |
6f428062 | 12432 | |
ab77a036 | 12433 | /* See how many nops might be needed to avoid hardware hazards. */ |
cfbf3ee8 RS |
12434 | if (!cfun->machine->ignore_hazard_length_p |
12435 | && INSN_P (insn) | |
12436 | && INSN_CODE (insn) >= 0) | |
ab77a036 RS |
12437 | switch (get_attr_hazard (insn)) |
12438 | { | |
12439 | case HAZARD_NONE: | |
12440 | break; | |
6f428062 | 12441 | |
ab77a036 | 12442 | case HAZARD_DELAY: |
da734fa1 | 12443 | length += NOP_INSN_LENGTH; |
ab77a036 | 12444 | break; |
6f428062 | 12445 | |
ab77a036 | 12446 | case HAZARD_HILO: |
da734fa1 | 12447 | length += NOP_INSN_LENGTH * 2; |
ab77a036 RS |
12448 | break; |
12449 | } | |
3d30741b | 12450 | |
ab77a036 | 12451 | return length; |
cff9f8d5 AH |
12452 | } |
12453 | ||
ab77a036 | 12454 | /* Return the assembly code for INSN, which has the operands given by |
0c433c31 RS |
12455 | OPERANDS, and which branches to OPERANDS[0] if some condition is true. |
12456 | BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0] | |
ab77a036 RS |
12457 | is in range of a direct branch. BRANCH_IF_FALSE is an inverted |
12458 | version of BRANCH_IF_TRUE. */ | |
a6008bd8 | 12459 | |
ab77a036 | 12460 | const char * |
c6f971f4 | 12461 | mips_output_conditional_branch (rtx_insn *insn, rtx *operands, |
ab77a036 RS |
12462 | const char *branch_if_true, |
12463 | const char *branch_if_false) | |
a6008bd8 | 12464 | { |
ab77a036 | 12465 | unsigned int length; |
19f8b229 | 12466 | rtx taken; |
a6008bd8 | 12467 | |
0c433c31 | 12468 | gcc_assert (LABEL_P (operands[0])); |
4cba945d | 12469 | |
ab77a036 RS |
12470 | length = get_attr_length (insn); |
12471 | if (length <= 8) | |
12472 | { | |
12473 | /* Just a simple conditional branch. */ | |
12474 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
12475 | return branch_if_true; | |
12476 | } | |
a6008bd8 | 12477 | |
ab77a036 RS |
12478 | /* Generate a reversed branch around a direct jump. This fallback does |
12479 | not use branch-likely instructions. */ | |
12480 | mips_branch_likely = false; | |
19f8b229 | 12481 | rtx_code_label *not_taken = gen_label_rtx (); |
0c433c31 | 12482 | taken = operands[0]; |
2bcb2ab3 | 12483 | |
ab77a036 | 12484 | /* Generate the reversed branch to NOT_TAKEN. */ |
0c433c31 | 12485 | operands[0] = not_taken; |
ab77a036 | 12486 | output_asm_insn (branch_if_false, operands); |
3d30741b | 12487 | |
ab77a036 RS |
12488 | /* If INSN has a delay slot, we must provide delay slots for both the |
12489 | branch to NOT_TAKEN and the conditional jump. We must also ensure | |
12490 | that INSN's delay slot is executed in the appropriate cases. */ | |
12491 | if (final_sequence) | |
a6008bd8 | 12492 | { |
ab77a036 RS |
12493 | /* This first delay slot will always be executed, so use INSN's |
12494 | delay slot if is not annulled. */ | |
12495 | if (!INSN_ANNULLED_BRANCH_P (insn)) | |
12496 | { | |
7fa55ff6 | 12497 | final_scan_insn (final_sequence->insn (1), |
ab77a036 | 12498 | asm_out_file, optimize, 1, NULL); |
4654c0cf | 12499 | final_sequence->insn (1)->set_deleted (); |
ab77a036 RS |
12500 | } |
12501 | else | |
12502 | output_asm_insn ("nop", 0); | |
12503 | fprintf (asm_out_file, "\n"); | |
a6008bd8 | 12504 | } |
cafe096b | 12505 | |
ab77a036 | 12506 | /* Output the unconditional branch to TAKEN. */ |
0c433c31 RS |
12507 | if (TARGET_ABSOLUTE_JUMPS) |
12508 | output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken); | |
ab77a036 | 12509 | else |
b8eb88d0 | 12510 | { |
0c433c31 | 12511 | mips_output_load_label (taken); |
ab77a036 | 12512 | output_asm_insn ("jr\t%@%]%/", 0); |
b8eb88d0 ILT |
12513 | } |
12514 | ||
ab77a036 RS |
12515 | /* Now deal with its delay slot; see above. */ |
12516 | if (final_sequence) | |
8214bf98 | 12517 | { |
ab77a036 RS |
12518 | /* This delay slot will only be executed if the branch is taken. |
12519 | Use INSN's delay slot if is annulled. */ | |
12520 | if (INSN_ANNULLED_BRANCH_P (insn)) | |
12521 | { | |
7fa55ff6 | 12522 | final_scan_insn (final_sequence->insn (1), |
ab77a036 | 12523 | asm_out_file, optimize, 1, NULL); |
4654c0cf | 12524 | final_sequence->insn (1)->set_deleted (); |
ab77a036 RS |
12525 | } |
12526 | else | |
12527 | output_asm_insn ("nop", 0); | |
12528 | fprintf (asm_out_file, "\n"); | |
2bcb2ab3 GK |
12529 | } |
12530 | ||
ab77a036 | 12531 | /* Output NOT_TAKEN. */ |
65239d20 RS |
12532 | targetm.asm_out.internal_label (asm_out_file, "L", |
12533 | CODE_LABEL_NUMBER (not_taken)); | |
ab77a036 | 12534 | return ""; |
46299de9 | 12535 | } |
d604bca3 | 12536 | |
0c433c31 | 12537 | /* Return the assembly code for INSN, which branches to OPERANDS[0] |
65239d20 | 12538 | if some ordering condition is true. The condition is given by |
0c433c31 RS |
12539 | OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of |
12540 | OPERANDS[1]. OPERANDS[2] is the comparison's first operand; | |
ab77a036 | 12541 | its second is always zero. */ |
4977bab6 | 12542 | |
ab77a036 | 12543 | const char * |
c6f971f4 | 12544 | mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands, bool inverted_p) |
4977bab6 | 12545 | { |
ab77a036 | 12546 | const char *branch[2]; |
62d9f2e9 | 12547 | |
0c433c31 | 12548 | /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true. |
ab77a036 | 12549 | Make BRANCH[0] branch on the inverse condition. */ |
0c433c31 | 12550 | switch (GET_CODE (operands[1])) |
118ea793 | 12551 | { |
ab77a036 RS |
12552 | /* These cases are equivalent to comparisons against zero. */ |
12553 | case LEU: | |
12554 | inverted_p = !inverted_p; | |
12555 | /* Fall through. */ | |
12556 | case GTU: | |
0c433c31 RS |
12557 | branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0"); |
12558 | branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0"); | |
ab77a036 | 12559 | break; |
118ea793 | 12560 | |
ab77a036 RS |
12561 | /* These cases are always true or always false. */ |
12562 | case LTU: | |
12563 | inverted_p = !inverted_p; | |
12564 | /* Fall through. */ | |
12565 | case GEU: | |
0c433c31 RS |
12566 | branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0"); |
12567 | branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0"); | |
ab77a036 | 12568 | break; |
118ea793 CF |
12569 | |
12570 | default: | |
0c433c31 RS |
12571 | branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0"); |
12572 | branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0"); | |
ab77a036 | 12573 | break; |
118ea793 | 12574 | } |
ab77a036 | 12575 | return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); |
06a4ab70 | 12576 | } |
ab77a036 | 12577 | \f |
6f5a62e9 RS |
12578 | /* Start a block of code that needs access to the LL, SC and SYNC |
12579 | instructions. */ | |
12580 | ||
12581 | static void | |
12582 | mips_start_ll_sc_sync_block (void) | |
12583 | { | |
12584 | if (!ISA_HAS_LL_SC) | |
12585 | { | |
12586 | output_asm_insn (".set\tpush", 0); | |
b259d352 JU |
12587 | if (TARGET_64BIT) |
12588 | output_asm_insn (".set\tmips3", 0); | |
12589 | else | |
12590 | output_asm_insn (".set\tmips2", 0); | |
6f5a62e9 RS |
12591 | } |
12592 | } | |
12593 | ||
12594 | /* End a block started by mips_start_ll_sc_sync_block. */ | |
12595 | ||
12596 | static void | |
12597 | mips_end_ll_sc_sync_block (void) | |
12598 | { | |
12599 | if (!ISA_HAS_LL_SC) | |
12600 | output_asm_insn (".set\tpop", 0); | |
12601 | } | |
12602 | ||
12603 | /* Output and/or return the asm template for a sync instruction. */ | |
ee9a72e5 JK |
12604 | |
12605 | const char * | |
6f5a62e9 | 12606 | mips_output_sync (void) |
ee9a72e5 | 12607 | { |
6f5a62e9 RS |
12608 | mips_start_ll_sc_sync_block (); |
12609 | output_asm_insn ("sync", 0); | |
12610 | mips_end_ll_sc_sync_block (); | |
12611 | return ""; | |
12612 | } | |
40a4a37b | 12613 | |
6f5a62e9 RS |
12614 | /* Return the asm template associated with sync_insn1 value TYPE. |
12615 | IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */ | |
068ca03a | 12616 | |
6f5a62e9 RS |
12617 | static const char * |
12618 | mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p) | |
12619 | { | |
12620 | switch (type) | |
12621 | { | |
12622 | case SYNC_INSN1_MOVE: | |
12623 | return "move\t%0,%z2"; | |
12624 | case SYNC_INSN1_LI: | |
12625 | return "li\t%0,%2"; | |
12626 | case SYNC_INSN1_ADDU: | |
12627 | return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2"; | |
12628 | case SYNC_INSN1_ADDIU: | |
12629 | return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2"; | |
12630 | case SYNC_INSN1_SUBU: | |
12631 | return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2"; | |
12632 | case SYNC_INSN1_AND: | |
12633 | return "and\t%0,%1,%z2"; | |
12634 | case SYNC_INSN1_ANDI: | |
12635 | return "andi\t%0,%1,%2"; | |
12636 | case SYNC_INSN1_OR: | |
12637 | return "or\t%0,%1,%z2"; | |
12638 | case SYNC_INSN1_ORI: | |
12639 | return "ori\t%0,%1,%2"; | |
12640 | case SYNC_INSN1_XOR: | |
12641 | return "xor\t%0,%1,%z2"; | |
12642 | case SYNC_INSN1_XORI: | |
12643 | return "xori\t%0,%1,%2"; | |
12644 | } | |
12645 | gcc_unreachable (); | |
12646 | } | |
12647 | ||
12648 | /* Return the asm template associated with sync_insn2 value TYPE. */ | |
12649 | ||
12650 | static const char * | |
12651 | mips_sync_insn2_template (enum attr_sync_insn2 type) | |
12652 | { | |
12653 | switch (type) | |
12654 | { | |
12655 | case SYNC_INSN2_NOP: | |
12656 | gcc_unreachable (); | |
12657 | case SYNC_INSN2_AND: | |
12658 | return "and\t%0,%1,%z2"; | |
12659 | case SYNC_INSN2_XOR: | |
12660 | return "xor\t%0,%1,%z2"; | |
12661 | case SYNC_INSN2_NOT: | |
12662 | return "nor\t%0,%1,%."; | |
12663 | } | |
12664 | gcc_unreachable (); | |
12665 | } | |
12666 | ||
12667 | /* OPERANDS are the operands to a sync loop instruction and INDEX is | |
12668 | the value of the one of the sync_* attributes. Return the operand | |
12669 | referred to by the attribute, or DEFAULT_VALUE if the insn doesn't | |
12670 | have the associated attribute. */ | |
12671 | ||
12672 | static rtx | |
12673 | mips_get_sync_operand (rtx *operands, int index, rtx default_value) | |
12674 | { | |
12675 | if (index > 0) | |
12676 | default_value = operands[index - 1]; | |
12677 | return default_value; | |
12678 | } | |
12679 | ||
12680 | /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn | |
12681 | sequence for it. */ | |
12682 | ||
12683 | static void | |
84034c69 | 12684 | mips_process_sync_loop (rtx_insn *insn, rtx *operands) |
6f5a62e9 RS |
12685 | { |
12686 | rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask; | |
01c196ea | 12687 | rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp; |
6f5a62e9 RS |
12688 | unsigned int tmp3_insn; |
12689 | enum attr_sync_insn1 insn1; | |
12690 | enum attr_sync_insn2 insn2; | |
12691 | bool is_64bit_p; | |
01c196ea TV |
12692 | int memmodel_attr; |
12693 | enum memmodel model; | |
6f5a62e9 RS |
12694 | |
12695 | /* Read an operand from the sync_WHAT attribute and store it in | |
12696 | variable WHAT. DEFAULT is the default value if no attribute | |
12697 | is specified. */ | |
12698 | #define READ_OPERAND(WHAT, DEFAULT) \ | |
12699 | WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \ | |
12700 | DEFAULT) | |
12701 | ||
12702 | /* Read the memory. */ | |
12703 | READ_OPERAND (mem, 0); | |
12704 | gcc_assert (mem); | |
12705 | is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64); | |
12706 | ||
12707 | /* Read the other attributes. */ | |
12708 | at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM); | |
12709 | READ_OPERAND (oldval, at); | |
01c196ea | 12710 | READ_OPERAND (cmp, 0); |
6f5a62e9 RS |
12711 | READ_OPERAND (newval, at); |
12712 | READ_OPERAND (inclusive_mask, 0); | |
12713 | READ_OPERAND (exclusive_mask, 0); | |
12714 | READ_OPERAND (required_oldval, 0); | |
12715 | READ_OPERAND (insn1_op2, 0); | |
12716 | insn1 = get_attr_sync_insn1 (insn); | |
12717 | insn2 = get_attr_sync_insn2 (insn); | |
12718 | ||
ff619148 MK |
12719 | /* Don't bother setting CMP result that is never used. */ |
12720 | if (cmp && find_reg_note (insn, REG_UNUSED, cmp)) | |
12721 | cmp = 0; | |
12722 | ||
01c196ea TV |
12723 | memmodel_attr = get_attr_sync_memmodel (insn); |
12724 | switch (memmodel_attr) | |
12725 | { | |
12726 | case 10: | |
12727 | model = MEMMODEL_ACQ_REL; | |
12728 | break; | |
12729 | case 11: | |
12730 | model = MEMMODEL_ACQUIRE; | |
12731 | break; | |
12732 | default: | |
636da826 | 12733 | model = (enum memmodel) INTVAL (operands[memmodel_attr]); |
01c196ea TV |
12734 | } |
12735 | ||
6f5a62e9 RS |
12736 | mips_multi_start (); |
12737 | ||
12738 | /* Output the release side of the memory barrier. */ | |
8930883e | 12739 | if (need_atomic_barrier_p (model, true)) |
916e9b31 DD |
12740 | { |
12741 | if (required_oldval == 0 && TARGET_OCTEON) | |
12742 | { | |
12743 | /* Octeon doesn't reorder reads, so a full barrier can be | |
12744 | created by using SYNCW to order writes combined with the | |
12745 | write from the following SC. When the SC successfully | |
12746 | completes, we know that all preceding writes are also | |
12747 | committed to the coherent memory system. It is possible | |
12748 | for a single SYNCW to fail, but a pair of them will never | |
12749 | fail, so we use two. */ | |
12750 | mips_multi_add_insn ("syncw", NULL); | |
12751 | mips_multi_add_insn ("syncw", NULL); | |
12752 | } | |
12753 | else | |
12754 | mips_multi_add_insn ("sync", NULL); | |
12755 | } | |
6f5a62e9 RS |
12756 | |
12757 | /* Output the branch-back label. */ | |
12758 | mips_multi_add_label ("1:"); | |
12759 | ||
12760 | /* OLDVAL = *MEM. */ | |
12761 | mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1", | |
12762 | oldval, mem, NULL); | |
12763 | ||
12764 | /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */ | |
12765 | if (required_oldval) | |
12766 | { | |
12767 | if (inclusive_mask == 0) | |
12768 | tmp1 = oldval; | |
12769 | else | |
12770 | { | |
12771 | gcc_assert (oldval != at); | |
12772 | mips_multi_add_insn ("and\t%0,%1,%2", | |
12773 | at, oldval, inclusive_mask, NULL); | |
12774 | tmp1 = at; | |
12775 | } | |
12776 | mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL); | |
01c196ea TV |
12777 | |
12778 | /* CMP = 0 [delay slot]. */ | |
12779 | if (cmp) | |
12780 | mips_multi_add_insn ("li\t%0,0", cmp, NULL); | |
6f5a62e9 RS |
12781 | } |
12782 | ||
12783 | /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */ | |
12784 | if (exclusive_mask == 0) | |
12785 | tmp1 = const0_rtx; | |
12786 | else | |
12787 | { | |
12788 | gcc_assert (oldval != at); | |
12789 | mips_multi_add_insn ("and\t%0,%1,%z2", | |
12790 | at, oldval, exclusive_mask, NULL); | |
12791 | tmp1 = at; | |
12792 | } | |
12793 | ||
12794 | /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2). | |
12795 | ||
12796 | We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit | |
12797 | at least one instruction in that case. */ | |
12798 | if (insn1 == SYNC_INSN1_MOVE | |
12799 | && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP)) | |
12800 | tmp2 = insn1_op2; | |
12801 | else | |
068ca03a | 12802 | { |
6f5a62e9 RS |
12803 | mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p), |
12804 | newval, oldval, insn1_op2, NULL); | |
12805 | tmp2 = newval; | |
068ca03a | 12806 | } |
6f5a62e9 RS |
12807 | |
12808 | /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */ | |
12809 | if (insn2 == SYNC_INSN2_NOP) | |
12810 | tmp3 = tmp2; | |
12811 | else | |
12812 | { | |
12813 | mips_multi_add_insn (mips_sync_insn2_template (insn2), | |
12814 | newval, tmp2, inclusive_mask, NULL); | |
12815 | tmp3 = newval; | |
12816 | } | |
12817 | tmp3_insn = mips_multi_last_index (); | |
12818 | ||
12819 | /* $AT = $TMP1 | $TMP3. */ | |
12820 | if (tmp1 == const0_rtx || tmp3 == const0_rtx) | |
12821 | { | |
12822 | mips_multi_set_operand (tmp3_insn, 0, at); | |
12823 | tmp3 = at; | |
12824 | } | |
12825 | else | |
12826 | { | |
12827 | gcc_assert (tmp1 != tmp3); | |
12828 | mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL); | |
12829 | } | |
12830 | ||
12831 | /* if (!commit (*MEM = $AT)) goto 1. | |
12832 | ||
12833 | This will sometimes be a delayed branch; see the write code below | |
12834 | for details. */ | |
12835 | mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); | |
12836 | mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); | |
12837 | ||
12838 | /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ | |
12839 | if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) | |
12840 | { | |
12841 | mips_multi_copy_insn (tmp3_insn); | |
12842 | mips_multi_set_operand (mips_multi_last_index (), 0, newval); | |
12843 | } | |
01c196ea | 12844 | else if (!(required_oldval && cmp)) |
6f5a62e9 RS |
12845 | mips_multi_add_insn ("nop", NULL); |
12846 | ||
01c196ea TV |
12847 | /* CMP = 1 -- either standalone or in a delay slot. */ |
12848 | if (required_oldval && cmp) | |
12849 | mips_multi_add_insn ("li\t%0,1", cmp, NULL); | |
12850 | ||
6f5a62e9 | 12851 | /* Output the acquire side of the memory barrier. */ |
8930883e | 12852 | if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false)) |
6f5a62e9 RS |
12853 | mips_multi_add_insn ("sync", NULL); |
12854 | ||
12855 | /* Output the exit label, if needed. */ | |
12856 | if (required_oldval) | |
12857 | mips_multi_add_label ("2:"); | |
12858 | ||
12859 | #undef READ_OPERAND | |
12860 | } | |
12861 | ||
12862 | /* Output and/or return the asm template for sync loop INSN, which has | |
12863 | the operands given by OPERANDS. */ | |
12864 | ||
12865 | const char * | |
84034c69 | 12866 | mips_output_sync_loop (rtx_insn *insn, rtx *operands) |
6f5a62e9 RS |
12867 | { |
12868 | mips_process_sync_loop (insn, operands); | |
12869 | ||
12870 | /* Use branch-likely instructions to work around the LL/SC R10000 | |
12871 | errata. */ | |
12872 | mips_branch_likely = TARGET_FIX_R10000; | |
12873 | ||
12874 | mips_push_asm_switch (&mips_noreorder); | |
12875 | mips_push_asm_switch (&mips_nomacro); | |
12876 | mips_push_asm_switch (&mips_noat); | |
12877 | mips_start_ll_sc_sync_block (); | |
12878 | ||
12879 | mips_multi_write (); | |
12880 | ||
12881 | mips_end_ll_sc_sync_block (); | |
12882 | mips_pop_asm_switch (&mips_noat); | |
12883 | mips_pop_asm_switch (&mips_nomacro); | |
12884 | mips_pop_asm_switch (&mips_noreorder); | |
12885 | ||
12886 | return ""; | |
12887 | } | |
12888 | ||
12889 | /* Return the number of individual instructions in sync loop INSN, | |
12890 | which has the operands given by OPERANDS. */ | |
12891 | ||
12892 | unsigned int | |
84034c69 | 12893 | mips_sync_loop_insns (rtx_insn *insn, rtx *operands) |
6f5a62e9 RS |
12894 | { |
12895 | mips_process_sync_loop (insn, operands); | |
12896 | return mips_multi_num_insns; | |
ee9a72e5 JK |
12897 | } |
12898 | \f | |
65239d20 RS |
12899 | /* Return the assembly code for DIV or DDIV instruction DIVISION, which has |
12900 | the operands given by OPERANDS. Add in a divide-by-zero check if needed. | |
9fc777ad | 12901 | |
ab77a036 RS |
12902 | When working around R4000 and R4400 errata, we need to make sure that |
12903 | the division is not immediately followed by a shift[1][2]. We also | |
12904 | need to stop the division from being put into a branch delay slot[3]. | |
12905 | The easiest way to avoid both problems is to add a nop after the | |
12906 | division. When a divide-by-zero check is needed, this nop can be | |
12907 | used to fill the branch delay slot. | |
9fc777ad | 12908 | |
ab77a036 RS |
12909 | [1] If a double-word or a variable shift executes immediately |
12910 | after starting an integer division, the shift may give an | |
12911 | incorrect result. See quotations of errata #16 and #28 from | |
12912 | "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" | |
12913 | in mips.md for details. | |
9fc777ad | 12914 | |
ab77a036 RS |
12915 | [2] A similar bug to [1] exists for all revisions of the |
12916 | R4000 and the R4400 when run in an MC configuration. | |
12917 | From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0": | |
d34053ed | 12918 | |
ab77a036 | 12919 | "19. In this following sequence: |
2bcb2ab3 | 12920 | |
ab77a036 RS |
12921 | ddiv (or ddivu or div or divu) |
12922 | dsll32 (or dsrl32, dsra32) | |
d6076cee | 12923 | |
ab77a036 RS |
12924 | if an MPT stall occurs, while the divide is slipping the cpu |
12925 | pipeline, then the following double shift would end up with an | |
12926 | incorrect result. | |
2bcb2ab3 | 12927 | |
ab77a036 RS |
12928 | Workaround: The compiler needs to avoid generating any |
12929 | sequence with divide followed by extended double shift." | |
2bcb2ab3 | 12930 | |
ab77a036 RS |
12931 | This erratum is also present in "MIPS R4400MC Errata, Processor |
12932 | Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0 | |
12933 | & 3.0" as errata #10 and #4, respectively. | |
2bcb2ab3 | 12934 | |
ab77a036 RS |
12935 | [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" |
12936 | (also valid for MIPS R4000MC processors): | |
2bcb2ab3 | 12937 | |
ab77a036 | 12938 | "52. R4000SC: This bug does not apply for the R4000PC. |
2bcb2ab3 | 12939 | |
ab77a036 | 12940 | There are two flavors of this bug: |
2bcb2ab3 | 12941 | |
ab77a036 RS |
12942 | 1) If the instruction just after divide takes an RF exception |
12943 | (tlb-refill, tlb-invalid) and gets an instruction cache | |
12944 | miss (both primary and secondary) and the line which is | |
12945 | currently in secondary cache at this index had the first | |
12946 | data word, where the bits 5..2 are set, then R4000 would | |
12947 | get a wrong result for the div. | |
a38e0142 | 12948 | |
ab77a036 RS |
12949 | ##1 |
12950 | nop | |
12951 | div r8, r9 | |
12952 | ------------------- # end-of page. -tlb-refill | |
12953 | nop | |
12954 | ##2 | |
12955 | nop | |
12956 | div r8, r9 | |
12957 | ------------------- # end-of page. -tlb-invalid | |
12958 | nop | |
a38e0142 | 12959 | |
ab77a036 RS |
12960 | 2) If the divide is in the taken branch delay slot, where the |
12961 | target takes RF exception and gets an I-cache miss for the | |
12962 | exception vector or where I-cache miss occurs for the | |
12963 | target address, under the above mentioned scenarios, the | |
12964 | div would get wrong results. | |
a38e0142 | 12965 | |
ab77a036 RS |
12966 | ##1 |
12967 | j r2 # to next page mapped or unmapped | |
12968 | div r8,r9 # this bug would be there as long | |
12969 | # as there is an ICache miss and | |
12970 | nop # the "data pattern" is present | |
2bcb2ab3 | 12971 | |
ab77a036 RS |
12972 | ##2 |
12973 | beq r0, r0, NextPage # to Next page | |
12974 | div r8,r9 | |
12975 | nop | |
a38e0142 | 12976 | |
ab77a036 RS |
12977 | This bug is present for div, divu, ddiv, and ddivu |
12978 | instructions. | |
a38e0142 | 12979 | |
ab77a036 RS |
12980 | Workaround: For item 1), OS could make sure that the next page |
12981 | after the divide instruction is also mapped. For item 2), the | |
12982 | compiler could make sure that the divide instruction is not in | |
12983 | the branch delay slot." | |
2bcb2ab3 | 12984 | |
ab77a036 RS |
12985 | These processors have PRId values of 0x00004220 and 0x00004300 for |
12986 | the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */ | |
2bcb2ab3 | 12987 | |
ab77a036 RS |
12988 | const char * |
12989 | mips_output_division (const char *division, rtx *operands) | |
2bcb2ab3 | 12990 | { |
ab77a036 | 12991 | const char *s; |
2bcb2ab3 | 12992 | |
ab77a036 RS |
12993 | s = division; |
12994 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) | |
2bcb2ab3 | 12995 | { |
ab77a036 RS |
12996 | output_asm_insn (s, operands); |
12997 | s = "nop"; | |
2bcb2ab3 | 12998 | } |
ab77a036 | 12999 | if (TARGET_CHECK_ZERO_DIV) |
3c7404d3 | 13000 | { |
ab77a036 RS |
13001 | if (TARGET_MIPS16) |
13002 | { | |
13003 | output_asm_insn (s, operands); | |
13004 | s = "bnez\t%2,1f\n\tbreak\t7\n1:"; | |
13005 | } | |
13006 | else if (GENERATE_DIVIDE_TRAPS) | |
67e67979 DU |
13007 | { |
13008 | /* Avoid long replay penalty on load miss by putting the trap before | |
13009 | the divide. */ | |
13010 | if (TUNE_74K) | |
13011 | output_asm_insn ("teq\t%2,%.,7", operands); | |
13012 | else | |
13013 | { | |
13014 | output_asm_insn (s, operands); | |
13015 | s = "teq\t%2,%.,7"; | |
13016 | } | |
13017 | } | |
ab77a036 RS |
13018 | else |
13019 | { | |
13020 | output_asm_insn ("%(bne\t%2,%.,1f", operands); | |
13021 | output_asm_insn (s, operands); | |
13022 | s = "break\t7%)\n1:"; | |
13023 | } | |
3c7404d3 | 13024 | } |
ab77a036 RS |
13025 | return s; |
13026 | } | |
13027 | \f | |
aaaa9efc JP |
13028 | /* Return true if destination of IN_INSN is used as add source in |
13029 | OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example: | |
13030 | madd.s dst, x, y, z | |
13031 | madd.s a, dst, b, c */ | |
13032 | ||
13033 | bool | |
647d790d | 13034 | mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn) |
aaaa9efc JP |
13035 | { |
13036 | int dst_reg, src_reg; | |
13037 | ||
13038 | gcc_assert (get_attr_type (in_insn) == TYPE_FMADD); | |
13039 | gcc_assert (get_attr_type (out_insn) == TYPE_FMADD); | |
13040 | ||
13041 | extract_insn (in_insn); | |
13042 | dst_reg = REG_P (recog_data.operand[0]); | |
13043 | ||
13044 | extract_insn (out_insn); | |
13045 | src_reg = REG_P (recog_data.operand[1]); | |
13046 | ||
13047 | if (dst_reg == src_reg) | |
13048 | return true; | |
13049 | ||
13050 | return false; | |
13051 | } | |
13052 | ||
65239d20 RS |
13053 | /* Return true if IN_INSN is a multiply-add or multiply-subtract |
13054 | instruction and if OUT_INSN assigns to the accumulator operand. */ | |
2bcb2ab3 | 13055 | |
ab77a036 | 13056 | bool |
647d790d | 13057 | mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn) |
ab77a036 | 13058 | { |
73590b4f MK |
13059 | enum attr_accum_in accum_in; |
13060 | int accum_in_opnum; | |
13061 | rtx accum_in_op; | |
2bcb2ab3 | 13062 | |
73590b4f | 13063 | if (recog_memoized (in_insn) < 0) |
ab77a036 | 13064 | return false; |
2bcb2ab3 | 13065 | |
73590b4f MK |
13066 | accum_in = get_attr_accum_in (in_insn); |
13067 | if (accum_in == ACCUM_IN_NONE) | |
13068 | return false; | |
2bcb2ab3 | 13069 | |
73590b4f | 13070 | accum_in_opnum = accum_in - ACCUM_IN_0; |
2bcb2ab3 | 13071 | |
73590b4f MK |
13072 | extract_insn (in_insn); |
13073 | gcc_assert (accum_in_opnum < recog_data.n_operands); | |
13074 | accum_in_op = recog_data.operand[accum_in_opnum]; | |
2bcb2ab3 | 13075 | |
73590b4f | 13076 | return reg_set_p (accum_in_op, out_insn); |
2bcb2ab3 GK |
13077 | } |
13078 | ||
65239d20 RS |
13079 | /* True if the dependency between OUT_INSN and IN_INSN is on the store |
13080 | data rather than the address. We need this because the cprestore | |
13081 | pattern is type "store", but is defined using an UNSPEC_VOLATILE, | |
13082 | which causes the default routine to abort. We just return false | |
13083 | for that case. */ | |
2bcb2ab3 | 13084 | |
65239d20 | 13085 | bool |
e8a54173 | 13086 | mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) |
2bcb2ab3 | 13087 | { |
ab77a036 RS |
13088 | if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) |
13089 | return false; | |
2bcb2ab3 | 13090 | |
65239d20 | 13091 | return !store_data_bypass_p (out_insn, in_insn); |
ab77a036 RS |
13092 | } |
13093 | \f | |
58684fa0 MK |
13094 | |
13095 | /* Variables and flags used in scheduler hooks when tuning for | |
13096 | Loongson 2E/2F. */ | |
13097 | static struct | |
13098 | { | |
13099 | /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch | |
13100 | strategy. */ | |
13101 | ||
13102 | /* If true, then next ALU1/2 instruction will go to ALU1. */ | |
13103 | bool alu1_turn_p; | |
13104 | ||
13105 | /* If true, then next FALU1/2 unstruction will go to FALU1. */ | |
13106 | bool falu1_turn_p; | |
13107 | ||
13108 | /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */ | |
13109 | int alu1_core_unit_code; | |
13110 | int alu2_core_unit_code; | |
13111 | int falu1_core_unit_code; | |
13112 | int falu2_core_unit_code; | |
13113 | ||
13114 | /* True if current cycle has a multi instruction. | |
13115 | This flag is used in mips_ls2_dfa_post_advance_cycle. */ | |
13116 | bool cycle_has_multi_p; | |
13117 | ||
13118 | /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units. | |
13119 | These are used in mips_ls2_dfa_post_advance_cycle to initialize | |
13120 | DFA state. | |
13121 | E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2 | |
13122 | instruction to go ALU1. */ | |
c6f971f4 DM |
13123 | rtx_insn *alu1_turn_enabled_insn; |
13124 | rtx_insn *alu2_turn_enabled_insn; | |
13125 | rtx_insn *falu1_turn_enabled_insn; | |
13126 | rtx_insn *falu2_turn_enabled_insn; | |
58684fa0 MK |
13127 | } mips_ls2; |
13128 | ||
ab77a036 RS |
13129 | /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output |
13130 | dependencies have no cost, except on the 20Kc where output-dependence | |
13131 | is treated like input-dependence. */ | |
2bcb2ab3 | 13132 | |
ab77a036 | 13133 | static int |
ac44248e DM |
13134 | mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link, |
13135 | rtx_insn *dep ATTRIBUTE_UNUSED, int cost) | |
ab77a036 RS |
13136 | { |
13137 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT | |
13138 | && TUNE_20KC) | |
13139 | return cost; | |
13140 | if (REG_NOTE_KIND (link) != 0) | |
13141 | return 0; | |
13142 | return cost; | |
13143 | } | |
a38e0142 | 13144 | |
ab77a036 RS |
13145 | /* Return the number of instructions that can be issued per cycle. */ |
13146 | ||
13147 | static int | |
13148 | mips_issue_rate (void) | |
a38e0142 | 13149 | { |
ab77a036 | 13150 | switch (mips_tune) |
a38e0142 | 13151 | { |
ab77a036 RS |
13152 | case PROCESSOR_74KC: |
13153 | case PROCESSOR_74KF2_1: | |
13154 | case PROCESSOR_74KF1_1: | |
13155 | case PROCESSOR_74KF3_2: | |
13156 | /* The 74k is not strictly quad-issue cpu, but can be seen as one | |
13157 | by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns, | |
65239d20 RS |
13158 | but in reality only a maximum of 3 insns can be issued as |
13159 | floating-point loads and stores also require a slot in the | |
13160 | AGEN pipe. */ | |
7a3446ec JK |
13161 | case PROCESSOR_R10000: |
13162 | /* All R10K Processors are quad-issue (being the first MIPS | |
13163 | processors to support this feature). */ | |
13164 | return 4; | |
ab77a036 RS |
13165 | |
13166 | case PROCESSOR_20KC: | |
13167 | case PROCESSOR_R4130: | |
13168 | case PROCESSOR_R5400: | |
13169 | case PROCESSOR_R5500: | |
107eea2c | 13170 | case PROCESSOR_R5900: |
ab77a036 RS |
13171 | case PROCESSOR_R7000: |
13172 | case PROCESSOR_R9000: | |
ce00be9e | 13173 | case PROCESSOR_OCTEON: |
38a53a0e | 13174 | case PROCESSOR_OCTEON2: |
ab77a036 RS |
13175 | return 2; |
13176 | ||
13177 | case PROCESSOR_SB1: | |
13178 | case PROCESSOR_SB1A: | |
13179 | /* This is actually 4, but we get better performance if we claim 3. | |
13180 | This is partly because of unwanted speculative code motion with the | |
13181 | larger number, and partly because in most common cases we can't | |
13182 | reach the theoretical max of 4. */ | |
13183 | return 3; | |
13184 | ||
58684fa0 MK |
13185 | case PROCESSOR_LOONGSON_2E: |
13186 | case PROCESSOR_LOONGSON_2F: | |
98824c6f | 13187 | case PROCESSOR_LOONGSON_3A: |
aaaa9efc | 13188 | case PROCESSOR_P5600: |
58684fa0 MK |
13189 | return 4; |
13190 | ||
eb448bee CLT |
13191 | case PROCESSOR_XLP: |
13192 | return (reload_completed ? 4 : 3); | |
13193 | ||
ab77a036 RS |
13194 | default: |
13195 | return 1; | |
a38e0142 SL |
13196 | } |
13197 | } | |
13198 | ||
58684fa0 MK |
13199 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */ |
13200 | ||
13201 | static void | |
13202 | mips_ls2_init_dfa_post_cycle_insn (void) | |
13203 | { | |
13204 | start_sequence (); | |
13205 | emit_insn (gen_ls2_alu1_turn_enabled_insn ()); | |
13206 | mips_ls2.alu1_turn_enabled_insn = get_insns (); | |
13207 | end_sequence (); | |
13208 | ||
13209 | start_sequence (); | |
13210 | emit_insn (gen_ls2_alu2_turn_enabled_insn ()); | |
13211 | mips_ls2.alu2_turn_enabled_insn = get_insns (); | |
13212 | end_sequence (); | |
13213 | ||
13214 | start_sequence (); | |
13215 | emit_insn (gen_ls2_falu1_turn_enabled_insn ()); | |
13216 | mips_ls2.falu1_turn_enabled_insn = get_insns (); | |
13217 | end_sequence (); | |
13218 | ||
13219 | start_sequence (); | |
13220 | emit_insn (gen_ls2_falu2_turn_enabled_insn ()); | |
13221 | mips_ls2.falu2_turn_enabled_insn = get_insns (); | |
13222 | end_sequence (); | |
13223 | ||
13224 | mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core"); | |
13225 | mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core"); | |
13226 | mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core"); | |
13227 | mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core"); | |
13228 | } | |
13229 | ||
13230 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook. | |
13231 | Init data used in mips_dfa_post_advance_cycle. */ | |
13232 | ||
13233 | static void | |
13234 | mips_init_dfa_post_cycle_insn (void) | |
13235 | { | |
13236 | if (TUNE_LOONGSON_2EF) | |
13237 | mips_ls2_init_dfa_post_cycle_insn (); | |
13238 | } | |
13239 | ||
13240 | /* Initialize STATE when scheduling for Loongson 2E/2F. | |
13241 | Support round-robin dispatch scheme by enabling only one of | |
13242 | ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions | |
13243 | respectively. */ | |
13244 | ||
13245 | static void | |
13246 | mips_ls2_dfa_post_advance_cycle (state_t state) | |
13247 | { | |
13248 | if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code)) | |
13249 | { | |
13250 | /* Though there are no non-pipelined ALU1 insns, | |
13251 | we can get an instruction of type 'multi' before reload. */ | |
13252 | gcc_assert (mips_ls2.cycle_has_multi_p); | |
13253 | mips_ls2.alu1_turn_p = false; | |
13254 | } | |
13255 | ||
13256 | mips_ls2.cycle_has_multi_p = false; | |
13257 | ||
13258 | if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code)) | |
13259 | /* We have a non-pipelined alu instruction in the core, | |
13260 | adjust round-robin counter. */ | |
13261 | mips_ls2.alu1_turn_p = true; | |
13262 | ||
13263 | if (mips_ls2.alu1_turn_p) | |
13264 | { | |
13265 | if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0) | |
13266 | gcc_unreachable (); | |
13267 | } | |
13268 | else | |
13269 | { | |
13270 | if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0) | |
13271 | gcc_unreachable (); | |
13272 | } | |
13273 | ||
13274 | if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code)) | |
13275 | { | |
13276 | /* There are no non-pipelined FALU1 insns. */ | |
13277 | gcc_unreachable (); | |
13278 | mips_ls2.falu1_turn_p = false; | |
13279 | } | |
13280 | ||
13281 | if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code)) | |
13282 | /* We have a non-pipelined falu instruction in the core, | |
13283 | adjust round-robin counter. */ | |
13284 | mips_ls2.falu1_turn_p = true; | |
13285 | ||
13286 | if (mips_ls2.falu1_turn_p) | |
13287 | { | |
13288 | if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0) | |
13289 | gcc_unreachable (); | |
13290 | } | |
13291 | else | |
13292 | { | |
13293 | if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0) | |
13294 | gcc_unreachable (); | |
13295 | } | |
13296 | } | |
13297 | ||
13298 | /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE. | |
13299 | This hook is being called at the start of each cycle. */ | |
13300 | ||
13301 | static void | |
13302 | mips_dfa_post_advance_cycle (void) | |
13303 | { | |
13304 | if (TUNE_LOONGSON_2EF) | |
13305 | mips_ls2_dfa_post_advance_cycle (curr_state); | |
13306 | } | |
13307 | ||
65239d20 | 13308 | /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should |
ab77a036 | 13309 | be as wide as the scheduling freedom in the DFA. */ |
2bcb2ab3 | 13310 | |
ab77a036 RS |
13311 | static int |
13312 | mips_multipass_dfa_lookahead (void) | |
13313 | { | |
13314 | /* Can schedule up to 4 of the 6 function units in any one cycle. */ | |
13315 | if (TUNE_SB1) | |
13316 | return 4; | |
2bcb2ab3 | 13317 | |
2b18eb32 | 13318 | if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) |
58684fa0 MK |
13319 | return 4; |
13320 | ||
ce00be9e AN |
13321 | if (TUNE_OCTEON) |
13322 | return 2; | |
13323 | ||
aaaa9efc JP |
13324 | if (TUNE_P5600) |
13325 | return 4; | |
13326 | ||
ab77a036 RS |
13327 | return 0; |
13328 | } | |
13329 | \f | |
13330 | /* Remove the instruction at index LOWER from ready queue READY and | |
13331 | reinsert it in front of the instruction at index HIGHER. LOWER must | |
13332 | be <= HIGHER. */ | |
2bcb2ab3 | 13333 | |
ab77a036 | 13334 | static void |
ce1ce33a | 13335 | mips_promote_ready (rtx_insn **ready, int lower, int higher) |
2bcb2ab3 | 13336 | { |
ce1ce33a | 13337 | rtx_insn *new_head; |
ab77a036 | 13338 | int i; |
2bcb2ab3 | 13339 | |
ab77a036 RS |
13340 | new_head = ready[lower]; |
13341 | for (i = lower; i < higher; i++) | |
13342 | ready[i] = ready[i + 1]; | |
13343 | ready[i] = new_head; | |
13344 | } | |
2bcb2ab3 | 13345 | |
ab77a036 RS |
13346 | /* If the priority of the instruction at POS2 in the ready queue READY |
13347 | is within LIMIT units of that of the instruction at POS1, swap the | |
13348 | instructions if POS2 is not already less than POS1. */ | |
2bcb2ab3 | 13349 | |
ab77a036 | 13350 | static void |
ce1ce33a | 13351 | mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit) |
ab77a036 RS |
13352 | { |
13353 | if (pos1 < pos2 | |
13354 | && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2])) | |
13355 | { | |
ce1ce33a | 13356 | rtx_insn *temp; |
65239d20 | 13357 | |
ab77a036 RS |
13358 | temp = ready[pos1]; |
13359 | ready[pos1] = ready[pos2]; | |
13360 | ready[pos2] = temp; | |
13361 | } | |
13362 | } | |
13363 | \f | |
13364 | /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction | |
13365 | that may clobber hi or lo. */ | |
647d790d | 13366 | static rtx_insn *mips_macc_chains_last_hilo; |
2bcb2ab3 | 13367 | |
ab77a036 RS |
13368 | /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has |
13369 | been scheduled, updating mips_macc_chains_last_hilo appropriately. */ | |
2bcb2ab3 | 13370 | |
ab77a036 | 13371 | static void |
647d790d | 13372 | mips_macc_chains_record (rtx_insn *insn) |
ab77a036 RS |
13373 | { |
13374 | if (get_attr_may_clobber_hilo (insn)) | |
13375 | mips_macc_chains_last_hilo = insn; | |
13376 | } | |
2bcb2ab3 | 13377 | |
ab77a036 RS |
13378 | /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which |
13379 | has NREADY elements, looking for a multiply-add or multiply-subtract | |
13380 | instruction that is cumulative with mips_macc_chains_last_hilo. | |
13381 | If there is one, promote it ahead of anything else that might | |
13382 | clobber hi or lo. */ | |
2bcb2ab3 | 13383 | |
ab77a036 | 13384 | static void |
ce1ce33a | 13385 | mips_macc_chains_reorder (rtx_insn **ready, int nready) |
ab77a036 RS |
13386 | { |
13387 | int i, j; | |
2bcb2ab3 | 13388 | |
ab77a036 RS |
13389 | if (mips_macc_chains_last_hilo != 0) |
13390 | for (i = nready - 1; i >= 0; i--) | |
13391 | if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i])) | |
13392 | { | |
13393 | for (j = nready - 1; j > i; j--) | |
13394 | if (recog_memoized (ready[j]) >= 0 | |
13395 | && get_attr_may_clobber_hilo (ready[j])) | |
13396 | { | |
13397 | mips_promote_ready (ready, i, j); | |
13398 | break; | |
13399 | } | |
13400 | break; | |
13401 | } | |
13402 | } | |
13403 | \f | |
13404 | /* The last instruction to be scheduled. */ | |
647d790d | 13405 | static rtx_insn *vr4130_last_insn; |
2bcb2ab3 | 13406 | |
ab77a036 RS |
13407 | /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA |
13408 | points to an rtx that is initially an instruction. Nullify the rtx | |
13409 | if the instruction uses the value of register X. */ | |
2bcb2ab3 | 13410 | |
ab77a036 | 13411 | static void |
65239d20 RS |
13412 | vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, |
13413 | void *data) | |
ab77a036 | 13414 | { |
65239d20 RS |
13415 | rtx *insn_ptr; |
13416 | ||
13417 | insn_ptr = (rtx *) data; | |
ab77a036 RS |
13418 | if (REG_P (x) |
13419 | && *insn_ptr != 0 | |
13420 | && reg_referenced_p (x, PATTERN (*insn_ptr))) | |
13421 | *insn_ptr = 0; | |
13422 | } | |
2bcb2ab3 | 13423 | |
ab77a036 RS |
13424 | /* Return true if there is true register dependence between vr4130_last_insn |
13425 | and INSN. */ | |
2bcb2ab3 | 13426 | |
ab77a036 RS |
13427 | static bool |
13428 | vr4130_true_reg_dependence_p (rtx insn) | |
13429 | { | |
13430 | note_stores (PATTERN (vr4130_last_insn), | |
13431 | vr4130_true_reg_dependence_p_1, &insn); | |
13432 | return insn == 0; | |
13433 | } | |
2bcb2ab3 | 13434 | |
ab77a036 RS |
13435 | /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of |
13436 | the ready queue and that INSN2 is the instruction after it, return | |
13437 | true if it is worth promoting INSN2 ahead of INSN1. Look for cases | |
13438 | in which INSN1 and INSN2 can probably issue in parallel, but for | |
13439 | which (INSN2, INSN1) should be less sensitive to instruction | |
13440 | alignment than (INSN1, INSN2). See 4130.md for more details. */ | |
2bcb2ab3 | 13441 | |
ab77a036 | 13442 | static bool |
647d790d | 13443 | vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2) |
ab77a036 RS |
13444 | { |
13445 | sd_iterator_def sd_it; | |
13446 | dep_t dep; | |
2bcb2ab3 | 13447 | |
ab77a036 | 13448 | /* Check for the following case: |
2bcb2ab3 | 13449 | |
ab77a036 RS |
13450 | 1) there is some other instruction X with an anti dependence on INSN1; |
13451 | 2) X has a higher priority than INSN2; and | |
13452 | 3) X is an arithmetic instruction (and thus has no unit restrictions). | |
2bcb2ab3 | 13453 | |
ab77a036 RS |
13454 | If INSN1 is the last instruction blocking X, it would better to |
13455 | choose (INSN1, X) over (INSN2, INSN1). */ | |
13456 | FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep) | |
13457 | if (DEP_TYPE (dep) == REG_DEP_ANTI | |
13458 | && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2) | |
13459 | && recog_memoized (DEP_CON (dep)) >= 0 | |
13460 | && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU) | |
13461 | return false; | |
2bcb2ab3 | 13462 | |
ab77a036 RS |
13463 | if (vr4130_last_insn != 0 |
13464 | && recog_memoized (insn1) >= 0 | |
13465 | && recog_memoized (insn2) >= 0) | |
13466 | { | |
13467 | /* See whether INSN1 and INSN2 use different execution units, | |
13468 | or if they are both ALU-type instructions. If so, they can | |
13469 | probably execute in parallel. */ | |
13470 | enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1); | |
13471 | enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2); | |
13472 | if (class1 != class2 || class1 == VR4130_CLASS_ALU) | |
2bcb2ab3 | 13473 | { |
ab77a036 RS |
13474 | /* If only one of the instructions has a dependence on |
13475 | vr4130_last_insn, prefer to schedule the other one first. */ | |
65239d20 RS |
13476 | bool dep1_p = vr4130_true_reg_dependence_p (insn1); |
13477 | bool dep2_p = vr4130_true_reg_dependence_p (insn2); | |
13478 | if (dep1_p != dep2_p) | |
13479 | return dep1_p; | |
2bcb2ab3 | 13480 | |
ab77a036 RS |
13481 | /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn |
13482 | is not an ALU-type instruction and if INSN1 uses the same | |
13483 | execution unit. (Note that if this condition holds, we already | |
13484 | know that INSN2 uses a different execution unit.) */ | |
13485 | if (class1 != VR4130_CLASS_ALU | |
13486 | && recog_memoized (vr4130_last_insn) >= 0 | |
13487 | && class1 == get_attr_vr4130_class (vr4130_last_insn)) | |
13488 | return true; | |
13489 | } | |
13490 | } | |
13491 | return false; | |
13492 | } | |
2bcb2ab3 | 13493 | |
ab77a036 RS |
13494 | /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready |
13495 | queue with at least two instructions. Swap the first two if | |
13496 | vr4130_swap_insns_p says that it could be worthwhile. */ | |
2bcb2ab3 | 13497 | |
ab77a036 | 13498 | static void |
ce1ce33a | 13499 | vr4130_reorder (rtx_insn **ready, int nready) |
ab77a036 RS |
13500 | { |
13501 | if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2])) | |
13502 | mips_promote_ready (ready, nready - 2, nready - 1); | |
13503 | } | |
13504 | \f | |
13505 | /* Record whether last 74k AGEN instruction was a load or store. */ | |
ab77a036 | 13506 | static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN; |
2bcb2ab3 | 13507 | |
ab77a036 RS |
13508 | /* Initialize mips_last_74k_agen_insn from INSN. A null argument |
13509 | resets to TYPE_UNKNOWN state. */ | |
2bcb2ab3 | 13510 | |
ab77a036 | 13511 | static void |
84034c69 | 13512 | mips_74k_agen_init (rtx_insn *insn) |
ab77a036 | 13513 | { |
006b29ab | 13514 | if (!insn || CALL_P (insn) || JUMP_P (insn)) |
ab77a036 | 13515 | mips_last_74k_agen_insn = TYPE_UNKNOWN; |
65239d20 | 13516 | else |
ab77a036 RS |
13517 | { |
13518 | enum attr_type type = get_attr_type (insn); | |
13519 | if (type == TYPE_LOAD || type == TYPE_STORE) | |
13520 | mips_last_74k_agen_insn = type; | |
13521 | } | |
13522 | } | |
2bcb2ab3 | 13523 | |
ab77a036 RS |
13524 | /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple |
13525 | loads to be grouped together, and multiple stores to be grouped | |
13526 | together. Swap things around in the ready queue to make this happen. */ | |
30244df3 | 13527 | |
ab77a036 | 13528 | static void |
ce1ce33a | 13529 | mips_74k_agen_reorder (rtx_insn **ready, int nready) |
ab77a036 RS |
13530 | { |
13531 | int i; | |
13532 | int store_pos, load_pos; | |
30244df3 | 13533 | |
ab77a036 RS |
13534 | store_pos = -1; |
13535 | load_pos = -1; | |
2bcb2ab3 | 13536 | |
ab77a036 RS |
13537 | for (i = nready - 1; i >= 0; i--) |
13538 | { | |
ce1ce33a | 13539 | rtx_insn *insn = ready[i]; |
ab77a036 RS |
13540 | if (USEFUL_INSN_P (insn)) |
13541 | switch (get_attr_type (insn)) | |
13542 | { | |
13543 | case TYPE_STORE: | |
13544 | if (store_pos == -1) | |
13545 | store_pos = i; | |
13546 | break; | |
2bcb2ab3 | 13547 | |
ab77a036 RS |
13548 | case TYPE_LOAD: |
13549 | if (load_pos == -1) | |
13550 | load_pos = i; | |
13551 | break; | |
2bcb2ab3 | 13552 | |
ab77a036 RS |
13553 | default: |
13554 | break; | |
13555 | } | |
13556 | } | |
2bcb2ab3 | 13557 | |
ab77a036 RS |
13558 | if (load_pos == -1 || store_pos == -1) |
13559 | return; | |
2bcb2ab3 | 13560 | |
ab77a036 | 13561 | switch (mips_last_74k_agen_insn) |
76cbf5bf | 13562 | { |
ab77a036 RS |
13563 | case TYPE_UNKNOWN: |
13564 | /* Prefer to schedule loads since they have a higher latency. */ | |
13565 | case TYPE_LOAD: | |
13566 | /* Swap loads to the front of the queue. */ | |
13567 | mips_maybe_swap_ready (ready, load_pos, store_pos, 4); | |
13568 | break; | |
13569 | case TYPE_STORE: | |
13570 | /* Swap stores to the front of the queue. */ | |
13571 | mips_maybe_swap_ready (ready, store_pos, load_pos, 4); | |
13572 | break; | |
13573 | default: | |
13574 | break; | |
76cbf5bf | 13575 | } |
ab77a036 RS |
13576 | } |
13577 | \f | |
13578 | /* Implement TARGET_SCHED_INIT. */ | |
76cbf5bf | 13579 | |
ab77a036 RS |
13580 | static void |
13581 | mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
13582 | int max_ready ATTRIBUTE_UNUSED) | |
13583 | { | |
13584 | mips_macc_chains_last_hilo = 0; | |
13585 | vr4130_last_insn = 0; | |
84034c69 | 13586 | mips_74k_agen_init (NULL); |
58684fa0 MK |
13587 | |
13588 | /* When scheduling for Loongson2, branch instructions go to ALU1, | |
13589 | therefore basic block is most likely to start with round-robin counter | |
13590 | pointed to ALU2. */ | |
13591 | mips_ls2.alu1_turn_p = false; | |
13592 | mips_ls2.falu1_turn_p = true; | |
2bcb2ab3 GK |
13593 | } |
13594 | ||
646e6f41 | 13595 | /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */ |
76cbf5bf | 13596 | |
646e6f41 JZ |
13597 | static void |
13598 | mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 13599 | rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) |
76cbf5bf | 13600 | { |
ab77a036 RS |
13601 | if (!reload_completed |
13602 | && TUNE_MACC_CHAINS | |
13603 | && *nreadyp > 0) | |
13604 | mips_macc_chains_reorder (ready, *nreadyp); | |
65239d20 | 13605 | |
ab77a036 RS |
13606 | if (reload_completed |
13607 | && TUNE_MIPS4130 | |
13608 | && !TARGET_VR4130_ALIGN | |
13609 | && *nreadyp > 1) | |
13610 | vr4130_reorder (ready, *nreadyp); | |
65239d20 | 13611 | |
ab77a036 RS |
13612 | if (TUNE_74K) |
13613 | mips_74k_agen_reorder (ready, *nreadyp); | |
646e6f41 | 13614 | } |
65239d20 | 13615 | |
646e6f41 JZ |
13616 | /* Implement TARGET_SCHED_REORDER. */ |
13617 | ||
13618 | static int | |
13619 | mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 13620 | rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) |
646e6f41 JZ |
13621 | { |
13622 | mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); | |
ab77a036 RS |
13623 | return mips_issue_rate (); |
13624 | } | |
76cbf5bf | 13625 | |
646e6f41 JZ |
13626 | /* Implement TARGET_SCHED_REORDER2. */ |
13627 | ||
13628 | static int | |
13629 | mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 13630 | rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) |
646e6f41 JZ |
13631 | { |
13632 | mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); | |
13633 | return cached_can_issue_more; | |
13634 | } | |
13635 | ||
58684fa0 MK |
13636 | /* Update round-robin counters for ALU1/2 and FALU1/2. */ |
13637 | ||
13638 | static void | |
647d790d | 13639 | mips_ls2_variable_issue (rtx_insn *insn) |
58684fa0 MK |
13640 | { |
13641 | if (mips_ls2.alu1_turn_p) | |
13642 | { | |
13643 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code)) | |
13644 | mips_ls2.alu1_turn_p = false; | |
13645 | } | |
13646 | else | |
13647 | { | |
13648 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code)) | |
13649 | mips_ls2.alu1_turn_p = true; | |
13650 | } | |
13651 | ||
13652 | if (mips_ls2.falu1_turn_p) | |
13653 | { | |
13654 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code)) | |
13655 | mips_ls2.falu1_turn_p = false; | |
13656 | } | |
13657 | else | |
13658 | { | |
13659 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code)) | |
13660 | mips_ls2.falu1_turn_p = true; | |
13661 | } | |
13662 | ||
13663 | if (recog_memoized (insn) >= 0) | |
13664 | mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI); | |
13665 | } | |
13666 | ||
ab77a036 | 13667 | /* Implement TARGET_SCHED_VARIABLE_ISSUE. */ |
76cbf5bf | 13668 | |
ab77a036 RS |
13669 | static int |
13670 | mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
ac44248e | 13671 | rtx_insn *insn, int more) |
ab77a036 | 13672 | { |
65239d20 RS |
13673 | /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */ |
13674 | if (USEFUL_INSN_P (insn)) | |
f2531eb6 | 13675 | { |
0c433c31 RS |
13676 | if (get_attr_type (insn) != TYPE_GHOST) |
13677 | more--; | |
ab77a036 RS |
13678 | if (!reload_completed && TUNE_MACC_CHAINS) |
13679 | mips_macc_chains_record (insn); | |
13680 | vr4130_last_insn = insn; | |
65239d20 RS |
13681 | if (TUNE_74K) |
13682 | mips_74k_agen_init (insn); | |
58684fa0 MK |
13683 | else if (TUNE_LOONGSON_2EF) |
13684 | mips_ls2_variable_issue (insn); | |
76cbf5bf | 13685 | } |
58684fa0 MK |
13686 | |
13687 | /* Instructions of type 'multi' should all be split before | |
13688 | the second scheduling pass. */ | |
13689 | gcc_assert (!reload_completed | |
13690 | || recog_memoized (insn) < 0 | |
13691 | || get_attr_type (insn) != TYPE_MULTI); | |
13692 | ||
646e6f41 | 13693 | cached_can_issue_more = more; |
ab77a036 | 13694 | return more; |
76cbf5bf | 13695 | } |
ab77a036 RS |
13696 | \f |
13697 | /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY), | |
65239d20 | 13698 | return the first operand of the associated PREF or PREFX insn. */ |
76cbf5bf | 13699 | |
ab77a036 RS |
13700 | rtx |
13701 | mips_prefetch_cookie (rtx write, rtx locality) | |
13702 | { | |
13703 | /* store_streamed / load_streamed. */ | |
13704 | if (INTVAL (locality) <= 0) | |
13705 | return GEN_INT (INTVAL (write) + 4); | |
76cbf5bf | 13706 | |
ab77a036 RS |
13707 | /* store / load. */ |
13708 | if (INTVAL (locality) <= 2) | |
13709 | return write; | |
2bcb2ab3 | 13710 | |
ab77a036 RS |
13711 | /* store_retained / load_retained. */ |
13712 | return GEN_INT (INTVAL (write) + 6); | |
13713 | } | |
13714 | \f | |
fd0eb897 RS |
13715 | /* Flags that indicate when a built-in function is available. |
13716 | ||
13717 | BUILTIN_AVAIL_NON_MIPS16 | |
a90c0245 RS |
13718 | The function is available on the current target if !TARGET_MIPS16. |
13719 | ||
13720 | BUILTIN_AVAIL_MIPS16 | |
13721 | The function is available on the current target if TARGET_MIPS16. */ | |
fd0eb897 | 13722 | #define BUILTIN_AVAIL_NON_MIPS16 1 |
a90c0245 | 13723 | #define BUILTIN_AVAIL_MIPS16 2 |
fd0eb897 RS |
13724 | |
13725 | /* Declare an availability predicate for built-in functions that | |
13726 | require non-MIPS16 mode and also require COND to be true. | |
13727 | NAME is the main part of the predicate's name. */ | |
13728 | #define AVAIL_NON_MIPS16(NAME, COND) \ | |
13729 | static unsigned int \ | |
13730 | mips_builtin_avail_##NAME (void) \ | |
13731 | { \ | |
13732 | return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ | |
13733 | } | |
13734 | ||
a90c0245 RS |
13735 | /* Declare an availability predicate for built-in functions that |
13736 | support both MIPS16 and non-MIPS16 code and also require COND | |
13737 | to be true. NAME is the main part of the predicate's name. */ | |
13738 | #define AVAIL_ALL(NAME, COND) \ | |
13739 | static unsigned int \ | |
13740 | mips_builtin_avail_##NAME (void) \ | |
13741 | { \ | |
13742 | return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \ | |
13743 | } | |
13744 | ||
65239d20 RS |
13745 | /* This structure describes a single built-in function. */ |
13746 | struct mips_builtin_description { | |
ab77a036 RS |
13747 | /* The code of the main .md file instruction. See mips_builtin_type |
13748 | for more information. */ | |
13749 | enum insn_code icode; | |
2bcb2ab3 | 13750 | |
ab77a036 RS |
13751 | /* The floating-point comparison code to use with ICODE, if any. */ |
13752 | enum mips_fp_condition cond; | |
2bcb2ab3 | 13753 | |
65239d20 | 13754 | /* The name of the built-in function. */ |
ab77a036 | 13755 | const char *name; |
2bcb2ab3 | 13756 | |
ab77a036 RS |
13757 | /* Specifies how the function should be expanded. */ |
13758 | enum mips_builtin_type builtin_type; | |
2bcb2ab3 | 13759 | |
ab77a036 RS |
13760 | /* The function's prototype. */ |
13761 | enum mips_function_type function_type; | |
2bcb2ab3 | 13762 | |
fd0eb897 RS |
13763 | /* Whether the function is available. */ |
13764 | unsigned int (*avail) (void); | |
ab77a036 | 13765 | }; |
76cbf5bf | 13766 | |
a90c0245 | 13767 | AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI) |
fd0eb897 RS |
13768 | AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT) |
13769 | AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT) | |
13770 | AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D) | |
13771 | AVAIL_NON_MIPS16 (dsp, TARGET_DSP) | |
13772 | AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) | |
13773 | AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) | |
770da00a | 13774 | AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) |
fd0eb897 | 13775 | AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) |
93581857 | 13776 | AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) |
4d210b07 | 13777 | AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) |
fd0eb897 RS |
13778 | |
13779 | /* Construct a mips_builtin_description from the given arguments. | |
13780 | ||
13781 | INSN is the name of the associated instruction pattern, without the | |
13782 | leading CODE_FOR_mips_. | |
13783 | ||
13784 | CODE is the floating-point condition code associated with the | |
13785 | function. It can be 'f' if the field is not applicable. | |
13786 | ||
13787 | NAME is the name of the function itself, without the leading | |
13788 | "__builtin_mips_". | |
13789 | ||
13790 | BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. | |
13791 | ||
13792 | AVAIL is the name of the availability predicate, without the leading | |
13793 | mips_builtin_avail_. */ | |
13794 | #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \ | |
13795 | FUNCTION_TYPE, AVAIL) \ | |
13796 | { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \ | |
13797 | "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \ | |
13798 | mips_builtin_avail_ ## AVAIL } | |
13799 | ||
13800 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function | |
13801 | mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL | |
13802 | are as for MIPS_BUILTIN. */ | |
13803 | #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
13804 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) | |
206c2d7a | 13805 | |
65239d20 | 13806 | /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which |
fd0eb897 RS |
13807 | are subject to mips_builtin_avail_<AVAIL>. */ |
13808 | #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \ | |
13809 | MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \ | |
13810 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \ | |
13811 | MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \ | |
13812 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL) | |
206c2d7a | 13813 | |
ab77a036 | 13814 | /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. |
fd0eb897 RS |
13815 | The lower and upper forms are subject to mips_builtin_avail_<AVAIL> |
13816 | while the any and all forms are subject to mips_builtin_avail_mips3d. */ | |
13817 | #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \ | |
13818 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \ | |
13819 | MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
13820 | mips3d), \ | |
13821 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \ | |
13822 | MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
13823 | mips3d), \ | |
13824 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \ | |
13825 | MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
13826 | AVAIL), \ | |
13827 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \ | |
13828 | MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
13829 | AVAIL) | |
206c2d7a | 13830 | |
ab77a036 | 13831 | /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions |
fd0eb897 | 13832 | are subject to mips_builtin_avail_mips3d. */ |
ab77a036 | 13833 | #define CMP_4S_BUILTINS(INSN, COND) \ |
fd0eb897 RS |
13834 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \ |
13835 | MIPS_BUILTIN_CMP_ANY, \ | |
13836 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \ | |
13837 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \ | |
13838 | MIPS_BUILTIN_CMP_ALL, \ | |
13839 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d) | |
206c2d7a | 13840 | |
ab77a036 | 13841 | /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison |
fd0eb897 RS |
13842 | instruction requires mips_builtin_avail_<AVAIL>. */ |
13843 | #define MOVTF_BUILTINS(INSN, COND, AVAIL) \ | |
13844 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \ | |
13845 | MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
13846 | AVAIL), \ | |
13847 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \ | |
13848 | MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
13849 | AVAIL) | |
2bcb2ab3 | 13850 | |
65239d20 | 13851 | /* Define all the built-in functions related to C.cond.fmt condition COND. */ |
ab77a036 | 13852 | #define CMP_BUILTINS(COND) \ |
fd0eb897 RS |
13853 | MOVTF_BUILTINS (c, COND, paired_single), \ |
13854 | MOVTF_BUILTINS (cabs, COND, mips3d), \ | |
13855 | CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \ | |
13856 | CMP_PS_BUILTINS (c, COND, paired_single), \ | |
13857 | CMP_PS_BUILTINS (cabs, COND, mips3d), \ | |
ab77a036 RS |
13858 | CMP_4S_BUILTINS (c, COND), \ |
13859 | CMP_4S_BUILTINS (cabs, COND) | |
18dbd950 | 13860 | |
fd0eb897 RS |
13861 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET |
13862 | function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE | |
13863 | and AVAIL are as for MIPS_BUILTIN. */ | |
13864 | #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
13865 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ | |
13866 | FUNCTION_TYPE, AVAIL) | |
2bcb2ab3 | 13867 | |
fd0eb897 RS |
13868 | /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP |
13869 | branch instruction. AVAIL is as for MIPS_BUILTIN. */ | |
13870 | #define BPOSGE_BUILTIN(VALUE, AVAIL) \ | |
13871 | MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ | |
13872 | MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) | |
dc884a86 | 13873 | |
93581857 MS |
13874 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> |
13875 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
13876 | builtin_description field. */ | |
13877 | #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \ | |
81f40b79 ILT |
13878 | { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \ |
13879 | "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \ | |
13880 | FUNCTION_TYPE, mips_builtin_avail_loongson } | |
93581857 MS |
13881 | |
13882 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN> | |
13883 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
13884 | builtin_description field. */ | |
13885 | #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \ | |
13886 | LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE) | |
13887 | ||
13888 | /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name. | |
13889 | We use functions of this form when the same insn can be usefully applied | |
13890 | to more than one datatype. */ | |
13891 | #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \ | |
13892 | LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE) | |
13893 | ||
ab77a036 | 13894 | #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 |
ab77a036 RS |
13895 | #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 |
13896 | #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 | |
13897 | #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 | |
13898 | #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3 | |
13899 | #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3 | |
293b77b0 CF |
13900 | #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit |
13901 | #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit | |
dc884a86 | 13902 | |
93581857 MS |
13903 | #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si |
13904 | #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi | |
13905 | #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi | |
13906 | #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3 | |
13907 | #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3 | |
13908 | #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3 | |
13909 | #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3 | |
13910 | #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3 | |
13911 | #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3 | |
13912 | #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3 | |
13913 | #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3 | |
13914 | #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3 | |
13915 | #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3 | |
13916 | #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3 | |
13917 | #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart | |
13918 | #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart | |
a44ecea1 | 13919 | #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3 |
59bdeecb MX |
13920 | #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3 |
13921 | #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3 | |
13922 | #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3 | |
13923 | #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3 | |
13924 | #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3 | |
13925 | #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3 | |
93581857 MS |
13926 | #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3 |
13927 | #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3 | |
13928 | #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3 | |
13929 | #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3 | |
13930 | #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3 | |
13931 | #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3 | |
13932 | #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3 | |
93581857 | 13933 | |
fd0eb897 | 13934 | static const struct mips_builtin_description mips_builtins[] = { |
70b2d364 | 13935 | #define MIPS_GET_FCSR 0 |
a90c0245 | 13936 | DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float), |
70b2d364 | 13937 | #define MIPS_SET_FCSR 1 |
a90c0245 RS |
13938 | DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float), |
13939 | ||
fd0eb897 RS |
13940 | DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), |
13941 | DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13942 | DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13943 | DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
13944 | DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single), | |
13945 | DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single), | |
13946 | DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single), | |
13947 | DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single), | |
13948 | ||
13949 | DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single), | |
13950 | DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13951 | DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13952 | DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13953 | DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13954 | ||
13955 | DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d), | |
13956 | DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d), | |
13957 | DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13958 | DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
13959 | DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
13960 | DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13961 | ||
13962 | DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d), | |
13963 | DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d), | |
13964 | DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
13965 | DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
13966 | DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
13967 | DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
13968 | ||
13969 | MIPS_FP_CONDITIONS (CMP_BUILTINS), | |
13970 | ||
13971 | /* Built-in functions for the SB-1 processor. */ | |
13972 | DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single), | |
13973 | ||
13974 | /* Built-in functions for the DSP ASE (32-bit and 64-bit). */ | |
13975 | DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13976 | DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13977 | DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
13978 | DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13979 | DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13980 | DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13981 | DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
13982 | DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
13983 | DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13984 | DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
13985 | DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp), | |
13986 | DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp), | |
13987 | DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp), | |
13988 | DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp), | |
13989 | DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp), | |
13990 | DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp), | |
13991 | DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
13992 | DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
13993 | DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
13994 | DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
13995 | DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp), | |
13996 | DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp), | |
13997 | DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13998 | DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
13999 | DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
14000 | DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
14001 | DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
14002 | DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
14003 | DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
14004 | DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
14005 | DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
14006 | DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
14007 | DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
14008 | DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
14009 | DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
14010 | DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
14011 | DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
14012 | DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
14013 | DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
14014 | DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
14015 | DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
14016 | DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
14017 | DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
14018 | DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp), | |
14019 | DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp), | |
14020 | DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp), | |
14021 | DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp), | |
14022 | DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
14023 | DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
14024 | DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
14025 | DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
14026 | DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
14027 | DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
14028 | DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
14029 | DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
14030 | DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
14031 | DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
14032 | DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
14033 | DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
14034 | DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp), | |
14035 | DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp), | |
14036 | DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
14037 | DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
14038 | DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
14039 | BPOSGE_BUILTIN (32, dsp), | |
14040 | ||
14041 | /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */ | |
14042 | DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2), | |
14043 | DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14044 | DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14045 | DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
14046 | DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
14047 | DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
14048 | DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
14049 | DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
14050 | DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
14051 | DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
14052 | DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14053 | DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14054 | DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
14055 | DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14056 | DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
14057 | DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2), | |
14058 | DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
14059 | DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
14060 | DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
14061 | DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
14062 | DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
14063 | DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2), | |
14064 | DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14065 | DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14066 | DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
14067 | DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
14068 | DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14069 | DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14070 | DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
14071 | DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
14072 | DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14073 | DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
14074 | DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
14075 | DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
14076 | ||
14077 | /* Built-in functions for the DSP ASE (32-bit only). */ | |
14078 | DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
14079 | DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
14080 | DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
14081 | DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
14082 | DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14083 | DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14084 | DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14085 | DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
14086 | DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
14087 | DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14088 | DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14089 | DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14090 | DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
14091 | DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
14092 | DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
14093 | DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
14094 | DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
14095 | DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
14096 | DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
14097 | DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
14098 | DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
293b77b0 CF |
14099 | DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), |
14100 | DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), | |
14101 | DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
14102 | DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), | |
14103 | DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32), | |
14104 | DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32), | |
fd0eb897 | 14105 | |
770da00a AP |
14106 | /* Built-in functions for the DSP ASE (64-bit only). */ |
14107 | DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64), | |
14108 | ||
fd0eb897 RS |
14109 | /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */ |
14110 | DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
14111 | DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
fd0eb897 | 14112 | DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
fd0eb897 RS |
14113 | DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
14114 | DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
14115 | DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
14116 | DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
14117 | DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
93581857 MS |
14118 | DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
14119 | ||
14120 | /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ | |
14121 | LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), | |
14122 | LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), | |
14123 | LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI), | |
14124 | LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14125 | LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14126 | LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14127 | LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
14128 | LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14129 | LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14130 | LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
14131 | LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI), | |
14132 | LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14133 | LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14134 | LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14135 | LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14136 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI), | |
14137 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14138 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14139 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14140 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI), | |
14141 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
14142 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14143 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14144 | LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14145 | LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14146 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14147 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14148 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14149 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
14150 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14151 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14152 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14153 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14154 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14155 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
14156 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14157 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14158 | LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI), | |
14159 | LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI), | |
14160 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14161 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14162 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14163 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14164 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14165 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14166 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14167 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14168 | LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI), | |
14169 | LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14170 | LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14171 | LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14172 | LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14173 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI), | |
14174 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI), | |
14175 | LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14176 | LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14177 | LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14178 | LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI), | |
14179 | LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14180 | LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI), | |
14181 | LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI), | |
7dab511c RH |
14182 | LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), |
14183 | LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
93581857 MS |
14184 | LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), |
14185 | LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
14186 | LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
14187 | LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
14188 | LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
14189 | LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
14190 | LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
14191 | LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
14192 | LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
14193 | LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
14194 | LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
14195 | LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
14196 | LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14197 | LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14198 | LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14199 | LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
14200 | LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14201 | LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14202 | LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
14203 | LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI), | |
14204 | LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14205 | LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14206 | LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14207 | LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14208 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14209 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14210 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14211 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14212 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
14213 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
14214 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
14215 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
14216 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
14217 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
14218 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
4d210b07 RS |
14219 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), |
14220 | ||
14221 | /* Sundry other built-in functions. */ | |
14222 | DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache) | |
ab77a036 | 14223 | }; |
dc884a86 | 14224 | |
7725086e RS |
14225 | /* Index I is the function declaration for mips_builtins[I], or null if the |
14226 | function isn't defined on this target. */ | |
14227 | static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)]; | |
14228 | ||
41030557 RS |
14229 | /* MODE is a vector mode whose elements have type TYPE. Return the type |
14230 | of the vector itself. */ | |
dc884a86 | 14231 | |
41030557 | 14232 | static tree |
ef4bddc2 | 14233 | mips_builtin_vector_type (tree type, machine_mode mode) |
dc884a86 | 14234 | { |
93581857 MS |
14235 | static tree types[2 * (int) MAX_MACHINE_MODE]; |
14236 | int mode_index; | |
dc884a86 | 14237 | |
93581857 MS |
14238 | mode_index = (int) mode; |
14239 | ||
14240 | if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type)) | |
14241 | mode_index += MAX_MACHINE_MODE; | |
14242 | ||
14243 | if (types[mode_index] == NULL_TREE) | |
14244 | types[mode_index] = build_vector_type_for_mode (type, mode); | |
14245 | return types[mode_index]; | |
41030557 | 14246 | } |
dc884a86 | 14247 | |
4d210b07 RS |
14248 | /* Return a type for 'const volatile void *'. */ |
14249 | ||
14250 | static tree | |
14251 | mips_build_cvpointer_type (void) | |
14252 | { | |
14253 | static tree cache; | |
14254 | ||
14255 | if (cache == NULL_TREE) | |
14256 | cache = build_pointer_type (build_qualified_type | |
14257 | (void_type_node, | |
14258 | TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)); | |
14259 | return cache; | |
14260 | } | |
14261 | ||
41030557 RS |
14262 | /* Source-level argument types. */ |
14263 | #define MIPS_ATYPE_VOID void_type_node | |
14264 | #define MIPS_ATYPE_INT integer_type_node | |
14265 | #define MIPS_ATYPE_POINTER ptr_type_node | |
4d210b07 | 14266 | #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type () |
dc884a86 | 14267 | |
41030557 | 14268 | /* Standard mode-based argument types. */ |
93581857 | 14269 | #define MIPS_ATYPE_UQI unsigned_intQI_type_node |
41030557 RS |
14270 | #define MIPS_ATYPE_SI intSI_type_node |
14271 | #define MIPS_ATYPE_USI unsigned_intSI_type_node | |
14272 | #define MIPS_ATYPE_DI intDI_type_node | |
93581857 | 14273 | #define MIPS_ATYPE_UDI unsigned_intDI_type_node |
41030557 RS |
14274 | #define MIPS_ATYPE_SF float_type_node |
14275 | #define MIPS_ATYPE_DF double_type_node | |
dc884a86 | 14276 | |
41030557 RS |
14277 | /* Vector argument types. */ |
14278 | #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode) | |
14279 | #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode) | |
93581857 | 14280 | #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode) |
41030557 | 14281 | #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode) |
93581857 MS |
14282 | #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode) |
14283 | #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode) | |
14284 | #define MIPS_ATYPE_UV2SI \ | |
14285 | mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode) | |
14286 | #define MIPS_ATYPE_UV4HI \ | |
14287 | mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode) | |
14288 | #define MIPS_ATYPE_UV8QI \ | |
14289 | mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode) | |
dc884a86 | 14290 | |
41030557 RS |
14291 | /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists |
14292 | their associated MIPS_ATYPEs. */ | |
14293 | #define MIPS_FTYPE_ATYPES1(A, B) \ | |
14294 | MIPS_ATYPE_##A, MIPS_ATYPE_##B | |
dc884a86 | 14295 | |
41030557 RS |
14296 | #define MIPS_FTYPE_ATYPES2(A, B, C) \ |
14297 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C | |
dc884a86 | 14298 | |
41030557 RS |
14299 | #define MIPS_FTYPE_ATYPES3(A, B, C, D) \ |
14300 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D | |
dc884a86 | 14301 | |
41030557 RS |
14302 | #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \ |
14303 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \ | |
14304 | MIPS_ATYPE_##E | |
dc884a86 | 14305 | |
41030557 | 14306 | /* Return the function type associated with function prototype TYPE. */ |
dc884a86 | 14307 | |
41030557 RS |
14308 | static tree |
14309 | mips_build_function_type (enum mips_function_type type) | |
14310 | { | |
14311 | static tree types[(int) MIPS_MAX_FTYPE_MAX]; | |
dc884a86 | 14312 | |
41030557 RS |
14313 | if (types[(int) type] == NULL_TREE) |
14314 | switch (type) | |
14315 | { | |
14316 | #define DEF_MIPS_FTYPE(NUM, ARGS) \ | |
14317 | case MIPS_FTYPE_NAME##NUM ARGS: \ | |
14318 | types[(int) type] \ | |
14319 | = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \ | |
14320 | NULL_TREE); \ | |
14321 | break; | |
14322 | #include "config/mips/mips-ftypes.def" | |
14323 | #undef DEF_MIPS_FTYPE | |
14324 | default: | |
14325 | gcc_unreachable (); | |
14326 | } | |
dc884a86 | 14327 | |
41030557 RS |
14328 | return types[(int) type]; |
14329 | } | |
6f2993e5 | 14330 | |
65239d20 | 14331 | /* Implement TARGET_INIT_BUILTINS. */ |
41030557 RS |
14332 | |
14333 | static void | |
14334 | mips_init_builtins (void) | |
14335 | { | |
65239d20 | 14336 | const struct mips_builtin_description *d; |
fd0eb897 | 14337 | unsigned int i; |
6f2993e5 | 14338 | |
ab77a036 RS |
14339 | /* Iterate through all of the bdesc arrays, initializing all of the |
14340 | builtin functions. */ | |
fd0eb897 | 14341 | for (i = 0; i < ARRAY_SIZE (mips_builtins); i++) |
ab77a036 | 14342 | { |
fd0eb897 RS |
14343 | d = &mips_builtins[i]; |
14344 | if (d->avail ()) | |
7725086e RS |
14345 | mips_builtin_decls[i] |
14346 | = add_builtin_function (d->name, | |
14347 | mips_build_function_type (d->function_type), | |
14348 | i, BUILT_IN_MD, NULL, NULL); | |
ab77a036 RS |
14349 | } |
14350 | } | |
6f2993e5 | 14351 | |
7725086e RS |
14352 | /* Implement TARGET_BUILTIN_DECL. */ |
14353 | ||
14354 | static tree | |
14355 | mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED) | |
14356 | { | |
14357 | if (code >= ARRAY_SIZE (mips_builtins)) | |
14358 | return error_mark_node; | |
14359 | return mips_builtin_decls[code]; | |
14360 | } | |
14361 | ||
b99ce2a8 RS |
14362 | /* Take argument ARGNO from EXP's argument list and convert it into |
14363 | an expand operand. Store the operand in *OP. */ | |
987a3c2b | 14364 | |
b99ce2a8 RS |
14365 | static void |
14366 | mips_prepare_builtin_arg (struct expand_operand *op, tree exp, | |
14367 | unsigned int argno) | |
ab77a036 | 14368 | { |
26b69f64 | 14369 | tree arg; |
ab77a036 | 14370 | rtx value; |
6f2993e5 | 14371 | |
26b69f64 RS |
14372 | arg = CALL_EXPR_ARG (exp, argno); |
14373 | value = expand_normal (arg); | |
b99ce2a8 RS |
14374 | create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg))); |
14375 | } | |
26b69f64 | 14376 | |
b99ce2a8 RS |
14377 | /* Expand instruction ICODE as part of a built-in function sequence. |
14378 | Use the first NOPS elements of OPS as the instruction's operands. | |
14379 | HAS_TARGET_P is true if operand 0 is a target; it is false if the | |
14380 | instruction has no target. | |
26b69f64 | 14381 | |
b99ce2a8 | 14382 | Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */ |
4d210b07 | 14383 | |
b99ce2a8 RS |
14384 | static rtx |
14385 | mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, | |
14386 | struct expand_operand *ops, bool has_target_p) | |
14387 | { | |
14388 | if (!maybe_expand_insn (icode, nops, ops)) | |
14389 | { | |
14390 | error ("invalid argument to built-in function"); | |
14391 | return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx; | |
ab77a036 | 14392 | } |
b99ce2a8 | 14393 | return has_target_p ? ops[0].value : const0_rtx; |
ab77a036 | 14394 | } |
0ac40e7a | 14395 | |
b99ce2a8 RS |
14396 | /* Expand a floating-point comparison for built-in function call EXP. |
14397 | The first NARGS arguments are the values to be compared. ICODE is | |
14398 | the .md pattern that does the comparison and COND is the condition | |
14399 | that is being tested. Return an rtx for the result. */ | |
0ac40e7a | 14400 | |
ab77a036 | 14401 | static rtx |
b99ce2a8 RS |
14402 | mips_expand_builtin_compare_1 (enum insn_code icode, |
14403 | enum mips_fp_condition cond, | |
14404 | tree exp, int nargs) | |
ab77a036 | 14405 | { |
b99ce2a8 | 14406 | struct expand_operand ops[MAX_RECOG_OPERANDS]; |
4b11e406 | 14407 | rtx output; |
b99ce2a8 | 14408 | int opno, argno; |
6f2993e5 | 14409 | |
b99ce2a8 RS |
14410 | /* The instruction should have a target operand, an operand for each |
14411 | argument, and an operand for COND. */ | |
f04713ee | 14412 | gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args); |
6f2993e5 | 14413 | |
4b11e406 | 14414 | output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode); |
b99ce2a8 | 14415 | opno = 0; |
4b11e406 | 14416 | create_fixed_operand (&ops[opno++], output); |
b99ce2a8 RS |
14417 | for (argno = 0; argno < nargs; argno++) |
14418 | mips_prepare_builtin_arg (&ops[opno++], exp, argno); | |
14419 | create_integer_operand (&ops[opno++], (int) cond); | |
14420 | return mips_expand_builtin_insn (icode, opno, ops, true); | |
6f2993e5 RS |
14421 | } |
14422 | ||
65239d20 RS |
14423 | /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function; |
14424 | HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function | |
14425 | and ICODE is the code of the associated .md pattern. TARGET, if nonnull, | |
14426 | suggests a good place to put the result. */ | |
6f2993e5 | 14427 | |
ab77a036 RS |
14428 | static rtx |
14429 | mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, | |
65239d20 | 14430 | bool has_target_p) |
6f2993e5 | 14431 | { |
b99ce2a8 | 14432 | struct expand_operand ops[MAX_RECOG_OPERANDS]; |
65239d20 | 14433 | int opno, argno; |
c15c90bb | 14434 | |
65239d20 RS |
14435 | /* Map any target to operand 0. */ |
14436 | opno = 0; | |
14437 | if (has_target_p) | |
b99ce2a8 | 14438 | create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp))); |
c235ddf2 | 14439 | |
f04713ee RS |
14440 | /* Map the arguments to the other operands. */ |
14441 | gcc_assert (opno + call_expr_nargs (exp) | |
14442 | == insn_data[icode].n_generator_args); | |
b99ce2a8 RS |
14443 | for (argno = 0; argno < call_expr_nargs (exp); argno++) |
14444 | mips_prepare_builtin_arg (&ops[opno++], exp, argno); | |
c15c90bb | 14445 | |
b99ce2a8 | 14446 | return mips_expand_builtin_insn (icode, opno, ops, has_target_p); |
c15c90bb | 14447 | } |
6f2993e5 | 14448 | |
65239d20 RS |
14449 | /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps |
14450 | function; TYPE says which. EXP is the CALL_EXPR that calls the | |
ab77a036 RS |
14451 | function, ICODE is the instruction that should be used to compare |
14452 | the first two arguments, and COND is the condition it should test. | |
14453 | TARGET, if nonnull, suggests a good place to put the result. */ | |
d604bca3 | 14454 | |
ab77a036 RS |
14455 | static rtx |
14456 | mips_expand_builtin_movtf (enum mips_builtin_type type, | |
14457 | enum insn_code icode, enum mips_fp_condition cond, | |
14458 | rtx target, tree exp) | |
14459 | { | |
b99ce2a8 RS |
14460 | struct expand_operand ops[4]; |
14461 | rtx cmp_result; | |
d604bca3 | 14462 | |
b99ce2a8 RS |
14463 | cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2); |
14464 | create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp))); | |
ab77a036 | 14465 | if (type == MIPS_BUILTIN_MOVT) |
d604bca3 | 14466 | { |
b99ce2a8 RS |
14467 | mips_prepare_builtin_arg (&ops[2], exp, 2); |
14468 | mips_prepare_builtin_arg (&ops[1], exp, 3); | |
c1bd2d66 | 14469 | } |
ab77a036 | 14470 | else |
d604bca3 | 14471 | { |
b99ce2a8 RS |
14472 | mips_prepare_builtin_arg (&ops[1], exp, 2); |
14473 | mips_prepare_builtin_arg (&ops[2], exp, 3); | |
c1bd2d66 | 14474 | } |
b99ce2a8 RS |
14475 | create_fixed_operand (&ops[3], cmp_result); |
14476 | return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps, | |
14477 | 4, ops, true); | |
d604bca3 MH |
14478 | } |
14479 | ||
ab77a036 RS |
14480 | /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE |
14481 | into TARGET otherwise. Return TARGET. */ | |
0ff83799 | 14482 | |
ab77a036 RS |
14483 | static rtx |
14484 | mips_builtin_branch_and_move (rtx condition, rtx target, | |
14485 | rtx value_if_true, rtx value_if_false) | |
0ff83799 | 14486 | { |
c6f971f4 | 14487 | rtx_code_label *true_label, *done_label; |
0ff83799 | 14488 | |
ab77a036 RS |
14489 | true_label = gen_label_rtx (); |
14490 | done_label = gen_label_rtx (); | |
21c9500d | 14491 | |
ab77a036 RS |
14492 | /* First assume that CONDITION is false. */ |
14493 | mips_emit_move (target, value_if_false); | |
21c9500d | 14494 | |
ab77a036 RS |
14495 | /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */ |
14496 | emit_jump_insn (gen_condjump (condition, true_label)); | |
14497 | emit_jump_insn (gen_jump (done_label)); | |
14498 | emit_barrier (); | |
21c9500d | 14499 | |
ab77a036 RS |
14500 | /* Fix TARGET if CONDITION is true. */ |
14501 | emit_label (true_label); | |
14502 | mips_emit_move (target, value_if_true); | |
0ff83799 | 14503 | |
ab77a036 RS |
14504 | emit_label (done_label); |
14505 | return target; | |
0ff83799 MM |
14506 | } |
14507 | ||
65239d20 RS |
14508 | /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is |
14509 | the CALL_EXPR that calls the function, ICODE is the code of the | |
14510 | comparison instruction, and COND is the condition it should test. | |
14511 | TARGET, if nonnull, suggests a good place to put the boolean result. */ | |
c8520e56 | 14512 | |
ab77a036 RS |
14513 | static rtx |
14514 | mips_expand_builtin_compare (enum mips_builtin_type builtin_type, | |
14515 | enum insn_code icode, enum mips_fp_condition cond, | |
14516 | rtx target, tree exp) | |
c8520e56 | 14517 | { |
b99ce2a8 | 14518 | rtx offset, condition, cmp_result; |
c8520e56 | 14519 | |
ab77a036 RS |
14520 | if (target == 0 || GET_MODE (target) != SImode) |
14521 | target = gen_reg_rtx (SImode); | |
b99ce2a8 RS |
14522 | cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, |
14523 | call_expr_nargs (exp)); | |
0ff83799 | 14524 | |
ab77a036 RS |
14525 | /* If the comparison sets more than one register, we define the result |
14526 | to be 0 if all registers are false and -1 if all registers are true. | |
14527 | The value of the complete result is indeterminate otherwise. */ | |
14528 | switch (builtin_type) | |
a8c1d5f8 | 14529 | { |
ab77a036 RS |
14530 | case MIPS_BUILTIN_CMP_ALL: |
14531 | condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx); | |
14532 | return mips_builtin_branch_and_move (condition, target, | |
14533 | const0_rtx, const1_rtx); | |
14534 | ||
14535 | case MIPS_BUILTIN_CMP_UPPER: | |
14536 | case MIPS_BUILTIN_CMP_LOWER: | |
14537 | offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER); | |
14538 | condition = gen_single_cc (cmp_result, offset); | |
14539 | return mips_builtin_branch_and_move (condition, target, | |
14540 | const1_rtx, const0_rtx); | |
14541 | ||
14542 | default: | |
14543 | condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx); | |
14544 | return mips_builtin_branch_and_move (condition, target, | |
14545 | const1_rtx, const0_rtx); | |
a8c1d5f8 | 14546 | } |
ab77a036 | 14547 | } |
0ff83799 | 14548 | |
65239d20 RS |
14549 | /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET, |
14550 | if nonnull, suggests a good place to put the boolean result. */ | |
0ff83799 | 14551 | |
ab77a036 RS |
14552 | static rtx |
14553 | mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) | |
14554 | { | |
14555 | rtx condition, cmp_result; | |
14556 | int cmp_value; | |
0ff83799 | 14557 | |
ab77a036 RS |
14558 | if (target == 0 || GET_MODE (target) != SImode) |
14559 | target = gen_reg_rtx (SImode); | |
0ff83799 | 14560 | |
ab77a036 RS |
14561 | cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM); |
14562 | ||
14563 | if (builtin_type == MIPS_BUILTIN_BPOSGE32) | |
14564 | cmp_value = 32; | |
a8c1d5f8 | 14565 | else |
ab77a036 RS |
14566 | gcc_assert (0); |
14567 | ||
14568 | condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value)); | |
14569 | return mips_builtin_branch_and_move (condition, target, | |
14570 | const1_rtx, const0_rtx); | |
14571 | } | |
14572 | ||
65239d20 | 14573 | /* Implement TARGET_EXPAND_BUILTIN. */ |
ab77a036 RS |
14574 | |
14575 | static rtx | |
14576 | mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
ef4bddc2 | 14577 | machine_mode mode, int ignore) |
ab77a036 | 14578 | { |
ab77a036 | 14579 | tree fndecl; |
fd0eb897 RS |
14580 | unsigned int fcode, avail; |
14581 | const struct mips_builtin_description *d; | |
ab77a036 RS |
14582 | |
14583 | fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
14584 | fcode = DECL_FUNCTION_CODE (fndecl); | |
fd0eb897 RS |
14585 | gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); |
14586 | d = &mips_builtins[fcode]; | |
14587 | avail = d->avail (); | |
14588 | gcc_assert (avail != 0); | |
a90c0245 | 14589 | if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)) |
a8c1d5f8 | 14590 | { |
29d08eba JM |
14591 | error ("built-in function %qE not supported for MIPS16", |
14592 | DECL_NAME (fndecl)); | |
0767b03f | 14593 | return ignore ? const0_rtx : CONST0_RTX (mode); |
a8c1d5f8 | 14594 | } |
fd0eb897 | 14595 | switch (d->builtin_type) |
0ff83799 | 14596 | { |
fd0eb897 RS |
14597 | case MIPS_BUILTIN_DIRECT: |
14598 | return mips_expand_builtin_direct (d->icode, target, exp, true); | |
14599 | ||
14600 | case MIPS_BUILTIN_DIRECT_NO_TARGET: | |
14601 | return mips_expand_builtin_direct (d->icode, target, exp, false); | |
14602 | ||
14603 | case MIPS_BUILTIN_MOVT: | |
14604 | case MIPS_BUILTIN_MOVF: | |
14605 | return mips_expand_builtin_movtf (d->builtin_type, d->icode, | |
14606 | d->cond, target, exp); | |
14607 | ||
14608 | case MIPS_BUILTIN_CMP_ANY: | |
14609 | case MIPS_BUILTIN_CMP_ALL: | |
14610 | case MIPS_BUILTIN_CMP_UPPER: | |
14611 | case MIPS_BUILTIN_CMP_LOWER: | |
14612 | case MIPS_BUILTIN_CMP_SINGLE: | |
14613 | return mips_expand_builtin_compare (d->builtin_type, d->icode, | |
14614 | d->cond, target, exp); | |
14615 | ||
14616 | case MIPS_BUILTIN_BPOSGE32: | |
14617 | return mips_expand_builtin_bposge (d->builtin_type, target); | |
a8c1d5f8 | 14618 | } |
5f5fe6d9 | 14619 | gcc_unreachable (); |
0ff83799 | 14620 | } |
a27fb29b | 14621 | \f |
65239d20 | 14622 | /* An entry in the MIPS16 constant pool. VALUE is the pool constant, |
ab77a036 | 14623 | MODE is its mode, and LABEL is the CODE_LABEL associated with it. */ |
ab77a036 RS |
14624 | struct mips16_constant { |
14625 | struct mips16_constant *next; | |
14626 | rtx value; | |
c6f971f4 | 14627 | rtx_code_label *label; |
ef4bddc2 | 14628 | machine_mode mode; |
ab77a036 | 14629 | }; |
6ba7b547 | 14630 | |
65239d20 | 14631 | /* Information about an incomplete MIPS16 constant pool. FIRST is the |
ab77a036 RS |
14632 | first constant, HIGHEST_ADDRESS is the highest address that the first |
14633 | byte of the pool can have, and INSN_ADDRESS is the current instruction | |
14634 | address. */ | |
ab77a036 RS |
14635 | struct mips16_constant_pool { |
14636 | struct mips16_constant *first; | |
14637 | int highest_address; | |
14638 | int insn_address; | |
14639 | }; | |
6ba7b547 | 14640 | |
ab77a036 RS |
14641 | /* Add constant VALUE to POOL and return its label. MODE is the |
14642 | value's mode (used for CONST_INTs, etc.). */ | |
6ba7b547 | 14643 | |
c6f971f4 | 14644 | static rtx_code_label * |
65239d20 | 14645 | mips16_add_constant (struct mips16_constant_pool *pool, |
ef4bddc2 | 14646 | rtx value, machine_mode mode) |
ab77a036 RS |
14647 | { |
14648 | struct mips16_constant **p, *c; | |
14649 | bool first_of_size_p; | |
6ba7b547 | 14650 | |
ab77a036 RS |
14651 | /* See whether the constant is already in the pool. If so, return the |
14652 | existing label, otherwise leave P pointing to the place where the | |
14653 | constant should be added. | |
6ba7b547 | 14654 | |
ab77a036 RS |
14655 | Keep the pool sorted in increasing order of mode size so that we can |
14656 | reduce the number of alignments needed. */ | |
14657 | first_of_size_p = true; | |
14658 | for (p = &pool->first; *p != 0; p = &(*p)->next) | |
14659 | { | |
14660 | if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value)) | |
14661 | return (*p)->label; | |
14662 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode)) | |
14663 | break; | |
14664 | if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode)) | |
14665 | first_of_size_p = false; | |
14666 | } | |
6ba7b547 | 14667 | |
ab77a036 RS |
14668 | /* In the worst case, the constant needed by the earliest instruction |
14669 | will end up at the end of the pool. The entire pool must then be | |
14670 | accessible from that instruction. | |
6ba7b547 | 14671 | |
ab77a036 RS |
14672 | When adding the first constant, set the pool's highest address to |
14673 | the address of the first out-of-range byte. Adjust this address | |
14674 | downwards each time a new constant is added. */ | |
14675 | if (pool->first == 0) | |
65239d20 RS |
14676 | /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address |
14677 | of the instruction with the lowest two bits clear. The base PC | |
14678 | value for LDPC has the lowest three bits clear. Assume the worst | |
14679 | case here; namely that the PC-relative instruction occupies the | |
14680 | last 2 bytes in an aligned word. */ | |
ab77a036 RS |
14681 | pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000; |
14682 | pool->highest_address -= GET_MODE_SIZE (mode); | |
14683 | if (first_of_size_p) | |
14684 | /* Take into account the worst possible padding due to alignment. */ | |
14685 | pool->highest_address -= GET_MODE_SIZE (mode) - 1; | |
6ba7b547 | 14686 | |
ab77a036 | 14687 | /* Create a new entry. */ |
65239d20 | 14688 | c = XNEW (struct mips16_constant); |
ab77a036 RS |
14689 | c->value = value; |
14690 | c->mode = mode; | |
14691 | c->label = gen_label_rtx (); | |
14692 | c->next = *p; | |
14693 | *p = c; | |
6ba7b547 | 14694 | |
ab77a036 RS |
14695 | return c->label; |
14696 | } | |
6ba7b547 | 14697 | |
ab77a036 RS |
14698 | /* Output constant VALUE after instruction INSN and return the last |
14699 | instruction emitted. MODE is the mode of the constant. */ | |
6ba7b547 | 14700 | |
c6f971f4 | 14701 | static rtx_insn * |
ef4bddc2 | 14702 | mips16_emit_constants_1 (machine_mode mode, rtx value, rtx_insn *insn) |
ab77a036 | 14703 | { |
65239d20 | 14704 | if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode)) |
ab77a036 RS |
14705 | { |
14706 | rtx size = GEN_INT (GET_MODE_SIZE (mode)); | |
14707 | return emit_insn_after (gen_consttable_int (value, size), insn); | |
14708 | } | |
6ba7b547 | 14709 | |
ab77a036 RS |
14710 | if (SCALAR_FLOAT_MODE_P (mode)) |
14711 | return emit_insn_after (gen_consttable_float (value), insn); | |
6ba7b547 | 14712 | |
ab77a036 RS |
14713 | if (VECTOR_MODE_P (mode)) |
14714 | { | |
14715 | int i; | |
6ba7b547 | 14716 | |
ab77a036 | 14717 | for (i = 0; i < CONST_VECTOR_NUNITS (value); i++) |
65239d20 RS |
14718 | insn = mips16_emit_constants_1 (GET_MODE_INNER (mode), |
14719 | CONST_VECTOR_ELT (value, i), insn); | |
ab77a036 RS |
14720 | return insn; |
14721 | } | |
6ba7b547 | 14722 | |
ab77a036 RS |
14723 | gcc_unreachable (); |
14724 | } | |
6ba7b547 | 14725 | |
ab77a036 | 14726 | /* Dump out the constants in CONSTANTS after INSN. */ |
32ad6a47 | 14727 | |
ab77a036 | 14728 | static void |
c6f971f4 | 14729 | mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn) |
32ad6a47 | 14730 | { |
ab77a036 RS |
14731 | struct mips16_constant *c, *next; |
14732 | int align; | |
46490403 | 14733 | |
ab77a036 RS |
14734 | align = 0; |
14735 | for (c = constants; c != NULL; c = next) | |
32ad6a47 | 14736 | { |
ab77a036 RS |
14737 | /* If necessary, increase the alignment of PC. */ |
14738 | if (align < GET_MODE_SIZE (c->mode)) | |
c9e0ce37 | 14739 | { |
ab77a036 RS |
14740 | int align_log = floor_log2 (GET_MODE_SIZE (c->mode)); |
14741 | insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn); | |
c9e0ce37 | 14742 | } |
ab77a036 | 14743 | align = GET_MODE_SIZE (c->mode); |
a27fb29b | 14744 | |
ab77a036 | 14745 | insn = emit_label_after (c->label, insn); |
65239d20 | 14746 | insn = mips16_emit_constants_1 (c->mode, c->value, insn); |
d07d525a | 14747 | |
ab77a036 RS |
14748 | next = c->next; |
14749 | free (c); | |
14750 | } | |
7dac2f89 | 14751 | |
ab77a036 | 14752 | emit_barrier_after (insn); |
a27fb29b | 14753 | } |
7dac2f89 | 14754 | |
ab77a036 | 14755 | /* Return the length of instruction INSN. */ |
f41a6bf1 | 14756 | |
ab77a036 | 14757 | static int |
c6f971f4 | 14758 | mips16_insn_length (rtx_insn *insn) |
ab77a036 | 14759 | { |
34f0d87a | 14760 | if (JUMP_TABLE_DATA_P (insn)) |
ab77a036 RS |
14761 | { |
14762 | rtx body = PATTERN (insn); | |
14763 | if (GET_CODE (body) == ADDR_VEC) | |
14764 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0); | |
39718607 | 14765 | else if (GET_CODE (body) == ADDR_DIFF_VEC) |
ab77a036 | 14766 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1); |
39718607 SB |
14767 | else |
14768 | gcc_unreachable (); | |
ab77a036 RS |
14769 | } |
14770 | return get_attr_length (insn); | |
14771 | } | |
7dac2f89 | 14772 | |
ab77a036 RS |
14773 | /* If *X is a symbolic constant that refers to the constant pool, add |
14774 | the constant to POOL and rewrite *X to use the constant's label. */ | |
7dac2f89 | 14775 | |
ab77a036 RS |
14776 | static void |
14777 | mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x) | |
a27fb29b | 14778 | { |
c6f971f4 DM |
14779 | rtx base, offset; |
14780 | rtx_code_label *label; | |
7dac2f89 | 14781 | |
ab77a036 RS |
14782 | split_const (*x, &base, &offset); |
14783 | if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base)) | |
14784 | { | |
36be1dee | 14785 | label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)), |
65239d20 | 14786 | get_pool_mode (base)); |
ab77a036 RS |
14787 | base = gen_rtx_LABEL_REF (Pmode, label); |
14788 | *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE); | |
14789 | } | |
a27fb29b | 14790 | } |
7dac2f89 | 14791 | |
9b3dd001 RS |
14792 | /* Rewrite INSN so that constant pool references refer to the constant's |
14793 | label instead. */ | |
7dac2f89 | 14794 | |
9b3dd001 RS |
14795 | static void |
14796 | mips16_rewrite_pool_refs (rtx_insn *insn, struct mips16_constant_pool *pool) | |
a27fb29b | 14797 | { |
9b3dd001 RS |
14798 | subrtx_ptr_iterator::array_type array; |
14799 | FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), ALL) | |
ab77a036 | 14800 | { |
9b3dd001 | 14801 | rtx *loc = *iter; |
ddaf8125 | 14802 | |
9b3dd001 RS |
14803 | if (force_to_mem_operand (*loc, Pmode)) |
14804 | { | |
14805 | rtx mem = force_const_mem (GET_MODE (*loc), *loc); | |
14806 | validate_change (insn, loc, mem, false); | |
14807 | } | |
a27fb29b | 14808 | |
9b3dd001 RS |
14809 | if (MEM_P (*loc)) |
14810 | { | |
14811 | mips16_rewrite_pool_constant (pool, &XEXP (*loc, 0)); | |
14812 | iter.skip_subrtxes (); | |
14813 | } | |
14814 | else | |
14815 | { | |
14816 | if (TARGET_MIPS16_TEXT_LOADS) | |
14817 | mips16_rewrite_pool_constant (pool, loc); | |
14818 | if (GET_CODE (*loc) == CONST | |
14819 | /* Don't rewrite the __mips16_rdwr symbol. */ | |
14820 | || (GET_CODE (*loc) == UNSPEC | |
14821 | && XINT (*loc, 1) == UNSPEC_TLS_GET_TP)) | |
14822 | iter.skip_subrtxes (); | |
14823 | } | |
14824 | } | |
7dac2f89 | 14825 | } |
7c262518 | 14826 | |
b53da244 AN |
14827 | /* Return whether CFG is used in mips_reorg. */ |
14828 | ||
14829 | static bool | |
14830 | mips_cfg_in_reorg (void) | |
14831 | { | |
14832 | return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE | |
14833 | || TARGET_RELAX_PIC_CALLS); | |
14834 | } | |
14835 | ||
36be1dee RS |
14836 | /* Build MIPS16 constant pools. Split the instructions if SPLIT_P, |
14837 | otherwise assume that they are already split. */ | |
a27fb29b | 14838 | |
ab77a036 | 14839 | static void |
36be1dee | 14840 | mips16_lay_out_constants (bool split_p) |
a27fb29b | 14841 | { |
ab77a036 | 14842 | struct mips16_constant_pool pool; |
c6f971f4 | 14843 | rtx_insn *insn, *barrier; |
a27fb29b | 14844 | |
ab77a036 RS |
14845 | if (!TARGET_MIPS16_PCREL_LOADS) |
14846 | return; | |
a27fb29b | 14847 | |
36be1dee RS |
14848 | if (split_p) |
14849 | { | |
14850 | if (mips_cfg_in_reorg ()) | |
14851 | split_all_insns (); | |
14852 | else | |
14853 | split_all_insns_noflow (); | |
14854 | } | |
ab77a036 RS |
14855 | barrier = 0; |
14856 | memset (&pool, 0, sizeof (pool)); | |
14857 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
14858 | { | |
14859 | /* Rewrite constant pool references in INSN. */ | |
006b29ab | 14860 | if (USEFUL_INSN_P (insn)) |
9b3dd001 | 14861 | mips16_rewrite_pool_refs (insn, &pool); |
dfad12b5 | 14862 | |
ab77a036 | 14863 | pool.insn_address += mips16_insn_length (insn); |
0e5a4ad8 | 14864 | |
ab77a036 RS |
14865 | if (pool.first != NULL) |
14866 | { | |
14867 | /* If there are no natural barriers between the first user of | |
14868 | the pool and the highest acceptable address, we'll need to | |
14869 | create a new instruction to jump around the constant pool. | |
14870 | In the worst case, this instruction will be 4 bytes long. | |
dfad12b5 | 14871 | |
ab77a036 RS |
14872 | If it's too late to do this transformation after INSN, |
14873 | do it immediately before INSN. */ | |
14874 | if (barrier == 0 && pool.insn_address + 4 > pool.highest_address) | |
14875 | { | |
c6f971f4 DM |
14876 | rtx_code_label *label; |
14877 | rtx_insn *jump; | |
54401342 | 14878 | |
ab77a036 RS |
14879 | label = gen_label_rtx (); |
14880 | ||
14881 | jump = emit_jump_insn_before (gen_jump (label), insn); | |
14882 | JUMP_LABEL (jump) = label; | |
14883 | LABEL_NUSES (label) = 1; | |
14884 | barrier = emit_barrier_after (jump); | |
14885 | ||
14886 | emit_label_after (label, barrier); | |
14887 | pool.insn_address += 4; | |
14888 | } | |
14889 | ||
14890 | /* See whether the constant pool is now out of range of the first | |
14891 | user. If so, output the constants after the previous barrier. | |
14892 | Note that any instructions between BARRIER and INSN (inclusive) | |
14893 | will use negative offsets to refer to the pool. */ | |
14894 | if (pool.insn_address > pool.highest_address) | |
14895 | { | |
65239d20 | 14896 | mips16_emit_constants (pool.first, barrier); |
ab77a036 RS |
14897 | pool.first = NULL; |
14898 | barrier = 0; | |
14899 | } | |
14900 | else if (BARRIER_P (insn)) | |
14901 | barrier = insn; | |
14902 | } | |
14903 | } | |
65239d20 | 14904 | mips16_emit_constants (pool.first, get_last_insn ()); |
0c8da560 | 14905 | } |
50d32cf6 | 14906 | \f |
4d210b07 RS |
14907 | /* Return true if it is worth r10k_simplify_address's while replacing |
14908 | an address with X. We are looking for constants, and for addresses | |
14909 | at a known offset from the incoming stack pointer. */ | |
14910 | ||
14911 | static bool | |
14912 | r10k_simplified_address_p (rtx x) | |
14913 | { | |
14914 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) | |
14915 | x = XEXP (x, 0); | |
14916 | return x == virtual_incoming_args_rtx || CONSTANT_P (x); | |
14917 | } | |
14918 | ||
14919 | /* X is an expression that appears in INSN. Try to use the UD chains | |
14920 | to simplify it, returning the simplified form on success and the | |
14921 | original form otherwise. Replace the incoming value of $sp with | |
14922 | virtual_incoming_args_rtx (which should never occur in X otherwise). */ | |
14923 | ||
14924 | static rtx | |
c6f971f4 | 14925 | r10k_simplify_address (rtx x, rtx_insn *insn) |
4d210b07 | 14926 | { |
c6f971f4 DM |
14927 | rtx newx, op0, op1, set, note; |
14928 | rtx_insn *def_insn; | |
57512f53 | 14929 | df_ref use, def; |
4d210b07 RS |
14930 | struct df_link *defs; |
14931 | ||
14932 | newx = NULL_RTX; | |
14933 | if (UNARY_P (x)) | |
14934 | { | |
14935 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
14936 | if (op0 != XEXP (x, 0)) | |
14937 | newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x), | |
14938 | op0, GET_MODE (XEXP (x, 0))); | |
14939 | } | |
14940 | else if (BINARY_P (x)) | |
14941 | { | |
14942 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
14943 | op1 = r10k_simplify_address (XEXP (x, 1), insn); | |
14944 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
14945 | newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); | |
14946 | } | |
14947 | else if (GET_CODE (x) == LO_SUM) | |
14948 | { | |
14949 | /* LO_SUMs can be offset from HIGHs, if we know they won't | |
14950 | overflow. See mips_classify_address for the rationale behind | |
14951 | the lax check. */ | |
14952 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
14953 | if (GET_CODE (op0) == HIGH) | |
14954 | newx = XEXP (x, 1); | |
14955 | } | |
14956 | else if (REG_P (x)) | |
14957 | { | |
14958 | /* Uses are recorded by regno_reg_rtx, not X itself. */ | |
14959 | use = df_find_use (insn, regno_reg_rtx[REGNO (x)]); | |
14960 | gcc_assert (use); | |
14961 | defs = DF_REF_CHAIN (use); | |
14962 | ||
14963 | /* Require a single definition. */ | |
14964 | if (defs && defs->next == NULL) | |
14965 | { | |
14966 | def = defs->ref; | |
14967 | if (DF_REF_IS_ARTIFICIAL (def)) | |
14968 | { | |
14969 | /* Replace the incoming value of $sp with | |
14970 | virtual_incoming_args_rtx. */ | |
14971 | if (x == stack_pointer_rtx | |
d6e193b3 | 14972 | && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
4d210b07 RS |
14973 | newx = virtual_incoming_args_rtx; |
14974 | } | |
14975 | else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use), | |
14976 | DF_REF_BB (def))) | |
14977 | { | |
14978 | /* Make sure that DEF_INSN is a single set of REG. */ | |
14979 | def_insn = DF_REF_INSN (def); | |
14980 | if (NONJUMP_INSN_P (def_insn)) | |
14981 | { | |
14982 | set = single_set (def_insn); | |
14983 | if (set && rtx_equal_p (SET_DEST (set), x)) | |
14984 | { | |
14985 | /* Prefer to use notes, since the def-use chains | |
14986 | are often shorter. */ | |
14987 | note = find_reg_equal_equiv_note (def_insn); | |
14988 | if (note) | |
14989 | newx = XEXP (note, 0); | |
14990 | else | |
14991 | newx = SET_SRC (set); | |
14992 | newx = r10k_simplify_address (newx, def_insn); | |
14993 | } | |
14994 | } | |
14995 | } | |
14996 | } | |
14997 | } | |
14998 | if (newx && r10k_simplified_address_p (newx)) | |
14999 | return newx; | |
15000 | return x; | |
15001 | } | |
15002 | ||
15003 | /* Return true if ADDRESS is known to be an uncached address | |
15004 | on R10K systems. */ | |
15005 | ||
15006 | static bool | |
15007 | r10k_uncached_address_p (unsigned HOST_WIDE_INT address) | |
15008 | { | |
15009 | unsigned HOST_WIDE_INT upper; | |
15010 | ||
15011 | /* Check for KSEG1. */ | |
15012 | if (address + 0x60000000 < 0x20000000) | |
15013 | return true; | |
15014 | ||
15015 | /* Check for uncached XKPHYS addresses. */ | |
15016 | if (Pmode == DImode) | |
15017 | { | |
15018 | upper = (address >> 40) & 0xf9ffff; | |
15019 | if (upper == 0x900000 || upper == 0xb80000) | |
15020 | return true; | |
15021 | } | |
15022 | return false; | |
15023 | } | |
15024 | ||
15025 | /* Return true if we can prove that an access to address X in instruction | |
15026 | INSN would be safe from R10K speculation. This X is a general | |
15027 | expression; it might not be a legitimate address. */ | |
15028 | ||
15029 | static bool | |
c6f971f4 | 15030 | r10k_safe_address_p (rtx x, rtx_insn *insn) |
4d210b07 RS |
15031 | { |
15032 | rtx base, offset; | |
15033 | HOST_WIDE_INT offset_val; | |
15034 | ||
15035 | x = r10k_simplify_address (x, insn); | |
15036 | ||
15037 | /* Check for references to the stack frame. It doesn't really matter | |
15038 | how much of the frame has been allocated at INSN; -mr10k-cache-barrier | |
15039 | allows us to assume that accesses to any part of the eventual frame | |
15040 | is safe from speculation at any point in the function. */ | |
15041 | mips_split_plus (x, &base, &offset_val); | |
15042 | if (base == virtual_incoming_args_rtx | |
15043 | && offset_val >= -cfun->machine->frame.total_size | |
15044 | && offset_val < cfun->machine->frame.args_size) | |
15045 | return true; | |
15046 | ||
15047 | /* Check for uncached addresses. */ | |
15048 | if (CONST_INT_P (x)) | |
15049 | return r10k_uncached_address_p (INTVAL (x)); | |
15050 | ||
15051 | /* Check for accesses to a static object. */ | |
15052 | split_const (x, &base, &offset); | |
15053 | return offset_within_block_p (base, INTVAL (offset)); | |
15054 | } | |
15055 | ||
15056 | /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is | |
15057 | an in-range access to an automatic variable, or to an object with | |
15058 | a link-time-constant address. */ | |
15059 | ||
15060 | static bool | |
7d362f6c | 15061 | r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset) |
4d210b07 | 15062 | { |
62332eba RS |
15063 | HOST_WIDE_INT bitoffset, bitsize; |
15064 | tree inner, var_offset; | |
ef4bddc2 | 15065 | machine_mode mode; |
62332eba | 15066 | int unsigned_p, volatile_p; |
4d210b07 | 15067 | |
62332eba | 15068 | inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode, |
b3ecff82 | 15069 | &unsigned_p, &volatile_p, false); |
62332eba RS |
15070 | if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset) |
15071 | return false; | |
4d210b07 | 15072 | |
62332eba | 15073 | offset += bitoffset / BITS_PER_UNIT; |
7d362f6c | 15074 | return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner)); |
4d210b07 RS |
15075 | } |
15076 | ||
9989ddc8 RS |
15077 | /* Return true if X contains a MEM that is not safe from R10K speculation. |
15078 | INSN is the instruction that contains X. */ | |
4d210b07 | 15079 | |
9989ddc8 RS |
15080 | static bool |
15081 | r10k_needs_protection_p_1 (rtx x, rtx_insn *insn) | |
4d210b07 | 15082 | { |
9989ddc8 RS |
15083 | subrtx_var_iterator::array_type array; |
15084 | FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) | |
15085 | { | |
15086 | rtx mem = *iter; | |
15087 | if (MEM_P (mem)) | |
15088 | { | |
15089 | if ((MEM_EXPR (mem) | |
15090 | && MEM_OFFSET_KNOWN_P (mem) | |
15091 | && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem))) | |
15092 | || r10k_safe_address_p (XEXP (mem, 0), insn)) | |
15093 | iter.skip_subrtxes (); | |
15094 | else | |
15095 | return true; | |
15096 | } | |
15097 | } | |
15098 | return false; | |
4d210b07 RS |
15099 | } |
15100 | ||
15101 | /* A note_stores callback for which DATA points to an instruction pointer. | |
15102 | If *DATA is nonnull, make it null if it X contains a MEM that is not | |
15103 | safe from R10K speculation. */ | |
15104 | ||
15105 | static void | |
15106 | r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED, | |
15107 | void *data) | |
15108 | { | |
c6f971f4 | 15109 | rtx_insn **insn_ptr; |
4d210b07 | 15110 | |
c6f971f4 | 15111 | insn_ptr = (rtx_insn **) data; |
9989ddc8 | 15112 | if (*insn_ptr && r10k_needs_protection_p_1 (x, *insn_ptr)) |
c6f971f4 | 15113 | *insn_ptr = NULL; |
4d210b07 RS |
15114 | } |
15115 | ||
d0cac36f RS |
15116 | /* X is the pattern of a call instruction. Return true if the call is |
15117 | not to a declared function. */ | |
4d210b07 | 15118 | |
d0cac36f RS |
15119 | static bool |
15120 | r10k_needs_protection_p_call (const_rtx x) | |
4d210b07 | 15121 | { |
d0cac36f RS |
15122 | subrtx_iterator::array_type array; |
15123 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
15124 | { | |
15125 | const_rtx mem = *iter; | |
15126 | if (MEM_P (mem)) | |
15127 | { | |
15128 | const_rtx addr = XEXP (mem, 0); | |
15129 | if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DECL (addr)) | |
15130 | iter.skip_subrtxes (); | |
15131 | else | |
15132 | return true; | |
15133 | } | |
15134 | } | |
15135 | return false; | |
4d210b07 RS |
15136 | } |
15137 | ||
15138 | /* Return true if instruction INSN needs to be protected by an R10K | |
15139 | cache barrier. */ | |
15140 | ||
15141 | static bool | |
c6f971f4 | 15142 | r10k_needs_protection_p (rtx_insn *insn) |
4d210b07 RS |
15143 | { |
15144 | if (CALL_P (insn)) | |
d0cac36f | 15145 | return r10k_needs_protection_p_call (PATTERN (insn)); |
4d210b07 RS |
15146 | |
15147 | if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE) | |
15148 | { | |
15149 | note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn); | |
15150 | return insn == NULL_RTX; | |
15151 | } | |
15152 | ||
9989ddc8 | 15153 | return r10k_needs_protection_p_1 (PATTERN (insn), insn); |
4d210b07 RS |
15154 | } |
15155 | ||
15156 | /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every | |
15157 | edge is unconditional. */ | |
15158 | ||
15159 | static bool | |
15160 | r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs) | |
15161 | { | |
15162 | edge_iterator ei; | |
15163 | edge e; | |
15164 | ||
15165 | FOR_EACH_EDGE (e, ei, bb->preds) | |
15166 | if (!single_succ_p (e->src) | |
d7c028c0 | 15167 | || !bitmap_bit_p (protected_bbs, e->src->index) |
4d210b07 RS |
15168 | || (e->flags & EDGE_COMPLEX) != 0) |
15169 | return false; | |
15170 | return true; | |
15171 | } | |
15172 | ||
15173 | /* Implement -mr10k-cache-barrier= for the current function. */ | |
15174 | ||
15175 | static void | |
15176 | r10k_insert_cache_barriers (void) | |
15177 | { | |
15178 | int *rev_post_order; | |
15179 | unsigned int i, n; | |
15180 | basic_block bb; | |
15181 | sbitmap protected_bbs; | |
c6f971f4 DM |
15182 | rtx_insn *insn, *end; |
15183 | rtx unprotected_region; | |
4d210b07 RS |
15184 | |
15185 | if (TARGET_MIPS16) | |
15186 | { | |
15187 | sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier"); | |
15188 | return; | |
15189 | } | |
15190 | ||
4d210b07 RS |
15191 | /* Calculate dominators. */ |
15192 | calculate_dominance_info (CDI_DOMINATORS); | |
15193 | ||
15194 | /* Bit X of PROTECTED_BBS is set if the last operation in basic block | |
15195 | X is protected by a cache barrier. */ | |
8b1c6fd7 | 15196 | protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
f61e445a | 15197 | bitmap_clear (protected_bbs); |
4d210b07 RS |
15198 | |
15199 | /* Iterate over the basic blocks in reverse post-order. */ | |
8b1c6fd7 | 15200 | rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun)); |
4d210b07 RS |
15201 | n = pre_and_rev_post_order_compute (NULL, rev_post_order, false); |
15202 | for (i = 0; i < n; i++) | |
15203 | { | |
06e28de2 | 15204 | bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]); |
4d210b07 RS |
15205 | |
15206 | /* If this block is only reached by unconditional edges, and if the | |
15207 | source of every edge is protected, the beginning of the block is | |
15208 | also protected. */ | |
15209 | if (r10k_protected_bb_p (bb, protected_bbs)) | |
15210 | unprotected_region = NULL_RTX; | |
15211 | else | |
15212 | unprotected_region = pc_rtx; | |
15213 | end = NEXT_INSN (BB_END (bb)); | |
15214 | ||
15215 | /* UNPROTECTED_REGION is: | |
15216 | ||
15217 | - null if we are processing a protected region, | |
15218 | - pc_rtx if we are processing an unprotected region but have | |
15219 | not yet found the first instruction in it | |
15220 | - the first instruction in an unprotected region otherwise. */ | |
15221 | for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn)) | |
15222 | { | |
006b29ab | 15223 | if (unprotected_region && USEFUL_INSN_P (insn)) |
4d210b07 RS |
15224 | { |
15225 | if (recog_memoized (insn) == CODE_FOR_mips_cache) | |
15226 | /* This CACHE instruction protects the following code. */ | |
15227 | unprotected_region = NULL_RTX; | |
15228 | else | |
15229 | { | |
15230 | /* See if INSN is the first instruction in this | |
15231 | unprotected region. */ | |
15232 | if (unprotected_region == pc_rtx) | |
15233 | unprotected_region = insn; | |
15234 | ||
15235 | /* See if INSN needs to be protected. If so, | |
15236 | we must insert a cache barrier somewhere between | |
15237 | PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't | |
15238 | clear which position is better performance-wise, | |
15239 | but as a tie-breaker, we assume that it is better | |
15240 | to allow delay slots to be back-filled where | |
15241 | possible, and that it is better not to insert | |
15242 | barriers in the middle of already-scheduled code. | |
15243 | We therefore insert the barrier at the beginning | |
15244 | of the region. */ | |
15245 | if (r10k_needs_protection_p (insn)) | |
15246 | { | |
15247 | emit_insn_before (gen_r10k_cache_barrier (), | |
15248 | unprotected_region); | |
15249 | unprotected_region = NULL_RTX; | |
15250 | } | |
15251 | } | |
15252 | } | |
15253 | ||
15254 | if (CALL_P (insn)) | |
15255 | /* The called function is not required to protect the exit path. | |
15256 | The code that follows a call is therefore unprotected. */ | |
15257 | unprotected_region = pc_rtx; | |
15258 | } | |
15259 | ||
15260 | /* Record whether the end of this block is protected. */ | |
15261 | if (unprotected_region == NULL_RTX) | |
d7c028c0 | 15262 | bitmap_set_bit (protected_bbs, bb->index); |
4d210b07 RS |
15263 | } |
15264 | XDELETEVEC (rev_post_order); | |
15265 | ||
15266 | sbitmap_free (protected_bbs); | |
15267 | ||
15268 | free_dominance_info (CDI_DOMINATORS); | |
b53da244 AN |
15269 | } |
15270 | \f | |
15271 | /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX | |
951771dc JW |
15272 | otherwise. If INSN has two call rtx, then store the second one in |
15273 | SECOND_CALL. */ | |
4d210b07 | 15274 | |
b53da244 | 15275 | static rtx |
c6f971f4 | 15276 | mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call) |
b53da244 AN |
15277 | { |
15278 | rtx x; | |
951771dc | 15279 | rtx x2; |
b53da244 AN |
15280 | |
15281 | if (!CALL_P (insn)) | |
15282 | return NULL_RTX; | |
4d210b07 | 15283 | |
b53da244 AN |
15284 | x = PATTERN (insn); |
15285 | if (GET_CODE (x) == PARALLEL) | |
951771dc JW |
15286 | { |
15287 | /* Calls returning complex values have two CALL rtx. Look for the second | |
15288 | one here, and return it via the SECOND_CALL arg. */ | |
15289 | x2 = XVECEXP (x, 0, 1); | |
15290 | if (GET_CODE (x2) == SET) | |
15291 | x2 = XEXP (x2, 1); | |
15292 | if (GET_CODE (x2) == CALL) | |
15293 | *second_call = x2; | |
15294 | ||
15295 | x = XVECEXP (x, 0, 0); | |
15296 | } | |
b53da244 AN |
15297 | if (GET_CODE (x) == SET) |
15298 | x = XEXP (x, 1); | |
b53da244 | 15299 | gcc_assert (GET_CODE (x) == CALL); |
951771dc | 15300 | |
b53da244 AN |
15301 | return x; |
15302 | } | |
15303 | ||
15304 | /* REG is set in DEF. See if the definition is one of the ways we load a | |
ee3ee488 RS |
15305 | register with a symbol address for a mips_use_pic_fn_addr_reg_p call. |
15306 | If it is, return the symbol reference of the function, otherwise return | |
15307 | NULL_RTX. | |
15308 | ||
15309 | If RECURSE_P is true, use mips_find_pic_call_symbol to interpret | |
15310 | the values of source registers, otherwise treat such registers as | |
15311 | having an unknown value. */ | |
b53da244 AN |
15312 | |
15313 | static rtx | |
ee3ee488 | 15314 | mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p) |
b53da244 | 15315 | { |
c6f971f4 DM |
15316 | rtx_insn *def_insn; |
15317 | rtx set; | |
b53da244 AN |
15318 | |
15319 | if (DF_REF_IS_ARTIFICIAL (def)) | |
15320 | return NULL_RTX; | |
15321 | ||
15322 | def_insn = DF_REF_INSN (def); | |
15323 | set = single_set (def_insn); | |
15324 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
15325 | { | |
15326 | rtx note, src, symbol; | |
15327 | ||
cb038fd2 RS |
15328 | /* First see whether the source is a plain symbol. This is used |
15329 | when calling symbols that are not lazily bound. */ | |
b53da244 | 15330 | src = SET_SRC (set); |
cb038fd2 RS |
15331 | if (GET_CODE (src) == SYMBOL_REF) |
15332 | return src; | |
15333 | ||
15334 | /* Handle %call16 references. */ | |
b53da244 AN |
15335 | symbol = mips_strip_unspec_call (src); |
15336 | if (symbol) | |
15337 | { | |
15338 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
15339 | return symbol; | |
15340 | } | |
15341 | ||
cb038fd2 RS |
15342 | /* If we have something more complicated, look for a |
15343 | REG_EQUAL or REG_EQUIV note. */ | |
15344 | note = find_reg_equal_equiv_note (def_insn); | |
15345 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
15346 | return XEXP (note, 0); | |
15347 | ||
ee3ee488 RS |
15348 | /* Follow at most one simple register copy. Such copies are |
15349 | interesting in cases like: | |
15350 | ||
15351 | for (...) | |
15352 | { | |
15353 | locally_binding_fn (...); | |
15354 | } | |
15355 | ||
15356 | and: | |
15357 | ||
15358 | locally_binding_fn (...); | |
15359 | ... | |
15360 | locally_binding_fn (...); | |
15361 | ||
15362 | where the load of locally_binding_fn can legitimately be | |
15363 | hoisted or shared. However, we do not expect to see complex | |
15364 | chains of copies, so a full worklist solution to the problem | |
15365 | would probably be overkill. */ | |
15366 | if (recurse_p && REG_P (src)) | |
15367 | return mips_find_pic_call_symbol (def_insn, src, false); | |
b53da244 AN |
15368 | } |
15369 | ||
15370 | return NULL_RTX; | |
15371 | } | |
15372 | ||
ee3ee488 RS |
15373 | /* Find the definition of the use of REG in INSN. See if the definition |
15374 | is one of the ways we load a register with a symbol address for a | |
15375 | mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference | |
15376 | of the function, otherwise return NULL_RTX. RECURSE_P is as for | |
15377 | mips_pic_call_symbol_from_set. */ | |
b53da244 AN |
15378 | |
15379 | static rtx | |
c6f971f4 | 15380 | mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p) |
b53da244 AN |
15381 | { |
15382 | df_ref use; | |
15383 | struct df_link *defs; | |
15384 | rtx symbol; | |
15385 | ||
15386 | use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]); | |
15387 | if (!use) | |
15388 | return NULL_RTX; | |
15389 | defs = DF_REF_CHAIN (use); | |
15390 | if (!defs) | |
15391 | return NULL_RTX; | |
ee3ee488 | 15392 | symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); |
b53da244 AN |
15393 | if (!symbol) |
15394 | return NULL_RTX; | |
15395 | ||
15396 | /* If we have more than one definition, they need to be identical. */ | |
15397 | for (defs = defs->next; defs; defs = defs->next) | |
15398 | { | |
15399 | rtx other; | |
15400 | ||
ee3ee488 | 15401 | other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); |
b53da244 AN |
15402 | if (!rtx_equal_p (symbol, other)) |
15403 | return NULL_RTX; | |
15404 | } | |
15405 | ||
15406 | return symbol; | |
15407 | } | |
15408 | ||
15409 | /* Replace the args_size operand of the call expression CALL with the | |
15410 | call-attribute UNSPEC and fill in SYMBOL as the function symbol. */ | |
15411 | ||
15412 | static void | |
15413 | mips_annotate_pic_call_expr (rtx call, rtx symbol) | |
15414 | { | |
15415 | rtx args_size; | |
15416 | ||
15417 | args_size = XEXP (call, 1); | |
15418 | XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size), | |
15419 | gen_rtvec (2, args_size, symbol), | |
15420 | UNSPEC_CALL_ATTR); | |
15421 | } | |
15422 | ||
15423 | /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See | |
15424 | if instead of the arg_size argument it contains the call attributes. If | |
15425 | yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function | |
15426 | symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is | |
15427 | -1. */ | |
15428 | ||
15429 | bool | |
15430 | mips_get_pic_call_symbol (rtx *operands, int args_size_opno) | |
15431 | { | |
15432 | rtx args_size, symbol; | |
15433 | ||
15434 | if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1) | |
15435 | return false; | |
15436 | ||
15437 | args_size = operands[args_size_opno]; | |
15438 | if (GET_CODE (args_size) != UNSPEC) | |
15439 | return false; | |
15440 | gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR); | |
15441 | ||
15442 | symbol = XVECEXP (args_size, 0, 1); | |
15443 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
15444 | ||
15445 | operands[args_size_opno] = symbol; | |
15446 | return true; | |
15447 | } | |
15448 | ||
15449 | /* Use DF to annotate PIC indirect calls with the function symbol they | |
15450 | dispatch to. */ | |
15451 | ||
15452 | static void | |
15453 | mips_annotate_pic_calls (void) | |
15454 | { | |
15455 | basic_block bb; | |
c6f971f4 | 15456 | rtx_insn *insn; |
b53da244 | 15457 | |
11cd3bed | 15458 | FOR_EACH_BB_FN (bb, cfun) |
b53da244 AN |
15459 | FOR_BB_INSNS (bb, insn) |
15460 | { | |
951771dc | 15461 | rtx call, reg, symbol, second_call; |
b53da244 | 15462 | |
951771dc JW |
15463 | second_call = 0; |
15464 | call = mips_call_expr_from_insn (insn, &second_call); | |
b53da244 AN |
15465 | if (!call) |
15466 | continue; | |
15467 | gcc_assert (MEM_P (XEXP (call, 0))); | |
15468 | reg = XEXP (XEXP (call, 0), 0); | |
15469 | if (!REG_P (reg)) | |
15470 | continue; | |
15471 | ||
ee3ee488 | 15472 | symbol = mips_find_pic_call_symbol (insn, reg, true); |
b53da244 | 15473 | if (symbol) |
951771dc JW |
15474 | { |
15475 | mips_annotate_pic_call_expr (call, symbol); | |
15476 | if (second_call) | |
15477 | mips_annotate_pic_call_expr (second_call, symbol); | |
15478 | } | |
b53da244 | 15479 | } |
4d210b07 RS |
15480 | } |
15481 | \f | |
9b8317b4 | 15482 | /* A temporary variable used by note_uses callbacks, etc. */ |
c6f971f4 | 15483 | static rtx_insn *mips_sim_insn; |
39ba1719 | 15484 | |
ab77a036 RS |
15485 | /* A structure representing the state of the processor pipeline. |
15486 | Used by the mips_sim_* family of functions. */ | |
15487 | struct mips_sim { | |
15488 | /* The maximum number of instructions that can be issued in a cycle. | |
15489 | (Caches mips_issue_rate.) */ | |
15490 | unsigned int issue_rate; | |
39ba1719 | 15491 | |
ab77a036 RS |
15492 | /* The current simulation time. */ |
15493 | unsigned int time; | |
39ba1719 | 15494 | |
ab77a036 RS |
15495 | /* How many more instructions can be issued in the current cycle. */ |
15496 | unsigned int insns_left; | |
39ba1719 | 15497 | |
ab77a036 RS |
15498 | /* LAST_SET[X].INSN is the last instruction to set register X. |
15499 | LAST_SET[X].TIME is the time at which that instruction was issued. | |
15500 | INSN is null if no instruction has yet set register X. */ | |
15501 | struct { | |
c6f971f4 | 15502 | rtx_insn *insn; |
ab77a036 RS |
15503 | unsigned int time; |
15504 | } last_set[FIRST_PSEUDO_REGISTER]; | |
39ba1719 | 15505 | |
ab77a036 RS |
15506 | /* The pipeline's current DFA state. */ |
15507 | state_t dfa_state; | |
15508 | }; | |
39ba1719 | 15509 | |
ab77a036 RS |
15510 | /* Reset STATE to the initial simulation state. */ |
15511 | ||
15512 | static void | |
15513 | mips_sim_reset (struct mips_sim *state) | |
15514 | { | |
4670abb0 RS |
15515 | curr_state = state->dfa_state; |
15516 | ||
ab77a036 RS |
15517 | state->time = 0; |
15518 | state->insns_left = state->issue_rate; | |
15519 | memset (&state->last_set, 0, sizeof (state->last_set)); | |
4670abb0 RS |
15520 | state_reset (curr_state); |
15521 | ||
15522 | targetm.sched.init (0, false, 0); | |
15523 | advance_state (curr_state); | |
39ba1719 | 15524 | } |
39ba1719 | 15525 | |
ab77a036 RS |
15526 | /* Initialize STATE before its first use. DFA_STATE points to an |
15527 | allocated but uninitialized DFA state. */ | |
39ba1719 | 15528 | |
ab77a036 RS |
15529 | static void |
15530 | mips_sim_init (struct mips_sim *state, state_t dfa_state) | |
15531 | { | |
4670abb0 RS |
15532 | if (targetm.sched.init_dfa_pre_cycle_insn) |
15533 | targetm.sched.init_dfa_pre_cycle_insn (); | |
15534 | ||
15535 | if (targetm.sched.init_dfa_post_cycle_insn) | |
15536 | targetm.sched.init_dfa_post_cycle_insn (); | |
15537 | ||
ab77a036 RS |
15538 | state->issue_rate = mips_issue_rate (); |
15539 | state->dfa_state = dfa_state; | |
15540 | mips_sim_reset (state); | |
15541 | } | |
15542 | ||
15543 | /* Advance STATE by one clock cycle. */ | |
39ba1719 RS |
15544 | |
15545 | static void | |
ab77a036 | 15546 | mips_sim_next_cycle (struct mips_sim *state) |
39ba1719 | 15547 | { |
4670abb0 RS |
15548 | curr_state = state->dfa_state; |
15549 | ||
ab77a036 RS |
15550 | state->time++; |
15551 | state->insns_left = state->issue_rate; | |
4670abb0 | 15552 | advance_state (curr_state); |
39ba1719 RS |
15553 | } |
15554 | ||
ab77a036 RS |
15555 | /* Advance simulation state STATE until instruction INSN can read |
15556 | register REG. */ | |
39ba1719 RS |
15557 | |
15558 | static void | |
c6f971f4 | 15559 | mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg) |
39ba1719 | 15560 | { |
65239d20 | 15561 | unsigned int regno, end_regno; |
39ba1719 | 15562 | |
65239d20 RS |
15563 | end_regno = END_REGNO (reg); |
15564 | for (regno = REGNO (reg); regno < end_regno; regno++) | |
15565 | if (state->last_set[regno].insn != 0) | |
ab77a036 RS |
15566 | { |
15567 | unsigned int t; | |
dc884a86 | 15568 | |
65239d20 RS |
15569 | t = (state->last_set[regno].time |
15570 | + insn_latency (state->last_set[regno].insn, insn)); | |
ab77a036 RS |
15571 | while (state->time < t) |
15572 | mips_sim_next_cycle (state); | |
15573 | } | |
15574 | } | |
dc884a86 | 15575 | |
9b8317b4 RS |
15576 | /* A note_uses callback. For each register in *X, advance simulation |
15577 | state DATA until mips_sim_insn can read the register's value. */ | |
dc884a86 | 15578 | |
ab77a036 RS |
15579 | static void |
15580 | mips_sim_wait_regs_1 (rtx *x, void *data) | |
dc884a86 | 15581 | { |
9b8317b4 RS |
15582 | subrtx_var_iterator::array_type array; |
15583 | FOR_EACH_SUBRTX_VAR (iter, array, *x, NONCONST) | |
15584 | if (REG_P (*iter)) | |
15585 | mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *iter); | |
dc884a86 RS |
15586 | } |
15587 | ||
ab77a036 RS |
15588 | /* Advance simulation state STATE until all of INSN's register |
15589 | dependencies are satisfied. */ | |
dc884a86 | 15590 | |
ab77a036 | 15591 | static void |
c6f971f4 | 15592 | mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn) |
dc884a86 | 15593 | { |
ab77a036 RS |
15594 | mips_sim_insn = insn; |
15595 | note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state); | |
15596 | } | |
dc884a86 | 15597 | |
ab77a036 RS |
15598 | /* Advance simulation state STATE until the units required by |
15599 | instruction INSN are available. */ | |
dc884a86 | 15600 | |
ab77a036 | 15601 | static void |
c6f971f4 | 15602 | mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn) |
ab77a036 RS |
15603 | { |
15604 | state_t tmp_state; | |
dc884a86 | 15605 | |
ab77a036 RS |
15606 | tmp_state = alloca (state_size ()); |
15607 | while (state->insns_left == 0 | |
15608 | || (memcpy (tmp_state, state->dfa_state, state_size ()), | |
15609 | state_transition (tmp_state, insn) >= 0)) | |
15610 | mips_sim_next_cycle (state); | |
dc884a86 RS |
15611 | } |
15612 | ||
ab77a036 | 15613 | /* Advance simulation state STATE until INSN is ready to issue. */ |
dc884a86 RS |
15614 | |
15615 | static void | |
c6f971f4 | 15616 | mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn) |
dc884a86 | 15617 | { |
ab77a036 RS |
15618 | mips_sim_wait_regs (state, insn); |
15619 | mips_sim_wait_units (state, insn); | |
dc884a86 | 15620 | } |
ab77a036 RS |
15621 | |
15622 | /* mips_sim_insn has just set X. Update the LAST_SET array | |
15623 | in simulation state DATA. */ | |
39ba1719 RS |
15624 | |
15625 | static void | |
ab77a036 | 15626 | mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
39ba1719 | 15627 | { |
ab77a036 | 15628 | struct mips_sim *state; |
39ba1719 | 15629 | |
5ead67f6 | 15630 | state = (struct mips_sim *) data; |
ab77a036 | 15631 | if (REG_P (x)) |
65239d20 RS |
15632 | { |
15633 | unsigned int regno, end_regno; | |
15634 | ||
15635 | end_regno = END_REGNO (x); | |
15636 | for (regno = REGNO (x); regno < end_regno; regno++) | |
15637 | { | |
15638 | state->last_set[regno].insn = mips_sim_insn; | |
15639 | state->last_set[regno].time = state->time; | |
15640 | } | |
15641 | } | |
39ba1719 RS |
15642 | } |
15643 | ||
ab77a036 RS |
15644 | /* Issue instruction INSN in scheduler state STATE. Assume that INSN |
15645 | can issue immediately (i.e., that mips_sim_wait_insn has already | |
15646 | been called). */ | |
39ba1719 | 15647 | |
174bd8ca | 15648 | static void |
c6f971f4 | 15649 | mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn) |
174bd8ca | 15650 | { |
4670abb0 RS |
15651 | curr_state = state->dfa_state; |
15652 | ||
15653 | state_transition (curr_state, insn); | |
15654 | state->insns_left = targetm.sched.variable_issue (0, false, insn, | |
15655 | state->insns_left); | |
174bd8ca | 15656 | |
ab77a036 RS |
15657 | mips_sim_insn = insn; |
15658 | note_stores (PATTERN (insn), mips_sim_record_set, state); | |
15659 | } | |
174bd8ca | 15660 | |
ab77a036 | 15661 | /* Simulate issuing a NOP in state STATE. */ |
174bd8ca SL |
15662 | |
15663 | static void | |
ab77a036 | 15664 | mips_sim_issue_nop (struct mips_sim *state) |
174bd8ca | 15665 | { |
ab77a036 RS |
15666 | if (state->insns_left == 0) |
15667 | mips_sim_next_cycle (state); | |
15668 | state->insns_left--; | |
174bd8ca SL |
15669 | } |
15670 | ||
ab77a036 RS |
15671 | /* Update simulation state STATE so that it's ready to accept the instruction |
15672 | after INSN. INSN should be part of the main rtl chain, not a member of a | |
15673 | SEQUENCE. */ | |
174bd8ca SL |
15674 | |
15675 | static void | |
c6f971f4 | 15676 | mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn) |
39ba1719 | 15677 | { |
ab77a036 RS |
15678 | /* If INSN is a jump with an implicit delay slot, simulate a nop. */ |
15679 | if (JUMP_P (insn)) | |
15680 | mips_sim_issue_nop (state); | |
174bd8ca | 15681 | |
ab77a036 | 15682 | switch (GET_CODE (SEQ_BEGIN (insn))) |
39ba1719 | 15683 | { |
ab77a036 RS |
15684 | case CODE_LABEL: |
15685 | case CALL_INSN: | |
15686 | /* We can't predict the processor state after a call or label. */ | |
15687 | mips_sim_reset (state); | |
15688 | break; | |
d33289b2 | 15689 | |
ab77a036 RS |
15690 | case JUMP_INSN: |
15691 | /* The delay slots of branch likely instructions are only executed | |
15692 | when the branch is taken. Therefore, if the caller has simulated | |
15693 | the delay slot instruction, STATE does not really reflect the state | |
15694 | of the pipeline for the instruction after the delay slot. Also, | |
15695 | branch likely instructions tend to incur a penalty when not taken, | |
15696 | so there will probably be an extra delay between the branch and | |
15697 | the instruction after the delay slot. */ | |
15698 | if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn))) | |
15699 | mips_sim_reset (state); | |
15700 | break; | |
d33289b2 | 15701 | |
ab77a036 RS |
15702 | default: |
15703 | break; | |
dc884a86 | 15704 | } |
174bd8ca | 15705 | } |
4670abb0 RS |
15706 | |
15707 | /* Use simulator state STATE to calculate the execution time of | |
15708 | instruction sequence SEQ. */ | |
15709 | ||
15710 | static unsigned int | |
c6f971f4 | 15711 | mips_seq_time (struct mips_sim *state, rtx_insn *seq) |
4670abb0 RS |
15712 | { |
15713 | mips_sim_reset (state); | |
c6f971f4 | 15714 | for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn)) |
4670abb0 RS |
15715 | { |
15716 | mips_sim_wait_insn (state, insn); | |
15717 | mips_sim_issue_insn (state, insn); | |
15718 | } | |
15719 | return state->time; | |
15720 | } | |
15721 | \f | |
15722 | /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p | |
15723 | setting SETTING, using STATE to simulate instruction sequences. */ | |
15724 | ||
15725 | static unsigned int | |
15726 | mips_mult_zero_zero_cost (struct mips_sim *state, bool setting) | |
15727 | { | |
15728 | mips_tuning_info.fast_mult_zero_zero_p = setting; | |
15729 | start_sequence (); | |
15730 | ||
ef4bddc2 | 15731 | machine_mode dword_mode = TARGET_64BIT ? TImode : DImode; |
4670abb0 RS |
15732 | rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST); |
15733 | mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED); | |
15734 | ||
15735 | /* If the target provides mulsidi3_32bit then that's the most likely | |
15736 | consumer of the result. Test for bypasses. */ | |
15737 | if (dword_mode == DImode && HAVE_maddsidi4) | |
15738 | { | |
15739 | rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4); | |
15740 | emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo)); | |
15741 | } | |
15742 | ||
15743 | unsigned int time = mips_seq_time (state, get_insns ()); | |
15744 | end_sequence (); | |
15745 | return time; | |
15746 | } | |
15747 | ||
15748 | /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0" | |
15749 | and set up mips_tuning_info.fast_mult_zero_zero_p accordingly. | |
15750 | Prefer MULT -- which is shorter -- in the event of a tie. */ | |
15751 | ||
15752 | static void | |
15753 | mips_set_fast_mult_zero_zero_p (struct mips_sim *state) | |
15754 | { | |
15755 | if (TARGET_MIPS16) | |
15756 | /* No MTLO or MTHI available. */ | |
15757 | mips_tuning_info.fast_mult_zero_zero_p = true; | |
15758 | else | |
15759 | { | |
15760 | unsigned int true_time = mips_mult_zero_zero_cost (state, true); | |
15761 | unsigned int false_time = mips_mult_zero_zero_cost (state, false); | |
15762 | mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time); | |
15763 | } | |
15764 | } | |
15765 | ||
15766 | /* Set up costs based on the current architecture and tuning settings. */ | |
15767 | ||
15768 | static void | |
15769 | mips_set_tuning_info (void) | |
15770 | { | |
15771 | if (mips_tuning_info.initialized_p | |
15772 | && mips_tuning_info.arch == mips_arch | |
15773 | && mips_tuning_info.tune == mips_tune | |
15774 | && mips_tuning_info.mips16_p == TARGET_MIPS16) | |
15775 | return; | |
15776 | ||
15777 | mips_tuning_info.arch = mips_arch; | |
15778 | mips_tuning_info.tune = mips_tune; | |
15779 | mips_tuning_info.mips16_p = TARGET_MIPS16; | |
15780 | mips_tuning_info.initialized_p = true; | |
15781 | ||
15782 | dfa_start (); | |
15783 | ||
15784 | struct mips_sim state; | |
15785 | mips_sim_init (&state, alloca (state_size ())); | |
15786 | ||
15787 | mips_set_fast_mult_zero_zero_p (&state); | |
15788 | ||
15789 | dfa_finish (); | |
15790 | } | |
15791 | ||
15792 | /* Implement TARGET_EXPAND_TO_RTL_HOOK. */ | |
15793 | ||
15794 | static void | |
15795 | mips_expand_to_rtl_hook (void) | |
15796 | { | |
15797 | /* We need to call this at a point where we can safely create sequences | |
15798 | of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also | |
15799 | need to call it at a point where the DFA infrastructure is not | |
15800 | already in use, so we can't just call it lazily on demand. | |
15801 | ||
15802 | At present, mips_tuning_info is only needed during post-expand | |
15803 | RTL passes such as split_insns, so this hook should be early enough. | |
15804 | We may need to move the call elsewhere if mips_tuning_info starts | |
15805 | to be used for other things (such as rtx_costs, or expanders that | |
15806 | could be called during gimple optimization). */ | |
15807 | mips_set_tuning_info (); | |
15808 | } | |
ab77a036 RS |
15809 | \f |
15810 | /* The VR4130 pipeline issues aligned pairs of instructions together, | |
15811 | but it stalls the second instruction if it depends on the first. | |
15812 | In order to cut down the amount of logic required, this dependence | |
15813 | check is not based on a full instruction decode. Instead, any non-SPECIAL | |
15814 | instruction is assumed to modify the register specified by bits 20-16 | |
15815 | (which is usually the "rt" field). | |
174bd8ca | 15816 | |
65239d20 | 15817 | In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an |
ab77a036 RS |
15818 | input, so we can end up with a false dependence between the branch |
15819 | and its delay slot. If this situation occurs in instruction INSN, | |
15820 | try to avoid it by swapping rs and rt. */ | |
174bd8ca SL |
15821 | |
15822 | static void | |
c6f971f4 | 15823 | vr4130_avoid_branch_rt_conflict (rtx_insn *insn) |
174bd8ca | 15824 | { |
c6f971f4 | 15825 | rtx_insn *first, *second; |
39ba1719 | 15826 | |
ab77a036 RS |
15827 | first = SEQ_BEGIN (insn); |
15828 | second = SEQ_END (insn); | |
15829 | if (JUMP_P (first) | |
15830 | && NONJUMP_INSN_P (second) | |
15831 | && GET_CODE (PATTERN (first)) == SET | |
15832 | && GET_CODE (SET_DEST (PATTERN (first))) == PC | |
15833 | && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE) | |
39ba1719 | 15834 | { |
ab77a036 RS |
15835 | /* Check for the right kind of condition. */ |
15836 | rtx cond = XEXP (SET_SRC (PATTERN (first)), 0); | |
15837 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
15838 | && REG_P (XEXP (cond, 0)) | |
15839 | && REG_P (XEXP (cond, 1)) | |
15840 | && reg_referenced_p (XEXP (cond, 1), PATTERN (second)) | |
15841 | && !reg_referenced_p (XEXP (cond, 0), PATTERN (second))) | |
15842 | { | |
15843 | /* SECOND mentions the rt register but not the rs register. */ | |
15844 | rtx tmp = XEXP (cond, 0); | |
15845 | XEXP (cond, 0) = XEXP (cond, 1); | |
15846 | XEXP (cond, 1) = tmp; | |
15847 | } | |
39ba1719 | 15848 | } |
39ba1719 RS |
15849 | } |
15850 | ||
ab77a036 RS |
15851 | /* Implement -mvr4130-align. Go through each basic block and simulate the |
15852 | processor pipeline. If we find that a pair of instructions could execute | |
65239d20 | 15853 | in parallel, and the first of those instructions is not 8-byte aligned, |
ab77a036 | 15854 | insert a nop to make it aligned. */ |
0c8da560 | 15855 | |
ab77a036 RS |
15856 | static void |
15857 | vr4130_align_insns (void) | |
b875d2ee | 15858 | { |
ab77a036 | 15859 | struct mips_sim state; |
c6f971f4 | 15860 | rtx_insn *insn, *subinsn, *last, *last2, *next; |
ab77a036 | 15861 | bool aligned_p; |
b875d2ee | 15862 | |
ab77a036 | 15863 | dfa_start (); |
50d32cf6 | 15864 | |
ab77a036 RS |
15865 | /* LAST is the last instruction before INSN to have a nonzero length. |
15866 | LAST2 is the last such instruction before LAST. */ | |
15867 | last = 0; | |
15868 | last2 = 0; | |
54401342 | 15869 | |
ab77a036 RS |
15870 | /* ALIGNED_P is true if INSN is known to be at an aligned address. */ |
15871 | aligned_p = true; | |
50d32cf6 | 15872 | |
ab77a036 RS |
15873 | mips_sim_init (&state, alloca (state_size ())); |
15874 | for (insn = get_insns (); insn != 0; insn = next) | |
15875 | { | |
15876 | unsigned int length; | |
50d32cf6 | 15877 | |
ab77a036 | 15878 | next = NEXT_INSN (insn); |
c81d6e2a | 15879 | |
ab77a036 RS |
15880 | /* See the comment above vr4130_avoid_branch_rt_conflict for details. |
15881 | This isn't really related to the alignment pass, but we do it on | |
15882 | the fly to avoid a separate instruction walk. */ | |
15883 | vr4130_avoid_branch_rt_conflict (insn); | |
c81d6e2a | 15884 | |
d8c51572 RS |
15885 | length = get_attr_length (insn); |
15886 | if (length > 0 && USEFUL_INSN_P (insn)) | |
ab77a036 RS |
15887 | FOR_EACH_SUBINSN (subinsn, insn) |
15888 | { | |
15889 | mips_sim_wait_insn (&state, subinsn); | |
c81d6e2a | 15890 | |
ab77a036 RS |
15891 | /* If we want this instruction to issue in parallel with the |
15892 | previous one, make sure that the previous instruction is | |
15893 | aligned. There are several reasons why this isn't worthwhile | |
15894 | when the second instruction is a call: | |
5ce6f47b | 15895 | |
ab77a036 RS |
15896 | - Calls are less likely to be performance critical, |
15897 | - There's a good chance that the delay slot can execute | |
15898 | in parallel with the call. | |
15899 | - The return address would then be unaligned. | |
4767c570 | 15900 | |
ab77a036 RS |
15901 | In general, if we're going to insert a nop between instructions |
15902 | X and Y, it's better to insert it immediately after X. That | |
15903 | way, if the nop makes Y aligned, it will also align any labels | |
15904 | between X and Y. */ | |
15905 | if (state.insns_left != state.issue_rate | |
15906 | && !CALL_P (subinsn)) | |
15907 | { | |
15908 | if (subinsn == SEQ_BEGIN (insn) && aligned_p) | |
15909 | { | |
15910 | /* SUBINSN is the first instruction in INSN and INSN is | |
15911 | aligned. We want to align the previous instruction | |
15912 | instead, so insert a nop between LAST2 and LAST. | |
8f2e3902 | 15913 | |
ab77a036 RS |
15914 | Note that LAST could be either a single instruction |
15915 | or a branch with a delay slot. In the latter case, | |
15916 | LAST, like INSN, is already aligned, but the delay | |
15917 | slot must have some extra delay that stops it from | |
15918 | issuing at the same time as the branch. We therefore | |
15919 | insert a nop before the branch in order to align its | |
15920 | delay slot. */ | |
d8c51572 | 15921 | gcc_assert (last2); |
ab77a036 RS |
15922 | emit_insn_after (gen_nop (), last2); |
15923 | aligned_p = false; | |
15924 | } | |
15925 | else if (subinsn != SEQ_BEGIN (insn) && !aligned_p) | |
15926 | { | |
15927 | /* SUBINSN is the delay slot of INSN, but INSN is | |
15928 | currently unaligned. Insert a nop between | |
15929 | LAST and INSN to align it. */ | |
d8c51572 | 15930 | gcc_assert (last); |
ab77a036 RS |
15931 | emit_insn_after (gen_nop (), last); |
15932 | aligned_p = true; | |
15933 | } | |
15934 | } | |
15935 | mips_sim_issue_insn (&state, subinsn); | |
15936 | } | |
15937 | mips_sim_finish_insn (&state, insn); | |
06a4ab70 | 15938 | |
ab77a036 RS |
15939 | /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ |
15940 | length = get_attr_length (insn); | |
15941 | if (length > 0) | |
15942 | { | |
15943 | /* If the instruction is an asm statement or multi-instruction | |
15944 | mips.md patern, the length is only an estimate. Insert an | |
15945 | 8 byte alignment after it so that the following instructions | |
15946 | can be handled correctly. */ | |
15947 | if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) | |
15948 | && (recog_memoized (insn) < 0 || length >= 8)) | |
15949 | { | |
15950 | next = emit_insn_after (gen_align (GEN_INT (3)), insn); | |
15951 | next = NEXT_INSN (next); | |
15952 | mips_sim_next_cycle (&state); | |
15953 | aligned_p = true; | |
15954 | } | |
15955 | else if (length & 4) | |
15956 | aligned_p = !aligned_p; | |
15957 | last2 = last; | |
15958 | last = insn; | |
15959 | } | |
4ca1f68f | 15960 | |
ab77a036 RS |
15961 | /* See whether INSN is an aligned label. */ |
15962 | if (LABEL_P (insn) && label_to_alignment (insn) >= 3) | |
15963 | aligned_p = true; | |
15964 | } | |
15965 | dfa_finish (); | |
15966 | } | |
15967 | \f | |
a35de342 RS |
15968 | /* This structure records that the current function has a LO_SUM |
15969 | involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is | |
15970 | the largest offset applied to BASE by all such LO_SUMs. */ | |
15971 | struct mips_lo_sum_offset { | |
15972 | rtx base; | |
15973 | HOST_WIDE_INT offset; | |
15974 | }; | |
15975 | ||
15976 | /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ | |
15977 | ||
15978 | static hashval_t | |
15979 | mips_hash_base (rtx base) | |
15980 | { | |
15981 | int do_not_record_p; | |
15982 | ||
15983 | return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); | |
15984 | } | |
15985 | ||
3a4f280b LC |
15986 | /* Hashtable helpers. */ |
15987 | ||
15988 | struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset> | |
15989 | { | |
15990 | typedef mips_lo_sum_offset value_type; | |
15991 | typedef rtx_def compare_type; | |
15992 | static inline hashval_t hash (const value_type *); | |
15993 | static inline bool equal (const value_type *, const compare_type *); | |
15994 | }; | |
15995 | ||
a35de342 RS |
15996 | /* Hash-table callbacks for mips_lo_sum_offsets. */ |
15997 | ||
3a4f280b LC |
15998 | inline hashval_t |
15999 | mips_lo_sum_offset_hasher::hash (const value_type *entry) | |
a35de342 | 16000 | { |
3a4f280b | 16001 | return mips_hash_base (entry->base); |
a35de342 RS |
16002 | } |
16003 | ||
3a4f280b LC |
16004 | inline bool |
16005 | mips_lo_sum_offset_hasher::equal (const value_type *entry, | |
16006 | const compare_type *value) | |
a35de342 | 16007 | { |
3a4f280b | 16008 | return rtx_equal_p (entry->base, value); |
a35de342 RS |
16009 | } |
16010 | ||
c203e8a7 | 16011 | typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table; |
3a4f280b | 16012 | |
a35de342 RS |
16013 | /* Look up symbolic constant X in HTAB, which is a hash table of |
16014 | mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be | |
16015 | paired with a recorded LO_SUM, otherwise record X in the table. */ | |
16016 | ||
16017 | static bool | |
c203e8a7 | 16018 | mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x, |
3a4f280b | 16019 | enum insert_option option) |
a35de342 RS |
16020 | { |
16021 | rtx base, offset; | |
3a4f280b | 16022 | mips_lo_sum_offset **slot; |
a35de342 RS |
16023 | struct mips_lo_sum_offset *entry; |
16024 | ||
16025 | /* Split X into a base and offset. */ | |
16026 | split_const (x, &base, &offset); | |
16027 | if (UNSPEC_ADDRESS_P (base)) | |
16028 | base = UNSPEC_ADDRESS (base); | |
16029 | ||
16030 | /* Look up the base in the hash table. */ | |
c203e8a7 | 16031 | slot = htab->find_slot_with_hash (base, mips_hash_base (base), option); |
a35de342 RS |
16032 | if (slot == NULL) |
16033 | return false; | |
16034 | ||
16035 | entry = (struct mips_lo_sum_offset *) *slot; | |
16036 | if (option == INSERT) | |
16037 | { | |
16038 | if (entry == NULL) | |
16039 | { | |
16040 | entry = XNEW (struct mips_lo_sum_offset); | |
16041 | entry->base = base; | |
16042 | entry->offset = INTVAL (offset); | |
16043 | *slot = entry; | |
16044 | } | |
16045 | else | |
16046 | { | |
16047 | if (INTVAL (offset) > entry->offset) | |
16048 | entry->offset = INTVAL (offset); | |
16049 | } | |
16050 | } | |
16051 | return INTVAL (offset) <= entry->offset; | |
16052 | } | |
16053 | ||
01333d81 | 16054 | /* Search X for LO_SUMs and record them in HTAB. */ |
a35de342 | 16055 | |
01333d81 RS |
16056 | static void |
16057 | mips_record_lo_sums (const_rtx x, mips_offset_table *htab) | |
a35de342 | 16058 | { |
01333d81 RS |
16059 | subrtx_iterator::array_type array; |
16060 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
16061 | if (GET_CODE (*iter) == LO_SUM) | |
16062 | mips_lo_sum_offset_lookup (htab, XEXP (*iter, 1), INSERT); | |
a35de342 RS |
16063 | } |
16064 | ||
16065 | /* Return true if INSN is a SET of an orphaned high-part relocation. | |
16066 | HTAB is a hash table of mips_lo_sum_offsets that describes all the | |
16067 | LO_SUMs in the current function. */ | |
16068 | ||
16069 | static bool | |
e8a54173 | 16070 | mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn) |
a35de342 RS |
16071 | { |
16072 | enum mips_symbol_type type; | |
16073 | rtx x, set; | |
16074 | ||
16075 | set = single_set (insn); | |
16076 | if (set) | |
16077 | { | |
16078 | /* Check for %his. */ | |
16079 | x = SET_SRC (set); | |
16080 | if (GET_CODE (x) == HIGH | |
16081 | && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) | |
16082 | return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); | |
16083 | ||
16084 | /* Check for local %gots (and %got_pages, which is redundant but OK). */ | |
16085 | if (GET_CODE (x) == UNSPEC | |
16086 | && XINT (x, 1) == UNSPEC_LOAD_GOT | |
16087 | && mips_symbolic_constant_p (XVECEXP (x, 0, 1), | |
16088 | SYMBOL_CONTEXT_LEA, &type) | |
16089 | && type == SYMBOL_GOTOFF_PAGE) | |
16090 | return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT); | |
16091 | } | |
16092 | return false; | |
16093 | } | |
16094 | ||
16095 | /* Subroutine of mips_reorg_process_insns. If there is a hazard between | |
16096 | INSN and a previous instruction, avoid it by inserting nops after | |
ab77a036 | 16097 | instruction AFTER. |
308cd611 | 16098 | |
ab77a036 RS |
16099 | *DELAYED_REG and *HILO_DELAY describe the hazards that apply at |
16100 | this point. If *DELAYED_REG is non-null, INSN must wait a cycle | |
16101 | before using the value of that register. *HILO_DELAY counts the | |
16102 | number of instructions since the last hilo hazard (that is, | |
65239d20 | 16103 | the number of instructions since the last MFLO or MFHI). |
4ca1f68f | 16104 | |
ab77a036 RS |
16105 | After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY |
16106 | for the next instruction. | |
4ca1f68f | 16107 | |
ab77a036 | 16108 | LO_REG is an rtx for the LO register, used in dependence checking. */ |
4ca1f68f | 16109 | |
ab77a036 | 16110 | static void |
c6f971f4 | 16111 | mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, |
ab77a036 RS |
16112 | rtx *delayed_reg, rtx lo_reg) |
16113 | { | |
16114 | rtx pattern, set; | |
dbc90b65 | 16115 | int nops, ninsns; |
06a4ab70 | 16116 | |
ab77a036 | 16117 | pattern = PATTERN (insn); |
4ca1f68f | 16118 | |
ab77a036 RS |
16119 | /* Do not put the whole function in .set noreorder if it contains |
16120 | an asm statement. We don't know whether there will be hazards | |
16121 | between the asm statement and the gcc-generated code. */ | |
16122 | if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0) | |
16123 | cfun->machine->all_noreorder_p = false; | |
4ca1f68f | 16124 | |
ab77a036 RS |
16125 | /* Ignore zero-length instructions (barriers and the like). */ |
16126 | ninsns = get_attr_length (insn) / 4; | |
16127 | if (ninsns == 0) | |
16128 | return; | |
4ca1f68f | 16129 | |
ab77a036 RS |
16130 | /* Work out how many nops are needed. Note that we only care about |
16131 | registers that are explicitly mentioned in the instruction's pattern. | |
16132 | It doesn't matter that calls use the argument registers or that they | |
16133 | clobber hi and lo. */ | |
16134 | if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) | |
16135 | nops = 2 - *hilo_delay; | |
16136 | else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) | |
16137 | nops = 1; | |
16138 | else | |
16139 | nops = 0; | |
4ca1f68f | 16140 | |
ab77a036 RS |
16141 | /* Insert the nops between this instruction and the previous one. |
16142 | Each new nop takes us further from the last hilo hazard. */ | |
16143 | *hilo_delay += nops; | |
16144 | while (nops-- > 0) | |
16145 | emit_insn_after (gen_hazard_nop (), after); | |
4ca1f68f | 16146 | |
ab77a036 RS |
16147 | /* Set up the state for the next instruction. */ |
16148 | *hilo_delay += ninsns; | |
16149 | *delayed_reg = 0; | |
16150 | if (INSN_CODE (insn) >= 0) | |
16151 | switch (get_attr_hazard (insn)) | |
16152 | { | |
16153 | case HAZARD_NONE: | |
16154 | break; | |
21c425ee | 16155 | |
ab77a036 RS |
16156 | case HAZARD_HILO: |
16157 | *hilo_delay = 0; | |
16158 | break; | |
4ca1f68f | 16159 | |
ab77a036 | 16160 | case HAZARD_DELAY: |
dbc90b65 RS |
16161 | set = single_set (insn); |
16162 | gcc_assert (set); | |
ab77a036 RS |
16163 | *delayed_reg = SET_DEST (set); |
16164 | break; | |
16165 | } | |
16166 | } | |
4ca1f68f | 16167 | |
ab77a036 | 16168 | /* Go through the instruction stream and insert nops where necessary. |
a35de342 RS |
16169 | Also delete any high-part relocations whose partnering low parts |
16170 | are now all dead. See if the whole function can then be put into | |
16171 | .set noreorder and .set nomacro. */ | |
06a4ab70 | 16172 | |
ab77a036 | 16173 | static void |
a35de342 | 16174 | mips_reorg_process_insns (void) |
ab77a036 | 16175 | { |
c6f971f4 DM |
16176 | rtx_insn *insn, *last_insn, *subinsn, *next_insn; |
16177 | rtx lo_reg, delayed_reg; | |
a35de342 | 16178 | int hilo_delay; |
1823bf53 | 16179 | |
ab77a036 RS |
16180 | /* Force all instructions to be split into their final form. */ |
16181 | split_all_insns_noflow (); | |
1823bf53 | 16182 | |
ab77a036 RS |
16183 | /* Recalculate instruction lengths without taking nops into account. */ |
16184 | cfun->machine->ignore_hazard_length_p = true; | |
16185 | shorten_branches (get_insns ()); | |
1823bf53 | 16186 | |
ab77a036 | 16187 | cfun->machine->all_noreorder_p = true; |
118ea793 | 16188 | |
08d0963a RS |
16189 | /* We don't track MIPS16 PC-relative offsets closely enough to make |
16190 | a good job of "set .noreorder" code in MIPS16 mode. */ | |
16191 | if (TARGET_MIPS16) | |
16192 | cfun->machine->all_noreorder_p = false; | |
16193 | ||
a35de342 RS |
16194 | /* Code that doesn't use explicit relocs can't be ".set nomacro". */ |
16195 | if (!TARGET_EXPLICIT_RELOCS) | |
16196 | cfun->machine->all_noreorder_p = false; | |
16197 | ||
ab77a036 RS |
16198 | /* Profiled functions can't be all noreorder because the profiler |
16199 | support uses assembler macros. */ | |
e3b5732b | 16200 | if (crtl->profile) |
ab77a036 | 16201 | cfun->machine->all_noreorder_p = false; |
118ea793 | 16202 | |
faaa3afb CM |
16203 | /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be |
16204 | all noreorder because we rely on the assembler to work around some | |
16205 | errata. The R5900 too has several bugs. */ | |
16206 | if (TARGET_FIX_VR4120 | |
16207 | || TARGET_FIX_RM7000 | |
16208 | || TARGET_FIX_24K | |
16209 | || TARGET_MIPS5900) | |
ab77a036 | 16210 | cfun->machine->all_noreorder_p = false; |
118ea793 | 16211 | |
65239d20 RS |
16212 | /* The same is true for -mfix-vr4130 if we might generate MFLO or |
16213 | MFHI instructions. Note that we avoid using MFLO and MFHI if | |
16214 | the VR4130 MACC and DMACC instructions are available instead; | |
ab77a036 RS |
16215 | see the *mfhilo_{si,di}_macc patterns. */ |
16216 | if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI) | |
16217 | cfun->machine->all_noreorder_p = false; | |
118ea793 | 16218 | |
c203e8a7 | 16219 | mips_offset_table htab (37); |
a35de342 RS |
16220 | |
16221 | /* Make a first pass over the instructions, recording all the LO_SUMs. */ | |
16222 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
16223 | FOR_EACH_SUBINSN (subinsn, insn) | |
006b29ab | 16224 | if (USEFUL_INSN_P (subinsn)) |
f9ae4df8 RS |
16225 | { |
16226 | rtx body = PATTERN (insn); | |
16227 | int noperands = asm_noperands (body); | |
16228 | if (noperands >= 0) | |
16229 | { | |
16230 | rtx *ops = XALLOCAVEC (rtx, noperands); | |
16231 | bool *used = XALLOCAVEC (bool, noperands); | |
16232 | const char *string = decode_asm_operands (body, ops, NULL, NULL, | |
16233 | NULL, NULL); | |
16234 | get_referenced_operands (string, used, noperands); | |
16235 | for (int i = 0; i < noperands; ++i) | |
16236 | if (used[i]) | |
01333d81 | 16237 | mips_record_lo_sums (ops[i], &htab); |
f9ae4df8 RS |
16238 | } |
16239 | else | |
01333d81 | 16240 | mips_record_lo_sums (PATTERN (subinsn), &htab); |
f9ae4df8 | 16241 | } |
a35de342 | 16242 | |
ab77a036 RS |
16243 | last_insn = 0; |
16244 | hilo_delay = 2; | |
16245 | delayed_reg = 0; | |
16246 | lo_reg = gen_rtx_REG (SImode, LO_REGNUM); | |
32041385 | 16247 | |
a35de342 RS |
16248 | /* Make a second pass over the instructions. Delete orphaned |
16249 | high-part relocations or turn them into NOPs. Avoid hazards | |
16250 | by inserting NOPs. */ | |
16251 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
16252 | { | |
16253 | next_insn = NEXT_INSN (insn); | |
006b29ab | 16254 | if (USEFUL_INSN_P (insn)) |
a35de342 RS |
16255 | { |
16256 | if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
16257 | { | |
16258 | /* If we find an orphaned high-part relocation in a delay | |
16259 | slot, it's easier to turn that instruction into a NOP than | |
16260 | to delete it. The delay slot will be a NOP either way. */ | |
16261 | FOR_EACH_SUBINSN (subinsn, insn) | |
16262 | if (INSN_P (subinsn)) | |
16263 | { | |
c203e8a7 | 16264 | if (mips_orphaned_high_part_p (&htab, subinsn)) |
a35de342 RS |
16265 | { |
16266 | PATTERN (subinsn) = gen_nop (); | |
16267 | INSN_CODE (subinsn) = CODE_FOR_nop; | |
16268 | } | |
16269 | mips_avoid_hazard (last_insn, subinsn, &hilo_delay, | |
16270 | &delayed_reg, lo_reg); | |
16271 | } | |
16272 | last_insn = insn; | |
16273 | } | |
16274 | else | |
16275 | { | |
16276 | /* INSN is a single instruction. Delete it if it's an | |
16277 | orphaned high-part relocation. */ | |
c203e8a7 | 16278 | if (mips_orphaned_high_part_p (&htab, insn)) |
a35de342 | 16279 | delete_insn (insn); |
4d210b07 RS |
16280 | /* Also delete cache barriers if the last instruction |
16281 | was an annulled branch. INSN will not be speculatively | |
16282 | executed. */ | |
16283 | else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier | |
16284 | && last_insn | |
9e187b31 | 16285 | && JUMP_P (SEQ_BEGIN (last_insn)) |
4d210b07 RS |
16286 | && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn))) |
16287 | delete_insn (insn); | |
a35de342 RS |
16288 | else |
16289 | { | |
16290 | mips_avoid_hazard (last_insn, insn, &hilo_delay, | |
16291 | &delayed_reg, lo_reg); | |
16292 | last_insn = insn; | |
16293 | } | |
16294 | } | |
16295 | } | |
16296 | } | |
ab77a036 RS |
16297 | } |
16298 | ||
a1c741f0 | 16299 | /* Return true if the function has a long branch instruction. */ |
0c433c31 RS |
16300 | |
16301 | static bool | |
a1c741f0 | 16302 | mips_has_long_branch_p (void) |
0c433c31 | 16303 | { |
c6f971f4 | 16304 | rtx_insn *insn, *subinsn; |
0c433c31 RS |
16305 | int normal_length; |
16306 | ||
a1c741f0 | 16307 | /* We need up-to-date instruction lengths. */ |
0c433c31 RS |
16308 | shorten_branches (get_insns ()); |
16309 | ||
16310 | /* Look for a branch that is longer than normal. The normal length for | |
16311 | non-MIPS16 branches is 8, because the length includes the delay slot. | |
16312 | It is 4 for MIPS16, because MIPS16 branches are extended instructions, | |
16313 | but they have no delay slot. */ | |
16314 | normal_length = (TARGET_MIPS16 ? 4 : 8); | |
16315 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
a1c741f0 RS |
16316 | FOR_EACH_SUBINSN (subinsn, insn) |
16317 | if (JUMP_P (subinsn) | |
a1c741f0 RS |
16318 | && get_attr_length (subinsn) > normal_length |
16319 | && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn))) | |
16320 | return true; | |
16321 | ||
16322 | return false; | |
16323 | } | |
16324 | ||
16325 | /* If we are using a GOT, but have not decided to use a global pointer yet, | |
16326 | see whether we need one to implement long branches. Convert the ghost | |
16327 | global-pointer instructions into real ones if so. */ | |
16328 | ||
16329 | static bool | |
16330 | mips_expand_ghost_gp_insns (void) | |
16331 | { | |
16332 | /* Quick exit if we already know that we will or won't need a | |
16333 | global pointer. */ | |
16334 | if (!TARGET_USE_GOT | |
16335 | || cfun->machine->global_pointer == INVALID_REGNUM | |
16336 | || mips_must_initialize_gp_p ()) | |
16337 | return false; | |
0c433c31 | 16338 | |
a1c741f0 RS |
16339 | /* Run a full check for long branches. */ |
16340 | if (!mips_has_long_branch_p ()) | |
0c433c31 RS |
16341 | return false; |
16342 | ||
16343 | /* We've now established that we need $gp. */ | |
16344 | cfun->machine->must_initialize_gp_p = true; | |
16345 | split_all_insns_noflow (); | |
16346 | ||
16347 | return true; | |
16348 | } | |
16349 | ||
b53da244 AN |
16350 | /* Subroutine of mips_reorg to manage passes that require DF. */ |
16351 | ||
16352 | static void | |
16353 | mips_df_reorg (void) | |
16354 | { | |
16355 | /* Create def-use chains. */ | |
16356 | df_set_flags (DF_EQ_NOTES); | |
16357 | df_chain_add_problem (DF_UD_CHAIN); | |
16358 | df_analyze (); | |
16359 | ||
16360 | if (TARGET_RELAX_PIC_CALLS) | |
16361 | mips_annotate_pic_calls (); | |
16362 | ||
16363 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE) | |
16364 | r10k_insert_cache_barriers (); | |
16365 | ||
16366 | df_finish_pass (false); | |
16367 | } | |
16368 | ||
36be1dee RS |
16369 | /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is |
16370 | called very late in mips_reorg, but the caller is required to run | |
16371 | mips16_lay_out_constants on the result. */ | |
16372 | ||
16373 | static void | |
16374 | mips16_load_branch_target (rtx dest, rtx src) | |
16375 | { | |
16376 | if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) | |
16377 | { | |
16378 | rtx page, low; | |
16379 | ||
16380 | if (mips_cfun_has_cprestore_slot_p ()) | |
16381 | mips_emit_move (dest, mips_cprestore_slot (dest, true)); | |
16382 | else | |
16383 | mips_emit_move (dest, pic_offset_table_rtx); | |
16384 | page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE); | |
16385 | low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST); | |
16386 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
16387 | PMODE_INSN (gen_unspec_got, (dest, page)))); | |
16388 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
16389 | gen_rtx_LO_SUM (Pmode, dest, low))); | |
16390 | } | |
16391 | else | |
16392 | { | |
16393 | src = mips_unspec_address (src, SYMBOL_ABSOLUTE); | |
16394 | mips_emit_move (dest, src); | |
16395 | } | |
16396 | } | |
16397 | ||
16398 | /* If we're compiling a MIPS16 function, look for and split any long branches. | |
16399 | This must be called after all other instruction modifications in | |
16400 | mips_reorg. */ | |
16401 | ||
16402 | static void | |
16403 | mips16_split_long_branches (void) | |
16404 | { | |
16405 | bool something_changed; | |
16406 | ||
16407 | if (!TARGET_MIPS16) | |
16408 | return; | |
16409 | ||
16410 | /* Loop until the alignments for all targets are sufficient. */ | |
16411 | do | |
16412 | { | |
c6f971f4 | 16413 | rtx_insn *insn; |
36be1dee RS |
16414 | |
16415 | shorten_branches (get_insns ()); | |
16416 | something_changed = false; | |
16417 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
16418 | if (JUMP_P (insn) | |
da734fa1 | 16419 | && get_attr_length (insn) > 4 |
545ca0f2 | 16420 | && (any_condjump_p (insn) || any_uncondjump_p (insn))) |
36be1dee | 16421 | { |
19f8b229 TS |
16422 | rtx old_label, temp, saved_temp; |
16423 | rtx_code_label *new_label; | |
c6f971f4 DM |
16424 | rtx target; |
16425 | rtx_insn *jump, *jump_sequence; | |
36be1dee RS |
16426 | |
16427 | start_sequence (); | |
16428 | ||
16429 | /* Free up a MIPS16 register by saving it in $1. */ | |
16430 | saved_temp = gen_rtx_REG (Pmode, AT_REGNUM); | |
16431 | temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); | |
16432 | emit_move_insn (saved_temp, temp); | |
16433 | ||
16434 | /* Load the branch target into TEMP. */ | |
16435 | old_label = JUMP_LABEL (insn); | |
16436 | target = gen_rtx_LABEL_REF (Pmode, old_label); | |
16437 | mips16_load_branch_target (temp, target); | |
16438 | ||
16439 | /* Jump to the target and restore the register's | |
16440 | original value. */ | |
16441 | jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore, | |
16442 | (temp, temp, saved_temp))); | |
16443 | JUMP_LABEL (jump) = old_label; | |
16444 | LABEL_NUSES (old_label)++; | |
16445 | ||
16446 | /* Rewrite any symbolic references that are supposed to use | |
16447 | a PC-relative constant pool. */ | |
16448 | mips16_lay_out_constants (false); | |
16449 | ||
16450 | if (simplejump_p (insn)) | |
16451 | /* We're going to replace INSN with a longer form. */ | |
19f8b229 | 16452 | new_label = NULL; |
36be1dee RS |
16453 | else |
16454 | { | |
16455 | /* Create a branch-around label for the original | |
16456 | instruction. */ | |
16457 | new_label = gen_label_rtx (); | |
16458 | emit_label (new_label); | |
16459 | } | |
16460 | ||
16461 | jump_sequence = get_insns (); | |
16462 | end_sequence (); | |
16463 | ||
16464 | emit_insn_after (jump_sequence, insn); | |
16465 | if (new_label) | |
16466 | invert_jump (insn, new_label, false); | |
16467 | else | |
16468 | delete_insn (insn); | |
16469 | something_changed = true; | |
16470 | } | |
16471 | } | |
16472 | while (something_changed); | |
16473 | } | |
16474 | ||
ab77a036 RS |
16475 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ |
16476 | ||
16477 | static void | |
16478 | mips_reorg (void) | |
32041385 | 16479 | { |
b53da244 AN |
16480 | /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during |
16481 | insn splitting in mips16_lay_out_constants, DF insn info is only kept up | |
16482 | to date if the CFG is available. */ | |
16483 | if (mips_cfg_in_reorg ()) | |
16484 | compute_bb_for_insn (); | |
36be1dee | 16485 | mips16_lay_out_constants (true); |
b53da244 AN |
16486 | if (mips_cfg_in_reorg ()) |
16487 | { | |
16488 | mips_df_reorg (); | |
16489 | free_bb_for_insn (); | |
16490 | } | |
fb0d5c60 | 16491 | } |
b53da244 | 16492 | |
fb0d5c60 SB |
16493 | /* We use a machine specific pass to do a second machine dependent reorg |
16494 | pass after delay branch scheduling. */ | |
16495 | ||
16496 | static unsigned int | |
16497 | mips_machine_reorg2 (void) | |
16498 | { | |
a35de342 | 16499 | mips_reorg_process_insns (); |
08d0963a RS |
16500 | if (!TARGET_MIPS16 |
16501 | && TARGET_EXPLICIT_RELOCS | |
16502 | && TUNE_MIPS4130 | |
16503 | && TARGET_VR4130_ALIGN) | |
a35de342 | 16504 | vr4130_align_insns (); |
0c433c31 RS |
16505 | if (mips_expand_ghost_gp_insns ()) |
16506 | /* The expansion could invalidate some of the VR4130 alignment | |
16507 | optimizations, but this should be an extremely rare case anyhow. */ | |
16508 | mips_reorg_process_insns (); | |
36be1dee | 16509 | mips16_split_long_branches (); |
4ffecb1f | 16510 | return 0; |
ab77a036 | 16511 | } |
fb0d5c60 | 16512 | |
27a4cd48 DM |
16513 | namespace { |
16514 | ||
16515 | const pass_data pass_data_mips_machine_reorg2 = | |
16516 | { | |
16517 | RTL_PASS, /* type */ | |
16518 | "mach2", /* name */ | |
16519 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
16520 | TV_MACH_DEP, /* tv_id */ |
16521 | 0, /* properties_required */ | |
16522 | 0, /* properties_provided */ | |
16523 | 0, /* properties_destroyed */ | |
16524 | 0, /* todo_flags_start */ | |
3bea341f | 16525 | 0, /* todo_flags_finish */ |
fb0d5c60 SB |
16526 | }; |
16527 | ||
27a4cd48 DM |
16528 | class pass_mips_machine_reorg2 : public rtl_opt_pass |
16529 | { | |
16530 | public: | |
16531 | pass_mips_machine_reorg2(gcc::context *ctxt) | |
16532 | : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt) | |
16533 | {} | |
16534 | ||
16535 | /* opt_pass methods: */ | |
be55bfe6 | 16536 | virtual unsigned int execute (function *) { return mips_machine_reorg2 (); } |
27a4cd48 DM |
16537 | |
16538 | }; // class pass_mips_machine_reorg2 | |
16539 | ||
16540 | } // anon namespace | |
16541 | ||
16542 | rtl_opt_pass * | |
16543 | make_pass_mips_machine_reorg2 (gcc::context *ctxt) | |
16544 | { | |
16545 | return new pass_mips_machine_reorg2 (ctxt); | |
16546 | } | |
16547 | ||
ab77a036 RS |
16548 | \f |
16549 | /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text | |
16550 | in order to avoid duplicating too much logic from elsewhere. */ | |
32041385 | 16551 | |
ab77a036 RS |
16552 | static void |
16553 | mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | |
16554 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
16555 | tree function) | |
16556 | { | |
c6f971f4 DM |
16557 | rtx this_rtx, temp1, temp2, fnaddr; |
16558 | rtx_insn *insn; | |
ab77a036 RS |
16559 | bool use_sibcall_p; |
16560 | ||
16561 | /* Pretend to be a post-reload pass while generating rtl. */ | |
16562 | reload_completed = 1; | |
16563 | ||
16564 | /* Mark the end of the (empty) prologue. */ | |
16565 | emit_note (NOTE_INSN_PROLOGUE_END); | |
16566 | ||
16567 | /* Determine if we can use a sibcall to call FUNCTION directly. */ | |
16568 | fnaddr = XEXP (DECL_RTL (function), 0); | |
16569 | use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL) | |
16570 | && const_call_insn_operand (fnaddr, Pmode)); | |
16571 | ||
16572 | /* Determine if we need to load FNADDR from the GOT. */ | |
08d0963a RS |
16573 | if (!use_sibcall_p |
16574 | && (mips_got_symbol_type_p | |
16575 | (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA)))) | |
16576 | { | |
16577 | /* Pick a global pointer. Use a call-clobbered register if | |
16578 | TARGET_CALL_SAVED_GP. */ | |
16579 | cfun->machine->global_pointer | |
16580 | = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM; | |
0c433c31 | 16581 | cfun->machine->must_initialize_gp_p = true; |
08d0963a | 16582 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); |
ab77a036 | 16583 | |
08d0963a RS |
16584 | /* Set up the global pointer for n32 or n64 abicalls. */ |
16585 | mips_emit_loadgp (); | |
16586 | } | |
ab77a036 RS |
16587 | |
16588 | /* We need two temporary registers in some cases. */ | |
16589 | temp1 = gen_rtx_REG (Pmode, 2); | |
16590 | temp2 = gen_rtx_REG (Pmode, 3); | |
16591 | ||
16592 | /* Find out which register contains the "this" pointer. */ | |
16593 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
0a2aaacc | 16594 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); |
ab77a036 | 16595 | else |
0a2aaacc | 16596 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); |
ab77a036 | 16597 | |
0a2aaacc | 16598 | /* Add DELTA to THIS_RTX. */ |
ab77a036 RS |
16599 | if (delta != 0) |
16600 | { | |
16601 | rtx offset = GEN_INT (delta); | |
16602 | if (!SMALL_OPERAND (delta)) | |
16603 | { | |
16604 | mips_emit_move (temp1, offset); | |
16605 | offset = temp1; | |
16606 | } | |
0a2aaacc | 16607 | emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); |
ab77a036 RS |
16608 | } |
16609 | ||
0a2aaacc | 16610 | /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ |
ab77a036 RS |
16611 | if (vcall_offset != 0) |
16612 | { | |
16613 | rtx addr; | |
16614 | ||
0a2aaacc KG |
16615 | /* Set TEMP1 to *THIS_RTX. */ |
16616 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); | |
ab77a036 | 16617 | |
0a2aaacc | 16618 | /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ |
ab77a036 RS |
16619 | addr = mips_add_offset (temp2, temp1, vcall_offset); |
16620 | ||
0a2aaacc | 16621 | /* Load the offset and add it to THIS_RTX. */ |
ab77a036 | 16622 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); |
0a2aaacc | 16623 | emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); |
ab77a036 RS |
16624 | } |
16625 | ||
16626 | /* Jump to the target function. Use a sibcall if direct jumps are | |
16627 | allowed, otherwise load the address into a register first. */ | |
16628 | if (use_sibcall_p) | |
16629 | { | |
16630 | insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); | |
16631 | SIBLING_CALL_P (insn) = 1; | |
16632 | } | |
16633 | else | |
16634 | { | |
65239d20 | 16635 | /* This is messy. GAS treats "la $25,foo" as part of a call |
ab77a036 RS |
16636 | sequence and may allow a global "foo" to be lazily bound. |
16637 | The general move patterns therefore reject this combination. | |
16638 | ||
16639 | In this context, lazy binding would actually be OK | |
16640 | for TARGET_CALL_CLOBBERED_GP, but it's still wrong for | |
16641 | TARGET_CALL_SAVED_GP; see mips_load_call_address. | |
16642 | We must therefore load the address via a temporary | |
16643 | register if mips_dangerous_for_la25_p. | |
16644 | ||
08d0963a RS |
16645 | If we jump to the temporary register rather than $25, |
16646 | the assembler can use the move insn to fill the jump's | |
16647 | delay slot. | |
16648 | ||
16649 | We can use the same technique for MIPS16 code, where $25 | |
16650 | is not a valid JR register. */ | |
ab77a036 | 16651 | if (TARGET_USE_PIC_FN_ADDR_REG |
08d0963a | 16652 | && !TARGET_MIPS16 |
ab77a036 RS |
16653 | && !mips_dangerous_for_la25_p (fnaddr)) |
16654 | temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
08d0963a | 16655 | mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr); |
ab77a036 RS |
16656 | |
16657 | if (TARGET_USE_PIC_FN_ADDR_REG | |
16658 | && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM) | |
16659 | mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1); | |
16660 | emit_jump_insn (gen_indirect_jump (temp1)); | |
16661 | } | |
16662 | ||
16663 | /* Run just enough of rest_of_compilation. This sequence was | |
16664 | "borrowed" from alpha.c. */ | |
16665 | insn = get_insns (); | |
ab77a036 | 16666 | split_all_insns_noflow (); |
36be1dee | 16667 | mips16_lay_out_constants (true); |
ab77a036 RS |
16668 | shorten_branches (insn); |
16669 | final_start_function (insn, file, 1); | |
16670 | final (insn, file, 1); | |
16671 | final_end_function (); | |
16672 | ||
16673 | /* Clean up the vars set above. Note that final_end_function resets | |
16674 | the global pointer for us. */ | |
16675 | reload_completed = 0; | |
16676 | } | |
16677 | \f | |
ab77a036 | 16678 | |
22c4c869 CM |
16679 | /* The last argument passed to mips_set_compression_mode, |
16680 | or negative if the function hasn't been called yet. */ | |
16681 | static unsigned int old_compression_mode = -1; | |
16682 | ||
16683 | /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE, | |
16684 | which is either MASK_MIPS16 or MASK_MICROMIPS. */ | |
ab77a036 RS |
16685 | |
16686 | static void | |
22c4c869 | 16687 | mips_set_compression_mode (unsigned int compression_mode) |
ab77a036 | 16688 | { |
22c4c869 CM |
16689 | |
16690 | if (compression_mode == old_compression_mode) | |
ab77a036 RS |
16691 | return; |
16692 | ||
16693 | /* Restore base settings of various flags. */ | |
16694 | target_flags = mips_base_target_flags; | |
ab77a036 RS |
16695 | flag_schedule_insns = mips_base_schedule_insns; |
16696 | flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition; | |
16697 | flag_move_loop_invariants = mips_base_move_loop_invariants; | |
16698 | align_loops = mips_base_align_loops; | |
16699 | align_jumps = mips_base_align_jumps; | |
16700 | align_functions = mips_base_align_functions; | |
22c4c869 CM |
16701 | target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS); |
16702 | target_flags |= compression_mode; | |
ab77a036 | 16703 | |
22c4c869 | 16704 | if (compression_mode & MASK_MIPS16) |
ab77a036 | 16705 | { |
65239d20 | 16706 | /* Switch to MIPS16 mode. */ |
ab77a036 RS |
16707 | target_flags |= MASK_MIPS16; |
16708 | ||
fdb45c0c SE |
16709 | /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */ |
16710 | target_flags &= ~MASK_SYNCI; | |
16711 | ||
ab77a036 RS |
16712 | /* Don't run the scheduler before reload, since it tends to |
16713 | increase register pressure. */ | |
16714 | flag_schedule_insns = 0; | |
16715 | ||
65239d20 | 16716 | /* Don't do hot/cold partitioning. mips16_lay_out_constants expects |
ab77a036 RS |
16717 | the whole function to be in a single section. */ |
16718 | flag_reorder_blocks_and_partition = 0; | |
16719 | ||
16720 | /* Don't move loop invariants, because it tends to increase | |
16721 | register pressure. It also introduces an extra move in cases | |
16722 | where the constant is the first operand in a two-operand binary | |
16723 | instruction, or when it forms a register argument to a functon | |
16724 | call. */ | |
16725 | flag_move_loop_invariants = 0; | |
16726 | ||
08d0963a | 16727 | target_flags |= MASK_EXPLICIT_RELOCS; |
ab77a036 | 16728 | |
65239d20 RS |
16729 | /* Experiments suggest we get the best overall section-anchor |
16730 | results from using the range of an unextended LW or SW. Code | |
16731 | that makes heavy use of byte or short accesses can do better | |
16732 | with ranges of 0...31 and 0...63 respectively, but most code is | |
16733 | sensitive to the range of LW and SW instead. */ | |
ab77a036 RS |
16734 | targetm.min_anchor_offset = 0; |
16735 | targetm.max_anchor_offset = 127; | |
16736 | ||
2c5bfdf7 AN |
16737 | targetm.const_anchor = 0; |
16738 | ||
b53da244 AN |
16739 | /* MIPS16 has no BAL instruction. */ |
16740 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
16741 | ||
a2ccf3c2 RS |
16742 | /* The R4000 errata don't apply to any known MIPS16 cores. |
16743 | It's simpler to make the R4000 fixes and MIPS16 mode | |
16744 | mutually exclusive. */ | |
16745 | target_flags &= ~MASK_FIX_R4000; | |
16746 | ||
08d0963a RS |
16747 | if (flag_pic && !TARGET_OLDABI) |
16748 | sorry ("MIPS16 PIC for ABIs other than o32 and o64"); | |
16749 | ||
16750 | if (TARGET_XGOT) | |
16751 | sorry ("MIPS16 -mxgot code"); | |
d375fd5e RS |
16752 | |
16753 | if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI) | |
16754 | sorry ("hard-float MIPS16 code for ABIs other than o32 and o64"); | |
ab77a036 RS |
16755 | } |
16756 | else | |
16757 | { | |
22c4c869 CM |
16758 | /* Switch to microMIPS or the standard encoding. */ |
16759 | ||
16760 | if (TARGET_MICROMIPS) | |
16761 | /* Avoid branch likely. */ | |
16762 | target_flags &= ~MASK_BRANCHLIKELY; | |
ab77a036 | 16763 | |
ab77a036 RS |
16764 | /* Provide default values for align_* for 64-bit targets. */ |
16765 | if (TARGET_64BIT) | |
16766 | { | |
16767 | if (align_loops == 0) | |
16768 | align_loops = 8; | |
16769 | if (align_jumps == 0) | |
16770 | align_jumps = 8; | |
16771 | if (align_functions == 0) | |
16772 | align_functions = 8; | |
16773 | } | |
1823bf53 | 16774 | |
ab77a036 RS |
16775 | targetm.min_anchor_offset = -32768; |
16776 | targetm.max_anchor_offset = 32767; | |
2c5bfdf7 AN |
16777 | |
16778 | targetm.const_anchor = 0x8000; | |
ab77a036 | 16779 | } |
1823bf53 | 16780 | |
65239d20 | 16781 | /* (Re)initialize MIPS target internals for new ISA. */ |
ab77a036 | 16782 | mips_init_relocs (); |
1823bf53 | 16783 | |
22c4c869 | 16784 | if (compression_mode & MASK_MIPS16) |
5aa62249 RS |
16785 | { |
16786 | if (!mips16_globals) | |
135204dd | 16787 | mips16_globals = save_target_globals_default_opts (); |
5aa62249 RS |
16788 | else |
16789 | restore_target_globals (mips16_globals); | |
16790 | } | |
16791 | else | |
16792 | restore_target_globals (&default_target_globals); | |
32041385 | 16793 | |
22c4c869 | 16794 | old_compression_mode = compression_mode; |
ab77a036 | 16795 | } |
1823bf53 | 16796 | |
ab77a036 | 16797 | /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current |
22c4c869 CM |
16798 | function should use the MIPS16 or microMIPS ISA and switch modes |
16799 | accordingly. */ | |
ab77a036 RS |
16800 | |
16801 | static void | |
16802 | mips_set_current_function (tree fndecl) | |
1823bf53 | 16803 | { |
22c4c869 | 16804 | mips_set_compression_mode (mips_get_compress_mode (fndecl)); |
ab77a036 RS |
16805 | } |
16806 | \f | |
16807 | /* Allocate a chunk of memory for per-function machine-dependent data. */ | |
65239d20 | 16808 | |
ab77a036 RS |
16809 | static struct machine_function * |
16810 | mips_init_machine_status (void) | |
16811 | { | |
766090c2 | 16812 | return ggc_cleared_alloc<machine_function> (); |
ab77a036 | 16813 | } |
06a4ab70 | 16814 | |
ab77a036 RS |
16815 | /* Return the processor associated with the given ISA level, or null |
16816 | if the ISA isn't valid. */ | |
ff55fb9c | 16817 | |
ab77a036 RS |
16818 | static const struct mips_cpu_info * |
16819 | mips_cpu_info_from_isa (int isa) | |
ff55fb9c | 16820 | { |
ab77a036 | 16821 | unsigned int i; |
ff55fb9c | 16822 | |
ab77a036 RS |
16823 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
16824 | if (mips_cpu_info_table[i].isa == isa) | |
16825 | return mips_cpu_info_table + i; | |
ff55fb9c | 16826 | |
65239d20 | 16827 | return NULL; |
ff55fb9c RS |
16828 | } |
16829 | ||
d371df6f JM |
16830 | /* Return a mips_cpu_info entry determined by an option valued |
16831 | OPT. */ | |
ff55fb9c | 16832 | |
d371df6f JM |
16833 | static const struct mips_cpu_info * |
16834 | mips_cpu_info_from_opt (int opt) | |
ab77a036 | 16835 | { |
d371df6f JM |
16836 | switch (opt) |
16837 | { | |
16838 | case MIPS_ARCH_OPTION_FROM_ABI: | |
16839 | /* 'from-abi' selects the most compatible architecture for the | |
16840 | given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit | |
16841 | ABIs. For the EABIs, we have to decide whether we're using | |
16842 | the 32-bit or 64-bit version. */ | |
16843 | return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1 | |
16844 | : ABI_NEEDS_64BIT_REGS ? 3 | |
16845 | : (TARGET_64BIT ? 3 : 1)); | |
ab77a036 | 16846 | |
d371df6f JM |
16847 | case MIPS_ARCH_OPTION_NATIVE: |
16848 | gcc_unreachable (); | |
ab77a036 | 16849 | |
d371df6f JM |
16850 | default: |
16851 | return &mips_cpu_info_table[opt]; | |
16852 | } | |
ff55fb9c RS |
16853 | } |
16854 | ||
d371df6f JM |
16855 | /* Return a default mips_cpu_info entry, given that no -march= option |
16856 | was explicitly specified. */ | |
ab77a036 RS |
16857 | |
16858 | static const struct mips_cpu_info * | |
d371df6f | 16859 | mips_default_arch (void) |
06a4ab70 | 16860 | { |
872dab53 | 16861 | #if defined (MIPS_CPU_STRING_DEFAULT) |
ab77a036 | 16862 | unsigned int i; |
ab77a036 | 16863 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
d371df6f | 16864 | if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0) |
ab77a036 | 16865 | return mips_cpu_info_table + i; |
d371df6f | 16866 | gcc_unreachable (); |
872dab53 RS |
16867 | #elif defined (MIPS_ISA_DEFAULT) |
16868 | return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT); | |
d371df6f JM |
16869 | #else |
16870 | /* 'from-abi' makes a good default: you get whatever the ABI | |
16871 | requires. */ | |
16872 | return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI); | |
16873 | #endif | |
ab77a036 RS |
16874 | } |
16875 | ||
ab77a036 RS |
16876 | /* Set up globals to generate code for the ISA or processor |
16877 | described by INFO. */ | |
16878 | ||
16879 | static void | |
16880 | mips_set_architecture (const struct mips_cpu_info *info) | |
16881 | { | |
16882 | if (info != 0) | |
f9e4a411 | 16883 | { |
ab77a036 RS |
16884 | mips_arch_info = info; |
16885 | mips_arch = info->cpu; | |
16886 | mips_isa = info->isa; | |
ad782bc9 RS |
16887 | if (mips_isa < 32) |
16888 | mips_isa_rev = 0; | |
16889 | else | |
16890 | mips_isa_rev = (mips_isa & 31) + 1; | |
f9e4a411 | 16891 | } |
ab77a036 | 16892 | } |
f9e4a411 | 16893 | |
ab77a036 RS |
16894 | /* Likewise for tuning. */ |
16895 | ||
16896 | static void | |
16897 | mips_set_tune (const struct mips_cpu_info *info) | |
16898 | { | |
16899 | if (info != 0) | |
1823bf53 | 16900 | { |
ab77a036 RS |
16901 | mips_tune_info = info; |
16902 | mips_tune = info->cpu; | |
1823bf53 | 16903 | } |
ab77a036 | 16904 | } |
ff55fb9c | 16905 | |
525c561d | 16906 | /* Implement TARGET_OPTION_OVERRIDE. */ |
06a4ab70 | 16907 | |
525c561d AS |
16908 | static void |
16909 | mips_option_override (void) | |
06a4ab70 | 16910 | { |
65239d20 | 16911 | int i, start, regno, mode; |
06a4ab70 | 16912 | |
d371df6f JM |
16913 | if (global_options_set.x_mips_isa_option) |
16914 | mips_isa_option_info = &mips_cpu_info_table[mips_isa_option]; | |
16915 | ||
ab77a036 RS |
16916 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
16917 | SUBTARGET_OVERRIDE_OPTIONS; | |
16918 | #endif | |
06a4ab70 | 16919 | |
22c4c869 CM |
16920 | /* MIPS16 and microMIPS cannot coexist. */ |
16921 | if (TARGET_MICROMIPS && TARGET_MIPS16) | |
16922 | error ("unsupported combination: %s", "-mips16 -mmicromips"); | |
16923 | ||
16924 | /* Save the base compression state and process flags as though we | |
16925 | were generating uncompressed code. */ | |
16926 | mips_base_compression_flags = TARGET_COMPRESSION; | |
16927 | target_flags &= ~TARGET_COMPRESSION; | |
16928 | ||
9f946bc1 RS |
16929 | /* -mno-float overrides -mhard-float and -msoft-float. */ |
16930 | if (TARGET_NO_FLOAT) | |
16931 | { | |
16932 | target_flags |= MASK_SOFT_FLOAT_ABI; | |
16933 | target_flags_explicit |= MASK_SOFT_FLOAT_ABI; | |
16934 | } | |
16935 | ||
ac9b0eea | 16936 | if (TARGET_FLIP_MIPS16) |
22c4c869 | 16937 | TARGET_INTERLINK_COMPRESSED = 1; |
ac9b0eea | 16938 | |
65239d20 | 16939 | /* Set the small data limit. */ |
fa37ed29 | 16940 | mips_small_data_threshold = (global_options_set.x_g_switch_value |
65239d20 RS |
16941 | ? g_switch_value |
16942 | : MIPS_DEFAULT_GVALUE); | |
8f2e3902 | 16943 | |
ab77a036 RS |
16944 | /* The following code determines the architecture and register size. |
16945 | Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()). | |
16946 | The GAS and GCC code should be kept in sync as much as possible. */ | |
06a4ab70 | 16947 | |
d371df6f JM |
16948 | if (global_options_set.x_mips_arch_option) |
16949 | mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option)); | |
06a4ab70 | 16950 | |
65239d20 | 16951 | if (mips_isa_option_info != 0) |
ab77a036 RS |
16952 | { |
16953 | if (mips_arch_info == 0) | |
65239d20 RS |
16954 | mips_set_architecture (mips_isa_option_info); |
16955 | else if (mips_arch_info->isa != mips_isa_option_info->isa) | |
16956 | error ("%<-%s%> conflicts with the other architecture options, " | |
ab77a036 | 16957 | "which specify a %s processor", |
65239d20 | 16958 | mips_isa_option_info->name, |
ab77a036 RS |
16959 | mips_cpu_info_from_isa (mips_arch_info->isa)->name); |
16960 | } | |
06a4ab70 | 16961 | |
ab77a036 | 16962 | if (mips_arch_info == 0) |
d371df6f | 16963 | mips_set_architecture (mips_default_arch ()); |
06a4ab70 | 16964 | |
ab77a036 | 16965 | if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS) |
65239d20 | 16966 | error ("%<-march=%s%> is not compatible with the selected ABI", |
ab77a036 | 16967 | mips_arch_info->name); |
06a4ab70 | 16968 | |
ab77a036 | 16969 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
d371df6f JM |
16970 | if (global_options_set.x_mips_tune_option) |
16971 | mips_set_tune (mips_cpu_info_from_opt (mips_tune_option)); | |
118ea793 | 16972 | |
ab77a036 RS |
16973 | if (mips_tune_info == 0) |
16974 | mips_set_tune (mips_arch_info); | |
118ea793 | 16975 | |
ab77a036 RS |
16976 | if ((target_flags_explicit & MASK_64BIT) != 0) |
16977 | { | |
16978 | /* The user specified the size of the integer registers. Make sure | |
16979 | it agrees with the ABI and ISA. */ | |
16980 | if (TARGET_64BIT && !ISA_HAS_64BIT_REGS) | |
65239d20 | 16981 | error ("%<-mgp64%> used with a 32-bit processor"); |
ab77a036 | 16982 | else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS) |
65239d20 | 16983 | error ("%<-mgp32%> used with a 64-bit ABI"); |
ab77a036 | 16984 | else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS) |
65239d20 | 16985 | error ("%<-mgp64%> used with a 32-bit ABI"); |
ab77a036 RS |
16986 | } |
16987 | else | |
16988 | { | |
16989 | /* Infer the integer register size from the ABI and processor. | |
16990 | Restrict ourselves to 32-bit registers if that's all the | |
16991 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
16992 | if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS) | |
16993 | target_flags &= ~MASK_64BIT; | |
16994 | else | |
16995 | target_flags |= MASK_64BIT; | |
118ea793 CF |
16996 | } |
16997 | ||
ab77a036 | 16998 | if ((target_flags_explicit & MASK_FLOAT64) != 0) |
118ea793 | 16999 | { |
65239d20 | 17000 | if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64) |
ab77a036 | 17001 | error ("unsupported combination: %s", "-mfp64 -msingle-float"); |
65239d20 RS |
17002 | else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64) |
17003 | error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float"); | |
17004 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
17005 | { | |
17006 | if (!ISA_HAS_MXHC1) | |
17007 | error ("%<-mgp32%> and %<-mfp64%> can only be combined if" | |
17008 | " the target supports the mfhc1 and mthc1 instructions"); | |
17009 | else if (mips_abi != ABI_32) | |
17010 | error ("%<-mgp32%> and %<-mfp64%> can only be combined when using" | |
17011 | " the o32 ABI"); | |
17012 | } | |
ab77a036 RS |
17013 | } |
17014 | else | |
17015 | { | |
17016 | /* -msingle-float selects 32-bit float registers. Otherwise the | |
17017 | float registers should be the same size as the integer ones. */ | |
17018 | if (TARGET_64BIT && TARGET_DOUBLE_FLOAT) | |
17019 | target_flags |= MASK_FLOAT64; | |
17020 | else | |
17021 | target_flags &= ~MASK_FLOAT64; | |
17022 | } | |
118ea793 | 17023 | |
ab77a036 | 17024 | /* End of code shared with GAS. */ |
118ea793 | 17025 | |
04dfc6df JU |
17026 | /* The R5900 FPU only supports single precision. */ |
17027 | if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT) | |
17028 | error ("unsupported combination: %s", | |
17029 | "-march=r5900 -mhard-float -mdouble-float"); | |
17030 | ||
81a478c8 RS |
17031 | /* If a -mlong* option was given, check that it matches the ABI, |
17032 | otherwise infer the -mlong* setting from the other options. */ | |
17033 | if ((target_flags_explicit & MASK_LONG64) != 0) | |
17034 | { | |
17035 | if (TARGET_LONG64) | |
17036 | { | |
17037 | if (mips_abi == ABI_N32) | |
17038 | error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64"); | |
17039 | else if (mips_abi == ABI_32) | |
17040 | error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64"); | |
17041 | else if (mips_abi == ABI_O64 && TARGET_ABICALLS) | |
17042 | /* We have traditionally allowed non-abicalls code to use | |
17043 | an LP64 form of o64. However, it would take a bit more | |
17044 | effort to support the combination of 32-bit GOT entries | |
17045 | and 64-bit pointers, so we treat the abicalls case as | |
17046 | an error. */ | |
17047 | error ("the combination of %qs and %qs is incompatible with %qs", | |
17048 | "-mabi=o64", "-mabicalls", "-mlong64"); | |
17049 | } | |
17050 | else | |
17051 | { | |
17052 | if (mips_abi == ABI_64) | |
17053 | error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32"); | |
17054 | } | |
17055 | } | |
17056 | else | |
ab77a036 RS |
17057 | { |
17058 | if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64) | |
17059 | target_flags |= MASK_LONG64; | |
17060 | else | |
17061 | target_flags &= ~MASK_LONG64; | |
17062 | } | |
118ea793 | 17063 | |
ab77a036 RS |
17064 | if (!TARGET_OLDABI) |
17065 | flag_pcc_struct_return = 0; | |
118ea793 | 17066 | |
65239d20 RS |
17067 | /* Decide which rtx_costs structure to use. */ |
17068 | if (optimize_size) | |
17069 | mips_cost = &mips_rtx_cost_optimize_size; | |
17070 | else | |
17071 | mips_cost = &mips_rtx_cost_data[mips_tune]; | |
17072 | ||
17073 | /* If the user hasn't specified a branch cost, use the processor's | |
17074 | default. */ | |
17075 | if (mips_branch_cost == 0) | |
17076 | mips_branch_cost = mips_cost->branch_cost; | |
17077 | ||
17078 | /* If neither -mbranch-likely nor -mno-branch-likely was given | |
17079 | on the command line, set MASK_BRANCHLIKELY based on the target | |
17080 | architecture and tuning flags. Annulled delay slots are a | |
17081 | size win, so we only consider the processor-specific tuning | |
17082 | for !optimize_size. */ | |
ab77a036 RS |
17083 | if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0) |
17084 | { | |
ab77a036 RS |
17085 | if (ISA_HAS_BRANCHLIKELY |
17086 | && (optimize_size | |
17087 | || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0)) | |
17088 | target_flags |= MASK_BRANCHLIKELY; | |
17089 | else | |
17090 | target_flags &= ~MASK_BRANCHLIKELY; | |
17091 | } | |
17092 | else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) | |
17093 | warning (0, "the %qs architecture does not support branch-likely" | |
17094 | " instructions", mips_arch_info->name); | |
118ea793 | 17095 | |
855e0d0b SE |
17096 | /* If the user hasn't specified -mimadd or -mno-imadd set |
17097 | MASK_IMADD based on the target architecture and tuning | |
17098 | flags. */ | |
17099 | if ((target_flags_explicit & MASK_IMADD) == 0) | |
17100 | { | |
17101 | if (ISA_HAS_MADD_MSUB && | |
17102 | (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0) | |
17103 | target_flags |= MASK_IMADD; | |
17104 | else | |
17105 | target_flags &= ~MASK_IMADD; | |
17106 | } | |
17107 | else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB) | |
17108 | warning (0, "the %qs architecture does not support madd or msub" | |
17109 | " instructions", mips_arch_info->name); | |
17110 | ||
ab77a036 RS |
17111 | /* The effect of -mabicalls isn't defined for the EABI. */ |
17112 | if (mips_abi == ABI_EABI && TARGET_ABICALLS) | |
17113 | { | |
17114 | error ("unsupported combination: %s", "-mabicalls -mabi=eabi"); | |
17115 | target_flags &= ~MASK_ABICALLS; | |
17116 | } | |
118ea793 | 17117 | |
5dd4087e SL |
17118 | /* PIC requires -mabicalls. */ |
17119 | if (flag_pic) | |
17120 | { | |
17121 | if (mips_abi == ABI_EABI) | |
17122 | error ("cannot generate position-independent code for %qs", | |
17123 | "-mabi=eabi"); | |
17124 | else if (!TARGET_ABICALLS) | |
17125 | error ("position-independent code requires %qs", "-mabicalls"); | |
17126 | } | |
17127 | ||
e21d5757 | 17128 | if (TARGET_ABICALLS_PIC2) |
ab77a036 RS |
17129 | /* We need to set flag_pic for executables as well as DSOs |
17130 | because we may reference symbols that are not defined in | |
17131 | the final executable. (MIPS does not use things like | |
17132 | copy relocs, for example.) | |
118ea793 | 17133 | |
e21d5757 DJ |
17134 | There is a body of code that uses __PIC__ to distinguish |
17135 | between -mabicalls and -mno-abicalls code. The non-__PIC__ | |
17136 | variant is usually appropriate for TARGET_ABICALLS_PIC0, as | |
17137 | long as any indirect jumps use $25. */ | |
ab77a036 | 17138 | flag_pic = 1; |
118ea793 | 17139 | |
ab77a036 RS |
17140 | /* -mvr4130-align is a "speed over size" optimization: it usually produces |
17141 | faster code, but at the expense of more nops. Enable it at -O3 and | |
17142 | above. */ | |
17143 | if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) | |
17144 | target_flags |= MASK_VR4130_ALIGN; | |
118ea793 | 17145 | |
ab77a036 RS |
17146 | /* Prefer a call to memcpy over inline code when optimizing for size, |
17147 | though see MOVE_RATIO in mips.h. */ | |
17148 | if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) | |
17149 | target_flags |= MASK_MEMCPY; | |
118ea793 | 17150 | |
ab77a036 RS |
17151 | /* If we have a nonzero small-data limit, check that the -mgpopt |
17152 | setting is consistent with the other target flags. */ | |
65239d20 | 17153 | if (mips_small_data_threshold > 0) |
ab77a036 RS |
17154 | { |
17155 | if (!TARGET_GPOPT) | |
17156 | { | |
60730ade | 17157 | if (!TARGET_EXPLICIT_RELOCS) |
ab77a036 | 17158 | error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>"); |
118ea793 | 17159 | |
ab77a036 RS |
17160 | TARGET_LOCAL_SDATA = false; |
17161 | TARGET_EXTERN_SDATA = false; | |
17162 | } | |
17163 | else | |
17164 | { | |
17165 | if (TARGET_VXWORKS_RTP) | |
17166 | warning (0, "cannot use small-data accesses for %qs", "-mrtp"); | |
118ea793 | 17167 | |
ab77a036 RS |
17168 | if (TARGET_ABICALLS) |
17169 | warning (0, "cannot use small-data accesses for %qs", | |
17170 | "-mabicalls"); | |
17171 | } | |
17172 | } | |
118ea793 | 17173 | |
ff3f3951 MR |
17174 | /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format |
17175 | for all its floating point. */ | |
17176 | if (mips_nan != MIPS_IEEE_754_2008) | |
17177 | { | |
17178 | REAL_MODE_FORMAT (SFmode) = &mips_single_format; | |
17179 | REAL_MODE_FORMAT (DFmode) = &mips_double_format; | |
17180 | REAL_MODE_FORMAT (TFmode) = &mips_quad_format; | |
17181 | } | |
17182 | ||
ab77a036 RS |
17183 | /* Make sure that the user didn't turn off paired single support when |
17184 | MIPS-3D support is requested. */ | |
65239d20 RS |
17185 | if (TARGET_MIPS3D |
17186 | && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT) | |
ab77a036 | 17187 | && !TARGET_PAIRED_SINGLE_FLOAT) |
65239d20 | 17188 | error ("%<-mips3d%> requires %<-mpaired-single%>"); |
118ea793 | 17189 | |
ab77a036 RS |
17190 | /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */ |
17191 | if (TARGET_MIPS3D) | |
17192 | target_flags |= MASK_PAIRED_SINGLE_FLOAT; | |
118ea793 | 17193 | |
ab77a036 RS |
17194 | /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 |
17195 | and TARGET_HARD_FLOAT_ABI are both true. */ | |
17196 | if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) | |
bd65fc87 RS |
17197 | { |
17198 | error ("%qs must be used with %qs", | |
17199 | TARGET_MIPS3D ? "-mips3d" : "-mpaired-single", | |
17200 | TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float"); | |
17201 | target_flags &= ~MASK_PAIRED_SINGLE_FLOAT; | |
17202 | TARGET_MIPS3D = 0; | |
17203 | } | |
118ea793 | 17204 | |
bd65fc87 RS |
17205 | /* Make sure that -mpaired-single is only used on ISAs that support it. |
17206 | We must disable it otherwise since it relies on other ISA properties | |
17207 | like ISA_HAS_8CC having their normal values. */ | |
e5a2b69d | 17208 | if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE) |
bd65fc87 RS |
17209 | { |
17210 | error ("the %qs architecture does not support paired-single" | |
e5a2b69d | 17211 | " instructions", mips_arch_info->name); |
bd65fc87 RS |
17212 | target_flags &= ~MASK_PAIRED_SINGLE_FLOAT; |
17213 | TARGET_MIPS3D = 0; | |
17214 | } | |
118ea793 | 17215 | |
4d210b07 RS |
17216 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE |
17217 | && !TARGET_CACHE_BUILTIN) | |
17218 | { | |
17219 | error ("%qs requires a target that provides the %qs instruction", | |
17220 | "-mr10k-cache-barrier", "cache"); | |
17221 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; | |
17222 | } | |
17223 | ||
a33fc7fe | 17224 | /* If TARGET_DSPR2, enable TARGET_DSP. */ |
ab77a036 | 17225 | if (TARGET_DSPR2) |
a33fc7fe | 17226 | TARGET_DSP = true; |
118ea793 | 17227 | |
082d2ebb RS |
17228 | /* .eh_frame addresses should be the same width as a C pointer. |
17229 | Most MIPS ABIs support only one pointer size, so the assembler | |
17230 | will usually know exactly how big an .eh_frame address is. | |
17231 | ||
17232 | Unfortunately, this is not true of the 64-bit EABI. The ABI was | |
17233 | originally defined to use 64-bit pointers (i.e. it is LP64), and | |
17234 | this is still the default mode. However, we also support an n32-like | |
17235 | ILP32 mode, which is selected by -mlong32. The problem is that the | |
17236 | assembler has traditionally not had an -mlong option, so it has | |
17237 | traditionally not known whether we're using the ILP32 or LP64 form. | |
17238 | ||
17239 | As it happens, gas versions up to and including 2.19 use _32-bit_ | |
17240 | addresses for EABI64 .cfi_* directives. This is wrong for the | |
17241 | default LP64 mode, so we can't use the directives by default. | |
17242 | Moreover, since gas's current behavior is at odds with gcc's | |
17243 | default behavior, it seems unwise to rely on future versions | |
17244 | of gas behaving the same way. We therefore avoid using .cfi | |
17245 | directives for -mlong32 as well. */ | |
17246 | if (mips_abi == ABI_EABI && TARGET_64BIT) | |
17247 | flag_dwarf2_cfi_asm = 0; | |
17248 | ||
49576e25 RS |
17249 | /* .cfi_* directives generate a read-only section, so fall back on |
17250 | manual .eh_frame creation if we need the section to be writable. */ | |
17251 | if (TARGET_WRITABLE_EH_FRAME) | |
17252 | flag_dwarf2_cfi_asm = 0; | |
17253 | ||
07045266 | 17254 | mips_init_print_operand_punct (); |
118ea793 | 17255 | |
ab77a036 RS |
17256 | /* Set up array to map GCC register number to debug register number. |
17257 | Ignore the special purpose register numbers. */ | |
118ea793 | 17258 | |
ab77a036 RS |
17259 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
17260 | { | |
22eab31a | 17261 | mips_dbx_regno[i] = IGNORED_DWARF_REGNUM; |
ab77a036 RS |
17262 | if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i)) |
17263 | mips_dwarf_regno[i] = i; | |
17264 | else | |
17265 | mips_dwarf_regno[i] = INVALID_REGNUM; | |
17266 | } | |
118ea793 | 17267 | |
ab77a036 RS |
17268 | start = GP_DBX_FIRST - GP_REG_FIRST; |
17269 | for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) | |
17270 | mips_dbx_regno[i] = i + start; | |
118ea793 | 17271 | |
ab77a036 RS |
17272 | start = FP_DBX_FIRST - FP_REG_FIRST; |
17273 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
17274 | mips_dbx_regno[i] = i + start; | |
118ea793 | 17275 | |
65239d20 | 17276 | /* Accumulator debug registers use big-endian ordering. */ |
ab77a036 RS |
17277 | mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0; |
17278 | mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1; | |
17279 | mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0; | |
17280 | mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1; | |
17281 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
17282 | { | |
17283 | mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i; | |
17284 | mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1; | |
17285 | } | |
118ea793 | 17286 | |
5f5fe6d9 RS |
17287 | /* Set up mips_hard_regno_mode_ok. */ |
17288 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
17289 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
bbbbb16a | 17290 | mips_hard_regno_mode_ok[mode][regno] |
ef4bddc2 | 17291 | = mips_hard_regno_mode_ok_p (regno, (machine_mode) mode); |
06a4ab70 | 17292 | |
ab77a036 RS |
17293 | /* Function to allocate machine-dependent function status. */ |
17294 | init_machine_status = &mips_init_machine_status; | |
4ca1f68f | 17295 | |
ab77a036 RS |
17296 | /* Default to working around R4000 errata only if the processor |
17297 | was selected explicitly. */ | |
17298 | if ((target_flags_explicit & MASK_FIX_R4000) == 0 | |
d371df6f | 17299 | && strcmp (mips_arch_info->name, "r4000") == 0) |
ab77a036 | 17300 | target_flags |= MASK_FIX_R4000; |
4ca1f68f | 17301 | |
ab77a036 RS |
17302 | /* Default to working around R4400 errata only if the processor |
17303 | was selected explicitly. */ | |
17304 | if ((target_flags_explicit & MASK_FIX_R4400) == 0 | |
d371df6f | 17305 | && strcmp (mips_arch_info->name, "r4400") == 0) |
ab77a036 | 17306 | target_flags |= MASK_FIX_R4400; |
4ca1f68f | 17307 | |
ee9a72e5 JK |
17308 | /* Default to working around R10000 errata only if the processor |
17309 | was selected explicitly. */ | |
17310 | if ((target_flags_explicit & MASK_FIX_R10000) == 0 | |
d371df6f | 17311 | && strcmp (mips_arch_info->name, "r10000") == 0) |
ee9a72e5 JK |
17312 | target_flags |= MASK_FIX_R10000; |
17313 | ||
17314 | /* Make sure that branch-likely instructions available when using | |
17315 | -mfix-r10000. The instructions are not available if either: | |
17316 | ||
17317 | 1. -mno-branch-likely was passed. | |
17318 | 2. The selected ISA does not support branch-likely and | |
17319 | the command line does not include -mbranch-likely. */ | |
17320 | if (TARGET_FIX_R10000 | |
17321 | && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0 | |
17322 | ? !ISA_HAS_BRANCHLIKELY | |
17323 | : !TARGET_BRANCHLIKELY)) | |
17324 | sorry ("%qs requires branch-likely instructions", "-mfix-r10000"); | |
17325 | ||
b96c5923 DD |
17326 | if (TARGET_SYNCI && !ISA_HAS_SYNCI) |
17327 | { | |
17328 | warning (0, "the %qs architecture does not support the synci " | |
17329 | "instruction", mips_arch_info->name); | |
17330 | target_flags &= ~MASK_SYNCI; | |
17331 | } | |
17332 | ||
b53da244 AN |
17333 | /* Only optimize PIC indirect calls if they are actually required. */ |
17334 | if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS) | |
17335 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
17336 | ||
ab77a036 | 17337 | /* Save base state of options. */ |
ab77a036 | 17338 | mips_base_target_flags = target_flags; |
ab77a036 RS |
17339 | mips_base_schedule_insns = flag_schedule_insns; |
17340 | mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition; | |
17341 | mips_base_move_loop_invariants = flag_move_loop_invariants; | |
17342 | mips_base_align_loops = align_loops; | |
17343 | mips_base_align_jumps = align_jumps; | |
17344 | mips_base_align_functions = align_functions; | |
118ea793 | 17345 | |
60730ade RS |
17346 | /* Now select the ISA mode. |
17347 | ||
22c4c869 CM |
17348 | Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes |
17349 | later if required. */ | |
17350 | mips_set_compression_mode (0); | |
fb0d5c60 SB |
17351 | |
17352 | /* We register a second machine specific reorg pass after delay slot | |
17353 | filling. Registering the pass must be done at start up. It's | |
17354 | convenient to do it here. */ | |
c5a12e26 DM |
17355 | opt_pass *new_pass = make_pass_mips_machine_reorg2 (g); |
17356 | struct register_pass_info insert_pass_mips_machine_reorg2 = | |
17357 | { | |
17358 | new_pass, /* pass */ | |
17359 | "dbr", /* reference_pass_name */ | |
17360 | 1, /* ref_pass_instance_number */ | |
17361 | PASS_POS_INSERT_AFTER /* po_op */ | |
17362 | }; | |
fb0d5c60 | 17363 | register_pass (&insert_pass_mips_machine_reorg2); |
04dfc6df JU |
17364 | |
17365 | if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900) | |
17366 | REAL_MODE_FORMAT (SFmode) = &spu_single_format; | |
ab77a036 | 17367 | } |
4ca1f68f | 17368 | |
ab77a036 RS |
17369 | /* Swap the register information for registers I and I + 1, which |
17370 | currently have the wrong endianness. Note that the registers' | |
17371 | fixedness and call-clobberedness might have been set on the | |
17372 | command line. */ | |
4ca1f68f | 17373 | |
ab77a036 RS |
17374 | static void |
17375 | mips_swap_registers (unsigned int i) | |
17376 | { | |
17377 | int tmpi; | |
17378 | const char *tmps; | |
4ca1f68f | 17379 | |
ab77a036 RS |
17380 | #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi) |
17381 | #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps) | |
4ca1f68f | 17382 | |
ab77a036 RS |
17383 | SWAP_INT (fixed_regs[i], fixed_regs[i + 1]); |
17384 | SWAP_INT (call_used_regs[i], call_used_regs[i + 1]); | |
17385 | SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]); | |
17386 | SWAP_STRING (reg_names[i], reg_names[i + 1]); | |
17387 | ||
17388 | #undef SWAP_STRING | |
17389 | #undef SWAP_INT | |
06a4ab70 CF |
17390 | } |
17391 | ||
5efd84c5 | 17392 | /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ |
06a4ab70 | 17393 | |
5efd84c5 | 17394 | static void |
ab77a036 | 17395 | mips_conditional_register_usage (void) |
06a4ab70 | 17396 | { |
1e27273f CM |
17397 | |
17398 | if (ISA_HAS_DSP) | |
17399 | { | |
17400 | /* These DSP control register fields are global. */ | |
17401 | global_regs[CCDSP_PO_REGNUM] = 1; | |
17402 | global_regs[CCDSP_SC_REGNUM] = 1; | |
17403 | } | |
006b72bf RS |
17404 | else |
17405 | AND_COMPL_HARD_REG_SET (accessible_reg_set, | |
17406 | reg_class_contents[(int) DSP_ACC_REGS]); | |
06a4ab70 | 17407 | |
ab77a036 RS |
17408 | if (!TARGET_HARD_FLOAT) |
17409 | { | |
006b72bf RS |
17410 | AND_COMPL_HARD_REG_SET (accessible_reg_set, |
17411 | reg_class_contents[(int) FP_REGS]); | |
17412 | AND_COMPL_HARD_REG_SET (accessible_reg_set, | |
17413 | reg_class_contents[(int) ST_REGS]); | |
ab77a036 | 17414 | } |
006b72bf | 17415 | else if (!ISA_HAS_8CC) |
ff55fb9c | 17416 | { |
65239d20 RS |
17417 | /* We only have a single condition-code register. We implement |
17418 | this by fixing all the condition-code registers and generating | |
17419 | RTL that refers directly to ST_REG_FIRST. */ | |
006b72bf RS |
17420 | AND_COMPL_HARD_REG_SET (accessible_reg_set, |
17421 | reg_class_contents[(int) ST_REGS]); | |
17422 | SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM); | |
17423 | fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1; | |
ff55fb9c | 17424 | } |
ab77a036 | 17425 | if (TARGET_MIPS16) |
ff55fb9c | 17426 | { |
76500022 | 17427 | /* In MIPS16 mode, we prohibit the unused $s registers, since they |
a2ccf3c2 | 17428 | are call-saved, and saving them via a MIPS16 register would |
76500022 SE |
17429 | probably waste more time than just reloading the value. |
17430 | ||
17431 | We permit the $t temporary registers when optimizing for speed | |
17432 | but not when optimizing for space because using them results in | |
17433 | code that is larger (but faster) then not using them. We do | |
17434 | allow $24 (t8) because it is used in CMP and CMPI instructions | |
17435 | and $25 (t9) because it is used as the function call address in | |
17436 | SVR4 PIC code. */ | |
17437 | ||
ab77a036 RS |
17438 | fixed_regs[18] = call_used_regs[18] = 1; |
17439 | fixed_regs[19] = call_used_regs[19] = 1; | |
17440 | fixed_regs[20] = call_used_regs[20] = 1; | |
17441 | fixed_regs[21] = call_used_regs[21] = 1; | |
17442 | fixed_regs[22] = call_used_regs[22] = 1; | |
17443 | fixed_regs[23] = call_used_regs[23] = 1; | |
17444 | fixed_regs[26] = call_used_regs[26] = 1; | |
17445 | fixed_regs[27] = call_used_regs[27] = 1; | |
17446 | fixed_regs[30] = call_used_regs[30] = 1; | |
76500022 SE |
17447 | if (optimize_size) |
17448 | { | |
17449 | fixed_regs[8] = call_used_regs[8] = 1; | |
17450 | fixed_regs[9] = call_used_regs[9] = 1; | |
17451 | fixed_regs[10] = call_used_regs[10] = 1; | |
17452 | fixed_regs[11] = call_used_regs[11] = 1; | |
17453 | fixed_regs[12] = call_used_regs[12] = 1; | |
17454 | fixed_regs[13] = call_used_regs[13] = 1; | |
17455 | fixed_regs[14] = call_used_regs[14] = 1; | |
17456 | fixed_regs[15] = call_used_regs[15] = 1; | |
17457 | } | |
a2ccf3c2 RS |
17458 | |
17459 | /* Do not allow HI and LO to be treated as register operands. | |
17460 | There are no MTHI or MTLO instructions (or any real need | |
17461 | for them) and one-way registers cannot easily be reloaded. */ | |
17462 | AND_COMPL_HARD_REG_SET (operand_reg_set, | |
17463 | reg_class_contents[(int) MD_REGS]); | |
ab77a036 | 17464 | } |
65239d20 | 17465 | /* $f20-$f23 are call-clobbered for n64. */ |
ab77a036 RS |
17466 | if (mips_abi == ABI_64) |
17467 | { | |
17468 | int regno; | |
17469 | for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) | |
17470 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
17471 | } | |
65239d20 RS |
17472 | /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered |
17473 | for n32. */ | |
ab77a036 RS |
17474 | if (mips_abi == ABI_N32) |
17475 | { | |
17476 | int regno; | |
17477 | for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) | |
17478 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
17479 | } | |
17480 | /* Make sure that double-register accumulator values are correctly | |
17481 | ordered for the current endianness. */ | |
17482 | if (TARGET_LITTLE_ENDIAN) | |
17483 | { | |
65239d20 RS |
17484 | unsigned int regno; |
17485 | ||
ab77a036 RS |
17486 | mips_swap_registers (MD_REG_FIRST); |
17487 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2) | |
17488 | mips_swap_registers (regno); | |
ff55fb9c | 17489 | } |
ff55fb9c | 17490 | } |
06a4ab70 | 17491 | |
0c433c31 RS |
17492 | /* Implement EH_USES. */ |
17493 | ||
17494 | bool | |
17495 | mips_eh_uses (unsigned int regno) | |
17496 | { | |
17497 | if (reload_completed && !TARGET_ABSOLUTE_JUMPS) | |
17498 | { | |
17499 | /* We need to force certain registers to be live in order to handle | |
17500 | PIC long branches correctly. See mips_must_initialize_gp_p for | |
17501 | details. */ | |
17502 | if (mips_cfun_has_cprestore_slot_p ()) | |
17503 | { | |
17504 | if (regno == CPRESTORE_SLOT_REGNUM) | |
17505 | return true; | |
17506 | } | |
17507 | else | |
17508 | { | |
17509 | if (cfun->machine->global_pointer == regno) | |
17510 | return true; | |
17511 | } | |
17512 | } | |
17513 | ||
17514 | return false; | |
17515 | } | |
17516 | ||
e19da24c CF |
17517 | /* Implement EPILOGUE_USES. */ |
17518 | ||
17519 | bool | |
17520 | mips_epilogue_uses (unsigned int regno) | |
17521 | { | |
17522 | /* Say that the epilogue uses the return address register. Note that | |
17523 | in the case of sibcalls, the values "used by the epilogue" are | |
17524 | considered live at the start of the called function. */ | |
293593b1 | 17525 | if (regno == RETURN_ADDR_REGNUM) |
e19da24c CF |
17526 | return true; |
17527 | ||
17528 | /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM. | |
17529 | See the comment above load_call<mode> for details. */ | |
17530 | if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM) | |
17531 | return true; | |
17532 | ||
17533 | /* An interrupt handler must preserve some registers that are | |
17534 | ordinarily call-clobbered. */ | |
17535 | if (cfun->machine->interrupt_handler_p | |
17536 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
17537 | return true; | |
17538 | ||
17539 | return false; | |
17540 | } | |
1afc5373 | 17541 | |
cf5fb4b0 RS |
17542 | /* Return true if INSN needs to be wrapped in ".set noat". |
17543 | INSN has NOPERANDS operands, stored in OPVEC. */ | |
1afc5373 | 17544 | |
cf5fb4b0 | 17545 | static bool |
647d790d | 17546 | mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands) |
1afc5373 | 17547 | { |
1afc5373 | 17548 | if (recog_memoized (insn) >= 0) |
d44f6d93 RS |
17549 | { |
17550 | subrtx_iterator::array_type array; | |
17551 | for (int i = 0; i < noperands; i++) | |
17552 | FOR_EACH_SUBRTX (iter, array, opvec[i], NONCONST) | |
17553 | if (REG_P (*iter) && REGNO (*iter) == AT_REGNUM) | |
17554 | return true; | |
17555 | } | |
cf5fb4b0 RS |
17556 | return false; |
17557 | } | |
17558 | ||
17559 | /* Implement FINAL_PRESCAN_INSN. */ | |
17560 | ||
17561 | void | |
c6f971f4 | 17562 | mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands) |
cf5fb4b0 RS |
17563 | { |
17564 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) | |
17565 | mips_push_asm_switch (&mips_noat); | |
1afc5373 CF |
17566 | } |
17567 | ||
17568 | /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */ | |
17569 | ||
0e097268 | 17570 | static void |
ac44248e | 17571 | mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn, |
cf5fb4b0 | 17572 | rtx *opvec, int noperands) |
1afc5373 | 17573 | { |
cf5fb4b0 RS |
17574 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) |
17575 | mips_pop_asm_switch (&mips_noat); | |
1afc5373 | 17576 | } |
a3c7bb26 AN |
17577 | |
17578 | /* Return the function that is used to expand the <u>mulsidi3 pattern. | |
17579 | EXT_CODE is the code of the extension used. Return NULL if widening | |
17580 | multiplication shouldn't be used. */ | |
17581 | ||
17582 | mulsidi3_gen_fn | |
17583 | mips_mulsidi3_gen_fn (enum rtx_code ext_code) | |
17584 | { | |
17585 | bool signed_p; | |
17586 | ||
17587 | signed_p = ext_code == SIGN_EXTEND; | |
17588 | if (TARGET_64BIT) | |
17589 | { | |
17590 | /* Don't use widening multiplication with MULT when we have DMUL. Even | |
17591 | with the extension of its input operands DMUL is faster. Note that | |
17592 | the extension is not needed for signed multiplication. In order to | |
17593 | ensure that we always remove the redundant sign-extension in this | |
17594 | case we still expand mulsidi3 for DMUL. */ | |
17595 | if (ISA_HAS_DMUL3) | |
17596 | return signed_p ? gen_mulsidi3_64bit_dmul : NULL; | |
a2ccf3c2 RS |
17597 | if (TARGET_MIPS16) |
17598 | return (signed_p | |
17599 | ? gen_mulsidi3_64bit_mips16 | |
17600 | : gen_umulsidi3_64bit_mips16); | |
a3c7bb26 AN |
17601 | if (TARGET_FIX_R4000) |
17602 | return NULL; | |
17603 | return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit; | |
17604 | } | |
17605 | else | |
17606 | { | |
a2ccf3c2 RS |
17607 | if (TARGET_MIPS16) |
17608 | return (signed_p | |
17609 | ? gen_mulsidi3_32bit_mips16 | |
17610 | : gen_umulsidi3_32bit_mips16); | |
293b77b0 | 17611 | if (TARGET_FIX_R4000 && !ISA_HAS_DSP) |
a3c7bb26 | 17612 | return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000; |
a3c7bb26 AN |
17613 | return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit; |
17614 | } | |
17615 | } | |
22c4c869 CM |
17616 | |
17617 | /* Return true if PATTERN matches the kind of instruction generated by | |
17618 | umips_build_save_restore. SAVE_P is true for store. */ | |
17619 | ||
17620 | bool | |
17621 | umips_save_restore_pattern_p (bool save_p, rtx pattern) | |
17622 | { | |
17623 | int n; | |
17624 | unsigned int i; | |
17625 | HOST_WIDE_INT first_offset = 0; | |
17626 | rtx first_base = 0; | |
17627 | unsigned int regmask = 0; | |
17628 | ||
17629 | for (n = 0; n < XVECLEN (pattern, 0); n++) | |
17630 | { | |
17631 | rtx set, reg, mem, this_base; | |
17632 | HOST_WIDE_INT this_offset; | |
17633 | ||
17634 | /* Check that we have a SET. */ | |
17635 | set = XVECEXP (pattern, 0, n); | |
17636 | if (GET_CODE (set) != SET) | |
17637 | return false; | |
17638 | ||
17639 | /* Check that the SET is a load (if restoring) or a store | |
17640 | (if saving). */ | |
17641 | mem = save_p ? SET_DEST (set) : SET_SRC (set); | |
17642 | if (!MEM_P (mem) || MEM_VOLATILE_P (mem)) | |
17643 | return false; | |
17644 | ||
17645 | /* Check that the address is the sum of base and a possibly-zero | |
17646 | constant offset. Determine if the offset is in range. */ | |
17647 | mips_split_plus (XEXP (mem, 0), &this_base, &this_offset); | |
17648 | if (!REG_P (this_base)) | |
17649 | return false; | |
17650 | ||
17651 | if (n == 0) | |
17652 | { | |
17653 | if (!UMIPS_12BIT_OFFSET_P (this_offset)) | |
17654 | return false; | |
17655 | first_base = this_base; | |
17656 | first_offset = this_offset; | |
17657 | } | |
17658 | else | |
17659 | { | |
17660 | /* Check that the save slots are consecutive. */ | |
17661 | if (REGNO (this_base) != REGNO (first_base) | |
17662 | || this_offset != first_offset + UNITS_PER_WORD * n) | |
17663 | return false; | |
17664 | } | |
17665 | ||
17666 | /* Check that SET's other operand is a register. */ | |
17667 | reg = save_p ? SET_SRC (set) : SET_DEST (set); | |
17668 | if (!REG_P (reg)) | |
17669 | return false; | |
17670 | ||
17671 | regmask |= 1 << REGNO (reg); | |
17672 | } | |
17673 | ||
17674 | for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++) | |
17675 | if (regmask == umips_swm_mask[i]) | |
17676 | return true; | |
17677 | ||
17678 | return false; | |
17679 | } | |
17680 | ||
17681 | /* Return the assembly instruction for microMIPS LWM or SWM. | |
17682 | SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */ | |
17683 | ||
17684 | const char * | |
17685 | umips_output_save_restore (bool save_p, rtx pattern) | |
17686 | { | |
17687 | static char buffer[300]; | |
17688 | char *s; | |
17689 | int n; | |
17690 | HOST_WIDE_INT offset; | |
17691 | rtx base, mem, set, last_set, last_reg; | |
17692 | ||
17693 | /* Parse the pattern. */ | |
17694 | gcc_assert (umips_save_restore_pattern_p (save_p, pattern)); | |
17695 | ||
17696 | s = strcpy (buffer, save_p ? "swm\t" : "lwm\t"); | |
17697 | s += strlen (s); | |
17698 | n = XVECLEN (pattern, 0); | |
17699 | ||
17700 | set = XVECEXP (pattern, 0, 0); | |
17701 | mem = save_p ? SET_DEST (set) : SET_SRC (set); | |
17702 | mips_split_plus (XEXP (mem, 0), &base, &offset); | |
17703 | ||
17704 | last_set = XVECEXP (pattern, 0, n - 1); | |
17705 | last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set); | |
17706 | ||
17707 | if (REGNO (last_reg) == 31) | |
17708 | n--; | |
17709 | ||
17710 | gcc_assert (n <= 9); | |
17711 | if (n == 0) | |
17712 | ; | |
17713 | else if (n == 1) | |
17714 | s += sprintf (s, "%s,", reg_names[16]); | |
17715 | else if (n < 9) | |
17716 | s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]); | |
17717 | else if (n == 9) | |
17718 | s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23], | |
17719 | reg_names[30]); | |
17720 | ||
17721 | if (REGNO (last_reg) == 31) | |
17722 | s += sprintf (s, "%s,", reg_names[31]); | |
17723 | ||
17724 | s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]); | |
17725 | return buffer; | |
17726 | } | |
17727 | ||
17728 | /* Return true if MEM1 and MEM2 use the same base register, and the | |
17729 | offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the | |
17730 | register into (from) which the contents of MEM1 will be loaded | |
17731 | (stored), depending on the value of LOAD_P. | |
17732 | SWAP_P is true when the 1st and 2nd instructions are swapped. */ | |
17733 | ||
17734 | static bool | |
17735 | umips_load_store_pair_p_1 (bool load_p, bool swap_p, | |
17736 | rtx first_reg, rtx mem1, rtx mem2) | |
17737 | { | |
17738 | rtx base1, base2; | |
17739 | HOST_WIDE_INT offset1, offset2; | |
17740 | ||
17741 | if (!MEM_P (mem1) || !MEM_P (mem2)) | |
17742 | return false; | |
17743 | ||
17744 | mips_split_plus (XEXP (mem1, 0), &base1, &offset1); | |
17745 | mips_split_plus (XEXP (mem2, 0), &base2, &offset2); | |
17746 | ||
17747 | if (!REG_P (base1) || !rtx_equal_p (base1, base2)) | |
17748 | return false; | |
17749 | ||
17750 | /* Avoid invalid load pair instructions. */ | |
17751 | if (load_p && REGNO (first_reg) == REGNO (base1)) | |
17752 | return false; | |
17753 | ||
17754 | /* We must avoid this case for anti-dependence. | |
17755 | Ex: lw $3, 4($3) | |
17756 | lw $2, 0($3) | |
17757 | first_reg is $2, but the base is $3. */ | |
17758 | if (load_p | |
17759 | && swap_p | |
17760 | && REGNO (first_reg) + 1 == REGNO (base1)) | |
17761 | return false; | |
17762 | ||
17763 | if (offset2 != offset1 + 4) | |
17764 | return false; | |
17765 | ||
17766 | if (!UMIPS_12BIT_OFFSET_P (offset1)) | |
17767 | return false; | |
17768 | ||
17769 | return true; | |
17770 | } | |
17771 | ||
17772 | /* OPERANDS describes the operands to a pair of SETs, in the order | |
17773 | dest1, src1, dest2, src2. Return true if the operands can be used | |
17774 | in an LWP or SWP instruction; LOAD_P says which. */ | |
17775 | ||
17776 | bool | |
17777 | umips_load_store_pair_p (bool load_p, rtx *operands) | |
17778 | { | |
17779 | rtx reg1, reg2, mem1, mem2; | |
17780 | ||
17781 | if (load_p) | |
17782 | { | |
17783 | reg1 = operands[0]; | |
17784 | reg2 = operands[2]; | |
17785 | mem1 = operands[1]; | |
17786 | mem2 = operands[3]; | |
17787 | } | |
17788 | else | |
17789 | { | |
17790 | reg1 = operands[1]; | |
17791 | reg2 = operands[3]; | |
17792 | mem1 = operands[0]; | |
17793 | mem2 = operands[2]; | |
17794 | } | |
17795 | ||
17796 | if (REGNO (reg2) == REGNO (reg1) + 1) | |
17797 | return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2); | |
17798 | ||
17799 | if (REGNO (reg1) == REGNO (reg2) + 1) | |
17800 | return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1); | |
17801 | ||
17802 | return false; | |
17803 | } | |
17804 | ||
17805 | /* Return the assembly instruction for a microMIPS LWP or SWP in which | |
17806 | the first register is REG and the first memory slot is MEM. | |
17807 | LOAD_P is true for LWP. */ | |
17808 | ||
17809 | static void | |
17810 | umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem) | |
17811 | { | |
17812 | rtx ops[] = {reg, mem}; | |
17813 | ||
17814 | if (load_p) | |
17815 | output_asm_insn ("lwp\t%0,%1", ops); | |
17816 | else | |
17817 | output_asm_insn ("swp\t%0,%1", ops); | |
17818 | } | |
17819 | ||
17820 | /* Output the assembly instruction for a microMIPS LWP or SWP instruction. | |
17821 | LOAD_P and OPERANDS are as for umips_load_store_pair_p. */ | |
17822 | ||
17823 | void | |
17824 | umips_output_load_store_pair (bool load_p, rtx *operands) | |
17825 | { | |
17826 | rtx reg1, reg2, mem1, mem2; | |
17827 | if (load_p) | |
17828 | { | |
17829 | reg1 = operands[0]; | |
17830 | reg2 = operands[2]; | |
17831 | mem1 = operands[1]; | |
17832 | mem2 = operands[3]; | |
17833 | } | |
17834 | else | |
17835 | { | |
17836 | reg1 = operands[1]; | |
17837 | reg2 = operands[3]; | |
17838 | mem1 = operands[0]; | |
17839 | mem2 = operands[2]; | |
17840 | } | |
17841 | ||
17842 | if (REGNO (reg2) == REGNO (reg1) + 1) | |
17843 | { | |
17844 | umips_output_load_store_pair_1 (load_p, reg1, mem1); | |
17845 | return; | |
17846 | } | |
17847 | ||
17848 | gcc_assert (REGNO (reg1) == REGNO (reg2) + 1); | |
17849 | umips_output_load_store_pair_1 (load_p, reg2, mem2); | |
17850 | } | |
17851 | ||
17852 | /* Return true if REG1 and REG2 match the criteria for a movep insn. */ | |
17853 | ||
17854 | bool | |
17855 | umips_movep_target_p (rtx reg1, rtx reg2) | |
17856 | { | |
17857 | int regno1, regno2, pair; | |
17858 | unsigned int i; | |
17859 | static const int match[8] = { | |
17860 | 0x00000060, /* 5, 6 */ | |
17861 | 0x000000a0, /* 5, 7 */ | |
17862 | 0x000000c0, /* 6, 7 */ | |
17863 | 0x00200010, /* 4, 21 */ | |
17864 | 0x00400010, /* 4, 22 */ | |
17865 | 0x00000030, /* 4, 5 */ | |
17866 | 0x00000050, /* 4, 6 */ | |
17867 | 0x00000090 /* 4, 7 */ | |
17868 | }; | |
17869 | ||
17870 | if (!REG_P (reg1) || !REG_P (reg2)) | |
17871 | return false; | |
17872 | ||
17873 | regno1 = REGNO (reg1); | |
17874 | regno2 = REGNO (reg2); | |
17875 | ||
17876 | if (!GP_REG_P (regno1) || !GP_REG_P (regno2)) | |
17877 | return false; | |
17878 | ||
17879 | pair = (1 << regno1) | (1 << regno2); | |
17880 | ||
17881 | for (i = 0; i < ARRAY_SIZE (match); i++) | |
17882 | if (pair == match[i]) | |
17883 | return true; | |
17884 | ||
17885 | return false; | |
17886 | } | |
a1d29c8c | 17887 | \f |
c640a3bd RS |
17888 | /* Return the size in bytes of the trampoline code, padded to |
17889 | TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target | |
17890 | function address immediately follow. */ | |
a1d29c8c | 17891 | |
c640a3bd RS |
17892 | int |
17893 | mips_trampoline_code_size (void) | |
17894 | { | |
17895 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
17896 | return 4 * 4; | |
17897 | else if (ptr_mode == DImode) | |
17898 | return 8 * 4; | |
17899 | else if (ISA_HAS_LOAD_DELAY) | |
17900 | return 6 * 4; | |
a1d29c8c | 17901 | else |
c640a3bd | 17902 | return 4 * 4; |
a1d29c8c RH |
17903 | } |
17904 | ||
17905 | /* Implement TARGET_TRAMPOLINE_INIT. */ | |
17906 | ||
17907 | static void | |
17908 | mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
17909 | { | |
c640a3bd RS |
17910 | rtx addr, end_addr, high, low, opcode, mem; |
17911 | rtx trampoline[8]; | |
17912 | unsigned int i, j; | |
17913 | HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset; | |
17914 | ||
17915 | /* Work out the offsets of the pointers from the start of the | |
17916 | trampoline code. */ | |
17917 | end_addr_offset = mips_trampoline_code_size (); | |
17918 | static_chain_offset = end_addr_offset; | |
17919 | target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); | |
a1d29c8c | 17920 | |
c640a3bd RS |
17921 | /* Get pointers to the beginning and end of the code block. */ |
17922 | addr = force_reg (Pmode, XEXP (m_tramp, 0)); | |
17923 | end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset)); | |
a1d29c8c | 17924 | |
c640a3bd | 17925 | #define OP(X) gen_int_mode (X, SImode) |
a1d29c8c | 17926 | |
c640a3bd RS |
17927 | /* Build up the code in TRAMPOLINE. */ |
17928 | i = 0; | |
17929 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
17930 | { | |
17931 | /* $25 contains the address of the trampoline. Emit code of the form: | |
17932 | ||
17933 | l[wd] $1, target_function_offset($25) | |
17934 | l[wd] $static_chain, static_chain_offset($25) | |
17935 | jr $1 | |
17936 | move $25,$1. */ | |
17937 | trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM, | |
17938 | target_function_offset, | |
17939 | PIC_FUNCTION_ADDR_REGNUM)); | |
17940 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
17941 | static_chain_offset, | |
17942 | PIC_FUNCTION_ADDR_REGNUM)); | |
17943 | trampoline[i++] = OP (MIPS_JR (AT_REGNUM)); | |
17944 | trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM)); | |
17945 | } | |
17946 | else if (ptr_mode == DImode) | |
17947 | { | |
17948 | /* It's too cumbersome to create the full 64-bit address, so let's | |
17949 | instead use: | |
17950 | ||
17951 | move $1, $31 | |
17952 | bal 1f | |
17953 | nop | |
17954 | 1: l[wd] $25, target_function_offset - 12($31) | |
17955 | l[wd] $static_chain, static_chain_offset - 12($31) | |
17956 | jr $25 | |
17957 | move $31, $1 | |
17958 | ||
17959 | where 12 is the offset of "1:" from the start of the code block. */ | |
17960 | trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM)); | |
17961 | trampoline[i++] = OP (MIPS_BAL (1)); | |
17962 | trampoline[i++] = OP (MIPS_NOP); | |
17963 | trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
17964 | target_function_offset - 12, | |
17965 | RETURN_ADDR_REGNUM)); | |
17966 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
17967 | static_chain_offset - 12, | |
17968 | RETURN_ADDR_REGNUM)); | |
17969 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
17970 | trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM)); | |
17971 | } | |
17972 | else | |
17973 | { | |
17974 | /* If the target has load delays, emit: | |
17975 | ||
17976 | lui $1, %hi(end_addr) | |
17977 | lw $25, %lo(end_addr + ...)($1) | |
17978 | lw $static_chain, %lo(end_addr + ...)($1) | |
17979 | jr $25 | |
17980 | nop | |
17981 | ||
17982 | Otherwise emit: | |
17983 | ||
17984 | lui $1, %hi(end_addr) | |
17985 | lw $25, %lo(end_addr + ...)($1) | |
17986 | jr $25 | |
17987 | lw $static_chain, %lo(end_addr + ...)($1). */ | |
17988 | ||
17989 | /* Split END_ADDR into %hi and %lo values. Trampolines are aligned | |
17990 | to 64 bits, so the %lo value will have the bottom 3 bits clear. */ | |
17991 | high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000), | |
17992 | NULL, false, OPTAB_WIDEN); | |
17993 | high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16), | |
17994 | NULL, false, OPTAB_WIDEN); | |
17995 | low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true); | |
17996 | ||
17997 | /* Emit the LUI. */ | |
17998 | opcode = OP (MIPS_LUI (AT_REGNUM, 0)); | |
17999 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high, | |
18000 | NULL, false, OPTAB_WIDEN); | |
18001 | ||
18002 | /* Emit the load of the target function. */ | |
18003 | opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
18004 | target_function_offset - end_addr_offset, | |
18005 | AT_REGNUM)); | |
18006 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
18007 | NULL, false, OPTAB_WIDEN); | |
18008 | ||
18009 | /* Emit the JR here, if we can. */ | |
18010 | if (!ISA_HAS_LOAD_DELAY) | |
18011 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
18012 | ||
18013 | /* Emit the load of the static chain register. */ | |
18014 | opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
18015 | static_chain_offset - end_addr_offset, | |
18016 | AT_REGNUM)); | |
18017 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
18018 | NULL, false, OPTAB_WIDEN); | |
18019 | ||
18020 | /* Emit the JR, if we couldn't above. */ | |
18021 | if (ISA_HAS_LOAD_DELAY) | |
18022 | { | |
18023 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
18024 | trampoline[i++] = OP (MIPS_NOP); | |
18025 | } | |
18026 | } | |
18027 | ||
18028 | #undef OP | |
18029 | ||
18030 | /* Copy the trampoline code. Leave any padding uninitialized. */ | |
18031 | for (j = 0; j < i; j++) | |
18032 | { | |
18033 | mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode)); | |
18034 | mips_emit_move (mem, trampoline[j]); | |
18035 | } | |
18036 | ||
18037 | /* Set up the static chain pointer field. */ | |
18038 | mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); | |
18039 | mips_emit_move (mem, chain_value); | |
18040 | ||
18041 | /* Set up the target function field. */ | |
18042 | mem = adjust_address (m_tramp, ptr_mode, target_function_offset); | |
18043 | mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); | |
18044 | ||
18045 | /* Flush the code part of the trampoline. */ | |
a1d29c8c RH |
18046 | emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); |
18047 | emit_insn (gen_clear_cache (addr, end_addr)); | |
18048 | } | |
c376dbfb DD |
18049 | |
18050 | /* Implement FUNCTION_PROFILER. */ | |
18051 | ||
18052 | void mips_function_profiler (FILE *file) | |
18053 | { | |
18054 | if (TARGET_MIPS16) | |
18055 | sorry ("mips16 function profiling"); | |
18056 | if (TARGET_LONG_CALLS) | |
18057 | { | |
18058 | /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ | |
18059 | if (Pmode == DImode) | |
18060 | fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]); | |
18061 | else | |
18062 | fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]); | |
18063 | } | |
18064 | mips_push_asm_switch (&mips_noat); | |
18065 | fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n", | |
18066 | reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]); | |
18067 | /* _mcount treats $2 as the static chain register. */ | |
18068 | if (cfun->static_chain_decl != NULL) | |
18069 | fprintf (file, "\tmove\t%s,%s\n", reg_names[2], | |
18070 | reg_names[STATIC_CHAIN_REGNUM]); | |
18071 | if (TARGET_MCOUNT_RA_ADDRESS) | |
18072 | { | |
18073 | /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the | |
18074 | ra save location. */ | |
18075 | if (cfun->machine->frame.ra_fp_offset == 0) | |
18076 | /* ra not saved, pass zero. */ | |
18077 | fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]); | |
18078 | else | |
18079 | fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n", | |
18080 | Pmode == DImode ? "dla" : "la", reg_names[12], | |
18081 | cfun->machine->frame.ra_fp_offset, | |
18082 | reg_names[STACK_POINTER_REGNUM]); | |
18083 | } | |
18084 | if (!TARGET_NEWABI) | |
18085 | fprintf (file, | |
18086 | "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", | |
18087 | TARGET_64BIT ? "dsubu" : "subu", | |
18088 | reg_names[STACK_POINTER_REGNUM], | |
18089 | reg_names[STACK_POINTER_REGNUM], | |
18090 | Pmode == DImode ? 16 : 8); | |
18091 | ||
18092 | if (TARGET_LONG_CALLS) | |
18093 | fprintf (file, "\tjalr\t%s\n", reg_names[3]); | |
18094 | else | |
18095 | fprintf (file, "\tjal\t_mcount\n"); | |
18096 | mips_pop_asm_switch (&mips_noat); | |
18097 | /* _mcount treats $2 as the static chain register. */ | |
18098 | if (cfun->static_chain_decl != NULL) | |
18099 | fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], | |
18100 | reg_names[2]); | |
18101 | } | |
49042313 MX |
18102 | |
18103 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default | |
18104 | behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even | |
1f5f063d | 18105 | when TARGET_LOONGSON_VECTORS is true. */ |
49042313 MX |
18106 | |
18107 | static unsigned HOST_WIDE_INT | |
ef4bddc2 | 18108 | mips_shift_truncation_mask (machine_mode mode) |
49042313 | 18109 | { |
1f5f063d | 18110 | if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) |
49042313 MX |
18111 | return 0; |
18112 | ||
18113 | return GET_MODE_BITSIZE (mode) - 1; | |
18114 | } | |
18115 | ||
e32ea2d1 RS |
18116 | /* Implement TARGET_PREPARE_PCH_SAVE. */ |
18117 | ||
18118 | static void | |
18119 | mips_prepare_pch_save (void) | |
18120 | { | |
18121 | /* We are called in a context where the current MIPS16 vs. non-MIPS16 | |
18122 | setting should be irrelevant. The question then is: which setting | |
18123 | makes most sense at load time? | |
18124 | ||
18125 | The PCH is loaded before the first token is read. We should never | |
18126 | have switched into MIPS16 mode by that point, and thus should not | |
18127 | have populated mips16_globals. Nor can we load the entire contents | |
18128 | of mips16_globals from the PCH file, because mips16_globals contains | |
18129 | a combination of GGC and non-GGC data. | |
18130 | ||
18131 | There is therefore no point in trying save the GGC part of | |
18132 | mips16_globals to the PCH file, or to preserve MIPS16ness across | |
18133 | the PCH save and load. The loading compiler would not have access | |
18134 | to the non-GGC parts of mips16_globals (either from the PCH file, | |
18135 | or from a copy that the loading compiler generated itself) and would | |
18136 | have to call target_reinit anyway. | |
18137 | ||
18138 | It therefore seems best to switch back to non-MIPS16 mode at | |
18139 | save time, and to ensure that mips16_globals remains null after | |
18140 | a PCH load. */ | |
22c4c869 | 18141 | mips_set_compression_mode (0); |
e32ea2d1 RS |
18142 | mips16_globals = 0; |
18143 | } | |
ab77a036 | 18144 | \f |
7dab511c RH |
18145 | /* Generate or test for an insn that supports a constant permutation. */ |
18146 | ||
18147 | #define MAX_VECT_LEN 8 | |
18148 | ||
18149 | struct expand_vec_perm_d | |
18150 | { | |
18151 | rtx target, op0, op1; | |
18152 | unsigned char perm[MAX_VECT_LEN]; | |
ef4bddc2 | 18153 | machine_mode vmode; |
7dab511c RH |
18154 | unsigned char nelt; |
18155 | bool one_vector_p; | |
18156 | bool testing_p; | |
18157 | }; | |
18158 | ||
18159 | /* Construct (set target (vec_select op0 (parallel perm))) and | |
18160 | return true if that's a valid instruction in the active ISA. */ | |
18161 | ||
18162 | static bool | |
18163 | mips_expand_vselect (rtx target, rtx op0, | |
18164 | const unsigned char *perm, unsigned nelt) | |
18165 | { | |
18166 | rtx rperm[MAX_VECT_LEN], x; | |
647d790d | 18167 | rtx_insn *insn; |
7dab511c RH |
18168 | unsigned i; |
18169 | ||
18170 | for (i = 0; i < nelt; ++i) | |
18171 | rperm[i] = GEN_INT (perm[i]); | |
18172 | ||
18173 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); | |
18174 | x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); | |
18175 | x = gen_rtx_SET (VOIDmode, target, x); | |
18176 | ||
647d790d DM |
18177 | insn = emit_insn (x); |
18178 | if (recog_memoized (insn) < 0) | |
7dab511c | 18179 | { |
647d790d | 18180 | remove_insn (insn); |
7dab511c RH |
18181 | return false; |
18182 | } | |
18183 | return true; | |
18184 | } | |
18185 | ||
18186 | /* Similar, but generate a vec_concat from op0 and op1 as well. */ | |
18187 | ||
18188 | static bool | |
18189 | mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1, | |
18190 | const unsigned char *perm, unsigned nelt) | |
18191 | { | |
ef4bddc2 | 18192 | machine_mode v2mode; |
7dab511c RH |
18193 | rtx x; |
18194 | ||
18195 | v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0)); | |
18196 | x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); | |
18197 | return mips_expand_vselect (target, x, perm, nelt); | |
18198 | } | |
18199 | ||
18200 | /* Recognize patterns for even-odd extraction. */ | |
18201 | ||
18202 | static bool | |
18203 | mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d) | |
18204 | { | |
18205 | unsigned i, odd, nelt = d->nelt; | |
18206 | rtx t0, t1, t2, t3; | |
18207 | ||
18208 | if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) | |
18209 | return false; | |
18210 | /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */ | |
18211 | if (nelt < 4) | |
18212 | return false; | |
18213 | ||
18214 | odd = d->perm[0]; | |
18215 | if (odd > 1) | |
18216 | return false; | |
18217 | for (i = 1; i < nelt; ++i) | |
18218 | if (d->perm[i] != i * 2 + odd) | |
18219 | return false; | |
18220 | ||
18221 | if (d->testing_p) | |
18222 | return true; | |
18223 | ||
18224 | /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */ | |
18225 | t0 = gen_reg_rtx (d->vmode); | |
18226 | t1 = gen_reg_rtx (d->vmode); | |
18227 | switch (d->vmode) | |
18228 | { | |
18229 | case V4HImode: | |
18230 | emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1)); | |
18231 | emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1)); | |
18232 | if (odd) | |
18233 | emit_insn (gen_loongson_punpckhhw (d->target, t1, t0)); | |
18234 | else | |
18235 | emit_insn (gen_loongson_punpcklhw (d->target, t1, t0)); | |
18236 | break; | |
18237 | ||
18238 | case V8QImode: | |
18239 | t2 = gen_reg_rtx (d->vmode); | |
18240 | t3 = gen_reg_rtx (d->vmode); | |
18241 | emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1)); | |
18242 | emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1)); | |
18243 | emit_insn (gen_loongson_punpckhbh (t2, t1, t0)); | |
18244 | emit_insn (gen_loongson_punpcklbh (t3, t1, t0)); | |
18245 | if (odd) | |
18246 | emit_insn (gen_loongson_punpckhbh (d->target, t3, t2)); | |
18247 | else | |
18248 | emit_insn (gen_loongson_punpcklbh (d->target, t3, t2)); | |
18249 | break; | |
18250 | ||
18251 | default: | |
18252 | gcc_unreachable (); | |
18253 | } | |
18254 | return true; | |
18255 | } | |
18256 | ||
18257 | /* Recognize patterns for the Loongson PSHUFH instruction. */ | |
18258 | ||
18259 | static bool | |
18260 | mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d) | |
18261 | { | |
18262 | unsigned i, mask; | |
18263 | rtx rmask; | |
18264 | ||
18265 | if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) | |
18266 | return false; | |
18267 | if (d->vmode != V4HImode) | |
18268 | return false; | |
18269 | if (d->testing_p) | |
18270 | return true; | |
18271 | ||
18272 | /* Convert the selector into the packed 8-bit form for pshufh. */ | |
18273 | /* Recall that loongson is little-endian only. No big-endian | |
18274 | adjustment required. */ | |
18275 | for (i = mask = 0; i < 4; i++) | |
18276 | mask |= (d->perm[i] & 3) << (i * 2); | |
18277 | rmask = force_reg (SImode, GEN_INT (mask)); | |
18278 | ||
18279 | if (d->one_vector_p) | |
18280 | emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask)); | |
18281 | else | |
18282 | { | |
18283 | rtx t0, t1, x, merge, rmerge[4]; | |
18284 | ||
18285 | t0 = gen_reg_rtx (V4HImode); | |
18286 | t1 = gen_reg_rtx (V4HImode); | |
18287 | emit_insn (gen_loongson_pshufh (t1, d->op1, rmask)); | |
18288 | emit_insn (gen_loongson_pshufh (t0, d->op0, rmask)); | |
18289 | ||
18290 | for (i = 0; i < 4; ++i) | |
18291 | rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx); | |
18292 | merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge)); | |
18293 | merge = force_reg (V4HImode, merge); | |
18294 | ||
18295 | x = gen_rtx_AND (V4HImode, merge, t1); | |
18296 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
18297 | ||
18298 | x = gen_rtx_NOT (V4HImode, merge); | |
18299 | x = gen_rtx_AND (V4HImode, x, t0); | |
18300 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
18301 | ||
18302 | x = gen_rtx_IOR (V4HImode, t0, t1); | |
18303 | emit_insn (gen_rtx_SET (VOIDmode, d->target, x)); | |
18304 | } | |
18305 | ||
18306 | return true; | |
18307 | } | |
18308 | ||
18309 | /* Recognize broadcast patterns for the Loongson. */ | |
18310 | ||
18311 | static bool | |
18312 | mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d) | |
18313 | { | |
18314 | unsigned i, elt; | |
18315 | rtx t0, t1; | |
18316 | ||
18317 | if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) | |
18318 | return false; | |
18319 | /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */ | |
18320 | if (d->vmode != V8QImode) | |
18321 | return false; | |
18322 | if (!d->one_vector_p) | |
18323 | return false; | |
18324 | ||
18325 | elt = d->perm[0]; | |
18326 | for (i = 1; i < 8; ++i) | |
18327 | if (d->perm[i] != elt) | |
18328 | return false; | |
18329 | ||
18330 | if (d->testing_p) | |
18331 | return true; | |
18332 | ||
18333 | /* With one interleave we put two of the desired element adjacent. */ | |
18334 | t0 = gen_reg_rtx (V8QImode); | |
18335 | if (elt < 4) | |
18336 | emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0)); | |
18337 | else | |
18338 | emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0)); | |
18339 | ||
18340 | /* Shuffle that one HImode element into all locations. */ | |
18341 | elt &= 3; | |
18342 | elt *= 0x55; | |
18343 | t1 = gen_reg_rtx (V4HImode); | |
18344 | emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0), | |
18345 | force_reg (SImode, GEN_INT (elt)))); | |
18346 | ||
18347 | emit_move_insn (d->target, gen_lowpart (V8QImode, t1)); | |
18348 | return true; | |
18349 | } | |
18350 | ||
18351 | static bool | |
18352 | mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) | |
18353 | { | |
18354 | unsigned int i, nelt = d->nelt; | |
18355 | unsigned char perm2[MAX_VECT_LEN]; | |
18356 | ||
18357 | if (d->one_vector_p) | |
18358 | { | |
18359 | /* Try interleave with alternating operands. */ | |
18360 | memcpy (perm2, d->perm, sizeof(perm2)); | |
18361 | for (i = 1; i < nelt; i += 2) | |
18362 | perm2[i] += nelt; | |
18363 | if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt)) | |
18364 | return true; | |
18365 | } | |
18366 | else | |
18367 | { | |
18368 | if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, | |
18369 | d->perm, nelt)) | |
18370 | return true; | |
18371 | ||
18372 | /* Try again with swapped operands. */ | |
18373 | for (i = 0; i < nelt; ++i) | |
18374 | perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1); | |
18375 | if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) | |
18376 | return true; | |
18377 | } | |
18378 | ||
18379 | if (mips_expand_vpc_loongson_even_odd (d)) | |
18380 | return true; | |
18381 | if (mips_expand_vpc_loongson_pshufh (d)) | |
18382 | return true; | |
18383 | if (mips_expand_vpc_loongson_bcast (d)) | |
18384 | return true; | |
18385 | return false; | |
18386 | } | |
18387 | ||
18388 | /* Expand a vec_perm_const pattern. */ | |
18389 | ||
18390 | bool | |
18391 | mips_expand_vec_perm_const (rtx operands[4]) | |
18392 | { | |
18393 | struct expand_vec_perm_d d; | |
18394 | int i, nelt, which; | |
18395 | unsigned char orig_perm[MAX_VECT_LEN]; | |
18396 | rtx sel; | |
18397 | bool ok; | |
18398 | ||
18399 | d.target = operands[0]; | |
18400 | d.op0 = operands[1]; | |
18401 | d.op1 = operands[2]; | |
18402 | sel = operands[3]; | |
18403 | ||
18404 | d.vmode = GET_MODE (d.target); | |
18405 | gcc_assert (VECTOR_MODE_P (d.vmode)); | |
18406 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
18407 | d.testing_p = false; | |
18408 | ||
18409 | for (i = which = 0; i < nelt; ++i) | |
18410 | { | |
18411 | rtx e = XVECEXP (sel, 0, i); | |
18412 | int ei = INTVAL (e) & (2 * nelt - 1); | |
18413 | which |= (ei < nelt ? 1 : 2); | |
18414 | orig_perm[i] = ei; | |
18415 | } | |
18416 | memcpy (d.perm, orig_perm, MAX_VECT_LEN); | |
18417 | ||
18418 | switch (which) | |
18419 | { | |
18420 | default: | |
18421 | gcc_unreachable(); | |
18422 | ||
18423 | case 3: | |
18424 | d.one_vector_p = false; | |
18425 | if (!rtx_equal_p (d.op0, d.op1)) | |
18426 | break; | |
18427 | /* FALLTHRU */ | |
18428 | ||
18429 | case 2: | |
18430 | for (i = 0; i < nelt; ++i) | |
18431 | d.perm[i] &= nelt - 1; | |
18432 | d.op0 = d.op1; | |
18433 | d.one_vector_p = true; | |
18434 | break; | |
18435 | ||
18436 | case 1: | |
18437 | d.op1 = d.op0; | |
18438 | d.one_vector_p = true; | |
18439 | break; | |
18440 | } | |
18441 | ||
18442 | ok = mips_expand_vec_perm_const_1 (&d); | |
18443 | ||
18444 | /* If we were given a two-vector permutation which just happened to | |
18445 | have both input vectors equal, we folded this into a one-vector | |
18446 | permutation. There are several loongson patterns that are matched | |
18447 | via direct vec_select+vec_concat expansion, but we do not have | |
18448 | support in mips_expand_vec_perm_const_1 to guess the adjustment | |
18449 | that should be made for a single operand. Just try again with | |
18450 | the original permutation. */ | |
18451 | if (!ok && which == 3) | |
18452 | { | |
18453 | d.op0 = operands[1]; | |
18454 | d.op1 = operands[2]; | |
18455 | d.one_vector_p = false; | |
18456 | memcpy (d.perm, orig_perm, MAX_VECT_LEN); | |
18457 | ok = mips_expand_vec_perm_const_1 (&d); | |
18458 | } | |
18459 | ||
18460 | return ok; | |
18461 | } | |
18462 | ||
18463 | /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ | |
18464 | ||
18465 | static bool | |
ef4bddc2 | 18466 | mips_vectorize_vec_perm_const_ok (machine_mode vmode, |
7dab511c RH |
18467 | const unsigned char *sel) |
18468 | { | |
18469 | struct expand_vec_perm_d d; | |
18470 | unsigned int i, nelt, which; | |
18471 | bool ret; | |
18472 | ||
18473 | d.vmode = vmode; | |
18474 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
18475 | d.testing_p = true; | |
18476 | memcpy (d.perm, sel, nelt); | |
18477 | ||
18478 | /* Categorize the set of elements in the selector. */ | |
18479 | for (i = which = 0; i < nelt; ++i) | |
18480 | { | |
18481 | unsigned char e = d.perm[i]; | |
18482 | gcc_assert (e < 2 * nelt); | |
18483 | which |= (e < nelt ? 1 : 2); | |
18484 | } | |
18485 | ||
18486 | /* For all elements from second vector, fold the elements to first. */ | |
18487 | if (which == 2) | |
18488 | for (i = 0; i < nelt; ++i) | |
18489 | d.perm[i] -= nelt; | |
18490 | ||
18491 | /* Check whether the mask can be applied to the vector type. */ | |
18492 | d.one_vector_p = (which != 3); | |
18493 | ||
18494 | d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); | |
18495 | d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); | |
18496 | if (!d.one_vector_p) | |
18497 | d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); | |
18498 | ||
18499 | start_sequence (); | |
18500 | ret = mips_expand_vec_perm_const_1 (&d); | |
18501 | end_sequence (); | |
18502 | ||
18503 | return ret; | |
18504 | } | |
18505 | ||
18506 | /* Expand an integral vector unpack operation. */ | |
18507 | ||
18508 | void | |
18509 | mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) | |
18510 | { | |
ef4bddc2 | 18511 | machine_mode imode = GET_MODE (operands[1]); |
7dab511c RH |
18512 | rtx (*unpack) (rtx, rtx, rtx); |
18513 | rtx (*cmpgt) (rtx, rtx, rtx); | |
18514 | rtx tmp, dest, zero; | |
18515 | ||
18516 | switch (imode) | |
18517 | { | |
18518 | case V8QImode: | |
18519 | if (high_p) | |
18520 | unpack = gen_loongson_punpckhbh; | |
18521 | else | |
18522 | unpack = gen_loongson_punpcklbh; | |
18523 | cmpgt = gen_loongson_pcmpgtb; | |
18524 | break; | |
18525 | case V4HImode: | |
18526 | if (high_p) | |
18527 | unpack = gen_loongson_punpckhhw; | |
18528 | else | |
18529 | unpack = gen_loongson_punpcklhw; | |
18530 | cmpgt = gen_loongson_pcmpgth; | |
18531 | break; | |
18532 | default: | |
18533 | gcc_unreachable (); | |
18534 | } | |
18535 | ||
18536 | zero = force_reg (imode, CONST0_RTX (imode)); | |
18537 | if (unsigned_p) | |
18538 | tmp = zero; | |
18539 | else | |
18540 | { | |
18541 | tmp = gen_reg_rtx (imode); | |
18542 | emit_insn (cmpgt (tmp, zero, operands[1])); | |
18543 | } | |
18544 | ||
18545 | dest = gen_reg_rtx (imode); | |
18546 | emit_insn (unpack (dest, operands[1], tmp)); | |
18547 | ||
18548 | emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest)); | |
18549 | } | |
18550 | ||
18551 | /* A subroutine of mips_expand_vec_init, match constant vector elements. */ | |
18552 | ||
18553 | static inline bool | |
18554 | mips_constant_elt_p (rtx x) | |
18555 | { | |
18556 | return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE; | |
18557 | } | |
18558 | ||
18559 | /* A subroutine of mips_expand_vec_init, expand via broadcast. */ | |
18560 | ||
18561 | static void | |
ef4bddc2 | 18562 | mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt) |
7dab511c RH |
18563 | { |
18564 | struct expand_vec_perm_d d; | |
18565 | rtx t1; | |
18566 | bool ok; | |
18567 | ||
18568 | if (elt != const0_rtx) | |
18569 | elt = force_reg (GET_MODE_INNER (vmode), elt); | |
18570 | if (REG_P (elt)) | |
18571 | elt = gen_lowpart (DImode, elt); | |
18572 | ||
18573 | t1 = gen_reg_rtx (vmode); | |
18574 | switch (vmode) | |
18575 | { | |
18576 | case V8QImode: | |
18577 | emit_insn (gen_loongson_vec_init1_v8qi (t1, elt)); | |
18578 | break; | |
18579 | case V4HImode: | |
18580 | emit_insn (gen_loongson_vec_init1_v4hi (t1, elt)); | |
18581 | break; | |
18582 | default: | |
18583 | gcc_unreachable (); | |
18584 | } | |
18585 | ||
18586 | memset (&d, 0, sizeof (d)); | |
18587 | d.target = target; | |
18588 | d.op0 = t1; | |
18589 | d.op1 = t1; | |
18590 | d.vmode = vmode; | |
18591 | d.nelt = GET_MODE_NUNITS (vmode); | |
18592 | d.one_vector_p = true; | |
18593 | ||
18594 | ok = mips_expand_vec_perm_const_1 (&d); | |
18595 | gcc_assert (ok); | |
18596 | } | |
18597 | ||
18598 | /* A subroutine of mips_expand_vec_init, replacing all of the non-constant | |
18599 | elements of VALS with zeros, copy the constant vector to TARGET. */ | |
18600 | ||
18601 | static void | |
ef4bddc2 | 18602 | mips_expand_vi_constant (machine_mode vmode, unsigned nelt, |
7dab511c RH |
18603 | rtx target, rtx vals) |
18604 | { | |
18605 | rtvec vec = shallow_copy_rtvec (XVEC (vals, 0)); | |
18606 | unsigned i; | |
18607 | ||
18608 | for (i = 0; i < nelt; ++i) | |
18609 | { | |
18610 | if (!mips_constant_elt_p (RTVEC_ELT (vec, i))) | |
18611 | RTVEC_ELT (vec, i) = const0_rtx; | |
18612 | } | |
18613 | ||
18614 | emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec)); | |
18615 | } | |
18616 | ||
18617 | ||
18618 | /* A subroutine of mips_expand_vec_init, expand via pinsrh. */ | |
18619 | ||
18620 | static void | |
18621 | mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var) | |
18622 | { | |
18623 | mips_expand_vi_constant (V4HImode, 4, target, vals); | |
18624 | ||
18625 | emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var), | |
18626 | GEN_INT (one_var))); | |
18627 | } | |
18628 | ||
18629 | /* A subroutine of mips_expand_vec_init, expand anything via memory. */ | |
18630 | ||
18631 | static void | |
ef4bddc2 | 18632 | mips_expand_vi_general (machine_mode vmode, machine_mode imode, |
7dab511c RH |
18633 | unsigned nelt, unsigned nvar, rtx target, rtx vals) |
18634 | { | |
9474e8ab | 18635 | rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode)); |
7dab511c RH |
18636 | unsigned int i, isize = GET_MODE_SIZE (imode); |
18637 | ||
18638 | if (nvar < nelt) | |
18639 | mips_expand_vi_constant (vmode, nelt, mem, vals); | |
18640 | ||
18641 | for (i = 0; i < nelt; ++i) | |
18642 | { | |
18643 | rtx x = XVECEXP (vals, 0, i); | |
18644 | if (!mips_constant_elt_p (x)) | |
18645 | emit_move_insn (adjust_address (mem, imode, i * isize), x); | |
18646 | } | |
18647 | ||
18648 | emit_move_insn (target, mem); | |
18649 | } | |
18650 | ||
18651 | /* Expand a vector initialization. */ | |
18652 | ||
18653 | void | |
18654 | mips_expand_vector_init (rtx target, rtx vals) | |
18655 | { | |
ef4bddc2 RS |
18656 | machine_mode vmode = GET_MODE (target); |
18657 | machine_mode imode = GET_MODE_INNER (vmode); | |
7dab511c RH |
18658 | unsigned i, nelt = GET_MODE_NUNITS (vmode); |
18659 | unsigned nvar = 0, one_var = -1u; | |
18660 | bool all_same = true; | |
18661 | rtx x; | |
18662 | ||
18663 | for (i = 0; i < nelt; ++i) | |
18664 | { | |
18665 | x = XVECEXP (vals, 0, i); | |
18666 | if (!mips_constant_elt_p (x)) | |
18667 | nvar++, one_var = i; | |
18668 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
18669 | all_same = false; | |
18670 | } | |
18671 | ||
18672 | /* Load constants from the pool, or whatever's handy. */ | |
18673 | if (nvar == 0) | |
18674 | { | |
18675 | emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0))); | |
18676 | return; | |
18677 | } | |
18678 | ||
18679 | /* For two-part initialization, always use CONCAT. */ | |
18680 | if (nelt == 2) | |
18681 | { | |
18682 | rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0)); | |
18683 | rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1)); | |
18684 | x = gen_rtx_VEC_CONCAT (vmode, op0, op1); | |
18685 | emit_insn (gen_rtx_SET (VOIDmode, target, x)); | |
18686 | return; | |
18687 | } | |
18688 | ||
18689 | /* Loongson is the only cpu with vectors with more elements. */ | |
18690 | gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS); | |
18691 | ||
18692 | /* If all values are identical, broadcast the value. */ | |
18693 | if (all_same) | |
18694 | { | |
18695 | mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0)); | |
18696 | return; | |
18697 | } | |
18698 | ||
18699 | /* If we've only got one non-variable V4HImode, use PINSRH. */ | |
18700 | if (nvar == 1 && vmode == V4HImode) | |
18701 | { | |
18702 | mips_expand_vi_loongson_one_pinsrh (target, vals, one_var); | |
18703 | return; | |
18704 | } | |
18705 | ||
18706 | mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals); | |
18707 | } | |
18708 | ||
18709 | /* Expand a vector reduction. */ | |
18710 | ||
18711 | void | |
18712 | mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx)) | |
18713 | { | |
ef4bddc2 | 18714 | machine_mode vmode = GET_MODE (in); |
7dab511c RH |
18715 | unsigned char perm2[2]; |
18716 | rtx last, next, fold, x; | |
18717 | bool ok; | |
18718 | ||
18719 | last = in; | |
18720 | fold = gen_reg_rtx (vmode); | |
18721 | switch (vmode) | |
18722 | { | |
18723 | case V2SFmode: | |
18724 | /* Use PUL/PLU to produce { L, H } op { H, L }. | |
18725 | By reversing the pair order, rather than a pure interleave high, | |
18726 | we avoid erroneous exceptional conditions that we might otherwise | |
18727 | produce from the computation of H op H. */ | |
18728 | perm2[0] = 1; | |
18729 | perm2[1] = 2; | |
18730 | ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2); | |
18731 | gcc_assert (ok); | |
18732 | break; | |
18733 | ||
18734 | case V2SImode: | |
18735 | /* Use interleave to produce { H, L } op { H, H }. */ | |
18736 | emit_insn (gen_loongson_punpckhwd (fold, last, last)); | |
18737 | break; | |
18738 | ||
18739 | case V4HImode: | |
18740 | /* Perform the first reduction with interleave, | |
18741 | and subsequent reductions with shifts. */ | |
18742 | emit_insn (gen_loongson_punpckhwd_hi (fold, last, last)); | |
18743 | ||
18744 | next = gen_reg_rtx (vmode); | |
18745 | emit_insn (gen (next, last, fold)); | |
18746 | last = next; | |
18747 | ||
18748 | fold = gen_reg_rtx (vmode); | |
18749 | x = force_reg (SImode, GEN_INT (16)); | |
18750 | emit_insn (gen_vec_shr_v4hi (fold, last, x)); | |
18751 | break; | |
18752 | ||
18753 | case V8QImode: | |
18754 | emit_insn (gen_loongson_punpckhwd_qi (fold, last, last)); | |
18755 | ||
18756 | next = gen_reg_rtx (vmode); | |
18757 | emit_insn (gen (next, last, fold)); | |
18758 | last = next; | |
18759 | ||
18760 | fold = gen_reg_rtx (vmode); | |
18761 | x = force_reg (SImode, GEN_INT (16)); | |
18762 | emit_insn (gen_vec_shr_v8qi (fold, last, x)); | |
18763 | ||
18764 | next = gen_reg_rtx (vmode); | |
18765 | emit_insn (gen (next, last, fold)); | |
18766 | last = next; | |
18767 | ||
18768 | fold = gen_reg_rtx (vmode); | |
18769 | x = force_reg (SImode, GEN_INT (8)); | |
18770 | emit_insn (gen_vec_shr_v8qi (fold, last, x)); | |
18771 | break; | |
18772 | ||
18773 | default: | |
18774 | gcc_unreachable (); | |
18775 | } | |
18776 | ||
18777 | emit_insn (gen (target, last, fold)); | |
18778 | } | |
18779 | ||
18780 | /* Expand a vector minimum/maximum. */ | |
18781 | ||
18782 | void | |
18783 | mips_expand_vec_minmax (rtx target, rtx op0, rtx op1, | |
18784 | rtx (*cmp) (rtx, rtx, rtx), bool min_p) | |
18785 | { | |
ef4bddc2 | 18786 | machine_mode vmode = GET_MODE (target); |
7dab511c RH |
18787 | rtx tc, t0, t1, x; |
18788 | ||
18789 | tc = gen_reg_rtx (vmode); | |
18790 | t0 = gen_reg_rtx (vmode); | |
18791 | t1 = gen_reg_rtx (vmode); | |
18792 | ||
18793 | /* op0 > op1 */ | |
18794 | emit_insn (cmp (tc, op0, op1)); | |
18795 | ||
18796 | x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0)); | |
18797 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
18798 | ||
18799 | x = gen_rtx_NOT (vmode, tc); | |
18800 | x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1)); | |
18801 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
18802 | ||
18803 | x = gen_rtx_IOR (vmode, t0, t1); | |
18804 | emit_insn (gen_rtx_SET (VOIDmode, target, x)); | |
18805 | } | |
14c21302 SE |
18806 | |
18807 | /* Implement TARGET_CASE_VALUES_THRESHOLD. */ | |
18808 | ||
18809 | unsigned int | |
18810 | mips_case_values_threshold (void) | |
18811 | { | |
18812 | /* In MIPS16 mode using a larger case threshold generates smaller code. */ | |
18813 | if (TARGET_MIPS16 && optimize_size) | |
18814 | return 10; | |
18815 | else | |
18816 | return default_case_values_threshold (); | |
18817 | } | |
70b2d364 RS |
18818 | |
18819 | /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */ | |
18820 | ||
18821 | static void | |
18822 | mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) | |
18823 | { | |
18824 | if (!TARGET_HARD_FLOAT_ABI) | |
18825 | return; | |
18826 | tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL); | |
18827 | tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL); | |
18828 | tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL); | |
18829 | tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR]; | |
18830 | tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR]; | |
18831 | tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0); | |
18832 | tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI, | |
18833 | fcsr_orig_var, get_fcsr_hold_call); | |
18834 | tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var, | |
18835 | build_int_cst (MIPS_ATYPE_USI, 0xfffff003)); | |
18836 | tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI, | |
18837 | fcsr_mod_var, hold_mod_val); | |
18838 | tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var); | |
18839 | tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI, | |
18840 | hold_assign_orig, hold_assign_mod); | |
18841 | *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all, | |
18842 | set_fcsr_hold_call); | |
18843 | ||
18844 | *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var); | |
18845 | ||
18846 | tree get_fcsr_update_call = build_call_expr (get_fcsr, 0); | |
18847 | *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI, | |
18848 | exceptions_var, get_fcsr_update_call); | |
18849 | tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var); | |
18850 | *update = build2 (COMPOUND_EXPR, void_type_node, *update, | |
18851 | set_fcsr_update_call); | |
18852 | tree atomic_feraiseexcept | |
18853 | = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); | |
18854 | tree int_exceptions_var = fold_convert (integer_type_node, | |
18855 | exceptions_var); | |
18856 | tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept, | |
18857 | 1, int_exceptions_var); | |
18858 | *update = build2 (COMPOUND_EXPR, void_type_node, *update, | |
18859 | atomic_feraiseexcept_call); | |
18860 | } | |
a78cc314 RS |
18861 | |
18862 | /* Implement TARGET_SPILL_CLASS. */ | |
18863 | ||
18864 | static reg_class_t | |
18865 | mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED, | |
ef4bddc2 | 18866 | machine_mode mode ATTRIBUTE_UNUSED) |
a78cc314 RS |
18867 | { |
18868 | if (TARGET_MIPS16) | |
18869 | return SPILL_REGS; | |
18870 | return NO_REGS; | |
18871 | } | |
18872 | ||
18873 | /* Implement TARGET_LRA_P. */ | |
18874 | ||
18875 | static bool | |
18876 | mips_lra_p (void) | |
18877 | { | |
18878 | return mips_lra_flag; | |
18879 | } | |
7dab511c | 18880 | \f |
ab77a036 RS |
18881 | /* Initialize the GCC target structure. */ |
18882 | #undef TARGET_ASM_ALIGNED_HI_OP | |
18883 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
18884 | #undef TARGET_ASM_ALIGNED_SI_OP | |
18885 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
18886 | #undef TARGET_ASM_ALIGNED_DI_OP | |
18887 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
a8c1d5f8 | 18888 | |
525c561d AS |
18889 | #undef TARGET_OPTION_OVERRIDE |
18890 | #define TARGET_OPTION_OVERRIDE mips_option_override | |
18891 | ||
506d7b68 PB |
18892 | #undef TARGET_LEGITIMIZE_ADDRESS |
18893 | #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address | |
18894 | ||
ab77a036 RS |
18895 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
18896 | #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue | |
18897 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
18898 | #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue | |
18899 | #undef TARGET_ASM_SELECT_RTX_SECTION | |
18900 | #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section | |
18901 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION | |
18902 | #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section | |
4ca1f68f | 18903 | |
ab77a036 RS |
18904 | #undef TARGET_SCHED_INIT |
18905 | #define TARGET_SCHED_INIT mips_sched_init | |
18906 | #undef TARGET_SCHED_REORDER | |
18907 | #define TARGET_SCHED_REORDER mips_sched_reorder | |
18908 | #undef TARGET_SCHED_REORDER2 | |
646e6f41 | 18909 | #define TARGET_SCHED_REORDER2 mips_sched_reorder2 |
ab77a036 RS |
18910 | #undef TARGET_SCHED_VARIABLE_ISSUE |
18911 | #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue | |
18912 | #undef TARGET_SCHED_ADJUST_COST | |
18913 | #define TARGET_SCHED_ADJUST_COST mips_adjust_cost | |
18914 | #undef TARGET_SCHED_ISSUE_RATE | |
18915 | #define TARGET_SCHED_ISSUE_RATE mips_issue_rate | |
58684fa0 MK |
18916 | #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN |
18917 | #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn | |
18918 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
18919 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle | |
ab77a036 RS |
18920 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
18921 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
18922 | mips_multipass_dfa_lookahead | |
e472d6bf | 18923 | #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P |
a1c4f19f AP |
18924 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
18925 | mips_small_register_classes_for_mode_p | |
4ca1f68f | 18926 | |
ab77a036 RS |
18927 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
18928 | #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall | |
4ca1f68f | 18929 | |
ab77a036 RS |
18930 | #undef TARGET_INSERT_ATTRIBUTES |
18931 | #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes | |
18932 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
18933 | #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes | |
c979d5f5 RS |
18934 | #undef TARGET_CAN_INLINE_P |
18935 | #define TARGET_CAN_INLINE_P mips_can_inline_p | |
ab77a036 RS |
18936 | #undef TARGET_SET_CURRENT_FUNCTION |
18937 | #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function | |
06a4ab70 | 18938 | |
ab77a036 RS |
18939 | #undef TARGET_VALID_POINTER_MODE |
18940 | #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode | |
faa832a7 AS |
18941 | #undef TARGET_REGISTER_MOVE_COST |
18942 | #define TARGET_REGISTER_MOVE_COST mips_register_move_cost | |
a78cc314 RS |
18943 | #undef TARGET_REGISTER_PRIORITY |
18944 | #define TARGET_REGISTER_PRIORITY mips_register_priority | |
faa832a7 AS |
18945 | #undef TARGET_MEMORY_MOVE_COST |
18946 | #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost | |
ab77a036 RS |
18947 | #undef TARGET_RTX_COSTS |
18948 | #define TARGET_RTX_COSTS mips_rtx_costs | |
18949 | #undef TARGET_ADDRESS_COST | |
18950 | #define TARGET_ADDRESS_COST mips_address_cost | |
06a4ab70 | 18951 | |
ab77a036 RS |
18952 | #undef TARGET_IN_SMALL_DATA_P |
18953 | #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p | |
118ea793 | 18954 | |
ab77a036 RS |
18955 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18956 | #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg | |
118ea793 | 18957 | |
ef78aed6 AS |
18958 | #undef TARGET_PREFERRED_RELOAD_CLASS |
18959 | #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class | |
18960 | ||
4670abb0 RS |
18961 | #undef TARGET_EXPAND_TO_RTL_HOOK |
18962 | #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook | |
ab77a036 RS |
18963 | #undef TARGET_ASM_FILE_START |
18964 | #define TARGET_ASM_FILE_START mips_file_start | |
18965 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
18966 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
78c27266 RS |
18967 | #undef TARGET_ASM_CODE_END |
18968 | #define TARGET_ASM_CODE_END mips_code_end | |
118ea793 | 18969 | |
ab77a036 RS |
18970 | #undef TARGET_INIT_LIBFUNCS |
18971 | #define TARGET_INIT_LIBFUNCS mips_init_libfuncs | |
118ea793 | 18972 | |
ab77a036 RS |
18973 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
18974 | #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list | |
d7bd8aeb JJ |
18975 | #undef TARGET_EXPAND_BUILTIN_VA_START |
18976 | #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start | |
ab77a036 RS |
18977 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
18978 | #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr | |
118ea793 | 18979 | |
cde0f3fd PB |
18980 | #undef TARGET_PROMOTE_FUNCTION_MODE |
18981 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
ab77a036 RS |
18982 | #undef TARGET_PROMOTE_PROTOTYPES |
18983 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
118ea793 | 18984 | |
47be3d6d AS |
18985 | #undef TARGET_FUNCTION_VALUE |
18986 | #define TARGET_FUNCTION_VALUE mips_function_value | |
18987 | #undef TARGET_LIBCALL_VALUE | |
18988 | #define TARGET_LIBCALL_VALUE mips_libcall_value | |
18989 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
18990 | #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p | |
ab77a036 RS |
18991 | #undef TARGET_RETURN_IN_MEMORY |
18992 | #define TARGET_RETURN_IN_MEMORY mips_return_in_memory | |
18993 | #undef TARGET_RETURN_IN_MSB | |
18994 | #define TARGET_RETURN_IN_MSB mips_return_in_msb | |
4dbdb061 | 18995 | |
ab77a036 RS |
18996 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
18997 | #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk | |
18998 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
18999 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true | |
4dbdb061 | 19000 | |
6e9e0126 NF |
19001 | #undef TARGET_PRINT_OPERAND |
19002 | #define TARGET_PRINT_OPERAND mips_print_operand | |
19003 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
19004 | #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address | |
19005 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
19006 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p | |
19007 | ||
ab77a036 RS |
19008 | #undef TARGET_SETUP_INCOMING_VARARGS |
19009 | #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs | |
19010 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
19011 | #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming | |
19012 | #undef TARGET_MUST_PASS_IN_STACK | |
19013 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
19014 | #undef TARGET_PASS_BY_REFERENCE | |
19015 | #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference | |
19016 | #undef TARGET_CALLEE_COPIES | |
19017 | #define TARGET_CALLEE_COPIES mips_callee_copies | |
19018 | #undef TARGET_ARG_PARTIAL_BYTES | |
19019 | #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes | |
c8717ea3 NF |
19020 | #undef TARGET_FUNCTION_ARG |
19021 | #define TARGET_FUNCTION_ARG mips_function_arg | |
19022 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
19023 | #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance | |
c2ed6cf8 NF |
19024 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
19025 | #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary | |
cd3a59b3 | 19026 | |
ab77a036 RS |
19027 | #undef TARGET_MODE_REP_EXTENDED |
19028 | #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended | |
912f2dac | 19029 | |
ab77a036 RS |
19030 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
19031 | #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p | |
912f2dac | 19032 | |
ab77a036 RS |
19033 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
19034 | #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p | |
912f2dac | 19035 | |
cc4b5170 RG |
19036 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
19037 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode | |
26983c22 | 19038 | |
ab77a036 RS |
19039 | #undef TARGET_INIT_BUILTINS |
19040 | #define TARGET_INIT_BUILTINS mips_init_builtins | |
7725086e RS |
19041 | #undef TARGET_BUILTIN_DECL |
19042 | #define TARGET_BUILTIN_DECL mips_builtin_decl | |
ab77a036 RS |
19043 | #undef TARGET_EXPAND_BUILTIN |
19044 | #define TARGET_EXPAND_BUILTIN mips_expand_builtin | |
b12cbf2c | 19045 | |
ab77a036 RS |
19046 | #undef TARGET_HAVE_TLS |
19047 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
b12cbf2c | 19048 | |
ab77a036 RS |
19049 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
19050 | #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem | |
a44380d2 | 19051 | |
1a627b35 RS |
19052 | #undef TARGET_LEGITIMATE_CONSTANT_P |
19053 | #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p | |
19054 | ||
ab77a036 RS |
19055 | #undef TARGET_ENCODE_SECTION_INFO |
19056 | #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info | |
a44380d2 | 19057 | |
ab77a036 RS |
19058 | #undef TARGET_ATTRIBUTE_TABLE |
19059 | #define TARGET_ATTRIBUTE_TABLE mips_attribute_table | |
19060 | /* All our function attributes are related to how out-of-line copies should | |
19061 | be compiled or called. They don't in themselves prevent inlining. */ | |
19062 | #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P | |
19063 | #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true | |
a44380d2 | 19064 | |
ab77a036 RS |
19065 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
19066 | #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry | |
076a5ce6 | 19067 | |
ab77a036 RS |
19068 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P |
19069 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p | |
19070 | #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P | |
19071 | #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p | |
076a5ce6 | 19072 | |
ab77a036 RS |
19073 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
19074 | #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes | |
076a5ce6 | 19075 | |
ab77a036 RS |
19076 | #ifdef HAVE_AS_DTPRELWORD |
19077 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
19078 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel | |
19079 | #endif | |
19080 | #undef TARGET_DWARF_REGISTER_SPAN | |
19081 | #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span | |
076a5ce6 | 19082 | |
1afc5373 CF |
19083 | #undef TARGET_ASM_FINAL_POSTSCAN_INSN |
19084 | #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn | |
19085 | ||
c6c3dba9 PB |
19086 | #undef TARGET_LEGITIMATE_ADDRESS_P |
19087 | #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p | |
19088 | ||
b52b1749 AS |
19089 | #undef TARGET_FRAME_POINTER_REQUIRED |
19090 | #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required | |
19091 | ||
7b5cbb57 AS |
19092 | #undef TARGET_CAN_ELIMINATE |
19093 | #define TARGET_CAN_ELIMINATE mips_can_eliminate | |
19094 | ||
5efd84c5 NF |
19095 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
19096 | #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage | |
19097 | ||
a1d29c8c RH |
19098 | #undef TARGET_TRAMPOLINE_INIT |
19099 | #define TARGET_TRAMPOLINE_INIT mips_trampoline_init | |
19100 | ||
b5f5d41d AS |
19101 | #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME |
19102 | #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename | |
19103 | ||
49042313 MX |
19104 | #undef TARGET_SHIFT_TRUNCATION_MASK |
19105 | #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask | |
19106 | ||
e32ea2d1 RS |
19107 | #undef TARGET_PREPARE_PCH_SAVE |
19108 | #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save | |
19109 | ||
7dab511c RH |
19110 | #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK |
19111 | #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok | |
19112 | ||
14c21302 SE |
19113 | #undef TARGET_CASE_VALUES_THRESHOLD |
19114 | #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold | |
19115 | ||
70b2d364 RS |
19116 | #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV |
19117 | #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv | |
19118 | ||
c2db3f3d RO |
19119 | #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS |
19120 | #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true | |
19121 | ||
a78cc314 RS |
19122 | #undef TARGET_SPILL_CLASS |
19123 | #define TARGET_SPILL_CLASS mips_spill_class | |
19124 | #undef TARGET_LRA_P | |
19125 | #define TARGET_LRA_P mips_lra_p | |
19126 | ||
ab77a036 | 19127 | struct gcc_target targetm = TARGET_INITIALIZER; |
a44380d2 | 19128 | \f |
e2500fed | 19129 | #include "gt-mips.h" |