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e75b25e7 1/* Definitions of target machine for GNU compiler. MIPS version.
5624e564 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
ae3e1bb4
RK		 3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
85f65093 5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
ae3e1bb4 6 Brendan Eich (brendan@microunity.com).
e75b25e7 7
7ec022b2 8This file is part of GCC.
e75b25e7 9
7ec022b2 10GCC is free software; you can redistribute it and/or modify
e75b25e7 11it under the terms of the GNU General Public License as published by
2f83c7d6 12the Free Software Foundation; either version 3, or (at your option)
e75b25e7
MM		 13any later version.
14
7ec022b2 15GCC is distributed in the hope that it will be useful,
e75b25e7
MM		 16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
2f83c7d6
NC		 21along with GCC; see the file COPYING3. If not see
22<http://www.gnu.org/licenses/>. */
e75b25e7
MM		 23
24
8cb6400c
RS		 25#include "config/vxworks-dummy.h"
26
f770d743
JM		 27#ifdef GENERATOR_FILE
28/* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30extern int target_flags_explicit;
31#endif
32
e75b25e7
MM		 33/* MIPS external variables defined in mips.c. */
34
ac8ab9fe
RS		 35/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
85f65093 37 to work on a 64-bit machine. */
b2d8cf33 38
04bd620d
JW		 39#define ABI_32 0
40#define ABI_N32 1
41#define ABI_64 2
42#define ABI_EABI 3
a53f72db 43#define ABI_O64 4
0e5a4ad8 44
0da4c1ea
RS		 45/* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
855e0d0b
SE		 50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57#define PTF_AVOID_BRANCHLIKELY 0x1
58#define PTF_AVOID_IMADD 0x2
0da4c1ea 59
05713b80 60/* Information about one recognized processor. Defined here for the
a27fb29b
RS		 61 benefit of TARGET_CPU_CPP_BUILTINS. */
62struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
85f65093 65 designation. It should be lowercase. */
a27fb29b
RS		 66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
24609606 71 enum processor cpu;
a27fb29b
RS		 72
73 /* The ISA level that the processor implements. */
74 int isa;
0da4c1ea
RS		 75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
a27fb29b
RS		 78};
79
3af42a7b 80#include "config/mips/mips-opts.h"
c93c5160 81
3a6ee9f4
MM		 82/* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
149e4e00
MM		 89\f
90/* Run-time compilation parameters selecting different hardware subsets. */
91
8cb6400c
RS		 92/* True if we are generating position-independent VxWorks RTP code. */
93#define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
e21d5757
DJ		 95/* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97#define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100/* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101#define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
cafe096b 104/* True if the call patterns should be split into a jalr followed by
14976818 105 an instruction to restore $gp. It is only safe to split the load
0c433c31
RS		 106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
cafe096b
EC		 110
111#define TARGET_SPLIT_CALLS \
0c433c31 112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
cafe096b 113
d9870b7e
RS		 114/* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121#define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
cafe096b
EC		 127/* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
14976818
RS		 136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
cafe096b 138#define TARGET_SIBCALLS \
14976818
RS		 139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141/* True if we need to use a global offset table to access some symbols. */
8cb6400c 142#define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
14976818
RS		 143
144/* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145#define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147/* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148#define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
0c433c31
RS		 150/* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154#define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157/* True if we can use the J and JAL instructions. */
158#define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
8cb6400c
RS		 161/* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163#define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
cafe096b 164
b24513a1 165/* True if .gpword or .gpdword should be used for switch tables. */
e21d5757 166#define TARGET_GPWORD \
b24513a1 167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
cafe096b 168
49576e25
RS		 169/* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171#ifdef HAVE_LD_PERSONALITY_RELAXATION
172#define TARGET_WRITABLE_EH_FRAME 0
173#else
174#define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175#endif
176
293b77b0
CF		 177/* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178#ifdef HAVE_AS_DSPR1_MULT
179#define ISA_HAS_DSP_MULT ISA_HAS_DSP
180#else
181#define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182#endif
183
954bdd58
MF		 184/* ISA has LSA available. */
185#define ISA_HAS_LSA (mips_isa_rev >= 6)
186
187/* ISA has DLSA available. */
188#define ISA_HAS_DLSA (TARGET_64BIT && mips_isa_rev >= 6)
189
22c4c869
CM		 190/* The ISA compression flags that are currently in effect. */
191#define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
192
7cc63a88 193/* Generate mips16 code */
40a350c9 194#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
f2d6ca50 195/* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
7cc63a88 196#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
e1260576
RS		 197/* Generate mips16e register save/restore sequences. */
198#define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
2bcb2ab3 199
c93c5160
RS		 200/* True if we're generating a form of MIPS16 code in which general
201 text loads are allowed. */
202#define TARGET_MIPS16_TEXT_LOADS \
203 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
204
205/* True if we're generating a form of MIPS16 code in which PC-relative
206 loads are allowed. */
207#define TARGET_MIPS16_PCREL_LOADS \
208 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
209
ce3649d2
EC		 210/* Generic ISA defines. */
211#define ISA_MIPS1 (mips_isa == 1)
212#define ISA_MIPS2 (mips_isa == 2)
213#define ISA_MIPS3 (mips_isa == 3)
214#define ISA_MIPS4 (mips_isa == 4)
215#define ISA_MIPS32 (mips_isa == 32)
2d2a50c3 216#define ISA_MIPS32R2 (mips_isa == 33)
2b3bd040
AB		 217#define ISA_MIPS32R3 (mips_isa == 34)
218#define ISA_MIPS32R5 (mips_isa == 36)
82f84ecb 219#define ISA_MIPS32R6 (mips_isa == 37)
ce3649d2 220#define ISA_MIPS64 (mips_isa == 64)
f2d6ca50 221#define ISA_MIPS64R2 (mips_isa == 65)
2b3bd040
AB		 222#define ISA_MIPS64R3 (mips_isa == 66)
223#define ISA_MIPS64R5 (mips_isa == 68)
82f84ecb 224#define ISA_MIPS64R6 (mips_isa == 69)
ce3649d2 225
7dac2f89 226/* Architecture target defines. */
f2d6ca50
AN		 227#define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
228#define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
229#define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
98824c6f 230#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
7dac2f89
EC		 231#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
232#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
3f7967e3 233#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
cf768d70 234#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
5ce6f47b
EC		 235#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
236#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
107eea2c 237#define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
5fe25f47 238#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
98450f0d 239#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
38a53a0e 240#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
ed60a04b
N		 241 || mips_arch == PROCESSOR_OCTEON2 \
242 || mips_arch == PROCESSOR_OCTEON3)
243#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
244 || mips_arch == PROCESSOR_OCTEON3)
c81d6e2a
JW		 245#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
246 || mips_arch == PROCESSOR_SB1A)
5ce6f47b 247#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
6399761a 248#define TARGET_XLP (mips_arch == PROCESSOR_XLP)
7dac2f89
EC		 249
250/* Scheduling target defines. */
f2d6ca50
AN		 251#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
252#define TUNE_24K (mips_tune == PROCESSOR_24KC \
253 || mips_tune == PROCESSOR_24KF2_1 \
254 || mips_tune == PROCESSOR_24KF1_1)
255#define TUNE_74K (mips_tune == PROCESSOR_74KC \
256 || mips_tune == PROCESSOR_74KF2_1 \
257 || mips_tune == PROCESSOR_74KF1_1 \
258 || mips_tune == PROCESSOR_74KF3_2)
259#define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
260 || mips_tune == PROCESSOR_LOONGSON_2F)
98824c6f 261#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
7a38df19
EC		 262#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
263#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
264#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
dc884a86
RS		 265#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
266#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
7a38df19 267#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
5ce6f47b
EC		 268#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
269#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
7a38df19 270#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
5fe25f47 271#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
98450f0d 272#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
38a53a0e 273#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
ed60a04b
N		 274 || mips_tune == PROCESSOR_OCTEON2 \
275 || mips_tune == PROCESSOR_OCTEON3)
c81d6e2a
JW		 276#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
277 || mips_tune == PROCESSOR_SB1A)
aaaa9efc 278#define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
7dac2f89 279
93581857
MS		 280/* Whether vector modes and intrinsics for ST Microelectronics
281 Loongson-2E/2F processors should be enabled. In o32 pairs of
282 floating-point registers provide 64-bit values. */
283#define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
98824c6f
MS		 284 && (TARGET_LOONGSON_2EF \
285 || TARGET_LOONGSON_3A))
93581857 286
39ba1719
RS		 287/* True if the pre-reload scheduler should try to create chains of
288 multiply-add or multiply-subtract instructions. For example,
289 suppose we have:
290
291 t1 = a * b
292 t2 = t1 + c * d
d0cb84e9
RS		 293 t3 = e * f
294 t4 = t3 - g * h
39ba1719 295
d0cb84e9 296 t1 will have a higher priority than t2 and t3 will have a higher
39ba1719
RS		 297 priority than t4. However, before reload, there is no dependence
298 between t1 and t3, and they can often have similar priorities.
299 The scheduler will then tend to prefer:
300
301 t1 = a * b
302 t3 = e * f
303 t2 = t1 + c * d
304 t4 = t3 - g * h
305
306 which stops us from making full use of macc/madd-style instructions.
307 This sort of situation occurs frequently in Fourier transforms and
308 in unrolled loops.
309
310 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
311 queue so that chained multiply-add and multiply-subtract instructions
312 appear ahead of any other instruction that is likely to clobber lo.
313 In the example above, if t2 and t3 become ready at the same time,
314 the code ensures that t2 is scheduled first.
315
316 Multiply-accumulate instructions are a bigger win for some targets
317 than others, so this macro is defined on an opt-in basis. */
dc884a86
RS		 318#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
319 || TUNE_MIPS4120 \
d56b9f12 320 || TUNE_MIPS4130 \
aaaa9efc
JP		 321 || TUNE_24K \
322 || TUNE_P5600)
39ba1719 323
7f9be256 324#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
cafe096b
EC		 325#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
326
cc4ebe7d
SL		 327/* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
328 directly accessible, while the command-line options select
329 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
330 in use. */
331#define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
332#define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
068ca03a 333
050af144
MF		 334/* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
335 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
336#define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
337
338/* TARGET_O32_FP64A_ABI represents all the conditions that form the
339 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
340#define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
341 && !TARGET_ODD_SPREG)
342
068ca03a
DD		 343/* False if SC acts as a memory barrier with respect to itself,
344 otherwise a SYNC will be emitted after SC for atomic operations
345 that require ordering between the SC and following loads and
346 stores. It does not tell anything about ordering of loads and
347 stores prior to and following the SC, only about the SC itself and
348 those loads and stores follow it. */
6399761a 349#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
068ca03a 350
a27fb29b
RS		 351/* Define preprocessor macros for the -march and -mtune options.
352 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
353 processor. If INFO's canonical name is "foo", define PREFIX to
354 be "foo", and define an additional macro PREFIX_FOO. */
355#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
356 do \
357 { \
358 char *macro, *p; \
359 \
360 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
361 for (p = macro; *p != 0; p++) \
14f2a7e2
AP		 362 if (*p == '+') \
363 *p = 'P'; \
364 else \
365 *p = TOUPPER (*p); \
a27fb29b
RS		 366 \
367 builtin_define (macro); \
368 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
369 free (macro); \
370 } \
371 while (0)
372
ce3649d2 373/* Target CPU builtins. */
0ea339ea
NS		 374#define TARGET_CPU_CPP_BUILTINS() \
375 do \
376 { \
b24513a1 377 builtin_assert ("machine=mips"); \
0ea339ea
NS		 378 builtin_assert ("cpu=mips"); \
379 builtin_define ("__mips__"); \
380 builtin_define ("_mips"); \
381 \
a7f051fe
RS		 382 /* We do this here because __mips is defined below and so we \
383 can't use builtin_define_std. We don't ever want to define \
384 "mips" for VxWorks because some of the VxWorks headers \
385 construct include filenames from a root directory macro, \
386 an architecture macro and a filename, where the architecture \
387 macro expands to 'mips'. If we define 'mips' to 1, the \
388 architecture macro expands to 1 as well. */ \
389 if (!flag_iso && !TARGET_VXWORKS) \
0ea339ea
NS		 390 builtin_define ("mips"); \
391 \
392 if (TARGET_64BIT) \
393 builtin_define ("__mips64"); \
394 \
b24513a1
RO		 395 /* Treat _R3000 and _R4000 like register-size \
396 defines, which is how they've historically \
397 been used. */ \
398 if (TARGET_64BIT) \
0ea339ea 399 { \
b24513a1
RO		 400 builtin_define_std ("R4000"); \
401 builtin_define ("_R4000"); \
402 } \
403 else \
404 { \
405 builtin_define_std ("R3000"); \
406 builtin_define ("_R3000"); \
0ea339ea 407 } \
b24513a1 408 \
0ea339ea
NS		 409 if (TARGET_FLOAT64) \
410 builtin_define ("__mips_fpr=64"); \
050af144
MF		 411 else if (TARGET_FLOATXX) \
412 builtin_define ("__mips_fpr=0"); \
0ea339ea
NS		 413 else \
414 builtin_define ("__mips_fpr=32"); \
415 \
22c4c869 416 if (mips_base_compression_flags & MASK_MIPS16) \
0ea339ea
NS		 417 builtin_define ("__mips16"); \
418 \
419 if (TARGET_MIPS3D) \
420 builtin_define ("__mips3d"); \
421 \
422 if (TARGET_SMARTMIPS) \
423 builtin_define ("__mips_smartmips"); \
424 \
22c4c869
CM		 425 if (mips_base_compression_flags & MASK_MICROMIPS) \
426 builtin_define ("__mips_micromips"); \
427 \
5cb5a23f
MR		 428 if (TARGET_MCU) \
429 builtin_define ("__mips_mcu"); \
430 \
44b20bb8
CM		 431 if (TARGET_EVA) \
432 builtin_define ("__mips_eva"); \
433 \
0ea339ea
NS		 434 if (TARGET_DSP) \
435 { \
436 builtin_define ("__mips_dsp"); \
437 if (TARGET_DSPR2) \
438 { \
439 builtin_define ("__mips_dspr2"); \
440 builtin_define ("__mips_dsp_rev=2"); \
441 } \
442 else \
443 builtin_define ("__mips_dsp_rev=1"); \
444 } \
445 \
446 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
447 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
448 \
449 if (ISA_MIPS1) \
450 { \
451 builtin_define ("__mips=1"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
453 } \
454 else if (ISA_MIPS2) \
455 { \
456 builtin_define ("__mips=2"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
458 } \
459 else if (ISA_MIPS3) \
460 { \
461 builtin_define ("__mips=3"); \
462 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
463 } \
464 else if (ISA_MIPS4) \
465 { \
466 builtin_define ("__mips=4"); \
467 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
468 } \
82f84ecb 469 else if (mips_isa >= 32 && mips_isa < 64) \
0ea339ea
NS		 470 { \
471 builtin_define ("__mips=32"); \
0ea339ea
NS		 472 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
473 } \
82f84ecb 474 else if (mips_isa >= 64) \
2b3bd040
AB		 475 { \
476 builtin_define ("__mips=64"); \
477 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
478 } \
ad782bc9
RS		 479 if (mips_isa_rev > 0) \
480 builtin_define_with_int_value ("__mips_isa_rev", \
481 mips_isa_rev); \
0ea339ea
NS		 482 \
483 switch (mips_abi) \
484 { \
485 case ABI_32: \
486 builtin_define ("_ABIO32=1"); \
487 builtin_define ("_MIPS_SIM=_ABIO32"); \
488 break; \
489 \
490 case ABI_N32: \
491 builtin_define ("_ABIN32=2"); \
492 builtin_define ("_MIPS_SIM=_ABIN32"); \
493 break; \
494 \
495 case ABI_64: \
496 builtin_define ("_ABI64=3"); \
497 builtin_define ("_MIPS_SIM=_ABI64"); \
498 break; \
499 \
500 case ABI_O64: \
501 builtin_define ("_ABIO64=4"); \
502 builtin_define ("_MIPS_SIM=_ABIO64"); \
503 break; \
504 } \
505 \
506 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
507 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
508 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
509 builtin_define_with_int_value ("_MIPS_FPSET", \
510 32 / MAX_FPRS_PER_FMT); \
050af144
MF		 511 builtin_define_with_int_value ("_MIPS_SPFPSET", \
512 TARGET_ODD_SPREG ? 32 : 16); \
0ea339ea
NS		 513 \
514 /* These defines reflect the ABI in use, not whether the \
515 FPU is directly accessible. */ \
9f946bc1
RS		 516 if (TARGET_NO_FLOAT) \
517 builtin_define ("__mips_no_float"); \
518 else if (TARGET_HARD_FLOAT_ABI) \
0ea339ea
NS		 519 builtin_define ("__mips_hard_float"); \
520 else \
521 builtin_define ("__mips_soft_float"); \
522 \
523 if (TARGET_SINGLE_FLOAT) \
524 builtin_define ("__mips_single_float"); \
525 \
526 if (TARGET_PAIRED_SINGLE_FLOAT) \
527 builtin_define ("__mips_paired_single_float"); \
528 \
ff3f3951
MR		 529 if (mips_abs == MIPS_IEEE_754_2008) \
530 builtin_define ("__mips_abs2008"); \
531 \
532 if (mips_nan == MIPS_IEEE_754_2008) \
533 builtin_define ("__mips_nan2008"); \
534 \
0ea339ea
NS		 535 if (TARGET_BIG_ENDIAN) \
536 { \
537 builtin_define_std ("MIPSEB"); \
538 builtin_define ("_MIPSEB"); \
539 } \
540 else \
541 { \
542 builtin_define_std ("MIPSEL"); \
543 builtin_define ("_MIPSEL"); \
544 } \
93581857 545 \
cf51e479
RS		 546 /* Whether calls should go through $25. The separate __PIC__ \
547 macro indicates whether abicalls code might use a GOT. */ \
548 if (TARGET_ABICALLS) \
549 builtin_define ("__mips_abicalls"); \
550 \
93581857
MS		 551 /* Whether Loongson vector modes are enabled. */ \
552 if (TARGET_LOONGSON_VECTORS) \
553 builtin_define ("__mips_loongson_vector_rev"); \
0ea339ea 554 \
d97e6aca
AN		 555 /* Historical Octeon macro. */ \
556 if (TARGET_OCTEON) \
557 builtin_define ("__OCTEON__"); \
558 \
166c02bd
RS		 559 if (TARGET_SYNCI) \
560 builtin_define ("__mips_synci"); \
561 \
0ea339ea
NS		 562 /* Macros dependent on the C dialect. */ \
563 if (preprocessing_asm_p ()) \
564 { \
565 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
566 builtin_define ("_LANGUAGE_ASSEMBLY"); \
567 } \
568 else if (c_dialect_cxx ()) \
569 { \
570 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
571 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
572 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
573 } \
574 else \
575 { \
576 builtin_define_std ("LANGUAGE_C"); \
577 builtin_define ("_LANGUAGE_C"); \
578 } \
579 if (c_dialect_objc ()) \
580 { \
581 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
582 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
b24513a1 583 /* Bizarre, but retained for backwards compatibility. */ \
0ea339ea
NS		 584 builtin_define_std ("LANGUAGE_C"); \
585 builtin_define ("_LANGUAGE_C"); \
586 } \
587 \
588 if (mips_abi == ABI_EABI) \
589 builtin_define ("__mips_eabi"); \
4d210b07
RS		 590 \
591 if (TARGET_CACHE_BUILTIN) \
592 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
0ea339ea
NS		 593 } \
594 while (0)
ce3649d2 595
149e4e00
MM		 596/* Default target_flags if no switches are specified */
597
598#ifndef TARGET_DEFAULT
599#define TARGET_DEFAULT 0
600#endif
601
404f986e
MM		 602#ifndef TARGET_CPU_DEFAULT
603#define TARGET_CPU_DEFAULT 0
604#endif
605
96abdcb1 606#ifndef TARGET_ENDIAN_DEFAULT
96abdcb1 607#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
96abdcb1
ILT		 608#endif
609
996ed075
JJ		 610#ifdef IN_LIBGCC2
611#undef TARGET_64BIT
612/* Make this compile time constant for libgcc2 */
613#ifdef __mips64
614#define TARGET_64BIT 1
615#else
616#define TARGET_64BIT 0
617#endif
440927ec 618#endif /* IN_LIBGCC2 */
996ed075 619
56e449d3
SL		 620/* Force the call stack unwinders in unwind.inc not to be MIPS16 code
621 when compiled with hardware floating point. This is because MIPS16
622 code cannot save and restore the floating-point registers, which is
623 important if in a mixed MIPS16/non-MIPS16 environment. */
624
625#ifdef IN_LIBGCC2
626#if __mips_hard_float
627#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
628#endif
629#endif /* IN_LIBGCC2 */
630
a0cfeb0f
DD		 631#define TARGET_LIBGCC_SDATA_SECTION ".sdata"
632
cbab8d02 633#ifndef MULTILIB_ENDIAN_DEFAULT
7f2e00db 634#if TARGET_ENDIAN_DEFAULT == 0
cbab8d02 635#define MULTILIB_ENDIAN_DEFAULT "EL"
7f2e00db 636#else
cbab8d02
GRK		 637#define MULTILIB_ENDIAN_DEFAULT "EB"
638#endif
7f2e00db 639#endif
cbab8d02 640
ea09f032 641#ifndef MULTILIB_ISA_DEFAULT
44e88db2
RS		 642#if MIPS_ISA_DEFAULT == 1
643#define MULTILIB_ISA_DEFAULT "mips1"
644#elif MIPS_ISA_DEFAULT == 2
645#define MULTILIB_ISA_DEFAULT "mips2"
646#elif MIPS_ISA_DEFAULT == 3
647#define MULTILIB_ISA_DEFAULT "mips3"
648#elif MIPS_ISA_DEFAULT == 4
649#define MULTILIB_ISA_DEFAULT "mips4"
650#elif MIPS_ISA_DEFAULT == 32
651#define MULTILIB_ISA_DEFAULT "mips32"
652#elif MIPS_ISA_DEFAULT == 33
653#define MULTILIB_ISA_DEFAULT "mips32r2"
82f84ecb
MF		 654#elif MIPS_ISA_DEFAULT == 37
655#define MULTILIB_ISA_DEFAULT "mips32r6"
44e88db2
RS		 656#elif MIPS_ISA_DEFAULT == 64
657#define MULTILIB_ISA_DEFAULT "mips64"
658#elif MIPS_ISA_DEFAULT == 65
659#define MULTILIB_ISA_DEFAULT "mips64r2"
82f84ecb
MF		 660#elif MIPS_ISA_DEFAULT == 69
661#define MULTILIB_ISA_DEFAULT "mips64r6"
44e88db2
RS		 662#else
663#define MULTILIB_ISA_DEFAULT "mips1"
664#endif
ea09f032
GRK		 665#endif
666
1ab8a8c2
JM		 667#ifndef MIPS_ABI_DEFAULT
668#define MIPS_ABI_DEFAULT ABI_32
669#endif
670
671/* Use the most portable ABI flag for the ASM specs. */
672
673#if MIPS_ABI_DEFAULT == ABI_32
674#define MULTILIB_ABI_DEFAULT "mabi=32"
44e88db2 675#elif MIPS_ABI_DEFAULT == ABI_O64
1ab8a8c2 676#define MULTILIB_ABI_DEFAULT "mabi=o64"
44e88db2 677#elif MIPS_ABI_DEFAULT == ABI_N32
1ab8a8c2 678#define MULTILIB_ABI_DEFAULT "mabi=n32"
44e88db2 679#elif MIPS_ABI_DEFAULT == ABI_64
1ab8a8c2 680#define MULTILIB_ABI_DEFAULT "mabi=64"
44e88db2 681#elif MIPS_ABI_DEFAULT == ABI_EABI
1ab8a8c2
JM		 682#define MULTILIB_ABI_DEFAULT "mabi=eabi"
683#endif
684
cbab8d02 685#ifndef MULTILIB_DEFAULTS
a27fb29b
RS		 686#define MULTILIB_DEFAULTS \
687 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
7f2e00db
RK		 688#endif
689
34bcd7fd
JW		 690/* We must pass -EL to the linker by default for little endian embedded
691 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
692 linker will default to using big-endian output files. The OUTPUT_FORMAT
693 line must be in the linker script, otherwise -EB/-EL will not work. */
694
120dc6cd 695#ifndef ENDIAN_SPEC
34bcd7fd 696#if TARGET_ENDIAN_DEFAULT == 0
ac282977 697#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
34bcd7fd 698#else
ac282977 699#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
34bcd7fd
JW		 700#endif
701#endif
702
e2c14f5d
RS		 703/* A spec condition that matches all non-mips16 -mips arguments. */
704
705#define MIPS_ISA_LEVEL_OPTION_SPEC \
706 "mips1|mips2|mips3|mips4|mips32*|mips64*"
707
708/* A spec condition that matches all non-mips16 architecture arguments. */
709
710#define MIPS_ARCH_OPTION_SPEC \
711 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
712
fcd7669c 713/* A spec that infers a -mips argument from an -march argument. */
e2c14f5d
RS		 714
715#define MIPS_ISA_LEVEL_SPEC \
716 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
717 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
718 %{march=mips2|march=r6000:-mips2} \
33db2060 719 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
304b14b1
JK		 720 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
721 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
9e32002f
RS		 722 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
723 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
22c4c869 724 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
2b3bd040 725 %{march=mips32r3: -mips32r3} \
aaaa9efc 726 %{march=mips32r5|march=p5600: -mips32r5} \
82f84ecb 727 %{march=mips32r6: -mips32r6} \
0051ef59 728 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
0c72fa78
H		 729 |march=xlr: -mips64} \
730 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
2b3bd040
AB		 731 %{march=mips64r3: -mips64r3} \
732 %{march=mips64r5: -mips64r5} \
fcd7669c
MF		 733 %{march=mips64r6: -mips64r6}}"
734
735/* A spec that injects the default multilib ISA if no architecture is
736 specified. */
737
738#define MIPS_DEFAULT_ISA_LEVEL_SPEC \
739 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
0ea339ea
NS		 740 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
741
7d8bed7b
RS		 742/* A spec that infers a -mhard-float or -msoft-float setting from an
743 -march argument. Note that soft-float and hard-float code are not
744 link-compatible. */
745
746#define MIPS_ARCH_FLOAT_SPEC \
3df0998b 747 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
7d8bed7b 748 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
fdd195f4 749 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
22c4c869 750 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
7d8bed7b
RS		 751 march=*: -mhard-float}"
752
0ea339ea
NS		 753/* A spec condition that matches 32-bit options. It only works if
754 MIPS_ISA_LEVEL_SPEC has been applied. */
755
756#define MIPS_32BIT_OPTION_SPEC \
757 "mips1|mips2|mips32*|mgp32"
e2c14f5d 758
050af144
MF		 759/* A spec condition that matches architectures should be targeted with
760 o32 FPXX for compatibility reasons. */
761#define MIPS_FPXX_OPTION_SPEC \
762 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
763 mips64|mips64r2|mips64r3|mips64r5"
764
965c1798
SE		 765/* Infer a -msynci setting from a -mips argument, on the assumption that
766 -msynci is desired where possible. */
767#define MIPS_ISA_SYNCI_SPEC \
82f84ecb
MF		 768 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
769 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
770
fcd7669c 771/* Infer a -mnan=2008 setting from a -mips argument. */
82f84ecb
MF		 772#define MIPS_ISA_NAN2008_SPEC \
773 "%{mnan*:;mips32r6|mips64r6:-mnan=2008}"
965c1798 774
44e88db2
RS		 775#if (MIPS_ABI_DEFAULT == ABI_O64 \
776 || MIPS_ABI_DEFAULT == ABI_N32 \
777 || MIPS_ABI_DEFAULT == ABI_64)
1ab8a8c2
JM		 778#define OPT_ARCH64 "mabi=32|mgp32:;"
779#define OPT_ARCH32 "mabi=32|mgp32"
780#else
781#define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
782#define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
783#endif
784
7816bea0
DJ		 785/* Support for a compile-time default CPU, et cetera. The rules are:
786 --with-arch is ignored if -march is specified or a -mips is specified
1ab8a8c2
JM		 787 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
788 --with-tune is ignored if -mtune is specified; likewise
789 --with-tune-32 and --with-tune-64.
7816bea0
DJ		 790 --with-abi is ignored if -mabi is specified.
791 --with-float is ignored if -mhard-float or -msoft-float are
9f0df97a 792 specified.
050af144
MF		 793 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
794 specified.
ff3f3951 795 --with-nan is ignored if -mnan is specified.
050af144
MF		 796 --with-fp-32 is ignored if -msoft-float, -msingle-float or -mfp are specified.
797 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
798 or -mno-odd-spreg are specified.
9f0df97a
DD		 799 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
800 specified. */
7816bea0 801#define OPTION_DEFAULT_SPECS \
e2c14f5d 802 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
1ab8a8c2
JM		 803 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
804 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
7816bea0 805 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
1ab8a8c2
JM		 806 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
807 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
7816bea0 808 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
9f0df97a 809 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
050af144 810 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
ff3f3951 811 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
050af144
MF		 812 {"fp_32", "%{" OPT_ARCH32 \
813 ":%{!msoft-float:%{!msingle-float:%{!mfp*:-mfp%(VALUE)}}}}" }, \
814 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
815 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
66471b47 816 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
e21d5757 817 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
b96c5923
DD		 818 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
819 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
9f0df97a 820
fcd7669c
MF		 821/* A spec that infers the:
822 -mnan=2008 setting from a -mips argument,
823 -mdsp setting from a -march argument. */
7f75ae86 824#define BASE_DRIVER_SELF_SPECS \
82f84ecb 825 MIPS_ISA_NAN2008_SPEC, \
037f9973 826 "%{!mno-dsp: \
fdd195f4 827 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
8e932114 828 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
7f75ae86 829
82f84ecb
MF		 830#define DRIVER_SELF_SPECS \
831 MIPS_ISA_LEVEL_SPEC, \
832 BASE_DRIVER_SELF_SPECS
7f75ae86 833
9f0df97a
DD		 834#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
835 && ISA_HAS_COND_TRAP)
7816bea0 836
0da4c1ea 837#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
e4f5c5d6 838
a27fb29b
RS		 839/* True if the ABI can only work with 64-bit integer registers. We
840 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
841 otherwise floating-point registers must also be 64-bit. */
7f9be256 842#define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
a27fb29b
RS		 843
844/* Likewise for 32-bit regs. */
845#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
846
2e8a796f
RS		 847/* True if the file format uses 64-bit symbols. At present, this is
848 only true for n64, which uses 64-bit ELF. */
849#define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
850
851/* True if symbols are 64 bits wide. This is usually determined by
852 the ABI's file format, but it can be overridden by -msym32. Note that
853 overriding the size with -msym32 changes the ABI of relocatable objects,
854 although it doesn't change the ABI of a fully-linked object. */
81a478c8
RS		 855#define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
856 && Pmode == DImode \
857 && !TARGET_SYM32)
cafe096b 858
85f65093 859/* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
8f2e3902
EC		 860#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
861 || ISA_MIPS4 \
f2d6ca50 862 || ISA_MIPS64 \
2b3bd040
AB		 863 || ISA_MIPS64R2 \
864 || ISA_MIPS64R3 \
82f84ecb
MF		 865 || ISA_MIPS64R5 \
866 || ISA_MIPS64R6)
867
868#define ISA_HAS_JR (mips_isa_rev <= 5)
1d5d552e 869
112cdef5 870/* ISA has branch likely instructions (e.g. mips2). */
7dac2f89
EC		 871/* Disable branchlikely for tx39 until compare rewrite. They haven't
872 been generated up to this point. */
82f84ecb 873#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
1d5d552e 874
050af144
MF		 875/* ISA has 32 single-precision registers. */
876#define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
877 && !TARGET_LOONGSON_3A) \
878 || TARGET_FLOAT64 \
879 || TARGET_MIPS5900)
880
2f8e468b 881/* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
3f07249e
RS		 882#define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
883 || TARGET_MIPS5400 \
884 || TARGET_MIPS5500 \
0de86a92 885 || TARGET_MIPS5900 \
3f07249e
RS		 886 || TARGET_MIPS7000 \
887 || TARGET_MIPS9000 \
888 || TARGET_MAD \
82f84ecb
MF		 889 || (mips_isa_rev >= 1 \
890 && mips_isa_rev <= 5)) \
3f07249e
RS		 891 && !TARGET_MIPS16)
892
d6d3e623 893/* ISA has a three-operand multiplication instruction. */
aa5409e7
AN		 894#define ISA_HAS_DMUL3 (TARGET_64BIT \
895 && TARGET_OCTEON \
896 && !TARGET_MIPS16)
d6d3e623 897
82f84ecb
MF		 898/* ISA has HI and LO registers. */
899#define ISA_HAS_HILO (mips_isa_rev <= 5)
900
0de86a92 901/* ISA supports instructions DMULT and DMULTU. */
82f84ecb
MF		 902#define ISA_HAS_DMULT (TARGET_64BIT \
903 && !TARGET_MIPS5900 \
904 && mips_isa_rev <= 5)
0de86a92 905
82f84ecb
MF		 906/* ISA supports instructions MULT and MULTU. */
907#define ISA_HAS_MULT (mips_isa_rev <= 5)
908
909/* ISA supports instructions MUL, MULU, MUH, MUHU. */
910#define ISA_HAS_R6MUL (mips_isa_rev >= 6)
911
912/* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
913#define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
0de86a92
JU		 914
915/* ISA supports instructions DDIV and DDIVU. */
82f84ecb
MF		 916#define ISA_HAS_DDIV (TARGET_64BIT \
917 && !TARGET_MIPS5900 \
918 && mips_isa_rev <= 5)
0de86a92
JU		 919
920/* ISA supports instructions DIV and DIVU.
921 This is always true, but the macro is needed for ISA_HAS_<D>DIV
922 in mips.md. */
82f84ecb 923#define ISA_HAS_DIV (mips_isa_rev <= 5)
0de86a92 924
44e88db2
RS		 925#define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
926 || TARGET_LOONGSON_3A) \
927 && !TARGET_MIPS16)
928
82f84ecb
MF		 929/* ISA supports instructions DIV, DIVU, MOD and MODU. */
930#define ISA_HAS_R6DIV (mips_isa_rev >= 6)
931
932/* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
933#define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
934
b51469a5
MK		 935/* ISA has the floating-point conditional move instructions introduced
936 in mips4. */
937#define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
82f84ecb
MF		 938 || (mips_isa_rev >= 1 \
939 && mips_isa_rev <= 5)) \
3f07249e 940 && !TARGET_MIPS5500 \
ce3649d2 941 && !TARGET_MIPS16)
76ee8042 942
b51469a5
MK		 943/* ISA has the integer conditional move instructions introduced in mips4 and
944 ST Loongson 2E/2F. */
107eea2c
JU		 945#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
946 || TARGET_MIPS5900 \
947 || TARGET_LOONGSON_2EF)
b51469a5 948
f457938f 949/* ISA has LDC1 and SDC1. */
04dfc6df
JU		 950#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
951 && !TARGET_MIPS5900 \
952 && !TARGET_MIPS16)
f457938f 953
76ee8042 954/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
987ba558 955 branch on CC, and move (both FP and non-FP) on CC. */
82f84ecb
MF		 956#define ISA_HAS_8CC (ISA_MIPS4 \
957 || (mips_isa_rev >= 1 \
958 && mips_isa_rev <= 5))
959
960/* ISA has the FP condition code instructions that store the flag in an
961 FP register. */
962#define ISA_HAS_CCF (mips_isa_rev >= 6)
963
964#define ISA_HAS_SEL (mips_isa_rev >= 6)
76ee8042 965
4dbe1556
CD		 966/* This is a catch all for other mips4 instructions: indexed load, the
967 FP madd and msub instructions, and the FP recip and recip sqrt
7cfe3cc1
MR		 968 instructions. Note that this macro should only be used by other
969 ISA_HAS_* macros. */
3f07249e 970#define ISA_HAS_FP4 ((ISA_MIPS4 \
f2d6ca50 971 || ISA_MIPS64 \
82f84ecb
MF		 972 || (mips_isa_rev >= 2 \
973 && mips_isa_rev <= 5)) \
3f07249e 974 && !TARGET_MIPS16)
76ee8042 975
7cfe3cc1
MR		 976/* ISA has floating-point indexed load and store instructions
977 (LWXC1, LDXC1, SWXC1 and SDXC1). */
978#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
979
e5a2b69d 980/* ISA has paired-single instructions. */
82f84ecb
MF		 981#define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 \
982 || (mips_isa_rev >= 2 \
983 && mips_isa_rev <= 5))
e5a2b69d 984
a0b6cdee 985/* ISA has conditional trap instructions. */
ce3649d2
EC		 986#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
987 && !TARGET_MIPS16)
1d5d552e 988
82f84ecb
MF		 989/* ISA has conditional trap with immediate instructions. */
990#define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
991 && mips_isa_rev <= 5 \
992 && !TARGET_MIPS16)
993
12bf26b6 994/* ISA has integer multiply-accumulate instructions, madd and msub. */
82f84ecb
MF		 995#define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
996 && mips_isa_rev <= 5)
0e5a4ad8 997
8dd58f01 998/* Integer multiply-accumulate instructions should be generated. */
855e0d0b 999#define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
8dd58f01 1000
b51469a5 1001/* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
7cfe3cc1 1002#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
b51469a5 1003
82f84ecb
MF		 1004/* ISA has floating-point MADDF and MSUBF instructions 'd = d [+-] a * b'. */
1005#define ISA_HAS_FP_MADDF_MSUBF (mips_isa_rev >= 6)
1006
b51469a5
MK		 1007/* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
1008#define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
1009
1010/* ISA has floating-point nmadd and nmsub instructions
1011 'd = -((a * b) [+-] c)'. */
7cfe3cc1 1012#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
149e4e00 1013
b51469a5
MK		 1014/* ISA has floating-point nmadd and nmsub instructions
1015 'c = -((a * b) [+-] c)'. */
f900a982 1016#define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
b51469a5 1017
287c5d38
MR		 1018/* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1019 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1020 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1021 this restriction to the MIPS IV ISA too. */
1022#define ISA_HAS_FP_RECIP_RSQRT(MODE) \
7cfe3cc1 1023 (((ISA_HAS_FP4 \
287c5d38
MR		 1024 && ((MODE) == SFmode \
1025 || ((TARGET_FLOAT64 \
ad782bc9 1026 || mips_isa_rev >= 2) \
287c5d38 1027 && (MODE) == DFmode))) \
82f84ecb
MF		 1028 || (((MODE) == SFmode \
1029 || (MODE) == DFmode) \
1030 && (mips_isa_rev >= 6)) \
287c5d38
MR		 1031 || (TARGET_SB1 \
1032 && (MODE) == V2SFmode)) \
1033 && !TARGET_MIPS16)
1034
82f84ecb
MF		 1035#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1036
1037#define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1038
1039#define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1040
0e5a4ad8 1041/* ISA has count leading zeroes/ones instruction (not implemented). */
ad782bc9 1042#define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
0e5a4ad8 1043
5ce6f47b
EC		 1044/* ISA has three operand multiply instructions that put
1045 the high part in an accumulator: mulhi or mulhiu. */
3f07249e
RS		 1046#define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1047 || TARGET_MIPS5500 \
1048 || TARGET_SR71K) \
1049 && !TARGET_MIPS16)
5ce6f47b 1050
d2ab0929
MR		 1051/* ISA has three operand multiply instructions that negate the
1052 result and put the result in an accumulator. */
3f07249e
RS		 1053#define ISA_HAS_MULS ((TARGET_MIPS5400 \
1054 || TARGET_MIPS5500 \
1055 || TARGET_SR71K) \
1056 && !TARGET_MIPS16)
5ce6f47b 1057
d2ab0929
MR		 1058/* ISA has three operand multiply instructions that subtract the
1059 result from a 4th operand and put the result in an accumulator. */
3f07249e
RS		 1060#define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1061 || TARGET_MIPS5500 \
1062 || TARGET_SR71K) \
1063 && !TARGET_MIPS16)
1064
d2ab0929
MR		 1065/* ISA has three operand multiply instructions that add the result
1066 to a 4th operand and put the result in an accumulator. */
3f07249e
RS		 1067#define ISA_HAS_MACC ((TARGET_MIPS4120 \
1068 || TARGET_MIPS4130 \
1069 || TARGET_MIPS5400 \
1070 || TARGET_MIPS5500 \
1071 || TARGET_SR71K) \
1072 && !TARGET_MIPS16)
5ce6f47b 1073
0ac40e7a 1074/* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
3f07249e
RS		 1075#define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1076 || TARGET_MIPS4130) \
1077 && !TARGET_MIPS16)
1078
1079/* ISA has the "ror" (rotate right) instructions. */
ad782bc9 1080#define ISA_HAS_ROR ((mips_isa_rev >= 2 \
3f07249e
RS		 1081 || TARGET_MIPS5400 \
1082 || TARGET_MIPS5500 \
0aa222d1
SL		 1083 || TARGET_SR71K \
1084 || TARGET_SMARTMIPS) \
3f07249e 1085 && !TARGET_MIPS16)
5ce6f47b 1086
0f37323c
RS		 1087/* ISA has the WSBH (word swap bytes within halfwords) instruction.
1088 64-bit targets also provide DSBH and DSHD. */
ad782bc9 1089#define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
0f37323c 1090
4dbe1556 1091/* ISA has data prefetch instructions. This controls use of 'pref'. */
8f2e3902 1092#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1a0f175d 1093 || TARGET_LOONGSON_2EF \
107eea2c 1094 || TARGET_MIPS5900 \
ad782bc9 1095 || mips_isa_rev >= 1) \
8f2e3902
EC		 1096 && !TARGET_MIPS16)
1097
047b52f6
MF		 1098/* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1099#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
82f84ecb 1100
4dbe1556
CD		 1101/* ISA has data indexed prefetch instructions. This controls use of
1102 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1103 (prefx is a cop1x instruction, so can only be used if FP is
1104 enabled.) */
7cfe3cc1 1105#define ISA_HAS_PREFETCHX ISA_HAS_FP4
4dbe1556 1106
8214bf98
RS		 1107/* True if trunc.w.s and trunc.w.d are real (not synthetic)
1108 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1109 also requires TARGET_DOUBLE_FLOAT. */
1110#define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1111
2d2a50c3 1112/* ISA includes the MIPS32r2 seb and seh instructions. */
ad782bc9 1113#define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
2d2a50c3 1114
e689b870 1115/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
ad782bc9 1116#define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
e689b870 1117
85f65093 1118/* ISA has instructions for accessing top part of 64-bit fp regs. */
050af144
MF		 1119#define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1120 && mips_isa_rev >= 2)
6f428062 1121
0aa222d1 1122/* ISA has lwxs instruction (load w/scaled index address. */
22c4c869
CM		 1123#define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1124 && !TARGET_MIPS16)
0aa222d1 1125
770da00a
AP		 1126/* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1127#define ISA_HAS_LBX (TARGET_OCTEON2)
1128#define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1129#define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1130#define ISA_HAS_LHUX (TARGET_OCTEON2)
1131#define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1132#define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1133#define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1134 && TARGET_64BIT)
1135
254d1646
RS		 1136/* The DSP ASE is available. */
1137#define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1138
1139/* Revision 2 of the DSP ASE is available. */
1140#define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1141
21c9500d
RS		 1142/* True if the result of a load is not available to the next instruction.
1143 A nop will then be needed between instructions like "lw $4,..."
1144 and "addiu $4,$4,1". */
3f07249e 1145#define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
21c9500d 1146 && !TARGET_MIPS3900 \
107eea2c 1147 && !TARGET_MIPS5900 \
22c4c869
CM		 1148 && !TARGET_MIPS16 \
1149 && !TARGET_MICROMIPS)
21c9500d
RS		 1150
1151/* Likewise mtc1 and mfc1. */
58684fa0 1152#define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
107eea2c 1153 && !TARGET_MIPS5900 \
58684fa0 1154 && !TARGET_LOONGSON_2EF)
21c9500d
RS		 1155
1156/* Likewise floating-point comparisons. */
58684fa0 1157#define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
107eea2c 1158 && !TARGET_MIPS5900 \
58684fa0 1159 && !TARGET_LOONGSON_2EF)
21c9500d
RS		 1160
1161/* True if mflo and mfhi can be immediately followed by instructions
fdcf1e1e
CD		 1162 which write to the HI and LO registers.
1163
1164 According to MIPS specifications, MIPS ISAs I, II, and III need
1165 (at least) two instructions between the reads of HI/LO and
1166 instructions which write them, and later ISAs do not. Contradicting
1167 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1168 the UM for the NEC Vr5000) document needing the instructions between
1169 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1170 MIPS64 and later ISAs to have the interlocks, plus any specific
1171 earlier-ISA CPUs for which CPU documentation declares that the
1172 instructions are really interlocked. */
ad782bc9 1173#define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
58684fa0 1174 || TARGET_MIPS5500 \
107eea2c 1175 || TARGET_MIPS5900 \
58684fa0 1176 || TARGET_LOONGSON_2EF)
df770e04
DD		 1177
1178/* ISA includes synci, jr.hb and jalr.hb. */
ad782bc9 1179#define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
df770e04 1180
8d2fc1c4
DD		 1181/* ISA includes sync. */
1182#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
e9276c30
RS		 1183#define GENERATE_SYNC \
1184 (target_flags_explicit & MASK_LLSC \
1185 ? TARGET_LLSC && !TARGET_MIPS16 \
1186 : ISA_HAS_SYNC)
8d2fc1c4
DD		 1187
1188/* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1189 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1190 instructions. */
b259d352 1191#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
e9276c30
RS		 1192#define GENERATE_LL_SC \
1193 (target_flags_explicit & MASK_LLSC \
1194 ? TARGET_LLSC && !TARGET_MIPS16 \
1195 : ISA_HAS_LL_SC)
d97e6aca 1196
6399761a
TV		 1197#define ISA_HAS_SWAP (TARGET_XLP)
1198#define ISA_HAS_LDADD (TARGET_XLP)
1199
7846e5f9 1200/* ISA includes the baddu instruction. */
aa5409e7 1201#define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
7846e5f9 1202
95f6fc60 1203/* ISA includes the bbit* instructions. */
aa5409e7 1204#define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
95f6fc60 1205
49912bcd 1206/* ISA includes the cins instruction. */
aa5409e7 1207#define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
49912bcd 1208
c8424132 1209/* ISA includes the exts instruction. */
aa5409e7 1210#define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
c8424132 1211
5299815b 1212/* ISA includes the seq and sne instructions. */
aa5409e7 1213#define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
5299815b 1214
d97e6aca 1215/* ISA includes the pop instruction. */
aa5409e7 1216#define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
4d210b07
RS		 1217
1218/* The CACHE instruction is available in non-MIPS16 code. */
1219#define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1220
1221/* The CACHE instruction is available. */
1222#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
e75b25e7 1223\f
59c94430
MM		 1224/* Tell collect what flags to pass to nm. */
1225#ifndef NM_FLAGS
2ce3c6c6 1226#define NM_FLAGS "-Bn"
59c94430
MM		 1227#endif
1228
e75b25e7 1229\f
4e88bbcd 1230/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
5811cb27
RS		 1231 the assembler. It may be overridden by subtargets.
1232
1233 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1234 COFF debugging info. */
1235
4e88bbcd
ILT		 1236#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1237#define SUBTARGET_ASM_DEBUGGING_SPEC "\
bb98bc58
JW		 1238%{g} %{g0} %{g1} %{g2} %{g3} \
1239%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1240%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1241%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
6d439235 1242%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
5811cb27 1243%{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
4e88bbcd 1244#endif
bb98bc58 1245
aa0c464a
MF		 1246/* FP_ASM_SPEC represents the floating-point options that must be passed
1247 to the assembler when FPXX support exists. Prior to that point the
1248 assembler could accept the options but were not required for
1249 correctness. We only add the options when absolutely necessary
1250 because passing -msoft-float to the assembler will cause it to reject
1251 all hard-float instructions which may require some user code to be
1252 updated. */
1253
1254#ifdef HAVE_AS_DOT_MODULE
1255#define FP_ASM_SPEC "\
1256%{mhard-float} %{msoft-float} \
1257%{msingle-float} %{mdouble-float}"
1258#else
1259#define FP_ASM_SPEC
1260#endif
1261
4e88bbcd
ILT		 1262/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1263 overridden by subtargets. */
1264
1265#ifndef SUBTARGET_ASM_SPEC
1266#define SUBTARGET_ASM_SPEC ""
bb98bc58 1267#endif
4e88bbcd 1268
b2bcb32d 1269#undef ASM_SPEC
4e88bbcd 1270#define ASM_SPEC "\
2d2a50c3 1271%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
f2d6ca50 1272%{mips32*} %{mips64*} \
500fc425 1273%{mips16} %{mno-mips16:-no-mips16} \
22c4c869 1274%{mmicromips} %{mno-micromips} \
500fc425
TS		 1275%{mips3d} %{mno-mips3d:-no-mips3d} \
1276%{mdmx} %{mno-mdmx:-no-mdmx} \
1277%{mdsp} %{mno-dsp} \
1278%{mdspr2} %{mno-dspr2} \
5cb5a23f 1279%{mmcu} %{mno-mcu} \
44b20bb8 1280%{meva} %{mno-eva} \
0a39d07b 1281%{mvirt} %{mno-virt} \
35773f53 1282%{mxpa} %{mno-xpa} \
0aa222d1 1283%{msmartmips} %{mno-smartmips} \
500fc425 1284%{mmt} %{mno-mt} \
faaa3afb 1285%{mfix-rm7000} %{mno-fix-rm7000} \
0ac40e7a 1286%{mfix-vr4120} %{mfix-vr4130} \
0eda4033 1287%{mfix-24k} \
29cedf8e 1288%{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
4e88bbcd 1289%(subtarget_asm_debugging_spec) \
e21d5757 1290%{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
ee692410 1291%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
050af144
MF		 1292%{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1293%{modd-spreg} %{mno-odd-spreg} \
d9870b7e 1294%{mshared} %{mno-shared} \
acda0e26 1295%{msym32} %{mno-sym32} \
aa0c464a
MF		 1296%{mtune=*}" \
1297FP_ASM_SPEC "\
4e88bbcd 1298%(subtarget_asm_spec)"
e75b25e7 1299
31c714e3 1300/* Extra switches sometimes passed to the linker. */
e75b25e7
MM		 1301
1302#ifndef LINK_SPEC
31c714e3 1303#define LINK_SPEC "\
120dc6cd 1304%(endian_spec) \
f2d6ca50 1305%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
368e0b39 1306%{shared}"
0e5a4ad8
EC		 1307#endif /* LINK_SPEC defined */
1308
e75b25e7
MM		 1309
1310/* Specs for the compiler proper */
1311
c9db96ce
JR		 1312/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1313 overridden by subtargets. */
1314#ifndef SUBTARGET_CC1_SPEC
1315#define SUBTARGET_CC1_SPEC ""
1316#endif
1317
1318/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1319
120311ec 1320#undef CC1_SPEC
31c714e3 1321#define CC1_SPEC "\
96abdcb1 1322%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
4e314d1f 1323%(subtarget_cc1_spec)"
e75b25e7 1324
4e88bbcd
ILT		 1325/* Preprocessor specs. */
1326
4e88bbcd
ILT		 1327/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1328 overridden by subtargets. */
1329#ifndef SUBTARGET_CPP_SPEC
1330#define SUBTARGET_CPP_SPEC ""
1331#endif
1332
ce3649d2 1333#define CPP_SPEC "%(subtarget_cpp_spec)"
4e88bbcd
ILT		 1334
1335/* This macro defines names of additional specifications to put in the specs
1336 that can be used in various specifications like CC1_SPEC. Its definition
1337 is an initializer with a subgrouping for each command option.
1338
1339 Each subgrouping contains a string constant, that defines the
7ec022b2 1340 specification name, and a string constant that used by the GCC driver
4e88bbcd
ILT		 1341 program.
1342
1343 Do not define this macro if it does not need to do anything. */
1344
1345#define EXTRA_SPECS \
829245be
KG		 1346 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1347 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
829245be
KG		 1348 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1349 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
5811cb27 1350 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
120dc6cd 1351 { "endian_spec", ENDIAN_SPEC }, \
4e88bbcd
ILT		 1352 SUBTARGET_EXTRA_SPECS
1353
1354#ifndef SUBTARGET_EXTRA_SPECS
1355#define SUBTARGET_EXTRA_SPECS
e75b25e7 1356#endif
e75b25e7 1357\f
23532de9 1358#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
deae8de6
EC		 1359#define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1360
1361#ifndef PREFERRED_DEBUGGING_TYPE
1362#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1363#endif
e75b25e7 1364
2e8a796f
RS		 1365/* The size of DWARF addresses should be the same as the size of symbols
1366 in the target file format. They shouldn't depend on things like -msym32,
1367 because many DWARF consumers do not allow the mixture of address sizes
1368 that one would then get from linking -msym32 code with -msym64 code.
1369
1370 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1371 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1372#define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
d2beeae7 1373
59c94430
MM		 1374/* By default, turn on GDB extensions. */
1375#define DEFAULT_GDB_EXTENSIONS 1
1376
fb01ed38
MF		 1377/* Registers may have a prefix which can be ignored when matching
1378 user asm and register definitions. */
1379#ifndef REGISTER_PREFIX
1380#define REGISTER_PREFIX "$"
1381#endif
1382
6ae1498b
JW		 1383/* Local compiler-generated symbols must have a prefix that the assembler
1384 understands. By default, this is $, although some targets (e.g.,
987ba558 1385 NetBSD-ELF) need to override this. */
6ae1498b
JW		 1386
1387#ifndef LOCAL_LABEL_PREFIX
1388#define LOCAL_LABEL_PREFIX "$"
1389#endif
1390
1391/* By default on the mips, external symbols do not have an underscore
987ba558 1392 prepended, but some targets (e.g., NetBSD) require this. */
6ae1498b
JW		 1393
1394#ifndef USER_LABEL_PREFIX
1395#define USER_LABEL_PREFIX ""
1396#endif
1397
e75b25e7
MM		 1398/* On Sun 4, this limit is 2048. We use 1500 to be safe,
1399 since the length can run past this up to a continuation point. */
44404b8b 1400#undef DBX_CONTIN_LENGTH
e75b25e7
MM		 1401#define DBX_CONTIN_LENGTH 1500
1402
987ba558 1403/* How to renumber registers for dbx and gdb. */
48156a39 1404#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
e75b25e7 1405
dfad12b5 1406/* The mapping from gcc register number to DWARF 2 CFA column number. */
48156a39 1407#define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
c8cc5c4a
JM		 1408
1409/* The DWARF 2 CFA column which tracks the return address. */
293593b1 1410#define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1f3d0661 1411
469ac993 1412/* Before the prologue, RA lives in r31. */
293593b1 1413#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
469ac993 1414
9e800206 1415/* Describe how we implement __builtin_eh_return. */
f1d5187e
RS		 1416#define EH_RETURN_DATA_REGNO(N) \
1417 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1418
9e800206
RH		 1419#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1420
0c433c31
RS		 1421#define EH_USES(N) mips_eh_uses (N)
1422
7dac2f89 1423/* Offsets recorded in opcodes are a multiple of this alignment factor.
b3276c7a
GK		 1424 The default for this in 64-bit mode is 8, which causes problems with
1425 SFmode register saves. */
85bfab36 1426#define DWARF_CIE_DATA_ALIGNMENT -4
b3276c7a 1427
ab78d4a8
MM		 1428/* Correct the offset of automatic variables and arguments. Note that
1429 the MIPS debug format wants all automatic variables and arguments
1430 to be in terms of the virtual frame pointer (stack pointer before
1431 any adjustment in the function), while the MIPS 3.0 linker wants
1432 the frame pointer to be the stack pointer after the initial
1433 adjustment. */
e75b25e7 1434
8f2e3902 1435#define DEBUGGER_AUTO_OFFSET(X) \
f5963e61 1436 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
8f2e3902 1437#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
f5963e61 1438 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
e75b25e7
MM		 1439\f
1440/* Target machine storage layout */
1441
4851a75c 1442#define BITS_BIG_ENDIAN 0
96abdcb1 1443#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
96abdcb1 1444#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7 1445
876c09d3 1446#define MAX_BITS_PER_WORD 64
e75b25e7
MM		 1447
1448/* Width of a word, in units (bytes). */
456f6501 1449#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
3b831805 1450#ifndef IN_LIBGCC2
ef0e53ce 1451#define MIN_UNITS_PER_WORD 4
3b831805 1452#endif
876c09d3
JW		 1453
1454/* For MIPS, width of a floating point register. */
456f6501 1455#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
e75b25e7 1456
e8ab09c1
SL		 1457/* The number of consecutive floating-point registers needed to store the
1458 largest format supported by the FPU. */
1459#define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1460
1461/* The number of consecutive floating-point registers needed to store the
1462 smallest format supported by the FPU. */
1463#define MIN_FPRS_PER_FMT \
050af144 1464 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
3f26edaa 1465
8a381273
AO		 1466/* The largest size of value that can be held in floating-point
1467 registers and moved with a single instruction. */
e8ab09c1 1468#define UNITS_PER_HWFPVALUE \
a38e0142 1469 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
8a381273
AO		 1470
1471/* The largest size of value that can be held in floating-point
1472 registers. */
0e808055 1473#define UNITS_PER_FPVALUE \
a38e0142 1474 (TARGET_SOFT_FLOAT_ABI ? 0 \
0e808055
RS		 1475 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1476 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
4d72536e
RS		 1477
1478/* The number of bytes in a double. */
1479#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
3f26edaa 1480
dfad12b5 1481/* Set the sizes of the core types. */
e75b25e7 1482#define SHORT_TYPE_SIZE 16
fb8136b2 1483#define INT_TYPE_SIZE 32
456f6501 1484#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
923d630e 1485#define LONG_LONG_TYPE_SIZE 64
e75b25e7 1486
dfad12b5 1487#define FLOAT_TYPE_SIZE 32
e75b25e7 1488#define DOUBLE_TYPE_SIZE 64
7f9be256 1489#define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
8a381273 1490
9fc777ad
CF		 1491/* Define the sizes of fixed-point types. */
1492#define SHORT_FRACT_TYPE_SIZE 8
1493#define FRACT_TYPE_SIZE 16
1494#define LONG_FRACT_TYPE_SIZE 32
1495#define LONG_LONG_FRACT_TYPE_SIZE 64
1496
1497#define SHORT_ACCUM_TYPE_SIZE 16
1498#define ACCUM_TYPE_SIZE 32
1499#define LONG_ACCUM_TYPE_SIZE 64
1500/* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1501 doesn't support 128-bit integers for MIPS32 currently. */
1502#define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1503
8a381273
AO		 1504/* long double is not a fixed mode, but the idea is that, if we
1505 support long double, we also want a 128-bit integer type. */
1506#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1507
cafe096b 1508/* Width in bits of a pointer. */
1eeed24e 1509#ifndef POINTER_SIZE
cafe096b 1510#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1eeed24e 1511#endif
e75b25e7 1512
e75b25e7 1513/* Allocation boundary (in *bits*) for storing arguments in argument list. */
e64ca6c4 1514#define PARM_BOUNDARY BITS_PER_WORD
cafe096b 1515
e75b25e7
MM		 1516/* Allocation boundary (in *bits*) for the code of a function. */
1517#define FUNCTION_BOUNDARY 32
1518
1519/* Alignment of field after `int : 0' in a structure. */
9e95597a 1520#define EMPTY_FIELD_BOUNDARY 32
e75b25e7
MM		 1521
1522/* Every structure's size must be a multiple of this. */
1523/* 8 is observed right on a DECstation and on riscos 4.02. */
1524#define STRUCTURE_SIZE_BOUNDARY 8
1525
1526/* There is no point aligning anything to a rounder boundary than this. */
8a381273 1527#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
e75b25e7 1528
dfad12b5 1529/* All accesses must be aligned. */
31c714e3 1530#define STRICT_ALIGNMENT 1
e75b25e7
MM		 1531
1532/* Define this if you wish to imitate the way many other C compilers
1533 handle alignment of bitfields and the structures that contain
1534 them.
1535
43a88a8c 1536 The behavior is that the type written for a bit-field (`int',
e75b25e7
MM		 1537 `short', or other integer type) imposes an alignment for the
1538 entire structure, as if the structure really did contain an
43a88a8c 1539 ordinary field of that type. In addition, the bit-field is placed
e75b25e7
MM		 1540 within the structure so that it would fit within such a field,
1541 not crossing a boundary for it.
1542
43a88a8c 1543 Thus, on most machines, a bit-field whose type is written as `int'
e75b25e7
MM		 1544 would not cross a four-byte boundary, and would force four-byte
1545 alignment for the whole structure. (The alignment used may not
1546 be four bytes; it is controlled by the other alignment
1547 parameters.)
1548
1549 If the macro is defined, its definition should be a C expression;
1550 a nonzero value for the expression enables this behavior. */
1551
1552#define PCC_BITFIELD_TYPE_MATTERS 1
1553
1554/* If defined, a C expression to compute the alignment given to a
1555 constant that is being placed in memory. CONSTANT is the constant
1556 and ALIGN is the alignment that the object would ordinarily have.
1557 The value of this macro is used instead of that alignment to align
1558 the object.
1559
1560 If this macro is not defined, then ALIGN is used.
1561
1562 The typical use of this macro is to increase alignment for string
1563 constants to be word aligned so that `strcpy' calls that copy
1564 constants can be done inline. */
1565
1566#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1567 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
75131237 1568 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
e75b25e7
MM		 1569
1570/* If defined, a C expression to compute the alignment for a static
1571 variable. TYPE is the data type, and ALIGN is the alignment that
1572 the object would ordinarily have. The value of this macro is used
1573 instead of that alignment to align the object.
1574
1575 If this macro is not defined, then ALIGN is used.
1576
1577 One use of this macro is to increase alignment of medium-size
1578 data to make it all fit in fewer cache lines. Another is to
1579 cause character arrays to be word-aligned so that `strcpy' calls
1580 that copy constants to character arrays can be done inline. */
1581
1582#undef DATA_ALIGNMENT
1583#define DATA_ALIGNMENT(TYPE, ALIGN) \
1584 ((((ALIGN) < BITS_PER_WORD) \
1585 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1586 || TREE_CODE (TYPE) == UNION_TYPE \
1587 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1588
adb417d7
NS		 1589/* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1590 character arrays to be word-aligned so that `strcpy' calls that copy
1591 constants to character arrays can be done inline, and 'strcmp' can be
1592 optimised to use word loads. */
1593#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1594 DATA_ALIGNMENT (TYPE, ALIGN)
1595
648bb159
RS		 1596#define PAD_VARARGS_DOWN \
1597 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
f5c8ac96 1598
9a63901f
RK		 1599/* Define if operations between registers always perform the operation
1600 on the full register even if a narrower mode is specified. */
1601#define WORD_REGISTER_OPERATIONS
1602
85f65093 1603/* When in 64-bit mode, move insns will sign extend SImode and CCmode
dab66575 1604 moves. All other references are zero extended. */
a872728c
JL		 1605#define LOAD_EXTEND_OP(MODE) \
1606 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1607 ? SIGN_EXTEND : ZERO_EXTEND)
2bcb2ab3
GK		 1608
1609/* Define this macro if it is advisable to hold scalars in registers
7dac2f89 1610 in a wider mode than that declared by the program. In such cases,
2bcb2ab3
GK		 1611 the value is constrained to be within the bounds of the declared
1612 type, but kept valid in the wider mode. The signedness of the
cafe096b 1613 extension may differ from that of the type. */
2bcb2ab3
GK		 1614
1615#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1616 if (GET_MODE_CLASS (MODE) == MODE_INT \
cafe096b
EC		 1617 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1618 { \
1619 if ((MODE) == SImode) \
1620 (UNSIGNEDP) = 0; \
1621 (MODE) = Pmode; \
1622 }
1623
0dc31782
RS		 1624/* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1625 Extensions of pointers to word_mode must be signed. */
1626#define POINTERS_EXTEND_UNSIGNED false
1627
cafe096b
EC		 1628/* Define if loading short immediate values into registers sign extends. */
1629#define SHORT_IMMEDIATES_SIGN_EXTEND
09d8cc0e
ILT		 1630
1631/* The [d]clz instructions have the natural values at 0. */
1632
1633#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
14670a74 1634 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
e75b25e7
MM		 1635\f
1636/* Standard register usage. */
1637
dfad12b5 1638/* Number of hardware registers. We have:
e75b25e7 1639
dfad12b5
RS		 1640 - 32 integer registers
1641 - 32 floating point registers
1642 - 8 condition code registers
1643 - 2 accumulator registers (hi and lo)
1644 - 32 registers each for coprocessors 0, 2 and 3
0c433c31 1645 - 4 fake registers:
bcbc6b7f
RS		 1646 - ARG_POINTER_REGNUM
1647 - FRAME_POINTER_REGNUM
dbc90b65 1648 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
0c433c31
RS		 1649 - CPRESTORE_SLOT_REGNUM
1650 - 2 dummy entries that were used at various times in the past.
118ea793
CF		 1651 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1652 - 6 DSP control registers */
e75b25e7 1653
118ea793 1654#define FIRST_PSEUDO_REGISTER 188
e75b25e7 1655
dfad12b5
RS		 1656/* By default, fix the kernel registers ($26 and $27), the global
1657 pointer ($28) and the stack pointer ($29). This can change
1658 depending on the command-line options.
e75b25e7 1659
dfad12b5 1660 Regarding coprocessor registers: without evidence to the contrary,
d604bca3 1661 it's best to assume that each coprocessor register has a unique
525c561d 1662 use. This can be overridden, in, e.g., mips_option_override or
5efd84c5
NF		 1663 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1664 inappropriate for a particular target. */
d604bca3 1665
e75b25e7
MM		 1666#define FIXED_REGISTERS \
1667{ \
1668 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
cafe096b 1669 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
e75b25e7
MM		 1670 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1671 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
d334c3c1 1672 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
d604bca3
MH		 1673 /* COP0 registers */ \
1674 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1675 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1676 /* COP2 registers */ \
1677 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1678 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1679 /* COP3 registers */ \
1680 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
118ea793
CF		 1681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1682 /* 6 DSP accumulator registers & 6 control registers */ \
1683 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
e75b25e7
MM		 1684}
1685
1686
dfad12b5
RS		 1687/* Set up this array for o32 by default.
1688
1689 Note that we don't mark $31 as a call-clobbered register. The idea is
1690 that it's really the call instructions themselves which clobber $31.
cafe096b
EC		 1691 We don't care what the called function does with it afterwards.
1692
1693 This approach makes it easier to implement sibcalls. Unlike normal
1694 calls, sibcalls don't clobber $31, so the register reaches the
1695 called function in tact. EPILOGUE_USES says that $31 is useful
1696 to the called function. */
e75b25e7
MM		 1697
1698#define CALL_USED_REGISTERS \
1699{ \
1700 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
cafe096b 1701 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
e75b25e7
MM		 1702 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1703 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
cafe096b 1704 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
d604bca3
MH		 1705 /* COP0 registers */ \
1706 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1707 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1708 /* COP2 registers */ \
1709 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1710 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1711 /* COP3 registers */ \
1712 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
118ea793
CF		 1713 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1714 /* 6 DSP accumulator registers & 6 control registers */ \
1715 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
e75b25e7
MM		 1716}
1717
2ca2d9ee 1718
dfad12b5 1719/* Define this since $28, though fixed, is call-saved in many ABIs. */
2ca2d9ee
EC		 1720
1721#define CALL_REALLY_USED_REGISTERS \
1722{ /* General registers. */ \
1723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
cafe096b 1724 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
2ca2d9ee
EC		 1725 /* Floating-point registers. */ \
1726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1727 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1728 /* Others. */ \
dbc90b65 1729 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
d604bca3
MH		 1730 /* COP0 registers */ \
1731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1732 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1733 /* COP2 registers */ \
1734 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1735 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1736 /* COP3 registers */ \
1737 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
118ea793
CF		 1738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1739 /* 6 DSP accumulator registers & 6 control registers */ \
1740 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
2ca2d9ee 1741}
e75b25e7
MM		 1742
1743/* Internal macros to classify a register number as to whether it's a
1744 general purpose register, a floating point register, a
516a2dfd 1745 multiply/divide register, or a status register. */
e75b25e7
MM		 1746
1747#define GP_REG_FIRST 0
1748#define GP_REG_LAST 31
1749#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1750#define GP_DBX_FIRST 0
e19da24c
CF		 1751#define K0_REG_NUM (GP_REG_FIRST + 26)
1752#define K1_REG_NUM (GP_REG_FIRST + 27)
1753#define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
e75b25e7
MM		 1754
1755#define FP_REG_FIRST 32
1756#define FP_REG_LAST 63
1757#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1758#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1759
1760#define MD_REG_FIRST 64
d334c3c1 1761#define MD_REG_LAST 65
e75b25e7 1762#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
77d4f3a4 1763#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
e75b25e7 1764
aa3e18a0
DD		 1765/* The DWARF 2 CFA column which tracks the return address from a
1766 signal handler context. This means that to maintain backwards
1767 compatibility, no hard register can be assigned this column if it
1768 would need to be handled by the DWARF unwinder. */
1769#define DWARF_ALT_FRAME_RETURN_COLUMN 66
1770
225b8835 1771#define ST_REG_FIRST 67
b8eb88d0 1772#define ST_REG_LAST 74
e75b25e7
MM		 1773#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1774
39dffea3 1775
cafe096b 1776/* FIXME: renumber. */
d604bca3
MH		 1777#define COP0_REG_FIRST 80
1778#define COP0_REG_LAST 111
1779#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1780
e19da24c
CF		 1781#define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1782#define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1783#define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1784
d604bca3
MH		 1785#define COP2_REG_FIRST 112
1786#define COP2_REG_LAST 143
1787#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1788
1789#define COP3_REG_FIRST 144
1790#define COP3_REG_LAST 175
1791#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
2cd45f0e
SE		 1792
1793/* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1794#define ALL_COP_REG_FIRST COP0_REG_FIRST
1795#define ALL_COP_REG_LAST COP3_REG_LAST
1796#define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
d604bca3 1797
118ea793
CF		 1798#define DSP_ACC_REG_FIRST 176
1799#define DSP_ACC_REG_LAST 181
1800#define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1801
e75b25e7 1802#define AT_REGNUM (GP_REG_FIRST + 1)
48156a39
NS		 1803#define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1804#define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
b8eb88d0 1805
e19da24c
CF		 1806/* A few bitfield locations for the coprocessor registers. */
1807/* Request Interrupt Priority Level is from bit 10 to bit 15 of
1808 the cause register for the EIC interrupt mode. */
1809#define CAUSE_IPL 10
1810/* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1811#define SR_IPL 10
1812/* Exception Level is at bit 1 of the status register. */
1813#define SR_EXL 1
1814/* Interrupt Enable is at bit 0 of the status register. */
1815#define SR_IE 0
1816
dfad12b5
RS		 1817/* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1818 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
b8eb88d0 1819 should be used instead. */
e75b25e7
MM		 1820#define FPSW_REGNUM ST_REG_FIRST
1821
75131237
RK		 1822#define GP_REG_P(REGNO) \
1823 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
2bcb2ab3
GK		 1824#define M16_REG_P(REGNO) \
1825 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
22c4c869
CM		 1826#define M16STORE_REG_P(REGNO) \
1827 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
75131237
RK		 1828#define FP_REG_P(REGNO) \
1829 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1830#define MD_REG_P(REGNO) \
1831 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1832#define ST_REG_P(REGNO) \
1833 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
d604bca3
MH		 1834#define COP0_REG_P(REGNO) \
1835 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1836#define COP2_REG_P(REGNO) \
1837 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1838#define COP3_REG_P(REGNO) \
1839 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1840#define ALL_COP_REG_P(REGNO) \
1841 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
118ea793
CF		 1842/* Test if REGNO is one of the 6 new DSP accumulators. */
1843#define DSP_ACC_REG_P(REGNO) \
1844 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1845/* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1846#define ACC_REG_P(REGNO) \
1847 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
d604bca3 1848
66083422 1849#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
5b0f0db6 1850
96a30b18
RS		 1851/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1852 to initialize the mips16 gp pseudo register. */
1853#define CONST_GP_P(X) \
1854 (GET_CODE (X) == CONST \
1855 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1856 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1857
d604bca3
MH		 1858/* Return coprocessor number from register number. */
1859
1860#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1861 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1862 : COP3_REG_P (REGNO) ? '3' : '?')
e75b25e7 1863
e75b25e7 1864
0e5a4ad8 1865#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
e75b25e7 1866
e75b25e7
MM		 1867#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1868 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1869
050af144
MF		 1870/* Select a register mode required for caller save of hard regno REGNO. */
1871#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1872 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1873
1874/* Odd-numbered single-precision registers are not considered callee-saved
1875 for o32 FPXX as they will be clobbered when run on an FR=1 FPU. */
1876#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1877 (TARGET_FLOATXX && hard_regno_nregs[REGNO][MODE] == 1 \
1878 && FP_REG_P (REGNO) && ((REGNO) & 1))
1879
e5a2b69d 1880#define MODES_TIEABLE_P mips_modes_tieable_p
e75b25e7 1881
e75b25e7 1882/* Register to use for pushing function arguments. */
0fb5ac6f 1883#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
e75b25e7 1884
bcbc6b7f
RS		 1885/* These two registers don't really exist: they get eliminated to either
1886 the stack or hard frame pointer. */
1887#define ARG_POINTER_REGNUM 77
1888#define FRAME_POINTER_REGNUM 78
2bcb2ab3
GK		 1889
1890/* $30 is not available on the mips16, so we use $17 as the frame
1891 pointer. */
1892#define HARD_FRAME_POINTER_REGNUM \
1893 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
e75b25e7 1894
e3339d0f
JM		 1895#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1896#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1897
e75b25e7 1898/* Register in which static-chain is passed to a function. */
e538e028 1899#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
e75b25e7 1900
08d0963a 1901/* Registers used as temporaries in prologue/epilogue code:
be763023 1902
08d0963a
RS		 1903 - If a MIPS16 PIC function needs access to _gp, it first loads
1904 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1905
1906 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1907 register. The register must not conflict with MIPS16_PIC_TEMP.
1908
3b601ca3
EB		 1909 - If we aren't generating MIPS16 code, the prologue can also use
1910 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1911
08d0963a
RS		 1912 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1913 register.
1914
1915 If we're generating MIPS16 code, these registers must come from the
1916 core set of 8. The prologue registers mustn't conflict with any
1917 incoming arguments, the static chain pointer, or the frame pointer.
1918 The epilogue temporary mustn't conflict with the return registers,
1919 the PIC call register ($25), the frame pointer, the EH stack adjustment,
e19da24c
CF		 1920 or the EH data registers.
1921
1922 If we're generating interrupt handlers, we use K0 as a temporary register
1923 in prologue/epilogue code. */
08d0963a
RS		 1924
1925#define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
e19da24c
CF		 1926#define MIPS_PROLOGUE_TEMP_REGNUM \
1927 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
3b601ca3
EB		 1928#define MIPS_PROLOGUE_TEMP2_REGNUM \
1929 (TARGET_MIPS16 \
1930 ? (gcc_unreachable (), INVALID_REGNUM) \
1931 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
e19da24c
CF		 1932#define MIPS_EPILOGUE_TEMP_REGNUM \
1933 (cfun->machine->interrupt_handler_p \
1934 ? K0_REG_NUM \
1935 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
be763023 1936
08d0963a 1937#define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
be763023 1938#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
3b601ca3
EB		 1939#define MIPS_PROLOGUE_TEMP2(MODE) \
1940 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
be763023 1941#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
e75b25e7
MM		 1942
1943/* Define this macro if it is as good or better to call a constant
1944 function address than to call an address kept in a register. */
1945#define NO_FUNCTION_CSE 1
1946
f833ffd4
RS		 1947/* The ABI-defined global pointer. Sometimes we use a different
1948 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1949#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1950
1951/* We normally use $28 as the global pointer. However, when generating
1952 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1953 register instead. They can then avoid saving and restoring $28
1954 and perhaps avoid using a frame at all.
1955
1956 When a leaf function uses something other than $28, mips_expand_prologue
1957 will modify pic_offset_table_rtx in place. Take the register number
1958 from there after reload. */
1959#define PIC_OFFSET_TABLE_REGNUM \
1960 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
e75b25e7
MM		 1961\f
1962/* Define the classes of registers for register constraints in the
1963 machine description. Also define ranges of constants.
1964
1965 One of the classes must always be named ALL_REGS and include all hard regs.
1966 If there is more than one class, another class must be named NO_REGS
1967 and contain no registers.
1968
1969 The name GENERAL_REGS must be the name of a class (or an alias for
1970 another name such as ALL_REGS). This is the class of registers
1971 that is allowed by "g" or "r" in a register constraint.
1972 Also, registers outside this class are allocated only when
1973 instructions express preferences for them.
1974
1975 The classes must be numbered in nondecreasing order; that is,
1976 a larger-numbered class must never be contained completely
1977 in a smaller-numbered class.
1978
1979 For any two classes, it is very desirable that there be another
1980 class that represents their union. */
1981
1982enum reg_class
1983{
1984 NO_REGS, /* no registers in set */
5e7d8b4c 1985 M16_STORE_REGS, /* microMIPS store registers */
2bcb2ab3 1986 M16_REGS, /* mips16 directly accessible registers */
a78cc314 1987 M16_SP_REGS, /* mips16 + $sp */
2bcb2ab3
GK		 1988 T_REG, /* mips16 T register ($24) */
1989 M16_T_REGS, /* mips16 registers plus T register */
cafe096b 1990 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2feaae20 1991 V1_REG, /* Register $v1 ($3) used for TLS access. */
a78cc314 1992 SPILL_REGS, /* All but $sp and call preserved regs are in here */
cafe096b 1993 LEA_REGS, /* Every GPR except $25 */
e75b25e7
MM		 1994 GR_REGS, /* integer registers */
1995 FP_REGS, /* floating point registers */
48156a39
NS		 1996 MD0_REG, /* first multiply/divide register */
1997 MD1_REG, /* second multiply/divide register */
e75b25e7 1998 MD_REGS, /* multiply/divide registers (hi/lo) */
d604bca3
MH		 1999 COP0_REGS, /* generic coprocessor classes */
2000 COP2_REGS,
2001 COP3_REGS,
e75b25e7 2002 ST_REGS, /* status registers (fp status) */
118ea793
CF		 2003 DSP_ACC_REGS, /* DSP accumulator registers */
2004 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
7314c7dd 2005 FRAME_REGS, /* $arg and $frame */
5c0a2e3a
RS		 2006 GR_AND_MD0_REGS, /* union classes */
2007 GR_AND_MD1_REGS,
2008 GR_AND_MD_REGS,
2009 GR_AND_ACC_REGS,
e75b25e7
MM		 2010 ALL_REGS, /* all registers */
2011 LIM_REG_CLASSES /* max value + 1 */
2012};
2013
2014#define N_REG_CLASSES (int) LIM_REG_CLASSES
2015
2016#define GENERAL_REGS GR_REGS
2017
2018/* An initializer containing the names of the register classes as C
2019 string constants. These names are used in writing some of the
2020 debugging dumps. */
2021
2022#define REG_CLASS_NAMES \
2023{ \
2024 "NO_REGS", \
5e7d8b4c 2025 "M16_STORE_REGS", \
2bcb2ab3 2026 "M16_REGS", \
a78cc314 2027 "M16_SP_REGS", \
2bcb2ab3
GK		 2028 "T_REG", \
2029 "M16_T_REGS", \
cafe096b 2030 "PIC_FN_ADDR_REG", \
2feaae20 2031 "V1_REG", \
a78cc314 2032 "SPILL_REGS", \
cafe096b 2033 "LEA_REGS", \
e75b25e7
MM		 2034 "GR_REGS", \
2035 "FP_REGS", \
48156a39
NS		 2036 "MD0_REG", \
2037 "MD1_REG", \
e75b25e7 2038 "MD_REGS", \
d604bca3
MH		 2039 /* coprocessor registers */ \
2040 "COP0_REGS", \
2041 "COP2_REGS", \
2042 "COP3_REGS", \
e75b25e7 2043 "ST_REGS", \
118ea793
CF		 2044 "DSP_ACC_REGS", \
2045 "ACC_REGS", \
7314c7dd 2046 "FRAME_REGS", \
5c0a2e3a
RS		 2047 "GR_AND_MD0_REGS", \
2048 "GR_AND_MD1_REGS", \
2049 "GR_AND_MD_REGS", \
2050 "GR_AND_ACC_REGS", \
e75b25e7
MM		 2051 "ALL_REGS" \
2052}
2053
2054/* An initializer containing the contents of the register classes,
2055 as integers which are bit masks. The Nth integer specifies the
2056 contents of class N. The way the integer MASK is interpreted is
2057 that register R is in the class if `MASK & (1 << R)' is 1.
2058
2059 When the machine has more than 32 registers, an integer does not
2060 suffice. Then the integers are replaced by sub-initializers,
2061 braced groupings containing several integers. Each
2062 sub-initializer must be suitable as an initializer for the type
2063 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2064
ec24a740
EC		 2065#define REG_CLASS_CONTENTS \
2066{ \
5c0a2e3a 2067 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
5e7d8b4c 2068 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
5c0a2e3a 2069 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
a78cc314 2070 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
5c0a2e3a
RS		 2071 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2072 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2073 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2074 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
a78cc314 2075 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
5c0a2e3a
RS		 2076 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2077 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2078 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2079 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2080 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2081 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2082 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2083 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2084 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2085 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2086 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2087 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2088 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2089 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2090 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2091 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2092 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2093 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
e75b25e7
MM		 2094}
2095
2096
2097/* A C expression whose value is a register class containing hard
2098 register REGNO. In general there is more that one such class;
2099 choose a class which is "minimal", meaning that no smaller class
2100 also contains the register. */
2101
e75b25e7
MM		 2102#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2103
2104/* A macro whose definition is the name of the class to which a
2105 valid base register must belong. A base register is one used in
2106 an address which is the register value plus a displacement. */
2107
a78cc314 2108#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
e75b25e7
MM		 2109
2110/* A macro whose definition is the name of the class to which a
2111 valid index register must belong. An index register is one used
2112 in an address where its value is either multiplied by a scale
2113 factor or added to another register (as well as added to a
2114 displacement). */
2115
876c09d3 2116#define INDEX_REG_CLASS NO_REGS
e75b25e7 2117
59dbe1d9
RS		 2118/* We generally want to put call-clobbered registers ahead of
2119 call-saved ones. (IRA expects this.) */
2bcb2ab3
GK		 2120
2121#define REG_ALLOC_ORDER \
e08be11c
RS		 2122{ /* Accumulator registers. When GPRs and accumulators have equal \
2123 cost, we generally prefer to use accumulators. For example, \
2124 a division of multiplication result is better allocated to LO, \
2125 so that we put the MFLO at the point of use instead of at the \
2126 point of definition. It's also needed if we're to take advantage \
2127 of the extra accumulators available with -mdspr2. In some cases, \
2128 it can also help to reduce register pressure. */ \
2129 64, 65,176,177,178,179,180,181, \
2130 /* Call-clobbered GPRs. */ \
2131 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
59dbe1d9
RS		 2132 24, 25, 31, \
2133 /* The global pointer. This is call-clobbered for o32 and o64 \
2134 abicalls, call-saved for n32 and n64 abicalls, and a program \
2135 invariant otherwise. Putting it between the call-clobbered \
2136 and call-saved registers should cope with all eventualities. */ \
2137 28, \
2138 /* Call-saved GPRs. */ \
2139 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2140 /* GPRs that can never be exposed to the register allocator. */ \
e08be11c 2141 0, 26, 27, 29, \
59dbe1d9 2142 /* Call-clobbered FPRs. */ \
2bcb2ab3 2143 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
59dbe1d9
RS		 2144 48, 49, 50, 51, \
2145 /* FPRs that are usually call-saved. The odd ones are actually \
2146 call-clobbered for n32, but listing them ahead of the even \
2147 registers might encourage the register allocator to fragment \
2148 the available FPR pairs. We need paired FPRs to store long \
2149 doubles, so it isn't clear that using a different order \
2150 for n32 would be a win. */ \
2151 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2152 /* None of the remaining classes have defined call-saved \
2153 registers. */ \
e08be11c 2154 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
d604bca3
MH		 2155 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2156 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2157 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2158 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2159 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
118ea793 2160 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
e08be11c 2161 182,183,184,185,186,187 \
2bcb2ab3
GK		 2162}
2163
569b7f6a 2164/* True if VALUE is an unsigned 6-bit number. */
118ea793
CF		 2165
2166#define UIMM6_OPERAND(VALUE) \
2167 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2168
2169/* True if VALUE is a signed 10-bit number. */
2170
2171#define IMM10_OPERAND(VALUE) \
2172 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2173
cafe096b
EC		 2174/* True if VALUE is a signed 16-bit number. */
2175
2176#define SMALL_OPERAND(VALUE) \
2177 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2178
2179/* True if VALUE is an unsigned 16-bit number. */
2180
2181#define SMALL_OPERAND_UNSIGNED(VALUE) \
2182 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2183
2184/* True if VALUE can be loaded into a register using LUI. */
2185
2186#define LUI_OPERAND(VALUE) \
2187 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2188 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2189
2190/* Return a value X with the low 16 bits clear, and such that
2191 VALUE - X is a signed 16-bit value. */
2192
2193#define CONST_HIGH_PART(VALUE) \
2194 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2195
2196#define CONST_LOW_PART(VALUE) \
2197 ((VALUE) - CONST_HIGH_PART (VALUE))
2198
2199#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2200#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2201#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
22c4c869 2202#define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
82f84ecb 2203#define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
cafe096b 2204
46299de9 2205/* The HI and LO registers can only be reloaded via the general
b8eb88d0
ILT		 2206 registers. Condition code registers can only be loaded to the
2207 general registers, and from the floating point registers. */
46299de9 2208
225b8835 2209#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
65239d20 2210 mips_secondary_reload_class (CLASS, MODE, X, true)
225b8835 2211#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
65239d20 2212 mips_secondary_reload_class (CLASS, MODE, X, false)
46299de9 2213
050af144
MF		 2214/* When targeting the o32 FPXX ABI, all moves with a length of doubleword
2215 or greater must be performed by FR-mode-aware instructions.
2216 This can be achieved using MFHC1/MTHC1 when these instructions are
2217 available but otherwise moves must go via memory.
2218 For the o32 FP64A ABI, all odd-numbered moves with a length of
2219 doubleword or greater are required to use memory. Using MTC1/MFC1
2220 to access the lower-half of these registers would require a forbidden
2221 single-precision access. We require all double-word moves to use
2222 memory because adding even and odd floating-point registers classes
2223 would have a significant impact on the backend. */
2224#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2225 mips_secondary_memory_needed ((CLASS1), (CLASS2), (MODE))
2226
e75b25e7
MM		 2227/* Return the maximum number of consecutive registers
2228 needed to represent mode MODE in a register of class CLASS. */
2229
d604bca3 2230#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
e75b25e7 2231
b0c42aed
JH		 2232#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2233 mips_cannot_change_mode_class (FROM, TO, CLASS)
e75b25e7
MM		 2234\f
2235/* Stack layout; function entry, exit and calling. */
2236
e75b25e7
MM		 2237#define STACK_GROWS_DOWNWARD
2238
ba6adec4 2239#define FRAME_GROWS_DOWNWARD flag_stack_protect
b5411fea 2240
ba6adec4
AN		 2241/* Size of the area allocated in the frame to save the GP. */
2242
2243#define MIPS_GP_SAVE_AREA_SIZE \
2244 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2245
2246/* The offset of the first local variable from the frame pointer. See
2247 mips_compute_frame_info for details about the frame layout. */
2248
2249#define STARTING_FRAME_OFFSET \
2250 (FRAME_GROWS_DOWNWARD \
2251 ? 0 \
2252 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
ab78d4a8 2253
cafe096b 2254#define RETURN_ADDR_RTX mips_return_addr
39dffea3 2255
57972505
RS		 2256/* Mask off the MIPS16 ISA bit in unwind addresses.
2257
2258 The reason for this is a little subtle. When unwinding a call,
2259 we are given the call's return address, which on most targets
2260 is the address of the following instruction. However, what we
2261 actually want to find is the EH region for the call itself.
2262 The target-independent unwind code therefore searches for "RA - 1".
2263
2264 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2265 RA - 1 is therefore the real (even-valued) start of the return
2266 instruction. EH region labels are usually odd-valued MIPS16 symbols
2267 too, so a search for an even address within a MIPS16 region would
2268 usually work.
2269
2270 However, there is an exception. If the end of an EH region is also
2271 the end of a function, the end label is allowed to be even. This is
2272 necessary because a following non-MIPS16 function may also need EH
2273 information for its first instruction.
2274
2275 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2276 non-ISA-encoded address. This probably isn't ideal, but it is
2277 the traditional (legacy) behavior. It is therefore only safe
2278 to search MIPS EH regions for an _odd-valued_ address.
2279
2280 Masking off the ISA bit means that the target-independent code
2281 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
7f48c9e1
AO		 2282#define MASK_RETURN_ADDR GEN_INT (-2)
2283
cafe096b 2284
7f48c9e1
AO		 2285/* Similarly, don't use the least-significant bit to tell pointers to
2286 code from vtable index. */
2287
2288#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2289
dfad12b5 2290/* The eliminations to $17 are only used for mips16 code. See the
2bcb2ab3 2291 definition of HARD_FRAME_POINTER_REGNUM. */
ab78d4a8
MM		 2292
2293#define ELIMINABLE_REGS \
2294{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2bcb2ab3
GK		 2295 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2296 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2bcb2ab3
GK		 2297 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2298 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2299 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
ab78d4a8 2300
b2471838 2301#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
dfad12b5 2302 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
e75b25e7 2303
dfad12b5 2304/* Allocate stack space for arguments at the beginning of each function. */
f73ad30e 2305#define ACCUMULATE_OUTGOING_ARGS 1
e75b25e7 2306
dfad12b5 2307/* The argument pointer always points to the first argument. */
305aa9e2 2308#define FIRST_PARM_OFFSET(FNDECL) 0
e75b25e7 2309
dfad12b5
RS		 2310/* o32 and o64 reserve stack space for all argument registers. */
2311#define REG_PARM_STACK_SPACE(FNDECL) \
7f9be256 2312 (TARGET_OLDABI \
dfad12b5 2313 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
ac8ab9fe 2314 : 0)
e75b25e7
MM		 2315
2316/* Define this if it is the responsibility of the caller to
7dac2f89 2317 allocate the area reserved for arguments passed in registers.
e75b25e7 2318 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
7dac2f89 2319 of this macro is to determine whether the space is included in
38173d38 2320 `crtl->outgoing_args_size'. */
81464b2c 2321#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
e75b25e7 2322
e64ca6c4 2323#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
e75b25e7 2324\f
e75b25e7
MM		 2325/* Symbolic macros for the registers used to return integer and floating
2326 point values. */
2327
2328#define GP_RETURN (GP_REG_FIRST + 2)
2329#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2330
7f9be256 2331#define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
ac8ab9fe 2332
e75b25e7
MM		 2333/* Symbolic macros for the first/last argument registers. */
2334
2335#define GP_ARG_FIRST (GP_REG_FIRST + 4)
ac8ab9fe 2336#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
e75b25e7 2337#define FP_ARG_FIRST (FP_REG_FIRST + 12)
ac8ab9fe 2338#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
e75b25e7 2339
c2db3f3d
RO		 2340/* Temporary register that is used when restoring $gp after a call. $4 and $5
2341 are used for returning complex double values in soft-float code, so $6 is the
2342 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2343 $gp itself as the temporary. */
2344#define POST_CALL_TMP_REG \
2345 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2346
46af8e31 2347/* 1 if N is a possible register number for function argument passing.
050af144
MF		 2348 We have no FP argument registers when soft-float. Special handling
2349 is required for O32 where only even numbered registers are used for
2350 O32-FPXX and O32-FP64. */
46af8e31
JW		 2351
2352#define FUNCTION_ARG_REGNO_P(N) \
8bf3ccbb 2353 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
050af144
MF		 2354 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2355 && (mips_abi != ABI_32 \
2356 || TARGET_FLOAT32 \
2357 || ((N) % 2 == 0)))) \
8bf3ccbb 2358 && !fixed_regs[N])
e75b25e7 2359\f
dfad12b5 2360/* This structure has to cope with two different argument allocation
b11a9d5f
RS		 2361 schemes. Most MIPS ABIs view the arguments as a structure, of which
2362 the first N words go in registers and the rest go on the stack. If I
2363 < N, the Ith word might go in Ith integer argument register or in a
2364 floating-point register. For these ABIs, we only need to remember
2365 the offset of the current argument into the structure.
4d72536e
RS		 2366
2367 The EABI instead allocates the integer and floating-point arguments
2368 separately. The first N words of FP arguments go in FP registers,
2369 the rest go on the stack. Likewise, the first N words of the other
2370 arguments go in integer registers, and the rest go on the stack. We
2371 need to maintain three counts: the number of integer registers used,
2372 the number of floating-point registers used, and the number of words
2373 passed on the stack.
2374
2375 We could keep separate information for the two ABIs (a word count for
2376 the standard ABIs, and three separate counts for the EABI). But it
2377 seems simpler to view the standard ABIs as forms of EABI that do not
2378 allocate floating-point registers.
2379
2380 So for the standard ABIs, the first N words are allocated to integer
65239d20
RS		 2381 registers, and mips_function_arg decides on an argument-by-argument
2382 basis whether that argument should really go in an integer register,
2383 or in a floating-point one. */
e75b25e7
MM		 2384
2385typedef struct mips_args {
4d72536e
RS		 2386 /* Always true for varargs functions. Otherwise true if at least
2387 one argument has been passed in an integer register. */
2388 int gp_reg_found;
2389
2390 /* The number of arguments seen so far. */
2391 unsigned int arg_number;
2392
b11a9d5f
RS		 2393 /* The number of integer registers used so far. For all ABIs except
2394 EABI, this is the number of words that have been added to the
2395 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
bb63e5a0 2396 unsigned int num_gprs;
4d72536e
RS		 2397
2398 /* For EABI, the number of floating-point registers used so far. */
bb63e5a0 2399 unsigned int num_fprs;
4d72536e
RS		 2400
2401 /* The number of words passed on the stack. */
2402 unsigned int stack_words;
2403
2404 /* On the mips16, we need to keep track of which floating point
2405 arguments were passed in general registers, but would have been
85f65093
KH		 2406 passed in the FP regs if this were a 32-bit function, so that we
2407 can move them to the FP regs if we wind up calling a 32-bit
4d72536e
RS		 2408 function. We record this information in fp_code, encoded in base
2409 four. A zero digit means no floating point argument, a one digit
2410 means an SFmode argument, and a two digit means a DFmode argument,
2411 and a three digit is not used. The low order digit is the first
2412 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2413 an SFmode argument. ??? A more sophisticated approach will be
2414 needed if MIPS_ABI != ABI_32. */
2415 int fp_code;
2416
2417 /* True if the function has a prototype. */
2418 int prototype;
e75b25e7
MM		 2419} CUMULATIVE_ARGS;
2420
2421/* Initialize a variable CUM of type CUMULATIVE_ARGS
2422 for a call to a function whose data type is FNTYPE.
ce6e2d90 2423 For a library call, FNTYPE is 0. */
e75b25e7 2424
0f6937fe 2425#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
65239d20 2426 mips_init_cumulative_args (&CUM, FNTYPE)
e75b25e7 2427
65239d20 2428#define FUNCTION_ARG_PADDING(MODE, TYPE) \
648bb159
RS		 2429 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2430
65239d20 2431#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
648bb159 2432 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
ac8ab9fe 2433
4d72536e
RS		 2434/* True if using EABI and varargs can be passed in floating-point
2435 registers. Under these conditions, we need a more complex form
2436 of va_list, which tracks GPR, FPR and stack arguments separately. */
2437#define EABI_FLOAT_VARARGS_P \
2438 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2439
e75b25e7 2440\f
e19da24c 2441#define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
cafe096b 2442
ac8ab9fe
RS		 2443/* Treat LOC as a byte offset from the stack pointer and round it up
2444 to the next fully-aligned offset. */
e64ca6c4
RS		 2445#define MIPS_STACK_ALIGN(LOC) \
2446 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
e75b25e7
MM		 2447
2448\f
2449/* Output assembler code to FILE to increment profiler label # LABELNO
2450 for profiling a function entry. */
2451
c376dbfb 2452#define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
e75b25e7 2453
d9dced13
RS		 2454/* The profiler preserves all interesting registers, including $31. */
2455#define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2456
f50c57ba
JW		 2457/* No mips port has ever used the profiler counter word, so don't emit it
2458 or the label for it. */
2459
2460#define NO_PROFILE_COUNTERS 1
2461
d8d5b1e1
MM		 2462/* Define this macro if the code for function profiling should come
2463 before the function prologue. Normally, the profiling code comes
2464 after. */
2465
2466/* #define PROFILE_BEFORE_PROLOGUE */
2467
e75b25e7
MM		 2468/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2469 the stack pointer does not matter. The value is tested only in
2470 functions that have frame pointers.
2471 No definition is equivalent to always zero. */
2472
2473#define EXIT_IGNORE_STACK 1
2474
2475\f
c640a3bd 2476/* Trampolines are a block of code followed by two pointers. */
e75b25e7 2477
c640a3bd
RS		 2478#define TRAMPOLINE_SIZE \
2479 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
e75b25e7 2480
c640a3bd
RS		 2481/* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2482 pointers from a single LUI base. */
e75b25e7 2483
c640a3bd 2484#define TRAMPOLINE_ALIGNMENT 64
e75b25e7 2485
a1d29c8c 2486/* mips_trampoline_init calls this library function to flush
c85f7c16
JL		 2487 program and data caches. */
2488
2489#ifndef CACHE_FLUSH_FUNC
2490#define CACHE_FLUSH_FUNC "_flush_cache"
2491#endif
2492
d9dced13
RS		 2493#define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2494 /* Flush both caches. We need to flush the data cache in case \
2495 the system has a write-back cache. */ \
2496 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
bbbbb16a 2497 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
d9dced13
RS		 2498 GEN_INT (3), TYPE_MODE (integer_type_node))
2499
e75b25e7
MM		 2500\f
2501/* Addressing modes, and classification of registers for them. */
2502
bcbc6b7f
RS		 2503#define REGNO_OK_FOR_INDEX_P(REGNO) 0
2504#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2505 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
e75b25e7
MM		 2506\f
2507/* Maximum number of registers that can appear in a valid memory address. */
2508
2509#define MAX_REGS_PER_ADDRESS 1
2510
cafe096b
EC		 2511/* Check for constness inline but use mips_legitimate_address_p
2512 to check whether a constant really is an address. */
2513
2514#define CONSTANT_ADDRESS_P(X) \
c6c3dba9 2515 (CONSTANT_P (X) && memory_address_p (SImode, X))
cafe096b 2516
9c9e7632
GK		 2517/* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2518 'the start of the function that this code is output in'. */
2519
2520#define ASM_OUTPUT_LABELREF(FILE,NAME) \
2521 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2522 asm_fprintf ((FILE), "%U%s", \
2523 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2524 else \
2525 asm_fprintf ((FILE), "%U%s", (NAME))
e75b25e7 2526\f
4dbdb061
JW		 2527/* Flag to mark a function decl symbol that requires a long call. */
2528#define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2529#define SYMBOL_REF_LONG_CALL_P(X) \
2530 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2531
08d0963a
RS		 2532/* This flag marks functions that cannot be lazily bound. */
2533#define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2534#define SYMBOL_REF_BIND_NOW_P(RTX) \
2535 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2536
c93c5160
RS		 2537/* True if we're generating a form of MIPS16 code in which jump tables
2538 are stored in the text section and encoded as 16-bit PC-relative
2539 offsets. This is only possible when general text loads are allowed,
545ca0f2
JB		 2540 since the table access itself will be an "lh" instruction. If the
2541 PC-relative offsets grow too large, 32-bit offsets are used instead. */
c93c5160 2542#define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2bcb2ab3 2543
c93c5160
RS		 2544#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2545
ca97b221 2546#define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
545ca0f2
JB		 2547
2548/* Only use short offsets if their range will not overflow. */
2549#define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
ca97b221
RS		 2550 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2551 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2552 : SImode)
c93c5160
RS		 2553
2554#define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
e75b25e7 2555
e75b25e7 2556/* Define this as 1 if `char' should by default be signed; else as 0. */
6639753e 2557#ifndef DEFAULT_SIGNED_CHAR
e75b25e7 2558#define DEFAULT_SIGNED_CHAR 1
6639753e 2559#endif
e75b25e7 2560
a1c6b246
RS		 2561/* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2562 we generally don't want to use them for copying arbitrary data.
2563 A single N-word move is usually the same cost as N single-word moves. */
2564#define MOVE_MAX UNITS_PER_WORD
876c09d3 2565#define MAX_MOVE_MAX 8
e75b25e7
MM		 2566
2567/* Define this macro as a C expression which is nonzero if
2568 accessing less than a word of memory (i.e. a `char' or a
2569 `short') is no faster than accessing a word of memory, i.e., if
2570 such access require more than one instruction or if there is no
2571 difference in cost between byte and (aligned) word loads.
2572
2573 On RISC machines, it tends to generate better code to define
64e7e238
SL		 2574 this as 1, since it avoids making a QI or HI mode register.
2575
2576 But, generating word accesses for -mips16 is generally bad as shifts
2577 (often extended) would be needed for byte accesses. */
2578#define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
e75b25e7 2579
49042313
MX		 2580/* Standard MIPS integer shifts truncate the shift amount to the
2581 width of the shifted operand. However, Loongson vector shifts
2582 do not truncate the shift amount at all. */
1f5f063d 2583#define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
e75b25e7
MM		 2584
2585/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2586 is done just by pretending it is already truncated. */
876c09d3
JW		 2587#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2588 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
e75b25e7 2589
cafe096b 2590
e75b25e7
MM		 2591/* Specify the machine mode that pointers have.
2592 After generation of rtl, the compiler makes no further distinction
cafe096b 2593 between pointers and any other objects of this machine mode. */
876c09d3 2594
1eeed24e 2595#ifndef Pmode
cafe096b 2596#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
1eeed24e 2597#endif
e75b25e7 2598
cafe096b
EC		 2599/* Give call MEMs SImode since it is the "most permissive" mode
2600 for both 32-bit and 64-bit targets. */
e75b25e7 2601
cafe096b 2602#define FUNCTION_MODE SImode
e75b25e7 2603
e75b25e7 2604\f
4b11e406
RS		 2605/* We allocate $fcc registers by hand and can't cope with moves of
2606 CCmode registers to and from pseudos (or memory). */
7506f491
DE		 2607#define AVOID_CCMODE_COPIES
2608
e75b25e7
MM		 2609/* A C expression for the cost of a branch instruction. A value of
2610 1 is the default; other values are interpreted relative to that. */
2611
3a4fd356 2612#define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
c1bd2d66 2613#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
e75b25e7 2614
da734fa1
RS		 2615/* The MIPS port has several functions that return an instruction count.
2616 Multiplying the count by this value gives the number of bytes that
2617 the instructions occupy. */
2618#define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2619
2620/* The length of a NOP in bytes. */
2621#define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2622
0ff83799
MM		 2623/* If defined, modifies the length assigned to instruction INSN as a
2624 function of the context in which it is used. LENGTH is an lvalue
2625 that contains the initially computed length of the insn and should
2626 be updated with the correct length of the insn. */
2627#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2628 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
a8c1d5f8
RS		 2629
2630/* Return the asm template for a non-MIPS16 conditional branch instruction.
2631 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2632 its operands. */
2633#define MIPS_BRANCH(OPCODE, OPERANDS) \
2634 "%*" OPCODE "%?\t" OPERANDS "%/"
d9870b7e 2635
0c433c31
RS		 2636/* Return an asm string that forces INSN to be treated as an absolute
2637 J or JAL instruction instead of an assembler macro. */
2638#define MIPS_ABSOLUTE_JUMP(INSN) \
2639 (TARGET_ABICALLS_PIC2 \
2640 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2641 : INSN)
2642
d9870b7e 2643/* Return the asm template for a call. INSN is the instruction's mnemonic
b53da244
AN		 2644 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2645 number of the target. SIZE_OPNO is the operand number of the argument size
2646 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2647 -1 and the call is indirect, use the function symbol from the call
2648 attributes to attach a R_MIPS_JALR relocation to the call.
d9870b7e 2649
14976818 2650 When generating GOT code without explicit relocation operators,
d9870b7e
RS		 2651 all calls should use assembly macros. Otherwise, all indirect
2652 calls should use "jr" or "jalr"; we will arrange to restore $gp
2653 afterwards if necessary. Finally, we can only generate direct
22c4c869
CM		 2654 calls for -mabicalls by temporarily switching to non-PIC mode.
2655
2656 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2657 instruction is in the delay slot of jal(r). */
b53da244 2658#define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
14976818 2659 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
b53da244 2660 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
b53da244 2661 : REG_P (OPERANDS[TARGET_OPNO]) \
22c4c869
CM		 2662 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2663 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2664 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2665 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2666 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2667 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
9f9d82aa
CM		 2668 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2669 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2670 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
22c4c869
CM		 2671
2672/* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2673 "jrc" when nop is in the delay slot of "jr". */
2674
2675#define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2676 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2677 ? "%*j\t%" #OPNO "%/" \
2678 : REG_P (OPERANDS[OPNO]) \
2679 ? "%*jr%:\t%" #OPNO \
2680 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2681
e75b25e7
MM		 2682\f
2683/* Control the assembler format that we output. */
2684
e75b25e7
MM		 2685/* Output to assembler file text saying following lines
2686 may contain character constants, extra white space, comments, etc. */
2687
b2bcb32d 2688#ifndef ASM_APP_ON
e75b25e7 2689#define ASM_APP_ON " #APP\n"
b2bcb32d 2690#endif
e75b25e7
MM		 2691
2692/* Output to assembler file text saying following lines
2693 no longer contain unusual constructs. */
2694
b2bcb32d 2695#ifndef ASM_APP_OFF
e75b25e7 2696#define ASM_APP_OFF " #NO_APP\n"
b2bcb32d 2697#endif
e75b25e7 2698
5b9cc93e
RS		 2699#define REGISTER_NAMES \
2700{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2701 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2702 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2703 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2704 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2705 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2706 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2707 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2708 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
0c433c31 2709 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
5b9cc93e
RS		 2710 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2711 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2712 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2713 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2714 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2715 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2716 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2717 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2718 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2719 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2720 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
118ea793
CF		 2721 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2722 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2723 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
5b9cc93e
RS		 2724
2725/* List the "software" names for each register. Also list the numerical
2726 names for $fp and $sp. */
e75b25e7
MM		 2727
2728#define ADDITIONAL_REGISTER_NAMES \
2729{ \
e75b25e7
MM		 2730 { "$29", 29 + GP_REG_FIRST }, \
2731 { "$30", 30 + GP_REG_FIRST }, \
e75b25e7
MM		 2732 { "at", 1 + GP_REG_FIRST }, \
2733 { "v0", 2 + GP_REG_FIRST }, \
2734 { "v1", 3 + GP_REG_FIRST }, \
2735 { "a0", 4 + GP_REG_FIRST }, \
2736 { "a1", 5 + GP_REG_FIRST }, \
2737 { "a2", 6 + GP_REG_FIRST }, \
2738 { "a3", 7 + GP_REG_FIRST }, \
2739 { "t0", 8 + GP_REG_FIRST }, \
2740 { "t1", 9 + GP_REG_FIRST }, \
2741 { "t2", 10 + GP_REG_FIRST }, \
2742 { "t3", 11 + GP_REG_FIRST }, \
2743 { "t4", 12 + GP_REG_FIRST }, \
2744 { "t5", 13 + GP_REG_FIRST }, \
2745 { "t6", 14 + GP_REG_FIRST }, \
2746 { "t7", 15 + GP_REG_FIRST }, \
2747 { "s0", 16 + GP_REG_FIRST }, \
2748 { "s1", 17 + GP_REG_FIRST }, \
2749 { "s2", 18 + GP_REG_FIRST }, \
2750 { "s3", 19 + GP_REG_FIRST }, \
2751 { "s4", 20 + GP_REG_FIRST }, \
2752 { "s5", 21 + GP_REG_FIRST }, \
2753 { "s6", 22 + GP_REG_FIRST }, \
2754 { "s7", 23 + GP_REG_FIRST }, \
2755 { "t8", 24 + GP_REG_FIRST }, \
2756 { "t9", 25 + GP_REG_FIRST }, \
2757 { "k0", 26 + GP_REG_FIRST }, \
2758 { "k1", 27 + GP_REG_FIRST }, \
2759 { "gp", 28 + GP_REG_FIRST }, \
2760 { "sp", 29 + GP_REG_FIRST }, \
2761 { "fp", 30 + GP_REG_FIRST }, \
0c93ed52 2762 { "ra", 31 + GP_REG_FIRST } \
e75b25e7
MM		 2763}
2764
e75b25e7
MM		 2765#define DBR_OUTPUT_SEQEND(STREAM) \
2766do \
2767 { \
cf5fb4b0
RS		 2768 /* Undo the effect of '%*'. */ \
2769 mips_pop_asm_switch (&mips_nomacro); \
2770 mips_pop_asm_switch (&mips_noreorder); \
2771 /* Emit a blank line after the delay slot for emphasis. */ \
e75b25e7
MM		 2772 fputs ("\n", STREAM); \
2773 } \
2774while (0)
2775
9ec36da5 2776/* The MIPS implementation uses some labels for its own purpose. The
e75b25e7
MM		 2777 following lists what labels are created, and are all formed by the
2778 pattern $L[a-z].*. The machine independent portion of GCC creates
2779 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2780
c5b7917e 2781 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
e75b25e7
MM		 2782 $Lb[0-9]+ Begin blocks for MIPS debug support
2783 $Lc[0-9]+ Label for use in s<xx> operation.
33005162 2784 $Le[0-9]+ End blocks for MIPS debug support */
e75b25e7 2785
44404b8b 2786#undef ASM_DECLARE_OBJECT_NAME
c1115ccd 2787#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
586de218 2788 mips_declare_object (STREAM, NAME, "", ":\n")
31c714e3 2789
506a61b1
KG		 2790/* Globalizing directive for a label. */
2791#define GLOBAL_ASM_OP "\t.globl\t"
e75b25e7 2792
31c714e3 2793/* This says how to define a global common symbol. */
e75b25e7 2794
35f5add9 2795#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
e75b25e7 2796
112cdef5 2797/* This says how to define a local common symbol (i.e., not visible to
31c714e3 2798 linker). */
e75b25e7 2799
48b2e0a7
RS		 2800#ifndef ASM_OUTPUT_ALIGNED_LOCAL
2801#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2802 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2803#endif
e75b25e7
MM		 2804
2805/* This says how to output an external. It would be possible not to
2806 output anything and let undefined symbol become external. However
2807 the assembler uses length information on externals to allocate in
2808 data/sdata bss/sbss, thereby saving exec time. */
2809
4d9f4c46 2810#undef ASM_OUTPUT_EXTERNAL
e75b25e7
MM		 2811#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2812 mips_output_external(STREAM,DECL,NAME)
2813
e75b25e7
MM		 2814/* This is how to declare a function name. The actual work of
2815 emitting the label is moved to function_prologue, so that we can
2816 get the line number correctly emitted before the .ent directive,
789b7de5 2817 and after any .file directives. Define as empty so that the function
4e314d1f
EC		 2818 is not declared before the .ent directive elsewhere. */
2819
44404b8b 2820#undef ASM_DECLARE_FUNCTION_NAME
33005162 2821#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4e314d1f 2822
e75b25e7
MM		 2823/* This is how to store into the string LABEL
2824 the symbol_ref name of an internal numbered label where
2825 PREFIX is the class of label and NUM is the number within the class.
2826 This is suitable for output with `assemble_name'. */
2827
44404b8b 2828#undef ASM_GENERATE_INTERNAL_LABEL
e75b25e7 2829#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4f70758f 2830 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
e75b25e7 2831
370d36c6
RS		 2832/* Print debug labels as "foo = ." rather than "foo:" because they should
2833 represent a byte pointer rather than an ISA-encoded address. This is
2834 particularly important for code like:
2835
2836 $LFBxxx = .
2837 .cfi_startproc
2838 ...
2839 .section .gcc_except_table,...
2840 ...
2841 .uleb128 foo-$LFBxxx
2842
2843 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2844 likewise a byte pointer rather than an ISA-encoded address.
2845
2846 At the time of writing, this hook is not used for the function end
2847 label:
2848
2849 $LFExxx:
2850 .end foo
2851
2852 But this doesn't matter, because GAS doesn't treat a pre-.end label
2853 as a MIPS16 one anyway. */
2854
2855#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2856 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2857
e75b25e7
MM		 2858/* This is how to output an element of a case-vector that is absolute. */
2859
2860#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
6ae1498b 2861 fprintf (STREAM, "\t%s\t%sL%d\n", \
cafe096b 2862 ptr_mode == DImode ? ".dword" : ".word", \
6ae1498b 2863 LOCAL_LABEL_PREFIX, \
876c09d3 2864 VALUE)
e75b25e7 2865
827555ea
RS		 2866/* This is how to output an element of a case-vector. We can make the
2867 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2868 is supported. */
e75b25e7 2869
33f7f353 2870#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
e0bfcea5 2871do { \
c93c5160 2872 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
545ca0f2
JB		 2873 { \
2874 if (GET_MODE (BODY) == HImode) \
2875 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2876 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2877 else \
2878 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2879 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2880 } \
cafe096b 2881 else if (TARGET_GPWORD) \
6ae1498b 2882 fprintf (STREAM, "\t%s\t%sL%d\n", \
cafe096b 2883 ptr_mode == DImode ? ".gpdword" : ".gpword", \
6ae1498b 2884 LOCAL_LABEL_PREFIX, VALUE); \
8cb6400c
RS		 2885 else if (TARGET_RTP_PIC) \
2886 { \
2887 /* Make the entry relative to the start of the function. */ \
2888 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2889 fprintf (STREAM, "\t%s\t%sL%d-", \
2890 Pmode == DImode ? ".dword" : ".word", \
2891 LOCAL_LABEL_PREFIX, VALUE); \
2892 assemble_name (STREAM, XSTR (fnsym, 0)); \
2893 fprintf (STREAM, "\n"); \
2894 } \
516a2dfd 2895 else \
b2d8cf33 2896 fprintf (STREAM, "\t%s\t%sL%d\n", \
cafe096b 2897 ptr_mode == DImode ? ".dword" : ".word", \
b2d8cf33 2898 LOCAL_LABEL_PREFIX, VALUE); \
e0bfcea5
ILT		 2899} while (0)
2900
e75b25e7
MM		 2901/* This is how to output an assembler line
2902 that says to advance the location counter
2903 to a multiple of 2**LOG bytes. */
2904
2905#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
a688e0b7 2906 fprintf (STREAM, "\t.align\t%d\n", (LOG))
e75b25e7 2907
38e01259 2908/* This is how to output an assembler line to advance the location
e75b25e7
MM		 2909 counter by SIZE bytes. */
2910
44404b8b 2911#undef ASM_OUTPUT_SKIP
e75b25e7 2912#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
16998094 2913 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
e75b25e7 2914
e75b25e7 2915/* This is how to output a string. */
44404b8b 2916#undef ASM_OUTPUT_ASCII
65239d20 2917#define ASM_OUTPUT_ASCII mips_output_ascii
e75b25e7 2918
e75b25e7 2919\f
b82b0773
MM		 2920/* Default to -G 8 */
2921#ifndef MIPS_DEFAULT_GVALUE
2922#define MIPS_DEFAULT_GVALUE 8
2923#endif
e75b25e7 2924
f3b39eba
MM		 2925/* Define the strings to put out for each section in the object file. */
2926#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2927#define DATA_SECTION_ASM_OP "\t.data" /* large data */
2017ed61
EC		 2928
2929#undef READONLY_DATA_SECTION_ASM_OP
d48bc59a 2930#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
e75b25e7 2931\f
e75b25e7
MM		 2932#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2933do \
2934 { \
f29adf5b
SL		 2935 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2936 TARGET_64BIT ? "daddiu" : "addiu", \
e75b25e7
MM		 2937 reg_names[STACK_POINTER_REGNUM], \
2938 reg_names[STACK_POINTER_REGNUM], \
876c09d3 2939 TARGET_64BIT ? "sd" : "sw", \
e75b25e7
MM		 2940 reg_names[REGNO], \
2941 reg_names[STACK_POINTER_REGNUM]); \
2942 } \
2943while (0)
2944
2945#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2946do \
2947 { \
cf5fb4b0 2948 mips_push_asm_switch (&mips_noreorder); \
876c09d3
JW		 2949 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2950 TARGET_64BIT ? "ld" : "lw", \
e75b25e7
MM		 2951 reg_names[REGNO], \
2952 reg_names[STACK_POINTER_REGNUM], \
876c09d3 2953 TARGET_64BIT ? "daddu" : "addu", \
e75b25e7
MM		 2954 reg_names[STACK_POINTER_REGNUM], \
2955 reg_names[STACK_POINTER_REGNUM]); \
cf5fb4b0 2956 mips_pop_asm_switch (&mips_noreorder); \
e75b25e7
MM		 2957 } \
2958while (0)
2959
4baed42f
DE		 2960/* How to start an assembler comment.
2961 The leading space is important (the mips native assembler requires it). */
e75b25e7 2962#ifndef ASM_COMMENT_START
4baed42f 2963#define ASM_COMMENT_START " #"
e75b25e7 2964#endif
3f1f8d8c 2965\f
498887c8 2966#undef SIZE_TYPE
cafe096b 2967#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3f1f8d8c 2968
498887c8 2969#undef PTRDIFF_TYPE
cafe096b 2970#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
cfa31150 2971
a1c6b246
RS		 2972/* The maximum number of bytes that can be copied by one iteration of
2973 a movmemsi loop; see mips_block_move_loop. */
2974#define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2975 (UNITS_PER_WORD * 4)
2976
2977/* The maximum number of bytes that can be copied by a straight-line
2978 implementation of movmemsi; see mips_block_move_straight. We want
2979 to make sure that any loop-based implementation will iterate at
2980 least twice. */
2981#define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2982 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2983
cfa31150
SL		 2984/* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2985 values were determined experimentally by benchmarking with CSiBE.
2986 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2987 for o32 where we have to restore $gp afterwards as well as make an
2988 indirect call), but in practice, bumping this up higher for
2989 TARGET_ABICALLS doesn't make much difference to code size. */
2990
2991#define MIPS_CALL_RATIO 8
2992
a1c6b246
RS		 2993/* Any loop-based implementation of movmemsi will have at least
2994 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2995 moves, so allow individual copies of fewer elements.
2996
2997 When movmemsi is not available, use a value approximating
2998 the length of a memcpy call sequence, so that move_by_pieces
2999 will generate inline code if it is shorter than a function call.
3000 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3001 we'll have to generate a load/store pair for each, halve the
3002 value of MIPS_CALL_RATIO to take that into account. */
3003
e04ad03d 3004#define MOVE_RATIO(speed) \
a1c6b246
RS		 3005 (HAVE_movmemsi \
3006 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3007 : MIPS_CALL_RATIO / 2)
3008
cfa31150
SL		 3009/* For CLEAR_RATIO, when optimizing for size, give a better estimate
3010 of the length of a memset call, but use the default otherwise. */
3011
e04ad03d
JH		 3012#define CLEAR_RATIO(speed)\
3013 ((speed) ? 15 : MIPS_CALL_RATIO)
cfa31150
SL		 3014
3015/* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3016 optimizing for size adjust the ratio to account for the overhead of
3017 loading the constant and replicating it across the word. */
3018
e04ad03d
JH		 3019#define SET_RATIO(speed) \
3020 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2bcb2ab3 3021\f
3c0121e4
AO		 3022/* Since the bits of the _init and _fini function is spread across
3023 many object files, each potentially with its own GP, we must assume
3024 we need to load our GP. We don't preserve $gp or $ra, since each
3025 init/fini chunk is supposed to initialize $gp, and crti/crtn
3026 already take care of preserving $ra and, when appropriate, $gp. */
27d54b2a 3027#if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3c0121e4
AO		 3028#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3029 asm (SECTION_OP "\n\
1274718f
CLT		 3030 .set push\n\
3031 .set nomips16\n\
3c0121e4
AO		 3032 .set noreorder\n\
3033 bal 1f\n\
3034 nop\n\
30351: .cpload $31\n\
3036 .set reorder\n\
8d92d274
PJ		 3037 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3038 jalr $25\n\
1274718f 3039 .set pop\n\
3c0121e4 3040 " TEXT_SECTION_ASM_OP);
8d92d274 3041#elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3c0121e4
AO		 3042#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3043 asm (SECTION_OP "\n\
1274718f
CLT		 3044 .set push\n\
3045 .set nomips16\n\
3c0121e4
AO		 3046 .set noreorder\n\
3047 bal 1f\n\
3048 nop\n\
30491: .set reorder\n\
3050 .cpsetup $31, $2, 1b\n\
8d92d274
PJ		 3051 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3052 jalr $25\n\
3053 .set pop\n\
3054 " TEXT_SECTION_ASM_OP);
3055#elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3056#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3057 asm (SECTION_OP "\n\
3058 .set push\n\
3059 .set nomips16\n\
3060 .set noreorder\n\
3061 bal 1f\n\
3062 nop\n\
30631: .set reorder\n\
3064 .cpsetup $31, $2, 1b\n\
3065 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3066 jalr $25\n\
1274718f 3067 .set pop\n\
3c0121e4
AO		 3068 " TEXT_SECTION_ASM_OP);
3069#endif
69229b81
DJ		 3070
3071#ifndef HAVE_AS_TLS
3072#define HAVE_AS_TLS 0
3073#endif
8d2fc1c4 3074
ff3f3951
MR		 3075#ifndef HAVE_AS_NAN
3076#define HAVE_AS_NAN 0
3077#endif
3078
ab77a036 3079#ifndef USED_FOR_TARGET
cf5fb4b0
RS		 3080/* Information about ".set noFOO; ...; .set FOO" blocks. */
3081struct mips_asm_switch {
3082 /* The FOO in the description above. */
3083 const char *name;
3084
3085 /* The current block nesting level, or 0 if we aren't in a block. */
3086 int nesting_level;
3087};
3088
ab77a036 3089extern const enum reg_class mips_regno_to_class[];
65239d20 3090extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
ab77a036
RS		 3091extern const char *current_function_file; /* filename current function is in */
3092extern int num_source_filenames; /* current .file # */
cf5fb4b0
RS		 3093extern struct mips_asm_switch mips_noreorder;
3094extern struct mips_asm_switch mips_nomacro;
3095extern struct mips_asm_switch mips_noat;
ab77a036
RS		 3096extern int mips_dbx_regno[];
3097extern int mips_dwarf_regno[];
3098extern bool mips_split_p[];
08d0963a 3099extern bool mips_split_hi_p[];
ddaf8125
RS		 3100extern bool mips_use_pcrel_pool_p[];
3101extern const char *mips_lo_relocs[];
3102extern const char *mips_hi_relocs[];
24609606
RS		 3103extern enum processor mips_arch; /* which cpu to codegen for */
3104extern enum processor mips_tune; /* which cpu to schedule for */
ab77a036 3105extern int mips_isa; /* architectural level */
ad782bc9 3106extern int mips_isa_rev;
ab77a036
RS		 3107extern const struct mips_cpu_info *mips_arch_info;
3108extern const struct mips_cpu_info *mips_tune_info;
22c4c869 3109extern unsigned int mips_base_compression_flags;
5aa62249 3110extern GTY(()) struct target_globals *mips16_globals;
ab77a036 3111#endif
58684fa0
MK		 3112
3113/* Enable querying of DFA units. */
3114#define CPU_UNITS_QUERY 1
1afc5373
CF		 3115
3116#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3117 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
28143fdd 3118
49576e25
RS		 3119/* As on most targets, we want the .eh_frame section to be read-only where
3120 possible. And as on most targets, this means two things:
3121
3122 (a) Non-locally-binding pointers must have an indirect encoding,
3123 so that the addresses in the .eh_frame section itself become
3124 locally-binding.
3125
3126 (b) A shared library's .eh_frame section must encode locally-binding
3127 pointers in a relative (relocation-free) form.
3128
3129 However, MIPS has traditionally not allowed directives like:
3130
3131 .long x-.
3132
3133 in cases where "x" is in a different section, or is not defined in the
3134 same assembly file. We are therefore unable to emit the PC-relative
3135 form required by (b) at assembly time.
3136
3137 Fortunately, the linker is able to convert absolute addresses into
3138 PC-relative addresses on our behalf. Unfortunately, only certain
3139 versions of the linker know how to do this for indirect pointers,
3140 and for personality data. We must fall back on using writable
3141 .eh_frame sections for shared libraries if the linker does not
3142 support this feature. */
3143#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3144 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
5aa62249
RS		 3145
3146/* For switching between MIPS16 and non-MIPS16 modes. */
3147#define SWITCHABLE_TARGET 1
81a478c8
RS		 3148
3149/* Several named MIPS patterns depend on Pmode. These patterns have the
3150 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3151 Add the appropriate suffix to generator function NAME and invoke it
3152 with arguments ARGS. */
3153#define PMODE_INSN(NAME, ARGS) \
3154 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
8cfebf86
SE		 3155
3156/* If we are *not* using multilibs and the default ABI is not ABI_32 we
3157 need to change these from /lib and /usr/lib. */
3158#if MIPS_ABI_DEFAULT == ABI_N32
3159#define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3160#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3161#elif MIPS_ABI_DEFAULT == ABI_64
3162#define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3163#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3164#endif
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