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c8829dad | 1 | /* Definitions of target machine for GNU compiler. MIPS version. |
aad93da1 | 2 | Copyright (C) 1989-2017 Free Software Foundation, Inc. |
bad0fa11 | 3 | Contributed by A. Lichnewsky (lich@inria.inria.fr). |
4 | Changed by Michael Meissner (meissner@osf.org). | |
c910419d | 5 | 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and |
bad0fa11 | 6 | Brendan Eich (brendan@microunity.com). |
c8829dad | 7 | |
187b36cf | 8 | This file is part of GCC. |
c8829dad | 9 | |
187b36cf | 10 | GCC is free software; you can redistribute it and/or modify |
c8829dad | 11 | it under the terms of the GNU General Public License as published by |
038d1e19 | 12 | the Free Software Foundation; either version 3, or (at your option) |
c8829dad | 13 | any later version. |
14 | ||
187b36cf | 15 | GCC is distributed in the hope that it will be useful, |
c8829dad | 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
038d1e19 | 21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
c8829dad | 23 | |
24 | ||
a8a393cb | 25 | #include "config/vxworks-dummy.h" |
26 | ||
96cfbaee | 27 | #ifdef GENERATOR_FILE |
28 | /* This is used in some insn conditions, so needs to be declared, but | |
29 | does not need to be defined. */ | |
30 | extern int target_flags_explicit; | |
31 | #endif | |
32 | ||
c8829dad | 33 | /* MIPS external variables defined in mips.c. */ |
34 | ||
efd092f3 | 35 | /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), |
36 | ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended | |
c910419d | 37 | to work on a 64-bit machine. */ |
6c51b52b | 38 | |
ef9c575c | 39 | #define ABI_32 0 |
40 | #define ABI_N32 1 | |
41 | #define ABI_64 2 | |
42 | #define ABI_EABI 3 | |
a4e2d767 | 43 | #define ABI_O64 4 |
582b17a6 | 44 | |
6b65ee54 | 45 | /* Masks that affect tuning. |
46 | ||
e55aa189 | 47 | PTF_AVOID_BRANCHLIKELY_SPEED |
6b65ee54 | 48 | Set if it is usually not profitable to use branch-likely instructions |
e55aa189 | 49 | for this target when optimizing code for speed, typically because |
50 | the branches are always predicted taken and so incur a large overhead | |
51 | when not taken. | |
52 | ||
53 | PTF_AVOID_BRANCHLIKELY_SIZE | |
54 | As above but when optimizing for size. | |
55 | ||
56 | PTF_AVOID_BRANCHLIKELY_ALWAYS | |
57 | As above but regardless of whether we optimize for speed or size. | |
14844884 | 58 | |
59 | PTF_AVOID_IMADD | |
60 | Set if it is usually not profitable to use the integer MADD or MSUB | |
61 | instructions because of the overhead of getting the result out of | |
62 | the HI/LO registers. */ | |
63 | ||
e55aa189 | 64 | #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1 |
65 | #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2 | |
66 | #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \ | |
67 | PTF_AVOID_BRANCHLIKELY_SIZE) | |
68 | #define PTF_AVOID_IMADD 0x4 | |
6b65ee54 | 69 | |
a2f10574 | 70 | /* Information about one recognized processor. Defined here for the |
5153cc32 | 71 | benefit of TARGET_CPU_CPP_BUILTINS. */ |
72 | struct mips_cpu_info { | |
73 | /* The 'canonical' name of the processor as far as GCC is concerned. | |
74 | It's typically a manufacturer's prefix followed by a numerical | |
c910419d | 75 | designation. It should be lowercase. */ |
5153cc32 | 76 | const char *name; |
77 | ||
78 | /* The internal processor number that most closely matches this | |
79 | entry. Several processors can have the same value, if there's no | |
80 | difference between them from GCC's point of view. */ | |
5d54fceb | 81 | enum processor cpu; |
5153cc32 | 82 | |
83 | /* The ISA level that the processor implements. */ | |
84 | int isa; | |
6b65ee54 | 85 | |
86 | /* A mask of PTF_* values. */ | |
87 | unsigned int tune_flags; | |
5153cc32 | 88 | }; |
89 | ||
498fed4e | 90 | #include "config/mips/mips-opts.h" |
f02776dd | 91 | |
e47c8b8f | 92 | /* Macros to silence warnings about numbers being signed in traditional |
93 | C and unsigned in ISO C when compiled on 32-bit hosts. */ | |
94 | ||
95 | #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ | |
96 | #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ | |
97 | #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ | |
98 | ||
1656cc5c | 99 | \f |
100 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
101 | ||
a8a393cb | 102 | /* True if we are generating position-independent VxWorks RTP code. */ |
103 | #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) | |
104 | ||
59449ca9 | 105 | /* Compact branches must not be used if the user either selects the |
106 | 'never' policy or the 'optimal' policy on a core that lacks | |
107 | compact branch instructions. */ | |
108 | #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \ | |
109 | || (mips_cb == MIPS_CB_OPTIMAL \ | |
110 | && !ISA_HAS_COMPACT_BRANCHES)) | |
111 | ||
112 | /* Compact branches may be used if the user either selects the | |
113 | 'always' policy or the 'optimal' policy on a core that supports | |
114 | compact branch instructions. */ | |
115 | #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \ | |
116 | || (mips_cb == MIPS_CB_OPTIMAL \ | |
117 | && ISA_HAS_COMPACT_BRANCHES)) | |
118 | ||
119 | /* Compact branches must always be generated if the user selects | |
120 | the 'always' policy or the 'optimal' policy om a core that | |
121 | lacks delay slot branch instructions. */ | |
122 | #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \ | |
123 | || (mips_cb == MIPS_CB_OPTIMAL \ | |
124 | && !ISA_HAS_DELAY_SLOTS)) | |
125 | ||
126 | /* Special handling for JRC that exists in microMIPSR3 as well as R6 | |
127 | ISAs with full compact branch support. */ | |
128 | #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \ | |
129 | || TARGET_MICROMIPS) \ | |
130 | && mips_cb != MIPS_CB_NEVER) | |
131 | ||
4a909f69 | 132 | /* True if the output file is marked as ".abicalls; .option pic0" |
133 | (-call_nonpic). */ | |
134 | #define TARGET_ABICALLS_PIC0 \ | |
135 | (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT) | |
136 | ||
137 | /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */ | |
138 | #define TARGET_ABICALLS_PIC2 \ | |
139 | (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0) | |
140 | ||
c9e1a048 | 141 | /* True if the call patterns should be split into a jalr followed by |
46414626 | 142 | an instruction to restore $gp. It is only safe to split the load |
74facf6e | 143 | from the call when every use of $gp is explicit. |
144 | ||
145 | See mips_must_initialize_gp_p for details about how we manage the | |
146 | global pointer. */ | |
c9e1a048 | 147 | |
148 | #define TARGET_SPLIT_CALLS \ | |
74facf6e | 149 | (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed) |
c9e1a048 | 150 | |
1b6b10a9 | 151 | /* True if we're generating a form of -mabicalls in which we can use |
152 | operators like %hi and %lo to refer to locally-binding symbols. | |
153 | We can only do this for -mno-shared, and only then if we can use | |
154 | relocation operations instead of assembly macros. It isn't really | |
155 | worth using absolute sequences for 64-bit symbols because GOT | |
156 | accesses are so much shorter. */ | |
157 | ||
158 | #define TARGET_ABSOLUTE_ABICALLS \ | |
159 | (TARGET_ABICALLS \ | |
160 | && !TARGET_SHARED \ | |
161 | && TARGET_EXPLICIT_RELOCS \ | |
162 | && !ABI_HAS_64BIT_SYMBOLS) | |
163 | ||
c9e1a048 | 164 | /* True if we can optimize sibling calls. For simplicity, we only |
165 | handle cases in which call_insn_operand will reject invalid | |
166 | sibcall addresses. There are two cases in which this isn't true: | |
167 | ||
168 | - TARGET_MIPS16. call_insn_operand accepts constant addresses | |
169 | but there is no direct jump instruction. It isn't worth | |
170 | using sibling calls in this case anyway; they would usually | |
171 | be longer than normal calls. | |
172 | ||
46414626 | 173 | - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand |
174 | accepts global constants, but all sibcalls must be indirect. */ | |
c9e1a048 | 175 | #define TARGET_SIBCALLS \ |
46414626 | 176 | (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) |
177 | ||
178 | /* True if we need to use a global offset table to access some symbols. */ | |
a8a393cb | 179 | #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) |
46414626 | 180 | |
181 | /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ | |
182 | #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) | |
183 | ||
184 | /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ | |
185 | #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) | |
186 | ||
74facf6e | 187 | /* True if we should use .cprestore to store to the cprestore slot. |
188 | ||
189 | We continue to use .cprestore for explicit-reloc code so that JALs | |
190 | inside inline asms will work correctly. */ | |
191 | #define TARGET_CPRESTORE_DIRECTIVE \ | |
192 | (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16) | |
193 | ||
194 | /* True if we can use the J and JAL instructions. */ | |
195 | #define TARGET_ABSOLUTE_JUMPS \ | |
196 | (!flag_pic || TARGET_ABSOLUTE_ABICALLS) | |
197 | ||
a8a393cb | 198 | /* True if indirect calls must use register class PIC_FN_ADDR_REG. |
199 | This is true for both the PIC and non-PIC VxWorks RTP modes. */ | |
200 | #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP) | |
c9e1a048 | 201 | |
5641963c | 202 | /* True if .gpword or .gpdword should be used for switch tables. */ |
4a909f69 | 203 | #define TARGET_GPWORD \ |
5641963c | 204 | (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) |
c9e1a048 | 205 | |
c4cf26ad | 206 | /* True if the output must have a writable .eh_frame. |
207 | See ASM_PREFERRED_EH_DATA_FORMAT for details. */ | |
208 | #ifdef HAVE_LD_PERSONALITY_RELAXATION | |
209 | #define TARGET_WRITABLE_EH_FRAME 0 | |
210 | #else | |
211 | #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED) | |
212 | #endif | |
213 | ||
3e60fdb7 | 214 | /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */ |
215 | #ifdef HAVE_AS_DSPR1_MULT | |
216 | #define ISA_HAS_DSP_MULT ISA_HAS_DSP | |
217 | #else | |
218 | #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2 | |
219 | #endif | |
220 | ||
79c79069 | 221 | /* ISA has LSA available. */ |
74324645 | 222 | #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA) |
79c79069 | 223 | |
224 | /* ISA has DLSA available. */ | |
74324645 | 225 | #define ISA_HAS_DLSA (TARGET_64BIT \ |
226 | && (mips_isa_rev >= 6 \ | |
227 | || ISA_HAS_MSA)) | |
79c79069 | 228 | |
ff9c1bc1 | 229 | /* The ISA compression flags that are currently in effect. */ |
230 | #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS)) | |
231 | ||
d0989c92 | 232 | /* Generate mips16 code */ |
17322e2e | 233 | #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) |
606c99b0 | 234 | /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ |
d0989c92 | 235 | #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) |
0e13e859 | 236 | /* Generate mips16e register save/restore sequences. */ |
237 | #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) | |
4ddcf2b2 | 238 | |
f02776dd | 239 | /* True if we're generating a form of MIPS16 code in which general |
240 | text loads are allowed. */ | |
241 | #define TARGET_MIPS16_TEXT_LOADS \ | |
242 | (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES) | |
243 | ||
244 | /* True if we're generating a form of MIPS16 code in which PC-relative | |
245 | loads are allowed. */ | |
246 | #define TARGET_MIPS16_PCREL_LOADS \ | |
247 | (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) | |
248 | ||
fa2b6990 | 249 | /* Generic ISA defines. */ |
250 | #define ISA_MIPS1 (mips_isa == 1) | |
251 | #define ISA_MIPS2 (mips_isa == 2) | |
252 | #define ISA_MIPS3 (mips_isa == 3) | |
253 | #define ISA_MIPS4 (mips_isa == 4) | |
254 | #define ISA_MIPS32 (mips_isa == 32) | |
a02568c6 | 255 | #define ISA_MIPS32R2 (mips_isa == 33) |
32ac2387 | 256 | #define ISA_MIPS32R3 (mips_isa == 34) |
257 | #define ISA_MIPS32R5 (mips_isa == 36) | |
78645e70 | 258 | #define ISA_MIPS32R6 (mips_isa == 37) |
fa2b6990 | 259 | #define ISA_MIPS64 (mips_isa == 64) |
606c99b0 | 260 | #define ISA_MIPS64R2 (mips_isa == 65) |
32ac2387 | 261 | #define ISA_MIPS64R3 (mips_isa == 66) |
262 | #define ISA_MIPS64R5 (mips_isa == 68) | |
78645e70 | 263 | #define ISA_MIPS64R6 (mips_isa == 69) |
fa2b6990 | 264 | |
08aec1b6 | 265 | /* Architecture target defines. */ |
606c99b0 | 266 | #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) |
267 | #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) | |
268 | #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) | |
b85e9a16 | 269 | #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) |
08aec1b6 | 270 | #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) |
271 | #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) | |
e3759132 | 272 | #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) |
bff47c96 | 273 | #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) |
2857c21b | 274 | #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) |
275 | #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) | |
60b34f30 | 276 | #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900) |
350ddac6 | 277 | #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) |
668de2f7 | 278 | #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000) |
587d2e9a | 279 | #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) |
caa36f1c | 280 | #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ |
f083e315 | 281 | || mips_arch == PROCESSOR_OCTEON2 \ |
282 | || mips_arch == PROCESSOR_OCTEON3) | |
283 | #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \ | |
284 | || mips_arch == PROCESSOR_OCTEON3) | |
2ca4dfa4 | 285 | #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ |
286 | || mips_arch == PROCESSOR_SB1A) | |
2857c21b | 287 | #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) |
974f0a74 | 288 | #define TARGET_XLP (mips_arch == PROCESSOR_XLP) |
08aec1b6 | 289 | |
290 | /* Scheduling target defines. */ | |
606c99b0 | 291 | #define TUNE_20KC (mips_tune == PROCESSOR_20KC) |
292 | #define TUNE_24K (mips_tune == PROCESSOR_24KC \ | |
293 | || mips_tune == PROCESSOR_24KF2_1 \ | |
294 | || mips_tune == PROCESSOR_24KF1_1) | |
295 | #define TUNE_74K (mips_tune == PROCESSOR_74KC \ | |
296 | || mips_tune == PROCESSOR_74KF2_1 \ | |
297 | || mips_tune == PROCESSOR_74KF1_1 \ | |
298 | || mips_tune == PROCESSOR_74KF3_2) | |
299 | #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ | |
300 | || mips_tune == PROCESSOR_LOONGSON_2F) | |
b85e9a16 | 301 | #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) |
34d2ed06 | 302 | #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) |
303 | #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) | |
304 | #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) | |
66e8e04f | 305 | #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) |
306 | #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) | |
34d2ed06 | 307 | #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) |
2857c21b | 308 | #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) |
309 | #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) | |
34d2ed06 | 310 | #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) |
350ddac6 | 311 | #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) |
587d2e9a | 312 | #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) |
caa36f1c | 313 | #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ |
f083e315 | 314 | || mips_tune == PROCESSOR_OCTEON2 \ |
315 | || mips_tune == PROCESSOR_OCTEON3) | |
2ca4dfa4 | 316 | #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ |
317 | || mips_tune == PROCESSOR_SB1A) | |
c3440169 | 318 | #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) |
607f558c | 319 | #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) |
08aec1b6 | 320 | |
9636921b | 321 | /* Whether vector modes and intrinsics for ST Microelectronics |
322 | Loongson-2E/2F processors should be enabled. In o32 pairs of | |
323 | floating-point registers provide 64-bit values. */ | |
324 | #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \ | |
b85e9a16 | 325 | && (TARGET_LOONGSON_2EF \ |
326 | || TARGET_LOONGSON_3A)) | |
9636921b | 327 | |
1a5fa45d | 328 | /* True if the pre-reload scheduler should try to create chains of |
329 | multiply-add or multiply-subtract instructions. For example, | |
330 | suppose we have: | |
331 | ||
332 | t1 = a * b | |
333 | t2 = t1 + c * d | |
92a94cc3 | 334 | t3 = e * f |
335 | t4 = t3 - g * h | |
1a5fa45d | 336 | |
92a94cc3 | 337 | t1 will have a higher priority than t2 and t3 will have a higher |
1a5fa45d | 338 | priority than t4. However, before reload, there is no dependence |
339 | between t1 and t3, and they can often have similar priorities. | |
340 | The scheduler will then tend to prefer: | |
341 | ||
342 | t1 = a * b | |
343 | t3 = e * f | |
344 | t2 = t1 + c * d | |
345 | t4 = t3 - g * h | |
346 | ||
347 | which stops us from making full use of macc/madd-style instructions. | |
348 | This sort of situation occurs frequently in Fourier transforms and | |
349 | in unrolled loops. | |
350 | ||
351 | To counter this, the TUNE_MACC_CHAINS code will reorder the ready | |
352 | queue so that chained multiply-add and multiply-subtract instructions | |
353 | appear ahead of any other instruction that is likely to clobber lo. | |
354 | In the example above, if t2 and t3 become ready at the same time, | |
355 | the code ensures that t2 is scheduled first. | |
356 | ||
357 | Multiply-accumulate instructions are a bigger win for some targets | |
358 | than others, so this macro is defined on an opt-in basis. */ | |
66e8e04f | 359 | #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ |
360 | || TUNE_MIPS4120 \ | |
7f666194 | 361 | || TUNE_MIPS4130 \ |
c3440169 | 362 | || TUNE_24K \ |
363 | || TUNE_P5600) | |
1a5fa45d | 364 | |
93a1903e | 365 | #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) |
c9e1a048 | 366 | #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) |
367 | ||
951d98af | 368 | /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is |
369 | directly accessible, while the command-line options select | |
370 | TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI | |
371 | in use. */ | |
372 | #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) | |
373 | #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) | |
3c367092 | 374 | |
f2b55aea | 375 | /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents |
376 | -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */ | |
377 | #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX) | |
378 | ||
379 | /* TARGET_O32_FP64A_ABI represents all the conditions that form the | |
380 | o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */ | |
381 | #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \ | |
382 | && !TARGET_ODD_SPREG) | |
383 | ||
3c367092 | 384 | /* False if SC acts as a memory barrier with respect to itself, |
385 | otherwise a SYNC will be emitted after SC for atomic operations | |
386 | that require ordering between the SC and following loads and | |
387 | stores. It does not tell anything about ordering of loads and | |
388 | stores prior to and following the SC, only about the SC itself and | |
389 | those loads and stores follow it. */ | |
974f0a74 | 390 | #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP) |
3c367092 | 391 | |
5153cc32 | 392 | /* Define preprocessor macros for the -march and -mtune options. |
393 | PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected | |
394 | processor. If INFO's canonical name is "foo", define PREFIX to | |
395 | be "foo", and define an additional macro PREFIX_FOO. */ | |
396 | #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ | |
397 | do \ | |
398 | { \ | |
399 | char *macro, *p; \ | |
400 | \ | |
401 | macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ | |
402 | for (p = macro; *p != 0; p++) \ | |
fe415b69 | 403 | if (*p == '+') \ |
404 | *p = 'P'; \ | |
405 | else \ | |
406 | *p = TOUPPER (*p); \ | |
5153cc32 | 407 | \ |
408 | builtin_define (macro); \ | |
409 | builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ | |
410 | free (macro); \ | |
411 | } \ | |
412 | while (0) | |
413 | ||
fa2b6990 | 414 | /* Target CPU builtins. */ |
5aeba334 | 415 | #define TARGET_CPU_CPP_BUILTINS() \ |
416 | do \ | |
417 | { \ | |
5641963c | 418 | builtin_assert ("machine=mips"); \ |
5aeba334 | 419 | builtin_assert ("cpu=mips"); \ |
420 | builtin_define ("__mips__"); \ | |
421 | builtin_define ("_mips"); \ | |
422 | \ | |
2baac351 | 423 | /* We do this here because __mips is defined below and so we \ |
424 | can't use builtin_define_std. We don't ever want to define \ | |
425 | "mips" for VxWorks because some of the VxWorks headers \ | |
426 | construct include filenames from a root directory macro, \ | |
427 | an architecture macro and a filename, where the architecture \ | |
428 | macro expands to 'mips'. If we define 'mips' to 1, the \ | |
429 | architecture macro expands to 1 as well. */ \ | |
430 | if (!flag_iso && !TARGET_VXWORKS) \ | |
5aeba334 | 431 | builtin_define ("mips"); \ |
432 | \ | |
433 | if (TARGET_64BIT) \ | |
434 | builtin_define ("__mips64"); \ | |
435 | \ | |
5641963c | 436 | /* Treat _R3000 and _R4000 like register-size \ |
437 | defines, which is how they've historically \ | |
438 | been used. */ \ | |
439 | if (TARGET_64BIT) \ | |
5aeba334 | 440 | { \ |
5641963c | 441 | builtin_define_std ("R4000"); \ |
442 | builtin_define ("_R4000"); \ | |
443 | } \ | |
444 | else \ | |
445 | { \ | |
446 | builtin_define_std ("R3000"); \ | |
447 | builtin_define ("_R3000"); \ | |
5aeba334 | 448 | } \ |
5641963c | 449 | \ |
5aeba334 | 450 | if (TARGET_FLOAT64) \ |
451 | builtin_define ("__mips_fpr=64"); \ | |
f2b55aea | 452 | else if (TARGET_FLOATXX) \ |
453 | builtin_define ("__mips_fpr=0"); \ | |
5aeba334 | 454 | else \ |
455 | builtin_define ("__mips_fpr=32"); \ | |
456 | \ | |
ff9c1bc1 | 457 | if (mips_base_compression_flags & MASK_MIPS16) \ |
5aeba334 | 458 | builtin_define ("__mips16"); \ |
459 | \ | |
460 | if (TARGET_MIPS3D) \ | |
461 | builtin_define ("__mips3d"); \ | |
462 | \ | |
463 | if (TARGET_SMARTMIPS) \ | |
464 | builtin_define ("__mips_smartmips"); \ | |
465 | \ | |
ff9c1bc1 | 466 | if (mips_base_compression_flags & MASK_MICROMIPS) \ |
467 | builtin_define ("__mips_micromips"); \ | |
468 | \ | |
e876044e | 469 | if (TARGET_MCU) \ |
470 | builtin_define ("__mips_mcu"); \ | |
471 | \ | |
3721f3a0 | 472 | if (TARGET_EVA) \ |
473 | builtin_define ("__mips_eva"); \ | |
474 | \ | |
5aeba334 | 475 | if (TARGET_DSP) \ |
476 | { \ | |
477 | builtin_define ("__mips_dsp"); \ | |
478 | if (TARGET_DSPR2) \ | |
479 | { \ | |
480 | builtin_define ("__mips_dspr2"); \ | |
481 | builtin_define ("__mips_dsp_rev=2"); \ | |
482 | } \ | |
483 | else \ | |
484 | builtin_define ("__mips_dsp_rev=1"); \ | |
485 | } \ | |
486 | \ | |
ddc6405a | 487 | if (ISA_HAS_MSA) \ |
488 | { \ | |
489 | builtin_define ("__mips_msa"); \ | |
490 | builtin_define ("__mips_msa_width=128"); \ | |
491 | } \ | |
492 | \ | |
5aeba334 | 493 | MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ |
494 | MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ | |
495 | \ | |
496 | if (ISA_MIPS1) \ | |
497 | { \ | |
498 | builtin_define ("__mips=1"); \ | |
499 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ | |
500 | } \ | |
501 | else if (ISA_MIPS2) \ | |
502 | { \ | |
503 | builtin_define ("__mips=2"); \ | |
504 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ | |
505 | } \ | |
506 | else if (ISA_MIPS3) \ | |
507 | { \ | |
508 | builtin_define ("__mips=3"); \ | |
509 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ | |
510 | } \ | |
511 | else if (ISA_MIPS4) \ | |
512 | { \ | |
513 | builtin_define ("__mips=4"); \ | |
514 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ | |
515 | } \ | |
78645e70 | 516 | else if (mips_isa >= 32 && mips_isa < 64) \ |
5aeba334 | 517 | { \ |
518 | builtin_define ("__mips=32"); \ | |
5aeba334 | 519 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ |
520 | } \ | |
78645e70 | 521 | else if (mips_isa >= 64) \ |
32ac2387 | 522 | { \ |
523 | builtin_define ("__mips=64"); \ | |
524 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ | |
525 | } \ | |
95faea77 | 526 | if (mips_isa_rev > 0) \ |
527 | builtin_define_with_int_value ("__mips_isa_rev", \ | |
528 | mips_isa_rev); \ | |
5aeba334 | 529 | \ |
530 | switch (mips_abi) \ | |
531 | { \ | |
532 | case ABI_32: \ | |
533 | builtin_define ("_ABIO32=1"); \ | |
534 | builtin_define ("_MIPS_SIM=_ABIO32"); \ | |
535 | break; \ | |
536 | \ | |
537 | case ABI_N32: \ | |
538 | builtin_define ("_ABIN32=2"); \ | |
539 | builtin_define ("_MIPS_SIM=_ABIN32"); \ | |
540 | break; \ | |
541 | \ | |
542 | case ABI_64: \ | |
543 | builtin_define ("_ABI64=3"); \ | |
544 | builtin_define ("_MIPS_SIM=_ABI64"); \ | |
545 | break; \ | |
546 | \ | |
547 | case ABI_O64: \ | |
548 | builtin_define ("_ABIO64=4"); \ | |
549 | builtin_define ("_MIPS_SIM=_ABIO64"); \ | |
550 | break; \ | |
551 | } \ | |
552 | \ | |
553 | builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \ | |
554 | builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \ | |
555 | builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \ | |
556 | builtin_define_with_int_value ("_MIPS_FPSET", \ | |
557 | 32 / MAX_FPRS_PER_FMT); \ | |
f2b55aea | 558 | builtin_define_with_int_value ("_MIPS_SPFPSET", \ |
559 | TARGET_ODD_SPREG ? 32 : 16); \ | |
5aeba334 | 560 | \ |
561 | /* These defines reflect the ABI in use, not whether the \ | |
562 | FPU is directly accessible. */ \ | |
27a909cf | 563 | if (TARGET_NO_FLOAT) \ |
564 | builtin_define ("__mips_no_float"); \ | |
565 | else if (TARGET_HARD_FLOAT_ABI) \ | |
5aeba334 | 566 | builtin_define ("__mips_hard_float"); \ |
567 | else \ | |
568 | builtin_define ("__mips_soft_float"); \ | |
569 | \ | |
570 | if (TARGET_SINGLE_FLOAT) \ | |
571 | builtin_define ("__mips_single_float"); \ | |
572 | \ | |
573 | if (TARGET_PAIRED_SINGLE_FLOAT) \ | |
574 | builtin_define ("__mips_paired_single_float"); \ | |
575 | \ | |
0bd32132 | 576 | if (mips_abs == MIPS_IEEE_754_2008) \ |
577 | builtin_define ("__mips_abs2008"); \ | |
578 | \ | |
579 | if (mips_nan == MIPS_IEEE_754_2008) \ | |
580 | builtin_define ("__mips_nan2008"); \ | |
581 | \ | |
5aeba334 | 582 | if (TARGET_BIG_ENDIAN) \ |
583 | { \ | |
584 | builtin_define_std ("MIPSEB"); \ | |
585 | builtin_define ("_MIPSEB"); \ | |
586 | } \ | |
587 | else \ | |
588 | { \ | |
589 | builtin_define_std ("MIPSEL"); \ | |
590 | builtin_define ("_MIPSEL"); \ | |
591 | } \ | |
9636921b | 592 | \ |
87c85492 | 593 | /* Whether calls should go through $25. The separate __PIC__ \ |
594 | macro indicates whether abicalls code might use a GOT. */ \ | |
595 | if (TARGET_ABICALLS) \ | |
596 | builtin_define ("__mips_abicalls"); \ | |
597 | \ | |
9636921b | 598 | /* Whether Loongson vector modes are enabled. */ \ |
599 | if (TARGET_LOONGSON_VECTORS) \ | |
600 | builtin_define ("__mips_loongson_vector_rev"); \ | |
5aeba334 | 601 | \ |
fc84efeb | 602 | /* Historical Octeon macro. */ \ |
603 | if (TARGET_OCTEON) \ | |
604 | builtin_define ("__OCTEON__"); \ | |
605 | \ | |
164f4c55 | 606 | if (TARGET_SYNCI) \ |
607 | builtin_define ("__mips_synci"); \ | |
608 | \ | |
5aeba334 | 609 | /* Macros dependent on the C dialect. */ \ |
610 | if (preprocessing_asm_p ()) \ | |
611 | { \ | |
612 | builtin_define_std ("LANGUAGE_ASSEMBLY"); \ | |
613 | builtin_define ("_LANGUAGE_ASSEMBLY"); \ | |
614 | } \ | |
615 | else if (c_dialect_cxx ()) \ | |
616 | { \ | |
617 | builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ | |
618 | builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ | |
619 | builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ | |
620 | } \ | |
621 | else \ | |
622 | { \ | |
623 | builtin_define_std ("LANGUAGE_C"); \ | |
624 | builtin_define ("_LANGUAGE_C"); \ | |
625 | } \ | |
626 | if (c_dialect_objc ()) \ | |
627 | { \ | |
628 | builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ | |
629 | builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ | |
5641963c | 630 | /* Bizarre, but retained for backwards compatibility. */ \ |
5aeba334 | 631 | builtin_define_std ("LANGUAGE_C"); \ |
632 | builtin_define ("_LANGUAGE_C"); \ | |
633 | } \ | |
634 | \ | |
635 | if (mips_abi == ABI_EABI) \ | |
636 | builtin_define ("__mips_eabi"); \ | |
f5ec18cc | 637 | \ |
638 | if (TARGET_CACHE_BUILTIN) \ | |
639 | builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ | |
fccc4b54 | 640 | if (!ISA_HAS_LXC1_SXC1) \ |
641 | builtin_define ("__mips_no_lxc1_sxc1"); \ | |
eb5c0cb6 | 642 | if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \ |
643 | builtin_define ("__mips_no_madd4"); \ | |
5aeba334 | 644 | } \ |
645 | while (0) | |
fa2b6990 | 646 | |
1656cc5c | 647 | /* Default target_flags if no switches are specified */ |
648 | ||
649 | #ifndef TARGET_DEFAULT | |
650 | #define TARGET_DEFAULT 0 | |
651 | #endif | |
652 | ||
e7a21b43 | 653 | #ifndef TARGET_CPU_DEFAULT |
654 | #define TARGET_CPU_DEFAULT 0 | |
655 | #endif | |
656 | ||
5a5f5a9c | 657 | #ifndef TARGET_ENDIAN_DEFAULT |
5a5f5a9c | 658 | #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN |
5a5f5a9c | 659 | #endif |
660 | ||
cf378360 | 661 | #ifdef IN_LIBGCC2 |
662 | #undef TARGET_64BIT | |
663 | /* Make this compile time constant for libgcc2 */ | |
664 | #ifdef __mips64 | |
665 | #define TARGET_64BIT 1 | |
666 | #else | |
667 | #define TARGET_64BIT 0 | |
668 | #endif | |
e94b904f | 669 | #endif /* IN_LIBGCC2 */ |
cf378360 | 670 | |
07e0e650 | 671 | /* Force the call stack unwinders in unwind.inc not to be MIPS16 code |
672 | when compiled with hardware floating point. This is because MIPS16 | |
673 | code cannot save and restore the floating-point registers, which is | |
674 | important if in a mixed MIPS16/non-MIPS16 environment. */ | |
675 | ||
676 | #ifdef IN_LIBGCC2 | |
677 | #if __mips_hard_float | |
678 | #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__)) | |
679 | #endif | |
680 | #endif /* IN_LIBGCC2 */ | |
681 | ||
91e8ab5c | 682 | #define TARGET_LIBGCC_SDATA_SECTION ".sdata" |
683 | ||
d7f27604 | 684 | #ifndef MULTILIB_ENDIAN_DEFAULT |
340eaec8 | 685 | #if TARGET_ENDIAN_DEFAULT == 0 |
d7f27604 | 686 | #define MULTILIB_ENDIAN_DEFAULT "EL" |
340eaec8 | 687 | #else |
d7f27604 | 688 | #define MULTILIB_ENDIAN_DEFAULT "EB" |
689 | #endif | |
340eaec8 | 690 | #endif |
d7f27604 | 691 | |
13823aa8 | 692 | #ifndef MULTILIB_ISA_DEFAULT |
e0462563 | 693 | #if MIPS_ISA_DEFAULT == 1 |
694 | #define MULTILIB_ISA_DEFAULT "mips1" | |
695 | #elif MIPS_ISA_DEFAULT == 2 | |
696 | #define MULTILIB_ISA_DEFAULT "mips2" | |
697 | #elif MIPS_ISA_DEFAULT == 3 | |
698 | #define MULTILIB_ISA_DEFAULT "mips3" | |
699 | #elif MIPS_ISA_DEFAULT == 4 | |
700 | #define MULTILIB_ISA_DEFAULT "mips4" | |
701 | #elif MIPS_ISA_DEFAULT == 32 | |
702 | #define MULTILIB_ISA_DEFAULT "mips32" | |
703 | #elif MIPS_ISA_DEFAULT == 33 | |
704 | #define MULTILIB_ISA_DEFAULT "mips32r2" | |
78645e70 | 705 | #elif MIPS_ISA_DEFAULT == 37 |
706 | #define MULTILIB_ISA_DEFAULT "mips32r6" | |
e0462563 | 707 | #elif MIPS_ISA_DEFAULT == 64 |
708 | #define MULTILIB_ISA_DEFAULT "mips64" | |
709 | #elif MIPS_ISA_DEFAULT == 65 | |
710 | #define MULTILIB_ISA_DEFAULT "mips64r2" | |
78645e70 | 711 | #elif MIPS_ISA_DEFAULT == 69 |
712 | #define MULTILIB_ISA_DEFAULT "mips64r6" | |
e0462563 | 713 | #else |
714 | #define MULTILIB_ISA_DEFAULT "mips1" | |
715 | #endif | |
13823aa8 | 716 | #endif |
717 | ||
38c0064e | 718 | #ifndef MIPS_ABI_DEFAULT |
719 | #define MIPS_ABI_DEFAULT ABI_32 | |
720 | #endif | |
721 | ||
722 | /* Use the most portable ABI flag for the ASM specs. */ | |
723 | ||
724 | #if MIPS_ABI_DEFAULT == ABI_32 | |
725 | #define MULTILIB_ABI_DEFAULT "mabi=32" | |
e0462563 | 726 | #elif MIPS_ABI_DEFAULT == ABI_O64 |
38c0064e | 727 | #define MULTILIB_ABI_DEFAULT "mabi=o64" |
e0462563 | 728 | #elif MIPS_ABI_DEFAULT == ABI_N32 |
38c0064e | 729 | #define MULTILIB_ABI_DEFAULT "mabi=n32" |
e0462563 | 730 | #elif MIPS_ABI_DEFAULT == ABI_64 |
38c0064e | 731 | #define MULTILIB_ABI_DEFAULT "mabi=64" |
e0462563 | 732 | #elif MIPS_ABI_DEFAULT == ABI_EABI |
38c0064e | 733 | #define MULTILIB_ABI_DEFAULT "mabi=eabi" |
734 | #endif | |
735 | ||
d7f27604 | 736 | #ifndef MULTILIB_DEFAULTS |
5153cc32 | 737 | #define MULTILIB_DEFAULTS \ |
738 | { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } | |
340eaec8 | 739 | #endif |
740 | ||
514d8465 | 741 | /* We must pass -EL to the linker by default for little endian embedded |
742 | targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the | |
743 | linker will default to using big-endian output files. The OUTPUT_FORMAT | |
744 | line must be in the linker script, otherwise -EB/-EL will not work. */ | |
745 | ||
fb9d1677 | 746 | #ifndef ENDIAN_SPEC |
514d8465 | 747 | #if TARGET_ENDIAN_DEFAULT == 0 |
557acce7 | 748 | #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" |
514d8465 | 749 | #else |
557acce7 | 750 | #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" |
514d8465 | 751 | #endif |
752 | #endif | |
753 | ||
7583e786 | 754 | /* A spec condition that matches all non-mips16 -mips arguments. */ |
755 | ||
756 | #define MIPS_ISA_LEVEL_OPTION_SPEC \ | |
757 | "mips1|mips2|mips3|mips4|mips32*|mips64*" | |
758 | ||
759 | /* A spec condition that matches all non-mips16 architecture arguments. */ | |
760 | ||
761 | #define MIPS_ARCH_OPTION_SPEC \ | |
762 | MIPS_ISA_LEVEL_OPTION_SPEC "|march=*" | |
763 | ||
c1fe1a98 | 764 | /* A spec that infers a -mips argument from an -march argument. */ |
7583e786 | 765 | |
766 | #define MIPS_ISA_LEVEL_SPEC \ | |
767 | "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ | |
768 | %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ | |
769 | %{march=mips2|march=r6000:-mips2} \ | |
e07ac3b5 | 770 | %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ |
271ed4b0 | 771 | %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ |
772 | |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \ | |
7b50aae4 | 773 | %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ |
774 | %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ | |
606d0d6e | 775 | |march=34k*|march=74k*|march=m14k*|march=1004k* \ |
776 | |march=interaptiv: -mips32r2} \ | |
32ac2387 | 777 | %{march=mips32r3: -mips32r3} \ |
68fb4349 | 778 | %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ |
78645e70 | 779 | %{march=mips32r6: -mips32r6} \ |
eb91c01f | 780 | %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |
2158068e | 781 | |march=xlr: -mips64} \ |
782 | %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ | |
32ac2387 | 783 | %{march=mips64r3: -mips64r3} \ |
784 | %{march=mips64r5: -mips64r5} \ | |
607f558c | 785 | %{march=mips64r6|march=i6400: -mips64r6}}" |
c1fe1a98 | 786 | |
787 | /* A spec that injects the default multilib ISA if no architecture is | |
788 | specified. */ | |
789 | ||
790 | #define MIPS_DEFAULT_ISA_LEVEL_SPEC \ | |
791 | "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ | |
5aeba334 | 792 | %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" |
793 | ||
7938ee8c | 794 | /* A spec that infers a -mhard-float or -msoft-float setting from an |
795 | -march argument. Note that soft-float and hard-float code are not | |
796 | link-compatible. */ | |
797 | ||
798 | #define MIPS_ARCH_FLOAT_SPEC \ | |
e931fbeb | 799 | "%{mhard-float|msoft-float|mno-float|march=mips*:; \ |
7938ee8c | 800 | march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ |
8dcd4f26 | 801 | |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ |
68fb4349 | 802 | |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \ |
7938ee8c | 803 | march=*: -mhard-float}" |
804 | ||
5aeba334 | 805 | /* A spec condition that matches 32-bit options. It only works if |
806 | MIPS_ISA_LEVEL_SPEC has been applied. */ | |
807 | ||
808 | #define MIPS_32BIT_OPTION_SPEC \ | |
809 | "mips1|mips2|mips32*|mgp32" | |
7583e786 | 810 | |
f2b55aea | 811 | /* A spec condition that matches architectures should be targeted with |
812 | o32 FPXX for compatibility reasons. */ | |
813 | #define MIPS_FPXX_OPTION_SPEC \ | |
814 | "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \ | |
815 | mips64|mips64r2|mips64r3|mips64r5" | |
816 | ||
32108f3d | 817 | /* Infer a -msynci setting from a -mips argument, on the assumption that |
818 | -msynci is desired where possible. */ | |
819 | #define MIPS_ISA_SYNCI_SPEC \ | |
78645e70 | 820 | "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \ |
821 | |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}" | |
822 | ||
c1fe1a98 | 823 | /* Infer a -mnan=2008 setting from a -mips argument. */ |
78645e70 | 824 | #define MIPS_ISA_NAN2008_SPEC \ |
68fb4349 | 825 | "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \ |
826 | %{!msoft-float:-mnan=2008}}" | |
32108f3d | 827 | |
e0462563 | 828 | #if (MIPS_ABI_DEFAULT == ABI_O64 \ |
829 | || MIPS_ABI_DEFAULT == ABI_N32 \ | |
830 | || MIPS_ABI_DEFAULT == ABI_64) | |
38c0064e | 831 | #define OPT_ARCH64 "mabi=32|mgp32:;" |
832 | #define OPT_ARCH32 "mabi=32|mgp32" | |
833 | #else | |
834 | #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64" | |
835 | #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;" | |
836 | #endif | |
837 | ||
7dd97ab6 | 838 | /* Support for a compile-time default CPU, et cetera. The rules are: |
839 | --with-arch is ignored if -march is specified or a -mips is specified | |
38c0064e | 840 | (other than -mips16); likewise --with-arch-32 and --with-arch-64. |
841 | --with-tune is ignored if -mtune is specified; likewise | |
842 | --with-tune-32 and --with-tune-64. | |
7dd97ab6 | 843 | --with-abi is ignored if -mabi is specified. |
844 | --with-float is ignored if -mhard-float or -msoft-float are | |
f9262d1e | 845 | specified. |
f2b55aea | 846 | --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are |
847 | specified. | |
0bd32132 | 848 | --with-nan is ignored if -mnan is specified. |
ddc6405a | 849 | --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are |
850 | specified. | |
f2b55aea | 851 | --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg |
852 | or -mno-odd-spreg are specified. | |
f9262d1e | 853 | --with-divide is ignored if -mdivide-traps or -mdivide-breaks are |
854 | specified. */ | |
7dd97ab6 | 855 | #define OPTION_DEFAULT_SPECS \ |
7583e786 | 856 | {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \ |
38c0064e | 857 | {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ |
858 | {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ | |
7dd97ab6 | 859 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ |
38c0064e | 860 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ |
861 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
7dd97ab6 | 862 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ |
f9262d1e | 863 | {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ |
f2b55aea | 864 | {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \ |
0bd32132 | 865 | {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \ |
f2b55aea | 866 | {"fp_32", "%{" OPT_ARCH32 \ |
ddc6405a | 867 | ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \ |
f2b55aea | 868 | {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \ |
869 | "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \ | |
bc4c18f7 | 870 | {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ |
4a909f69 | 871 | {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ |
1af9587c | 872 | {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ |
fccc4b54 | 873 | {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ |
eb5c0cb6 | 874 | {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \ |
875 | {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \ | |
f9262d1e | 876 | |
c1fe1a98 | 877 | /* A spec that infers the: |
878 | -mnan=2008 setting from a -mips argument, | |
879 | -mdsp setting from a -march argument. */ | |
4e6c8c3b | 880 | #define BASE_DRIVER_SELF_SPECS \ |
78645e70 | 881 | MIPS_ISA_NAN2008_SPEC, \ |
86a6a456 | 882 | "%{!mno-dsp: \ |
606d0d6e | 883 | %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \ |
884 | |march=interaptiv: -mdsp} \ | |
351a64c5 | 885 | %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" |
4e6c8c3b | 886 | |
78645e70 | 887 | #define DRIVER_SELF_SPECS \ |
888 | MIPS_ISA_LEVEL_SPEC, \ | |
889 | BASE_DRIVER_SELF_SPECS | |
4e6c8c3b | 890 | |
f9262d1e | 891 | #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ |
892 | && ISA_HAS_COND_TRAP) | |
7dd97ab6 | 893 | |
6b65ee54 | 894 | #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16) |
44333ad0 | 895 | |
5153cc32 | 896 | /* True if the ABI can only work with 64-bit integer registers. We |
897 | generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but | |
898 | otherwise floating-point registers must also be 64-bit. */ | |
93a1903e | 899 | #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) |
5153cc32 | 900 | |
901 | /* Likewise for 32-bit regs. */ | |
902 | #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) | |
903 | ||
0a959c1d | 904 | /* True if the file format uses 64-bit symbols. At present, this is |
905 | only true for n64, which uses 64-bit ELF. */ | |
906 | #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64) | |
907 | ||
908 | /* True if symbols are 64 bits wide. This is usually determined by | |
909 | the ABI's file format, but it can be overridden by -msym32. Note that | |
910 | overriding the size with -msym32 changes the ABI of relocatable objects, | |
911 | although it doesn't change the ABI of a fully-linked object. */ | |
9d81057b | 912 | #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \ |
913 | && Pmode == DImode \ | |
914 | && !TARGET_SYM32) | |
c9e1a048 | 915 | |
c910419d | 916 | /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ |
d2f64a9e | 917 | #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ |
918 | || ISA_MIPS4 \ | |
606c99b0 | 919 | || ISA_MIPS64 \ |
32ac2387 | 920 | || ISA_MIPS64R2 \ |
921 | || ISA_MIPS64R3 \ | |
78645e70 | 922 | || ISA_MIPS64R5 \ |
923 | || ISA_MIPS64R6) | |
924 | ||
925 | #define ISA_HAS_JR (mips_isa_rev <= 5) | |
3edb38b8 | 926 | |
59449ca9 | 927 | #define ISA_HAS_DELAY_SLOTS 1 |
928 | ||
929 | #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6) | |
930 | ||
a361b456 | 931 | /* ISA has branch likely instructions (e.g. mips2). */ |
08aec1b6 | 932 | /* Disable branchlikely for tx39 until compare rewrite. They haven't |
933 | been generated up to this point. */ | |
78645e70 | 934 | #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5) |
3edb38b8 | 935 | |
f2b55aea | 936 | /* ISA has 32 single-precision registers. */ |
937 | #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ | |
938 | && !TARGET_LOONGSON_3A) \ | |
939 | || TARGET_FLOAT64 \ | |
940 | || TARGET_MIPS5900) | |
941 | ||
fa7637bd | 942 | /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */ |
425e1c96 | 943 | #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ |
944 | || TARGET_MIPS5400 \ | |
945 | || TARGET_MIPS5500 \ | |
0b4e9fcd | 946 | || TARGET_MIPS5900 \ |
425e1c96 | 947 | || TARGET_MIPS7000 \ |
948 | || TARGET_MIPS9000 \ | |
949 | || TARGET_MAD \ | |
78645e70 | 950 | || (mips_isa_rev >= 1 \ |
951 | && mips_isa_rev <= 5)) \ | |
425e1c96 | 952 | && !TARGET_MIPS16) |
953 | ||
9c6a9ea0 | 954 | /* ISA has a three-operand multiplication instruction. */ |
0118f95f | 955 | #define ISA_HAS_DMUL3 (TARGET_64BIT \ |
956 | && TARGET_OCTEON \ | |
957 | && !TARGET_MIPS16) | |
9c6a9ea0 | 958 | |
78645e70 | 959 | /* ISA has HI and LO registers. */ |
960 | #define ISA_HAS_HILO (mips_isa_rev <= 5) | |
961 | ||
0b4e9fcd | 962 | /* ISA supports instructions DMULT and DMULTU. */ |
78645e70 | 963 | #define ISA_HAS_DMULT (TARGET_64BIT \ |
964 | && !TARGET_MIPS5900 \ | |
965 | && mips_isa_rev <= 5) | |
0b4e9fcd | 966 | |
78645e70 | 967 | /* ISA supports instructions MULT and MULTU. */ |
968 | #define ISA_HAS_MULT (mips_isa_rev <= 5) | |
969 | ||
970 | /* ISA supports instructions MUL, MULU, MUH, MUHU. */ | |
971 | #define ISA_HAS_R6MUL (mips_isa_rev >= 6) | |
972 | ||
973 | /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */ | |
974 | #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6) | |
0b4e9fcd | 975 | |
5e08e6c7 | 976 | /* For Loongson, it is preferable to use the Loongson-specific division and |
977 | modulo instructions instead of the regular (D)DIV(U) instruction, | |
978 | because the former are faster and can also have the effect of reducing | |
979 | code size. */ | |
980 | #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ | |
981 | || TARGET_LOONGSON_3A) \ | |
982 | && !TARGET_MIPS16) | |
983 | ||
0b4e9fcd | 984 | /* ISA supports instructions DDIV and DDIVU. */ |
78645e70 | 985 | #define ISA_HAS_DDIV (TARGET_64BIT \ |
986 | && !TARGET_MIPS5900 \ | |
5e08e6c7 | 987 | && !ISA_AVOID_DIV_HILO \ |
78645e70 | 988 | && mips_isa_rev <= 5) |
0b4e9fcd | 989 | |
990 | /* ISA supports instructions DIV and DIVU. | |
991 | This is always true, but the macro is needed for ISA_HAS_<D>DIV | |
992 | in mips.md. */ | |
5e08e6c7 | 993 | #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \ |
994 | && mips_isa_rev <= 5) | |
e0462563 | 995 | |
78645e70 | 996 | /* ISA supports instructions DIV, DIVU, MOD and MODU. */ |
997 | #define ISA_HAS_R6DIV (mips_isa_rev >= 6) | |
998 | ||
999 | /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */ | |
1000 | #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6) | |
1001 | ||
d598f4ff | 1002 | /* ISA has the floating-point conditional move instructions introduced |
1003 | in mips4. */ | |
1004 | #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ | |
78645e70 | 1005 | || (mips_isa_rev >= 1 \ |
1006 | && mips_isa_rev <= 5)) \ | |
425e1c96 | 1007 | && !TARGET_MIPS5500 \ |
fa2b6990 | 1008 | && !TARGET_MIPS16) |
2cec2f38 | 1009 | |
d598f4ff | 1010 | /* ISA has the integer conditional move instructions introduced in mips4 and |
1011 | ST Loongson 2E/2F. */ | |
60b34f30 | 1012 | #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ |
1013 | || TARGET_MIPS5900 \ | |
1014 | || TARGET_LOONGSON_2EF) | |
d598f4ff | 1015 | |
36a24c97 | 1016 | /* ISA has LDC1 and SDC1. */ |
394563b3 | 1017 | #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \ |
1018 | && !TARGET_MIPS5900 \ | |
1019 | && !TARGET_MIPS16) | |
36a24c97 | 1020 | |
2cec2f38 | 1021 | /* ISA has the mips4 FP condition code instructions: FP-compare to CC, |
00f58f47 | 1022 | branch on CC, and move (both FP and non-FP) on CC. */ |
78645e70 | 1023 | #define ISA_HAS_8CC (ISA_MIPS4 \ |
1024 | || (mips_isa_rev >= 1 \ | |
1025 | && mips_isa_rev <= 5)) | |
1026 | ||
1027 | /* ISA has the FP condition code instructions that store the flag in an | |
1028 | FP register. */ | |
1029 | #define ISA_HAS_CCF (mips_isa_rev >= 6) | |
1030 | ||
1031 | #define ISA_HAS_SEL (mips_isa_rev >= 6) | |
2cec2f38 | 1032 | |
e0820f9b | 1033 | /* This is a catch all for other mips4 instructions: indexed load, the |
1034 | FP madd and msub instructions, and the FP recip and recip sqrt | |
75be7a44 | 1035 | instructions. Note that this macro should only be used by other |
1036 | ISA_HAS_* macros. */ | |
425e1c96 | 1037 | #define ISA_HAS_FP4 ((ISA_MIPS4 \ |
606c99b0 | 1038 | || ISA_MIPS64 \ |
78645e70 | 1039 | || (mips_isa_rev >= 2 \ |
1040 | && mips_isa_rev <= 5)) \ | |
425e1c96 | 1041 | && !TARGET_MIPS16) |
2cec2f38 | 1042 | |
75be7a44 | 1043 | /* ISA has floating-point indexed load and store instructions |
1044 | (LWXC1, LDXC1, SWXC1 and SDXC1). */ | |
fccc4b54 | 1045 | #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ |
1046 | && mips_lxc1_sxc1) | |
75be7a44 | 1047 | |
07a96917 | 1048 | /* ISA has paired-single instructions. */ |
81d49cc1 | 1049 | #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ |
1050 | || (mips_isa_rev >= 2 \ | |
1051 | && mips_isa_rev <= 5)) \ | |
1052 | && !TARGET_OCTEON) | |
07a96917 | 1053 | |
ea98ee52 | 1054 | /* ISA has conditional trap instructions. */ |
fa2b6990 | 1055 | #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ |
1056 | && !TARGET_MIPS16) | |
3edb38b8 | 1057 | |
78645e70 | 1058 | /* ISA has conditional trap with immediate instructions. */ |
1059 | #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \ | |
1060 | && mips_isa_rev <= 5 \ | |
1061 | && !TARGET_MIPS16) | |
1062 | ||
d8c4db28 | 1063 | /* ISA has integer multiply-accumulate instructions, madd and msub. */ |
78645e70 | 1064 | #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \ |
1065 | && mips_isa_rev <= 5) | |
582b17a6 | 1066 | |
11b70d7d | 1067 | /* Integer multiply-accumulate instructions should be generated. */ |
14844884 | 1068 | #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) |
11b70d7d | 1069 | |
668de2f7 | 1070 | /* ISA has 4 operand fused madd instructions of the form |
1071 | 'd = [+-] (a * b [+-] c)'. */ | |
eb5c0cb6 | 1072 | #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ |
1073 | && (TARGET_MIPS8000 \ | |
1074 | || TARGET_LOONGSON_3A)) | |
d598f4ff | 1075 | |
668de2f7 | 1076 | /* ISA has 4 operand unfused madd instructions of the form |
1077 | 'd = [+-] (a * b [+-] c)'. */ | |
eb5c0cb6 | 1078 | #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ |
1079 | && ISA_HAS_FP4 \ | |
04877b8f | 1080 | && !TARGET_MIPS8000 \ |
1081 | && !TARGET_LOONGSON_3A) | |
78645e70 | 1082 | |
668de2f7 | 1083 | /* ISA has 3 operand r6 fused madd instructions of the form |
1084 | 'c = c [+-] (a * b)'. */ | |
1085 | #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6) | |
d598f4ff | 1086 | |
668de2f7 | 1087 | /* ISA has 3 operand loongson fused madd instructions of the form |
1088 | 'c = [+-] (a * b [+-] c)'. */ | |
1089 | #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF | |
d598f4ff | 1090 | |
385361c9 | 1091 | /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The |
1092 | MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when | |
1093 | doubles are stored in pairs of FPRs, so for safety's sake, we apply | |
1094 | this restriction to the MIPS IV ISA too. */ | |
1095 | #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ | |
75be7a44 | 1096 | (((ISA_HAS_FP4 \ |
385361c9 | 1097 | && ((MODE) == SFmode \ |
1098 | || ((TARGET_FLOAT64 \ | |
95faea77 | 1099 | || mips_isa_rev >= 2) \ |
385361c9 | 1100 | && (MODE) == DFmode))) \ |
78645e70 | 1101 | || (((MODE) == SFmode \ |
1102 | || (MODE) == DFmode) \ | |
1103 | && (mips_isa_rev >= 6)) \ | |
385361c9 | 1104 | || (TARGET_SB1 \ |
1105 | && (MODE) == V2SFmode)) \ | |
1106 | && !TARGET_MIPS16) | |
1107 | ||
78645e70 | 1108 | #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) |
1109 | ||
1110 | #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) | |
1111 | ||
1112 | #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2) | |
1113 | ||
582b17a6 | 1114 | /* ISA has count leading zeroes/ones instruction (not implemented). */ |
95faea77 | 1115 | #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) |
582b17a6 | 1116 | |
2857c21b | 1117 | /* ISA has three operand multiply instructions that put |
1118 | the high part in an accumulator: mulhi or mulhiu. */ | |
425e1c96 | 1119 | #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ |
1120 | || TARGET_MIPS5500 \ | |
1121 | || TARGET_SR71K) \ | |
1122 | && !TARGET_MIPS16) | |
2857c21b | 1123 | |
512f12d6 | 1124 | /* ISA has three operand multiply instructions that negate the |
1125 | result and put the result in an accumulator. */ | |
425e1c96 | 1126 | #define ISA_HAS_MULS ((TARGET_MIPS5400 \ |
1127 | || TARGET_MIPS5500 \ | |
1128 | || TARGET_SR71K) \ | |
1129 | && !TARGET_MIPS16) | |
2857c21b | 1130 | |
512f12d6 | 1131 | /* ISA has three operand multiply instructions that subtract the |
1132 | result from a 4th operand and put the result in an accumulator. */ | |
425e1c96 | 1133 | #define ISA_HAS_MSAC ((TARGET_MIPS5400 \ |
1134 | || TARGET_MIPS5500 \ | |
1135 | || TARGET_SR71K) \ | |
1136 | && !TARGET_MIPS16) | |
1137 | ||
512f12d6 | 1138 | /* ISA has three operand multiply instructions that add the result |
1139 | to a 4th operand and put the result in an accumulator. */ | |
425e1c96 | 1140 | #define ISA_HAS_MACC ((TARGET_MIPS4120 \ |
1141 | || TARGET_MIPS4130 \ | |
1142 | || TARGET_MIPS5400 \ | |
1143 | || TARGET_MIPS5500 \ | |
1144 | || TARGET_SR71K) \ | |
1145 | && !TARGET_MIPS16) | |
2857c21b | 1146 | |
b6586786 | 1147 | /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ |
425e1c96 | 1148 | #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ |
1149 | || TARGET_MIPS4130) \ | |
1150 | && !TARGET_MIPS16) | |
1151 | ||
1152 | /* ISA has the "ror" (rotate right) instructions. */ | |
95faea77 | 1153 | #define ISA_HAS_ROR ((mips_isa_rev >= 2 \ |
425e1c96 | 1154 | || TARGET_MIPS5400 \ |
1155 | || TARGET_MIPS5500 \ | |
122a6978 | 1156 | || TARGET_SR71K \ |
1157 | || TARGET_SMARTMIPS) \ | |
425e1c96 | 1158 | && !TARGET_MIPS16) |
2857c21b | 1159 | |
a5ca8551 | 1160 | /* ISA has the WSBH (word swap bytes within halfwords) instruction. |
1161 | 64-bit targets also provide DSBH and DSHD. */ | |
95faea77 | 1162 | #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16) |
a5ca8551 | 1163 | |
e0820f9b | 1164 | /* ISA has data prefetch instructions. This controls use of 'pref'. */ |
d2f64a9e | 1165 | #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ |
eb1b9bce | 1166 | || TARGET_LOONGSON_2EF \ |
60b34f30 | 1167 | || TARGET_MIPS5900 \ |
95faea77 | 1168 | || mips_isa_rev >= 1) \ |
d2f64a9e | 1169 | && !TARGET_MIPS16) |
1170 | ||
05af34e2 | 1171 | /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ |
1172 | #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) | |
78645e70 | 1173 | |
e0820f9b | 1174 | /* ISA has data indexed prefetch instructions. This controls use of |
1175 | 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. | |
1176 | (prefx is a cop1x instruction, so can only be used if FP is | |
1177 | enabled.) */ | |
75be7a44 | 1178 | #define ISA_HAS_PREFETCHX ISA_HAS_FP4 |
e0820f9b | 1179 | |
01a6581c | 1180 | /* True if trunc.w.s and trunc.w.d are real (not synthetic) |
1181 | instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d | |
1182 | also requires TARGET_DOUBLE_FLOAT. */ | |
1183 | #define ISA_HAS_TRUNC_W (!ISA_MIPS1) | |
1184 | ||
a02568c6 | 1185 | /* ISA includes the MIPS32r2 seb and seh instructions. */ |
95faea77 | 1186 | #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16) |
a02568c6 | 1187 | |
48365021 | 1188 | /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ |
95faea77 | 1189 | #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16) |
48365021 | 1190 | |
c910419d | 1191 | /* ISA has instructions for accessing top part of 64-bit fp regs. */ |
f2b55aea | 1192 | #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \ |
1193 | && mips_isa_rev >= 2) | |
4ec596ee | 1194 | |
122a6978 | 1195 | /* ISA has lwxs instruction (load w/scaled index address. */ |
ff9c1bc1 | 1196 | #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \ |
1197 | && !TARGET_MIPS16) | |
122a6978 | 1198 | |
b7508909 | 1199 | /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */ |
1200 | #define ISA_HAS_LBX (TARGET_OCTEON2) | |
1201 | #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2) | |
1202 | #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2) | |
1203 | #define ISA_HAS_LHUX (TARGET_OCTEON2) | |
1204 | #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2) | |
1205 | #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT) | |
1206 | #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \ | |
1207 | && TARGET_64BIT) | |
1208 | ||
c19eff17 | 1209 | /* The DSP ASE is available. */ |
1210 | #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) | |
1211 | ||
1212 | /* Revision 2 of the DSP ASE is available. */ | |
1213 | #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) | |
1214 | ||
ddc6405a | 1215 | /* The MSA ASE is available. */ |
1216 | #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16) | |
1217 | ||
203ea55a | 1218 | /* True if the result of a load is not available to the next instruction. |
1219 | A nop will then be needed between instructions like "lw $4,..." | |
1220 | and "addiu $4,$4,1". */ | |
425e1c96 | 1221 | #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ |
203ea55a | 1222 | && !TARGET_MIPS3900 \ |
60b34f30 | 1223 | && !TARGET_MIPS5900 \ |
ff9c1bc1 | 1224 | && !TARGET_MIPS16 \ |
1225 | && !TARGET_MICROMIPS) | |
203ea55a | 1226 | |
1227 | /* Likewise mtc1 and mfc1. */ | |
dc5599bf | 1228 | #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \ |
60b34f30 | 1229 | && !TARGET_MIPS5900 \ |
dc5599bf | 1230 | && !TARGET_LOONGSON_2EF) |
203ea55a | 1231 | |
1232 | /* Likewise floating-point comparisons. */ | |
dc5599bf | 1233 | #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \ |
60b34f30 | 1234 | && !TARGET_MIPS5900 \ |
dc5599bf | 1235 | && !TARGET_LOONGSON_2EF) |
203ea55a | 1236 | |
1237 | /* True if mflo and mfhi can be immediately followed by instructions | |
e78db7f7 | 1238 | which write to the HI and LO registers. |
1239 | ||
1240 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
1241 | (at least) two instructions between the reads of HI/LO and | |
1242 | instructions which write them, and later ISAs do not. Contradicting | |
1243 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
1244 | the UM for the NEC Vr5000) document needing the instructions between | |
1245 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
1246 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
1247 | earlier-ISA CPUs for which CPU documentation declares that the | |
1248 | instructions are really interlocked. */ | |
95faea77 | 1249 | #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \ |
dc5599bf | 1250 | || TARGET_MIPS5500 \ |
60b34f30 | 1251 | || TARGET_MIPS5900 \ |
dc5599bf | 1252 | || TARGET_LOONGSON_2EF) |
381be270 | 1253 | |
1254 | /* ISA includes synci, jr.hb and jalr.hb. */ | |
95faea77 | 1255 | #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) |
381be270 | 1256 | |
e5ee2a85 | 1257 | /* ISA includes sync. */ |
1258 | #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16) | |
652f626b | 1259 | #define GENERATE_SYNC \ |
1260 | (target_flags_explicit & MASK_LLSC \ | |
1261 | ? TARGET_LLSC && !TARGET_MIPS16 \ | |
1262 | : ISA_HAS_SYNC) | |
e5ee2a85 | 1263 | |
1264 | /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC | |
1265 | because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC | |
1266 | instructions. */ | |
5e524dea | 1267 | #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16) |
652f626b | 1268 | #define GENERATE_LL_SC \ |
1269 | (target_flags_explicit & MASK_LLSC \ | |
1270 | ? TARGET_LLSC && !TARGET_MIPS16 \ | |
1271 | : ISA_HAS_LL_SC) | |
fc84efeb | 1272 | |
974f0a74 | 1273 | #define ISA_HAS_SWAP (TARGET_XLP) |
1274 | #define ISA_HAS_LDADD (TARGET_XLP) | |
1275 | ||
765b6fef | 1276 | /* ISA includes the baddu instruction. */ |
0118f95f | 1277 | #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) |
765b6fef | 1278 | |
17ae43a3 | 1279 | /* ISA includes the bbit* instructions. */ |
0118f95f | 1280 | #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) |
17ae43a3 | 1281 | |
04877dac | 1282 | /* ISA includes the cins instruction. */ |
0118f95f | 1283 | #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) |
04877dac | 1284 | |
71966e79 | 1285 | /* ISA includes the exts instruction. */ |
0118f95f | 1286 | #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) |
71966e79 | 1287 | |
5d4f5520 | 1288 | /* ISA includes the seq and sne instructions. */ |
0118f95f | 1289 | #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) |
5d4f5520 | 1290 | |
fc84efeb | 1291 | /* ISA includes the pop instruction. */ |
0118f95f | 1292 | #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) |
f5ec18cc | 1293 | |
1294 | /* The CACHE instruction is available in non-MIPS16 code. */ | |
1295 | #define TARGET_CACHE_BUILTIN (mips_isa >= 3) | |
1296 | ||
1297 | /* The CACHE instruction is available. */ | |
1298 | #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) | |
c8829dad | 1299 | \f |
8d1a12c9 | 1300 | /* Tell collect what flags to pass to nm. */ |
1301 | #ifndef NM_FLAGS | |
9bc65db1 | 1302 | #define NM_FLAGS "-Bn" |
8d1a12c9 | 1303 | #endif |
1304 | ||
c8829dad | 1305 | \f |
4fc9a770 | 1306 | /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to |
b93bf04a | 1307 | the assembler. It may be overridden by subtargets. |
1308 | ||
1309 | Beginning with gas 2.13, -mdebug must be passed to correctly handle | |
1310 | COFF debugging info. */ | |
1311 | ||
4fc9a770 | 1312 | #ifndef SUBTARGET_ASM_DEBUGGING_SPEC |
1313 | #define SUBTARGET_ASM_DEBUGGING_SPEC "\ | |
63586066 | 1314 | %{g} %{g0} %{g1} %{g2} %{g3} \ |
1315 | %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ | |
1316 | %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ | |
1317 | %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ | |
3c791c03 | 1318 | %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ |
b93bf04a | 1319 | %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" |
4fc9a770 | 1320 | #endif |
63586066 | 1321 | |
b33cff21 | 1322 | /* FP_ASM_SPEC represents the floating-point options that must be passed |
1323 | to the assembler when FPXX support exists. Prior to that point the | |
1324 | assembler could accept the options but were not required for | |
1325 | correctness. We only add the options when absolutely necessary | |
1326 | because passing -msoft-float to the assembler will cause it to reject | |
1327 | all hard-float instructions which may require some user code to be | |
1328 | updated. */ | |
1329 | ||
1330 | #ifdef HAVE_AS_DOT_MODULE | |
1331 | #define FP_ASM_SPEC "\ | |
1332 | %{mhard-float} %{msoft-float} \ | |
1333 | %{msingle-float} %{mdouble-float}" | |
1334 | #else | |
1335 | #define FP_ASM_SPEC | |
1336 | #endif | |
1337 | ||
4fc9a770 | 1338 | /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be |
1339 | overridden by subtargets. */ | |
1340 | ||
1341 | #ifndef SUBTARGET_ASM_SPEC | |
1342 | #define SUBTARGET_ASM_SPEC "" | |
63586066 | 1343 | #endif |
4fc9a770 | 1344 | |
71d957f9 | 1345 | #undef ASM_SPEC |
4fc9a770 | 1346 | #define ASM_SPEC "\ |
a02568c6 | 1347 | %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ |
606c99b0 | 1348 | %{mips32*} %{mips64*} \ |
e6a71de3 | 1349 | %{mips16} %{mno-mips16:-no-mips16} \ |
ff9c1bc1 | 1350 | %{mmicromips} %{mno-micromips} \ |
e6a71de3 | 1351 | %{mips3d} %{mno-mips3d:-no-mips3d} \ |
1352 | %{mdmx} %{mno-mdmx:-no-mdmx} \ | |
1353 | %{mdsp} %{mno-dsp} \ | |
1354 | %{mdspr2} %{mno-dspr2} \ | |
e876044e | 1355 | %{mmcu} %{mno-mcu} \ |
3721f3a0 | 1356 | %{meva} %{mno-eva} \ |
486e9c5f | 1357 | %{mvirt} %{mno-virt} \ |
c7078bf2 | 1358 | %{mxpa} %{mno-xpa} \ |
ddc6405a | 1359 | %{mmsa} %{mno-msa} \ |
122a6978 | 1360 | %{msmartmips} %{mno-smartmips} \ |
e6a71de3 | 1361 | %{mmt} %{mno-mt} \ |
20607a76 | 1362 | %{mfix-rm7000} %{mno-fix-rm7000} \ |
b6586786 | 1363 | %{mfix-vr4120} %{mfix-vr4130} \ |
516cedbd | 1364 | %{mfix-24k} \ |
dd71e058 | 1365 | %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \ |
4fc9a770 | 1366 | %(subtarget_asm_debugging_spec) \ |
4a909f69 | 1367 | %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ |
9f733327 | 1368 | %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ |
f2b55aea | 1369 | %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \ |
1370 | %{modd-spreg} %{mno-odd-spreg} \ | |
1b6b10a9 | 1371 | %{mshared} %{mno-shared} \ |
6f172a83 | 1372 | %{msym32} %{mno-sym32} \ |
b33cff21 | 1373 | %{mtune=*}" \ |
1374 | FP_ASM_SPEC "\ | |
4fc9a770 | 1375 | %(subtarget_asm_spec)" |
c8829dad | 1376 | |
904c9ae7 | 1377 | /* Extra switches sometimes passed to the linker. */ |
c8829dad | 1378 | |
1379 | #ifndef LINK_SPEC | |
904c9ae7 | 1380 | #define LINK_SPEC "\ |
fb9d1677 | 1381 | %(endian_spec) \ |
606c99b0 | 1382 | %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ |
1572b5b7 | 1383 | %{shared}" |
582b17a6 | 1384 | #endif /* LINK_SPEC defined */ |
1385 | ||
c8829dad | 1386 | |
1387 | /* Specs for the compiler proper */ | |
1388 | ||
5fafa3a5 | 1389 | /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be |
1390 | overridden by subtargets. */ | |
1391 | #ifndef SUBTARGET_CC1_SPEC | |
1392 | #define SUBTARGET_CC1_SPEC "" | |
1393 | #endif | |
1394 | ||
1395 | /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ | |
1396 | ||
06eca8b8 | 1397 | #undef CC1_SPEC |
904c9ae7 | 1398 | #define CC1_SPEC "\ |
5a5f5a9c | 1399 | %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ |
6a59b91a | 1400 | %(subtarget_cc1_spec)" |
c8829dad | 1401 | |
4fc9a770 | 1402 | /* Preprocessor specs. */ |
1403 | ||
4fc9a770 | 1404 | /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be |
1405 | overridden by subtargets. */ | |
1406 | #ifndef SUBTARGET_CPP_SPEC | |
1407 | #define SUBTARGET_CPP_SPEC "" | |
1408 | #endif | |
1409 | ||
fa2b6990 | 1410 | #define CPP_SPEC "%(subtarget_cpp_spec)" |
4fc9a770 | 1411 | |
1412 | /* This macro defines names of additional specifications to put in the specs | |
1413 | that can be used in various specifications like CC1_SPEC. Its definition | |
1414 | is an initializer with a subgrouping for each command option. | |
1415 | ||
1416 | Each subgrouping contains a string constant, that defines the | |
187b36cf | 1417 | specification name, and a string constant that used by the GCC driver |
4fc9a770 | 1418 | program. |
1419 | ||
1420 | Do not define this macro if it does not need to do anything. */ | |
1421 | ||
1422 | #define EXTRA_SPECS \ | |
6b40eba4 | 1423 | { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ |
1424 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
6b40eba4 | 1425 | { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ |
1426 | { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
b93bf04a | 1427 | { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ |
fb9d1677 | 1428 | { "endian_spec", ENDIAN_SPEC }, \ |
4fc9a770 | 1429 | SUBTARGET_EXTRA_SPECS |
1430 | ||
1431 | #ifndef SUBTARGET_EXTRA_SPECS | |
1432 | #define SUBTARGET_EXTRA_SPECS | |
c8829dad | 1433 | #endif |
c8829dad | 1434 | \f |
a4cad234 | 1435 | #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ |
09b049bd | 1436 | #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ |
1437 | ||
1438 | #ifndef PREFERRED_DEBUGGING_TYPE | |
1439 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1440 | #endif | |
c8829dad | 1441 | |
0a959c1d | 1442 | /* The size of DWARF addresses should be the same as the size of symbols |
1443 | in the target file format. They shouldn't depend on things like -msym32, | |
1444 | because many DWARF consumers do not allow the mixture of address sizes | |
1445 | that one would then get from linking -msym32 code with -msym64 code. | |
1446 | ||
1447 | Note that the default POINTER_SIZE test is not appropriate for MIPS. | |
1448 | EABI64 has 64-bit pointers but uses 32-bit ELF. */ | |
1449 | #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4) | |
004cc9ee | 1450 | |
8d1a12c9 | 1451 | /* By default, turn on GDB extensions. */ |
1452 | #define DEFAULT_GDB_EXTENSIONS 1 | |
1453 | ||
d1e7dfe2 | 1454 | /* Registers may have a prefix which can be ignored when matching |
1455 | user asm and register definitions. */ | |
1456 | #ifndef REGISTER_PREFIX | |
1457 | #define REGISTER_PREFIX "$" | |
1458 | #endif | |
1459 | ||
34a7f2a4 | 1460 | /* Local compiler-generated symbols must have a prefix that the assembler |
1461 | understands. By default, this is $, although some targets (e.g., | |
00f58f47 | 1462 | NetBSD-ELF) need to override this. */ |
34a7f2a4 | 1463 | |
1464 | #ifndef LOCAL_LABEL_PREFIX | |
1465 | #define LOCAL_LABEL_PREFIX "$" | |
1466 | #endif | |
1467 | ||
1468 | /* By default on the mips, external symbols do not have an underscore | |
00f58f47 | 1469 | prepended, but some targets (e.g., NetBSD) require this. */ |
34a7f2a4 | 1470 | |
1471 | #ifndef USER_LABEL_PREFIX | |
1472 | #define USER_LABEL_PREFIX "" | |
1473 | #endif | |
1474 | ||
c8829dad | 1475 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, |
1476 | since the length can run past this up to a continuation point. */ | |
cd16e7b6 | 1477 | #undef DBX_CONTIN_LENGTH |
c8829dad | 1478 | #define DBX_CONTIN_LENGTH 1500 |
1479 | ||
00f58f47 | 1480 | /* How to renumber registers for dbx and gdb. */ |
4509d619 | 1481 | #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO] |
c8829dad | 1482 | |
933d6ec0 | 1483 | /* The mapping from gcc register number to DWARF 2 CFA column number. */ |
4509d619 | 1484 | #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO] |
212538c2 | 1485 | |
1486 | /* The DWARF 2 CFA column which tracks the return address. */ | |
2ae168f4 | 1487 | #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM |
2c36ab68 | 1488 | |
df78b73b | 1489 | /* Before the prologue, RA lives in r31. */ |
4083d5ee | 1490 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) |
df78b73b | 1491 | |
b92c85dc | 1492 | /* Describe how we implement __builtin_eh_return. */ |
9f115c31 | 1493 | #define EH_RETURN_DATA_REGNO(N) \ |
1494 | ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
1495 | ||
b92c85dc | 1496 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) |
1497 | ||
74facf6e | 1498 | #define EH_USES(N) mips_eh_uses (N) |
1499 | ||
08aec1b6 | 1500 | /* Offsets recorded in opcodes are a multiple of this alignment factor. |
ffbc3131 | 1501 | The default for this in 64-bit mode is 8, which causes problems with |
1502 | SFmode register saves. */ | |
a18b01d6 | 1503 | #define DWARF_CIE_DATA_ALIGNMENT -4 |
ffbc3131 | 1504 | |
9f4bac70 | 1505 | /* Correct the offset of automatic variables and arguments. Note that |
1506 | the MIPS debug format wants all automatic variables and arguments | |
1507 | to be in terms of the virtual frame pointer (stack pointer before | |
1508 | any adjustment in the function), while the MIPS 3.0 linker wants | |
1509 | the frame pointer to be the stack pointer after the initial | |
1510 | adjustment. */ | |
c8829dad | 1511 | |
d2f64a9e | 1512 | #define DEBUGGER_AUTO_OFFSET(X) \ |
c5aa1e92 | 1513 | mips_debugger_offset (X, (HOST_WIDE_INT) 0) |
d2f64a9e | 1514 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ |
c5aa1e92 | 1515 | mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) |
c8829dad | 1516 | \f |
1517 | /* Target machine storage layout */ | |
1518 | ||
9f571898 | 1519 | #define BITS_BIG_ENDIAN 0 |
5a5f5a9c | 1520 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
5a5f5a9c | 1521 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
c8829dad | 1522 | |
e29b85c8 | 1523 | #define MAX_BITS_PER_WORD 64 |
c8829dad | 1524 | |
1525 | /* Width of a word, in units (bytes). */ | |
e425840e | 1526 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
53a488ea | 1527 | #ifndef IN_LIBGCC2 |
65748b1b | 1528 | #define MIN_UNITS_PER_WORD 4 |
53a488ea | 1529 | #endif |
e29b85c8 | 1530 | |
ddc6405a | 1531 | /* Width of a MSA vector register in bytes. */ |
1532 | #define UNITS_PER_MSA_REG 16 | |
1533 | /* Width of a MSA vector register in bits. */ | |
1534 | #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT) | |
1535 | ||
e29b85c8 | 1536 | /* For MIPS, width of a floating point register. */ |
e425840e | 1537 | #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) |
c8829dad | 1538 | |
fef98e29 | 1539 | /* The number of consecutive floating-point registers needed to store the |
1540 | largest format supported by the FPU. */ | |
1541 | #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) | |
1542 | ||
1543 | /* The number of consecutive floating-point registers needed to store the | |
1544 | smallest format supported by the FPU. */ | |
1545 | #define MIN_FPRS_PER_FMT \ | |
f2b55aea | 1546 | (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT) |
8c9bf23a | 1547 | |
3968abe0 | 1548 | /* The largest size of value that can be held in floating-point |
1549 | registers and moved with a single instruction. */ | |
fef98e29 | 1550 | #define UNITS_PER_HWFPVALUE \ |
50b412ce | 1551 | (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG) |
3968abe0 | 1552 | |
1553 | /* The largest size of value that can be held in floating-point | |
1554 | registers. */ | |
2538b6a3 | 1555 | #define UNITS_PER_FPVALUE \ |
50b412ce | 1556 | (TARGET_SOFT_FLOAT_ABI ? 0 \ |
2538b6a3 | 1557 | : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ |
1558 | : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) | |
09a41b31 | 1559 | |
1560 | /* The number of bytes in a double. */ | |
1561 | #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) | |
8c9bf23a | 1562 | |
933d6ec0 | 1563 | /* Set the sizes of the core types. */ |
c8829dad | 1564 | #define SHORT_TYPE_SIZE 16 |
6cb9e8e1 | 1565 | #define INT_TYPE_SIZE 32 |
e425840e | 1566 | #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) |
9147314e | 1567 | #define LONG_LONG_TYPE_SIZE 64 |
c8829dad | 1568 | |
933d6ec0 | 1569 | #define FLOAT_TYPE_SIZE 32 |
c8829dad | 1570 | #define DOUBLE_TYPE_SIZE 64 |
93a1903e | 1571 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) |
3968abe0 | 1572 | |
d20b198f | 1573 | /* Define the sizes of fixed-point types. */ |
1574 | #define SHORT_FRACT_TYPE_SIZE 8 | |
1575 | #define FRACT_TYPE_SIZE 16 | |
1576 | #define LONG_FRACT_TYPE_SIZE 32 | |
1577 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
1578 | ||
1579 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
1580 | #define ACCUM_TYPE_SIZE 32 | |
1581 | #define LONG_ACCUM_TYPE_SIZE 64 | |
1582 | /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC | |
1583 | doesn't support 128-bit integers for MIPS32 currently. */ | |
1584 | #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) | |
1585 | ||
3968abe0 | 1586 | /* long double is not a fixed mode, but the idea is that, if we |
1587 | support long double, we also want a 128-bit integer type. */ | |
1588 | #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE | |
1589 | ||
c9e1a048 | 1590 | /* Width in bits of a pointer. */ |
7a9d1fec | 1591 | #ifndef POINTER_SIZE |
c9e1a048 | 1592 | #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) |
7a9d1fec | 1593 | #endif |
c8829dad | 1594 | |
c8829dad | 1595 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
a5ab28e7 | 1596 | #define PARM_BOUNDARY BITS_PER_WORD |
c9e1a048 | 1597 | |
c8829dad | 1598 | /* Allocation boundary (in *bits*) for the code of a function. */ |
1599 | #define FUNCTION_BOUNDARY 32 | |
1600 | ||
1601 | /* Alignment of field after `int : 0' in a structure. */ | |
449fb1f8 | 1602 | #define EMPTY_FIELD_BOUNDARY 32 |
c8829dad | 1603 | |
1604 | /* Every structure's size must be a multiple of this. */ | |
1605 | /* 8 is observed right on a DECstation and on riscos 4.02. */ | |
1606 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
1607 | ||
ddc6405a | 1608 | /* There is no point aligning anything to a rounder boundary than |
1609 | LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is | |
1610 | BITS_PER_MSA_REG. */ | |
1611 | #define BIGGEST_ALIGNMENT \ | |
1612 | (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE) | |
c8829dad | 1613 | |
933d6ec0 | 1614 | /* All accesses must be aligned. */ |
904c9ae7 | 1615 | #define STRICT_ALIGNMENT 1 |
c8829dad | 1616 | |
1617 | /* Define this if you wish to imitate the way many other C compilers | |
1618 | handle alignment of bitfields and the structures that contain | |
1619 | them. | |
1620 | ||
ceb2fe0f | 1621 | The behavior is that the type written for a bit-field (`int', |
c8829dad | 1622 | `short', or other integer type) imposes an alignment for the |
1623 | entire structure, as if the structure really did contain an | |
ceb2fe0f | 1624 | ordinary field of that type. In addition, the bit-field is placed |
c8829dad | 1625 | within the structure so that it would fit within such a field, |
1626 | not crossing a boundary for it. | |
1627 | ||
ceb2fe0f | 1628 | Thus, on most machines, a bit-field whose type is written as `int' |
c8829dad | 1629 | would not cross a four-byte boundary, and would force four-byte |
1630 | alignment for the whole structure. (The alignment used may not | |
1631 | be four bytes; it is controlled by the other alignment | |
1632 | parameters.) | |
1633 | ||
1634 | If the macro is defined, its definition should be a C expression; | |
1635 | a nonzero value for the expression enables this behavior. */ | |
1636 | ||
1637 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
1638 | ||
1639 | /* If defined, a C expression to compute the alignment given to a | |
1640 | constant that is being placed in memory. CONSTANT is the constant | |
1641 | and ALIGN is the alignment that the object would ordinarily have. | |
1642 | The value of this macro is used instead of that alignment to align | |
1643 | the object. | |
1644 | ||
1645 | If this macro is not defined, then ALIGN is used. | |
1646 | ||
1647 | The typical use of this macro is to increase alignment for string | |
1648 | constants to be word aligned so that `strcpy' calls that copy | |
1649 | constants can be done inline. */ | |
1650 | ||
1651 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
1652 | ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
0eacd412 | 1653 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) |
c8829dad | 1654 | |
1655 | /* If defined, a C expression to compute the alignment for a static | |
1656 | variable. TYPE is the data type, and ALIGN is the alignment that | |
1657 | the object would ordinarily have. The value of this macro is used | |
1658 | instead of that alignment to align the object. | |
1659 | ||
1660 | If this macro is not defined, then ALIGN is used. | |
1661 | ||
1662 | One use of this macro is to increase alignment of medium-size | |
1663 | data to make it all fit in fewer cache lines. Another is to | |
1664 | cause character arrays to be word-aligned so that `strcpy' calls | |
1665 | that copy constants to character arrays can be done inline. */ | |
1666 | ||
1667 | #undef DATA_ALIGNMENT | |
1668 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
1669 | ((((ALIGN) < BITS_PER_WORD) \ | |
1670 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
1671 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
1672 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
1673 | ||
3e7d5e0d | 1674 | /* We need this for the same reason as DATA_ALIGNMENT, namely to cause |
1675 | character arrays to be word-aligned so that `strcpy' calls that copy | |
1676 | constants to character arrays can be done inline, and 'strcmp' can be | |
1677 | optimised to use word loads. */ | |
1678 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
1679 | DATA_ALIGNMENT (TYPE, ALIGN) | |
1680 | ||
0fee47f4 | 1681 | #define PAD_VARARGS_DOWN \ |
1682 | (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
262088a4 | 1683 | |
29701bb8 | 1684 | /* Define if operations between registers always perform the operation |
1685 | on the full register even if a narrower mode is specified. */ | |
94f1fba7 | 1686 | #define WORD_REGISTER_OPERATIONS 1 |
29701bb8 | 1687 | |
c910419d | 1688 | /* When in 64-bit mode, move insns will sign extend SImode and CCmode |
dfd1079d | 1689 | moves. All other references are zero extended. */ |
75bf6244 | 1690 | #define LOAD_EXTEND_OP(MODE) \ |
1691 | (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ | |
1692 | ? SIGN_EXTEND : ZERO_EXTEND) | |
4ddcf2b2 | 1693 | |
1694 | /* Define this macro if it is advisable to hold scalars in registers | |
08aec1b6 | 1695 | in a wider mode than that declared by the program. In such cases, |
4ddcf2b2 | 1696 | the value is constrained to be within the bounds of the declared |
1697 | type, but kept valid in the wider mode. The signedness of the | |
c9e1a048 | 1698 | extension may differ from that of the type. */ |
4ddcf2b2 | 1699 | |
1700 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1701 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
c9e1a048 | 1702 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ |
1703 | { \ | |
1704 | if ((MODE) == SImode) \ | |
1705 | (UNSIGNEDP) = 0; \ | |
1706 | (MODE) = Pmode; \ | |
1707 | } | |
1708 | ||
223ccc42 | 1709 | /* Pmode is always the same as ptr_mode, but not always the same as word_mode. |
1710 | Extensions of pointers to word_mode must be signed. */ | |
1711 | #define POINTERS_EXTEND_UNSIGNED false | |
1712 | ||
c9e1a048 | 1713 | /* Define if loading short immediate values into registers sign extends. */ |
d0b99710 | 1714 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
929dcf95 | 1715 | |
1716 | /* The [d]clz instructions have the natural values at 0. */ | |
1717 | ||
1718 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
ddc6405a | 1719 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
c8829dad | 1720 | \f |
1721 | /* Standard register usage. */ | |
1722 | ||
933d6ec0 | 1723 | /* Number of hardware registers. We have: |
c8829dad | 1724 | |
933d6ec0 | 1725 | - 32 integer registers |
1726 | - 32 floating point registers | |
1727 | - 8 condition code registers | |
1728 | - 2 accumulator registers (hi and lo) | |
1729 | - 32 registers each for coprocessors 0, 2 and 3 | |
74facf6e | 1730 | - 4 fake registers: |
5b1aef3e | 1731 | - ARG_POINTER_REGNUM |
1732 | - FRAME_POINTER_REGNUM | |
5eec32fe | 1733 | - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details) |
74facf6e | 1734 | - CPRESTORE_SLOT_REGNUM |
1735 | - 2 dummy entries that were used at various times in the past. | |
b7efe757 | 1736 | - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE |
1737 | - 6 DSP control registers */ | |
c8829dad | 1738 | |
b7efe757 | 1739 | #define FIRST_PSEUDO_REGISTER 188 |
c8829dad | 1740 | |
933d6ec0 | 1741 | /* By default, fix the kernel registers ($26 and $27), the global |
1742 | pointer ($28) and the stack pointer ($29). This can change | |
1743 | depending on the command-line options. | |
c8829dad | 1744 | |
933d6ec0 | 1745 | Regarding coprocessor registers: without evidence to the contrary, |
8d85666f | 1746 | it's best to assume that each coprocessor register has a unique |
e188502f | 1747 | use. This can be overridden, in, e.g., mips_option_override or |
b2d7ede1 | 1748 | TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be |
1749 | inappropriate for a particular target. */ | |
8d85666f | 1750 | |
c8829dad | 1751 | #define FIXED_REGISTERS \ |
1752 | { \ | |
1753 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
c9e1a048 | 1754 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ |
c8829dad | 1755 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1756 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
c5717e12 | 1757 | 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ |
8d85666f | 1758 | /* COP0 registers */ \ |
1759 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1760 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1761 | /* COP2 registers */ \ | |
1762 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1763 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1764 | /* COP3 registers */ \ | |
1765 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
b7efe757 | 1766 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1767 | /* 6 DSP accumulator registers & 6 control registers */ \ | |
1768 | 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ | |
c8829dad | 1769 | } |
1770 | ||
1771 | ||
933d6ec0 | 1772 | /* Set up this array for o32 by default. |
1773 | ||
1774 | Note that we don't mark $31 as a call-clobbered register. The idea is | |
1775 | that it's really the call instructions themselves which clobber $31. | |
c9e1a048 | 1776 | We don't care what the called function does with it afterwards. |
1777 | ||
1778 | This approach makes it easier to implement sibcalls. Unlike normal | |
1779 | calls, sibcalls don't clobber $31, so the register reaches the | |
1780 | called function in tact. EPILOGUE_USES says that $31 is useful | |
1781 | to the called function. */ | |
c8829dad | 1782 | |
1783 | #define CALL_USED_REGISTERS \ | |
1784 | { \ | |
1785 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
c9e1a048 | 1786 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ |
c8829dad | 1787 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1788 | 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
c9e1a048 | 1789 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
8d85666f | 1790 | /* COP0 registers */ \ |
1791 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1792 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1793 | /* COP2 registers */ \ | |
1794 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1795 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1796 | /* COP3 registers */ \ | |
1797 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
b7efe757 | 1798 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1799 | /* 6 DSP accumulator registers & 6 control registers */ \ | |
1800 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
c8829dad | 1801 | } |
1802 | ||
dfabc2e7 | 1803 | |
933d6ec0 | 1804 | /* Define this since $28, though fixed, is call-saved in many ABIs. */ |
dfabc2e7 | 1805 | |
1806 | #define CALL_REALLY_USED_REGISTERS \ | |
1807 | { /* General registers. */ \ | |
1808 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
c9e1a048 | 1809 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ |
dfabc2e7 | 1810 | /* Floating-point registers. */ \ |
1811 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1812 | 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1813 | /* Others. */ \ | |
5eec32fe | 1814 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \ |
8d85666f | 1815 | /* COP0 registers */ \ |
1816 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1817 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1818 | /* COP2 registers */ \ | |
1819 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1820 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1821 | /* COP3 registers */ \ | |
1822 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
b7efe757 | 1823 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1824 | /* 6 DSP accumulator registers & 6 control registers */ \ | |
1825 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ | |
dfabc2e7 | 1826 | } |
c8829dad | 1827 | |
1828 | /* Internal macros to classify a register number as to whether it's a | |
1829 | general purpose register, a floating point register, a | |
37727f6d | 1830 | multiply/divide register, or a status register. */ |
c8829dad | 1831 | |
1832 | #define GP_REG_FIRST 0 | |
1833 | #define GP_REG_LAST 31 | |
1834 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
1835 | #define GP_DBX_FIRST 0 | |
0bfaf4c4 | 1836 | #define K0_REG_NUM (GP_REG_FIRST + 26) |
1837 | #define K1_REG_NUM (GP_REG_FIRST + 27) | |
1838 | #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM)) | |
c8829dad | 1839 | |
1840 | #define FP_REG_FIRST 32 | |
1841 | #define FP_REG_LAST 63 | |
1842 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
1843 | #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) | |
1844 | ||
1845 | #define MD_REG_FIRST 64 | |
c5717e12 | 1846 | #define MD_REG_LAST 65 |
c8829dad | 1847 | #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) |
f4bfc916 | 1848 | #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) |
c8829dad | 1849 | |
ddc6405a | 1850 | #define MSA_REG_FIRST FP_REG_FIRST |
1851 | #define MSA_REG_LAST FP_REG_LAST | |
1852 | #define MSA_REG_NUM FP_REG_NUM | |
1853 | ||
f7e97fb8 | 1854 | /* The DWARF 2 CFA column which tracks the return address from a |
1855 | signal handler context. This means that to maintain backwards | |
1856 | compatibility, no hard register can be assigned this column if it | |
1857 | would need to be handled by the DWARF unwinder. */ | |
1858 | #define DWARF_ALT_FRAME_RETURN_COLUMN 66 | |
1859 | ||
fe761857 | 1860 | #define ST_REG_FIRST 67 |
0ca99114 | 1861 | #define ST_REG_LAST 74 |
c8829dad | 1862 | #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) |
1863 | ||
2b801d92 | 1864 | |
c9e1a048 | 1865 | /* FIXME: renumber. */ |
8d85666f | 1866 | #define COP0_REG_FIRST 80 |
1867 | #define COP0_REG_LAST 111 | |
1868 | #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) | |
1869 | ||
0bfaf4c4 | 1870 | #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12) |
1871 | #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13) | |
1872 | #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14) | |
1873 | ||
8d85666f | 1874 | #define COP2_REG_FIRST 112 |
1875 | #define COP2_REG_LAST 143 | |
1876 | #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) | |
1877 | ||
1878 | #define COP3_REG_FIRST 144 | |
1879 | #define COP3_REG_LAST 175 | |
1880 | #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) | |
2df386e3 | 1881 | |
1882 | /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */ | |
1883 | #define ALL_COP_REG_FIRST COP0_REG_FIRST | |
1884 | #define ALL_COP_REG_LAST COP3_REG_LAST | |
1885 | #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1) | |
8d85666f | 1886 | |
b7efe757 | 1887 | #define DSP_ACC_REG_FIRST 176 |
1888 | #define DSP_ACC_REG_LAST 181 | |
1889 | #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) | |
1890 | ||
c8829dad | 1891 | #define AT_REGNUM (GP_REG_FIRST + 1) |
4509d619 | 1892 | #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1) |
1893 | #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST) | |
0ca99114 | 1894 | |
0bfaf4c4 | 1895 | /* A few bitfield locations for the coprocessor registers. */ |
1896 | /* Request Interrupt Priority Level is from bit 10 to bit 15 of | |
1897 | the cause register for the EIC interrupt mode. */ | |
1898 | #define CAUSE_IPL 10 | |
b6f884d4 | 1899 | /* COP1 Enable is at bit 29 of the status register. */ |
1900 | #define SR_COP1 29 | |
0bfaf4c4 | 1901 | /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ |
1902 | #define SR_IPL 10 | |
70b5547a | 1903 | /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status |
1904 | register. */ | |
1905 | #define SR_IM0 8 | |
0bfaf4c4 | 1906 | /* Exception Level is at bit 1 of the status register. */ |
1907 | #define SR_EXL 1 | |
1908 | /* Interrupt Enable is at bit 0 of the status register. */ | |
1909 | #define SR_IE 0 | |
1910 | ||
933d6ec0 | 1911 | /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. |
1912 | If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG | |
0ca99114 | 1913 | should be used instead. */ |
c8829dad | 1914 | #define FPSW_REGNUM ST_REG_FIRST |
1915 | ||
0eacd412 | 1916 | #define GP_REG_P(REGNO) \ |
1917 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
4ddcf2b2 | 1918 | #define M16_REG_P(REGNO) \ |
1919 | (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) | |
ff9c1bc1 | 1920 | #define M16STORE_REG_P(REGNO) \ |
1921 | (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17) | |
0eacd412 | 1922 | #define FP_REG_P(REGNO) \ |
1923 | ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
1924 | #define MD_REG_P(REGNO) \ | |
1925 | ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) | |
1926 | #define ST_REG_P(REGNO) \ | |
1927 | ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) | |
8d85666f | 1928 | #define COP0_REG_P(REGNO) \ |
1929 | ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) | |
1930 | #define COP2_REG_P(REGNO) \ | |
1931 | ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) | |
1932 | #define COP3_REG_P(REGNO) \ | |
1933 | ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) | |
1934 | #define ALL_COP_REG_P(REGNO) \ | |
1935 | ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) | |
b7efe757 | 1936 | /* Test if REGNO is one of the 6 new DSP accumulators. */ |
1937 | #define DSP_ACC_REG_P(REGNO) \ | |
1938 | ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) | |
1939 | /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ | |
1940 | #define ACC_REG_P(REGNO) \ | |
1941 | (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) | |
ddc6405a | 1942 | #define MSA_REG_P(REGNO) \ |
1943 | ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM) | |
8d85666f | 1944 | |
a605649a | 1945 | #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) |
ddc6405a | 1946 | #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X))) |
8d5952bf | 1947 | |
2fbff099 | 1948 | /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used |
1949 | to initialize the mips16 gp pseudo register. */ | |
1950 | #define CONST_GP_P(X) \ | |
1951 | (GET_CODE (X) == CONST \ | |
1952 | && GET_CODE (XEXP (X, 0)) == UNSPEC \ | |
1953 | && XINT (XEXP (X, 0), 1) == UNSPEC_GP) | |
1954 | ||
8d85666f | 1955 | /* Return coprocessor number from register number. */ |
1956 | ||
1957 | #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ | |
1958 | (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ | |
1959 | : COP3_REG_P (REGNO) ? '3' : '?') | |
c8829dad | 1960 | |
c8829dad | 1961 | |
582b17a6 | 1962 | #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) |
c8829dad | 1963 | |
35ed5ce3 | 1964 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ |
1965 | mips_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
1966 | ||
f2b55aea | 1967 | /* Select a register mode required for caller save of hard regno REGNO. */ |
1968 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
1969 | mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE) | |
1970 | ||
07a96917 | 1971 | #define MODES_TIEABLE_P mips_modes_tieable_p |
c8829dad | 1972 | |
c8829dad | 1973 | /* Register to use for pushing function arguments. */ |
e15eeed0 | 1974 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) |
c8829dad | 1975 | |
5b1aef3e | 1976 | /* These two registers don't really exist: they get eliminated to either |
1977 | the stack or hard frame pointer. */ | |
1978 | #define ARG_POINTER_REGNUM 77 | |
1979 | #define FRAME_POINTER_REGNUM 78 | |
4ddcf2b2 | 1980 | |
1981 | /* $30 is not available on the mips16, so we use $17 as the frame | |
1982 | pointer. */ | |
1983 | #define HARD_FRAME_POINTER_REGNUM \ | |
1984 | (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) | |
c8829dad | 1985 | |
5ae82d58 | 1986 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
1987 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
1988 | ||
c8829dad | 1989 | /* Register in which static-chain is passed to a function. */ |
d0d816ec | 1990 | #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) |
c8829dad | 1991 | |
559b0712 | 1992 | /* Registers used as temporaries in prologue/epilogue code: |
3ba8ab31 | 1993 | |
559b0712 | 1994 | - If a MIPS16 PIC function needs access to _gp, it first loads |
1995 | the value into MIPS16_PIC_TEMP and then copies it to $gp. | |
1996 | ||
1997 | - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary | |
1998 | register. The register must not conflict with MIPS16_PIC_TEMP. | |
1999 | ||
51ad9863 | 2000 | - If we aren't generating MIPS16 code, the prologue can also use |
2001 | MIPS_PROLOGUE_TEMP2 as a general temporary register. | |
2002 | ||
559b0712 | 2003 | - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary |
2004 | register. | |
2005 | ||
2006 | If we're generating MIPS16 code, these registers must come from the | |
2007 | core set of 8. The prologue registers mustn't conflict with any | |
2008 | incoming arguments, the static chain pointer, or the frame pointer. | |
2009 | The epilogue temporary mustn't conflict with the return registers, | |
2010 | the PIC call register ($25), the frame pointer, the EH stack adjustment, | |
0bfaf4c4 | 2011 | or the EH data registers. |
2012 | ||
2013 | If we're generating interrupt handlers, we use K0 as a temporary register | |
2014 | in prologue/epilogue code. */ | |
559b0712 | 2015 | |
2016 | #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2) | |
0bfaf4c4 | 2017 | #define MIPS_PROLOGUE_TEMP_REGNUM \ |
2018 | (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3) | |
51ad9863 | 2019 | #define MIPS_PROLOGUE_TEMP2_REGNUM \ |
2020 | (TARGET_MIPS16 \ | |
2021 | ? (gcc_unreachable (), INVALID_REGNUM) \ | |
2022 | : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12) | |
0bfaf4c4 | 2023 | #define MIPS_EPILOGUE_TEMP_REGNUM \ |
2024 | (cfun->machine->interrupt_handler_p \ | |
2025 | ? K0_REG_NUM \ | |
2026 | : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) | |
3ba8ab31 | 2027 | |
559b0712 | 2028 | #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM) |
3ba8ab31 | 2029 | #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) |
51ad9863 | 2030 | #define MIPS_PROLOGUE_TEMP2(MODE) \ |
2031 | gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM) | |
3ba8ab31 | 2032 | #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) |
c8829dad | 2033 | |
2034 | /* Define this macro if it is as good or better to call a constant | |
2035 | function address than to call an address kept in a register. */ | |
2036 | #define NO_FUNCTION_CSE 1 | |
2037 | ||
5e681afc | 2038 | /* The ABI-defined global pointer. Sometimes we use a different |
2039 | register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ | |
2040 | #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) | |
2041 | ||
2042 | /* We normally use $28 as the global pointer. However, when generating | |
2043 | n32/64 PIC, it is better for leaf functions to use a call-clobbered | |
2044 | register instead. They can then avoid saving and restoring $28 | |
2045 | and perhaps avoid using a frame at all. | |
2046 | ||
2047 | When a leaf function uses something other than $28, mips_expand_prologue | |
2048 | will modify pic_offset_table_rtx in place. Take the register number | |
2049 | from there after reload. */ | |
2050 | #define PIC_OFFSET_TABLE_REGNUM \ | |
2051 | (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) | |
c8829dad | 2052 | \f |
2053 | /* Define the classes of registers for register constraints in the | |
2054 | machine description. Also define ranges of constants. | |
2055 | ||
2056 | One of the classes must always be named ALL_REGS and include all hard regs. | |
2057 | If there is more than one class, another class must be named NO_REGS | |
2058 | and contain no registers. | |
2059 | ||
2060 | The name GENERAL_REGS must be the name of a class (or an alias for | |
2061 | another name such as ALL_REGS). This is the class of registers | |
2062 | that is allowed by "g" or "r" in a register constraint. | |
2063 | Also, registers outside this class are allocated only when | |
2064 | instructions express preferences for them. | |
2065 | ||
2066 | The classes must be numbered in nondecreasing order; that is, | |
2067 | a larger-numbered class must never be contained completely | |
2068 | in a smaller-numbered class. | |
2069 | ||
2070 | For any two classes, it is very desirable that there be another | |
2071 | class that represents their union. */ | |
2072 | ||
2073 | enum reg_class | |
2074 | { | |
2075 | NO_REGS, /* no registers in set */ | |
8deb0486 | 2076 | M16_STORE_REGS, /* microMIPS store registers */ |
4ddcf2b2 | 2077 | M16_REGS, /* mips16 directly accessible registers */ |
3c0e3fb9 | 2078 | M16_SP_REGS, /* mips16 + $sp */ |
4ddcf2b2 | 2079 | T_REG, /* mips16 T register ($24) */ |
2080 | M16_T_REGS, /* mips16 registers plus T register */ | |
c9e1a048 | 2081 | PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ |
ccb1cd1e | 2082 | V1_REG, /* Register $v1 ($3) used for TLS access. */ |
3c0e3fb9 | 2083 | SPILL_REGS, /* All but $sp and call preserved regs are in here */ |
c9e1a048 | 2084 | LEA_REGS, /* Every GPR except $25 */ |
c8829dad | 2085 | GR_REGS, /* integer registers */ |
2086 | FP_REGS, /* floating point registers */ | |
4509d619 | 2087 | MD0_REG, /* first multiply/divide register */ |
2088 | MD1_REG, /* second multiply/divide register */ | |
c8829dad | 2089 | MD_REGS, /* multiply/divide registers (hi/lo) */ |
8d85666f | 2090 | COP0_REGS, /* generic coprocessor classes */ |
2091 | COP2_REGS, | |
2092 | COP3_REGS, | |
c8829dad | 2093 | ST_REGS, /* status registers (fp status) */ |
b7efe757 | 2094 | DSP_ACC_REGS, /* DSP accumulator registers */ |
2095 | ACC_REGS, /* Hi/Lo and DSP accumulator registers */ | |
024f0a8a | 2096 | FRAME_REGS, /* $arg and $frame */ |
1678533f | 2097 | GR_AND_MD0_REGS, /* union classes */ |
2098 | GR_AND_MD1_REGS, | |
2099 | GR_AND_MD_REGS, | |
2100 | GR_AND_ACC_REGS, | |
c8829dad | 2101 | ALL_REGS, /* all registers */ |
2102 | LIM_REG_CLASSES /* max value + 1 */ | |
2103 | }; | |
2104 | ||
2105 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
2106 | ||
2107 | #define GENERAL_REGS GR_REGS | |
2108 | ||
2109 | /* An initializer containing the names of the register classes as C | |
2110 | string constants. These names are used in writing some of the | |
2111 | debugging dumps. */ | |
2112 | ||
2113 | #define REG_CLASS_NAMES \ | |
2114 | { \ | |
2115 | "NO_REGS", \ | |
8deb0486 | 2116 | "M16_STORE_REGS", \ |
4ddcf2b2 | 2117 | "M16_REGS", \ |
3c0e3fb9 | 2118 | "M16_SP_REGS", \ |
4ddcf2b2 | 2119 | "T_REG", \ |
2120 | "M16_T_REGS", \ | |
c9e1a048 | 2121 | "PIC_FN_ADDR_REG", \ |
ccb1cd1e | 2122 | "V1_REG", \ |
3c0e3fb9 | 2123 | "SPILL_REGS", \ |
c9e1a048 | 2124 | "LEA_REGS", \ |
c8829dad | 2125 | "GR_REGS", \ |
2126 | "FP_REGS", \ | |
4509d619 | 2127 | "MD0_REG", \ |
2128 | "MD1_REG", \ | |
c8829dad | 2129 | "MD_REGS", \ |
8d85666f | 2130 | /* coprocessor registers */ \ |
2131 | "COP0_REGS", \ | |
2132 | "COP2_REGS", \ | |
2133 | "COP3_REGS", \ | |
c8829dad | 2134 | "ST_REGS", \ |
b7efe757 | 2135 | "DSP_ACC_REGS", \ |
2136 | "ACC_REGS", \ | |
024f0a8a | 2137 | "FRAME_REGS", \ |
1678533f | 2138 | "GR_AND_MD0_REGS", \ |
2139 | "GR_AND_MD1_REGS", \ | |
2140 | "GR_AND_MD_REGS", \ | |
2141 | "GR_AND_ACC_REGS", \ | |
c8829dad | 2142 | "ALL_REGS" \ |
2143 | } | |
2144 | ||
2145 | /* An initializer containing the contents of the register classes, | |
2146 | as integers which are bit masks. The Nth integer specifies the | |
2147 | contents of class N. The way the integer MASK is interpreted is | |
2148 | that register R is in the class if `MASK & (1 << R)' is 1. | |
2149 | ||
2150 | When the machine has more than 32 registers, an integer does not | |
2151 | suffice. Then the integers are replaced by sub-initializers, | |
2152 | braced groupings containing several integers. Each | |
2153 | sub-initializer must be suitable as an initializer for the type | |
2154 | `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
2155 | ||
8eb3a059 | 2156 | #define REG_CLASS_CONTENTS \ |
2157 | { \ | |
1678533f | 2158 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
8deb0486 | 2159 | { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \ |
1678533f | 2160 | { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ |
3c0e3fb9 | 2161 | { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \ |
1678533f | 2162 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ |
2163 | { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ | |
2164 | { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ | |
2165 | { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ | |
3c0e3fb9 | 2166 | { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \ |
1678533f | 2167 | { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ |
2168 | { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ | |
2169 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ | |
2170 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ | |
2171 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \ | |
2172 | { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \ | |
2173 | { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \ | |
2174 | { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \ | |
2175 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \ | |
2176 | { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \ | |
2177 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \ | |
2178 | { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \ | |
2179 | { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \ | |
2180 | { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \ | |
2181 | { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \ | |
2182 | { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \ | |
2183 | { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \ | |
2184 | { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \ | |
c8829dad | 2185 | } |
2186 | ||
2187 | ||
2188 | /* A C expression whose value is a register class containing hard | |
2189 | register REGNO. In general there is more that one such class; | |
2190 | choose a class which is "minimal", meaning that no smaller class | |
2191 | also contains the register. */ | |
2192 | ||
c8829dad | 2193 | #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] |
2194 | ||
2195 | /* A macro whose definition is the name of the class to which a | |
2196 | valid base register must belong. A base register is one used in | |
2197 | an address which is the register value plus a displacement. */ | |
2198 | ||
3c0e3fb9 | 2199 | #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS) |
c8829dad | 2200 | |
2201 | /* A macro whose definition is the name of the class to which a | |
2202 | valid index register must belong. An index register is one used | |
2203 | in an address where its value is either multiplied by a scale | |
2204 | factor or added to another register (as well as added to a | |
2205 | displacement). */ | |
2206 | ||
e29b85c8 | 2207 | #define INDEX_REG_CLASS NO_REGS |
c8829dad | 2208 | |
a0fa45d8 | 2209 | /* We generally want to put call-clobbered registers ahead of |
2210 | call-saved ones. (IRA expects this.) */ | |
4ddcf2b2 | 2211 | |
2212 | #define REG_ALLOC_ORDER \ | |
867a63a5 | 2213 | { /* Accumulator registers. When GPRs and accumulators have equal \ |
2214 | cost, we generally prefer to use accumulators. For example, \ | |
2215 | a division of multiplication result is better allocated to LO, \ | |
2216 | so that we put the MFLO at the point of use instead of at the \ | |
2217 | point of definition. It's also needed if we're to take advantage \ | |
2218 | of the extra accumulators available with -mdspr2. In some cases, \ | |
2219 | it can also help to reduce register pressure. */ \ | |
2220 | 64, 65,176,177,178,179,180,181, \ | |
2221 | /* Call-clobbered GPRs. */ \ | |
2222 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
a0fa45d8 | 2223 | 24, 25, 31, \ |
2224 | /* The global pointer. This is call-clobbered for o32 and o64 \ | |
2225 | abicalls, call-saved for n32 and n64 abicalls, and a program \ | |
2226 | invariant otherwise. Putting it between the call-clobbered \ | |
2227 | and call-saved registers should cope with all eventualities. */ \ | |
2228 | 28, \ | |
2229 | /* Call-saved GPRs. */ \ | |
2230 | 16, 17, 18, 19, 20, 21, 22, 23, 30, \ | |
2231 | /* GPRs that can never be exposed to the register allocator. */ \ | |
867a63a5 | 2232 | 0, 26, 27, 29, \ |
a0fa45d8 | 2233 | /* Call-clobbered FPRs. */ \ |
4ddcf2b2 | 2234 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ |
a0fa45d8 | 2235 | 48, 49, 50, 51, \ |
2236 | /* FPRs that are usually call-saved. The odd ones are actually \ | |
2237 | call-clobbered for n32, but listing them ahead of the even \ | |
2238 | registers might encourage the register allocator to fragment \ | |
2239 | the available FPR pairs. We need paired FPRs to store long \ | |
2240 | doubles, so it isn't clear that using a different order \ | |
2241 | for n32 would be a win. */ \ | |
2242 | 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
2243 | /* None of the remaining classes have defined call-saved \ | |
2244 | registers. */ \ | |
867a63a5 | 2245 | 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ |
8d85666f | 2246 | 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ |
2247 | 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ | |
2248 | 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ | |
2249 | 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ | |
2250 | 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ | |
b7efe757 | 2251 | 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ |
867a63a5 | 2252 | 182,183,184,185,186,187 \ |
4ddcf2b2 | 2253 | } |
2254 | ||
77aa6362 | 2255 | /* True if VALUE is an unsigned 6-bit number. */ |
b7efe757 | 2256 | |
2257 | #define UIMM6_OPERAND(VALUE) \ | |
2258 | (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) | |
2259 | ||
2260 | /* True if VALUE is a signed 10-bit number. */ | |
2261 | ||
2262 | #define IMM10_OPERAND(VALUE) \ | |
2263 | ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) | |
2264 | ||
c9e1a048 | 2265 | /* True if VALUE is a signed 16-bit number. */ |
2266 | ||
2267 | #define SMALL_OPERAND(VALUE) \ | |
2268 | ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) | |
2269 | ||
2270 | /* True if VALUE is an unsigned 16-bit number. */ | |
2271 | ||
2272 | #define SMALL_OPERAND_UNSIGNED(VALUE) \ | |
2273 | (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) | |
2274 | ||
2275 | /* True if VALUE can be loaded into a register using LUI. */ | |
2276 | ||
2277 | #define LUI_OPERAND(VALUE) \ | |
2278 | (((VALUE) | 0x7fff0000) == 0x7fff0000 \ | |
2279 | || ((VALUE) | 0x7fff0000) + 0x10000 == 0) | |
2280 | ||
2281 | /* Return a value X with the low 16 bits clear, and such that | |
2282 | VALUE - X is a signed 16-bit value. */ | |
2283 | ||
2284 | #define CONST_HIGH_PART(VALUE) \ | |
2285 | (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) | |
2286 | ||
2287 | #define CONST_LOW_PART(VALUE) \ | |
2288 | ((VALUE) - CONST_HIGH_PART (VALUE)) | |
2289 | ||
2290 | #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) | |
2291 | #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) | |
2292 | #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) | |
ff9c1bc1 | 2293 | #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) |
78645e70 | 2294 | #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255)) |
c9e1a048 | 2295 | |
2fe68916 | 2296 | /* The HI and LO registers can only be reloaded via the general |
0ca99114 | 2297 | registers. Condition code registers can only be loaded to the |
2298 | general registers, and from the floating point registers. */ | |
2fe68916 | 2299 | |
fe761857 | 2300 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
a798da4d | 2301 | mips_secondary_reload_class (CLASS, MODE, X, true) |
fe761857 | 2302 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
a798da4d | 2303 | mips_secondary_reload_class (CLASS, MODE, X, false) |
2fe68916 | 2304 | |
f2b55aea | 2305 | /* When targeting the o32 FPXX ABI, all moves with a length of doubleword |
2306 | or greater must be performed by FR-mode-aware instructions. | |
2307 | This can be achieved using MFHC1/MTHC1 when these instructions are | |
2308 | available but otherwise moves must go via memory. | |
2309 | For the o32 FP64A ABI, all odd-numbered moves with a length of | |
2310 | doubleword or greater are required to use memory. Using MTC1/MFC1 | |
2311 | to access the lower-half of these registers would require a forbidden | |
2312 | single-precision access. We require all double-word moves to use | |
2313 | memory because adding even and odd floating-point registers classes | |
2314 | would have a significant impact on the backend. */ | |
2315 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
2316 | mips_secondary_memory_needed ((CLASS1), (CLASS2), (MODE)) | |
2317 | ||
c8829dad | 2318 | /* Return the maximum number of consecutive registers |
2319 | needed to represent mode MODE in a register of class CLASS. */ | |
2320 | ||
8d85666f | 2321 | #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) |
c8829dad | 2322 | |
22aae821 | 2323 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
2324 | mips_cannot_change_mode_class (FROM, TO, CLASS) | |
c8829dad | 2325 | \f |
2326 | /* Stack layout; function entry, exit and calling. */ | |
2327 | ||
2b785411 | 2328 | #define STACK_GROWS_DOWNWARD 1 |
c8829dad | 2329 | |
f9eddbcf | 2330 | #define FRAME_GROWS_DOWNWARD flag_stack_protect |
d529383e | 2331 | |
f9eddbcf | 2332 | /* Size of the area allocated in the frame to save the GP. */ |
2333 | ||
2334 | #define MIPS_GP_SAVE_AREA_SIZE \ | |
2335 | (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0) | |
2336 | ||
2337 | /* The offset of the first local variable from the frame pointer. See | |
2338 | mips_compute_frame_info for details about the frame layout. */ | |
2339 | ||
2340 | #define STARTING_FRAME_OFFSET \ | |
2341 | (FRAME_GROWS_DOWNWARD \ | |
2342 | ? 0 \ | |
2343 | : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE) | |
9f4bac70 | 2344 | |
c9e1a048 | 2345 | #define RETURN_ADDR_RTX mips_return_addr |
2b801d92 | 2346 | |
036b8c98 | 2347 | /* Mask off the MIPS16 ISA bit in unwind addresses. |
2348 | ||
2349 | The reason for this is a little subtle. When unwinding a call, | |
2350 | we are given the call's return address, which on most targets | |
2351 | is the address of the following instruction. However, what we | |
2352 | actually want to find is the EH region for the call itself. | |
2353 | The target-independent unwind code therefore searches for "RA - 1". | |
2354 | ||
2355 | In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address. | |
2356 | RA - 1 is therefore the real (even-valued) start of the return | |
2357 | instruction. EH region labels are usually odd-valued MIPS16 symbols | |
2358 | too, so a search for an even address within a MIPS16 region would | |
2359 | usually work. | |
2360 | ||
2361 | However, there is an exception. If the end of an EH region is also | |
2362 | the end of a function, the end label is allowed to be even. This is | |
2363 | necessary because a following non-MIPS16 function may also need EH | |
2364 | information for its first instruction. | |
2365 | ||
2366 | Thus a MIPS16 region may be terminated by an ISA-encoded or a | |
2367 | non-ISA-encoded address. This probably isn't ideal, but it is | |
2368 | the traditional (legacy) behavior. It is therefore only safe | |
2369 | to search MIPS EH regions for an _odd-valued_ address. | |
2370 | ||
2371 | Masking off the ISA bit means that the target-independent code | |
2372 | will search for "(RA & -2) - 1", which is guaranteed to be odd. */ | |
1a6a6dab | 2373 | #define MASK_RETURN_ADDR GEN_INT (-2) |
2374 | ||
c9e1a048 | 2375 | |
1a6a6dab | 2376 | /* Similarly, don't use the least-significant bit to tell pointers to |
2377 | code from vtable index. */ | |
2378 | ||
2379 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
2380 | ||
933d6ec0 | 2381 | /* The eliminations to $17 are only used for mips16 code. See the |
4ddcf2b2 | 2382 | definition of HARD_FRAME_POINTER_REGNUM. */ |
9f4bac70 | 2383 | |
2384 | #define ELIMINABLE_REGS \ | |
2385 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
4ddcf2b2 | 2386 | { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ |
2387 | { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ | |
4ddcf2b2 | 2388 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
2389 | { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ | |
2390 | { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} | |
9f4bac70 | 2391 | |
cfdba943 | 2392 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
933d6ec0 | 2393 | (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) |
c8829dad | 2394 | |
933d6ec0 | 2395 | /* Allocate stack space for arguments at the beginning of each function. */ |
4448f543 | 2396 | #define ACCUMULATE_OUTGOING_ARGS 1 |
c8829dad | 2397 | |
933d6ec0 | 2398 | /* The argument pointer always points to the first argument. */ |
13a452a6 | 2399 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
c8829dad | 2400 | |
933d6ec0 | 2401 | /* o32 and o64 reserve stack space for all argument registers. */ |
2402 | #define REG_PARM_STACK_SPACE(FNDECL) \ | |
93a1903e | 2403 | (TARGET_OLDABI \ |
933d6ec0 | 2404 | ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ |
efd092f3 | 2405 | : 0) |
c8829dad | 2406 | |
2407 | /* Define this if it is the responsibility of the caller to | |
08aec1b6 | 2408 | allocate the area reserved for arguments passed in registers. |
c8829dad | 2409 | If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect |
08aec1b6 | 2410 | of this macro is to determine whether the space is included in |
abe32cce | 2411 | `crtl->outgoing_args_size'. */ |
22c61100 | 2412 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
c8829dad | 2413 | |
a5ab28e7 | 2414 | #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) |
c8829dad | 2415 | \f |
c8829dad | 2416 | /* Symbolic macros for the registers used to return integer and floating |
2417 | point values. */ | |
2418 | ||
2419 | #define GP_RETURN (GP_REG_FIRST + 2) | |
2420 | #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) | |
2421 | ||
93a1903e | 2422 | #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) |
efd092f3 | 2423 | |
c8829dad | 2424 | /* Symbolic macros for the first/last argument registers. */ |
2425 | ||
2426 | #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
efd092f3 | 2427 | #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) |
c8829dad | 2428 | #define FP_ARG_FIRST (FP_REG_FIRST + 12) |
efd092f3 | 2429 | #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) |
c8829dad | 2430 | |
ddc6405a | 2431 | /* True if MODE is vector and supported in a MSA vector register. */ |
2432 | #define MSA_SUPPORTED_MODE_P(MODE) \ | |
2433 | (ISA_HAS_MSA \ | |
2434 | && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \ | |
2435 | && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \ | |
2436 | || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)) | |
2437 | ||
9d0ddb1d | 2438 | /* Temporary register that is used when restoring $gp after a call. $4 and $5 |
2439 | are used for returning complex double values in soft-float code, so $6 is the | |
2440 | first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use | |
2441 | $gp itself as the temporary. */ | |
2442 | #define POST_CALL_TMP_REG \ | |
2443 | (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM) | |
2444 | ||
60cc2ea6 | 2445 | /* 1 if N is a possible register number for function argument passing. |
f2b55aea | 2446 | We have no FP argument registers when soft-float. Special handling |
2447 | is required for O32 where only even numbered registers are used for | |
2448 | O32-FPXX and O32-FP64. */ | |
60cc2ea6 | 2449 | |
2450 | #define FUNCTION_ARG_REGNO_P(N) \ | |
b6026f5a | 2451 | ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ |
f2b55aea | 2452 | || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \ |
2453 | && (mips_abi != ABI_32 \ | |
2454 | || TARGET_FLOAT32 \ | |
2455 | || ((N) % 2 == 0)))) \ | |
b6026f5a | 2456 | && !fixed_regs[N]) |
c8829dad | 2457 | \f |
933d6ec0 | 2458 | /* This structure has to cope with two different argument allocation |
26bcab5a | 2459 | schemes. Most MIPS ABIs view the arguments as a structure, of which |
2460 | the first N words go in registers and the rest go on the stack. If I | |
2461 | < N, the Ith word might go in Ith integer argument register or in a | |
2462 | floating-point register. For these ABIs, we only need to remember | |
2463 | the offset of the current argument into the structure. | |
09a41b31 | 2464 | |
2465 | The EABI instead allocates the integer and floating-point arguments | |
2466 | separately. The first N words of FP arguments go in FP registers, | |
2467 | the rest go on the stack. Likewise, the first N words of the other | |
2468 | arguments go in integer registers, and the rest go on the stack. We | |
2469 | need to maintain three counts: the number of integer registers used, | |
2470 | the number of floating-point registers used, and the number of words | |
2471 | passed on the stack. | |
2472 | ||
2473 | We could keep separate information for the two ABIs (a word count for | |
2474 | the standard ABIs, and three separate counts for the EABI). But it | |
2475 | seems simpler to view the standard ABIs as forms of EABI that do not | |
2476 | allocate floating-point registers. | |
2477 | ||
2478 | So for the standard ABIs, the first N words are allocated to integer | |
a798da4d | 2479 | registers, and mips_function_arg decides on an argument-by-argument |
2480 | basis whether that argument should really go in an integer register, | |
2481 | or in a floating-point one. */ | |
c8829dad | 2482 | |
2483 | typedef struct mips_args { | |
09a41b31 | 2484 | /* Always true for varargs functions. Otherwise true if at least |
2485 | one argument has been passed in an integer register. */ | |
2486 | int gp_reg_found; | |
2487 | ||
2488 | /* The number of arguments seen so far. */ | |
2489 | unsigned int arg_number; | |
2490 | ||
26bcab5a | 2491 | /* The number of integer registers used so far. For all ABIs except |
2492 | EABI, this is the number of words that have been added to the | |
2493 | argument structure, limited to MAX_ARGS_IN_REGISTERS. */ | |
e87dac45 | 2494 | unsigned int num_gprs; |
09a41b31 | 2495 | |
2496 | /* For EABI, the number of floating-point registers used so far. */ | |
e87dac45 | 2497 | unsigned int num_fprs; |
09a41b31 | 2498 | |
2499 | /* The number of words passed on the stack. */ | |
2500 | unsigned int stack_words; | |
2501 | ||
2502 | /* On the mips16, we need to keep track of which floating point | |
2503 | arguments were passed in general registers, but would have been | |
c910419d | 2504 | passed in the FP regs if this were a 32-bit function, so that we |
2505 | can move them to the FP regs if we wind up calling a 32-bit | |
09a41b31 | 2506 | function. We record this information in fp_code, encoded in base |
2507 | four. A zero digit means no floating point argument, a one digit | |
2508 | means an SFmode argument, and a two digit means a DFmode argument, | |
2509 | and a three digit is not used. The low order digit is the first | |
2510 | argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by | |
2511 | an SFmode argument. ??? A more sophisticated approach will be | |
2512 | needed if MIPS_ABI != ABI_32. */ | |
2513 | int fp_code; | |
2514 | ||
2515 | /* True if the function has a prototype. */ | |
2516 | int prototype; | |
c8829dad | 2517 | } CUMULATIVE_ARGS; |
2518 | ||
2519 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2520 | for a call to a function whose data type is FNTYPE. | |
e487406e | 2521 | For a library call, FNTYPE is 0. */ |
c8829dad | 2522 | |
30c70355 | 2523 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
a798da4d | 2524 | mips_init_cumulative_args (&CUM, FNTYPE) |
c8829dad | 2525 | |
a798da4d | 2526 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
0fee47f4 | 2527 | (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) |
2528 | ||
a798da4d | 2529 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ |
0fee47f4 | 2530 | (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) |
efd092f3 | 2531 | |
09a41b31 | 2532 | /* True if using EABI and varargs can be passed in floating-point |
2533 | registers. Under these conditions, we need a more complex form | |
2534 | of va_list, which tracks GPR, FPR and stack arguments separately. */ | |
2535 | #define EABI_FLOAT_VARARGS_P \ | |
2536 | (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) | |
2537 | ||
c8829dad | 2538 | \f |
0bfaf4c4 | 2539 | #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO) |
c9e1a048 | 2540 | |
efd092f3 | 2541 | /* Treat LOC as a byte offset from the stack pointer and round it up |
2542 | to the next fully-aligned offset. */ | |
a5ab28e7 | 2543 | #define MIPS_STACK_ALIGN(LOC) \ |
63e70e28 | 2544 | (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8)) |
c8829dad | 2545 | |
2546 | \f | |
2547 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
2548 | for profiling a function entry. */ | |
2549 | ||
57bb39d9 | 2550 | #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE)) |
c8829dad | 2551 | |
68c9bc25 | 2552 | /* The profiler preserves all interesting registers, including $31. */ |
2553 | #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false | |
2554 | ||
e54b69e7 | 2555 | /* No mips port has ever used the profiler counter word, so don't emit it |
2556 | or the label for it. */ | |
2557 | ||
2558 | #define NO_PROFILE_COUNTERS 1 | |
2559 | ||
7e3176e8 | 2560 | /* Define this macro if the code for function profiling should come |
2561 | before the function prologue. Normally, the profiling code comes | |
2562 | after. */ | |
2563 | ||
2564 | /* #define PROFILE_BEFORE_PROLOGUE */ | |
2565 | ||
c8829dad | 2566 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
2567 | the stack pointer does not matter. The value is tested only in | |
2568 | functions that have frame pointers. | |
2569 | No definition is equivalent to always zero. */ | |
2570 | ||
2571 | #define EXIT_IGNORE_STACK 1 | |
2572 | ||
2573 | \f | |
eb725716 | 2574 | /* Trampolines are a block of code followed by two pointers. */ |
c8829dad | 2575 | |
eb725716 | 2576 | #define TRAMPOLINE_SIZE \ |
2577 | (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2) | |
c8829dad | 2578 | |
eb725716 | 2579 | /* Forcing a 64-bit alignment for 32-bit targets allows us to load two |
2580 | pointers from a single LUI base. */ | |
c8829dad | 2581 | |
eb725716 | 2582 | #define TRAMPOLINE_ALIGNMENT 64 |
c8829dad | 2583 | |
433e9b6a | 2584 | /* mips_trampoline_init calls this library function to flush |
220345e0 | 2585 | program and data caches. */ |
2586 | ||
2587 | #ifndef CACHE_FLUSH_FUNC | |
2588 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
2589 | #endif | |
2590 | ||
68c9bc25 | 2591 | #define MIPS_ICACHE_SYNC(ADDR, SIZE) \ |
2592 | /* Flush both caches. We need to flush the data cache in case \ | |
2593 | the system has a write-back cache. */ \ | |
2594 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ | |
9e9e5c15 | 2595 | LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \ |
68c9bc25 | 2596 | GEN_INT (3), TYPE_MODE (integer_type_node)) |
2597 | ||
c8829dad | 2598 | \f |
2599 | /* Addressing modes, and classification of registers for them. */ | |
2600 | ||
5b1aef3e | 2601 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 |
2602 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
2603 | mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) | |
c8829dad | 2604 | \f |
2605 | /* Maximum number of registers that can appear in a valid memory address. */ | |
2606 | ||
2607 | #define MAX_REGS_PER_ADDRESS 1 | |
2608 | ||
c9e1a048 | 2609 | /* Check for constness inline but use mips_legitimate_address_p |
2610 | to check whether a constant really is an address. */ | |
2611 | ||
2612 | #define CONSTANT_ADDRESS_P(X) \ | |
fd50b071 | 2613 | (CONSTANT_P (X) && memory_address_p (SImode, X)) |
c9e1a048 | 2614 | |
2cf63cd9 | 2615 | /* This handles the magic '..CURRENT_FUNCTION' symbol, which means |
2616 | 'the start of the function that this code is output in'. */ | |
2617 | ||
2618 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
2619 | if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
2620 | asm_fprintf ((FILE), "%U%s", \ | |
2621 | XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ | |
2622 | else \ | |
2623 | asm_fprintf ((FILE), "%U%s", (NAME)) | |
c8829dad | 2624 | \f |
3d375286 | 2625 | /* Flag to mark a function decl symbol that requires a long call. */ |
2626 | #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) | |
2627 | #define SYMBOL_REF_LONG_CALL_P(X) \ | |
2628 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) | |
2629 | ||
559b0712 | 2630 | /* This flag marks functions that cannot be lazily bound. */ |
2631 | #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) | |
2632 | #define SYMBOL_REF_BIND_NOW_P(RTX) \ | |
2633 | ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) | |
2634 | ||
f02776dd | 2635 | /* True if we're generating a form of MIPS16 code in which jump tables |
2636 | are stored in the text section and encoded as 16-bit PC-relative | |
2637 | offsets. This is only possible when general text loads are allowed, | |
4db9805e | 2638 | since the table access itself will be an "lh" instruction. If the |
2639 | PC-relative offsets grow too large, 32-bit offsets are used instead. */ | |
f02776dd | 2640 | #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS |
4ddcf2b2 | 2641 | |
f02776dd | 2642 | #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES |
2643 | ||
7df01788 | 2644 | #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode) |
4db9805e | 2645 | |
2646 | /* Only use short offsets if their range will not overflow. */ | |
2647 | #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \ | |
7df01788 | 2648 | (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \ |
2649 | : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \ | |
2650 | : SImode) | |
f02776dd | 2651 | |
2652 | #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES | |
c8829dad | 2653 | |
c8829dad | 2654 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
779e55fe | 2655 | #ifndef DEFAULT_SIGNED_CHAR |
c8829dad | 2656 | #define DEFAULT_SIGNED_CHAR 1 |
779e55fe | 2657 | #endif |
c8829dad | 2658 | |
959fd5af | 2659 | /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets, |
2660 | we generally don't want to use them for copying arbitrary data. | |
2661 | A single N-word move is usually the same cost as N single-word moves. */ | |
2662 | #define MOVE_MAX UNITS_PER_WORD | |
ddc6405a | 2663 | /* We don't modify it for MSA as it is only used by the classic reload. */ |
e29b85c8 | 2664 | #define MAX_MOVE_MAX 8 |
c8829dad | 2665 | |
2666 | /* Define this macro as a C expression which is nonzero if | |
2667 | accessing less than a word of memory (i.e. a `char' or a | |
2668 | `short') is no faster than accessing a word of memory, i.e., if | |
2669 | such access require more than one instruction or if there is no | |
2670 | difference in cost between byte and (aligned) word loads. | |
2671 | ||
2672 | On RISC machines, it tends to generate better code to define | |
5ee52cdb | 2673 | this as 1, since it avoids making a QI or HI mode register. |
2674 | ||
2675 | But, generating word accesses for -mips16 is generally bad as shifts | |
2676 | (often extended) would be needed for byte accesses. */ | |
2677 | #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) | |
c8829dad | 2678 | |
cfa9c500 | 2679 | /* Standard MIPS integer shifts truncate the shift amount to the |
2680 | width of the shifted operand. However, Loongson vector shifts | |
2681 | do not truncate the shift amount at all. */ | |
f755482b | 2682 | #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS) |
c8829dad | 2683 | |
2684 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2685 | is done just by pretending it is already truncated. */ | |
e29b85c8 | 2686 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ |
2687 | (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) | |
c8829dad | 2688 | |
c9e1a048 | 2689 | |
c8829dad | 2690 | /* Specify the machine mode that pointers have. |
2691 | After generation of rtl, the compiler makes no further distinction | |
c9e1a048 | 2692 | between pointers and any other objects of this machine mode. */ |
e29b85c8 | 2693 | |
7a9d1fec | 2694 | #ifndef Pmode |
c9e1a048 | 2695 | #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) |
7a9d1fec | 2696 | #endif |
c8829dad | 2697 | |
c9e1a048 | 2698 | /* Give call MEMs SImode since it is the "most permissive" mode |
2699 | for both 32-bit and 64-bit targets. */ | |
c8829dad | 2700 | |
c9e1a048 | 2701 | #define FUNCTION_MODE SImode |
c8829dad | 2702 | |
c8829dad | 2703 | \f |
554bbdba | 2704 | /* We allocate $fcc registers by hand and can't cope with moves of |
2705 | CCmode registers to and from pseudos (or memory). */ | |
18aa2adf | 2706 | #define AVOID_CCMODE_COPIES |
2707 | ||
c8829dad | 2708 | /* A C expression for the cost of a branch instruction. A value of |
2709 | 1 is the default; other values are interpreted relative to that. */ | |
2710 | ||
4a9d7ef7 | 2711 | #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost |
9ddd79fc | 2712 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
c8829dad | 2713 | |
6bb79546 | 2714 | /* The MIPS port has several functions that return an instruction count. |
2715 | Multiplying the count by this value gives the number of bytes that | |
2716 | the instructions occupy. */ | |
2717 | #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4) | |
2718 | ||
2719 | /* The length of a NOP in bytes. */ | |
2720 | #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4) | |
2721 | ||
17695875 | 2722 | /* If defined, modifies the length assigned to instruction INSN as a |
2723 | function of the context in which it is used. LENGTH is an lvalue | |
2724 | that contains the initially computed length of the insn and should | |
2725 | be updated with the correct length of the insn. */ | |
2726 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
2727 | ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) | |
fe2ed30d | 2728 | |
2729 | /* Return the asm template for a non-MIPS16 conditional branch instruction. | |
2730 | OPCODE is the opcode's mnemonic and OPERANDS is the asm template for | |
2731 | its operands. */ | |
2732 | #define MIPS_BRANCH(OPCODE, OPERANDS) \ | |
2733 | "%*" OPCODE "%?\t" OPERANDS "%/" | |
1b6b10a9 | 2734 | |
59449ca9 | 2735 | #define MIPS_BRANCH_C(OPCODE, OPERANDS) \ |
2736 | "%*" OPCODE "%:\t" OPERANDS | |
2737 | ||
74facf6e | 2738 | /* Return an asm string that forces INSN to be treated as an absolute |
2739 | J or JAL instruction instead of an assembler macro. */ | |
2740 | #define MIPS_ABSOLUTE_JUMP(INSN) \ | |
2741 | (TARGET_ABICALLS_PIC2 \ | |
2742 | ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \ | |
2743 | : INSN) | |
2744 | ||
c8829dad | 2745 | \f |
2746 | /* Control the assembler format that we output. */ | |
2747 | ||
c8829dad | 2748 | /* Output to assembler file text saying following lines |
2749 | may contain character constants, extra white space, comments, etc. */ | |
2750 | ||
71d957f9 | 2751 | #ifndef ASM_APP_ON |
c8829dad | 2752 | #define ASM_APP_ON " #APP\n" |
71d957f9 | 2753 | #endif |
c8829dad | 2754 | |
2755 | /* Output to assembler file text saying following lines | |
2756 | no longer contain unusual constructs. */ | |
2757 | ||
71d957f9 | 2758 | #ifndef ASM_APP_OFF |
c8829dad | 2759 | #define ASM_APP_OFF " #NO_APP\n" |
71d957f9 | 2760 | #endif |
c8829dad | 2761 | |
dbc6b055 | 2762 | #define REGISTER_NAMES \ |
2763 | { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ | |
2764 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
2765 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
2766 | "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ | |
2767 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ | |
2768 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
2769 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ | |
2770 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ | |
2771 | "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ | |
74facf6e | 2772 | "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \ |
dbc6b055 | 2773 | "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ |
2774 | "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ | |
2775 | "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ | |
2776 | "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ | |
2777 | "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ | |
2778 | "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ | |
2779 | "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ | |
2780 | "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ | |
2781 | "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ | |
2782 | "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ | |
2783 | "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ | |
b7efe757 | 2784 | "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ |
2785 | "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ | |
2786 | "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } | |
dbc6b055 | 2787 | |
2788 | /* List the "software" names for each register. Also list the numerical | |
2789 | names for $fp and $sp. */ | |
c8829dad | 2790 | |
2791 | #define ADDITIONAL_REGISTER_NAMES \ | |
2792 | { \ | |
c8829dad | 2793 | { "$29", 29 + GP_REG_FIRST }, \ |
2794 | { "$30", 30 + GP_REG_FIRST }, \ | |
c8829dad | 2795 | { "at", 1 + GP_REG_FIRST }, \ |
2796 | { "v0", 2 + GP_REG_FIRST }, \ | |
2797 | { "v1", 3 + GP_REG_FIRST }, \ | |
2798 | { "a0", 4 + GP_REG_FIRST }, \ | |
2799 | { "a1", 5 + GP_REG_FIRST }, \ | |
2800 | { "a2", 6 + GP_REG_FIRST }, \ | |
2801 | { "a3", 7 + GP_REG_FIRST }, \ | |
2802 | { "t0", 8 + GP_REG_FIRST }, \ | |
2803 | { "t1", 9 + GP_REG_FIRST }, \ | |
2804 | { "t2", 10 + GP_REG_FIRST }, \ | |
2805 | { "t3", 11 + GP_REG_FIRST }, \ | |
2806 | { "t4", 12 + GP_REG_FIRST }, \ | |
2807 | { "t5", 13 + GP_REG_FIRST }, \ | |
2808 | { "t6", 14 + GP_REG_FIRST }, \ | |
2809 | { "t7", 15 + GP_REG_FIRST }, \ | |
2810 | { "s0", 16 + GP_REG_FIRST }, \ | |
2811 | { "s1", 17 + GP_REG_FIRST }, \ | |
2812 | { "s2", 18 + GP_REG_FIRST }, \ | |
2813 | { "s3", 19 + GP_REG_FIRST }, \ | |
2814 | { "s4", 20 + GP_REG_FIRST }, \ | |
2815 | { "s5", 21 + GP_REG_FIRST }, \ | |
2816 | { "s6", 22 + GP_REG_FIRST }, \ | |
2817 | { "s7", 23 + GP_REG_FIRST }, \ | |
2818 | { "t8", 24 + GP_REG_FIRST }, \ | |
2819 | { "t9", 25 + GP_REG_FIRST }, \ | |
2820 | { "k0", 26 + GP_REG_FIRST }, \ | |
2821 | { "k1", 27 + GP_REG_FIRST }, \ | |
2822 | { "gp", 28 + GP_REG_FIRST }, \ | |
2823 | { "sp", 29 + GP_REG_FIRST }, \ | |
2824 | { "fp", 30 + GP_REG_FIRST }, \ | |
ddc6405a | 2825 | { "ra", 31 + GP_REG_FIRST }, \ |
2826 | { "$w0", 0 + FP_REG_FIRST }, \ | |
2827 | { "$w1", 1 + FP_REG_FIRST }, \ | |
2828 | { "$w2", 2 + FP_REG_FIRST }, \ | |
2829 | { "$w3", 3 + FP_REG_FIRST }, \ | |
2830 | { "$w4", 4 + FP_REG_FIRST }, \ | |
2831 | { "$w5", 5 + FP_REG_FIRST }, \ | |
2832 | { "$w6", 6 + FP_REG_FIRST }, \ | |
2833 | { "$w7", 7 + FP_REG_FIRST }, \ | |
2834 | { "$w8", 8 + FP_REG_FIRST }, \ | |
2835 | { "$w9", 9 + FP_REG_FIRST }, \ | |
2836 | { "$w10", 10 + FP_REG_FIRST }, \ | |
2837 | { "$w11", 11 + FP_REG_FIRST }, \ | |
2838 | { "$w12", 12 + FP_REG_FIRST }, \ | |
2839 | { "$w13", 13 + FP_REG_FIRST }, \ | |
2840 | { "$w14", 14 + FP_REG_FIRST }, \ | |
2841 | { "$w15", 15 + FP_REG_FIRST }, \ | |
2842 | { "$w16", 16 + FP_REG_FIRST }, \ | |
2843 | { "$w17", 17 + FP_REG_FIRST }, \ | |
2844 | { "$w18", 18 + FP_REG_FIRST }, \ | |
2845 | { "$w19", 19 + FP_REG_FIRST }, \ | |
2846 | { "$w20", 20 + FP_REG_FIRST }, \ | |
2847 | { "$w21", 21 + FP_REG_FIRST }, \ | |
2848 | { "$w22", 22 + FP_REG_FIRST }, \ | |
2849 | { "$w23", 23 + FP_REG_FIRST }, \ | |
2850 | { "$w24", 24 + FP_REG_FIRST }, \ | |
2851 | { "$w25", 25 + FP_REG_FIRST }, \ | |
2852 | { "$w26", 26 + FP_REG_FIRST }, \ | |
2853 | { "$w27", 27 + FP_REG_FIRST }, \ | |
2854 | { "$w28", 28 + FP_REG_FIRST }, \ | |
2855 | { "$w29", 29 + FP_REG_FIRST }, \ | |
2856 | { "$w30", 30 + FP_REG_FIRST }, \ | |
2857 | { "$w31", 31 + FP_REG_FIRST } \ | |
c8829dad | 2858 | } |
2859 | ||
c8829dad | 2860 | #define DBR_OUTPUT_SEQEND(STREAM) \ |
2861 | do \ | |
2862 | { \ | |
0a54d56a | 2863 | /* Undo the effect of '%*'. */ \ |
2864 | mips_pop_asm_switch (&mips_nomacro); \ | |
2865 | mips_pop_asm_switch (&mips_noreorder); \ | |
2866 | /* Emit a blank line after the delay slot for emphasis. */ \ | |
c8829dad | 2867 | fputs ("\n", STREAM); \ |
2868 | } \ | |
2869 | while (0) | |
2870 | ||
9e042f31 | 2871 | /* The MIPS implementation uses some labels for its own purpose. The |
c8829dad | 2872 | following lists what labels are created, and are all formed by the |
2873 | pattern $L[a-z].*. The machine independent portion of GCC creates | |
2874 | labels matching: $L[A-Z][0-9]+ and $L[0-9]+. | |
2875 | ||
b550e058 | 2876 | LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. |
c8829dad | 2877 | $Lb[0-9]+ Begin blocks for MIPS debug support |
2878 | $Lc[0-9]+ Label for use in s<xx> operation. | |
c060279b | 2879 | $Le[0-9]+ End blocks for MIPS debug support */ |
c8829dad | 2880 | |
cd16e7b6 | 2881 | #undef ASM_DECLARE_OBJECT_NAME |
592ea28a | 2882 | #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ |
fb80456a | 2883 | mips_declare_object (STREAM, NAME, "", ":\n") |
904c9ae7 | 2884 | |
0036ad94 | 2885 | /* Globalizing directive for a label. */ |
2886 | #define GLOBAL_ASM_OP "\t.globl\t" | |
c8829dad | 2887 | |
904c9ae7 | 2888 | /* This says how to define a global common symbol. */ |
c8829dad | 2889 | |
31b5e645 | 2890 | #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common |
c8829dad | 2891 | |
a361b456 | 2892 | /* This says how to define a local common symbol (i.e., not visible to |
904c9ae7 | 2893 | linker). */ |
c8829dad | 2894 | |
97a4eb3d | 2895 | #ifndef ASM_OUTPUT_ALIGNED_LOCAL |
2896 | #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ | |
2897 | mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) | |
2898 | #endif | |
c8829dad | 2899 | |
2900 | /* This says how to output an external. It would be possible not to | |
2901 | output anything and let undefined symbol become external. However | |
2902 | the assembler uses length information on externals to allocate in | |
2903 | data/sdata bss/sbss, thereby saving exec time. */ | |
2904 | ||
a9a4d6d9 | 2905 | #undef ASM_OUTPUT_EXTERNAL |
c8829dad | 2906 | #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ |
2907 | mips_output_external(STREAM,DECL,NAME) | |
2908 | ||
c8829dad | 2909 | /* This is how to declare a function name. The actual work of |
2910 | emitting the label is moved to function_prologue, so that we can | |
2911 | get the line number correctly emitted before the .ent directive, | |
61ab9ea9 | 2912 | and after any .file directives. Define as empty so that the function |
6a59b91a | 2913 | is not declared before the .ent directive elsewhere. */ |
2914 | ||
cd16e7b6 | 2915 | #undef ASM_DECLARE_FUNCTION_NAME |
c060279b | 2916 | #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) |
6a59b91a | 2917 | |
c8829dad | 2918 | /* This is how to store into the string LABEL |
2919 | the symbol_ref name of an internal numbered label where | |
2920 | PREFIX is the class of label and NUM is the number within the class. | |
2921 | This is suitable for output with `assemble_name'. */ | |
2922 | ||
cd16e7b6 | 2923 | #undef ASM_GENERATE_INTERNAL_LABEL |
c8829dad | 2924 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
02da6382 | 2925 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) |
c8829dad | 2926 | |
95a3a85e | 2927 | /* Print debug labels as "foo = ." rather than "foo:" because they should |
2928 | represent a byte pointer rather than an ISA-encoded address. This is | |
2929 | particularly important for code like: | |
2930 | ||
2931 | $LFBxxx = . | |
2932 | .cfi_startproc | |
2933 | ... | |
2934 | .section .gcc_except_table,... | |
2935 | ... | |
2936 | .uleb128 foo-$LFBxxx | |
2937 | ||
2938 | The .uleb128 requies $LFBxxx to match the FDE start address, which is | |
2939 | likewise a byte pointer rather than an ISA-encoded address. | |
2940 | ||
2941 | At the time of writing, this hook is not used for the function end | |
2942 | label: | |
2943 | ||
2944 | $LFExxx: | |
2945 | .end foo | |
2946 | ||
2947 | But this doesn't matter, because GAS doesn't treat a pre-.end label | |
2948 | as a MIPS16 one anyway. */ | |
2949 | ||
2950 | #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ | |
2951 | fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) | |
2952 | ||
c8829dad | 2953 | /* This is how to output an element of a case-vector that is absolute. */ |
2954 | ||
2955 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
34a7f2a4 | 2956 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
c9e1a048 | 2957 | ptr_mode == DImode ? ".dword" : ".word", \ |
34a7f2a4 | 2958 | LOCAL_LABEL_PREFIX, \ |
e29b85c8 | 2959 | VALUE) |
c8829dad | 2960 | |
364dfbc0 | 2961 | /* This is how to output an element of a case-vector. We can make the |
2962 | entries PC-relative in MIPS16 code and GP-relative when .gp(d)word | |
2963 | is supported. */ | |
c8829dad | 2964 | |
9eaab178 | 2965 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
82b0e8e5 | 2966 | do { \ |
f02776dd | 2967 | if (TARGET_MIPS16_SHORT_JUMP_TABLES) \ |
4db9805e | 2968 | { \ |
2969 | if (GET_MODE (BODY) == HImode) \ | |
2970 | fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ | |
2971 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
2972 | else \ | |
2973 | fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ | |
2974 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
2975 | } \ | |
c9e1a048 | 2976 | else if (TARGET_GPWORD) \ |
34a7f2a4 | 2977 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
c9e1a048 | 2978 | ptr_mode == DImode ? ".gpdword" : ".gpword", \ |
34a7f2a4 | 2979 | LOCAL_LABEL_PREFIX, VALUE); \ |
a8a393cb | 2980 | else if (TARGET_RTP_PIC) \ |
2981 | { \ | |
2982 | /* Make the entry relative to the start of the function. */ \ | |
2983 | rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \ | |
2984 | fprintf (STREAM, "\t%s\t%sL%d-", \ | |
2985 | Pmode == DImode ? ".dword" : ".word", \ | |
2986 | LOCAL_LABEL_PREFIX, VALUE); \ | |
2987 | assemble_name (STREAM, XSTR (fnsym, 0)); \ | |
2988 | fprintf (STREAM, "\n"); \ | |
2989 | } \ | |
37727f6d | 2990 | else \ |
6c51b52b | 2991 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
c9e1a048 | 2992 | ptr_mode == DImode ? ".dword" : ".word", \ |
6c51b52b | 2993 | LOCAL_LABEL_PREFIX, VALUE); \ |
82b0e8e5 | 2994 | } while (0) |
2995 | ||
35293eb1 | 2996 | /* Mark inline jump tables as data for the purpose of disassembly. For |
2997 | simplicity embed the jump table's label number in the local symbol | |
2998 | produced so that multiple jump tables within a single function end | |
2999 | up marked with unique symbols. Retain the alignment setting from | |
3000 | `elfos.h' as we are replacing the definition from there. */ | |
3001 | ||
3002 | #undef ASM_OUTPUT_BEFORE_CASE_LABEL | |
3003 | #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \ | |
3004 | do \ | |
3005 | { \ | |
3006 | ASM_OUTPUT_ALIGN ((STREAM), 2); \ | |
3007 | if (JUMP_TABLES_IN_TEXT_SECTION) \ | |
3008 | mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \ | |
3009 | } \ | |
3010 | while (0); | |
3011 | ||
3012 | /* Reset text marking to code after an inline jump table. Like with | |
3013 | the beginning of a jump table use the label number to keep symbols | |
3014 | unique. */ | |
3015 | ||
3016 | #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \ | |
3017 | do \ | |
3018 | if (JUMP_TABLES_IN_TEXT_SECTION) \ | |
3019 | mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \ | |
3020 | while (0); | |
3021 | ||
c8829dad | 3022 | /* This is how to output an assembler line |
3023 | that says to advance the location counter | |
3024 | to a multiple of 2**LOG bytes. */ | |
3025 | ||
3026 | #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
c84a4504 | 3027 | fprintf (STREAM, "\t.align\t%d\n", (LOG)) |
c8829dad | 3028 | |
3398e91d | 3029 | /* This is how to output an assembler line to advance the location |
c8829dad | 3030 | counter by SIZE bytes. */ |
3031 | ||
cd16e7b6 | 3032 | #undef ASM_OUTPUT_SKIP |
c8829dad | 3033 | #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ |
f03df321 | 3034 | fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
c8829dad | 3035 | |
c8829dad | 3036 | /* This is how to output a string. */ |
cd16e7b6 | 3037 | #undef ASM_OUTPUT_ASCII |
a798da4d | 3038 | #define ASM_OUTPUT_ASCII mips_output_ascii |
c8829dad | 3039 | |
c8829dad | 3040 | \f |
8963a639 | 3041 | /* Default to -G 8 */ |
3042 | #ifndef MIPS_DEFAULT_GVALUE | |
3043 | #define MIPS_DEFAULT_GVALUE 8 | |
3044 | #endif | |
c8829dad | 3045 | |
490085e5 | 3046 | /* Define the strings to put out for each section in the object file. */ |
3047 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
3048 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
858ac7b9 | 3049 | |
3050 | #undef READONLY_DATA_SECTION_ASM_OP | |
6cde52a2 | 3051 | #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ |
c8829dad | 3052 | \f |
c8829dad | 3053 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ |
3054 | do \ | |
3055 | { \ | |
c865346a | 3056 | fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ |
3057 | TARGET_64BIT ? "daddiu" : "addiu", \ | |
c8829dad | 3058 | reg_names[STACK_POINTER_REGNUM], \ |
3059 | reg_names[STACK_POINTER_REGNUM], \ | |
e29b85c8 | 3060 | TARGET_64BIT ? "sd" : "sw", \ |
c8829dad | 3061 | reg_names[REGNO], \ |
3062 | reg_names[STACK_POINTER_REGNUM]); \ | |
3063 | } \ | |
3064 | while (0) | |
3065 | ||
3066 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ | |
3067 | do \ | |
3068 | { \ | |
0a54d56a | 3069 | mips_push_asm_switch (&mips_noreorder); \ |
e29b85c8 | 3070 | fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ |
3071 | TARGET_64BIT ? "ld" : "lw", \ | |
c8829dad | 3072 | reg_names[REGNO], \ |
3073 | reg_names[STACK_POINTER_REGNUM], \ | |
e29b85c8 | 3074 | TARGET_64BIT ? "daddu" : "addu", \ |
c8829dad | 3075 | reg_names[STACK_POINTER_REGNUM], \ |
3076 | reg_names[STACK_POINTER_REGNUM]); \ | |
0a54d56a | 3077 | mips_pop_asm_switch (&mips_noreorder); \ |
c8829dad | 3078 | } \ |
3079 | while (0) | |
3080 | ||
3d207e9d | 3081 | /* How to start an assembler comment. |
3082 | The leading space is important (the mips native assembler requires it). */ | |
c8829dad | 3083 | #ifndef ASM_COMMENT_START |
3d207e9d | 3084 | #define ASM_COMMENT_START " #" |
c8829dad | 3085 | #endif |
9df6b43a | 3086 | \f |
ec2603a9 | 3087 | #undef SIZE_TYPE |
c9e1a048 | 3088 | #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") |
9df6b43a | 3089 | |
ec2603a9 | 3090 | #undef PTRDIFF_TYPE |
c9e1a048 | 3091 | #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") |
4b297e2e | 3092 | |
1731ea58 | 3093 | /* The minimum alignment of any expanded block move. */ |
3094 | #define MIPS_MIN_MOVE_MEM_ALIGN 16 | |
3095 | ||
959fd5af | 3096 | /* The maximum number of bytes that can be copied by one iteration of |
3097 | a movmemsi loop; see mips_block_move_loop. */ | |
3098 | #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ | |
3099 | (UNITS_PER_WORD * 4) | |
3100 | ||
3101 | /* The maximum number of bytes that can be copied by a straight-line | |
3102 | implementation of movmemsi; see mips_block_move_straight. We want | |
3103 | to make sure that any loop-based implementation will iterate at | |
3104 | least twice. */ | |
3105 | #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ | |
3106 | (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) | |
3107 | ||
4b297e2e | 3108 | /* The base cost of a memcpy call, for MOVE_RATIO and friends. These |
3109 | values were determined experimentally by benchmarking with CSiBE. | |
3110 | In theory, the call overhead is higher for TARGET_ABICALLS (especially | |
3111 | for o32 where we have to restore $gp afterwards as well as make an | |
3112 | indirect call), but in practice, bumping this up higher for | |
3113 | TARGET_ABICALLS doesn't make much difference to code size. */ | |
3114 | ||
3115 | #define MIPS_CALL_RATIO 8 | |
3116 | ||
959fd5af | 3117 | /* Any loop-based implementation of movmemsi will have at least |
3118 | MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory | |
3119 | moves, so allow individual copies of fewer elements. | |
3120 | ||
3121 | When movmemsi is not available, use a value approximating | |
3122 | the length of a memcpy call sequence, so that move_by_pieces | |
3123 | will generate inline code if it is shorter than a function call. | |
3124 | Since move_by_pieces_ninsns counts memory-to-memory moves, but | |
3125 | we'll have to generate a load/store pair for each, halve the | |
3126 | value of MIPS_CALL_RATIO to take that into account. */ | |
3127 | ||
f5733e7c | 3128 | #define MOVE_RATIO(speed) \ |
959fd5af | 3129 | (HAVE_movmemsi \ |
3130 | ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ | |
3131 | : MIPS_CALL_RATIO / 2) | |
3132 | ||
4b297e2e | 3133 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate |
3134 | of the length of a memset call, but use the default otherwise. */ | |
3135 | ||
f5733e7c | 3136 | #define CLEAR_RATIO(speed)\ |
3137 | ((speed) ? 15 : MIPS_CALL_RATIO) | |
4b297e2e | 3138 | |
3139 | /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
3140 | optimizing for size adjust the ratio to account for the overhead of | |
3141 | loading the constant and replicating it across the word. */ | |
3142 | ||
f5733e7c | 3143 | #define SET_RATIO(speed) \ |
3144 | ((speed) ? 15 : MIPS_CALL_RATIO - 2) | |
4ddcf2b2 | 3145 | \f |
f5d86738 | 3146 | /* Since the bits of the _init and _fini function is spread across |
3147 | many object files, each potentially with its own GP, we must assume | |
3148 | we need to load our GP. We don't preserve $gp or $ra, since each | |
3149 | init/fini chunk is supposed to initialize $gp, and crti/crtn | |
3150 | already take care of preserving $ra and, when appropriate, $gp. */ | |
2a5f9ffc | 3151 | #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) |
f5d86738 | 3152 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
3153 | asm (SECTION_OP "\n\ | |
5780132c | 3154 | .set push\n\ |
3155 | .set nomips16\n\ | |
f5d86738 | 3156 | .set noreorder\n\ |
3157 | bal 1f\n\ | |
3158 | nop\n\ | |
3159 | 1: .cpload $31\n\ | |
3160 | .set reorder\n\ | |
3e42171c | 3161 | la $25, " USER_LABEL_PREFIX #FUNC "\n\ |
3162 | jalr $25\n\ | |
5780132c | 3163 | .set pop\n\ |
f5d86738 | 3164 | " TEXT_SECTION_ASM_OP); |
3e42171c | 3165 | #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32) |
f5d86738 | 3166 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
3167 | asm (SECTION_OP "\n\ | |
5780132c | 3168 | .set push\n\ |
3169 | .set nomips16\n\ | |
f5d86738 | 3170 | .set noreorder\n\ |
3171 | bal 1f\n\ | |
3172 | nop\n\ | |
3173 | 1: .set reorder\n\ | |
3174 | .cpsetup $31, $2, 1b\n\ | |
3e42171c | 3175 | la $25, " USER_LABEL_PREFIX #FUNC "\n\ |
3176 | jalr $25\n\ | |
3177 | .set pop\n\ | |
3178 | " TEXT_SECTION_ASM_OP); | |
3179 | #elif (defined _ABI64 && _MIPS_SIM == _ABI64) | |
3180 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
3181 | asm (SECTION_OP "\n\ | |
3182 | .set push\n\ | |
3183 | .set nomips16\n\ | |
3184 | .set noreorder\n\ | |
3185 | bal 1f\n\ | |
3186 | nop\n\ | |
3187 | 1: .set reorder\n\ | |
3188 | .cpsetup $31, $2, 1b\n\ | |
3189 | dla $25, " USER_LABEL_PREFIX #FUNC "\n\ | |
3190 | jalr $25\n\ | |
5780132c | 3191 | .set pop\n\ |
f5d86738 | 3192 | " TEXT_SECTION_ASM_OP); |
3193 | #endif | |
42bdde4b | 3194 | |
3195 | #ifndef HAVE_AS_TLS | |
3196 | #define HAVE_AS_TLS 0 | |
3197 | #endif | |
e5ee2a85 | 3198 | |
0bd32132 | 3199 | #ifndef HAVE_AS_NAN |
3200 | #define HAVE_AS_NAN 0 | |
3201 | #endif | |
3202 | ||
3c73affd | 3203 | #ifndef USED_FOR_TARGET |
0a54d56a | 3204 | /* Information about ".set noFOO; ...; .set FOO" blocks. */ |
3205 | struct mips_asm_switch { | |
3206 | /* The FOO in the description above. */ | |
3207 | const char *name; | |
3208 | ||
3209 | /* The current block nesting level, or 0 if we aren't in a block. */ | |
3210 | int nesting_level; | |
3211 | }; | |
3212 | ||
3c73affd | 3213 | extern const enum reg_class mips_regno_to_class[]; |
3c73affd | 3214 | extern const char *current_function_file; /* filename current function is in */ |
3215 | extern int num_source_filenames; /* current .file # */ | |
0a54d56a | 3216 | extern struct mips_asm_switch mips_noreorder; |
3217 | extern struct mips_asm_switch mips_nomacro; | |
3218 | extern struct mips_asm_switch mips_noat; | |
3c73affd | 3219 | extern int mips_dbx_regno[]; |
3220 | extern int mips_dwarf_regno[]; | |
3221 | extern bool mips_split_p[]; | |
559b0712 | 3222 | extern bool mips_split_hi_p[]; |
a657080a | 3223 | extern bool mips_use_pcrel_pool_p[]; |
3224 | extern const char *mips_lo_relocs[]; | |
3225 | extern const char *mips_hi_relocs[]; | |
5d54fceb | 3226 | extern enum processor mips_arch; /* which cpu to codegen for */ |
3227 | extern enum processor mips_tune; /* which cpu to schedule for */ | |
3c73affd | 3228 | extern int mips_isa; /* architectural level */ |
95faea77 | 3229 | extern int mips_isa_rev; |
3c73affd | 3230 | extern const struct mips_cpu_info *mips_arch_info; |
3231 | extern const struct mips_cpu_info *mips_tune_info; | |
ff9c1bc1 | 3232 | extern unsigned int mips_base_compression_flags; |
07f1949b | 3233 | extern GTY(()) struct target_globals *mips16_globals; |
60b5d25f | 3234 | extern GTY(()) struct target_globals *micromips_globals; |
0c9081e8 | 3235 | |
3236 | /* Information about a function's frame layout. */ | |
3237 | struct GTY(()) mips_frame_info { | |
3238 | /* The size of the frame in bytes. */ | |
3239 | HOST_WIDE_INT total_size; | |
3240 | ||
3241 | /* The number of bytes allocated to variables. */ | |
3242 | HOST_WIDE_INT var_size; | |
3243 | ||
3244 | /* The number of bytes allocated to outgoing function arguments. */ | |
3245 | HOST_WIDE_INT args_size; | |
3246 | ||
3247 | /* The number of bytes allocated to the .cprestore slot, or 0 if there | |
3248 | is no such slot. */ | |
3249 | HOST_WIDE_INT cprestore_size; | |
3250 | ||
3251 | /* Bit X is set if the function saves or restores GPR X. */ | |
3252 | unsigned int mask; | |
3253 | ||
3254 | /* Likewise FPR X. */ | |
3255 | unsigned int fmask; | |
3256 | ||
3257 | /* Likewise doubleword accumulator X ($acX). */ | |
3258 | unsigned int acc_mask; | |
3259 | ||
3260 | /* The number of GPRs, FPRs, doubleword accumulators and COP0 | |
3261 | registers saved. */ | |
3262 | unsigned int num_gp; | |
3263 | unsigned int num_fp; | |
3264 | unsigned int num_acc; | |
3265 | unsigned int num_cop0_regs; | |
3266 | ||
3267 | /* The offset of the topmost GPR, FPR, accumulator and COP0-register | |
3268 | save slots from the top of the frame, or zero if no such slots are | |
3269 | needed. */ | |
3270 | HOST_WIDE_INT gp_save_offset; | |
3271 | HOST_WIDE_INT fp_save_offset; | |
3272 | HOST_WIDE_INT acc_save_offset; | |
3273 | HOST_WIDE_INT cop0_save_offset; | |
3274 | ||
3275 | /* Likewise, but giving offsets from the bottom of the frame. */ | |
3276 | HOST_WIDE_INT gp_sp_offset; | |
3277 | HOST_WIDE_INT fp_sp_offset; | |
3278 | HOST_WIDE_INT acc_sp_offset; | |
3279 | HOST_WIDE_INT cop0_sp_offset; | |
3280 | ||
3281 | /* Similar, but the value passed to _mcount. */ | |
3282 | HOST_WIDE_INT ra_fp_offset; | |
3283 | ||
3284 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ | |
3285 | HOST_WIDE_INT arg_pointer_offset; | |
3286 | ||
3287 | /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ | |
3288 | HOST_WIDE_INT hard_frame_pointer_offset; | |
3289 | }; | |
3290 | ||
3291 | /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */ | |
3292 | enum mips_int_mask | |
3293 | { | |
3294 | INT_MASK_EIC = -1, | |
3295 | INT_MASK_SW0 = 0, | |
3296 | INT_MASK_SW1 = 1, | |
3297 | INT_MASK_HW0 = 2, | |
3298 | INT_MASK_HW1 = 3, | |
3299 | INT_MASK_HW2 = 4, | |
3300 | INT_MASK_HW3 = 5, | |
3301 | INT_MASK_HW4 = 6, | |
3302 | INT_MASK_HW5 = 7 | |
3303 | }; | |
3304 | ||
3305 | /* Enumeration to mark the existence of the shadow register set. | |
3306 | SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack | |
3307 | pointer. */ | |
3308 | enum mips_shadow_set | |
3309 | { | |
3310 | SHADOW_SET_NO, | |
3311 | SHADOW_SET_YES, | |
3312 | SHADOW_SET_INTSTACK | |
3313 | }; | |
3314 | ||
3315 | struct GTY(()) machine_function { | |
3316 | /* The next floating-point condition-code register to allocate | |
3317 | for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */ | |
3318 | unsigned int next_fcc; | |
3319 | ||
3320 | /* The register returned by mips16_gp_pseudo_reg; see there for details. */ | |
3321 | rtx mips16_gp_pseudo_rtx; | |
3322 | ||
3323 | /* The number of extra stack bytes taken up by register varargs. | |
3324 | This area is allocated by the callee at the very top of the frame. */ | |
3325 | int varargs_size; | |
3326 | ||
3327 | /* The current frame information, calculated by mips_compute_frame_info. */ | |
3328 | struct mips_frame_info frame; | |
3329 | ||
3330 | /* The register to use as the function's global pointer, or INVALID_REGNUM | |
3331 | if the function doesn't need one. */ | |
3332 | unsigned int global_pointer; | |
3333 | ||
3334 | /* How many instructions it takes to load a label into $AT, or 0 if | |
3335 | this property hasn't yet been calculated. */ | |
3336 | unsigned int load_label_num_insns; | |
3337 | ||
3338 | /* True if mips_adjust_insn_length should ignore an instruction's | |
3339 | hazard attribute. */ | |
3340 | bool ignore_hazard_length_p; | |
3341 | ||
3342 | /* True if the whole function is suitable for .set noreorder and | |
3343 | .set nomacro. */ | |
3344 | bool all_noreorder_p; | |
3345 | ||
3346 | /* True if the function has "inflexible" and "flexible" references | |
3347 | to the global pointer. See mips_cfun_has_inflexible_gp_ref_p | |
3348 | and mips_cfun_has_flexible_gp_ref_p for details. */ | |
3349 | bool has_inflexible_gp_insn_p; | |
3350 | bool has_flexible_gp_insn_p; | |
3351 | ||
3352 | /* True if the function's prologue must load the global pointer | |
3353 | value into pic_offset_table_rtx and store the same value in | |
3354 | the function's cprestore slot (if any). Even if this value | |
3355 | is currently false, we may decide to set it to true later; | |
3356 | see mips_must_initialize_gp_p () for details. */ | |
3357 | bool must_initialize_gp_p; | |
3358 | ||
3359 | /* True if the current function must restore $gp after any potential | |
3360 | clobber. This value is only meaningful during the first post-epilogue | |
3361 | split_insns pass; see mips_must_initialize_gp_p () for details. */ | |
3362 | bool must_restore_gp_when_clobbered_p; | |
3363 | ||
3364 | /* True if this is an interrupt handler. */ | |
3365 | bool interrupt_handler_p; | |
3366 | ||
3367 | /* Records the way in which interrupts should be masked. Only used if | |
3368 | interrupts are not kept masked. */ | |
3369 | enum mips_int_mask int_mask; | |
3370 | ||
3371 | /* Records if this is an interrupt handler that uses shadow registers. */ | |
3372 | enum mips_shadow_set use_shadow_register_set; | |
3373 | ||
3374 | /* True if this is an interrupt handler that should keep interrupts | |
3375 | masked. */ | |
3376 | bool keep_interrupts_masked_p; | |
3377 | ||
3378 | /* True if this is an interrupt handler that should use DERET | |
3379 | instead of ERET. */ | |
3380 | bool use_debug_exception_return_p; | |
3381 | ||
3382 | /* True if at least one of the formal parameters to a function must be | |
3383 | written to the frame header (probably so its address can be taken). */ | |
3384 | bool does_not_use_frame_header; | |
3385 | ||
3386 | /* True if none of the functions that are called by this function need | |
3387 | stack space allocated for their arguments. */ | |
3388 | bool optimize_call_stack; | |
2208bcd9 | 3389 | |
3390 | /* True if one of the functions calling this function may not allocate | |
3391 | a frame header. */ | |
3392 | bool callers_may_not_allocate_frame; | |
3393 | ||
3394 | /* True if GCC stored callee saved registers in the frame header. */ | |
3395 | bool use_frame_header_for_callee_saved_regs; | |
0c9081e8 | 3396 | }; |
3c73affd | 3397 | #endif |
dc5599bf | 3398 | |
3399 | /* Enable querying of DFA units. */ | |
3400 | #define CPU_UNITS_QUERY 1 | |
e6554c42 | 3401 | |
3402 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
3403 | mips_final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
287179e8 | 3404 | |
c4cf26ad | 3405 | /* As on most targets, we want the .eh_frame section to be read-only where |
3406 | possible. And as on most targets, this means two things: | |
3407 | ||
3408 | (a) Non-locally-binding pointers must have an indirect encoding, | |
3409 | so that the addresses in the .eh_frame section itself become | |
3410 | locally-binding. | |
3411 | ||
3412 | (b) A shared library's .eh_frame section must encode locally-binding | |
3413 | pointers in a relative (relocation-free) form. | |
3414 | ||
3415 | However, MIPS has traditionally not allowed directives like: | |
3416 | ||
3417 | .long x-. | |
3418 | ||
3419 | in cases where "x" is in a different section, or is not defined in the | |
3420 | same assembly file. We are therefore unable to emit the PC-relative | |
3421 | form required by (b) at assembly time. | |
3422 | ||
3423 | Fortunately, the linker is able to convert absolute addresses into | |
3424 | PC-relative addresses on our behalf. Unfortunately, only certain | |
3425 | versions of the linker know how to do this for indirect pointers, | |
3426 | and for personality data. We must fall back on using writable | |
3427 | .eh_frame sections for shared libraries if the linker does not | |
3428 | support this feature. */ | |
3429 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
3430 | (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) | |
07f1949b | 3431 | |
3432 | /* For switching between MIPS16 and non-MIPS16 modes. */ | |
3433 | #define SWITCHABLE_TARGET 1 | |
9d81057b | 3434 | |
3435 | /* Several named MIPS patterns depend on Pmode. These patterns have the | |
3436 | form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode. | |
3437 | Add the appropriate suffix to generator function NAME and invoke it | |
3438 | with arguments ARGS. */ | |
3439 | #define PMODE_INSN(NAME, ARGS) \ | |
3440 | (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS) | |
257ccd46 | 3441 | |
3442 | /* If we are *not* using multilibs and the default ABI is not ABI_32 we | |
3443 | need to change these from /lib and /usr/lib. */ | |
3444 | #if MIPS_ABI_DEFAULT == ABI_N32 | |
3445 | #define STANDARD_STARTFILE_PREFIX_1 "/lib32/" | |
3446 | #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/" | |
3447 | #elif MIPS_ABI_DEFAULT == ABI_64 | |
3448 | #define STANDARD_STARTFILE_PREFIX_1 "/lib64/" | |
3449 | #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/" | |
3450 | #endif | |
069b9d52 | 3451 | |
3452 | /* Load store bonding is not supported by micromips and fix_24k. The | |
3453 | performance can be degraded for those targets. Hence, do not bond for | |
3454 | micromips or fix_24k. */ | |
3455 | #define ENABLE_LD_ST_PAIRS \ | |
7bb34078 | 3456 | (TARGET_LOAD_STORE_PAIRS && (TUNE_P5600 || TUNE_I6400) \ |
069b9d52 | 3457 | && !TARGET_MICROMIPS && !TARGET_FIX_24K) |