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[thirdparty/gcc.git] / gcc / config / mips / mips.h
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e75b25e7 1/* Definitions of target machine for GNU compiler. MIPS version.
a872728c 2 Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
ae3e1bb4
RK		 3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
e75b25e7
MM		 7
8This file is part of GNU CC.
9
10GNU CC is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15GNU CC is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with GNU CC; see the file COPYING. If not, write to
75fe0c5e
RK		 22the Free Software Foundation, 59 Temple Place - Suite 330,
23Boston, MA 02111-1307, USA. */
e75b25e7
MM		 24
25
e75b25e7
MM		 26/* Standard GCC variables that we reference. */
27
0fb5ac6f
MM		 28extern char *asm_file_name;
29extern char call_used_regs[];
0fb5ac6f 30extern int may_call_alloca;
0fb5ac6f
MM		 31extern char **save_argv;
32extern int target_flags;
33extern char *version_string;
e75b25e7
MM		 34
35/* MIPS external variables defined in mips.c. */
36
37/* comparison type */
38enum cmp_type {
876c09d3
JW		 39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
e75b25e7
MM		 41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
44};
45
46/* types of delay slot */
47enum delay_type {
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
34b650b3
MM		 50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
e75b25e7
MM		 52};
53
54/* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
4a392643
RS		 56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
e75b25e7
MM		 58
59enum processor_type {
60 PROCESSOR_DEFAULT,
61 PROCESSOR_R3000,
e9a25f70 62 PROCESSOR_R3900,
e75b25e7 63 PROCESSOR_R6000,
876c09d3 64 PROCESSOR_R4000,
00b3e052
JW		 65 PROCESSOR_R4100,
66 PROCESSOR_R4300,
516a2dfd 67 PROCESSOR_R4600,
053665d7 68 PROCESSOR_R4650,
b8eb88d0 69 PROCESSOR_R5000,
516a2dfd 70 PROCESSOR_R8000
e75b25e7
MM		 71};
72
4a392643
RS		 73/* Recast the cpu class to be the cpu attribute. */
74#define mips_cpu_attr ((enum attr_cpu)mips_cpu)
75
04bd620d 76/* Which ABI to use. These are constants because abi64.h must check their
a53f72db
GRK		 77 value at preprocessing time.
78
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
b2d8cf33 81
04bd620d
JW		 82#define ABI_32 0
83#define ABI_N32 1
84#define ABI_64 2
85#define ABI_EABI 3
a53f72db 86#define ABI_O64 4
b2d8cf33
JW		 87
88#ifndef MIPS_ABI_DEFAULT
89/* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91#define mips_abi ABI_32
92#else
04bd620d 93extern int mips_abi;
b2d8cf33
JW		 94#endif
95
45ceb85d
RS		 96/* Whether to emit abicalls code sequences or not. */
97
98enum mips_abicalls_type {
99 MIPS_ABICALLS_NO,
100 MIPS_ABICALLS_YES
101};
102
103/* Recast the abicalls class to be the abicalls attribute. */
104#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
105
b7d3fabe
RS		 106/* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
108
109enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
113};
114
e75b25e7
MM		 115extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
e2fe6aba 117extern const char *current_function_file; /* filename current function is in */
e75b25e7
MM		 118extern int num_source_filenames; /* current .file # */
119extern int inside_function; /* != 0 if inside of a function */
120extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121extern int file_in_function_warning; /* warning given about .file in func */
122extern int sdb_label_count; /* block start/end next label # */
a642a781 123extern int sdb_begin_function_line; /* Starting Line of current function */
e75b25e7
MM		 124extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125extern int g_switch_value; /* value of the -G xx switch */
126extern int g_switch_set; /* whether -G xx was passed. */
127extern int sym_lineno; /* sgi next label # for each stmt */
128extern int set_noreorder; /* # of nested .set noreorder's */
129extern int set_nomacro; /* # of nested .set nomacro's */
130extern int set_noat; /* # of nested .set noat's */
131extern int set_volatile; /* # of nested .set volatile's */
e75b25e7
MM		 132extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133extern int mips_dbx_regno[]; /* Map register # to debug register # */
e75b25e7
MM		 134extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135extern enum cmp_type branch_type; /* what type of branch to use */
136extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
45ceb85d 137extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
e75b25e7 138extern int mips_isa; /* architectural level */
2bcb2ab3
GK		 139extern int mips16; /* whether generating mips16 code */
140extern int mips16_hard_float; /* mips16 without -msoft-float */
141extern int mips_entry; /* generate entry/exit for mips16 */
e2fe6aba
KG		 142extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
143extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
144extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
145extern const char *mips_entry_string; /* for -mentry */
146extern const char *mips_no_mips16_string;/* for -mno-mips16 */
3ce1ba83 147extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
ce57d6f4 148extern int mips_split_addresses; /* perform high/lo_sum support */
e75b25e7
MM		 149extern int dslots_load_total; /* total # load related delay slots */
150extern int dslots_load_filled; /* # filled load delay slots */
151extern int dslots_jump_total; /* total # jump related delay slots */
152extern int dslots_jump_filled; /* # filled jump delay slots */
153extern int dslots_number_nops; /* # of nops needed by previous insn */
154extern int num_refs[3]; /* # 1/2/3 word references */
155extern struct rtx_def *mips_load_reg; /* register to check for load delay */
156extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
157extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
158extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
92544bdf 159extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
2bcb2ab3
GK		 160extern int mips_string_length; /* length of strings for mips16 */
161extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
e75b25e7 162
64ccbc99
KG		 163/* Functions within mips.c that we reference. Some of these return
164 type HOST_WIDE_INT, so define that here. */
f5963e61 165
64ccbc99 166#include "hwint.h"
e75b25e7 167
e75b25e7
MM		 168extern int arith32_operand ();
169extern int arith_operand ();
e75b25e7 170extern int cmp_op ();
64ccbc99 171#ifdef HOST_WIDE_INT
f5963e61 172extern HOST_WIDE_INT compute_frame_size ();
64ccbc99 173#endif
6e92f4b6 174extern int const_float_1_operand ();
e75b25e7
MM		 175extern void expand_block_move ();
176extern int equality_op ();
65437fe8 177extern void final_prescan_insn ();
e75b25e7
MM		 178extern struct rtx_def * function_arg ();
179extern void function_arg_advance ();
180extern int function_arg_partial_nregs ();
293a36eb 181extern int function_arg_pass_by_reference ();
e75b25e7
MM		 182extern void function_epilogue ();
183extern void function_prologue ();
184extern void gen_conditional_branch ();
b8eb88d0 185extern void gen_conditional_move ();
34b650b3 186extern struct rtx_def * gen_int_relational ();
e75b25e7
MM		 187extern void init_cumulative_args ();
188extern int large_int ();
688f0603 189extern void machine_dependent_reorg ();
e75b25e7
MM		 190extern int mips_address_cost ();
191extern void mips_asm_file_end ();
192extern void mips_asm_file_start ();
6e92f4b6 193extern int mips_can_use_return_insn ();
e75b25e7 194extern int mips_const_double_ok ();
e75b25e7 195extern void mips_count_memory_refs ();
64ccbc99 196#ifdef HOST_WIDE_INT
f5963e61 197extern HOST_WIDE_INT mips_debugger_offset ();
64ccbc99 198#endif
0fb5ac6f 199extern void mips_declare_object ();
e75b25e7 200extern int mips_epilogue_delay_slots ();
0fb5ac6f
MM		 201extern void mips_expand_epilogue ();
202extern void mips_expand_prologue ();
ce57d6f4 203extern int mips_check_split ();
e75b25e7 204extern char *mips_fill_delay_slot ();
e2fe6aba
KG		 205extern const char *mips_move_1word ();
206extern const char *mips_move_2words ();
dbe9742d 207extern void mips_output_double ();
e75b25e7 208extern int mips_output_external ();
dbe9742d 209extern void mips_output_float ();
e75b25e7
MM		 210extern void mips_output_filename ();
211extern void mips_output_lineno ();
e2fe6aba 212extern const char *output_block_move ();
e75b25e7 213extern void override_options ();
34b650b3 214extern int pc_or_label_operand ();
e75b25e7
MM		 215extern void print_operand_address ();
216extern void print_operand ();
217extern void print_options ();
218extern int reg_or_0_operand ();
def72bd2 219extern int true_reg_or_0_operand ();
0fb5ac6f 220extern int simple_epilogue_p ();
e75b25e7 221extern int simple_memory_operand ();
2bcb2ab3 222extern int double_memory_operand ();
e75b25e7 223extern int small_int ();
f5963e61 224extern void trace ();
e75b25e7 225extern int uns_arith_operand ();
92544bdf 226extern struct rtx_def * embedded_pic_offset ();
2bcb2ab3
GK		 227extern void mips_order_regs_for_local_alloc ();
228extern struct rtx_def * mips16_gp_pseudo_reg ();
229extern struct rtx_def * mips16_gp_offset ();
230extern int mips16_gp_offset_p ();
6e92f4b6 231extern int mips16_constant ();
2bcb2ab3
GK		 232extern int mips16_constant_after_function_p ();
233extern int build_mips16_call_stub ();
0ff83799
MM		 234extern char *mips_output_conditional_branch ();
235extern int mips_adjust_insn_length ();
e75b25e7 236
0fb5ac6f
MM		 237/* Recognition functions that return if a condition is true. */
238extern int address_operand ();
6e92f4b6 239extern int call_insn_operand ();
0fb5ac6f
MM		 240extern int const_double_operand ();
241extern int const_int_operand ();
6e92f4b6 242extern int consttable_operand ();
0fb5ac6f
MM		 243extern int general_operand ();
244extern int immediate_operand ();
245extern int memory_address_p ();
246extern int memory_operand ();
247extern int nonimmediate_operand ();
248extern int nonmemory_operand ();
6e92f4b6 249extern int pic_address_needs_scratch ();
0fb5ac6f
MM		 250extern int register_operand ();
251extern int scratch_operand ();
ce57d6f4 252extern int move_operand ();
1908a152
ILT		 253extern int movdi_operand ();
254extern int se_register_operand ();
255extern int se_reg_or_0_operand ();
256extern int se_uns_arith_operand ();
257extern int se_arith_operand ();
258extern int se_nonmemory_operand ();
259extern int se_nonimmediate_operand ();
cb923660
KR		 260extern int extend_operator ();
261extern int highpart_shift_operator ();
2bcb2ab3
GK		 262extern int m16_uimm3_b ();
263extern int m16_simm4_1 ();
264extern int m16_nsimm4_1 ();
265extern int m16_simm5_1 ();
266extern int m16_nsimm5_1 ();
267extern int m16_uimm5_4 ();
268extern int m16_nuimm5_4 ();
269extern int m16_simm8_1 ();
270extern int m16_nsimm8_1 ();
271extern int m16_uimm8_1 ();
272extern int m16_nuimm8_1 ();
273extern int m16_uimm8_m1_1 ();
274extern int m16_uimm8_4 ();
275extern int m16_nuimm8_4 ();
276extern int m16_simm8_8 ();
277extern int m16_nsimm8_8 ();
278extern int m16_usym8_4 ();
279extern int m16_usym5_4 ();
0fb5ac6f
MM		 280
281/* Functions to change what output section we are using. */
e75b25e7
MM		 282extern void data_section ();
283extern void rdata_section ();
284extern void readonly_data_section ();
285extern void sdata_section ();
286extern void text_section ();
6e92f4b6
KG		 287extern void mips_select_rtx_section ();
288extern void mips_select_section ();
e75b25e7 289
31c714e3
MM		 290/* Stubs for half-pic support if not OSF/1 reference platform. */
291
292#ifndef HALF_PIC_P
293#define HALF_PIC_P() 0
4a392643
RS		 294#define HALF_PIC_NUMBER_PTRS 0
295#define HALF_PIC_NUMBER_REFS 0
31c714e3 296#define HALF_PIC_ENCODE(DECL)
f3b39eba 297#define HALF_PIC_DECLARE(NAME)
31c714e3
MM		 298#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
299#define HALF_PIC_ADDRESS_P(X) 0
d26e29e1
MM		 300#define HALF_PIC_PTR(X) X
301#define HALF_PIC_FINISH(STREAM)
31c714e3
MM		 302#endif
303
149e4e00
MM		 304\f
305/* Run-time compilation parameters selecting different hardware subsets. */
306
307/* Macros used in the machine description to test the flags. */
308
309 /* Bits for real switches */
310#define MASK_INT64 0x00000001 /* ints are 64 bits */
fb1bf66d 311#define MASK_LONG64 0x00000002 /* longs are 64 bits */
5ef37cd3 312#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
149e4e00
MM		 313#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
314#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
315#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
316#define MASK_STATS 0x00000040 /* print statistics to stderr */
317#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
318#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
319#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
320#define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
321#define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
322#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
2370b831 323#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
e0bfcea5 324#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
365c6a0b 325#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
96abdcb1 326#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
46299de9
ILT		 327#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
328#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
00b3e052 329#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
e9a25f70 330#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
2bcb2ab3 331#define MASK_MIPS16 0x01000000 /* Generate mips16 code */
08c2951c
SC		 332#define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
333#define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
149e4e00
MM		 334
335 /* Dummy switches used only in spec's*/
336#define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
337
338 /* Debug switches, not documented */
08c2951c
SC		 339#define MASK_DEBUG 0 /* Eliminate version # in .s file */
340#define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
341#define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
342#define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
343#define MASK_DEBUG_D 0 /* don't do define_split's */
e4f5c5d6 344#define MASK_DEBUG_E 0 /* function_arg debug */
2bcb2ab3
GK		 345#define MASK_DEBUG_F 0
346#define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
6d1350cd 347#define MASK_DEBUG_H 0 /* allow ints in FP registers */
e4f5c5d6 348#define MASK_DEBUG_I 0 /* unused */
149e4e00
MM		 349
350 /* r4000 64 bit sizes */
351#define TARGET_INT64 (target_flags & MASK_INT64)
352#define TARGET_LONG64 (target_flags & MASK_LONG64)
149e4e00 353#define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
876c09d3 354#define TARGET_64BIT (target_flags & MASK_64BIT)
149e4e00 355
5ef37cd3
JW		 356 /* Mips vs. GNU linker */
357#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
358
e9a25f70
JL		 359/* generate mips 3900 insns */
360#define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
361
149e4e00
MM		 362 /* Mips vs. GNU assembler */
363#define TARGET_GAS (target_flags & MASK_GAS)
364#define TARGET_UNIX_ASM (!TARGET_GAS)
365#define TARGET_MIPS_AS TARGET_UNIX_ASM
366
367 /* Debug Mode */
368#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
369#define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
370#define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
371#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
372#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
373#define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
374#define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
375#define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
376#define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
377#define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
149e4e00
MM		 378
379 /* Reg. Naming in .s ($21 vs. $a0) */
380#define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
381
382 /* Optimize for Sdata/Sbss */
383#define TARGET_GP_OPT (target_flags & MASK_GPOPT)
384
385 /* print program statistics */
386#define TARGET_STATS (target_flags & MASK_STATS)
387
388 /* call memcpy instead of inline code */
389#define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
390
391 /* .abicalls, etc from Pyramid V.4 */
392#define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
393
394 /* OSF pic references to externs */
395#define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
396
397 /* software floating point */
398#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
399#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
400
401 /* always call through a register */
402#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
403
e0bfcea5
ILT		 404 /* generate embedded PIC code;
405 requires gas. */
406#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
407
365c6a0b
JW		 408 /* for embedded systems, optimize for
409 reduced RAM space instead of for
410 fastest code. */
411#define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
412
96abdcb1
ILT		 413 /* generate big endian code. */
414#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
415
46299de9
ILT		 416#define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
417#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
418
419#define TARGET_MAD (target_flags & MASK_MAD)
420
00b3e052
JW		 421#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
422
08c2951c
SC		 423#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
424#define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
425
33b5e50b
JW		 426/* This is true if we must enable the assembly language file switching
427 code. */
428
429#define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
430
431/* We must disable the function end stabs when doing the file switching trick,
432 because the Lscope stabs end up in the wrong place, making it impossible
433 to debug the resulting code. */
434#define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
435
2bcb2ab3
GK		 436 /* Generate mips16 code */
437#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
438
149e4e00
MM		 439/* Macro to define tables used to set the flags.
440 This is a list in braces of pairs in braces,
441 each pair being { "NAME", VALUE }
442 where VALUE is the bits to set or minus the bits to clear.
443 An empty string NAME is used to identify the default VALUE. */
444
445#define TARGET_SWITCHES \
446{ \
a127db75
JW		 447 {"int64", MASK_INT64 | MASK_LONG64, \
448 "Use 64-bit int type"}, \
449 {"long64", MASK_LONG64, \
450 "Use 64-bit long type"}, \
451 {"long32", -(MASK_LONG64 | MASK_INT64), \
452 "Use 32-bit long type"}, \
453 {"split-addresses", MASK_SPLIT_ADDR, \
454 "Optimize lui/addiu address loads"}, \
455 {"no-split-addresses", -MASK_SPLIT_ADDR, \
456 "Don't optimize lui/addiu address loads"}, \
457 {"mips-as", -MASK_GAS, \
458 "Use MIPS as"}, \
459 {"gas", MASK_GAS, \
460 "Use GNU as"}, \
461 {"rnames", MASK_NAME_REGS, \
462 "Use symbolic register names"}, \
463 {"no-rnames", -MASK_NAME_REGS, \
464 "Don't use symbolic register names"}, \
465 {"gpOPT", MASK_GPOPT, \
466 "Use GP relative sdata/sbss sections"}, \
467 {"gpopt", MASK_GPOPT, \
468 "Use GP relative sdata/sbss sections"}, \
469 {"no-gpOPT", -MASK_GPOPT, \
470 "Don't use GP relative sdata/sbss sections"}, \
471 {"no-gpopt", -MASK_GPOPT, \
472 "Don't use GP relative sdata/sbss sections"}, \
473 {"stats", MASK_STATS, \
474 "Output compiler statistics"}, \
475 {"no-stats", -MASK_STATS, \
476 "Don't output compiler statistics"}, \
477 {"memcpy", MASK_MEMCPY, \
478 "Don't optimize block moves"}, \
479 {"no-memcpy", -MASK_MEMCPY, \
480 "Optimize block moves"}, \
481 {"mips-tfile", MASK_MIPS_TFILE, \
482 "Use mips-tfile asm postpass"}, \
483 {"no-mips-tfile", -MASK_MIPS_TFILE, \
484 "Don't use mips-tfile asm postpass"}, \
485 {"soft-float", MASK_SOFT_FLOAT, \
486 "Use software floating point"}, \
487 {"hard-float", -MASK_SOFT_FLOAT, \
488 "Use hardware floating point"}, \
489 {"fp64", MASK_FLOAT64, \
490 "Use 64-bit FP registers"}, \
491 {"fp32", -MASK_FLOAT64, \
492 "Use 32-bit FP registers"}, \
493 {"gp64", MASK_64BIT, \
494 "Use 64-bit general registers"}, \
495 {"gp32", -MASK_64BIT, \
496 "Use 32-bit general registers"}, \
497 {"abicalls", MASK_ABICALLS, \
498 "Use Irix PIC"}, \
499 {"no-abicalls", -MASK_ABICALLS, \
500 "Don't use Irix PIC"}, \
501 {"half-pic", MASK_HALF_PIC, \
502 "Use OSF PIC"}, \
503 {"no-half-pic", -MASK_HALF_PIC, \
504 "Don't use OSF PIC"}, \
505 {"long-calls", MASK_LONG_CALLS, \
506 "Use indirect calls"}, \
507 {"no-long-calls", -MASK_LONG_CALLS, \
508 "Don't use indirect calls"}, \
509 {"embedded-pic", MASK_EMBEDDED_PIC, \
510 "Use embedded PIC"}, \
511 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
512 "Don't use embedded PIC"}, \
513 {"embedded-data", MASK_EMBEDDED_DATA, \
514 "Use ROM instead of RAM"}, \
515 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
516 "Don't use ROM instead of RAM"}, \
517 {"eb", MASK_BIG_ENDIAN, \
518 "Use big-endian byte order"}, \
519 {"el", -MASK_BIG_ENDIAN, \
520 "Use little-endian byte order"}, \
521 {"single-float", MASK_SINGLE_FLOAT, \
522 "Use single (32-bit) FP only"}, \
523 {"double-float", -MASK_SINGLE_FLOAT, \
524 "Don't use single (32-bit) FP only"}, \
525 {"mad", MASK_MAD, \
526 "Use multiply accumulate"}, \
527 {"no-mad", -MASK_MAD, \
528 "Don't use multiply accumulate"}, \
529 {"fix4300", MASK_4300_MUL_FIX, \
530 "Work around early 4300 hardware bug"}, \
531 {"no-fix4300", -MASK_4300_MUL_FIX, \
532 "Don't work around early 4300 hardware bug"}, \
533 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
534 "Optimize for 4650"}, \
535 {"3900", MASK_MIPS3900, \
536 "Optimize for 3900"}, \
537 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
538 "Trap on integer divide by zero"}, \
539 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
540 "Don't trap on integer divide by zero"}, \
541 {"check-range-division",MASK_CHECK_RANGE_DIV, \
542 "Trap on integer divide overflow"}, \
543 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
544 "Don't trap on integer divide overflow"}, \
545 {"debug", MASK_DEBUG, \
546 NULL}, \
547 {"debuga", MASK_DEBUG_A, \
548 NULL}, \
549 {"debugb", MASK_DEBUG_B, \
550 NULL}, \
551 {"debugc", MASK_DEBUG_C, \
552 NULL}, \
553 {"debugd", MASK_DEBUG_D, \
554 NULL}, \
555 {"debuge", MASK_DEBUG_E, \
556 NULL}, \
557 {"debugf", MASK_DEBUG_F, \
558 NULL}, \
559 {"debugg", MASK_DEBUG_G, \
560 NULL}, \
561 {"debugh", MASK_DEBUG_H, \
562 NULL}, \
563 {"debugi", MASK_DEBUG_I, \
564 NULL}, \
96abdcb1
ILT		 565 {"", (TARGET_DEFAULT \
566 | TARGET_CPU_DEFAULT \
a127db75
JW		 567 | TARGET_ENDIAN_DEFAULT), \
568 NULL}, \
569}
149e4e00
MM		 570
571/* Default target_flags if no switches are specified */
572
573#ifndef TARGET_DEFAULT
574#define TARGET_DEFAULT 0
575#endif
576
404f986e
MM		 577#ifndef TARGET_CPU_DEFAULT
578#define TARGET_CPU_DEFAULT 0
579#endif
580
96abdcb1
ILT		 581#ifndef TARGET_ENDIAN_DEFAULT
582#ifndef DECSTATION
583#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
584#else
585#define TARGET_ENDIAN_DEFAULT 0
586#endif
587#endif
588
7f2e00db
RK		 589#ifndef MULTILIB_DEFAULTS
590#if TARGET_ENDIAN_DEFAULT == 0
591#define MULTILIB_DEFAULTS { "EL", "mips1" }
592#else
593#define MULTILIB_DEFAULTS { "EB", "mips1" }
594#endif
595#endif
596
34bcd7fd
JW		 597/* We must pass -EL to the linker by default for little endian embedded
598 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
599 linker will default to using big-endian output files. The OUTPUT_FORMAT
600 line must be in the linker script, otherwise -EB/-EL will not work. */
601
602#ifndef LINKER_ENDIAN_SPEC
603#if TARGET_ENDIAN_DEFAULT == 0
604#define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
605#else
606#define LINKER_ENDIAN_SPEC ""
607#endif
608#endif
609
149e4e00
MM		 610/* This macro is similar to `TARGET_SWITCHES' but defines names of
611 command options that have values. Its definition is an
612 initializer with a subgrouping for each command option.
613
614 Each subgrouping contains a string constant, that defines the
615 fixed part of the option name, and the address of a variable.
616 The variable, type `char *', is set to the variable part of the
617 given option if the fixed part matches. The actual option name
618 is made by appending `-m' to the specified name.
619
620 Here is an example which defines `-mshort-data-NUMBER'. If the
621 given option is `-mshort-data-512', the variable `m88k_short_data'
622 will be set to the string `"512"'.
623
624 extern char *m88k_short_data;
625 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
626
627#define TARGET_OPTIONS \
628{ \
b2d8cf33 629 SUBTARGET_TARGET_OPTIONS \
a127db75
JW		 630 { "cpu=", &mips_cpu_string, \
631 "Specify CPU for scheduling purposes"}, \
632 { "ips", &mips_isa_string, \
633 "Specify MIPS ISA"}, \
634 { "entry", &mips_entry_string, \
635 "Use mips16 entry/exit psuedo ops"}, \
636 { "no-mips16", &mips_no_mips16_string, \
637 "Don't use MIPS16 instructions"}, \
638 { "explicit-type-size", &mips_explicit_type_size_string, \
639 NULL}, \
149e4e00
MM		 640}
641
b2d8cf33
JW		 642/* This is meant to be redefined in the host dependent files. */
643#define SUBTARGET_TARGET_OPTIONS
644
2bcb2ab3 645#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
e4f5c5d6
KR		 646
647/* Generate three-operand multiply instructions for both SImode and DImode. */
2bcb2ab3 648#define GENERATE_MULT3 (TARGET_MIPS3900 \
60db002d 649 && !TARGET_MIPS16)
e9a25f70 650
149e4e00
MM		 651/* Macros to decide whether certain features are available or not,
652 depending on the instruction set architecture level. */
653
e9a25f70 654#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
149e4e00
MM		 655#define HAVE_SQRT_P() (mips_isa >= 2)
656
516a2dfd
JW		 657/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
658 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
2370b831
JW		 659 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
660 target_flags, and -mgp64 sets MASK_64BIT.
876c09d3 661
2370b831
JW		 662 Setting MASK_64BIT in target_flags will cause gcc to assume that
663 registers are 64 bits wide. int, long and void * will be 32 bit;
664 this may be changed with -mint64 or -mlong64.
876c09d3 665
2370b831
JW		 666 The gen* programs link code that refers to MASK_64BIT. They don't
667 actually use the information in target_flags; they just refer to
668 it. */
e75b25e7
MM		 669\f
670/* Switch Recognition by gcc.c. Add -G xx support */
671
672#ifdef SWITCH_TAKES_ARG
673#undef SWITCH_TAKES_ARG
674#endif
675
676#define SWITCH_TAKES_ARG(CHAR) \
7d4ea832 677 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
e75b25e7
MM		 678
679/* Sometimes certain combinations of command options do not make sense
680 on a particular target machine. You can define a macro
681 `OVERRIDE_OPTIONS' to take account of this. This macro, if
682 defined, is executed once just after all the command options have
683 been parsed.
684
685 On the MIPS, it is used to handle -G. We also use it to set up all
686 of the tables referenced in the other macros. */
687
688#define OVERRIDE_OPTIONS override_options ()
689
690/* Zero or more C statements that may conditionally modify two
691 variables `fixed_regs' and `call_used_regs' (both of type `char
692 []') after they have been initialized from the two preceding
693 macros.
694
695 This is necessary in case the fixed or call-clobbered registers
696 depend on target flags.
697
698 You need not define this macro if it has no work to do.
699
700 If the usage of an entire class of registers depends on the target
701 flags, you may indicate this to GCC by using this macro to modify
702 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
703 the classes which should not be used by GCC. Also define the macro
704 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
705 letter for a class that shouldn't be used.
706
707 (However, if this class is not included in `GENERAL_REGS' and all
708 of the insn patterns whose constraints permit this class are
709 controlled by target switches, then GCC will automatically avoid
710 using these registers when the target switches are opposed to
711 them.) */
712
713#define CONDITIONAL_REGISTER_USAGE \
714do \
715 { \
716 if (!TARGET_HARD_FLOAT) \
717 { \
718 int regno; \
719 \
720 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
721 fixed_regs[regno] = call_used_regs[regno] = 1; \
b8eb88d0
ILT		 722 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
723 fixed_regs[regno] = call_used_regs[regno] = 1; \
724 } \
725 else if (mips_isa < 4) \
726 { \
727 int regno; \
728 \
729 /* We only have a single condition code register. We \
730 implement this by hiding all the condition code registers, \
731 and generating RTL that refers directly to ST_REG_FIRST. */ \
732 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
733 fixed_regs[regno] = call_used_regs[regno] = 1; \
e75b25e7 734 } \
2bcb2ab3
GK		 735 /* In mips16 mode, we permit the $t temporary registers to be used \
736 for reload. We prohibit the unused $s registers, since they \
737 are caller saved, and saving them via a mips16 register would \
738 probably waste more time than just reloading the value. */ \
739 if (TARGET_MIPS16) \
740 { \
741 fixed_regs[18] = call_used_regs[18] = 1; \
742 fixed_regs[19] = call_used_regs[19] = 1; \
743 fixed_regs[20] = call_used_regs[20] = 1; \
744 fixed_regs[21] = call_used_regs[21] = 1; \
745 fixed_regs[22] = call_used_regs[22] = 1; \
746 fixed_regs[23] = call_used_regs[23] = 1; \
747 fixed_regs[26] = call_used_regs[26] = 1; \
748 fixed_regs[27] = call_used_regs[27] = 1; \
749 fixed_regs[30] = call_used_regs[30] = 1; \
750 } \
516a2dfd 751 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
e75b25e7
MM		 752 } \
753while (0)
754
b2d8cf33 755/* This is meant to be redefined in the host dependent files. */
516a2dfd
JW		 756#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
757
7be1e523
RK		 758/* Show we can debug even without a frame pointer. */
759#define CAN_DEBUG_WITHOUT_FP
760\f
e75b25e7
MM		 761/* Complain about missing specs and predefines that should be defined in each
762 of the target tm files to override the defaults. This is mostly a place-
763 holder until I can get each of the files updated [mm]. */
764
765#if defined(OSF_OS) \
766 || defined(DECSTATION) \
767 || defined(SGI_TARGET) \
768 || defined(MIPS_NEWS) \
769 || defined(MIPS_SYSV) \
59c94430 770 || defined(MIPS_SVR4) \
e75b25e7
MM		 771 || defined(MIPS_BSD43)
772
773#ifndef CPP_PREDEFINES
774 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
775#endif
776
e75b25e7
MM		 777#ifndef LIB_SPEC
778 #error "Define LIB_SPEC in the appropriate tm.h file"
779#endif
780
781#ifndef STARTFILE_SPEC
782 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
783#endif
784
785#ifndef MACHINE_TYPE
786 #error "Define MACHINE_TYPE in the appropriate tm.h file"
787#endif
788#endif
789
59c94430
MM		 790/* Tell collect what flags to pass to nm. */
791#ifndef NM_FLAGS
2ce3c6c6 792#define NM_FLAGS "-Bn"
59c94430
MM		 793#endif
794
e75b25e7
MM		 795\f
796/* Names to predefine in the preprocessor for this target machine. */
797
798#ifndef CPP_PREDEFINES
d4099651 799#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
65c42379
DE		 800-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
801-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
e75b25e7
MM		 802#endif
803
4e88bbcd
ILT		 804/* Assembler specs. */
805
806/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
807 than gas. */
808
809#define MIPS_AS_ASM_SPEC "\
810%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
811%{pipe: %e-pipe is not supported.} \
812%{K} %(subtarget_mips_as_asm_spec)"
813
814/* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
815 rather than gas. It may be overridden by subtargets. */
816
817#ifndef SUBTARGET_MIPS_AS_ASM_SPEC
818#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
819#endif
820
821/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
822 assembler. */
823
e9a25f70 824#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
4e88bbcd
ILT		 825
826/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
827 GAS_ASM_SPEC as the default, depending upon the value of
828 TARGET_DEFAULT. */
e75b25e7 829
bb98bc58
JW		 830#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
831/* GAS */
bb98bc58 832
4e88bbcd
ILT		 833#define TARGET_ASM_SPEC "\
834%{mmips-as: %(mips_as_asm_spec)} \
835%{!mmips-as: %(gas_asm_spec)}"
836
837#else /* not GAS */
838
839#define TARGET_ASM_SPEC "\
840%{!mgas: %(mips_as_asm_spec)} \
841%{mgas: %(gas_asm_spec)}"
842
843#endif /* not GAS */
844
845/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
846 to the assembler. It may be overridden by subtargets. */
847#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
848#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
bb98bc58 849%{noasmopt:-O0} \
4e88bbcd
ILT		 850%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
851#endif
852
853/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
854 the assembler. It may be overridden by subtargets. */
855#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
856#define SUBTARGET_ASM_DEBUGGING_SPEC "\
bb98bc58
JW		 857%{g} %{g0} %{g1} %{g2} %{g3} \
858%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
859%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
860%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
4e88bbcd
ILT		 861%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
862#endif
bb98bc58 863
4e88bbcd
ILT		 864/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
865 overridden by subtargets. */
866
867#ifndef SUBTARGET_ASM_SPEC
868#define SUBTARGET_ASM_SPEC ""
bb98bc58 869#endif
4e88bbcd
ILT		 870
871/* ASM_SPEC is the set of arguments to pass to the assembler. */
872
873#define ASM_SPEC "\
874%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
2bcb2ab3 875%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
4e88bbcd
ILT		 876%(subtarget_asm_optimizing_spec) \
877%(subtarget_asm_debugging_spec) \
878%{membedded-pic} \
879%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
880%(target_asm_spec) \
881%(subtarget_asm_spec)"
e75b25e7
MM		 882
883/* Specify to run a post-processor, mips-tfile after the assembler
884 has run to stuff the mips debug information into the object file.
885 This is needed because the $#!%^ MIPS assembler provides no way
a813fadf
MM		 886 of specifying such information in the assembly file. If we are
887 cross compiling, disable mips-tfile unless the user specifies
888 -mmips-tfile. */
e75b25e7
MM		 889
890#ifndef ASM_FINAL_SPEC
bb98bc58
JW		 891#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
892/* GAS */
31c714e3 893#define ASM_FINAL_SPEC "\
149e4e00 894%{mmips-as: %{!mno-mips-tfile: \
31c714e3
MM		 895 \n mips-tfile %{v*: -v} \
896 %{K: -I %b.o~} \
897 %{!K: %{save-temps: -I %b.o~}} \
ab78d4a8 898 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
31c714e3 899 %{.s:%i} %{!.s:%g.s}}}"
a813fadf 900
bb98bc58
JW		 901#else
902/* not GAS */
a813fadf 903#define ASM_FINAL_SPEC "\
149e4e00 904%{!mgas: %{!mno-mips-tfile: \
a813fadf
MM		 905 \n mips-tfile %{v*: -v} \
906 %{K: -I %b.o~} \
907 %{!K: %{save-temps: -I %b.o~}} \
908 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
909 %{.s:%i} %{!.s:%g.s}}}"
910
bb98bc58 911#endif
a813fadf 912#endif /* ASM_FINAL_SPEC */
e75b25e7
MM		 913
914/* Redefinition of libraries used. Mips doesn't support normal
915 UNIX style profiling via calling _mcount. It does offer
916 profiling that samples the PC, so do what we can... */
917
918#ifndef LIB_SPEC
919#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
920#endif
921
31c714e3 922/* Extra switches sometimes passed to the linker. */
bb98bc58
JW		 923/* ??? The bestGnum will never be passed to the linker, because the gcc driver
924 will interpret it as a -b option. */
e75b25e7
MM		 925
926#ifndef LINK_SPEC
31c714e3 927#define LINK_SPEC "\
516a2dfd 928%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
34bcd7fd
JW		 929%{bestGnum} %{shared} %{non_shared} \
930%(linker_endian_spec)"
bb98bc58 931#endif /* LINK_SPEC defined */
e75b25e7
MM		 932
933/* Specs for the compiler proper */
934
c9db96ce
JR		 935/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
936 overridden by subtargets. */
937#ifndef SUBTARGET_CC1_SPEC
938#define SUBTARGET_CC1_SPEC ""
939#endif
940
941/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
942
e75b25e7 943#ifndef CC1_SPEC
31c714e3 944#define CC1_SPEC "\
31c714e3 945%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
7e99e494 946%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
46299de9 947%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
516a2dfd 948%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
46299de9
ILT		 949%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
950%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
3ce1ba83 951%{mint64|mlong64|mlong32:-mexplicit-type-size }\
46299de9 952%{m4650:-mcpu=r4650} \
e9a25f70 953%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
96abdcb1 954%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
31c714e3
MM		 955%{pic-none: -mno-half-pic} \
956%{pic-lib: -mhalf-pic} \
957%{pic-extern: -mhalf-pic} \
958%{pic-calls: -mhalf-pic} \
c9db96ce
JR		 959%{save-temps: } \
960%(subtarget_cc1_spec) "
e75b25e7
MM		 961#endif
962
4e88bbcd
ILT		 963/* Preprocessor specs. */
964
965/* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
966 be overridden by subtargets. */
967
968#ifndef SUBTARGET_CPP_SIZE_SPEC
969#define SUBTARGET_CPP_SIZE_SPEC "\
3ce1ba83 970%{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
4e88bbcd
ILT		 971%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
972#endif
973
974/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
975 overridden by subtargets. */
976#ifndef SUBTARGET_CPP_SPEC
977#define SUBTARGET_CPP_SPEC ""
978#endif
979
4eb66248
JL		 980/* If we're using 64bit longs, then we have to define __LONG_MAX__
981 correctly. Similarly for 64bit ints and __INT_MAX__. */
982#ifndef LONG_MAX_SPEC
983#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
3ce1ba83 984#define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
4eb66248
JL		 985#else
986#define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
987#endif
988#endif
989
4e88bbcd 990/* CPP_SPEC is the set of arguments to pass to the preprocessor. */
e75b25e7
MM		 991
992#ifndef CPP_SPEC
31c714e3 993#define CPP_SPEC "\
31c714e3
MM		 994%{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
995%{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
996%{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
0002d808 997%{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
31c714e3 998%{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
6630a026 999%{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
4e88bbcd
ILT		 1000%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
1001%(subtarget_cpp_size_spec) \
192616a4
RK		 1002%{mips3:-U__mips -D__mips=3 -D__mips64} \
1003%{mips4:-U__mips -D__mips=4 -D__mips64} \
1004%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
54efdaa4
JW		 1005%{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1006%{m4650:%{!msoft-float:-D__mips_single_float}} \
293a36eb
ILT		 1007%{msoft-float:-D__mips_soft_float} \
1008%{mabi=eabi:-D__mips_eabi} \
2bcb2ab3 1009%{mips16:%{!mno-mips16:-D__mips16}} \
96abdcb1 1010%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
4e88bbcd 1011%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
4eb66248 1012%(long_max_spec) \
4e88bbcd
ILT		 1013%(subtarget_cpp_spec) "
1014#endif
1015
1016/* This macro defines names of additional specifications to put in the specs
1017 that can be used in various specifications like CC1_SPEC. Its definition
1018 is an initializer with a subgrouping for each command option.
1019
1020 Each subgrouping contains a string constant, that defines the
1021 specification name, and a string constant that used by the GNU CC driver
1022 program.
1023
1024 Do not define this macro if it does not need to do anything. */
1025
1026#define EXTRA_SPECS \
829245be
KG		 1027 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1028 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1029 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1030 { "long_max_spec", LONG_MAX_SPEC }, \
1031 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1032 { "gas_asm_spec", GAS_ASM_SPEC }, \
1033 { "target_asm_spec", TARGET_ASM_SPEC }, \
1034 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1035 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1036 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1037 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1038 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
4e88bbcd
ILT		 1039 SUBTARGET_EXTRA_SPECS
1040
1041#ifndef SUBTARGET_EXTRA_SPECS
1042#define SUBTARGET_EXTRA_SPECS
e75b25e7
MM		 1043#endif
1044
1045/* If defined, this macro is an additional prefix to try after
1046 `STANDARD_EXEC_PREFIX'. */
1047
1048#ifndef MD_EXEC_PREFIX
31c714e3 1049#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
e75b25e7
MM		 1050#endif
1051
59c94430
MM		 1052#ifndef MD_STARTFILE_PREFIX
1053#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1054#endif
1055
e75b25e7
MM		 1056\f
1057/* Print subsidiary information on the compiler version in use. */
1058
42dee4c7 1059#define MIPS_VERSION "[AL 1.1, MM 40]"
e75b25e7
MM		 1060
1061#ifndef MACHINE_TYPE
1062#define MACHINE_TYPE "BSD Mips"
1063#endif
1064
1065#ifndef TARGET_VERSION_INTERNAL
1066#define TARGET_VERSION_INTERNAL(STREAM) \
1067 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1068#endif
1069
1070#ifndef TARGET_VERSION
1071#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1072#endif
1073
1074\f
1075#define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1076#define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1077#define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1078
1079#ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
fe0986b4 1080#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
e75b25e7
MM		 1081#endif
1082
59c94430
MM		 1083/* By default, turn on GDB extensions. */
1084#define DEFAULT_GDB_EXTENSIONS 1
1085
e75b25e7
MM		 1086/* If we are passing smuggling stabs through the MIPS ECOFF object
1087 format, put a comment in front of the .stab<x> operation so
1088 that the MIPS assembler does not choke. The mips-tfile program
1089 will correctly put the stab into the object file. */
1090
1091#define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1092#define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1093#define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1094
6ae1498b
JW		 1095/* Local compiler-generated symbols must have a prefix that the assembler
1096 understands. By default, this is $, although some targets (e.g.,
1097 NetBSD-ELF) need to override this. */
1098
1099#ifndef LOCAL_LABEL_PREFIX
1100#define LOCAL_LABEL_PREFIX "$"
1101#endif
1102
1103/* By default on the mips, external symbols do not have an underscore
1104 prepended, but some targets (e.g., NetBSD) require this. */
1105
1106#ifndef USER_LABEL_PREFIX
1107#define USER_LABEL_PREFIX ""
1108#endif
1109
e75b25e7
MM		 1110/* Forward references to tags are allowed. */
1111#define SDB_ALLOW_FORWARD_REFERENCES
1112
1113/* Unknown tags are also allowed. */
1114#define SDB_ALLOW_UNKNOWN_REFERENCES
1115
1116/* On Sun 4, this limit is 2048. We use 1500 to be safe,
1117 since the length can run past this up to a continuation point. */
1118#define DBX_CONTIN_LENGTH 1500
1119
e75b25e7
MM		 1120/* How to renumber registers for dbx and gdb. */
1121#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1122
c8cc5c4a 1123/* The mapping from gcc register number to DWARF 2 CFA column number.
0021b564
JM		 1124 This mapping does not allow for tracking register 0, since SGI's broken
1125 dwarf reader thinks column 0 is used for the frame address, but since
1126 register 0 is fixed this is not a problem. */
469ac993 1127#define DWARF_FRAME_REGNUM(REG) \
0021b564 1128 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
c8cc5c4a
JM		 1129
1130/* The DWARF 2 CFA column which tracks the return address. */
1131#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
e75b25e7 1132
469ac993 1133/* Before the prologue, RA lives in r31. */
c5c76735 1134#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
469ac993 1135
e75b25e7
MM		 1136/* Overrides for the COFF debug format. */
1137#define PUT_SDB_SCL(a) \
1138do { \
1139 extern FILE *asm_out_text_file; \
1140 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1141} while (0)
1142
1143#define PUT_SDB_INT_VAL(a) \
1144do { \
1145 extern FILE *asm_out_text_file; \
1146 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1147} while (0)
1148
1149#define PUT_SDB_VAL(a) \
1150do { \
1151 extern FILE *asm_out_text_file; \
1152 fputs ("\t.val\t", asm_out_text_file); \
1153 output_addr_const (asm_out_text_file, (a)); \
1154 fputc (';', asm_out_text_file); \
1155} while (0)
1156
1157#define PUT_SDB_DEF(a) \
1158do { \
1159 extern FILE *asm_out_text_file; \
b82b0773
MM		 1160 fprintf (asm_out_text_file, "\t%s.def\t", \
1161 (TARGET_GAS) ? "" : "#"); \
e75b25e7
MM		 1162 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1163 fputc (';', asm_out_text_file); \
1164} while (0)
1165
1166#define PUT_SDB_PLAIN_DEF(a) \
1167do { \
1168 extern FILE *asm_out_text_file; \
b82b0773
MM		 1169 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1170 (TARGET_GAS) ? "" : "#", (a)); \
e75b25e7
MM		 1171} while (0)
1172
1173#define PUT_SDB_ENDEF \
1174do { \
1175 extern FILE *asm_out_text_file; \
1176 fprintf (asm_out_text_file, "\t.endef\n"); \
1177} while (0)
1178
1179#define PUT_SDB_TYPE(a) \
1180do { \
1181 extern FILE *asm_out_text_file; \
1182 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1183} while (0)
1184
1185#define PUT_SDB_SIZE(a) \
1186do { \
1187 extern FILE *asm_out_text_file; \
1188 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1189} while (0)
1190
1191#define PUT_SDB_DIM(a) \
1192do { \
1193 extern FILE *asm_out_text_file; \
1194 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1195} while (0)
1196
1197#ifndef PUT_SDB_START_DIM
1198#define PUT_SDB_START_DIM \
1199do { \
1200 extern FILE *asm_out_text_file; \
1201 fprintf (asm_out_text_file, "\t.dim\t"); \
1202} while (0)
1203#endif
1204
1205#ifndef PUT_SDB_NEXT_DIM
1206#define PUT_SDB_NEXT_DIM(a) \
1207do { \
1208 extern FILE *asm_out_text_file; \
1209 fprintf (asm_out_text_file, "%d,", a); \
1210} while (0)
1211#endif
1212
1213#ifndef PUT_SDB_LAST_DIM
1214#define PUT_SDB_LAST_DIM(a) \
1215do { \
1216 extern FILE *asm_out_text_file; \
1217 fprintf (asm_out_text_file, "%d;", a); \
1218} while (0)
1219#endif
1220
1221#define PUT_SDB_TAG(a) \
1222do { \
1223 extern FILE *asm_out_text_file; \
1224 fprintf (asm_out_text_file, "\t.tag\t"); \
1225 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1226 fputc (';', asm_out_text_file); \
1227} while (0)
1228
1229/* For block start and end, we create labels, so that
1230 later we can figure out where the correct offset is.
1231 The normal .ent/.end serve well enough for functions,
1232 so those are just commented out. */
1233
1234#define PUT_SDB_BLOCK_START(LINE) \
1235do { \
1236 extern FILE *asm_out_text_file; \
1237 fprintf (asm_out_text_file, \
6ae1498b
JW		 1238 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1239 LOCAL_LABEL_PREFIX, \
e75b25e7 1240 sdb_label_count, \
b82b0773 1241 (TARGET_GAS) ? "" : "#", \
6ae1498b 1242 LOCAL_LABEL_PREFIX, \
e75b25e7
MM		 1243 sdb_label_count, \
1244 (LINE)); \
1245 sdb_label_count++; \
1246} while (0)
1247
1248#define PUT_SDB_BLOCK_END(LINE) \
1249do { \
1250 extern FILE *asm_out_text_file; \
1251 fprintf (asm_out_text_file, \
6ae1498b
JW		 1252 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1253 LOCAL_LABEL_PREFIX, \
e75b25e7 1254 sdb_label_count, \
b82b0773 1255 (TARGET_GAS) ? "" : "#", \
6ae1498b 1256 LOCAL_LABEL_PREFIX, \
e75b25e7
MM		 1257 sdb_label_count, \
1258 (LINE)); \
1259 sdb_label_count++; \
1260} while (0)
1261
1262#define PUT_SDB_FUNCTION_START(LINE)
1263
a642a781
RK		 1264#define PUT_SDB_FUNCTION_END(LINE) \
1265do { \
1266 extern FILE *asm_out_text_file; \
1267 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1268} while (0)
e75b25e7
MM		 1269
1270#define PUT_SDB_EPILOGUE_END(NAME)
1271
cc694a81
DE		 1272#define PUT_SDB_SRC_FILE(FILENAME) \
1273do { \
1274 extern FILE *asm_out_text_file; \
1275 output_file_directive (asm_out_text_file, (FILENAME)); \
1276} while (0)
1277
e75b25e7
MM		 1278#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1279 sprintf ((BUFFER), ".%dfake", (NUMBER));
1280
ab78d4a8
MM		 1281/* Correct the offset of automatic variables and arguments. Note that
1282 the MIPS debug format wants all automatic variables and arguments
1283 to be in terms of the virtual frame pointer (stack pointer before
1284 any adjustment in the function), while the MIPS 3.0 linker wants
1285 the frame pointer to be the stack pointer after the initial
1286 adjustment. */
e75b25e7 1287
f5963e61
JL		 1288#define DEBUGGER_AUTO_OFFSET(X) \
1289 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1290#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1291 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
31c714e3
MM		 1292
1293/* Tell collect that the object format is ECOFF */
1294#ifndef OBJECT_FORMAT_ROSE
1295#define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1296#define EXTENDED_COFF /* ECOFF, not normal coff */
1297#endif
1298
b61cccc2
RS		 1299#if 0 /* These definitions normally have no effect because
1300 MIPS systems define USE_COLLECT2, so
1301 assemble_constructor does nothing anyway. */
1302
b913db7d
MM		 1303/* Don't use the default definitions, because we don't have gld.
1304 Also, we don't want stabs when generating ECOFF output.
1305 Instead we depend on collect to handle these. */
1306
1307#define ASM_OUTPUT_CONSTRUCTOR(file, name)
1308#define ASM_OUTPUT_DESTRUCTOR(file, name)
1309
b61cccc2 1310#endif /* 0 */
e75b25e7
MM		 1311\f
1312/* Target machine storage layout */
1313
96abdcb1
ILT		 1314/* Define in order to support both big and little endian float formats
1315 in the same gcc binary. */
1316#define REAL_ARITHMETIC
1317
e75b25e7
MM		 1318/* Define this if most significant bit is lowest numbered
1319 in instructions that operate on numbered bit-fields.
1320*/
4851a75c 1321#define BITS_BIG_ENDIAN 0
e75b25e7
MM		 1322
1323/* Define this if most significant byte of a word is the lowest numbered. */
96abdcb1 1324#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7
MM		 1325
1326/* Define this if most significant word of a multiword number is the lowest. */
96abdcb1 1327#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7 1328
96abdcb1
ILT		 1329/* Define this to set the endianness to use in libgcc2.c, which can
1330 not depend on target_flags. */
1331#if !defined(MIPSEL) && !defined(__MIPSEL__)
1332#define LIBGCC2_WORDS_BIG_ENDIAN 1
e75b25e7 1333#else
96abdcb1 1334#define LIBGCC2_WORDS_BIG_ENDIAN 0
e75b25e7
MM		 1335#endif
1336
31c714e3 1337/* Number of bits in an addressable storage unit */
e75b25e7
MM		 1338#define BITS_PER_UNIT 8
1339
1340/* Width in bits of a "word", which is the contents of a machine register.
1341 Note that this is not necessarily the width of data type `int';
1342 if using 16-bit ints on a 68000, this would still be 32.
1343 But on a machine with 16-bit registers, this would be 16. */
876c09d3
JW		 1344#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1345#define MAX_BITS_PER_WORD 64
e75b25e7
MM		 1346
1347/* Width of a word, in units (bytes). */
876c09d3 1348#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
ef0e53ce 1349#define MIN_UNITS_PER_WORD 4
876c09d3
JW		 1350
1351/* For MIPS, width of a floating point register. */
1352#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
e75b25e7
MM		 1353
1354/* A C expression for the size in bits of the type `int' on the
1355 target machine. If you don't define this, the default is one
1356 word. */
876c09d3
JW		 1357#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1358#define MAX_INT_TYPE_SIZE 64
1359
1360/* Tell the preprocessor the maximum size of wchar_t. */
1361#ifndef MAX_WCHAR_TYPE_SIZE
1362#ifndef WCHAR_TYPE_SIZE
1363#define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1364#endif
1365#endif
e75b25e7
MM		 1366
1367/* A C expression for the size in bits of the type `short' on the
1368 target machine. If you don't define this, the default is half a
1369 word. (If this would be less than one storage unit, it is
1370 rounded up to one unit.) */
1371#define SHORT_TYPE_SIZE 16
1372
1373/* A C expression for the size in bits of the type `long' on the
1374 target machine. If you don't define this, the default is one
1375 word. */
876c09d3
JW		 1376#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1377#define MAX_LONG_TYPE_SIZE 64
e75b25e7
MM		 1378
1379/* A C expression for the size in bits of the type `long long' on the
1380 target machine. If you don't define this, the default is two
1381 words. */
923d630e 1382#define LONG_LONG_TYPE_SIZE 64
e75b25e7
MM		 1383
1384/* A C expression for the size in bits of the type `char' on the
1385 target machine. If you don't define this, the default is one
1386 quarter of a word. (If this would be less than one storage unit,
1387 it is rounded up to one unit.) */
1388#define CHAR_TYPE_SIZE BITS_PER_UNIT
1389
1390/* A C expression for the size in bits of the type `float' on the
1391 target machine. If you don't define this, the default is one
1392 word. */
1393#define FLOAT_TYPE_SIZE 32
1394
1395/* A C expression for the size in bits of the type `double' on the
1396 target machine. If you don't define this, the default is two
1397 words. */
1398#define DOUBLE_TYPE_SIZE 64
1399
1400/* A C expression for the size in bits of the type `long double' on
1401 the target machine. If you don't define this, the default is two
1402 words. */
1403#define LONG_DOUBLE_TYPE_SIZE 64
1404
1405/* Width in bits of a pointer.
1406 See also the macro `Pmode' defined below. */
1eeed24e 1407#ifndef POINTER_SIZE
fb1bf66d 1408#define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1eeed24e 1409#endif
e75b25e7
MM		 1410
1411/* Allocation boundary (in *bits*) for storing pointers in memory. */
1eeed24e 1412#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
e75b25e7
MM		 1413
1414/* Allocation boundary (in *bits*) for storing arguments in argument list. */
876c09d3 1415#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
e75b25e7
MM		 1416
1417/* Allocation boundary (in *bits*) for the code of a function. */
1418#define FUNCTION_BOUNDARY 32
1419
1420/* Alignment of field after `int : 0' in a structure. */
9e95597a 1421#define EMPTY_FIELD_BOUNDARY 32
e75b25e7
MM		 1422
1423/* Every structure's size must be a multiple of this. */
1424/* 8 is observed right on a DECstation and on riscos 4.02. */
1425#define STRUCTURE_SIZE_BOUNDARY 8
1426
1427/* There is no point aligning anything to a rounder boundary than this. */
1428#define BIGGEST_ALIGNMENT 64
1429
31c714e3 1430/* Set this nonzero if move instructions will actually fail to work
e75b25e7 1431 when given unaligned data. */
31c714e3 1432#define STRICT_ALIGNMENT 1
e75b25e7
MM		 1433
1434/* Define this if you wish to imitate the way many other C compilers
1435 handle alignment of bitfields and the structures that contain
1436 them.
1437
1438 The behavior is that the type written for a bitfield (`int',
1439 `short', or other integer type) imposes an alignment for the
1440 entire structure, as if the structure really did contain an
1441 ordinary field of that type. In addition, the bitfield is placed
1442 within the structure so that it would fit within such a field,
1443 not crossing a boundary for it.
1444
1445 Thus, on most machines, a bitfield whose type is written as `int'
1446 would not cross a four-byte boundary, and would force four-byte
1447 alignment for the whole structure. (The alignment used may not
1448 be four bytes; it is controlled by the other alignment
1449 parameters.)
1450
1451 If the macro is defined, its definition should be a C expression;
1452 a nonzero value for the expression enables this behavior. */
1453
1454#define PCC_BITFIELD_TYPE_MATTERS 1
1455
1456/* If defined, a C expression to compute the alignment given to a
1457 constant that is being placed in memory. CONSTANT is the constant
1458 and ALIGN is the alignment that the object would ordinarily have.
1459 The value of this macro is used instead of that alignment to align
1460 the object.
1461
1462 If this macro is not defined, then ALIGN is used.
1463
1464 The typical use of this macro is to increase alignment for string
1465 constants to be word aligned so that `strcpy' calls that copy
1466 constants can be done inline. */
1467
1468#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1469 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1470 && (ALIGN) < BITS_PER_WORD \
1471 ? BITS_PER_WORD \
1472 : (ALIGN))
1473
1474/* If defined, a C expression to compute the alignment for a static
1475 variable. TYPE is the data type, and ALIGN is the alignment that
1476 the object would ordinarily have. The value of this macro is used
1477 instead of that alignment to align the object.
1478
1479 If this macro is not defined, then ALIGN is used.
1480
1481 One use of this macro is to increase alignment of medium-size
1482 data to make it all fit in fewer cache lines. Another is to
1483 cause character arrays to be word-aligned so that `strcpy' calls
1484 that copy constants to character arrays can be done inline. */
1485
1486#undef DATA_ALIGNMENT
1487#define DATA_ALIGNMENT(TYPE, ALIGN) \
1488 ((((ALIGN) < BITS_PER_WORD) \
1489 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1490 || TREE_CODE (TYPE) == UNION_TYPE \
1491 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1492
1493/* Define this macro if an argument declared as `char' or `short' in a
1494 prototype should actually be passed as an `int'. In addition to
1495 avoiding errors in certain cases of mismatch, it also makes for
1496 better code on certain machines. */
1497
cb560352 1498#define PROMOTE_PROTOTYPES 1
e75b25e7 1499
9a63901f
RK		 1500/* Define if operations between registers always perform the operation
1501 on the full register even if a narrower mode is specified. */
1502#define WORD_REGISTER_OPERATIONS
1503
1504/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1505 will either zero-extend or sign-extend. The value of this macro should
1506 be the code that says which one of the two operations is implicitly
a872728c
JL		 1507 done, NIL if none.
1508
1509 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1510 moves. All other referces are zero extended. */
1511#define LOAD_EXTEND_OP(MODE) \
1512 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1513 ? SIGN_EXTEND : ZERO_EXTEND)
2bcb2ab3
GK		 1514
1515/* Define this macro if it is advisable to hold scalars in registers
1516 in a wider mode than that declared by the program. In such cases,
1517 the value is constrained to be within the bounds of the declared
1518 type, but kept valid in the wider mode. The signedness of the
1519 extension may differ from that of the type.
1520
1521 We promote any value smaller than SImode up to SImode. We don't
1522 want to promote to DImode when in 64 bit mode, because that would
1523 prevent us from using the faster SImode multiply and divide
1524 instructions. */
1525
1526#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1527 if (GET_MODE_CLASS (MODE) == MODE_INT \
1528 && GET_MODE_SIZE (MODE) < 4) \
1529 (MODE) = SImode;
1530
1531/* Define this if function arguments should also be promoted using the above
1532 procedure. */
1533
1534#define PROMOTE_FUNCTION_ARGS
1535
1536/* Likewise, if the function return value is promoted. */
1537
1538#define PROMOTE_FUNCTION_RETURN
e75b25e7
MM		 1539\f
1540/* Standard register usage. */
1541
1542/* Number of actual hardware registers.
1543 The hardware registers are assigned numbers for the compiler
1544 from 0 to just below FIRST_PSEUDO_REGISTER.
1545 All registers that the compiler knows about must be given numbers,
1546 even those that are not normally considered general registers.
1547
225b8835 1548 On the Mips, we have 32 integer registers, 32 floating point
b8eb88d0
ILT		 1549 registers, 8 condition code registers, and the special registers
1550 hi, lo, hilo, and rap. The 8 condition code registers are only
1551 used if mips_isa >= 4. The hilo register is only used in 64 bit
1552 mode. It represents a 64 bit value stored as two 32 bit values in
1553 the hi and lo registers; this is the result of the mult
1554 instruction. rap is a pointer to the stack where the return
1555 address reg ($31) was stored. This is needed for C++ exception
1556 handling. */
e75b25e7 1557
b8eb88d0 1558#define FIRST_PSEUDO_REGISTER 76
e75b25e7
MM		 1559
1560/* 1 for registers that have pervasive standard uses
1561 and are not available for the register allocator.
1562
1563 On the MIPS, see conventions, page D-2 */
1564
1565#define FIXED_REGISTERS \
1566{ \
1567 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
b8eb88d0 1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
e75b25e7
MM		 1572}
1573
1574
1575/* 1 for registers not available across function calls.
1576 These must include the FIXED_REGISTERS and also any
1577 registers that can be used without being saved.
1578 The latter must include the registers where values are returned
1579 and the register where structure-value addresses are passed.
1580 Aside from that, you can include as many other registers as you like. */
1581
1582#define CALL_USED_REGISTERS \
1583{ \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
b8eb88d0 1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
e75b25e7
MM		 1589}
1590
1591
1592/* Internal macros to classify a register number as to whether it's a
1593 general purpose register, a floating point register, a
516a2dfd 1594 multiply/divide register, or a status register. */
e75b25e7
MM		 1595
1596#define GP_REG_FIRST 0
1597#define GP_REG_LAST 31
1598#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1599#define GP_DBX_FIRST 0
1600
1601#define FP_REG_FIRST 32
1602#define FP_REG_LAST 63
1603#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1604#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1605
1606#define MD_REG_FIRST 64
225b8835 1607#define MD_REG_LAST 66
e75b25e7
MM		 1608#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1609
225b8835 1610#define ST_REG_FIRST 67
b8eb88d0 1611#define ST_REG_LAST 74
e75b25e7
MM		 1612#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1613
b8eb88d0 1614#define RAP_REG_NUM 75
39dffea3 1615
e75b25e7
MM		 1616#define AT_REGNUM (GP_REG_FIRST + 1)
1617#define HI_REGNUM (MD_REG_FIRST + 0)
1618#define LO_REGNUM (MD_REG_FIRST + 1)
225b8835 1619#define HILO_REGNUM (MD_REG_FIRST + 2)
b8eb88d0
ILT		 1620
1621/* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1622 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1623 should be used instead. */
e75b25e7
MM		 1624#define FPSW_REGNUM ST_REG_FIRST
1625
1626#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
2bcb2ab3
GK		 1627#define M16_REG_P(REGNO) \
1628 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
e75b25e7
MM		 1629#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1630#define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
b8eb88d0 1631#define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
e75b25e7 1632
e75b25e7
MM		 1633/* Return number of consecutive hard regs needed starting at reg REGNO
1634 to hold something of mode MODE.
1635 This is ordinarily the length in words of a value of mode MODE
1636 but can be less for certain modes in special long registers.
1637
1638 On the MIPS, all general registers are one word long. Except on
1639 the R4000 with the FR bit set, the floating point uses register
956d6950 1640 pairs, with the second register not being allocable. */
e75b25e7
MM		 1641
1642#define HARD_REGNO_NREGS(REGNO, MODE) \
1643 (! FP_REG_P (REGNO) \
1644 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
ef9e5f13 1645 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
e75b25e7
MM		 1646
1647/* Value is 1 if hard register REGNO can hold a value of machine-mode
876c09d3
JW		 1648 MODE. In 32 bit mode, require that DImode and DFmode be in even
1649 registers. For DImode, this makes some of the insns easier to
1650 write, since you don't have to worry about a DImode value in
1651 registers 3 & 4, producing a result in 4 & 5.
e75b25e7
MM		 1652
1653 To make the code simpler HARD_REGNO_MODE_OK now just references an
1654 array built in override_options. Because machmodes.h is not yet
1655 included before this file is processed, the MODE bound can't be
1656 expressed here. */
1657
1658extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1659
1660#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1661 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1662
1663/* Value is 1 if it is a good idea to tie two pseudo registers
1664 when one has mode MODE1 and one has mode MODE2.
1665 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1666 for any hard reg, then this must be 0 for correct output. */
1667#define MODES_TIEABLE_P(MODE1, MODE2) \
1668 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1669 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1670 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1671 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1672
1673/* MIPS pc is not overloaded on a register. */
1674/* #define PC_REGNUM xx */
1675
1676/* Register to use for pushing function arguments. */
0fb5ac6f 1677#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
e75b25e7 1678
97116296
ILT		 1679/* Offset from the stack pointer to the first available location. Use
1680 the default value zero. */
1681/* #define STACK_POINTER_OFFSET 0 */
e75b25e7 1682
2bcb2ab3
GK		 1683/* Base register for access to local variables of the function. We
1684 pretend that the frame pointer is $1, and then eliminate it to
1685 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1686 a fixed register, and will not be used for anything else. */
1687#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1688
0ff83799
MM		 1689/* Temporary scratch register for use by the assembler. */
1690#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1691
2bcb2ab3
GK		 1692/* $30 is not available on the mips16, so we use $17 as the frame
1693 pointer. */
1694#define HARD_FRAME_POINTER_REGNUM \
1695 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
e75b25e7
MM		 1696
1697/* Value should be nonzero if functions must have frame pointers.
1698 Zero means the frame pointer need not be set up (and parms
1699 may be accessed via the stack pointer) in functions that seem suitable.
1700 This is computed in `reload', in reload1.c. */
1701#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1702
1703/* Base register for access to arguments of the function. */
ab78d4a8 1704#define ARG_POINTER_REGNUM GP_REG_FIRST
e75b25e7 1705
39dffea3
JW		 1706/* Fake register that holds the address on the stack of the
1707 current function's return address. */
1708#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1709
e75b25e7 1710/* Register in which static-chain is passed to a function. */
0fb5ac6f 1711#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
e75b25e7 1712
1154b096
MM		 1713/* If the structure value address is passed in a register, then
1714 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1715/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1716
1717/* If the structure value address is not passed in a register, define
1718 `STRUCT_VALUE' as an expression returning an RTX for the place
1719 where the address is passed. If it returns 0, the address is
1720 passed as an "invisible" first argument. */
f58cfbfb 1721#define STRUCT_VALUE 0
e75b25e7
MM		 1722
1723/* Mips registers used in prologue/epilogue code when the stack frame
1724 is larger than 32K bytes. These registers must come from the
1725 scratch register set, and not used for passing and returning
1726 arguments and any other information used in the calling sequence
516a2dfd
JW		 1727 (such as pic). Must start at 12, since t0/t3 are parameter passing
1728 registers in the 64 bit ABI. */
7bea35e7 1729
516a2dfd
JW		 1730#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1731#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
e75b25e7
MM		 1732
1733/* Define this macro if it is as good or better to call a constant
1734 function address than to call an address kept in a register. */
1735#define NO_FUNCTION_CSE 1
1736
1737/* Define this macro if it is as good or better for a function to
1738 call itself with an explicit address than to call an address
1739 kept in a register. */
1740#define NO_RECURSIVE_FUNCTION_CSE 1
1741
1742/* The register number of the register used to address a table of
1743 static data addresses in memory. In some cases this register is
1744 defined by a processor's "application binary interface" (ABI).
1745 When this macro is defined, RTL is generated for this register
1746 once, as with the stack pointer and frame pointer registers. If
1747 this macro is not defined, it is up to the machine-dependent
1748 files to allocate such a register (if necessary). */
0fb5ac6f 1749#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
e75b25e7 1750
24e214e3
JW		 1751#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1752
77b597df
JW		 1753/* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1754 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1755 isn't always called for static inline functions. */
2bcb2ab3
GK		 1756#define INIT_EXPANDERS \
1757do { \
1758 embedded_pic_fnaddr_rtx = NULL; \
1759 mips16_gp_pseudo_rtx = NULL; \
1760} while (0)
e75b25e7
MM		 1761\f
1762/* Define the classes of registers for register constraints in the
1763 machine description. Also define ranges of constants.
1764
1765 One of the classes must always be named ALL_REGS and include all hard regs.
1766 If there is more than one class, another class must be named NO_REGS
1767 and contain no registers.
1768
1769 The name GENERAL_REGS must be the name of a class (or an alias for
1770 another name such as ALL_REGS). This is the class of registers
1771 that is allowed by "g" or "r" in a register constraint.
1772 Also, registers outside this class are allocated only when
1773 instructions express preferences for them.
1774
1775 The classes must be numbered in nondecreasing order; that is,
1776 a larger-numbered class must never be contained completely
1777 in a smaller-numbered class.
1778
1779 For any two classes, it is very desirable that there be another
1780 class that represents their union. */
1781
1782enum reg_class
1783{
1784 NO_REGS, /* no registers in set */
2bcb2ab3
GK		 1785 M16_NA_REGS, /* mips16 regs not used to pass args */
1786 M16_REGS, /* mips16 directly accessible registers */
1787 T_REG, /* mips16 T register ($24) */
1788 M16_T_REGS, /* mips16 registers plus T register */
e75b25e7
MM		 1789 GR_REGS, /* integer registers */
1790 FP_REGS, /* floating point registers */
1791 HI_REG, /* hi register */
1792 LO_REG, /* lo register */
225b8835 1793 HILO_REG, /* hilo register pair for 64 bit mode mult */
e75b25e7 1794 MD_REGS, /* multiply/divide registers (hi/lo) */
e4f5c5d6
KR		 1795 HI_AND_GR_REGS, /* union classes */
1796 LO_AND_GR_REGS,
1797 HILO_AND_GR_REGS,
e75b25e7
MM		 1798 ST_REGS, /* status registers (fp status) */
1799 ALL_REGS, /* all registers */
1800 LIM_REG_CLASSES /* max value + 1 */
1801};
1802
1803#define N_REG_CLASSES (int) LIM_REG_CLASSES
1804
1805#define GENERAL_REGS GR_REGS
1806
1807/* An initializer containing the names of the register classes as C
1808 string constants. These names are used in writing some of the
1809 debugging dumps. */
1810
1811#define REG_CLASS_NAMES \
1812{ \
1813 "NO_REGS", \
2bcb2ab3
GK		 1814 "M16_NA_REGS", \
1815 "M16_REGS", \
1816 "T_REG", \
1817 "M16_T_REGS", \
e75b25e7
MM		 1818 "GR_REGS", \
1819 "FP_REGS", \
1820 "HI_REG", \
1821 "LO_REG", \
225b8835 1822 "HILO_REG", \
e75b25e7 1823 "MD_REGS", \
e4f5c5d6
KR		 1824 "HI_AND_GR_REGS", \
1825 "LO_AND_GR_REGS", \
1826 "HILO_AND_GR_REGS", \
e75b25e7
MM		 1827 "ST_REGS", \
1828 "ALL_REGS" \
1829}
1830
1831/* An initializer containing the contents of the register classes,
1832 as integers which are bit masks. The Nth integer specifies the
1833 contents of class N. The way the integer MASK is interpreted is
1834 that register R is in the class if `MASK & (1 << R)' is 1.
1835
1836 When the machine has more than 32 registers, an integer does not
1837 suffice. Then the integers are replaced by sub-initializers,
1838 braced groupings containing several integers. Each
1839 sub-initializer must be suitable as an initializer for the type
1840 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1841
1842#define REG_CLASS_CONTENTS \
1843{ \
1844 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2bcb2ab3
GK		 1845 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1846 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1847 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1848 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
e75b25e7
MM		 1849 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1850 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
2e7bfcec
MM		 1851 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1852 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
225b8835 1853 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
e75b25e7 1854 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
e4f5c5d6
KR		 1855 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1856 { 0xffffffff, 0x00000000, 0x00000002 }, \
1857 { 0xffffffff, 0x00000000, 0x00000004 }, \
b8eb88d0
ILT		 1858 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1859 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
e75b25e7
MM		 1860}
1861
1862
1863/* A C expression whose value is a register class containing hard
1864 register REGNO. In general there is more that one such class;
1865 choose a class which is "minimal", meaning that no smaller class
1866 also contains the register. */
1867
1868extern enum reg_class mips_regno_to_class[];
1869
1870#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1871
1872/* A macro whose definition is the name of the class to which a
1873 valid base register must belong. A base register is one used in
1874 an address which is the register value plus a displacement. */
1875
2bcb2ab3 1876#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
e75b25e7
MM		 1877
1878/* A macro whose definition is the name of the class to which a
1879 valid index register must belong. An index register is one used
1880 in an address where its value is either multiplied by a scale
1881 factor or added to another register (as well as added to a
1882 displacement). */
1883
876c09d3 1884#define INDEX_REG_CLASS NO_REGS
e75b25e7 1885
2bcb2ab3
GK		 1886/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1887 registers explicitly used in the rtl to be used as spill registers
1888 but prevents the compiler from extending the lifetime of these
1889 registers. */
1890
1891#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1892
1893/* This macro is used later on in the file. */
1894#define GR_REG_CLASS_P(CLASS) \
1895 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1896 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1897
1898/* REG_ALLOC_ORDER is to order in which to allocate registers. This
1899 is the default value (allocate the registers in numeric order). We
1900 define it just so that we can override it for the mips16 target in
1901 ORDER_REGS_FOR_LOCAL_ALLOC. */
1902
1903#define REG_ALLOC_ORDER \
1904{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1905 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1906 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1907 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1908 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1909}
1910
1911/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1912 to be rearranged based on a particular function. On the mips16, we
1913 want to allocate $24 (T_REG) before other registers for
1914 instructions for which it is possible. */
1915
1916#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
e75b25e7
MM		 1917
1918/* REGISTER AND CONSTANT CLASSES */
1919
1920/* Get reg_class from a letter such as appears in the machine
1921 description.
1922
1923 DEFINED REGISTER CLASSES:
1924
1925 'd' General (aka integer) registers
2bcb2ab3
GK		 1926 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1927 'y' General registers (in both mips16 and non mips16 mode)
1928 'e' mips16 non argument registers (M16_NA_REGS)
1929 't' mips16 temporary register ($24)
e75b25e7
MM		 1930 'f' Floating point registers
1931 'h' Hi register
1932 'l' Lo register
34b650b3 1933 'x' Multiply/divide registers
225b8835
ILT		 1934 'a' HILO_REG
1935 'z' FP Status register
1936 'b' All registers */
e75b25e7
MM		 1937
1938extern enum reg_class mips_char_to_class[];
1939
1940#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1941
1942/* The letters I, J, K, L, M, N, O, and P in a register constraint
1943 string can be used to stand for particular ranges of immediate
1944 operands. This macro defines what the ranges are. C is the
1945 letter, and VALUE is a constant value. Return 1 if VALUE is
1946 in the range specified by C. */
1947
1948/* For MIPS:
1949
1950 `I' is used for the range of constants an arithmetic insn can
1951 actually contain (16 bits signed integers).
1952
1953 `J' is used for the range which is just zero (ie, $r0).
1954
1955 `K' is used for the range of constants a logical insn can actually
1956 contain (16 bit zero-extended integers).
1957
1958 `L' is used for the range of constants that be loaded with lui
1959 (ie, the bottom 16 bits are zero).
1960
1961 `M' is used for the range of constants that take two words to load
1962 (ie, not matched by `I', `K', and `L').
1963
2bcb2ab3 1964 `N' is used for negative 16 bit constants other than -65536.
e75b25e7 1965
2bcb2ab3 1966 `O' is a 15 bit signed integer.
e75b25e7
MM		 1967
1968 `P' is used for positive 16 bit constants. */
1969
516a2dfd
JW		 1970#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1971#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
e75b25e7
MM		 1972
1973#define CONST_OK_FOR_LETTER_P(VALUE, C) \
516a2dfd 1974 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
e75b25e7 1975 : (C) == 'J' ? ((VALUE) == 0) \
516a2dfd 1976 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
876c09d3
JW		 1977 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1978 && (((VALUE) & ~2147483647) == 0 \
1979 || ((VALUE) & ~2147483647) == ~2147483647)) \
99cbc4b0
MM		 1980 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1981 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
876c09d3
JW		 1982 && (((VALUE) & 0x0000ffff) != 0 \
1983 || (((VALUE) & ~2147483647) != 0 \
1984 && ((VALUE) & ~2147483647) != ~2147483647))) \
2bcb2ab3
GK		 1985 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1986 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
99cbc4b0 1987 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
e75b25e7
MM		 1988 : 0)
1989
1990/* Similar, but for floating constants, and defining letters G and H.
1991 Here VALUE is the CONST_DOUBLE rtx itself. */
1992
1993/* For Mips
1994
1995 'G' : Floating point 0 */
1996
1997#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1998 ((C) == 'G' \
876c09d3 1999 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
e75b25e7
MM		 2000
2001/* Letters in the range `Q' through `U' may be defined in a
2002 machine-dependent fashion to stand for arbitrary operand types.
2003 The machine description macro `EXTRA_CONSTRAINT' is passed the
2004 operand as its first argument and the constraint letter as its
2005 second operand.
2006
2bcb2ab3 2007 `Q' is for mips16 GP relative constants
31c714e3 2008 `R' is for memory references which take 1 word for the instruction.
2bcb2ab3
GK		 2009 `S' is for references to extern items which are PIC for OSF/rose.
2010 `T' is for memory addresses that can be used to load two words. */
e75b25e7
MM		 2011
2012#define EXTRA_CONSTRAINT(OP,CODE) \
2bcb2ab3
GK		 2013 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2014 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2015 && mips16_gp_offset_p (OP)) \
2016 : (GET_CODE (OP) != MEM) ? FALSE \
e75b25e7 2017 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
31c714e3
MM		 2018 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2019 && HALF_PIC_ADDRESS_P (OP)) \
e75b25e7
MM		 2020 : FALSE)
2021
2022/* Given an rtx X being reloaded into a reg required to be
2023 in class CLASS, return the class of reg to actually use.
2024 In general this is just CLASS; but on some machines
2025 in some cases it is preferable to use a more restrictive class. */
2026
2027#define PREFERRED_RELOAD_CLASS(X,CLASS) \
876c09d3 2028 ((CLASS) != ALL_REGS \
2bcb2ab3
GK		 2029 ? (! TARGET_MIPS16 \
2030 ? (CLASS) \
2031 : ((CLASS) != GR_REGS \
2032 ? (CLASS) \
2033 : M16_REGS)) \
876c09d3
JW		 2034 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2035 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2bcb2ab3
GK		 2036 ? (TARGET_SOFT_FLOAT \
2037 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2038 : FP_REGS) \
876c09d3
JW		 2039 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2040 || GET_MODE (X) == VOIDmode) \
2bcb2ab3 2041 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
876c09d3 2042 : (CLASS))))
e75b25e7 2043
0fb5ac6f
MM		 2044/* Certain machines have the property that some registers cannot be
2045 copied to some other registers without using memory. Define this
2046 macro on those machines to be a C expression that is non-zero if
2047 objects of mode MODE in registers of CLASS1 can only be copied to
2048 registers of class CLASS2 by storing a register of CLASS1 into
2049 memory and loading that memory location into a register of CLASS2.
2050
2051 Do not define this macro if its value would always be zero. */
2052
2053#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2370b831
JW		 2054 ((!TARGET_DEBUG_H_MODE \
2055 && GET_MODE_CLASS (MODE) == MODE_INT \
2bcb2ab3
GK		 2056 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2057 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2370b831 2058 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2bcb2ab3
GK		 2059 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2060 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
0fb5ac6f 2061
46299de9 2062/* The HI and LO registers can only be reloaded via the general
b8eb88d0
ILT		 2063 registers. Condition code registers can only be loaded to the
2064 general registers, and from the floating point registers. */
46299de9 2065
225b8835
ILT		 2066#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2067 mips_secondary_reload_class (CLASS, MODE, X, 1)
2068#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2069 mips_secondary_reload_class (CLASS, MODE, X, 0)
46299de9
ILT		 2070
2071/* Not declared above, with the other functions, because enum
2072 reg_class is not declared yet. */
2073extern enum reg_class mips_secondary_reload_class ();
2074
e75b25e7
MM		 2075/* Return the maximum number of consecutive registers
2076 needed to represent mode MODE in a register of class CLASS. */
2077
b206a757
JW		 2078#define CLASS_UNITS(mode, size) \
2079 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
574c75a3 2080
e75b25e7 2081#define CLASS_MAX_NREGS(CLASS, MODE) \
b206a757
JW		 2082 ((CLASS) == FP_REGS \
2083 ? (TARGET_FLOAT64 \
2084 ? CLASS_UNITS (MODE, 8) \
2085 : 2 * CLASS_UNITS (MODE, 8)) \
2086 : CLASS_UNITS (MODE, UNITS_PER_WORD))
e75b25e7 2087
87d9d860
R		 2088/* If defined, gives a class of registers that cannot be used as the
2089 operand of a SUBREG that changes the size of the object. */
2090
2091#define CLASS_CANNOT_CHANGE_SIZE \
2092 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2093
e75b25e7
MM		 2094/* If defined, this is a C expression whose value should be
2095 nonzero if the insn INSN has the effect of mysteriously
2096 clobbering the contents of hard register number REGNO. By
2097 "mysterious" we mean that the insn's RTL expression doesn't
2098 describe such an effect.
2099
2100 If this macro is not defined, it means that no insn clobbers
2101 registers mysteriously. This is the usual situation; all else
2102 being equal, it is best for the RTL expression to show all the
2103 activity. */
2104
2105/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
2106
2107\f
2108/* Stack layout; function entry, exit and calling. */
2109
2110/* Define this if pushing a word on the stack
2111 makes the stack pointer a smaller address. */
2112#define STACK_GROWS_DOWNWARD
2113
2114/* Define this if the nominal address of the stack frame
2115 is at the high-address end of the local variables;
2116 that is, each additional local variable allocated
2117 goes at a more negative offset in the frame. */
ab78d4a8 2118/* #define FRAME_GROWS_DOWNWARD */
e75b25e7
MM		 2119
2120/* Offset within stack frame to start allocating local variables at.
2121 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2122 first local allocated. Otherwise, it is the offset to the BEGINNING
2123 of the first local allocated. */
24e214e3
JW		 2124#define STARTING_FRAME_OFFSET \
2125 (current_function_outgoing_args_size \
2126 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
ab78d4a8
MM		 2127
2128/* Offset from the stack pointer register to an item dynamically
2129 allocated on the stack, e.g., by `alloca'.
2130
2131 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2132 length of the outgoing arguments. The default is correct for most
2133 machines. See `function.c' for details.
2134
51bdc4d3
MM		 2135 The MIPS ABI states that functions which dynamically allocate the
2136 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2137 we are trying to create a second frame pointer to the function, so
2138 allocate some stack space to make it happy.
ab78d4a8 2139
51bdc4d3
MM		 2140 However, the linker currently complains about linking any code that
2141 dynamically allocates stack space, and there seems to be a bug in
2142 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2143
2144#if 0
ab78d4a8
MM		 2145#define STACK_DYNAMIC_OFFSET(FUNDECL) \
2146 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2147 ? 4*UNITS_PER_WORD \
2148 : current_function_outgoing_args_size)
51bdc4d3 2149#endif
e75b25e7 2150
39dffea3
JW		 2151/* The return address for the current frame is in r31 is this is a leaf
2152 function. Otherwise, it is on the stack. It is at a variable offset
2153 from sp/fp/ap, so we define a fake hard register rap which is a
2154 poiner to the return address on the stack. This always gets eliminated
2155 during reload to be either the frame pointer or the stack pointer plus
2156 an offset. */
2157
2158/* ??? This definition fails for leaf functions. There is currently no
2159 general solution for this problem. */
2160
2161/* ??? There appears to be no way to get the return address of any previous
2162 frame except by disassembling instructions in the prologue/epilogue.
2163 So currently we support only the current frame. */
2164
2165#define RETURN_ADDR_RTX(count, frame) \
2166 ((count == 0) \
c5c76735 2167 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
24ba333f 2168 : (rtx) 0)
39dffea3 2169
e75b25e7
MM		 2170/* Structure to be filled in by compute_frame_size with register
2171 save masks, and offsets for the current function. */
2172
2173struct mips_frame_info
2174{
7bea35e7
MM		 2175 long total_size; /* # bytes that the entire frame takes up */
2176 long var_size; /* # bytes that variables take up */
2177 long args_size; /* # bytes that outgoing arguments take up */
2178 long extra_size; /* # bytes of extra gunk */
2179 int gp_reg_size; /* # bytes needed to store gp regs */
2180 int fp_reg_size; /* # bytes needed to store fp regs */
2181 long mask; /* mask of saved gp registers */
2182 long fmask; /* mask of saved fp registers */
2183 long gp_save_offset; /* offset from vfp to store gp registers */
2184 long fp_save_offset; /* offset from vfp to store fp registers */
2185 long gp_sp_offset; /* offset from new sp to store gp registers */
2186 long fp_sp_offset; /* offset from new sp to store fp registers */
2187 int initialized; /* != 0 if frame size already calculated */
2188 int num_gp; /* number of gp registers saved */
2189 int num_fp; /* number of fp registers saved */
2bcb2ab3 2190 long insns_len; /* length of insns; mips16 only */
e75b25e7
MM		 2191};
2192
2193extern struct mips_frame_info current_frame_info;
2194
ab78d4a8
MM		 2195/* If defined, this macro specifies a table of register pairs used to
2196 eliminate unneeded registers that point into the stack frame. If
2197 it is not defined, the only elimination attempted by the compiler
2198 is to replace references to the frame pointer with references to
2199 the stack pointer.
2200
2201 The definition of this macro is a list of structure
2202 initializations, each of which specifies an original and
2203 replacement register.
2204
2205 On some machines, the position of the argument pointer is not
2206 known until the compilation is completed. In such a case, a
2207 separate hard register must be used for the argument pointer.
2208 This register can be eliminated by replacing it with either the
2209 frame pointer or the argument pointer, depending on whether or not
2210 the frame pointer has been eliminated.
2211
2212 In this case, you might specify:
2213 #define ELIMINABLE_REGS \
2214 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2215 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2216 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2217
2218 Note that the elimination of the argument pointer with the stack
2bcb2ab3
GK		 2219 pointer is specified first since that is the preferred elimination.
2220
2221 The eliminations to $17 are only used on the mips16. See the
2222 definition of HARD_FRAME_POINTER_REGNUM. */
ab78d4a8
MM		 2223
2224#define ELIMINABLE_REGS \
2225{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2bcb2ab3
GK		 2226 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2227 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
39dffea3 2228 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2bcb2ab3
GK		 2229 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2230 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
08c2951c 2231 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2bcb2ab3
GK		 2232 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2233 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2234 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
ab78d4a8 2235
ab78d4a8
MM		 2236/* A C expression that returns non-zero if the compiler is allowed to
2237 try to replace register number FROM-REG with register number
2238 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2239 defined, and will usually be the constant 1, since most of the
2240 cases preventing register elimination are things that the compiler
2bcb2ab3
GK		 2241 already knows about.
2242
365ca18b
GK		 2243 When not in mips16 and mips64, we can always eliminate to the
2244 frame pointer. We can eliminate to the stack pointer unless
2245 a frame pointer is needed. In mips16 mode, we need a frame
2246 pointer for a large frame; otherwise, reload may be unable
2247 to compute the address of a local variable, since there is
2248 no way to add a large constant to the stack pointer
2249 without using a temporary register.
2250
2251 In mips16, for some instructions (eg lwu), we can't eliminate the
2252 frame pointer for the stack pointer. These instructions are
2253 only generated in TARGET_64BIT mode.
2254 */
ab78d4a8
MM		 2255
2256#define CAN_ELIMINATE(FROM, TO) \
08c2951c 2257 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
973838fd 2258 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
08c2951c
SC		 2259 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2260 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2bcb2ab3 2261 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
365ca18b 2262 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2bcb2ab3 2263 && (! TARGET_MIPS16 \
08c2951c 2264 || compute_frame_size (get_frame_size ()) < 32768)))))
ab78d4a8
MM		 2265
2266/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2267 specifies the initial difference between the specified pair of
2268 registers. This macro must be defined if `ELIMINABLE_REGS' is
2269 defined. */
2270
2271#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2272{ compute_frame_size (get_frame_size ()); \
2bcb2ab3
GK		 2273 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2274 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2275 (OFFSET) = - current_function_outgoing_args_size; \
2276 else if ((FROM) == FRAME_POINTER_REGNUM) \
ab78d4a8 2277 (OFFSET) = 0; \
2bcb2ab3
GK		 2278 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2279 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2280 (OFFSET) = (current_frame_info.total_size \
2281 - current_function_outgoing_args_size \
a53f72db
GRK		 2282 - ((mips_abi != ABI_32 \
2283 && mips_abi != ABI_O64 \
2284 && mips_abi != ABI_EABI) \
2bcb2ab3
GK		 2285 ? current_function_pretend_args_size \
2286 : 0)); \
2287 else if ((FROM) == ARG_POINTER_REGNUM) \
a2ef6e41 2288 (OFFSET) = (current_frame_info.total_size \
a53f72db
GRK		 2289 - ((mips_abi != ABI_32 \
2290 && mips_abi != ABI_O64 \
2291 && mips_abi != ABI_EABI) \
a2ef6e41
RK		 2292 ? current_function_pretend_args_size \
2293 : 0)); \
c9b4de06
JW		 2294 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2295 so we must add 4 bytes to the offset to get the right value. */ \
2bcb2ab3 2296 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
973838fd 2297 { \
08c2951c
SC		 2298 if (leaf_function_p ()) \
2299 (OFFSET) = 0; \
2300 else (OFFSET) = current_frame_info.gp_sp_offset \
c9b4de06
JW		 2301 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2302 * (BYTES_BIG_ENDIAN != 0)); \
973838fd 2303 } \
ab78d4a8
MM		 2304}
2305
e75b25e7
MM		 2306/* If we generate an insn to push BYTES bytes,
2307 this says how many the stack pointer really advances by.
2308 On the vax, sp@- in a byte insn really pushes a word. */
2309
2310/* #define PUSH_ROUNDING(BYTES) 0 */
2311
2312/* If defined, the maximum amount of space required for outgoing
2313 arguments will be computed and placed into the variable
2314 `current_function_outgoing_args_size'. No space will be pushed
2315 onto the stack for each call; instead, the function prologue
2316 should increase the stack frame size by this amount.
2317
2318 It is not proper to define both `PUSH_ROUNDING' and
2319 `ACCUMULATE_OUTGOING_ARGS'. */
2320#define ACCUMULATE_OUTGOING_ARGS
2321
6cb6c3b3
MM		 2322/* Offset from the argument pointer register to the first argument's
2323 address. On some machines it may depend on the data type of the
2324 function.
e75b25e7 2325
6cb6c3b3 2326 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
39282292
MM		 2327 the first argument's address.
2328
2329 On the MIPS, we must skip the first argument position if we are
876c09d3 2330 returning a structure or a union, to account for its address being
305aa9e2
MM		 2331 passed in $4. However, at the current time, this produces a compiler
2332 that can't bootstrap, so comment it out for now. */
e75b25e7 2333
305aa9e2 2334#if 0
6cb6c3b3
MM		 2335#define FIRST_PARM_OFFSET(FNDECL) \
2336 (FNDECL != 0 \
2337 && TREE_TYPE (FNDECL) != 0 \
2338 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2339 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
39282292
MM		 2340 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2341 ? UNITS_PER_WORD \
2342 : 0)
305aa9e2
MM		 2343#else
2344#define FIRST_PARM_OFFSET(FNDECL) 0
2345#endif
e75b25e7
MM		 2346
2347/* When a parameter is passed in a register, stack space is still
2348 allocated for it. For the MIPS, stack space must be allocated, cf
2349 Asm Lang Prog Guide page 7-8.
2350
2351 BEWARE that some space is also allocated for non existing arguments
2352 in register. In case an argument list is of form GF used registers
2353 are a0 (a2,a3), but we should push over a1... */
2354
516a2dfd
JW		 2355#define REG_PARM_STACK_SPACE(FNDECL) \
2356 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
e75b25e7
MM		 2357
2358/* Define this if it is the responsibility of the caller to
2359 allocate the area reserved for arguments passed in registers.
2360 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2361 of this macro is to determine whether the space is included in
2362 `current_function_outgoing_args_size'. */
2363#define OUTGOING_REG_PARM_STACK_SPACE
2364
2365/* Align stack frames on 64 bits (Double Word ). */
d1c17572 2366#ifndef STACK_BOUNDARY
e75b25e7 2367#define STACK_BOUNDARY 64
d1c17572 2368#endif
e75b25e7 2369
876c09d3 2370/* Make sure 4 words are always allocated on the stack. */
e75b25e7
MM		 2371
2372#ifndef STACK_ARGS_ADJUST
2373#define STACK_ARGS_ADJUST(SIZE) \
2374{ \
876c09d3
JW		 2375 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2376 SIZE.constant = 4 * UNITS_PER_WORD; \
e75b25e7
MM		 2377}
2378#endif
2379
2380\f
2381/* A C expression that should indicate the number of bytes of its
38e01259 2382 own arguments that a function pops on returning, or 0
e75b25e7
MM		 2383 if the function pops no arguments and the caller must therefore
2384 pop them all after the function returns.
2385
8b109b37
RK		 2386 FUNDECL is the declaration node of the function (as a tree).
2387
e75b25e7
MM		 2388 FUNTYPE is a C variable whose value is a tree node that
2389 describes the function in question. Normally it is a node of
2390 type `FUNCTION_TYPE' that describes the data type of the function.
2391 From this it is possible to obtain the data types of the value
2392 and arguments (if known).
2393
2394 When a call to a library function is being considered, FUNTYPE
2395 will contain an identifier node for the library function. Thus,
2396 if you need to distinguish among various library functions, you
2397 can do so by their names. Note that "library function" in this
2398 context means a function used to perform arithmetic, whose name
2399 is known specially in the compiler and was not mentioned in the
2400 C code being compiled.
2401
2402 STACK-SIZE is the number of bytes of arguments passed on the
2403 stack. If a variable number of bytes is passed, it is zero, and
2404 argument popping will always be the responsibility of the
2405 calling function. */
2406
8b109b37 2407#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
e75b25e7
MM		 2408
2409
2410/* Symbolic macros for the registers used to return integer and floating
2411 point values. */
2412
2413#define GP_RETURN (GP_REG_FIRST + 2)
2414#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2415
2416/* Symbolic macros for the first/last argument registers. */
2417
2418#define GP_ARG_FIRST (GP_REG_FIRST + 4)
2419#define GP_ARG_LAST (GP_REG_FIRST + 7)
2420#define FP_ARG_FIRST (FP_REG_FIRST + 12)
2421#define FP_ARG_LAST (FP_REG_FIRST + 15)
2422
2423#define MAX_ARGS_IN_REGISTERS 4
2424
2425/* Define how to find the value returned by a library function
2bcb2ab3
GK		 2426 assuming the value has mode MODE. Because we define
2427 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2428 PROMOTE_MODE does. */
e75b25e7
MM		 2429
2430#define LIBCALL_VALUE(MODE) \
2bcb2ab3
GK		 2431 gen_rtx (REG, \
2432 ((GET_MODE_CLASS (MODE) != MODE_INT \
2433 || GET_MODE_SIZE (MODE) >= 4) \
2434 ? (MODE) \
2435 : SImode), \
46299de9
ILT		 2436 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2437 && (! TARGET_SINGLE_FLOAT \
2438 || GET_MODE_SIZE (MODE) <= 4)) \
2439 ? FP_RETURN \
2440 : GP_RETURN))
e75b25e7
MM		 2441
2442/* Define how to find the value returned by a function.
2443 VALTYPE is the data type of the value (as a tree).
2444 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2445 otherwise, FUNC is 0. */
2446
2447#define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2448
2449
2450/* 1 if N is a possible register number for a function value.
2451 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2452 Currently, R2 and F0 are only implemented here (C has no complex type) */
2453
2454#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2455
46af8e31
JW		 2456/* 1 if N is a possible register number for function argument passing.
2457 We have no FP argument registers when soft-float. When FP registers
2458 are 32 bits, we can't directly reference the odd numbered ones. */
2459
2460#define FUNCTION_ARG_REGNO_P(N) \
2461 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
6e92f4b6 2462 || ((! TARGET_SOFT_FLOAT \
46af8e31 2463 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2bcb2ab3 2464 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
6e92f4b6 2465 && ! fixed_regs[N]))
e75b25e7
MM		 2466
2467/* A C expression which can inhibit the returning of certain function
2468 values in registers, based on the type of value. A nonzero value says
2469 to return the function value in memory, just as large structures are
2470 always returned. Here TYPE will be a C expression of type
2471 `tree', representing the data type of the value.
2472
e14fa9c4
DE		 2473 Note that values of mode `BLKmode' must be explicitly
2474 handled by this macro. Also, the option `-fpcc-struct-return'
e75b25e7
MM		 2475 takes effect regardless of this macro. On most systems, it is
2476 possible to leave the macro undefined; this causes a default
e14fa9c4
DE		 2477 definition to be used, whose value is the constant 1 for BLKmode
2478 values, and 0 otherwise.
e75b25e7
MM		 2479
2480 GCC normally converts 1 byte structures into chars, 2 byte
2481 structs into shorts, and 4 byte structs into ints, and returns
2482 them this way. Defining the following macro overrides this,
2483 to give us MIPS cc compatibility. */
2484
2485#define RETURN_IN_MEMORY(TYPE) \
e419152d 2486 (TYPE_MODE (TYPE) == BLKmode)
e75b25e7
MM		 2487\f
2488/* A code distinguishing the floating point format of the target
2489 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2490 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2491
2492#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2493
2494\f
2495/* Define a data type for recording info about an argument list
2496 during the scan of that argument list. This data type should
2497 hold all necessary information about the function itself
2498 and about the args processed so far, enough to enable macros
2499 such as FUNCTION_ARG to determine where the next arg should go.
2bcb2ab3
GK		 2500
2501 On the mips16, we need to keep track of which floating point
2502 arguments were passed in general registers, but would have been
2503 passed in the FP regs if this were a 32 bit function, so that we
2504 can move them to the FP regs if we wind up calling a 32 bit
2505 function. We record this information in fp_code, encoded in base
2506 four. A zero digit means no floating point argument, a one digit
2507 means an SFmode argument, and a two digit means a DFmode argument,
2508 and a three digit is not used. The low order digit is the first
2509 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2510 an SFmode argument. ??? A more sophisticated approach will be
2511 needed if MIPS_ABI != ABI_32. */
e75b25e7
MM		 2512
2513typedef struct mips_args {
3f1f8d8c
MM		 2514 int gp_reg_found; /* whether a gp register was found yet */
2515 int arg_number; /* argument number */
2516 int arg_words; /* # total words the arguments take */
293a36eb
ILT		 2517 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2518 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2bcb2ab3 2519 int fp_code; /* Mode of FP arguments (mips16) */
3f1f8d8c
MM		 2520 int num_adjusts; /* number of adjustments made */
2521 /* Adjustments made to args pass in regs. */
b796c573
RS		 2522 /* ??? The size is doubled to work around a
2523 bug in the code that sets the adjustments
2524 in function_arg. */
2525 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
e75b25e7
MM		 2526} CUMULATIVE_ARGS;
2527
2528/* Initialize a variable CUM of type CUMULATIVE_ARGS
2529 for a call to a function whose data type is FNTYPE.
2530 For a library call, FNTYPE is 0.
2531
2532*/
2533
2c7ee1a6 2534#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
e75b25e7
MM		 2535 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2536
2537/* Update the data in CUM to advance over an argument
2538 of mode MODE and data type TYPE.
2539 (TYPE is null for libcalls where that information may not be available.) */
2540
2541#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2542 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2543
2544/* Determine where to put an argument to a function.
2545 Value is zero to push the argument on the stack,
2546 or a hard register in which to store the argument.
2547
2548 MODE is the argument's machine mode.
2549 TYPE is the data type of the argument (as a tree).
2550 This is null for libcalls where that information may
2551 not be available.
2552 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2553 the preceding args and about the function being called.
2554 NAMED is nonzero if this argument is a named parameter
2555 (otherwise it is an extra parameter matching an ellipsis). */
2556
2557#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2558 function_arg( &CUM, MODE, TYPE, NAMED)
2559
2560/* For an arg passed partly in registers and partly in memory,
2561 this is the number of registers used.
2562 For args passed entirely in registers or entirely in memory, zero. */
2563
2564#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2565 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2566
2567/* If defined, a C expression that gives the alignment boundary, in
2568 bits, of an argument with the specified mode and type. If it is
2569 not defined, `PARM_BOUNDARY' is used for all arguments. */
2570
2571#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2572 (((TYPE) != 0) \
c84e2712 2573 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
e75b25e7
MM		 2574 ? PARM_BOUNDARY \
2575 : TYPE_ALIGN(TYPE)) \
2576 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2577 ? PARM_BOUNDARY \
2578 : GET_MODE_ALIGNMENT(MODE)))
2579
2580\f
2581/* This macro generates the assembly code for function entry.
2582 FILE is a stdio stream to output the code to.
2583 SIZE is an int: how many units of temporary storage to allocate.
2584 Refer to the array `regs_ever_live' to determine which registers
2585 to save; `regs_ever_live[I]' is nonzero if register number I
2586 is ever used in the function. This macro is responsible for
2587 knowing which registers should not be saved even if used. */
2588
2589#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2590
2591/* This macro generates the assembly code for function exit,
2592 on machines that need it. If FUNCTION_EPILOGUE is not defined
2593 then individual return instructions are generated for each
2594 return statement. Args are same as for FUNCTION_PROLOGUE. */
2595
2596#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2597
e75b25e7
MM		 2598/* Tell prologue and epilogue if register REGNO should be saved / restored. */
2599
2600#define MUST_SAVE_REGISTER(regno) \
2bcb2ab3
GK		 2601 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2602 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
ab78d4a8 2603 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
e75b25e7
MM		 2604
2605/* ALIGN FRAMES on double word boundaries */
d1c17572
JL		 2606#ifndef MIPS_STACK_ALIGN
2607#define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2608#endif
e75b25e7
MM		 2609
2610\f
2611/* Output assembler code to FILE to increment profiler label # LABELNO
2612 for profiling a function entry. */
2613
2614#define FUNCTION_PROFILER(FILE, LABELNO) \
2615{ \
2bcb2ab3
GK		 2616 if (TARGET_MIPS16) \
2617 sorry ("mips16 function profiling"); \
e75b25e7
MM		 2618 fprintf (FILE, "\t.set\tnoreorder\n"); \
2619 fprintf (FILE, "\t.set\tnoat\n"); \
2620 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2621 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2622 fprintf (FILE, "\tjal\t_mcount\n"); \
876c09d3
JW		 2623 fprintf (FILE, \
2624 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2625 TARGET_64BIT ? "dsubu" : "subu", \
e75b25e7 2626 reg_names[STACK_POINTER_REGNUM], \
876c09d3 2627 reg_names[STACK_POINTER_REGNUM], \
1eeed24e 2628 Pmode == DImode ? 16 : 8); \
e75b25e7
MM		 2629 fprintf (FILE, "\t.set\treorder\n"); \
2630 fprintf (FILE, "\t.set\tat\n"); \
2631}
2632
d8d5b1e1
MM		 2633/* Define this macro if the code for function profiling should come
2634 before the function prologue. Normally, the profiling code comes
2635 after. */
2636
2637/* #define PROFILE_BEFORE_PROLOGUE */
2638
e75b25e7
MM		 2639/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2640 the stack pointer does not matter. The value is tested only in
2641 functions that have frame pointers.
2642 No definition is equivalent to always zero. */
2643
2644#define EXIT_IGNORE_STACK 1
2645
2646\f
2647/* A C statement to output, on the stream FILE, assembler code for a
2648 block of data that contains the constant parts of a trampoline.
2649 This code should not include a label--the label is taken care of
2650 automatically. */
2651
2652#define TRAMPOLINE_TEMPLATE(STREAM) \
2653{ \
2654 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2655 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2656 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
1eeed24e 2657 if (Pmode == DImode) \
876c09d3
JW		 2658 { \
2659 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2660 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2661 } \
2662 else \
2663 { \
0acefe54
JW		 2664 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2665 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
876c09d3 2666 } \
0acefe54 2667 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
e75b25e7
MM		 2668 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2669 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
1eeed24e 2670 if (Pmode == DImode) \
876c09d3 2671 { \
876c09d3
JW		 2672 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2673 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2674 } \
2675 else \
2676 { \
2677 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2678 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2679 } \
e75b25e7
MM		 2680}
2681
2682/* A C expression for the size in bytes of the trampoline, as an
2683 integer. */
2684
1eeed24e 2685#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
e75b25e7 2686
876c09d3 2687/* Alignment required for trampolines, in bits. */
e75b25e7 2688
1eeed24e 2689#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
e75b25e7 2690
c85f7c16
JL		 2691/* INITIALIZE_TRAMPOLINE calls this library function to flush
2692 program and data caches. */
2693
2694#ifndef CACHE_FLUSH_FUNC
2695#define CACHE_FLUSH_FUNC "_flush_cache"
2696#endif
2697
e75b25e7
MM		 2698/* A C statement to initialize the variable parts of a trampoline.
2699 ADDR is an RTX for the address of the trampoline; FNADDR is an
2700 RTX for the address of the nested function; STATIC_CHAIN is an
2701 RTX for the static chain value that should be passed to the
2702 function when it is called. */
2703
2704#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2705{ \
2706 rtx addr = ADDR; \
1eeed24e 2707 if (Pmode == DImode) \
876c09d3 2708 { \
c5c76735
JL		 2709 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2710 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
876c09d3
JW		 2711 } \
2712 else \
2713 { \
c5c76735
JL		 2714 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2715 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
876c09d3 2716 } \
e75b25e7 2717 \
22b54c57
RK		 2718 /* Flush both caches. We need to flush the data cache in case \
2719 the system has a write-back cache. */ \
876c09d3 2720 /* ??? Should check the return value for errors. */ \
c5c76735 2721 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
876c09d3 2722 0, VOIDmode, 3, addr, Pmode, \
01d74729 2723 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
22b54c57 2724 GEN_INT (3), TYPE_MODE (integer_type_node)); \
e75b25e7 2725}
e75b25e7
MM		 2726\f
2727/* Addressing modes, and classification of registers for them. */
2728
940da324
JL		 2729/* #define HAVE_POST_INCREMENT 0 */
2730/* #define HAVE_POST_DECREMENT 0 */
e75b25e7 2731
940da324
JL		 2732/* #define HAVE_PRE_DECREMENT 0 */
2733/* #define HAVE_PRE_INCREMENT 0 */
e75b25e7
MM		 2734
2735/* These assume that REGNO is a hard or pseudo reg number.
2736 They give nonzero only if REGNO is a hard reg of the suitable class
2737 or a pseudo reg currently allocated to a suitable hard reg.
2738 These definitions are NOT overridden anywhere. */
2739
2bcb2ab3
GK		 2740#define BASE_REG_P(regno, mode) \
2741 (TARGET_MIPS16 \
2742 ? (M16_REG_P (regno) \
2743 || (regno) == FRAME_POINTER_REGNUM \
2744 || (regno) == ARG_POINTER_REGNUM \
2745 || ((regno) == STACK_POINTER_REGNUM \
2746 && (GET_MODE_SIZE (mode) == 4 \
2747 || GET_MODE_SIZE (mode) == 8))) \
2748 : GP_REG_P (regno))
e75b25e7 2749
2bcb2ab3
GK		 2750#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2751 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2752 (mode))
2753
2754#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2755 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
e75b25e7 2756
876c09d3 2757#define REGNO_OK_FOR_INDEX_P(regno) 0
2bcb2ab3
GK		 2758#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2759 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
e75b25e7
MM		 2760
2761/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2762 and check its validity for a certain class.
2763 We have two alternate definitions for each of them.
2764 The usual definition accepts all pseudo regs; the other rejects them all.
2765 The symbol REG_OK_STRICT causes the latter definition to be used.
2766
2767 Most source files want to accept pseudo regs in the hope that
2768 they will get allocated to the class that the insn wants them to be in.
2769 Some source files that are used after register allocation
2770 need to be strict. */
2771
2772#ifndef REG_OK_STRICT
2773
2774#define REG_OK_STRICT_P 0
876c09d3 2775#define REG_OK_FOR_INDEX_P(X) 0
2bcb2ab3
GK		 2776#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2777 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
e75b25e7
MM		 2778
2779#else
2780
2781#define REG_OK_STRICT_P 1
876c09d3 2782#define REG_OK_FOR_INDEX_P(X) 0
2bcb2ab3
GK		 2783#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2784 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
e75b25e7
MM		 2785
2786#endif
2787
2788\f
2789/* Maximum number of registers that can appear in a valid memory address. */
2790
2791#define MAX_REGS_PER_ADDRESS 1
2792
2793/* A C compound statement with a conditional `goto LABEL;' executed
2794 if X (an RTX) is a legitimate memory address on the target
2795 machine for a memory operand of mode MODE.
2796
2797 It usually pays to define several simpler macros to serve as
2798 subroutines for this one. Otherwise it may be too complicated
2799 to understand.
2800
2801 This macro must exist in two variants: a strict variant and a
2802 non-strict one. The strict variant is used in the reload pass.
2803 It must be defined so that any pseudo-register that has not been
2804 allocated a hard register is considered a memory reference. In
2805 contexts where some kind of register is required, a
2806 pseudo-register with no hard register must be rejected.
2807
2808 The non-strict variant is used in other passes. It must be
2809 defined to accept all pseudo-registers in every context where
2810 some kind of register is required.
2811
2812 Compiler source files that want to use the strict variant of
2813 this macro define the macro `REG_OK_STRICT'. You should use an
2814 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2815 in that case and the non-strict variant otherwise.
2816
2817 Typically among the subroutines used to define
2818 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2819 acceptable registers for various purposes (one for base
2820 registers, one for index registers, and so on). Then only these
2821 subroutine macros need have two variants; the higher levels of
2822 macros may be the same whether strict or not.
2823
2824 Normally, constant addresses which are the sum of a `symbol_ref'
2825 and an integer are stored inside a `const' RTX to mark them as
2826 constant. Therefore, there is no need to recognize such sums
2827 specifically as legitimate addresses. Normally you would simply
2828 recognize any `const' as legitimate.
2829
2830 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2831 constant sums that are not marked with `const'. It assumes
2832 that a naked `plus' indicates indexing. If so, then you *must*
2833 reject such naked constant sums as illegitimate addresses, so
2834 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2835
2836 On some machines, whether a symbolic address is legitimate
2837 depends on the section that the address refers to. On these
2838 machines, define the macro `ENCODE_SECTION_INFO' to store the
2839 information into the `symbol_ref', and then check for it here.
2840 When you see a `const', you will have to look inside it to find
2841 the `symbol_ref' in order to determine the section. */
2842
2843#if 1
2844#define GO_PRINTF(x) trace(x)
2845#define GO_PRINTF2(x,y) trace(x,y)
2846#define GO_DEBUG_RTX(x) debug_rtx(x)
2847
2848#else
2849#define GO_PRINTF(x)
2850#define GO_PRINTF2(x,y)
2851#define GO_DEBUG_RTX(x)
2852#endif
2853
2854#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2855{ \
2856 register rtx xinsn = (X); \
2857 \
2858 if (TARGET_DEBUG_B_MODE) \
2859 { \
2860 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2861 (REG_OK_STRICT_P) ? "" : "not "); \
2862 GO_DEBUG_RTX (xinsn); \
2863 } \
2864 \
51f0646f
JL		 2865 while (GET_CODE (xinsn) == SUBREG) \
2866 xinsn = SUBREG_REG (xinsn); \
2867 \
2bcb2ab3
GK		 2868 /* The mips16 can only use the stack pointer as a base register when \
2869 loading SImode or DImode values. */ \
2870 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
e75b25e7
MM		 2871 goto ADDR; \
2872 \
ce57d6f4 2873 if (CONSTANT_ADDRESS_P (xinsn) \
2bcb2ab3
GK		 2874 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2875 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
e75b25e7
MM		 2876 goto ADDR; \
2877 \
ce57d6f4
JW		 2878 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2879 { \
2880 register rtx xlow0 = XEXP (xinsn, 0); \
2881 register rtx xlow1 = XEXP (xinsn, 1); \
2882 \
51f0646f
JL		 2883 while (GET_CODE (xlow0) == SUBREG) \
2884 xlow0 = SUBREG_REG (xlow0); \
2bcb2ab3
GK		 2885 if (GET_CODE (xlow0) == REG \
2886 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
ce57d6f4
JW		 2887 && mips_check_split (xlow1, MODE)) \
2888 goto ADDR; \
2889 } \
2890 \
e75b25e7
MM		 2891 if (GET_CODE (xinsn) == PLUS) \
2892 { \
2893 register rtx xplus0 = XEXP (xinsn, 0); \
2894 register rtx xplus1 = XEXP (xinsn, 1); \
51f0646f
JL		 2895 register enum rtx_code code0; \
2896 register enum rtx_code code1; \
2897 \
2898 while (GET_CODE (xplus0) == SUBREG) \
2899 xplus0 = SUBREG_REG (xplus0); \
2900 code0 = GET_CODE (xplus0); \
2901 \
2902 while (GET_CODE (xplus1) == SUBREG) \
2903 xplus1 = SUBREG_REG (xplus1); \
2904 code1 = GET_CODE (xplus1); \
e75b25e7 2905 \
2bcb2ab3
GK		 2906 /* The mips16 can only use the stack pointer as a base register \
2907 when loading SImode or DImode values. */ \
2908 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
e75b25e7 2909 { \
876c09d3
JW		 2910 if (code1 == CONST_INT \
2911 && INTVAL (xplus1) >= -32768 \
2912 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2913 goto ADDR; \
e75b25e7 2914 \
2bcb2ab3
GK		 2915 /* On the mips16, we represent GP relative offsets in RTL. \
2916 These are 16 bit signed values, and can serve as register \
2917 offsets. */ \
2918 if (TARGET_MIPS16 \
2919 && mips16_gp_offset_p (xplus1)) \
2920 goto ADDR; \
2921 \
e75b25e7
MM		 2922 /* For some code sequences, you actually get better code by \
2923 pretending that the MIPS supports an address mode of a \
2924 constant address + a register, even though the real \
2925 machine doesn't support it. This is because the \
2926 assembler can use $r1 to load just the high 16 bits, add \
2927 in the register, and fold the low 16 bits into the memory \
31c714e3 2928 reference, whereas the compiler generates a 4 instruction \
e75b25e7
MM		 2929 sequence. On the other hand, CSE is not as effective. \
2930 It would be a win to generate the lui directly, but the \
2931 MIPS assembler does not have syntax to generate the \
2932 appropriate relocation. */ \
2933 \
5de1e2ce 2934 /* Also accept CONST_INT addresses here, so no else. */ \
92544bdf
ILT		 2935 /* Reject combining an embedded PIC text segment reference \
2936 with a register. That requires an additional \
2937 instruction. */ \
516a2dfd
JW		 2938 /* ??? Reject combining an address with a register for the MIPS \
2939 64 bit ABI, because the SGI assembler can not handle this. */ \
5de1e2ce 2940 if (!TARGET_DEBUG_A_MODE \
a53f72db
GRK		 2941 && (mips_abi == ABI_32 \
2942 || mips_abi == ABI_O64 \
2943 || mips_abi == ABI_EABI) \
92544bdf 2944 && CONSTANT_ADDRESS_P (xplus1) \
ce57d6f4 2945 && ! mips_split_addresses \
92544bdf
ILT		 2946 && (!TARGET_EMBEDDED_PIC \
2947 || code1 != CONST \
2bcb2ab3
GK		 2948 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2949 && !TARGET_MIPS16) \
e75b25e7
MM		 2950 goto ADDR; \
2951 } \
2952 } \
2953 \
2954 if (TARGET_DEBUG_B_MODE) \
2955 GO_PRINTF ("Not a legitimate address\n"); \
2956}
2957
2958
2959/* A C expression that is 1 if the RTX X is a constant which is a
6eff269e
BK		 2960 valid address. This is defined to be the same as `CONSTANT_P (X)',
2961 but rejecting CONST_DOUBLE. */
5de1e2ce
JW		 2962/* When pic, we must reject addresses of the form symbol+large int.
2963 This is because an instruction `sw $4,s+70000' needs to be converted
2964 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2965 assembler would use $at as a temp to load in the large offset. In this
2966 case $at is already in use. We convert such problem addresses to
2967 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
516a2dfd 2968/* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
31c714e3 2969#define CONSTANT_ADDRESS_P(X) \
6eff269e 2970 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
5de1e2ce
JW		 2971 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2972 || (GET_CODE (X) == CONST \
516a2dfd 2973 && ! (flag_pic && pic_address_needs_scratch (X)) \
a53f72db
GRK		 2974 && (mips_abi == ABI_32 \
2975 || mips_abi == ABI_O64 \
2976 || mips_abi == ABI_EABI))) \
5de1e2ce 2977 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
e75b25e7 2978
5de1e2ce
JW		 2979/* Define this, so that when PIC, reload won't try to reload invalid
2980 addresses which require two reload registers. */
2981
2982#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
e75b25e7
MM		 2983
2984/* Nonzero if the constant value X is a legitimate general operand.
2985 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2986
2987 At present, GAS doesn't understand li.[sd], so don't allow it
2988 to be generated at present. Also, the MIPS assembler does not
2989 grok li.d Infinity. */
2990
516a2dfd 2991/* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
e75b25e7 2992#define LEGITIMATE_CONSTANT_P(X) \
516a2dfd
JW		 2993 ((GET_CODE (X) != CONST_DOUBLE \
2994 || mips_const_double_ok (X, GET_MODE (X))) \
293a36eb 2995 && ! (GET_CODE (X) == CONST \
a53f72db
GRK		 2996 && mips_abi != ABI_32 \
2997 && mips_abi != ABI_O64 \
2998 && mips_abi != ABI_EABI) \
2bcb2ab3 2999 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
e75b25e7
MM		 3000
3001/* A C compound statement that attempts to replace X with a valid
3002 memory address for an operand of mode MODE. WIN will be a C
3003 statement label elsewhere in the code; the macro definition may
3004 use
3005
3006 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3007
3008 to avoid further processing if the address has become legitimate.
3009
3010 X will always be the result of a call to `break_out_memory_refs',
3011 and OLDX will be the operand that was given to that function to
3012 produce X.
3013
3014 The code generated by this macro should not alter the
3015 substructure of X. If it transforms X into a more legitimate
3016 form, it should assign X (which will always be a C variable) a
3017 new value.
3018
3019 It is not necessary for this macro to come up with a legitimate
3020 address. The compiler has standard ways of doing so in all
3021 cases. In fact, it is safe for this macro to do nothing. But
2649b2ee 3022 often a machine-dependent strategy can generate better code.
e75b25e7 3023
2649b2ee
MM		 3024 For the MIPS, transform:
3025
3026 memory(X + <large int>)
3027
3028 into:
3029
3030 Y = <large int> & ~0x7fff;
3031 Z = X + Y
3032 memory (Z + (<large int> & 0x7fff));
3033
5de1e2ce
JW		 3034 This is for CSE to find several similar references, and only use one Z.
3035
3036 When PIC, convert addresses of the form memory (symbol+large int) to
3037 memory (reg+large int). */
3038
2649b2ee
MM		 3039
3040#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3041{ \
3042 register rtx xinsn = (X); \
3043 \
3044 if (TARGET_DEBUG_B_MODE) \
3045 { \
3046 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3047 GO_DEBUG_RTX (xinsn); \
3048 } \
3049 \
ce57d6f4
JW		 3050 if (mips_split_addresses && mips_check_split (X, MODE)) \
3051 { \
3052 /* ??? Is this ever executed? */ \
c5c76735
JL		 3053 X = gen_rtx_LO_SUM (Pmode, \
3054 copy_to_mode_reg (Pmode, \
3055 gen_rtx (HIGH, Pmode, X)), \
3056 X); \
ce57d6f4
JW		 3057 goto WIN; \
3058 } \
3059 \
516a2dfd
JW		 3060 if (GET_CODE (xinsn) == CONST \
3061 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3062 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
a53f72db
GRK		 3063 || (mips_abi != ABI_32 \
3064 && mips_abi != ABI_O64 \
3065 && mips_abi != ABI_EABI))) \
516a2dfd
JW		 3066 { \
3067 rtx ptr_reg = gen_reg_rtx (Pmode); \
3068 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3069 \
3070 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3071 \
c5c76735 3072 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
516a2dfd
JW		 3073 if (SMALL_INT (constant)) \
3074 goto WIN; \
3075 /* Otherwise we fall through so the code below will fix the \
3076 constant. */ \
3077 xinsn = X; \
3078 } \
3079 \
b3de0f1f 3080 if (GET_CODE (xinsn) == PLUS) \
2649b2ee
MM		 3081 { \
3082 register rtx xplus0 = XEXP (xinsn, 0); \
3083 register rtx xplus1 = XEXP (xinsn, 1); \
3084 register enum rtx_code code0 = GET_CODE (xplus0); \
3085 register enum rtx_code code1 = GET_CODE (xplus1); \
3086 \
3087 if (code0 != REG && code1 == REG) \
3088 { \
3089 xplus0 = XEXP (xinsn, 1); \
3090 xplus1 = XEXP (xinsn, 0); \
3091 code0 = GET_CODE (xplus0); \
3092 code1 = GET_CODE (xplus1); \
3093 } \
3094 \
2bcb2ab3 3095 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2649b2ee
MM		 3096 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3097 { \
3098 rtx int_reg = gen_reg_rtx (Pmode); \
3099 rtx ptr_reg = gen_reg_rtx (Pmode); \
3100 \
3101 emit_move_insn (int_reg, \
3102 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3103 \
c5c76735
JL		 3104 emit_insn (gen_rtx_SET (VOIDmode, \
3105 ptr_reg, \
3106 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
2649b2ee 3107 \
c5c76735
JL		 3108 X = gen_rtx_PLUS (Pmode, ptr_reg, \
3109 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2649b2ee
MM		 3110 goto WIN; \
3111 } \
3112 } \
3113 \
3114 if (TARGET_DEBUG_B_MODE) \
3115 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3116}
e75b25e7
MM		 3117
3118
3119/* A C statement or compound statement with a conditional `goto
3120 LABEL;' executed if memory address X (an RTX) can have different
3121 meanings depending on the machine mode of the memory reference it
3122 is used for.
3123
3124 Autoincrement and autodecrement addresses typically have
3125 mode-dependent effects because the amount of the increment or
3126 decrement is the size of the operand being addressed. Some
3127 machines have other mode-dependent addresses. Many RISC machines
3128 have no mode-dependent addresses.
3129
3130 You may assume that ADDR is a valid address for the machine. */
3131
3132#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3133
3134
3135/* Define this macro if references to a symbol must be treated
3136 differently depending on something about the variable or
3137 function named by the symbol (such as what section it is in).
3138
3139 The macro definition, if any, is executed immediately after the
3140 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3141 The value of the rtl will be a `mem' whose address is a
3142 `symbol_ref'.
3143
3144 The usual thing for this macro to do is to a flag in the
3145 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3146 name string in the `symbol_ref' (if one bit is not enough
3147 information).
3148
3149 The best way to modify the name string is by adding text to the
3150 beginning, with suitable punctuation to prevent any ambiguity.
3151 Allocate the new name in `saveable_obstack'. You will have to
3152 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3153 and output the name accordingly.
3154
3155 You can also check the information stored in the `symbol_ref' in
3156 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2bcb2ab3
GK		 3157 `PRINT_OPERAND_ADDRESS'.
3158
3159 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3160 small objects.
3161
3162 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3163 symbols which are not in the .text section.
3164
3165 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3166 constants which are put in the .text section. We also record the
3167 total length of all such strings; this total is used to decide
3168 whether we need to split the constant table, and need not be
a9e3e611
GRK		 3169 precisely correct.
3170
3171 When not mips16 code nor embedded PIC, if a symbol is in a
3172 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3173 splitting the reference so that gas can generate a gp relative
3174 reference.
5f680ab6
DD		 3175
3176 When TARGET_EMBEDDED_DATA is set, we assume that all const
3177 variables will be stored in ROM, which is too far from %gp to use
3178 %gprel addressing. Note that (1) we include "extern const"
3179 variables in this, which mips_select_section doesn't, and (2) we
3180 can't always tell if they're really const (they might be const C++
3181 objects with non-const constructors), so we err on the side of
3182 caution and won't use %gprel anyway (otherwise we'd have to defer
3183 this decision to the linker/loader). The handling of extern consts
3184 is why the DECL_INITIAL macros differ from mips_select_section.
3185
3186 If you are changing this macro, you should look at
3187 mips_select_section and see if it needs a similar change. */
e75b25e7 3188
45e7144a
JW		 3189#ifndef UNIQUE_SECTION_P
3190#define UNIQUE_SECTION_P(DECL) (0)
3191#endif
3192
e75b25e7
MM		 3193#define ENCODE_SECTION_INFO(DECL) \
3194do \
3195 { \
2bcb2ab3
GK		 3196 if (TARGET_MIPS16) \
3197 { \
3198 if (TREE_CODE (DECL) == STRING_CST \
52ecdfda
JW		 3199 && ! flag_writable_strings \
3200 /* If this string is from a function, and the function will \
3201 go in a gnu linkonce section, then we can't directly \
3202 access the string. This gets an assembler error \
3203 "unsupported PC relative reference to different section".\
3204 If we modify SELECT_SECTION to put it in function_section\
3205 instead of text_section, it still fails because \
3206 DECL_SECTION_NAME isn't set until assemble_start_function.\
3207 If we fix that, it still fails because strings are shared\
3208 among multiple functions, and we have cross section \
3209 references again. We force it to work by putting string \
3210 addresses in the constant pool and indirecting. */ \
3211 && (! current_function_decl \
3212 || ! UNIQUE_SECTION_P (current_function_decl))) \
2bcb2ab3
GK		 3213 { \
3214 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3215 mips_string_length += TREE_STRING_LENGTH (DECL); \
3216 } \
3217 } \
5f680ab6
DD		 3218 \
3219 if (TARGET_EMBEDDED_DATA \
3220 && (TREE_CODE (DECL) == VAR_DECL \
3221 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3222 && (!DECL_INITIAL (DECL) \
3223 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3224 { \
3225 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3226 } \
3227 \
3228 else if (TARGET_EMBEDDED_PIC) \
92544bdf
ILT		 3229 { \
3230 if (TREE_CODE (DECL) == VAR_DECL) \
3231 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3232 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3233 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3234 else if (TREE_CODE (DECL) == STRING_CST \
3235 && ! flag_writable_strings) \
3236 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3237 else \
3238 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3239 } \
3240 \
a9e3e611
GRK		 3241 else if (TREE_CODE (DECL) == VAR_DECL \
3242 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3243 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3244 ".sdata") \
3245 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3246 ".sbss"))) \
3247 { \
3248 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3249 } \
3250 \
13b6b42c
JL		 3251 /* We can not perform GP optimizations on variables which are in \
3252 specific sections, except for .sdata and .sbss which are \
3253 handled above. */ \
3254 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3255 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
e75b25e7
MM		 3256 { \
3257 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3258 \
3259 if (size > 0 && size <= mips_section_threshold) \
3260 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3261 } \
3262 \
31c714e3 3263 else if (HALF_PIC_P ()) \
6e92f4b6
KG		 3264 { \
3265 HALF_PIC_ENCODE (DECL); \
3266 } \
e75b25e7
MM		 3267 } \
3268while (0)
3269
2bcb2ab3
GK		 3270/* The mips16 wants the constant pool to be after the function,
3271 because the PC relative load instructions use unsigned offsets. */
3272
3273#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3274
3275#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3276 mips_string_length = 0;
3277
3278#if 0
3279/* In mips16 mode, put most string constants after the function. */
3280#define CONSTANT_AFTER_FUNCTION_P(tree) \
3281 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3282#endif
e75b25e7
MM		 3283\f
3284/* Specify the machine mode that this machine uses
2bcb2ab3
GK		 3285 for the index in the tablejump instruction.
3286 ??? Using HImode in mips16 mode can cause overflow. However, the
3287 overflow is no more likely than the overflow in a branch
3288 instruction. Large functions can currently break in both ways. */
3289#define CASE_VECTOR_MODE \
1eeed24e 3290 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
2bcb2ab3
GK		 3291
3292/* Define as C expression which evaluates to nonzero if the tablejump
3293 instruction expects the table to contain offsets from the address of the
3294 table.
3295 Do not define this if the table should contain absolute addresses. */
3296#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
e75b25e7
MM		 3297
3298/* Specify the tree operation to be used to convert reals to integers. */
3299#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3300
3301/* This is the kind of divide that is easiest to do in the general case. */
3302#define EASY_DIV_EXPR TRUNC_DIV_EXPR
3303
3304/* Define this as 1 if `char' should by default be signed; else as 0. */
6639753e 3305#ifndef DEFAULT_SIGNED_CHAR
e75b25e7 3306#define DEFAULT_SIGNED_CHAR 1
6639753e 3307#endif
e75b25e7
MM		 3308
3309/* Max number of bytes we can move from memory to memory
3310 in one reasonably fast instruction. */
876c09d3
JW		 3311#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3312#define MAX_MOVE_MAX 8
e75b25e7
MM		 3313
3314/* Define this macro as a C expression which is nonzero if
3315 accessing less than a word of memory (i.e. a `char' or a
3316 `short') is no faster than accessing a word of memory, i.e., if
3317 such access require more than one instruction or if there is no
3318 difference in cost between byte and (aligned) word loads.
3319
3320 On RISC machines, it tends to generate better code to define
3321 this as 1, since it avoids making a QI or HI mode register. */
3322#define SLOW_BYTE_ACCESS 1
3323
3324/* We assume that the store-condition-codes instructions store 0 for false
3325 and some other value for true. This is the value stored for true. */
3326
3327#define STORE_FLAG_VALUE 1
3328
3329/* Define this if zero-extension is slow (more than one real instruction). */
3330#define SLOW_ZERO_EXTEND
3331
d969caf8
RK		 3332/* Define this to be nonzero if shift instructions ignore all but the low-order
3333 few bits. */
3334#define SHIFT_COUNT_TRUNCATED 1
e75b25e7
MM		 3335
3336/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3337 is done just by pretending it is already truncated. */
876c09d3
JW		 3338/* In 64 bit mode, 32 bit instructions require that register values be properly
3339 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3340 converts a value >32 bits to a value <32 bits. */
3341/* ??? This results in inefficient code for 64 bit to 32 conversions.
3342 Something needs to be done about this. Perhaps not use any 32 bit
3343 instructions? Perhaps use PROMOTE_MODE? */
3344#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3345 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
e75b25e7 3346
e75b25e7
MM		 3347/* Specify the machine mode that pointers have.
3348 After generation of rtl, the compiler makes no further distinction
fb1bf66d
GRK		 3349 between pointers and any other objects of this machine mode.
3350
3351 For MIPS we make pointers are the smaller of longs and gp-registers. */
876c09d3 3352
1eeed24e 3353#ifndef Pmode
8ca47902 3354#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
1eeed24e 3355#endif
e75b25e7
MM		 3356
3357/* A function address in a call instruction
3358 is a word address (for indexing purposes)
3359 so give the MEM rtx a words's mode. */
3360
1eeed24e 3361#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
e75b25e7
MM		 3362
3363/* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3364 memset, instead of the BSD functions bcopy and bzero. */
3365
3366#if defined(MIPS_SYSV) || defined(OSF_OS)
3367#define TARGET_MEM_FUNCTIONS
3368#endif
3369
3370\f
3371/* A part of a C `switch' statement that describes the relative
3372 costs of constant RTL expressions. It must contain `case'
3373 labels for expression codes `const_int', `const', `symbol_ref',
3374 `label_ref' and `const_double'. Each case must ultimately reach
3375 a `return' statement to return the relative cost of the use of
3376 that kind of constant value in an expression. The cost may
3377 depend on the precise value of the constant, which is available
3378 for examination in X.
3379
3380 CODE is the expression code--redundant, since it can be obtained
3381 with `GET_CODE (X)'. */
3382
def9623c 3383#define CONST_COSTS(X,CODE,OUTER_CODE) \
e75b25e7 3384 case CONST_INT: \
2bcb2ab3
GK		 3385 if (! TARGET_MIPS16) \
3386 { \
3387 /* Always return 0, since we don't have different sized \
3388 instructions, hence different costs according to Richard \
3389 Kenner */ \
3390 return 0; \
3391 } \
3392 if ((OUTER_CODE) == SET) \
3393 { \
3394 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3395 return 0; \
3396 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3397 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3398 return COSTS_N_INSNS (1); \
3399 else \
3400 return COSTS_N_INSNS (2); \
3401 } \
3402 /* A PLUS could be an address. We don't want to force an address \
3403 to use a register, so accept any signed 16 bit value without \
3404 complaint. */ \
3405 if ((OUTER_CODE) == PLUS \
3406 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3407 return 0; \
3408 /* A number between 1 and 8 inclusive is efficient for a shift. \
3409 Otherwise, we will need an extended instruction. */ \
3410 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3411 || (OUTER_CODE) == LSHIFTRT) \
3412 { \
3413 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3414 return 0; \
3415 return COSTS_N_INSNS (1); \
3416 } \
3417 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3418 if ((OUTER_CODE) == XOR \
3419 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3420 return 0; \
3421 /* We may be able to use slt or sltu for a comparison with a \
3422 signed 16 bit value. (The boundary conditions aren't quite \
3423 right, but this is just a heuristic anyhow.) */ \
3424 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3425 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3426 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3427 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3428 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3429 return 0; \
3430 /* Equality comparisons with 0 are cheap. */ \
3431 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3432 && INTVAL (X) == 0) \
3433 return 0; \
3434 \
3435 /* Otherwise, work out the cost to load the value into a \
3436 register. */ \
3437 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3438 return COSTS_N_INSNS (1); \
3439 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3440 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3441 return COSTS_N_INSNS (2); \
3442 else \
3443 return COSTS_N_INSNS (3); \
e75b25e7
MM		 3444 \
3445 case LABEL_REF: \
3446 return COSTS_N_INSNS (2); \
3447 \
3448 case CONST: \
3449 { \
31c714e3 3450 rtx offset = const0_rtx; \
876c09d3 3451 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
e75b25e7 3452 \
2bcb2ab3
GK		 3453 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3454 { \
3455 /* Treat this like a signed 16 bit CONST_INT. */ \
3456 if ((OUTER_CODE) == PLUS) \
3457 return 0; \
3458 else if ((OUTER_CODE) == SET) \
3459 return COSTS_N_INSNS (1); \
3460 else \
3461 return COSTS_N_INSNS (2); \
3462 } \
3463 \
e75b25e7
MM		 3464 if (GET_CODE (symref) == LABEL_REF) \
3465 return COSTS_N_INSNS (2); \
3466 \
3467 if (GET_CODE (symref) != SYMBOL_REF) \
3468 return COSTS_N_INSNS (4); \
3469 \
3470 /* let's be paranoid.... */ \
31c714e3 3471 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
e75b25e7
MM		 3472 return COSTS_N_INSNS (2); \
3473 \
3474 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3475 } \
3476 \
3477 case SYMBOL_REF: \
3478 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3479 \
3480 case CONST_DOUBLE: \
96abdcb1
ILT		 3481 { \
3482 rtx high, low; \
2bcb2ab3
GK		 3483 if (TARGET_MIPS16) \
3484 return COSTS_N_INSNS (4); \
96abdcb1
ILT		 3485 split_double (X, &high, &low); \
3486 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3487 || low == CONST0_RTX (GET_MODE (low))) \
3488 ? 2 : 4); \
3489 }
e75b25e7
MM		 3490
3491/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3492 This can be used, for example, to indicate how costly a multiply
3493 instruction is. In writing this macro, you can use the construct
3494 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3495
3496 This macro is optional; do not define it if the default cost
3497 assumptions are adequate for the target machine.
3498
3499 If -mdebugd is used, change the multiply cost to 2, so multiply by
3500 a constant isn't converted to a series of shifts. This helps
3501 strength reduction, and also makes it easier to identify what the
3502 compiler is doing. */
3503
516a2dfd 3504/* ??? Fix this to be right for the R8000. */
def9623c 3505#define RTX_COSTS(X,CODE,OUTER_CODE) \
e75b25e7
MM		 3506 case MEM: \
3507 { \
3508 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3509 if (simple_memory_operand (X, GET_MODE (X))) \
3510 return COSTS_N_INSNS (num_words); \
3511 \
3512 return COSTS_N_INSNS (2*num_words); \
3513 } \
3514 \
3515 case FFS: \
3516 return COSTS_N_INSNS (6); \
3517 \
3518 case NOT: \
876c09d3 3519 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
e75b25e7
MM		 3520 \
3521 case AND: \
3522 case IOR: \
3523 case XOR: \
876c09d3 3524 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
e75b25e7
MM		 3525 return COSTS_N_INSNS (2); \
3526 \
2bcb2ab3 3527 break; \
e75b25e7
MM		 3528 \
3529 case ASHIFT: \
3530 case ASHIFTRT: \
e75b25e7 3531 case LSHIFTRT: \
876c09d3
JW		 3532 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3533 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
e75b25e7 3534 \
2bcb2ab3 3535 break; \
e75b25e7
MM		 3536 \
3537 case ABS: \
3538 { \
3539 enum machine_mode xmode = GET_MODE (X); \
3540 if (xmode == SFmode || xmode == DFmode) \
3541 return COSTS_N_INSNS (1); \
3542 \
3543 return COSTS_N_INSNS (4); \
3544 } \
3545 \
3546 case PLUS: \
3547 case MINUS: \
3548 { \
3549 enum machine_mode xmode = GET_MODE (X); \
3550 if (xmode == SFmode || xmode == DFmode) \
9a863c83 3551 { \
e9a25f70
JL		 3552 if (mips_cpu == PROCESSOR_R3000 \
3553 || mips_cpu == PROCESSOR_R3900) \
9a863c83
JW		 3554 return COSTS_N_INSNS (2); \
3555 else if (mips_cpu == PROCESSOR_R6000) \
3556 return COSTS_N_INSNS (3); \
3557 else \
3558 return COSTS_N_INSNS (6); \
3559 } \
e75b25e7 3560 \
876c09d3 3561 if (xmode == DImode && !TARGET_64BIT) \
e75b25e7
MM		 3562 return COSTS_N_INSNS (4); \
3563 \
2bcb2ab3 3564 break; \
e75b25e7
MM		 3565 } \
3566 \
3567 case NEG: \
2bcb2ab3
GK		 3568 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3569 return 4; \
3570 \
3571 break; \
e75b25e7
MM		 3572 \
3573 case MULT: \
3574 { \
3575 enum machine_mode xmode = GET_MODE (X); \
3576 if (xmode == SFmode) \
9a863c83 3577 { \
b8eb88d0 3578 if (mips_cpu == PROCESSOR_R3000 \
e9a25f70 3579 || mips_cpu == PROCESSOR_R3900 \
b8eb88d0 3580 || mips_cpu == PROCESSOR_R5000) \
9a863c83
JW		 3581 return COSTS_N_INSNS (4); \
3582 else if (mips_cpu == PROCESSOR_R6000) \
3583 return COSTS_N_INSNS (5); \
3584 else \
3585 return COSTS_N_INSNS (7); \
3586 } \
e75b25e7
MM		 3587 \
3588 if (xmode == DFmode) \
9a863c83 3589 { \
b8eb88d0 3590 if (mips_cpu == PROCESSOR_R3000 \
e9a25f70 3591 || mips_cpu == PROCESSOR_R3900 \
b8eb88d0 3592 || mips_cpu == PROCESSOR_R5000) \
9a863c83
JW		 3593 return COSTS_N_INSNS (5); \
3594 else if (mips_cpu == PROCESSOR_R6000) \
3595 return COSTS_N_INSNS (6); \
3596 else \
3597 return COSTS_N_INSNS (8); \
3598 } \
e75b25e7 3599 \
9a863c83
JW		 3600 if (mips_cpu == PROCESSOR_R3000) \
3601 return COSTS_N_INSNS (12); \
e9a25f70
JL		 3602 else if (mips_cpu == PROCESSOR_R3900) \
3603 return COSTS_N_INSNS (2); \
9a863c83
JW		 3604 else if (mips_cpu == PROCESSOR_R6000) \
3605 return COSTS_N_INSNS (17); \
b8eb88d0
ILT		 3606 else if (mips_cpu == PROCESSOR_R5000) \
3607 return COSTS_N_INSNS (5); \
9a863c83
JW		 3608 else \
3609 return COSTS_N_INSNS (10); \
e75b25e7
MM		 3610 } \
3611 \
3612 case DIV: \
3613 case MOD: \
3614 { \
3615 enum machine_mode xmode = GET_MODE (X); \
3616 if (xmode == SFmode) \
9a863c83 3617 { \
e9a25f70
JL		 3618 if (mips_cpu == PROCESSOR_R3000 \
3619 || mips_cpu == PROCESSOR_R3900) \
9a863c83
JW		 3620 return COSTS_N_INSNS (12); \
3621 else if (mips_cpu == PROCESSOR_R6000) \
3622 return COSTS_N_INSNS (15); \
3623 else \
3624 return COSTS_N_INSNS (23); \
3625 } \
e75b25e7
MM		 3626 \
3627 if (xmode == DFmode) \
9a863c83 3628 { \
e9a25f70
JL		 3629 if (mips_cpu == PROCESSOR_R3000 \
3630 || mips_cpu == PROCESSOR_R3900) \
9a863c83
JW		 3631 return COSTS_N_INSNS (19); \
3632 else if (mips_cpu == PROCESSOR_R6000) \
3633 return COSTS_N_INSNS (16); \
3634 else \
3635 return COSTS_N_INSNS (36); \
3636 } \
e75b25e7
MM		 3637 } \
3638 /* fall through */ \
3639 \
3640 case UDIV: \
3641 case UMOD: \
e9a25f70
JL		 3642 if (mips_cpu == PROCESSOR_R3000 \
3643 || mips_cpu == PROCESSOR_R3900) \
9a863c83
JW		 3644 return COSTS_N_INSNS (35); \
3645 else if (mips_cpu == PROCESSOR_R6000) \
3646 return COSTS_N_INSNS (38); \
b8eb88d0
ILT		 3647 else if (mips_cpu == PROCESSOR_R5000) \
3648 return COSTS_N_INSNS (36); \
9a863c83 3649 else \
1a4fa807
ILT		 3650 return COSTS_N_INSNS (69); \
3651 \
3652 case SIGN_EXTEND: \
3653 /* A sign extend from SImode to DImode in 64 bit mode is often \
3654 zero instructions, because the result can often be used \
3655 directly by another instruction; we'll call it one. */ \
3656 if (TARGET_64BIT && GET_MODE (X) == DImode \
3657 && GET_MODE (XEXP (X, 0)) == SImode) \
3658 return COSTS_N_INSNS (1); \
3659 else \
3660 return COSTS_N_INSNS (2); \
3661 \
3662 case ZERO_EXTEND: \
3663 if (TARGET_64BIT && GET_MODE (X) == DImode \
3664 && GET_MODE (XEXP (X, 0)) == SImode) \
3665 return COSTS_N_INSNS (2); \
3666 else \
3667 return COSTS_N_INSNS (1);
e75b25e7
MM		 3668
3669/* An expression giving the cost of an addressing mode that
3670 contains ADDRESS. If not defined, the cost is computed from the
3671 form of the ADDRESS expression and the `CONST_COSTS' values.
3672
3673 For most CISC machines, the default cost is a good approximation
3674 of the true cost of the addressing mode. However, on RISC
3675 machines, all instructions normally have the same length and
3676 execution time. Hence all addresses will have equal costs.
3677
3678 In cases where more than one form of an address is known, the
3679 form with the lowest cost will be used. If multiple forms have
3680 the same, lowest, cost, the one that is the most complex will be
3681 used.
3682
3683 For example, suppose an address that is equal to the sum of a
3684 register and a constant is used twice in the same basic block.
3685 When this macro is not defined, the address will be computed in
3686 a register and memory references will be indirect through that
3687 register. On machines where the cost of the addressing mode
3688 containing the sum is no higher than that of a simple indirect
3689 reference, this will produce an additional instruction and
3690 possibly require an additional register. Proper specification
3691 of this macro eliminates this overhead for such machines.
3692
3693 Similar use of this macro is made in strength reduction of loops.
3694
3695 ADDRESS need not be valid as an address. In such a case, the
3696 cost is not relevant and can be any value; invalid addresses
3697 need not be assigned a different cost.
3698
3699 On machines where an address involving more than one register is
3700 as cheap as an address computation involving only one register,
3701 defining `ADDRESS_COST' to reflect this can cause two registers
3702 to be live over a region of code where only one would have been
3703 if `ADDRESS_COST' were not defined in that manner. This effect
3704 should be considered in the definition of this macro.
3705 Equivalent costs should probably only be given to addresses with
3706 different numbers of registers on machines with lots of registers.
3707
3708 This macro will normally either not be defined or be defined as
3709 a constant. */
3710
3711#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3712
3713/* A C expression for the cost of moving data from a register in
3714 class FROM to one in class TO. The classes are expressed using
3715 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3716 the default; other values are interpreted relative to that.
3717
3718 It is not required that the cost always equal 2 when FROM is the
3719 same as TO; on some machines it is expensive to move between
3720 registers if they are not general registers.
3721
3722 If reload sees an insn consisting of a single `set' between two
3723 hard registers, and if `REGISTER_MOVE_COST' applied to their
3724 classes returns a value of 2, reload does not check to ensure
3725 that the constraints of the insn are met. Setting a cost of
3726 other than 2 will allow reload to verify that the constraints are
3727 met. You should do this if the `movM' pattern's constraints do
56dc4d15
JW		 3728 not allow such copying.
3729
3730 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3731 registers the same as for one of moving general registers to
3732 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3733 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3734 isn't clear if it is wise. And it might not work in all cases. We
3735 could solve the DImode LO reg problem by using a multiply, just like
3736 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3737 by using divide instructions. divu puts the remainder in the HI
3738 reg, so doing a divide by -1 will move the value in the HI reg for
3739 all values except -1. We could handle that case by using a signed
3740 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3741 compare/branch to test the input value to see which instruction we
3742 need to use. This gets pretty messy, but it is feasible. */
e75b25e7 3743
9a863c83 3744#define REGISTER_MOVE_COST(FROM, TO) \
2bcb2ab3
GK		 3745 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3746 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3747 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3748 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3749 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
9a863c83 3750 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
2bcb2ab3
GK		 3751 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3752 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3753 : (((FROM) == HI_REG || (FROM) == LO_REG \
3754 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3755 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
225b8835
ILT		 3756 : (((FROM) == HI_REG || (FROM) == LO_REG \
3757 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
56dc4d15 3758 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
225b8835 3759 : (((TO) == HI_REG || (TO) == LO_REG \
2bcb2ab3
GK		 3760 || (TO) == MD_REGS || (TO) == HILO_REG) \
3761 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3762 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
b8eb88d0 3763 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
46299de9 3764 : 12)
e75b25e7 3765
516a2dfd 3766/* ??? Fix this to be right for the R8000. */
cbd5b9a2
KR		 3767#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3768 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3769 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
876c09d3 3770
7506f491
DE		 3771/* Define if copies to/from condition code registers should be avoided.
3772
3773 This is needed for the MIPS because reload_outcc is not complete;
3774 it needs to handle cases where the source is a general or another
3775 condition code register. */
3776#define AVOID_CCMODE_COPIES
3777
e75b25e7
MM		 3778/* A C expression for the cost of a branch instruction. A value of
3779 1 is the default; other values are interpreted relative to that. */
3780
516a2dfd 3781/* ??? Fix this to be right for the R8000. */
2bcb2ab3
GK		 3782#define BRANCH_COST \
3783 ((! TARGET_MIPS16 \
3784 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3785 ? 2 : 1)
e75b25e7 3786
9a863c83
JW		 3787/* A C statement (sans semicolon) to update the integer variable COST
3788 based on the relationship between INSN that is dependent on
3789 DEP_INSN through the dependence LINK. The default is to make no
3790 adjustment to COST. On the MIPS, ignore the cost of anti- and
3791 output-dependencies. */
e75b25e7 3792
9a863c83
JW		 3793#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3794 if (REG_NOTE_KIND (LINK) != 0) \
3795 (COST) = 0; /* Anti or output dependence. */
0ff83799
MM		 3796
3797/* If defined, modifies the length assigned to instruction INSN as a
3798 function of the context in which it is used. LENGTH is an lvalue
3799 that contains the initially computed length of the insn and should
3800 be updated with the correct length of the insn. */
3801#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3802 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3803
e75b25e7
MM		 3804\f
3805/* Optionally define this if you have added predicates to
3806 `MACHINE.c'. This macro is called within an initializer of an
3807 array of structures. The first field in the structure is the
31c714e3 3808 name of a predicate and the second field is an array of rtl
e75b25e7
MM		 3809 codes. For each predicate, list all rtl codes that can be in
3810 expressions matched by the predicate. The list should have a
3811 trailing comma. Here is an example of two entries in the list
3812 for a typical RISC machine:
3813
3814 #define PREDICATE_CODES \
3815 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3816 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3817
3818 Defining this macro does not affect the generated code (however,
3819 incorrect definitions that omit an rtl code that may be matched
3820 by the predicate can cause the compiler to malfunction).
3821 Instead, it allows the table built by `genrecog' to be more
3822 compact and efficient, thus speeding up the compiler. The most
3823 important predicates to include in the list specified by this
3824 macro are thoses used in the most insn patterns. */
3825
3826#define PREDICATE_CODES \
3827 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3828 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3829 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
def72bd2
GRK		 3830 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3831 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
e75b25e7
MM		 3832 {"small_int", { CONST_INT }}, \
3833 {"large_int", { CONST_INT }}, \
e75b25e7 3834 {"mips_const_double_ok", { CONST_DOUBLE }}, \
b8eb88d0 3835 {"const_float_1_operand", { CONST_DOUBLE }}, \
e75b25e7 3836 {"simple_memory_operand", { MEM, SUBREG }}, \
e75b25e7
MM		 3837 {"equality_op", { EQ, NE }}, \
3838 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3839 LTU, LEU }}, \
f8634644 3840 {"pc_or_label_operand", { PC, LABEL_REF }}, \
ce57d6f4
JW		 3841 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3842 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3843 SYMBOL_REF, LABEL_REF, SUBREG, \
3844 REG, MEM}}, \
1908a152
ILT		 3845 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3846 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3847 MEM, SIGN_EXTEND }}, \
3848 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
def72bd2 3849 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
1908a152
ILT		 3850 SIGN_EXTEND }}, \
3851 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3852 SIGN_EXTEND }}, \
3853 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3854 SIGN_EXTEND }}, \
3855 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3856 SYMBOL_REF, LABEL_REF, SUBREG, \
3857 REG, SIGN_EXTEND }}, \
2bcb2ab3
GK		 3858 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3859 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
cb923660
KR		 3860 CONST_DOUBLE, CONST }}, \
3861 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3862 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3863
e75b25e7
MM		 3864
3865\f
3866/* If defined, a C statement to be executed just prior to the
3867 output of assembler code for INSN, to modify the extracted
3868 operands so they will be output differently.
3869
3870 Here the argument OPVEC is the vector containing the operands
3871 extracted from INSN, and NOPERANDS is the number of elements of
3872 the vector which contain meaningful data for this insn. The
3873 contents of this vector are what will be used to convert the
3874 insn template into assembler code, so you can change the
3875 assembler output by changing the contents of the vector.
3876
3877 We use it to check if the current insn needs a nop in front of it
3878 because of load delays, and also to update the delay slot
3879 statistics. */
3880
3881#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
65437fe8 3882 final_prescan_insn (INSN, OPVEC, NOPERANDS)
e75b25e7 3883
e75b25e7
MM		 3884\f
3885/* Control the assembler format that we output. */
3886
3887/* Output at beginning of assembler file.
3888 If we are optimizing to use the global pointer, create a temporary
3889 file to hold all of the text stuff, and write it out to the end.
3890 This is needed because the MIPS assembler is evidently one pass,
3891 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3892 declaration when the code is processed, it generates a two
3893 instruction sequence. */
3894
3895#define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3896
3897/* Output to assembler file text saying following lines
3898 may contain character constants, extra white space, comments, etc. */
3899
3900#define ASM_APP_ON " #APP\n"
3901
3902/* Output to assembler file text saying following lines
3903 no longer contain unusual constructs. */
3904
3905#define ASM_APP_OFF " #NO_APP\n"
3906
3907/* How to refer to registers in assembler output.
3908 This sequence is indexed by compiler's hard-register-number (see above).
3909
3910 In order to support the two different conventions for register names,
3911 we use the name of a table set up in mips.c, which is overwritten
3912 if -mrnames is used. */
3913
3914#define REGISTER_NAMES \
3915{ \
3916 &mips_reg_names[ 0][0], \
3917 &mips_reg_names[ 1][0], \
3918 &mips_reg_names[ 2][0], \
3919 &mips_reg_names[ 3][0], \
3920 &mips_reg_names[ 4][0], \
3921 &mips_reg_names[ 5][0], \
3922 &mips_reg_names[ 6][0], \
3923 &mips_reg_names[ 7][0], \
3924 &mips_reg_names[ 8][0], \
3925 &mips_reg_names[ 9][0], \
3926 &mips_reg_names[10][0], \
3927 &mips_reg_names[11][0], \
3928 &mips_reg_names[12][0], \
3929 &mips_reg_names[13][0], \
3930 &mips_reg_names[14][0], \
3931 &mips_reg_names[15][0], \
3932 &mips_reg_names[16][0], \
3933 &mips_reg_names[17][0], \
3934 &mips_reg_names[18][0], \
3935 &mips_reg_names[19][0], \
3936 &mips_reg_names[20][0], \
3937 &mips_reg_names[21][0], \
3938 &mips_reg_names[22][0], \
3939 &mips_reg_names[23][0], \
3940 &mips_reg_names[24][0], \
3941 &mips_reg_names[25][0], \
3942 &mips_reg_names[26][0], \
3943 &mips_reg_names[27][0], \
3944 &mips_reg_names[28][0], \
3945 &mips_reg_names[29][0], \
3946 &mips_reg_names[30][0], \
3947 &mips_reg_names[31][0], \
3948 &mips_reg_names[32][0], \
3949 &mips_reg_names[33][0], \
3950 &mips_reg_names[34][0], \
3951 &mips_reg_names[35][0], \
3952 &mips_reg_names[36][0], \
3953 &mips_reg_names[37][0], \
3954 &mips_reg_names[38][0], \
3955 &mips_reg_names[39][0], \
3956 &mips_reg_names[40][0], \
3957 &mips_reg_names[41][0], \
3958 &mips_reg_names[42][0], \
3959 &mips_reg_names[43][0], \
3960 &mips_reg_names[44][0], \
3961 &mips_reg_names[45][0], \
3962 &mips_reg_names[46][0], \
3963 &mips_reg_names[47][0], \
3964 &mips_reg_names[48][0], \
3965 &mips_reg_names[49][0], \
3966 &mips_reg_names[50][0], \
3967 &mips_reg_names[51][0], \
3968 &mips_reg_names[52][0], \
3969 &mips_reg_names[53][0], \
3970 &mips_reg_names[54][0], \
3971 &mips_reg_names[55][0], \
3972 &mips_reg_names[56][0], \
3973 &mips_reg_names[57][0], \
3974 &mips_reg_names[58][0], \
3975 &mips_reg_names[59][0], \
3976 &mips_reg_names[60][0], \
3977 &mips_reg_names[61][0], \
3978 &mips_reg_names[62][0], \
3979 &mips_reg_names[63][0], \
3980 &mips_reg_names[64][0], \
3981 &mips_reg_names[65][0], \
3982 &mips_reg_names[66][0], \
225b8835 3983 &mips_reg_names[67][0], \
39dffea3 3984 &mips_reg_names[68][0], \
b8eb88d0
ILT		 3985 &mips_reg_names[69][0], \
3986 &mips_reg_names[70][0], \
3987 &mips_reg_names[71][0], \
3988 &mips_reg_names[72][0], \
3989 &mips_reg_names[73][0], \
3990 &mips_reg_names[74][0], \
3991 &mips_reg_names[75][0], \
e75b25e7
MM		 3992}
3993
46cca58c
RS		 3994/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3995 So define this for it. */
3996#define DEBUG_REGISTER_NAMES \
3997{ \
3998 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3999 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4000 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4001 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4002 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4003 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4004 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4005 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
b8eb88d0
ILT		 4006 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4007 "$fcc5","$fcc6","$fcc7","$rap" \
46cca58c
RS		 4008}
4009
e75b25e7
MM		 4010/* If defined, a C initializer for an array of structures
4011 containing a name and a register number. This macro defines
4012 additional names for hard registers, thus allowing the `asm'
4013 option in declarations to refer to registers using alternate
4014 names.
4015
4016 We define both names for the integer registers here. */
4017
4018#define ADDITIONAL_REGISTER_NAMES \
4019{ \
4020 { "$0", 0 + GP_REG_FIRST }, \
4021 { "$1", 1 + GP_REG_FIRST }, \
4022 { "$2", 2 + GP_REG_FIRST }, \
4023 { "$3", 3 + GP_REG_FIRST }, \
4024 { "$4", 4 + GP_REG_FIRST }, \
4025 { "$5", 5 + GP_REG_FIRST }, \
4026 { "$6", 6 + GP_REG_FIRST }, \
4027 { "$7", 7 + GP_REG_FIRST }, \
4028 { "$8", 8 + GP_REG_FIRST }, \
4029 { "$9", 9 + GP_REG_FIRST }, \
4030 { "$10", 10 + GP_REG_FIRST }, \
4031 { "$11", 11 + GP_REG_FIRST }, \
4032 { "$12", 12 + GP_REG_FIRST }, \
4033 { "$13", 13 + GP_REG_FIRST }, \
4034 { "$14", 14 + GP_REG_FIRST }, \
4035 { "$15", 15 + GP_REG_FIRST }, \
4036 { "$16", 16 + GP_REG_FIRST }, \
4037 { "$17", 17 + GP_REG_FIRST }, \
4038 { "$18", 18 + GP_REG_FIRST }, \
4039 { "$19", 19 + GP_REG_FIRST }, \
4040 { "$20", 20 + GP_REG_FIRST }, \
4041 { "$21", 21 + GP_REG_FIRST }, \
4042 { "$22", 22 + GP_REG_FIRST }, \
4043 { "$23", 23 + GP_REG_FIRST }, \
4044 { "$24", 24 + GP_REG_FIRST }, \
4045 { "$25", 25 + GP_REG_FIRST }, \
4046 { "$26", 26 + GP_REG_FIRST }, \
4047 { "$27", 27 + GP_REG_FIRST }, \
4048 { "$28", 28 + GP_REG_FIRST }, \
4049 { "$29", 29 + GP_REG_FIRST }, \
4050 { "$30", 30 + GP_REG_FIRST }, \
4051 { "$31", 31 + GP_REG_FIRST }, \
4052 { "$sp", 29 + GP_REG_FIRST }, \
4053 { "$fp", 30 + GP_REG_FIRST }, \
4054 { "at", 1 + GP_REG_FIRST }, \
4055 { "v0", 2 + GP_REG_FIRST }, \
4056 { "v1", 3 + GP_REG_FIRST }, \
4057 { "a0", 4 + GP_REG_FIRST }, \
4058 { "a1", 5 + GP_REG_FIRST }, \
4059 { "a2", 6 + GP_REG_FIRST }, \
4060 { "a3", 7 + GP_REG_FIRST }, \
4061 { "t0", 8 + GP_REG_FIRST }, \
4062 { "t1", 9 + GP_REG_FIRST }, \
4063 { "t2", 10 + GP_REG_FIRST }, \
4064 { "t3", 11 + GP_REG_FIRST }, \
4065 { "t4", 12 + GP_REG_FIRST }, \
4066 { "t5", 13 + GP_REG_FIRST }, \
4067 { "t6", 14 + GP_REG_FIRST }, \
4068 { "t7", 15 + GP_REG_FIRST }, \
4069 { "s0", 16 + GP_REG_FIRST }, \
4070 { "s1", 17 + GP_REG_FIRST }, \
4071 { "s2", 18 + GP_REG_FIRST }, \
4072 { "s3", 19 + GP_REG_FIRST }, \
4073 { "s4", 20 + GP_REG_FIRST }, \
4074 { "s5", 21 + GP_REG_FIRST }, \
4075 { "s6", 22 + GP_REG_FIRST }, \
4076 { "s7", 23 + GP_REG_FIRST }, \
4077 { "t8", 24 + GP_REG_FIRST }, \
4078 { "t9", 25 + GP_REG_FIRST }, \
4079 { "k0", 26 + GP_REG_FIRST }, \
4080 { "k1", 27 + GP_REG_FIRST }, \
4081 { "gp", 28 + GP_REG_FIRST }, \
4082 { "sp", 29 + GP_REG_FIRST }, \
4083 { "fp", 30 + GP_REG_FIRST }, \
4084 { "ra", 31 + GP_REG_FIRST }, \
924706a0 4085 { "$sp", 29 + GP_REG_FIRST }, \
b8eb88d0 4086 { "$fp", 30 + GP_REG_FIRST } \
e75b25e7
MM		 4087}
4088
4089/* Define results of standard character escape sequences. */
4090#define TARGET_BELL 007
4091#define TARGET_BS 010
4092#define TARGET_TAB 011
4093#define TARGET_NEWLINE 012
4094#define TARGET_VT 013
4095#define TARGET_FF 014
4096#define TARGET_CR 015
4097
4098/* A C compound statement to output to stdio stream STREAM the
4099 assembler syntax for an instruction operand X. X is an RTL
4100 expression.
4101
4102 CODE is a value that can be used to specify one of several ways
4103 of printing the operand. It is used when identical operands
4104 must be printed differently depending on the context. CODE
4105 comes from the `%' specification that was used to request
4106 printing of the operand. If the specification was just `%DIGIT'
4107 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4108 is the ASCII code for LTR.
4109
4110 If X is a register, this macro should print the register's name.
4111 The names can be found in an array `reg_names' whose type is
4112 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4113
4114 When the machine description has a specification `%PUNCT' (a `%'
4115 followed by a punctuation character), this macro is called with
4116 a null pointer for X and the punctuation character for CODE.
4117
4118 See mips.c for the MIPS specific codes. */
4119
4120#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4121
4122/* A C expression which evaluates to true if CODE is a valid
4123 punctuation character for use in the `PRINT_OPERAND' macro. If
4124 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4125 punctuation characters (except for the standard one, `%') are
4126 used in this way. */
4127
4128#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4129
4130/* A C compound statement to output to stdio stream STREAM the
4131 assembler syntax for an instruction operand that is a memory
4132 reference whose address is ADDR. ADDR is an RTL expression.
4133
4134 On some machines, the syntax for a symbolic address depends on
4135 the section that the address refers to. On these machines,
4136 define the macro `ENCODE_SECTION_INFO' to store the information
4137 into the `symbol_ref', and then check for it here. */
4138
4139#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4140
4141
4142/* A C statement, to be executed after all slot-filler instructions
4143 have been output. If necessary, call `dbr_sequence_length' to
4144 determine the number of slots filled in a sequence (zero if not
4145 currently outputting a sequence), to decide how many no-ops to
4146 output, or whatever.
4147
4148 Don't define this macro if it has nothing to do, but it is
4149 helpful in reading assembly output if the extent of the delay
4150 sequence is made explicit (e.g. with white space).
4151
4152 Note that output routines for instructions with delay slots must
4153 be prepared to deal with not being output as part of a sequence
4154 (i.e. when the scheduling pass is not run, or when no slot
4155 fillers could be found.) The variable `final_sequence' is null
4156 when not processing a sequence, otherwise it contains the
4157 `sequence' rtx being output. */
4158
4159#define DBR_OUTPUT_SEQEND(STREAM) \
4160do \
4161 { \
4162 if (set_nomacro > 0 && --set_nomacro == 0) \
4163 fputs ("\t.set\tmacro\n", STREAM); \
4164 \
4165 if (set_noreorder > 0 && --set_noreorder == 0) \
4166 fputs ("\t.set\treorder\n", STREAM); \
4167 \
4168 dslots_jump_filled++; \
4169 fputs ("\n", STREAM); \
4170 } \
4171while (0)
4172
4173
4174/* How to tell the debugger about changes of source files. Note, the
4175 mips ECOFF format cannot deal with changes of files inside of
4176 functions, which means the output of parser generators like bison
4177 is generally not debuggable without using the -l switch. Lose,
4178 lose, lose. Silicon graphics seems to want all .file's hardwired
4179 to 1. */
4180
4181#ifndef SET_FILE_NUMBER
4182#define SET_FILE_NUMBER() ++num_source_filenames
4183#endif
4184
4185#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4186 mips_output_filename (STREAM, NAME)
4187
ddd5a7c1 4188/* This is defined so that it can be overridden in iris6.h. */
516a2dfd
JW		 4189#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4190do \
4191 { \
4192 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4193 output_quoted_string (STREAM, NAME); \
4194 fputs ("\n", STREAM); \
4195 } \
4196while (0)
4197
e75b25e7
MM		 4198/* This is how to output a note the debugger telling it the line number
4199 to which the following sequence of instructions corresponds.
4200 Silicon graphics puts a label after each .loc. */
4201
4202#ifndef LABEL_AFTER_LOC
4203#define LABEL_AFTER_LOC(STREAM)
4204#endif
4205
4206#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4207 mips_output_lineno (STREAM, LINE)
4208
9ec36da5 4209/* The MIPS implementation uses some labels for its own purpose. The
e75b25e7
MM		 4210 following lists what labels are created, and are all formed by the
4211 pattern $L[a-z].*. The machine independent portion of GCC creates
4212 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4213
c5b7917e 4214 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
e75b25e7
MM		 4215 $Lb[0-9]+ Begin blocks for MIPS debug support
4216 $Lc[0-9]+ Label for use in s<xx> operation.
4217 $Le[0-9]+ End blocks for MIPS debug support
ab78d4a8 4218 $Lp\..+ Half-pic labels. */
e75b25e7
MM		 4219
4220/* This is how to output the definition of a user-level label named NAME,
4221 such as the label on a static function or variable NAME.
4222
4223 If we are optimizing the gp, remember that this label has been put
4224 out, so we know not to emit an .extern for it in mips_asm_file_end.
4225 We use one of the common bits in the IDENTIFIER tree node for this,
4226 since those bits seem to be unused, and we don't have any method
4227 of getting the decl nodes from the name. */
4228
e75b25e7
MM		 4229#define ASM_OUTPUT_LABEL(STREAM,NAME) \
4230do { \
4231 assemble_name (STREAM, NAME); \
4232 fputs (":\n", STREAM); \
e75b25e7
MM		 4233} while (0)
4234
31c714e3
MM		 4235
4236/* A C statement (sans semicolon) to output to the stdio stream
4237 STREAM any text necessary for declaring the name NAME of an
4238 initialized variable which is being defined. This macro must
4239 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4240 The argument DECL is the `VAR_DECL' tree node representing the
4241 variable.
4242
4243 If this macro is not defined, then the variable name is defined
4244 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4245
4246#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
f3b39eba
MM		 4247do \
4248 { \
4249 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4250 HALF_PIC_DECLARE (NAME); \
4251 } \
4252while (0)
31c714e3 4253
e75b25e7
MM		 4254
4255/* This is how to output a command to make the user-level label named NAME
4256 defined for reference from other files. */
4257
e75b25e7
MM		 4258#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4259 do { \
4260 fputs ("\t.globl\t", STREAM); \
4261 assemble_name (STREAM, NAME); \
4262 fputs ("\n", STREAM); \
4263 } while (0)
4264
31c714e3 4265/* This says how to define a global common symbol. */
e75b25e7
MM		 4266
4267#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
69520b54 4268 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
e75b25e7 4269
c5b7917e 4270/* This says how to define a local common symbol (ie, not visible to
31c714e3 4271 linker). */
e75b25e7
MM		 4272
4273#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
69520b54 4274 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
e75b25e7
MM		 4275
4276
4277/* This says how to output an external. It would be possible not to
4278 output anything and let undefined symbol become external. However
4279 the assembler uses length information on externals to allocate in
4280 data/sdata bss/sbss, thereby saving exec time. */
4281
4282#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4283 mips_output_external(STREAM,DECL,NAME)
4284
4285/* This says what to print at the end of the assembly file */
4286#define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4287
4288
4289/* This is how to declare a function name. The actual work of
4290 emitting the label is moved to function_prologue, so that we can
4291 get the line number correctly emitted before the .ent directive,
4292 and after any .file directives.
4293
4294 Also, switch files if we are optimizing the global pointer. */
4295
4296#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4297{ \
4298 extern FILE *asm_out_text_file; \
2bcb2ab3 4299 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
92d89408
DE		 4300 { \
4301 STREAM = asm_out_text_file; \
4302 /* ??? text_section gets called too soon. If the previous \
4303 function is in a special section and we're not, we have \
4304 to switch back to the text section. We can't call \
4305 text_section again as gcc thinks we're already there. */ \
4306 /* ??? See varasm.c. There are other things that get output \
4307 too early, like alignment (before we've switched STREAM). */ \
4308 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4309 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4310 } \
e75b25e7 4311 \
f3b39eba 4312 HALF_PIC_DECLARE (NAME); \
e75b25e7
MM		 4313}
4314
e75b25e7
MM		 4315/* This is how to output an internal numbered label where
4316 PREFIX is the class of label and NUM is the number within the class. */
4317
4318#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
6ae1498b 4319 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
e75b25e7
MM		 4320
4321/* This is how to store into the string LABEL
4322 the symbol_ref name of an internal numbered label where
4323 PREFIX is the class of label and NUM is the number within the class.
4324 This is suitable for output with `assemble_name'. */
4325
4326#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4f70758f 4327 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
e75b25e7
MM		 4328
4329/* This is how to output an assembler line defining a `double' constant. */
4330
4331#define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
dbe9742d
MM		 4332 mips_output_double (STREAM, VALUE)
4333
e75b25e7
MM		 4334
4335/* This is how to output an assembler line defining a `float' constant. */
4336
4337#define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
dbe9742d
MM		 4338 mips_output_float (STREAM, VALUE)
4339
e75b25e7
MM		 4340
4341/* This is how to output an assembler line defining an `int' constant. */
4342
e75b25e7
MM		 4343#define ASM_OUTPUT_INT(STREAM,VALUE) \
4344do { \
4345 fprintf (STREAM, "\t.word\t"); \
4346 output_addr_const (STREAM, (VALUE)); \
4347 fprintf (STREAM, "\n"); \
4348} while (0)
4349
d89ccde6
GRK		 4350/* Likewise for 64 bit, `char' and `short' constants.
4351
4352 FIXME: operand_subword can't handle some complex constant expressions
4353 that output_addr_const can (for example it does not call
4354 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4355 rely on that to avoid operand_subword for most of the cases where this
4356 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4357 or the same case with the type of 'i' changed to long long.
4358
4359*/
876c09d3
JW		 4360
4361#define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4362do { \
d89ccde6 4363 if (TARGET_64BIT || TARGET_GAS) \
876c09d3
JW		 4364 { \
4365 fprintf (STREAM, "\t.dword\t"); \
a88d48a4
JW		 4366 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4367 /* We can't use 'X' for negative numbers, because then we won't \
4368 get the right value for the upper 32 bits. */ \
4369 output_addr_const (STREAM, VALUE); \
4370 else \
4371 /* We must use 'X', because otherwise LONG_MIN will print as \
4372 a number that the Irix 6 assembler won't accept. */ \
4373 print_operand (STREAM, VALUE, 'X'); \
876c09d3
JW		 4374 fprintf (STREAM, "\n"); \
4375 } \
4376 else \
4377 { \
4378 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4379 UNITS_PER_WORD, 1); \
4380 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4381 UNITS_PER_WORD, 1); \
4382 } \
4383} while (0)
e75b25e7
MM		 4384
4385#define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4386{ \
4387 fprintf (STREAM, "\t.half\t"); \
4388 output_addr_const (STREAM, (VALUE)); \
4389 fprintf (STREAM, "\n"); \
4390}
4391
4392#define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4393{ \
4394 fprintf (STREAM, "\t.byte\t"); \
4395 output_addr_const (STREAM, (VALUE)); \
4396 fprintf (STREAM, "\n"); \
4397}
4398
e75b25e7
MM		 4399/* This is how to output an assembler line for a numeric constant byte. */
4400
4401#define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4402 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4403
4404/* This is how to output an element of a case-vector that is absolute. */
4405
4406#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
6ae1498b 4407 fprintf (STREAM, "\t%s\t%sL%d\n", \
1eeed24e 4408 Pmode == DImode ? ".dword" : ".word", \
6ae1498b 4409 LOCAL_LABEL_PREFIX, \
876c09d3 4410 VALUE)
e75b25e7
MM		 4411
4412/* This is how to output an element of a case-vector that is relative.
e0bfcea5
ILT		 4413 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4414 TARGET_EMBEDDED_PIC). */
e75b25e7 4415
33f7f353 4416#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
e0bfcea5 4417do { \
2bcb2ab3
GK		 4418 if (TARGET_MIPS16) \
4419 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4420 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4421 else if (TARGET_EMBEDDED_PIC) \
6ae1498b 4422 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
1eeed24e 4423 Pmode == DImode ? ".dword" : ".word", \
6ae1498b 4424 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
a53f72db 4425 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
6ae1498b 4426 fprintf (STREAM, "\t%s\t%sL%d\n", \
1eeed24e 4427 Pmode == DImode ? ".gpdword" : ".gpword", \
6ae1498b 4428 LOCAL_LABEL_PREFIX, VALUE); \
516a2dfd 4429 else \
b2d8cf33 4430 fprintf (STREAM, "\t%s\t%sL%d\n", \
1eeed24e 4431 Pmode == DImode ? ".dword" : ".word", \
b2d8cf33 4432 LOCAL_LABEL_PREFIX, VALUE); \
e0bfcea5
ILT		 4433} while (0)
4434
2bcb2ab3
GK		 4435/* When generating embedded PIC or mips16 code we want to put the jump
4436 table in the .text section. In all other cases, we want to put the
4437 jump table in the .rdata section. Unfortunately, we can't use
e0bfcea5
ILT		 4438 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4439 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4440 section if appropriate. */
4441#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4442do { \
2bcb2ab3
GK		 4443 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4444 function_section (current_function_decl); \
e0bfcea5
ILT		 4445 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4446} while (0)
e75b25e7
MM		 4447
4448/* This is how to output an assembler line
4449 that says to advance the location counter
4450 to a multiple of 2**LOG bytes. */
4451
4452#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
a688e0b7 4453 fprintf (STREAM, "\t.align\t%d\n", (LOG))
e75b25e7 4454
38e01259 4455/* This is how to output an assembler line to advance the location
e75b25e7
MM		 4456 counter by SIZE bytes. */
4457
4458#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4459 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4460
e75b25e7
MM		 4461/* This is how to output a string. */
4462#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4463do { \
4464 register int i, c, len = (LEN), cur_pos = 17; \
4465 register unsigned char *string = (unsigned char *)(STRING); \
4466 fprintf ((STREAM), "\t.ascii\t\""); \
4467 for (i = 0; i < len; i++) \
4468 { \
4469 register int c = string[i]; \
4470 \
4471 switch (c) \
4472 { \
4473 case '\"': \
4474 case '\\': \
4475 putc ('\\', (STREAM)); \
4476 putc (c, (STREAM)); \
4477 cur_pos += 2; \
4478 break; \
4479 \
4480 case TARGET_NEWLINE: \
87fc3db7 4481 fputs ("\\n", (STREAM)); \
e75b25e7
MM		 4482 if (i+1 < len \
4483 && (((c = string[i+1]) >= '\040' && c <= '~') \
4484 || c == TARGET_TAB)) \
4485 cur_pos = 32767; /* break right here */ \
4486 else \
4487 cur_pos += 2; \
4488 break; \
4489 \
4490 case TARGET_TAB: \
4491 fputs ("\\t", (STREAM)); \
4492 cur_pos += 2; \
4493 break; \
4494 \
4495 case TARGET_FF: \
4496 fputs ("\\f", (STREAM)); \
4497 cur_pos += 2; \
4498 break; \
4499 \
4500 case TARGET_BS: \
4501 fputs ("\\b", (STREAM)); \
4502 cur_pos += 2; \
4503 break; \
4504 \
4505 case TARGET_CR: \
4506 fputs ("\\r", (STREAM)); \
4507 cur_pos += 2; \
4508 break; \
4509 \
4510 default: \
4511 if (c >= ' ' && c < 0177) \
4512 { \
4513 putc (c, (STREAM)); \
4514 cur_pos++; \
4515 } \
4516 else \
4517 { \
4518 fprintf ((STREAM), "\\%03o", c); \
4519 cur_pos += 4; \
4520 } \
4521 } \
4522 \
4523 if (cur_pos > 72 && i+1 < len) \
4524 { \
4525 cur_pos = 17; \
4526 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4527 } \
4528 } \
4529 fprintf ((STREAM), "\"\n"); \
4530} while (0)
4531
4532/* Handle certain cpp directives used in header files on sysV. */
4533#define SCCS_DIRECTIVE
4534
4535/* Output #ident as a in the read-only data section. */
4536#define ASM_OUTPUT_IDENT(FILE, STRING) \
4537{ \
4538 char *p = STRING; \
4539 int size = strlen (p) + 1; \
4540 rdata_section (); \
4541 assemble_string (p, size); \
4542}
4543\f
b82b0773
MM		 4544/* Default to -G 8 */
4545#ifndef MIPS_DEFAULT_GVALUE
4546#define MIPS_DEFAULT_GVALUE 8
4547#endif
e75b25e7 4548
f3b39eba
MM		 4549/* Define the strings to put out for each section in the object file. */
4550#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4551#define DATA_SECTION_ASM_OP "\t.data" /* large data */
4552#define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4553#define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4554#define READONLY_DATA_SECTION rdata_section
3cf6400d 4555#define SMALL_DATA_SECTION sdata_section
e75b25e7
MM		 4556
4557/* What other sections we support other than the normal .data/.text. */
4558
876c09d3 4559#define EXTRA_SECTIONS in_sdata, in_rdata
e75b25e7
MM		 4560
4561/* Define the additional functions to select our additional sections. */
4562
4563/* on the MIPS it is not a good idea to put constants in the text
4564 section, since this defeats the sdata/data mechanism. This is
4565 especially true when -O is used. In this case an effort is made to
4566 address with faster (gp) register relative addressing, which can
4567 only get at sdata and sbss items (there is no stext !!) However,
4568 if the constant is too large for sdata, and it's readonly, it
4569 will go into the .rdata section. */
4570
4571#define EXTRA_SECTION_FUNCTIONS \
4572void \
4573sdata_section () \
4574{ \
4575 if (in_section != in_sdata) \
4576 { \
4577 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4578 in_section = in_sdata; \
4579 } \
4580} \
4581 \
4582void \
4583rdata_section () \
4584{ \
4585 if (in_section != in_rdata) \
4586 { \
4587 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4588 in_section = in_rdata; \
4589 } \
4590}
4591
4592/* Given a decl node or constant node, choose the section to output it in
4593 and select that section. */
4594
365c6a0b 4595#define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
e75b25e7 4596
365c6a0b 4597#define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
e75b25e7
MM		 4598
4599\f
4600/* Store in OUTPUT a string (made with alloca) containing
4601 an assembler-name for a local static variable named NAME.
4602 LABELNO is an integer which is different for each call. */
4603
4604#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4605( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4606 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4607
4608#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4609do \
4610 { \
876c09d3
JW		 4611 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4612 TARGET_64BIT ? "dsubu" : "subu", \
e75b25e7
MM		 4613 reg_names[STACK_POINTER_REGNUM], \
4614 reg_names[STACK_POINTER_REGNUM], \
876c09d3 4615 TARGET_64BIT ? "sd" : "sw", \
e75b25e7
MM		 4616 reg_names[REGNO], \
4617 reg_names[STACK_POINTER_REGNUM]); \
4618 } \
4619while (0)
4620
4621#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4622do \
4623 { \
4624 if (! set_noreorder) \
4625 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4626 \
4627 dslots_load_total++; \
4628 dslots_load_filled++; \
876c09d3
JW		 4629 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4630 TARGET_64BIT ? "ld" : "lw", \
e75b25e7
MM		 4631 reg_names[REGNO], \
4632 reg_names[STACK_POINTER_REGNUM], \
876c09d3 4633 TARGET_64BIT ? "daddu" : "addu", \
e75b25e7
MM		 4634 reg_names[STACK_POINTER_REGNUM], \
4635 reg_names[STACK_POINTER_REGNUM]); \
4636 \
4637 if (! set_noreorder) \
4638 fprintf (STREAM, "\t.set\treorder\n"); \
4639 } \
4640while (0)
4641
4642/* Define the parentheses used to group arithmetic operations
4643 in assembler code. */
4644
4645#define ASM_OPEN_PAREN "("
4646#define ASM_CLOSE_PAREN ")"
4647
4baed42f
DE		 4648/* How to start an assembler comment.
4649 The leading space is important (the mips native assembler requires it). */
e75b25e7 4650#ifndef ASM_COMMENT_START
4baed42f 4651#define ASM_COMMENT_START " #"
e75b25e7 4652#endif
e75b25e7
MM		 4653\f
4654
4655/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4656 and mips-tdump.c to print them out.
4657
4658 These must match the corresponding definitions in gdb/mipsread.c.
4659 Unfortunately, gcc and gdb do not currently share any directories. */
4660
4661#define CODE_MASK 0x8F300
4662#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4663#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4664#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3f1f8d8c
MM		 4665
4666\f
4667/* Default definitions for size_t and ptrdiff_t. */
4668
4669#ifndef SIZE_TYPE
876c09d3 4670#define NO_BUILTIN_SIZE_TYPE
1eeed24e 4671#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
3f1f8d8c
MM		 4672#endif
4673
4674#ifndef PTRDIFF_TYPE
876c09d3 4675#define NO_BUILTIN_PTRDIFF_TYPE
1eeed24e 4676#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
3f1f8d8c 4677#endif
28174a14
MS		 4678
4679/* See mips_expand_prologue's use of loadgp for when this should be
4680 true. */
4681
a53f72db
GRK		 4682#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4683 && mips_abi != ABI_32 \
4684 && mips_abi != ABI_O64)
2bcb2ab3
GK		 4685\f
4686/* In mips16 mode, we need to look through the function to check for
4687 PC relative loads that are out of range. */
4688#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4689
4690/* We need to use a special set of functions to handle hard floating
4691 point code in mips16 mode. */
337e2b69
ILT		 4692
4693#ifndef INIT_SUBTARGET_OPTABS
4694#define INIT_SUBTARGET_OPTABS
4695#endif
4696
4697#define INIT_TARGET_OPTABS \
4698do \
4699 { \
2bcb2ab3
GK		 4700 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4701 INIT_SUBTARGET_OPTABS; \
4702 else \
4703 { \
4704 add_optab->handlers[(int) SFmode].libfunc = \
4705 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4706 sub_optab->handlers[(int) SFmode].libfunc = \
4707 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4708 smul_optab->handlers[(int) SFmode].libfunc = \
4709 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4710 flodiv_optab->handlers[(int) SFmode].libfunc = \
4711 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4712 \
4713 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4714 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4715 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4716 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4717 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4718 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4719 \
4720 floatsisf_libfunc = \
4721 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4722 fixsfsi_libfunc = \
4723 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4724 \
4725 if (TARGET_DOUBLE_FLOAT) \
4726 { \
4727 add_optab->handlers[(int) DFmode].libfunc = \
4728 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4729 sub_optab->handlers[(int) DFmode].libfunc = \
4730 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4731 smul_optab->handlers[(int) DFmode].libfunc = \
4732 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4733 flodiv_optab->handlers[(int) DFmode].libfunc = \
4734 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4735 \
4736 extendsfdf2_libfunc = \
4737 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4738 truncdfsf2_libfunc = \
4739 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4740 \
4741 eqdf2_libfunc = \
4742 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4743 nedf2_libfunc = \
4744 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4745 gtdf2_libfunc = \
4746 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4747 gedf2_libfunc = \
4748 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4749 ltdf2_libfunc = \
4750 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4751 ledf2_libfunc = \
4752 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4753 \
4754 floatsidf_libfunc = \
4755 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4756 fixdfsi_libfunc = \
4757 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
4758 } \
4759 } \
337e2b69
ILT		 4760 } \
4761while (0)
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