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1; Options for the MIPS port of the compiler
2;
2f83c7d6 3; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
2f83c7d6 9; Software Foundation; either version 3, or (at your option) any later
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10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT
13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15; License for more details.
16;
17; You should have received a copy of the GNU General Public License
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18; along with GCC; see the file COPYING3. If not see
19; <http://www.gnu.org/licenses/>.
3ad7bb65 20
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21mabi=
22Target RejectNegative Joined
23-mabi=ABI Generate code that conforms to the given ABI
24
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25mabicalls
26Target Report Mask(ABICALLS)
d9870b7e 27Generate code that can be used in SVR4-style dynamic objects
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28
29mad
30Target Report Var(TARGET_MAD)
31Use PMC-style 'mad' instructions
32
d522e7a2 33march=
55bea00a 34Target RejectNegative Joined Var(mips_arch_string)
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35-march=ISA Generate code for the given ISA
36
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37mbranch-cost=
38Target RejectNegative Joined UInteger Var(mips_branch_cost)
39-mbranch-cost=COST Set the cost of branches to roughly COST instructions
40
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41mbranch-likely
42Target Report Mask(BRANCHLIKELY)
43Use Branch Likely instructions, overriding the architecture default
44
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45mflip-mips16
46Target Report Var(TARGET_FLIP_MIPS16)
47Switch on/off MIPS16 ASE on alternating functions for compiler testing
48
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49mcheck-zero-division
50Target Report Mask(CHECK_ZERO_DIV)
51Trap on integer divide by zero
52
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53mcode-readable=
54Target RejectNegative Joined
55-mcode-readable=SETTING Specify when instructions are allowed to access code
56
21c425ee 57mdivide-breaks
25e3d99d 58Target Report RejectNegative Mask(DIVIDE_BREAKS)
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59Use branch-and-break sequences to check for integer divide by zero
60
61mdivide-traps
25e3d99d 62Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
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63Use trap instructions to check for integer divide by zero
64
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65mdmx
66Target Report RejectNegative Var(TARGET_MDMX)
67Allow the use of MDMX instructions
68
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69mdouble-float
70Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
71Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations
72
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73mdsp
74Target Report Mask(DSP)
75Use MIPS-DSP instructions
76
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77mdspr2
78Target Report Mask(DSPR2)
79Use MIPS-DSP REV 2 instructions
80
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81mdebug
82Target Var(TARGET_DEBUG_MODE) Undocumented
83
84mdebugd
85Target Var(TARGET_DEBUG_D_MODE) Undocumented
86
87meb
88Target Report RejectNegative Mask(BIG_ENDIAN)
89Use big-endian byte order
90
91mel
92Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
93Use little-endian byte order
94
95membedded-data
96Target Report Var(TARGET_EMBEDDED_DATA)
97Use ROM instead of RAM
98
99mexplicit-relocs
100Target Report Mask(EXPLICIT_RELOCS)
101Use NewABI-style %reloc() assembly operators
102
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103mextern-sdata
104Target Report Var(TARGET_EXTERN_SDATA) Init(1)
105Use -G for data that is not defined by the current object
106
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107mfix-r4000
108Target Report Mask(FIX_R4000)
109Work around certain R4000 errata
110
111mfix-r4400
112Target Report Mask(FIX_R4400)
113Work around certain R4400 errata
114
115mfix-sb1
116Target Report Var(TARGET_FIX_SB1)
117Work around errata for early SB-1 revision 2 cores
118
119mfix-vr4120
120Target Report Var(TARGET_FIX_VR4120)
121Work around certain VR4120 errata
122
123mfix-vr4130
124Target Report Var(TARGET_FIX_VR4130)
125Work around VR4130 mflo/mfhi errata
126
127mfix4300
128Target Report Var(TARGET_4300_MUL_FIX)
129Work around an early 4300 hardware bug
130
131mfp-exceptions
132Target Report Mask(FP_EXCEPTIONS)
133FP exceptions are enabled
134
135mfp32
136Target Report RejectNegative InverseMask(FLOAT64)
137Use 32-bit floating-point registers
138
139mfp64
140Target Report RejectNegative Mask(FLOAT64)
141Use 64-bit floating-point registers
142
d522e7a2 143mflush-func=
55bea00a 144Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC)
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145-mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines
146
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147mfused-madd
148Target Report Mask(FUSED_MADD)
149Generate floating-point multiply-add instructions
150
151mgp32
152Target Report RejectNegative InverseMask(64BIT)
153Use 32-bit general registers
154
155mgp64
156Target Report RejectNegative Mask(64BIT)
157Use 64-bit general registers
158
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159mgpopt
160Target Report Var(TARGET_GPOPT) Init(1)
161Use GP-relative addressing to access small data
162
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163mplt
164Target Report Var(TARGET_PLT)
165When generating -mabicalls code, allow executables to use PLTs and copy relocations
166
21c425ee 167mhard-float
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168Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
169Allow the use of hardware floating-point ABI and instructions
21c425ee 170
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171minterlink-mips16
172Target Report Var(TARGET_INTERLINK_MIPS16) Init(0)
173Generate code that can be safely linked with MIPS16 code.
174
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175mips
176Target RejectNegative Joined
177-mipsN Generate code for ISA level N
178
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179mips16
180Target Report RejectNegative Mask(MIPS16)
500fc425 181Generate MIPS16 code
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182
183mips3d
184Target Report RejectNegative Mask(MIPS3D)
185Use MIPS-3D instructions
186
66471b47 187mllsc
e9276c30 188Target Report Mask(LLSC)
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189Use ll, sc and sync instructions
190
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191mlocal-sdata
192Target Report Var(TARGET_LOCAL_SDATA) Init(1)
193Use -G for object-local data
194
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195mlong-calls
196Target Report Var(TARGET_LONG_CALLS)
197Use indirect calls
198
199mlong32
200Target Report RejectNegative InverseMask(LONG64, LONG32)
201Use a 32-bit long type
202
203mlong64
204Target Report RejectNegative Mask(LONG64)
205Use a 64-bit long type
206
207mmemcpy
cfa31150 208Target Report Mask(MEMCPY)
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209Don't optimize block moves
210
211mmips-tfile
212Target
213Use the mips-tfile postpass
214
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215mmt
216Target Report Var(TARGET_MT)
217Allow the use of MT instructions
218
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219mno-flush-func
220Target RejectNegative
221Do not use a cache-flushing function before calling stack trampolines
222
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223mno-mdmx
224Target Report RejectNegative InverseVar(MDMX)
225Do not use MDMX instructions
226
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227mno-mips16
228Target Report RejectNegative InverseMask(MIPS16)
229Generate normal-mode code
230
231mno-mips3d
232Target Report RejectNegative InverseMask(MIPS3D)
233Do not use MIPS-3D instructions
234
235mpaired-single
236Target Report Mask(PAIRED_SINGLE_FLOAT)
237Use paired-single floating-point instructions
238
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239mshared
240Target Report Var(TARGET_SHARED) Init(1)
241When generating -mabicalls code, make the code suitable for use in shared libraries
242
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243msingle-float
244Target Report RejectNegative Mask(SINGLE_FLOAT)
245Restrict the use of hardware floating-point instructions to 32-bit operations
246
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247msmartmips
248Target Report RejectNegative Mask(SMARTMIPS)
249Use SmartMIPS instructions
250
21c425ee 251msoft-float
cc4ebe7d 252Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
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253Prevent the use of all hardware floating-point instructions
254
255msplit-addresses
256Target Report Mask(SPLIT_ADDRESSES)
257Optimize lui/addiu address loads
258
259msym32
260Target Report Var(TARGET_SYM32)
261Assume all symbols have 32-bit values
262
d522e7a2 263mtune=
55bea00a 264Target RejectNegative Joined Var(mips_tune_string)
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265-mtune=PROCESSOR Optimize the output for PROCESSOR
266
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267muninit-const-in-rodata
268Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
269Put uninitialized constants in ROM (needs -membedded-data)
270
271mvr4130-align
272Target Report Mask(VR4130_ALIGN)
273Perform VR4130-specific alignment optimizations
274
275mxgot
276Target Report Var(TARGET_XGOT)
277Lift restrictions on GOT size