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6045fab3 | 1 | ;; Octeon pipeline description. |
71e45bc2 | 2 | ;; Copyright (C) 2008, 2011, 2012 |
6045fab3 | 3 | ;; Free Software Foundation, Inc. |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ;; Copyright (C) 2004, 2005, 2006 Cavium Networks. | |
21 | ||
22 | ||
23 | ;; Octeon is a dual-issue processor that can issue all instructions on | |
24 | ;; pipe0 and a subset on pipe1. | |
25 | ||
26 | (define_automaton "octeon_main, octeon_mult") | |
27 | ||
28 | (define_cpu_unit "octeon_pipe0" "octeon_main") | |
29 | (define_cpu_unit "octeon_pipe1" "octeon_main") | |
30 | (define_cpu_unit "octeon_mult" "octeon_mult") | |
31 | ||
32 | (define_insn_reservation "octeon_arith" 1 | |
caa36f1c | 33 | (and (eq_attr "cpu" "octeon,octeon2") |
6045fab3 | 34 | (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop")) |
35 | "octeon_pipe0 | octeon_pipe1") | |
36 | ||
37 | (define_insn_reservation "octeon_condmove" 2 | |
caa36f1c | 38 | (and (eq_attr "cpu" "octeon,octeon2") |
6045fab3 | 39 | (eq_attr "type" "condmove")) |
40 | "octeon_pipe0 | octeon_pipe1") | |
41 | ||
caa36f1c | 42 | (define_insn_reservation "octeon_load_o1" 2 |
6045fab3 | 43 | (and (eq_attr "cpu" "octeon") |
44 | (eq_attr "type" "load,prefetch,mtc,mfc")) | |
45 | "octeon_pipe0") | |
46 | ||
caa36f1c | 47 | (define_insn_reservation "octeon_load_o2" 3 |
48 | (and (eq_attr "cpu" "octeon2") | |
49 | (eq_attr "type" "load,prefetch")) | |
50 | "octeon_pipe0") | |
51 | ||
52 | ;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency. | |
53 | ;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now. | |
54 | (define_insn_reservation "octeon_cop_o2" 1 | |
55 | (and (eq_attr "cpu" "octeon2") | |
56 | (eq_attr "type" "mtc,mfc")) | |
57 | "octeon_pipe1") | |
58 | ||
6045fab3 | 59 | (define_insn_reservation "octeon_store" 1 |
caa36f1c | 60 | (and (eq_attr "cpu" "octeon,octeon2") |
6045fab3 | 61 | (eq_attr "type" "store")) |
62 | "octeon_pipe0") | |
63 | ||
caa36f1c | 64 | (define_insn_reservation "octeon_brj_o1" 1 |
6045fab3 | 65 | (and (eq_attr "cpu" "octeon") |
66 | (eq_attr "type" "branch,jump,call,trap")) | |
67 | "octeon_pipe0") | |
68 | ||
caa36f1c | 69 | (define_insn_reservation "octeon_brj_o2" 2 |
70 | (and (eq_attr "cpu" "octeon2") | |
71 | (eq_attr "type" "branch,jump,call,trap")) | |
72 | "octeon_pipe1") | |
73 | ||
74 | (define_insn_reservation "octeon_imul3_o1" 5 | |
6045fab3 | 75 | (and (eq_attr "cpu" "octeon") |
76 | (eq_attr "type" "imul3,pop,clz")) | |
77 | "(octeon_pipe0 | octeon_pipe1) + octeon_mult") | |
78 | ||
caa36f1c | 79 | (define_insn_reservation "octeon_imul3_o2" 6 |
80 | (and (eq_attr "cpu" "octeon2") | |
81 | (eq_attr "type" "imul3,pop,clz")) | |
82 | "octeon_pipe1 + octeon_mult") | |
83 | ||
84 | (define_insn_reservation "octeon_imul_o1" 2 | |
6045fab3 | 85 | (and (eq_attr "cpu" "octeon") |
8ad8575f | 86 | (eq_attr "type" "imul,mthi,mtlo")) |
6045fab3 | 87 | "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult") |
88 | ||
caa36f1c | 89 | (define_insn_reservation "octeon_imul_o2" 1 |
90 | (and (eq_attr "cpu" "octeon2") | |
8ad8575f | 91 | (eq_attr "type" "imul,mthi,mtlo")) |
caa36f1c | 92 | "octeon_pipe1 + octeon_mult") |
93 | ||
94 | (define_insn_reservation "octeon_mfhilo_o1" 5 | |
6045fab3 | 95 | (and (eq_attr "cpu" "octeon") |
8ad8575f | 96 | (eq_attr "type" "mfhi,mflo")) |
6045fab3 | 97 | "(octeon_pipe0 | octeon_pipe1) + octeon_mult") |
98 | ||
caa36f1c | 99 | (define_insn_reservation "octeon_mfhilo_o2" 6 |
100 | (and (eq_attr "cpu" "octeon2") | |
8ad8575f | 101 | (eq_attr "type" "mfhi,mflo")) |
caa36f1c | 102 | "octeon_pipe1 + octeon_mult") |
103 | ||
104 | (define_insn_reservation "octeon_imadd_o1" 4 | |
6045fab3 | 105 | (and (eq_attr "cpu" "octeon") |
106 | (eq_attr "type" "imadd")) | |
107 | "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3") | |
108 | ||
caa36f1c | 109 | (define_insn_reservation "octeon_imadd_o2" 1 |
110 | (and (eq_attr "cpu" "octeon2") | |
111 | (eq_attr "type" "imadd")) | |
112 | "octeon_pipe1 + octeon_mult") | |
113 | ||
114 | (define_insn_reservation "octeon_idiv_o1" 72 | |
6045fab3 | 115 | (and (eq_attr "cpu" "octeon") |
116 | (eq_attr "type" "idiv")) | |
117 | "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71") | |
118 | ||
caa36f1c | 119 | (define_insn_reservation "octeon_idiv_o2_si" 18 |
120 | (and (eq_attr "cpu" "octeon2") | |
121 | (eq_attr "mode" "SI") | |
122 | (eq_attr "type" "idiv")) | |
123 | "octeon_pipe1 + octeon_mult, octeon_mult*17") | |
124 | ||
125 | (define_insn_reservation "octeon_idiv_o2_di" 35 | |
126 | (and (eq_attr "cpu" "octeon2") | |
127 | (eq_attr "mode" "DI") | |
128 | (eq_attr "type" "idiv")) | |
129 | "octeon_pipe1 + octeon_mult, octeon_mult*34") | |
130 | ||
6045fab3 | 131 | ;; Assume both pipes are needed for unknown and multiple-instruction |
132 | ;; patterns. | |
133 | ||
134 | (define_insn_reservation "octeon_unknown" 1 | |
caa36f1c | 135 | (and (eq_attr "cpu" "octeon,octeon2") |
408ae786 | 136 | (eq_attr "type" "unknown,multi,atomic,syncloop")) |
6045fab3 | 137 | "octeon_pipe0 + octeon_pipe1") |