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99dee823 | 1 | /* Copyright (C) 1999-2021 Free Software Foundation, Inc. |
55047c9d PE |
2 | |
3 | This file is part of GCC. | |
4 | ||
5 | GCC is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 7 | the Free Software Foundation; either version 3, or (at your option) |
55047c9d PE |
8 | any later version. |
9 | ||
10 | GCC is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
16 | along with GCC; see the file COPYING3. If not see |
17 | <http://www.gnu.org/licenses/>. */ | |
55047c9d | 18 | |
55047c9d PE |
19 | #undef ASM_SPEC |
20 | #define ASM_SPEC "\ | |
21 | %{!G:-G 0} %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ | |
22 | %{mips32} %{mips32r2} %{mips64} \ | |
23 | %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ | |
24 | %(subtarget_asm_optimizing_spec) \ | |
25 | %(subtarget_asm_debugging_spec) \ | |
5811cb27 | 26 | %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \ |
55047c9d | 27 | %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ |
78a14252 | 28 | %{mtune=*} \ |
55047c9d PE |
29 | %(subtarget_asm_spec)" |
30 | ||
31 | #undef LINK_SPEC | |
55047c9d PE |
32 | #define LINK_SPEC "\ |
33 | %(endian_spec) \ | |
cbabf03f | 34 | %{!G:-G 0} %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} " \ |
9200d6c8 RS |
35 | VXWORKS_LINK_SPEC |
36 | ||
37 | #undef LIB_SPEC | |
38 | #define LIB_SPEC VXWORKS_LIB_SPEC | |
39 | #undef STARTFILE_SPEC | |
40 | #define STARTFILE_SPEC VXWORKS_STARTFILE_SPEC | |
41 | #undef ENDFILE_SPEC | |
42 | #define ENDFILE_SPEC VXWORKS_ENDFILE_SPEC | |
55047c9d PE |
43 | |
44 | #define TARGET_OS_CPP_BUILTINS() \ | |
45 | do \ | |
46 | { \ | |
9200d6c8 RS |
47 | if (TARGET_64BIT) \ |
48 | builtin_define ("CPU=MIPS64"); \ | |
49 | else \ | |
50 | builtin_define ("CPU=MIPS32"); \ | |
51 | if (TARGET_BIG_ENDIAN) \ | |
52 | builtin_define ("MIPSEB"); \ | |
53 | else \ | |
54 | builtin_define ("MIPSEL"); \ | |
55 | if (TARGET_SOFT_FLOAT) \ | |
56 | builtin_define ("SOFT_FLOAT"); \ | |
57 | VXWORKS_OS_CPP_BUILTINS (); \ | |
55047c9d PE |
58 | } \ |
59 | while (0) | |
60 | ||
61 | #undef SUBTARGET_CPP_SPEC | |
9200d6c8 | 62 | #define SUBTARGET_CPP_SPEC VXWORKS_ADDITIONAL_CPP_SPEC |
55047c9d PE |
63 | |
64 | /* No sdata. */ | |
65 | #undef MIPS_DEFAULT_GVALUE | |
66 | #define MIPS_DEFAULT_GVALUE 0 | |
9200d6c8 | 67 | |
9200d6c8 RS |
68 | /* No _mcount profiling on VxWorks. */ |
69 | #undef FUNCTION_PROFILER | |
70 | #define FUNCTION_PROFILER VXWORKS_FUNCTION_PROFILER | |
8cb6400c RS |
71 | |
72 | #undef SUBTARGET_ASM_SPEC | |
428b3812 | 73 | #define SUBTARGET_ASM_SPEC "%{mrtp:%{" FPIC_SPEC ":-mvxworks-pic}}" |
d1138d8e RS |
74 | |
75 | #undef SUBTARGET_OVERRIDE_OPTIONS | |
76 | #define SUBTARGET_OVERRIDE_OPTIONS VXWORKS_OVERRIDE_OPTIONS | |
efa58006 JM |
77 | |
78 | #undef DBX_REGISTER_NUMBER |