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29a404f9 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
3072d30e | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
7cf0dbf3 | 3 | 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
29a404f9 | 4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
3626e955 | 6 | This file is part of GCC. |
29a404f9 | 7 | |
3626e955 | 8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
29a404f9 | 12 | |
3626e955 | 13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
29a404f9 | 17 | |
3626e955 | 18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
29a404f9 | 21 | |
29a404f9 | 22 | #include "config.h" |
7014838c | 23 | #include "system.h" |
805e22b2 | 24 | #include "coretypes.h" |
25 | #include "tm.h" | |
29a404f9 | 26 | #include "rtl.h" |
4faf81b8 | 27 | #include "tree.h" |
29a404f9 | 28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
29a404f9 | 30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
29a404f9 | 32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
8b8be022 | 36 | #include "reload.h" |
29a404f9 | 37 | #include "expr.h" |
d8fc4d0b | 38 | #include "optabs.h" |
4faf81b8 | 39 | #include "function.h" |
29a404f9 | 40 | #include "obstack.h" |
0b205f4c | 41 | #include "diagnostic-core.h" |
59086782 | 42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
a767736d | 44 | #include "target.h" |
45 | #include "target-def.h" | |
5574dbdd | 46 | #include "df.h" |
29a404f9 | 47 | |
b87a151a | 48 | /* This is used by GOTaddr2picreg to uniquely identify |
49 | UNSPEC_INT_LABELs. */ | |
50 | int mn10300_unspec_int_label_counter; | |
51 | ||
1acdfc69 | 52 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
53 | names are not prefixed by underscores, to tell whether to prefix a | |
54 | label with a plus sign or not, so that the assembler can tell | |
55 | symbol names from register names. */ | |
56 | int mn10300_protect_label; | |
57 | ||
8c2c40c5 | 58 | /* The selected processor. */ |
59 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
60 | ||
4879b320 | 61 | /* Processor type to select for tuning. */ |
62 | static const char * mn10300_tune_string = NULL; | |
63 | ||
64 | /* Selected processor type for tuning. */ | |
65 | enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT; | |
66 | ||
8ecf154e | 67 | /* The size of the callee register save area. Right now we save everything |
68 | on entry since it costs us nothing in code size. It does cost us from a | |
69 | speed standpoint, so we want to optimize this sooner or later. */ | |
3626e955 | 70 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
71 | + 4 * df_regs_ever_live_p (3) \ | |
72 | + 4 * df_regs_ever_live_p (6) \ | |
73 | + 4 * df_regs_ever_live_p (7) \ | |
74 | + 16 * (df_regs_ever_live_p (14) \ | |
75 | || df_regs_ever_live_p (15) \ | |
76 | || df_regs_ever_live_p (16) \ | |
77 | || df_regs_ever_live_p (17))) | |
e92d3ba8 | 78 | |
3626e955 | 79 | static int mn10300_address_cost (rtx, bool); |
c17f64cc | 80 | |
81 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ | |
82 | static const struct default_options mn10300_option_optimization_table[] = | |
83 | { | |
84 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
85 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
86 | }; | |
a767736d | 87 | \f |
8c2c40c5 | 88 | /* Implement TARGET_HANDLE_OPTION. */ |
89 | ||
90 | static bool | |
91 | mn10300_handle_option (size_t code, | |
92 | const char *arg ATTRIBUTE_UNUSED, | |
93 | int value) | |
94 | { | |
95 | switch (code) | |
96 | { | |
97 | case OPT_mam33: | |
98 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
99 | return true; | |
4879b320 | 100 | |
8c2c40c5 | 101 | case OPT_mam33_2: |
102 | mn10300_processor = (value | |
103 | ? PROCESSOR_AM33_2 | |
104 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
105 | return true; | |
4879b320 | 106 | |
107 | case OPT_mam34: | |
108 | mn10300_processor = (value ? PROCESSOR_AM34 : PROCESSOR_DEFAULT); | |
109 | return true; | |
110 | ||
111 | case OPT_mtune_: | |
112 | mn10300_tune_string = arg; | |
113 | return true; | |
114 | ||
8c2c40c5 | 115 | default: |
116 | return true; | |
117 | } | |
118 | } | |
119 | ||
4c834714 | 120 | /* Implement TARGET_OPTION_OVERRIDE. */ |
8c2c40c5 | 121 | |
4c834714 | 122 | static void |
123 | mn10300_option_override (void) | |
8c2c40c5 | 124 | { |
125 | if (TARGET_AM33) | |
126 | target_flags &= ~MASK_MULT_BUG; | |
4879b320 | 127 | else |
128 | { | |
129 | /* Disable scheduling for the MN10300 as we do | |
130 | not have timing information available for it. */ | |
131 | flag_schedule_insns = 0; | |
132 | flag_schedule_insns_after_reload = 0; | |
133 | } | |
134 | ||
135 | if (mn10300_tune_string) | |
136 | { | |
137 | if (strcasecmp (mn10300_tune_string, "mn10300") == 0) | |
138 | mn10300_tune_cpu = PROCESSOR_MN10300; | |
139 | else if (strcasecmp (mn10300_tune_string, "am33") == 0) | |
140 | mn10300_tune_cpu = PROCESSOR_AM33; | |
141 | else if (strcasecmp (mn10300_tune_string, "am33-2") == 0) | |
142 | mn10300_tune_cpu = PROCESSOR_AM33_2; | |
143 | else if (strcasecmp (mn10300_tune_string, "am34") == 0) | |
144 | mn10300_tune_cpu = PROCESSOR_AM34; | |
145 | else | |
146 | error ("-mtune= expects mn10300, am33, am33-2, or am34"); | |
147 | } | |
8c2c40c5 | 148 | } |
149 | ||
92c473b8 | 150 | static void |
3285410a | 151 | mn10300_file_start (void) |
29a404f9 | 152 | { |
92c473b8 | 153 | default_file_start (); |
911517ac | 154 | |
b166356e | 155 | if (TARGET_AM33_2) |
156 | fprintf (asm_out_file, "\t.am33_2\n"); | |
157 | else if (TARGET_AM33) | |
92c473b8 | 158 | fprintf (asm_out_file, "\t.am33\n"); |
29a404f9 | 159 | } |
160 | \f | |
29a404f9 | 161 | /* Print operand X using operand code CODE to assembly language output file |
162 | FILE. */ | |
163 | ||
164 | void | |
3626e955 | 165 | mn10300_print_operand (FILE *file, rtx x, int code) |
29a404f9 | 166 | { |
167 | switch (code) | |
168 | { | |
169 | case 'b': | |
170 | case 'B': | |
5574dbdd | 171 | if (GET_MODE (XEXP (x, 0)) == CC_FLOATmode) |
b166356e | 172 | { |
173 | switch (code == 'b' ? GET_CODE (x) | |
174 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
175 | { | |
176 | case NE: | |
177 | fprintf (file, "ne"); | |
178 | break; | |
179 | case EQ: | |
180 | fprintf (file, "eq"); | |
181 | break; | |
182 | case GE: | |
183 | fprintf (file, "ge"); | |
184 | break; | |
185 | case GT: | |
186 | fprintf (file, "gt"); | |
187 | break; | |
188 | case LE: | |
189 | fprintf (file, "le"); | |
190 | break; | |
191 | case LT: | |
192 | fprintf (file, "lt"); | |
193 | break; | |
194 | case ORDERED: | |
195 | fprintf (file, "lge"); | |
196 | break; | |
197 | case UNORDERED: | |
198 | fprintf (file, "uo"); | |
199 | break; | |
200 | case LTGT: | |
201 | fprintf (file, "lg"); | |
202 | break; | |
203 | case UNEQ: | |
204 | fprintf (file, "ue"); | |
205 | break; | |
206 | case UNGE: | |
207 | fprintf (file, "uge"); | |
208 | break; | |
209 | case UNGT: | |
210 | fprintf (file, "ug"); | |
211 | break; | |
212 | case UNLE: | |
213 | fprintf (file, "ule"); | |
214 | break; | |
215 | case UNLT: | |
216 | fprintf (file, "ul"); | |
217 | break; | |
218 | default: | |
cf41bb03 | 219 | gcc_unreachable (); |
b166356e | 220 | } |
221 | break; | |
222 | } | |
29a404f9 | 223 | /* These are normal and reversed branches. */ |
224 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
225 | { | |
226 | case NE: | |
227 | fprintf (file, "ne"); | |
228 | break; | |
229 | case EQ: | |
230 | fprintf (file, "eq"); | |
231 | break; | |
232 | case GE: | |
233 | fprintf (file, "ge"); | |
234 | break; | |
235 | case GT: | |
236 | fprintf (file, "gt"); | |
237 | break; | |
238 | case LE: | |
239 | fprintf (file, "le"); | |
240 | break; | |
241 | case LT: | |
242 | fprintf (file, "lt"); | |
243 | break; | |
244 | case GEU: | |
245 | fprintf (file, "cc"); | |
246 | break; | |
247 | case GTU: | |
248 | fprintf (file, "hi"); | |
249 | break; | |
250 | case LEU: | |
251 | fprintf (file, "ls"); | |
252 | break; | |
253 | case LTU: | |
254 | fprintf (file, "cs"); | |
255 | break; | |
256 | default: | |
cf41bb03 | 257 | gcc_unreachable (); |
29a404f9 | 258 | } |
259 | break; | |
260 | case 'C': | |
261 | /* This is used for the operand to a call instruction; | |
262 | if it's a REG, enclose it in parens, else output | |
263 | the operand normally. */ | |
3626e955 | 264 | if (REG_P (x)) |
29a404f9 | 265 | { |
266 | fputc ('(', file); | |
3626e955 | 267 | mn10300_print_operand (file, x, 0); |
29a404f9 | 268 | fputc (')', file); |
269 | } | |
270 | else | |
3626e955 | 271 | mn10300_print_operand (file, x, 0); |
29a404f9 | 272 | break; |
fb16c776 | 273 | |
b166356e | 274 | case 'D': |
275 | switch (GET_CODE (x)) | |
276 | { | |
277 | case MEM: | |
278 | fputc ('(', file); | |
279 | output_address (XEXP (x, 0)); | |
280 | fputc (')', file); | |
281 | break; | |
282 | ||
283 | case REG: | |
284 | fprintf (file, "fd%d", REGNO (x) - 18); | |
285 | break; | |
286 | ||
287 | default: | |
cf41bb03 | 288 | gcc_unreachable (); |
b166356e | 289 | } |
290 | break; | |
291 | ||
6ce19398 | 292 | /* These are the least significant word in a 64bit value. */ |
293 | case 'L': | |
294 | switch (GET_CODE (x)) | |
295 | { | |
296 | case MEM: | |
297 | fputc ('(', file); | |
298 | output_address (XEXP (x, 0)); | |
299 | fputc (')', file); | |
300 | break; | |
301 | ||
302 | case REG: | |
303 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
304 | break; | |
305 | ||
306 | case SUBREG: | |
701e46d0 | 307 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
6ce19398 | 308 | break; |
309 | ||
310 | case CONST_DOUBLE: | |
311 | { | |
312 | long val[2]; | |
313 | REAL_VALUE_TYPE rv; | |
314 | ||
315 | switch (GET_MODE (x)) | |
316 | { | |
317 | case DFmode: | |
318 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
319 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 320 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 321 | break;; |
322 | case SFmode: | |
323 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
324 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
ad3c0f03 | 325 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 326 | break;; |
327 | case VOIDmode: | |
328 | case DImode: | |
3626e955 | 329 | mn10300_print_operand_address (file, |
330 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
6ce19398 | 331 | break; |
59086782 | 332 | default: |
333 | break; | |
6ce19398 | 334 | } |
335 | break; | |
336 | } | |
337 | ||
338 | case CONST_INT: | |
964d057c | 339 | { |
340 | rtx low, high; | |
341 | split_double (x, &low, &high); | |
342 | fprintf (file, "%ld", (long)INTVAL (low)); | |
343 | break; | |
344 | } | |
6ce19398 | 345 | |
346 | default: | |
cf41bb03 | 347 | gcc_unreachable (); |
6ce19398 | 348 | } |
349 | break; | |
350 | ||
351 | /* Similarly, but for the most significant word. */ | |
352 | case 'H': | |
353 | switch (GET_CODE (x)) | |
354 | { | |
355 | case MEM: | |
356 | fputc ('(', file); | |
eafc6604 | 357 | x = adjust_address (x, SImode, 4); |
6ce19398 | 358 | output_address (XEXP (x, 0)); |
359 | fputc (')', file); | |
360 | break; | |
361 | ||
362 | case REG: | |
363 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
364 | break; | |
365 | ||
366 | case SUBREG: | |
701e46d0 | 367 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
6ce19398 | 368 | break; |
369 | ||
370 | case CONST_DOUBLE: | |
371 | { | |
372 | long val[2]; | |
373 | REAL_VALUE_TYPE rv; | |
374 | ||
375 | switch (GET_MODE (x)) | |
376 | { | |
377 | case DFmode: | |
378 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
379 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 380 | fprintf (file, "0x%lx", val[1]); |
6ce19398 | 381 | break;; |
382 | case SFmode: | |
cf41bb03 | 383 | gcc_unreachable (); |
6ce19398 | 384 | case VOIDmode: |
385 | case DImode: | |
3626e955 | 386 | mn10300_print_operand_address (file, |
387 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
6ce19398 | 388 | break; |
59086782 | 389 | default: |
390 | break; | |
6ce19398 | 391 | } |
392 | break; | |
393 | } | |
394 | ||
395 | case CONST_INT: | |
964d057c | 396 | { |
397 | rtx low, high; | |
398 | split_double (x, &low, &high); | |
399 | fprintf (file, "%ld", (long)INTVAL (high)); | |
400 | break; | |
401 | } | |
402 | ||
6ce19398 | 403 | default: |
cf41bb03 | 404 | gcc_unreachable (); |
6ce19398 | 405 | } |
406 | break; | |
407 | ||
408 | case 'A': | |
409 | fputc ('(', file); | |
4879b320 | 410 | if (REG_P (XEXP (x, 0))) |
bcd9bd66 | 411 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
6ce19398 | 412 | else |
413 | output_address (XEXP (x, 0)); | |
414 | fputc (')', file); | |
415 | break; | |
416 | ||
167fa942 | 417 | case 'N': |
cf41bb03 | 418 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
058f71f0 | 419 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
420 | break; | |
421 | ||
422 | case 'U': | |
cf41bb03 | 423 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
058f71f0 | 424 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
167fa942 | 425 | break; |
426 | ||
63e678f2 | 427 | /* For shift counts. The hardware ignores the upper bits of |
428 | any immediate, but the assembler will flag an out of range | |
429 | shift count as an error. So we mask off the high bits | |
430 | of the immediate here. */ | |
431 | case 'S': | |
4879b320 | 432 | if (CONST_INT_P (x)) |
63e678f2 | 433 | { |
058f71f0 | 434 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
63e678f2 | 435 | break; |
436 | } | |
437 | /* FALL THROUGH */ | |
438 | ||
29a404f9 | 439 | default: |
440 | switch (GET_CODE (x)) | |
441 | { | |
442 | case MEM: | |
443 | fputc ('(', file); | |
444 | output_address (XEXP (x, 0)); | |
445 | fputc (')', file); | |
446 | break; | |
447 | ||
6ce19398 | 448 | case PLUS: |
449 | output_address (x); | |
450 | break; | |
451 | ||
29a404f9 | 452 | case REG: |
453 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
454 | break; | |
455 | ||
456 | case SUBREG: | |
701e46d0 | 457 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
29a404f9 | 458 | break; |
459 | ||
6ce19398 | 460 | /* This will only be single precision.... */ |
461 | case CONST_DOUBLE: | |
462 | { | |
463 | unsigned long val; | |
464 | REAL_VALUE_TYPE rv; | |
465 | ||
466 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
467 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
ad3c0f03 | 468 | fprintf (file, "0x%lx", val); |
6ce19398 | 469 | break; |
470 | } | |
471 | ||
29a404f9 | 472 | case CONST_INT: |
473 | case SYMBOL_REF: | |
474 | case CONST: | |
475 | case LABEL_REF: | |
476 | case CODE_LABEL: | |
b87a151a | 477 | case UNSPEC: |
3626e955 | 478 | mn10300_print_operand_address (file, x); |
29a404f9 | 479 | break; |
480 | default: | |
cf41bb03 | 481 | gcc_unreachable (); |
29a404f9 | 482 | } |
483 | break; | |
484 | } | |
485 | } | |
486 | ||
487 | /* Output assembly language output for the address ADDR to FILE. */ | |
488 | ||
489 | void | |
3626e955 | 490 | mn10300_print_operand_address (FILE *file, rtx addr) |
29a404f9 | 491 | { |
492 | switch (GET_CODE (addr)) | |
493 | { | |
911517ac | 494 | case POST_INC: |
3626e955 | 495 | mn10300_print_operand_address (file, XEXP (addr, 0)); |
911517ac | 496 | fputc ('+', file); |
497 | break; | |
29a404f9 | 498 | case REG: |
3626e955 | 499 | mn10300_print_operand (file, addr, 0); |
29a404f9 | 500 | break; |
501 | case PLUS: | |
502 | { | |
503 | rtx base, index; | |
504 | if (REG_P (XEXP (addr, 0)) | |
505 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
506 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
507 | else if (REG_P (XEXP (addr, 1)) | |
508 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
509 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
510 | else | |
cf41bb03 | 511 | gcc_unreachable (); |
3626e955 | 512 | mn10300_print_operand (file, index, 0); |
29a404f9 | 513 | fputc (',', file); |
3626e955 | 514 | mn10300_print_operand (file, base, 0);; |
29a404f9 | 515 | break; |
516 | } | |
517 | case SYMBOL_REF: | |
518 | output_addr_const (file, addr); | |
519 | break; | |
520 | default: | |
521 | output_addr_const (file, addr); | |
522 | break; | |
523 | } | |
524 | } | |
525 | ||
b166356e | 526 | /* Count the number of FP registers that have to be saved. */ |
527 | static int | |
3285410a | 528 | fp_regs_to_save (void) |
b166356e | 529 | { |
530 | int i, n = 0; | |
531 | ||
532 | if (! TARGET_AM33_2) | |
533 | return 0; | |
534 | ||
535 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 536 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
b166356e | 537 | ++n; |
538 | ||
539 | return n; | |
540 | } | |
541 | ||
4caa3669 | 542 | /* Print a set of registers in the format required by "movm" and "ret". |
543 | Register K is saved if bit K of MASK is set. The data and address | |
544 | registers can be stored individually, but the extended registers cannot. | |
f2b32076 | 545 | We assume that the mask already takes that into account. For instance, |
09e5ce26 | 546 | bits 14 to 17 must have the same value. */ |
4caa3669 | 547 | |
548 | void | |
3285410a | 549 | mn10300_print_reg_list (FILE *file, int mask) |
4caa3669 | 550 | { |
551 | int need_comma; | |
552 | int i; | |
553 | ||
554 | need_comma = 0; | |
555 | fputc ('[', file); | |
556 | ||
557 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
558 | if ((mask & (1 << i)) != 0) | |
559 | { | |
560 | if (need_comma) | |
561 | fputc (',', file); | |
562 | fputs (reg_names [i], file); | |
563 | need_comma = 1; | |
564 | } | |
565 | ||
566 | if ((mask & 0x3c000) != 0) | |
567 | { | |
cf41bb03 | 568 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
4caa3669 | 569 | if (need_comma) |
570 | fputc (',', file); | |
571 | fputs ("exreg1", file); | |
572 | need_comma = 1; | |
573 | } | |
574 | ||
575 | fputc (']', file); | |
576 | } | |
577 | ||
6ce19398 | 578 | int |
3626e955 | 579 | mn10300_can_use_return_insn (void) |
6ce19398 | 580 | { |
36ed4406 | 581 | /* size includes the fixed stack space needed for function calls. */ |
abe32cce | 582 | int size = get_frame_size () + crtl->outgoing_args_size; |
36ed4406 | 583 | |
584 | /* And space for the return pointer. */ | |
abe32cce | 585 | size += crtl->outgoing_args_size ? 4 : 0; |
6ce19398 | 586 | |
587 | return (reload_completed | |
588 | && size == 0 | |
3072d30e | 589 | && !df_regs_ever_live_p (2) |
590 | && !df_regs_ever_live_p (3) | |
591 | && !df_regs_ever_live_p (6) | |
592 | && !df_regs_ever_live_p (7) | |
593 | && !df_regs_ever_live_p (14) | |
594 | && !df_regs_ever_live_p (15) | |
595 | && !df_regs_ever_live_p (16) | |
596 | && !df_regs_ever_live_p (17) | |
b166356e | 597 | && fp_regs_to_save () == 0 |
6ce19398 | 598 | && !frame_pointer_needed); |
599 | } | |
600 | ||
4caa3669 | 601 | /* Returns the set of live, callee-saved registers as a bitmask. The |
602 | callee-saved extended registers cannot be stored individually, so | |
09e5ce26 | 603 | all of them will be included in the mask if any one of them is used. */ |
4caa3669 | 604 | |
605 | int | |
3285410a | 606 | mn10300_get_live_callee_saved_regs (void) |
4caa3669 | 607 | { |
608 | int mask; | |
609 | int i; | |
610 | ||
611 | mask = 0; | |
b166356e | 612 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
d37e81ec | 613 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
4caa3669 | 614 | mask |= (1 << i); |
615 | if ((mask & 0x3c000) != 0) | |
616 | mask |= 0x3c000; | |
617 | ||
618 | return mask; | |
619 | } | |
620 | ||
5f2853dd | 621 | static rtx |
622 | F (rtx r) | |
623 | { | |
624 | RTX_FRAME_RELATED_P (r) = 1; | |
625 | return r; | |
626 | } | |
627 | ||
4caa3669 | 628 | /* Generate an instruction that pushes several registers onto the stack. |
629 | Register K will be saved if bit K in MASK is set. The function does | |
630 | nothing if MASK is zero. | |
631 | ||
632 | To be compatible with the "movm" instruction, the lowest-numbered | |
633 | register must be stored in the lowest slot. If MASK is the set | |
634 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
635 | instruction will have the form: | |
636 | ||
637 | (parallel | |
638 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
639 | (set (mem:SI (plus:SI (reg:SI 9) | |
640 | (const_int -1*4))) | |
641 | (reg:SI RN)) | |
642 | ... | |
643 | (set (mem:SI (plus:SI (reg:SI 9) | |
644 | (const_int -N*4))) | |
645 | (reg:SI R1))) */ | |
646 | ||
647 | void | |
3285410a | 648 | mn10300_gen_multiple_store (int mask) |
4caa3669 | 649 | { |
650 | if (mask != 0) | |
651 | { | |
652 | int i; | |
653 | int count; | |
654 | rtx par; | |
655 | int pari; | |
656 | ||
09e5ce26 | 657 | /* Count how many registers need to be saved. */ |
4caa3669 | 658 | count = 0; |
b166356e | 659 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 660 | if ((mask & (1 << i)) != 0) |
661 | count += 1; | |
662 | ||
663 | /* We need one PARALLEL element to update the stack pointer and | |
09e5ce26 | 664 | an additional element for each register that is stored. */ |
4caa3669 | 665 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
666 | ||
09e5ce26 | 667 | /* Create the instruction that updates the stack pointer. */ |
4caa3669 | 668 | XVECEXP (par, 0, 0) |
5f2853dd | 669 | = F (gen_rtx_SET (SImode, |
670 | stack_pointer_rtx, | |
671 | gen_rtx_PLUS (SImode, | |
672 | stack_pointer_rtx, | |
673 | GEN_INT (-count * 4)))); | |
4caa3669 | 674 | |
09e5ce26 | 675 | /* Create each store. */ |
4caa3669 | 676 | pari = 1; |
b166356e | 677 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
4caa3669 | 678 | if ((mask & (1 << i)) != 0) |
679 | { | |
680 | rtx address = gen_rtx_PLUS (SImode, | |
681 | stack_pointer_rtx, | |
682 | GEN_INT (-pari * 4)); | |
683 | XVECEXP(par, 0, pari) | |
5f2853dd | 684 | = F (gen_rtx_SET (VOIDmode, |
685 | gen_rtx_MEM (SImode, address), | |
686 | gen_rtx_REG (SImode, i))); | |
4caa3669 | 687 | pari += 1; |
688 | } | |
689 | ||
5f2853dd | 690 | F (emit_insn (par)); |
4caa3669 | 691 | } |
692 | } | |
693 | ||
29a404f9 | 694 | void |
3626e955 | 695 | mn10300_expand_prologue (void) |
29a404f9 | 696 | { |
e3f95b40 | 697 | HOST_WIDE_INT size; |
f1899bff | 698 | |
f1899bff | 699 | /* SIZE includes the fixed stack space needed for function calls. */ |
abe32cce | 700 | size = get_frame_size () + crtl->outgoing_args_size; |
701 | size += (crtl->outgoing_args_size ? 4 : 0); | |
29a404f9 | 702 | |
09e5ce26 | 703 | /* If we use any of the callee-saved registers, save them now. */ |
4caa3669 | 704 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
48cb86e3 | 705 | |
b166356e | 706 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
707 | { | |
708 | int num_regs_to_save = fp_regs_to_save (), i; | |
709 | HOST_WIDE_INT xsize; | |
3626e955 | 710 | enum |
711 | { | |
712 | save_sp_merge, | |
713 | save_sp_no_merge, | |
714 | save_sp_partial_merge, | |
715 | save_a0_merge, | |
716 | save_a0_no_merge | |
717 | } strategy; | |
b166356e | 718 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; |
719 | rtx reg; | |
b166356e | 720 | |
721 | /* We have several different strategies to save FP registers. | |
722 | We can store them using SP offsets, which is beneficial if | |
723 | there are just a few registers to save, or we can use `a0' in | |
724 | post-increment mode (`a0' is the only call-clobbered address | |
725 | register that is never used to pass information to a | |
726 | function). Furthermore, if we don't need a frame pointer, we | |
727 | can merge the two SP adds into a single one, but this isn't | |
728 | always beneficial; sometimes we can just split the two adds | |
729 | so that we don't exceed a 16-bit constant size. The code | |
730 | below will select which strategy to use, so as to generate | |
731 | smallest code. Ties are broken in favor or shorter sequences | |
732 | (in terms of number of instructions). */ | |
733 | ||
734 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
735 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
736 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
737 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
e14cac83 | 738 | |
739 | /* We add 0 * (S) in two places to promote to the type of S, | |
740 | so that all arms of the conditional have the same type. */ | |
b166356e | 741 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ |
e14cac83 | 742 | (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \ |
b166356e | 743 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ |
744 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
e14cac83 | 745 | : 0 * (S) + (ELSE)) |
b166356e | 746 | #define SIZE_FMOV_SP_(S,N) \ |
747 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
748 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
749 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
750 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
751 | ||
752 | /* Consider alternative save_sp_merge only if we don't need the | |
fa483857 | 753 | frame pointer and size is nonzero. */ |
b166356e | 754 | if (! frame_pointer_needed && size) |
755 | { | |
756 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
757 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
758 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
759 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
760 | ||
761 | if (this_strategy_size < strategy_size) | |
762 | { | |
763 | strategy = save_sp_merge; | |
764 | strategy_size = this_strategy_size; | |
765 | } | |
766 | } | |
767 | ||
768 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
769 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
770 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
771 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
772 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
773 | if (size) | |
774 | { | |
775 | /* Insn: add -size, sp. */ | |
776 | this_strategy_size += SIZE_ADD_SP (-size); | |
777 | } | |
778 | ||
779 | if (this_strategy_size < strategy_size) | |
780 | { | |
781 | strategy = save_sp_no_merge; | |
782 | strategy_size = this_strategy_size; | |
783 | } | |
784 | ||
785 | /* Consider alternative save_sp_partial_merge only if we don't | |
786 | need a frame pointer and size is reasonably large. */ | |
787 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
788 | { | |
789 | /* Insn: add -128, sp. */ | |
790 | this_strategy_size = SIZE_ADD_SP (-128); | |
791 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
792 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
793 | num_regs_to_save); | |
794 | if (size) | |
795 | { | |
796 | /* Insn: add 128-size, sp. */ | |
797 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
798 | } | |
799 | ||
800 | if (this_strategy_size < strategy_size) | |
801 | { | |
802 | strategy = save_sp_partial_merge; | |
803 | strategy_size = this_strategy_size; | |
804 | } | |
805 | } | |
806 | ||
807 | /* Consider alternative save_a0_merge only if we don't need a | |
fa483857 | 808 | frame pointer, size is nonzero and the user hasn't |
b166356e | 809 | changed the calling conventions of a0. */ |
810 | if (! frame_pointer_needed && size | |
d37e81ec | 811 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
b166356e | 812 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
813 | { | |
814 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
815 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
816 | /* Insn: mov sp, a0. */ | |
817 | this_strategy_size++; | |
818 | if (size) | |
819 | { | |
820 | /* Insn: add size, a0. */ | |
821 | this_strategy_size += SIZE_ADD_AX (size); | |
822 | } | |
823 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
824 | this_strategy_size += 3 * num_regs_to_save; | |
825 | ||
826 | if (this_strategy_size < strategy_size) | |
827 | { | |
828 | strategy = save_a0_merge; | |
829 | strategy_size = this_strategy_size; | |
830 | } | |
831 | } | |
832 | ||
833 | /* Consider alternative save_a0_no_merge if the user hasn't | |
09e5ce26 | 834 | changed the calling conventions of a0. */ |
d37e81ec | 835 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
b166356e | 836 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
837 | { | |
838 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
839 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
840 | /* Insn: mov sp, a0. */ | |
841 | this_strategy_size++; | |
842 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
843 | this_strategy_size += 3 * num_regs_to_save; | |
844 | if (size) | |
845 | { | |
846 | /* Insn: add -size, sp. */ | |
847 | this_strategy_size += SIZE_ADD_SP (-size); | |
848 | } | |
849 | ||
850 | if (this_strategy_size < strategy_size) | |
851 | { | |
852 | strategy = save_a0_no_merge; | |
853 | strategy_size = this_strategy_size; | |
854 | } | |
855 | } | |
856 | ||
857 | /* Emit the initial SP add, common to all strategies. */ | |
858 | switch (strategy) | |
859 | { | |
860 | case save_sp_no_merge: | |
861 | case save_a0_no_merge: | |
5f2853dd | 862 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
863 | stack_pointer_rtx, | |
864 | GEN_INT (-4 * num_regs_to_save)))); | |
b166356e | 865 | xsize = 0; |
866 | break; | |
867 | ||
868 | case save_sp_partial_merge: | |
5f2853dd | 869 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
870 | stack_pointer_rtx, | |
871 | GEN_INT (-128)))); | |
b166356e | 872 | xsize = 128 - 4 * num_regs_to_save; |
873 | size -= xsize; | |
874 | break; | |
875 | ||
876 | case save_sp_merge: | |
877 | case save_a0_merge: | |
5f2853dd | 878 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
879 | stack_pointer_rtx, | |
880 | GEN_INT (-(size + 4 * num_regs_to_save))))); | |
b166356e | 881 | /* We'll have to adjust FP register saves according to the |
09e5ce26 | 882 | frame size. */ |
b166356e | 883 | xsize = size; |
884 | /* Since we've already created the stack frame, don't do it | |
09e5ce26 | 885 | again at the end of the function. */ |
b166356e | 886 | size = 0; |
887 | break; | |
888 | ||
889 | default: | |
cf41bb03 | 890 | gcc_unreachable (); |
b166356e | 891 | } |
fb16c776 | 892 | |
b166356e | 893 | /* Now prepare register a0, if we have decided to use it. */ |
894 | switch (strategy) | |
895 | { | |
896 | case save_sp_merge: | |
897 | case save_sp_no_merge: | |
898 | case save_sp_partial_merge: | |
899 | reg = 0; | |
900 | break; | |
901 | ||
902 | case save_a0_merge: | |
903 | case save_a0_no_merge: | |
904 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
5f2853dd | 905 | F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); |
b166356e | 906 | if (xsize) |
5f2853dd | 907 | F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); |
b166356e | 908 | reg = gen_rtx_POST_INC (SImode, reg); |
909 | break; | |
fb16c776 | 910 | |
b166356e | 911 | default: |
cf41bb03 | 912 | gcc_unreachable (); |
b166356e | 913 | } |
fb16c776 | 914 | |
b166356e | 915 | /* Now actually save the FP registers. */ |
916 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 917 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
b166356e | 918 | { |
919 | rtx addr; | |
920 | ||
921 | if (reg) | |
922 | addr = reg; | |
923 | else | |
924 | { | |
925 | /* If we aren't using `a0', use an SP offset. */ | |
926 | if (xsize) | |
927 | { | |
928 | addr = gen_rtx_PLUS (SImode, | |
929 | stack_pointer_rtx, | |
930 | GEN_INT (xsize)); | |
931 | } | |
932 | else | |
933 | addr = stack_pointer_rtx; | |
fb16c776 | 934 | |
b166356e | 935 | xsize += 4; |
936 | } | |
937 | ||
5f2853dd | 938 | F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), |
939 | gen_rtx_REG (SFmode, i)))); | |
b166356e | 940 | } |
941 | } | |
942 | ||
48cb86e3 | 943 | /* Now put the frame pointer into the frame pointer register. */ |
29a404f9 | 944 | if (frame_pointer_needed) |
5f2853dd | 945 | F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); |
29a404f9 | 946 | |
48cb86e3 | 947 | /* Allocate stack for this frame. */ |
29a404f9 | 948 | if (size) |
5f2853dd | 949 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
950 | stack_pointer_rtx, | |
951 | GEN_INT (-size)))); | |
952 | ||
3072d30e | 953 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
954 | emit_insn (gen_GOTaddr2picreg ()); | |
29a404f9 | 955 | } |
956 | ||
957 | void | |
3626e955 | 958 | mn10300_expand_epilogue (void) |
29a404f9 | 959 | { |
e3f95b40 | 960 | HOST_WIDE_INT size; |
f1899bff | 961 | |
f1899bff | 962 | /* SIZE includes the fixed stack space needed for function calls. */ |
abe32cce | 963 | size = get_frame_size () + crtl->outgoing_args_size; |
964 | size += (crtl->outgoing_args_size ? 4 : 0); | |
5574dbdd | 965 | |
b166356e | 966 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
967 | { | |
968 | int num_regs_to_save = fp_regs_to_save (), i; | |
969 | rtx reg = 0; | |
970 | ||
971 | /* We have several options to restore FP registers. We could | |
972 | load them from SP offsets, but, if there are enough FP | |
973 | registers to restore, we win if we use a post-increment | |
974 | addressing mode. */ | |
975 | ||
976 | /* If we have a frame pointer, it's the best option, because we | |
977 | already know it has the value we want. */ | |
978 | if (frame_pointer_needed) | |
979 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
980 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
981 | it's never used for return values. But only do so if it's | |
982 | smaller than using SP offsets. */ | |
983 | else | |
984 | { | |
985 | enum { restore_sp_post_adjust, | |
986 | restore_sp_pre_adjust, | |
987 | restore_sp_partial_adjust, | |
988 | restore_a1 } strategy; | |
989 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
990 | ||
991 | /* Consider using sp offsets before adjusting sp. */ | |
992 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
993 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
994 | /* If size is too large, we'll have to adjust SP with an | |
995 | add. */ | |
996 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
997 | { | |
998 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
999 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1000 | } | |
1001 | /* If we don't have to restore any non-FP registers, | |
1002 | we'll be able to save one byte by using rets. */ | |
1003 | if (! REG_SAVE_BYTES) | |
1004 | this_strategy_size--; | |
1005 | ||
1006 | if (this_strategy_size < strategy_size) | |
1007 | { | |
1008 | strategy = restore_sp_post_adjust; | |
1009 | strategy_size = this_strategy_size; | |
1010 | } | |
1011 | ||
1012 | /* Consider using sp offsets after adjusting sp. */ | |
1013 | /* Insn: add size, sp. */ | |
1014 | this_strategy_size = SIZE_ADD_SP (size); | |
1015 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1016 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1017 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 1018 | save area, so, no savings. */ |
b166356e | 1019 | |
1020 | if (this_strategy_size < strategy_size) | |
1021 | { | |
1022 | strategy = restore_sp_pre_adjust; | |
1023 | strategy_size = this_strategy_size; | |
1024 | } | |
1025 | ||
1026 | /* Consider using sp offsets after partially adjusting sp. | |
1027 | When size is close to 32Kb, we may be able to adjust SP | |
1028 | with an imm16 add instruction while still using fmov | |
1029 | (d8,sp). */ | |
1030 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1031 | { | |
1032 | /* Insn: add size + 4 * num_regs_to_save | |
1033 | + REG_SAVE_BYTES - 252,sp. */ | |
1034 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1035 | + REG_SAVE_BYTES - 252); | |
1036 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1037 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1038 | - 4 * num_regs_to_save, | |
1039 | num_regs_to_save); | |
1040 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 1041 | save area, so, no savings. */ |
b166356e | 1042 | |
1043 | if (this_strategy_size < strategy_size) | |
1044 | { | |
1045 | strategy = restore_sp_partial_adjust; | |
1046 | strategy_size = this_strategy_size; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | /* Consider using a1 in post-increment mode, as long as the | |
1051 | user hasn't changed the calling conventions of a1. */ | |
d37e81ec | 1052 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
b166356e | 1053 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1054 | { | |
1055 | /* Insn: mov sp,a1. */ | |
1056 | this_strategy_size = 1; | |
1057 | if (size) | |
1058 | { | |
1059 | /* Insn: add size,a1. */ | |
1060 | this_strategy_size += SIZE_ADD_AX (size); | |
1061 | } | |
1062 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1063 | this_strategy_size += 3 * num_regs_to_save; | |
1064 | /* If size is large enough, we may be able to save a | |
1065 | couple of bytes. */ | |
1066 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1067 | { | |
1068 | /* Insn: mov a1,sp. */ | |
1069 | this_strategy_size += 2; | |
1070 | } | |
1071 | /* If we don't have to restore any non-FP registers, | |
1072 | we'll be able to save one byte by using rets. */ | |
1073 | if (! REG_SAVE_BYTES) | |
1074 | this_strategy_size--; | |
1075 | ||
1076 | if (this_strategy_size < strategy_size) | |
1077 | { | |
1078 | strategy = restore_a1; | |
1079 | strategy_size = this_strategy_size; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | switch (strategy) | |
1084 | { | |
1085 | case restore_sp_post_adjust: | |
1086 | break; | |
1087 | ||
1088 | case restore_sp_pre_adjust: | |
1089 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1090 | stack_pointer_rtx, | |
1091 | GEN_INT (size))); | |
1092 | size = 0; | |
1093 | break; | |
1094 | ||
1095 | case restore_sp_partial_adjust: | |
1096 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1097 | stack_pointer_rtx, | |
1098 | GEN_INT (size + 4 * num_regs_to_save | |
1099 | + REG_SAVE_BYTES - 252))); | |
1100 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1101 | break; | |
fb16c776 | 1102 | |
b166356e | 1103 | case restore_a1: |
1104 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1105 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1106 | if (size) | |
1107 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1108 | break; | |
1109 | ||
1110 | default: | |
cf41bb03 | 1111 | gcc_unreachable (); |
b166356e | 1112 | } |
1113 | } | |
1114 | ||
1115 | /* Adjust the selected register, if any, for post-increment. */ | |
1116 | if (reg) | |
1117 | reg = gen_rtx_POST_INC (SImode, reg); | |
1118 | ||
1119 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 1120 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
b166356e | 1121 | { |
1122 | rtx addr; | |
fb16c776 | 1123 | |
b166356e | 1124 | if (reg) |
1125 | addr = reg; | |
1126 | else if (size) | |
1127 | { | |
1128 | /* If we aren't using a post-increment register, use an | |
09e5ce26 | 1129 | SP offset. */ |
b166356e | 1130 | addr = gen_rtx_PLUS (SImode, |
1131 | stack_pointer_rtx, | |
1132 | GEN_INT (size)); | |
1133 | } | |
1134 | else | |
1135 | addr = stack_pointer_rtx; | |
1136 | ||
1137 | size += 4; | |
1138 | ||
5f2853dd | 1139 | emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), |
1140 | gen_rtx_MEM (SFmode, addr))); | |
b166356e | 1141 | } |
1142 | ||
1143 | /* If we were using the restore_a1 strategy and the number of | |
1144 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1145 | to `sp', to avoid having to use `add' to adjust it. */ | |
1146 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1147 | { | |
1148 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1149 | size = 0; | |
1150 | } | |
1151 | } | |
1152 | ||
461cabcc | 1153 | /* Maybe cut back the stack, except for the register save area. |
1154 | ||
1155 | If the frame pointer exists, then use the frame pointer to | |
1156 | cut back the stack. | |
1157 | ||
1158 | If the stack size + register save area is more than 255 bytes, | |
1159 | then the stack must be cut back here since the size + register | |
fb16c776 | 1160 | save size is too big for a ret/retf instruction. |
461cabcc | 1161 | |
1162 | Else leave it alone, it will be cut back as part of the | |
1163 | ret/retf instruction, or there wasn't any stack to begin with. | |
1164 | ||
dfd1079d | 1165 | Under no circumstances should the register save area be |
461cabcc | 1166 | deallocated here, that would leave a window where an interrupt |
1167 | could occur and trash the register save area. */ | |
29a404f9 | 1168 | if (frame_pointer_needed) |
1169 | { | |
29a404f9 | 1170 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
b21218d6 | 1171 | size = 0; |
1172 | } | |
55daf463 | 1173 | else if (size + REG_SAVE_BYTES > 255) |
b21218d6 | 1174 | { |
1175 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1176 | stack_pointer_rtx, | |
1177 | GEN_INT (size))); | |
1178 | size = 0; | |
29a404f9 | 1179 | } |
29a404f9 | 1180 | |
55daf463 | 1181 | /* Adjust the stack and restore callee-saved registers, if any. */ |
3072d30e | 1182 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1183 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1184 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1185 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
48cb86e3 | 1186 | || frame_pointer_needed) |
55daf463 | 1187 | emit_jump_insn (gen_return_internal_regs |
1188 | (GEN_INT (size + REG_SAVE_BYTES))); | |
48cb86e3 | 1189 | else |
55daf463 | 1190 | emit_jump_insn (gen_return_internal ()); |
29a404f9 | 1191 | } |
1192 | ||
a2f10574 | 1193 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
4caa3669 | 1194 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1195 | parallel. If OP is a multiple store, return a mask indicating which | |
1196 | registers it saves. Return 0 otherwise. */ | |
1197 | ||
1198 | int | |
3626e955 | 1199 | mn10300_store_multiple_operation (rtx op, |
1200 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
4caa3669 | 1201 | { |
1202 | int count; | |
1203 | int mask; | |
1204 | int i; | |
1205 | unsigned int last; | |
1206 | rtx elt; | |
1207 | ||
1208 | count = XVECLEN (op, 0); | |
1209 | if (count < 2) | |
1210 | return 0; | |
1211 | ||
1212 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1213 | elt = XVECEXP (op, 0, 0); | |
1214 | if (GET_CODE (elt) != SET | |
3626e955 | 1215 | || (! REG_P (SET_DEST (elt))) |
4caa3669 | 1216 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM |
1217 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1218 | return 0; | |
1219 | ||
1220 | /* Check that A is the stack pointer and B is the expected stack size. | |
1221 | For OP to match, each subsequent instruction should push a word onto | |
1222 | the stack. We therefore expect the first instruction to create | |
09e5ce26 | 1223 | COUNT-1 stack slots. */ |
4caa3669 | 1224 | elt = SET_SRC (elt); |
3626e955 | 1225 | if ((! REG_P (XEXP (elt, 0))) |
4caa3669 | 1226 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
3626e955 | 1227 | || (! CONST_INT_P (XEXP (elt, 1))) |
4caa3669 | 1228 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) |
1229 | return 0; | |
1230 | ||
1231 | /* Now go through the rest of the vector elements. They must be | |
1232 | ordered so that the first instruction stores the highest-numbered | |
1233 | register to the highest stack slot and that subsequent instructions | |
1234 | store a lower-numbered register to the slot below. | |
1235 | ||
1236 | LAST keeps track of the smallest-numbered register stored so far. | |
09e5ce26 | 1237 | MASK is the set of stored registers. */ |
b166356e | 1238 | last = LAST_EXTENDED_REGNUM + 1; |
4caa3669 | 1239 | mask = 0; |
1240 | for (i = 1; i < count; i++) | |
1241 | { | |
09e5ce26 | 1242 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
4caa3669 | 1243 | elt = XVECEXP (op, 0, i); |
1244 | if (GET_CODE (elt) != SET | |
3626e955 | 1245 | || (! MEM_P (SET_DEST (elt))) |
1246 | || (! REG_P (SET_SRC (elt))) | |
4caa3669 | 1247 | || REGNO (SET_SRC (elt)) >= last) |
1248 | return 0; | |
1249 | ||
1250 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
09e5ce26 | 1251 | case if the rest of the instruction has a flaw. */ |
4caa3669 | 1252 | last = REGNO (SET_SRC (elt)); |
1253 | mask |= (1 << last); | |
1254 | ||
1255 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1256 | elt = XEXP (SET_DEST (elt), 0); | |
1257 | if (GET_CODE (elt) != PLUS | |
3626e955 | 1258 | || (! REG_P (XEXP (elt, 0))) |
4caa3669 | 1259 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
3626e955 | 1260 | || (! CONST_INT_P (XEXP (elt, 1))) |
4caa3669 | 1261 | || INTVAL (XEXP (elt, 1)) != -i * 4) |
1262 | return 0; | |
1263 | } | |
1264 | ||
09e5ce26 | 1265 | /* All or none of the callee-saved extended registers must be in the set. */ |
4caa3669 | 1266 | if ((mask & 0x3c000) != 0 |
1267 | && (mask & 0x3c000) != 0x3c000) | |
1268 | return 0; | |
1269 | ||
1270 | return mask; | |
1271 | } | |
1272 | ||
29a404f9 | 1273 | /* What (if any) secondary registers are needed to move IN with mode |
8deb3959 | 1274 | MODE into a register in register class RCLASS. |
29a404f9 | 1275 | |
1276 | We might be able to simplify this. */ | |
3626e955 | 1277 | |
29a404f9 | 1278 | enum reg_class |
8deb3959 | 1279 | mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode, |
51149d85 | 1280 | rtx in) |
29a404f9 | 1281 | { |
8b8be022 | 1282 | rtx inner = in; |
1283 | ||
1284 | /* Strip off any SUBREG expressions from IN. Basically we want | |
1285 | to know if IN is a pseudo or (subreg (pseudo)) as those can | |
1286 | turn into MEMs during reload. */ | |
1287 | while (GET_CODE (inner) == SUBREG) | |
1288 | inner = SUBREG_REG (inner); | |
1289 | ||
29a404f9 | 1290 | /* Memory loads less than a full word wide can't have an |
1291 | address or stack pointer destination. They must use | |
1292 | a data register as an intermediate register. */ | |
4879b320 | 1293 | if ((MEM_P (in) |
1294 | || (REG_P (inner) | |
8b8be022 | 1295 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER)) |
29a404f9 | 1296 | && (mode == QImode || mode == HImode) |
8deb3959 | 1297 | && (rclass == ADDRESS_REGS || rclass == SP_REGS |
1298 | || rclass == SP_OR_ADDRESS_REGS)) | |
8ecf154e | 1299 | { |
911517ac | 1300 | if (TARGET_AM33) |
1301 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1302 | return DATA_REGS; |
1303 | } | |
29a404f9 | 1304 | |
1305 | /* We can't directly load sp + const_int into a data register; | |
1306 | we must use an address register as an intermediate. */ | |
8deb3959 | 1307 | if (rclass != SP_REGS |
1308 | && rclass != ADDRESS_REGS | |
1309 | && rclass != SP_OR_ADDRESS_REGS | |
1310 | && rclass != SP_OR_EXTENDED_REGS | |
1311 | && rclass != ADDRESS_OR_EXTENDED_REGS | |
1312 | && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
29a404f9 | 1313 | && (in == stack_pointer_rtx |
1314 | || (GET_CODE (in) == PLUS | |
48cb86e3 | 1315 | && (XEXP (in, 0) == stack_pointer_rtx |
1316 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
29a404f9 | 1317 | return ADDRESS_REGS; |
1318 | ||
8b8be022 | 1319 | if (TARGET_AM33_2 |
1320 | && rclass == FP_REGS) | |
b166356e | 1321 | { |
8b8be022 | 1322 | /* We can't load directly into an FP register from a |
1323 | constant address. */ | |
4879b320 | 1324 | if (MEM_P (in) |
8b8be022 | 1325 | && CONSTANT_ADDRESS_P (XEXP (in, 0))) |
5574dbdd | 1326 | return DATA_OR_EXTENDED_REGS; |
8b8be022 | 1327 | |
1328 | /* Handle case were a pseudo may not get a hard register | |
1329 | but has an equivalent memory location defined. */ | |
4879b320 | 1330 | if (REG_P (inner) |
8b8be022 | 1331 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER |
1332 | && reg_equiv_mem [REGNO (inner)] | |
1333 | && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0))) | |
5574dbdd | 1334 | return DATA_OR_EXTENDED_REGS; |
b166356e | 1335 | } |
1336 | ||
48cb86e3 | 1337 | /* Otherwise assume no secondary reloads are needed. */ |
1338 | return NO_REGS; | |
1339 | } | |
1340 | ||
1341 | int | |
3626e955 | 1342 | mn10300_initial_offset (int from, int to) |
48cb86e3 | 1343 | { |
f1899bff | 1344 | /* The difference between the argument pointer and the frame pointer |
1345 | is the size of the callee register save area. */ | |
48cb86e3 | 1346 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
29a404f9 | 1347 | { |
3072d30e | 1348 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1349 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1350 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1351 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
b166356e | 1352 | || fp_regs_to_save () |
48cb86e3 | 1353 | || frame_pointer_needed) |
b166356e | 1354 | return REG_SAVE_BYTES |
1355 | + 4 * fp_regs_to_save (); | |
48cb86e3 | 1356 | else |
bb4959a8 | 1357 | return 0; |
29a404f9 | 1358 | } |
1359 | ||
f1899bff | 1360 | /* The difference between the argument pointer and the stack pointer is |
1361 | the sum of the size of this function's frame, the callee register save | |
1362 | area, and the fixed stack space needed for function calls (if any). */ | |
48cb86e3 | 1363 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1364 | { | |
3072d30e | 1365 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1366 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1367 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1368 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
b166356e | 1369 | || fp_regs_to_save () |
48cb86e3 | 1370 | || frame_pointer_needed) |
8ecf154e | 1371 | return (get_frame_size () + REG_SAVE_BYTES |
b166356e | 1372 | + 4 * fp_regs_to_save () |
abe32cce | 1373 | + (crtl->outgoing_args_size |
1374 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1375 | else |
36ed4406 | 1376 | return (get_frame_size () |
abe32cce | 1377 | + (crtl->outgoing_args_size |
1378 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1379 | } |
29a404f9 | 1380 | |
f1899bff | 1381 | /* The difference between the frame pointer and stack pointer is the sum |
1382 | of the size of this function's frame and the fixed stack space needed | |
1383 | for function calls (if any). */ | |
48cb86e3 | 1384 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
36ed4406 | 1385 | return (get_frame_size () |
abe32cce | 1386 | + (crtl->outgoing_args_size |
1387 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1388 | |
cf41bb03 | 1389 | gcc_unreachable (); |
29a404f9 | 1390 | } |
bb4959a8 | 1391 | |
6644435d | 1392 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1393 | ||
f2d49d02 | 1394 | static bool |
fb80456a | 1395 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
f2d49d02 | 1396 | { |
1397 | /* Return values > 8 bytes in length in memory. */ | |
00b1da0e | 1398 | return (int_size_in_bytes (type) > 8 |
1399 | || int_size_in_bytes (type) == 0 | |
1400 | || TYPE_MODE (type) == BLKmode); | |
f2d49d02 | 1401 | } |
1402 | ||
bb4959a8 | 1403 | /* Flush the argument registers to the stack for a stdarg function; |
1404 | return the new argument pointer. */ | |
f2d49d02 | 1405 | static rtx |
3285410a | 1406 | mn10300_builtin_saveregs (void) |
bb4959a8 | 1407 | { |
ed554036 | 1408 | rtx offset, mem; |
bb4959a8 | 1409 | tree fntype = TREE_TYPE (current_function_decl); |
257d99c3 | 1410 | int argadj = ((!stdarg_p (fntype)) |
bb4959a8 | 1411 | ? UNITS_PER_WORD : 0); |
32c2fdea | 1412 | alias_set_type set = get_varargs_alias_set (); |
bb4959a8 | 1413 | |
1414 | if (argadj) | |
abe32cce | 1415 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
bb4959a8 | 1416 | else |
abe32cce | 1417 | offset = crtl->args.arg_offset_rtx; |
bb4959a8 | 1418 | |
abe32cce | 1419 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ab6ab77e | 1420 | set_mem_alias_set (mem, set); |
ed554036 | 1421 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1422 | ||
1423 | mem = gen_rtx_MEM (SImode, | |
abe32cce | 1424 | plus_constant (crtl->args.internal_arg_pointer, 4)); |
ab6ab77e | 1425 | set_mem_alias_set (mem, set); |
ed554036 | 1426 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1427 | ||
bb4959a8 | 1428 | return copy_to_reg (expand_binop (Pmode, add_optab, |
abe32cce | 1429 | crtl->args.internal_arg_pointer, |
bb4959a8 | 1430 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1431 | } | |
1432 | ||
8a58ed0a | 1433 | static void |
3285410a | 1434 | mn10300_va_start (tree valist, rtx nextarg) |
ed554036 | 1435 | { |
7ccc713a | 1436 | nextarg = expand_builtin_saveregs (); |
7df226a2 | 1437 | std_expand_builtin_va_start (valist, nextarg); |
ed554036 | 1438 | } |
1439 | ||
b981d932 | 1440 | /* Return true when a parameter should be passed by reference. */ |
1441 | ||
1442 | static bool | |
1443 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
fb80456a | 1444 | enum machine_mode mode, const_tree type, |
b981d932 | 1445 | bool named ATTRIBUTE_UNUSED) |
1446 | { | |
1447 | unsigned HOST_WIDE_INT size; | |
1448 | ||
1449 | if (type) | |
1450 | size = int_size_in_bytes (type); | |
1451 | else | |
1452 | size = GET_MODE_SIZE (mode); | |
1453 | ||
00b1da0e | 1454 | return (size > 8 || size == 0); |
b981d932 | 1455 | } |
1456 | ||
bb4959a8 | 1457 | /* Return an RTX to represent where a value with mode MODE will be returned |
e92d3ba8 | 1458 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
bb4959a8 | 1459 | |
dc67179a | 1460 | static rtx |
3626e955 | 1461 | mn10300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
dc67179a | 1462 | const_tree type, bool named ATTRIBUTE_UNUSED) |
bb4959a8 | 1463 | { |
e92d3ba8 | 1464 | rtx result = NULL_RTX; |
e14cac83 | 1465 | int size; |
bb4959a8 | 1466 | |
1467 | /* We only support using 2 data registers as argument registers. */ | |
1468 | int nregs = 2; | |
1469 | ||
1470 | /* Figure out the size of the object to be passed. */ | |
1471 | if (mode == BLKmode) | |
1472 | size = int_size_in_bytes (type); | |
1473 | else | |
1474 | size = GET_MODE_SIZE (mode); | |
1475 | ||
bb4959a8 | 1476 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1477 | ||
1478 | /* Don't pass this arg via a register if all the argument registers | |
1479 | are used up. */ | |
1480 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
e92d3ba8 | 1481 | return result; |
bb4959a8 | 1482 | |
1483 | /* Don't pass this arg via a register if it would be split between | |
1484 | registers and memory. */ | |
1485 | if (type == NULL_TREE | |
1486 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
e92d3ba8 | 1487 | return result; |
bb4959a8 | 1488 | |
1489 | switch (cum->nbytes / UNITS_PER_WORD) | |
1490 | { | |
1491 | case 0: | |
e92d3ba8 | 1492 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
bb4959a8 | 1493 | break; |
1494 | case 1: | |
e92d3ba8 | 1495 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
bb4959a8 | 1496 | break; |
1497 | default: | |
e92d3ba8 | 1498 | break; |
bb4959a8 | 1499 | } |
1500 | ||
1501 | return result; | |
1502 | } | |
1503 | ||
dc67179a | 1504 | /* Update the data in CUM to advance over an argument |
1505 | of mode MODE and data type TYPE. | |
1506 | (TYPE is null for libcalls where that information may not be available.) */ | |
1507 | ||
1508 | static void | |
1509 | mn10300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1510 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
1511 | { | |
1512 | cum->nbytes += (mode != BLKmode | |
1513 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1514 | : (int_size_in_bytes (type) + 3) & ~3); | |
1515 | } | |
1516 | ||
f054eb3c | 1517 | /* Return the number of bytes of registers to use for an argument passed |
1518 | partially in registers and partially in memory. */ | |
bb4959a8 | 1519 | |
f054eb3c | 1520 | static int |
1521 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1522 | tree type, bool named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1523 | { |
e14cac83 | 1524 | int size; |
bb4959a8 | 1525 | |
1526 | /* We only support using 2 data registers as argument registers. */ | |
1527 | int nregs = 2; | |
1528 | ||
1529 | /* Figure out the size of the object to be passed. */ | |
1530 | if (mode == BLKmode) | |
1531 | size = int_size_in_bytes (type); | |
1532 | else | |
1533 | size = GET_MODE_SIZE (mode); | |
1534 | ||
bb4959a8 | 1535 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1536 | ||
1537 | /* Don't pass this arg via a register if all the argument registers | |
1538 | are used up. */ | |
1539 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1540 | return 0; | |
1541 | ||
1542 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1543 | return 0; | |
1544 | ||
1545 | /* Don't pass this arg via a register if it would be split between | |
1546 | registers and memory. */ | |
1547 | if (type == NULL_TREE | |
1548 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1549 | return 0; | |
1550 | ||
f054eb3c | 1551 | return nregs * UNITS_PER_WORD - cum->nbytes; |
bb4959a8 | 1552 | } |
1553 | ||
00b1da0e | 1554 | /* Return the location of the function's value. This will be either |
1555 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1556 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1557 | we only return the PARALLEL for outgoing values; we do not want | |
1558 | callers relying on this extra copy. */ | |
1559 | ||
b6713ba6 | 1560 | static rtx |
1561 | mn10300_function_value (const_tree valtype, | |
1562 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1563 | bool outgoing) | |
00b1da0e | 1564 | { |
1565 | rtx rv; | |
1566 | enum machine_mode mode = TYPE_MODE (valtype); | |
1567 | ||
1568 | if (! POINTER_TYPE_P (valtype)) | |
1569 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1570 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
18d50ae6 | 1571 | || cfun->returns_struct) |
00b1da0e | 1572 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1573 | ||
1574 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1575 | XVECEXP (rv, 0, 0) | |
1576 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1577 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1578 | GEN_INT (0)); | |
fb16c776 | 1579 | |
00b1da0e | 1580 | XVECEXP (rv, 0, 1) |
1581 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1582 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1583 | GEN_INT (0)); | |
1584 | return rv; | |
1585 | } | |
1586 | ||
b6713ba6 | 1587 | /* Implements TARGET_LIBCALL_VALUE. */ |
1588 | ||
1589 | static rtx | |
1590 | mn10300_libcall_value (enum machine_mode mode, | |
1591 | const_rtx fun ATTRIBUTE_UNUSED) | |
1592 | { | |
1593 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1594 | } | |
1595 | ||
1596 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1597 | ||
1598 | bool | |
1599 | mn10300_function_value_regno_p (const unsigned int regno) | |
1600 | { | |
1601 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1602 | } | |
1603 | ||
5574dbdd | 1604 | /* Output a compare insn. */ |
1605 | ||
feb9af9f | 1606 | const char * |
5574dbdd | 1607 | mn10300_output_cmp (rtx operand, rtx insn) |
bb4959a8 | 1608 | { |
bb4959a8 | 1609 | rtx temp; |
1610 | int past_call = 0; | |
1611 | ||
1612 | /* We can save a byte if we can find a register which has the value | |
1613 | zero in it. */ | |
1614 | temp = PREV_INSN (insn); | |
6e90c6cd | 1615 | while (optimize && temp) |
bb4959a8 | 1616 | { |
1617 | rtx set; | |
1618 | ||
1619 | /* We allow the search to go through call insns. We record | |
1620 | the fact that we've past a CALL_INSN and reject matches which | |
1621 | use call clobbered registers. */ | |
3626e955 | 1622 | if (LABEL_P (temp) |
1623 | || JUMP_P (temp) | |
bb4959a8 | 1624 | || GET_CODE (temp) == BARRIER) |
1625 | break; | |
1626 | ||
3626e955 | 1627 | if (CALL_P (temp)) |
bb4959a8 | 1628 | past_call = 1; |
1629 | ||
1630 | if (GET_CODE (temp) == NOTE) | |
1631 | { | |
1632 | temp = PREV_INSN (temp); | |
1633 | continue; | |
1634 | } | |
1635 | ||
09e5ce26 | 1636 | /* It must be an insn, see if it is a simple set. */ |
bb4959a8 | 1637 | set = single_set (temp); |
1638 | if (!set) | |
1639 | { | |
1640 | temp = PREV_INSN (temp); | |
1641 | continue; | |
1642 | } | |
1643 | ||
1644 | /* Are we setting a data register to zero (this does not win for | |
fb16c776 | 1645 | address registers)? |
bb4959a8 | 1646 | |
1647 | If it's a call clobbered register, have we past a call? | |
1648 | ||
1649 | Make sure the register we find isn't the same as ourself; | |
8ecf154e | 1650 | the mn10300 can't encode that. |
1651 | ||
1652 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1653 | so the code to detect calls here isn't doing anything useful. */ | |
bb4959a8 | 1654 | if (REG_P (SET_DEST (set)) |
1655 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1656 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
6e90c6cd | 1657 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1658 | == REGNO_REG_CLASS (REGNO (operand))) | |
911517ac | 1659 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1660 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
fb16c776 | 1661 | && (!past_call |
d37e81ec | 1662 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
911517ac | 1663 | { |
1664 | rtx xoperands[2]; | |
1665 | xoperands[0] = operand; | |
1666 | xoperands[1] = SET_DEST (set); | |
1667 | ||
1668 | output_asm_insn ("cmp %1,%0", xoperands); | |
1669 | return ""; | |
1670 | } | |
1671 | ||
1672 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1673 | && REG_P (SET_DEST (set)) | |
1674 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1675 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1676 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1677 | != REGNO_REG_CLASS (REGNO (operand))) | |
1678 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
bb4959a8 | 1679 | && REGNO (SET_DEST (set)) != REGNO (operand) |
fb16c776 | 1680 | && (!past_call |
d37e81ec | 1681 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
bb4959a8 | 1682 | { |
1683 | rtx xoperands[2]; | |
1684 | xoperands[0] = operand; | |
1685 | xoperands[1] = SET_DEST (set); | |
1686 | ||
1687 | output_asm_insn ("cmp %1,%0", xoperands); | |
1688 | return ""; | |
1689 | } | |
1690 | temp = PREV_INSN (temp); | |
1691 | } | |
1692 | return "cmp 0,%0"; | |
1693 | } | |
36ed4406 | 1694 | |
9d3b5b5e | 1695 | /* Similarly, but when using a zero_extract pattern for a btst where |
1696 | the source operand might end up in memory. */ | |
1697 | int | |
3626e955 | 1698 | mn10300_mask_ok_for_mem_btst (int len, int bit) |
9d3b5b5e | 1699 | { |
805e22b2 | 1700 | unsigned int mask = 0; |
9d3b5b5e | 1701 | |
1702 | while (len > 0) | |
1703 | { | |
1704 | mask |= (1 << bit); | |
1705 | bit++; | |
1706 | len--; | |
1707 | } | |
1708 | ||
1709 | /* MASK must bit into an 8bit value. */ | |
1710 | return (((mask & 0xff) == mask) | |
1711 | || ((mask & 0xff00) == mask) | |
1712 | || ((mask & 0xff0000) == mask) | |
1713 | || ((mask & 0xff000000) == mask)); | |
1714 | } | |
1715 | ||
c4cd8f6a | 1716 | /* Return 1 if X contains a symbolic expression. We know these |
1717 | expressions will have one of a few well defined forms, so | |
1718 | we need only check those forms. */ | |
3626e955 | 1719 | |
c4cd8f6a | 1720 | int |
3626e955 | 1721 | mn10300_symbolic_operand (rtx op, |
1722 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1723 | { |
1724 | switch (GET_CODE (op)) | |
1725 | { | |
1726 | case SYMBOL_REF: | |
1727 | case LABEL_REF: | |
1728 | return 1; | |
1729 | case CONST: | |
1730 | op = XEXP (op, 0); | |
1731 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1732 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
4879b320 | 1733 | && CONST_INT_P (XEXP (op, 1))); |
c4cd8f6a | 1734 | default: |
1735 | return 0; | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | /* Try machine dependent ways of modifying an illegitimate address | |
1740 | to be legitimate. If we find one, return the new valid address. | |
1741 | This macro is used in only one place: `memory_address' in explow.c. | |
1742 | ||
1743 | OLDX is the address as it was before break_out_memory_refs was called. | |
1744 | In some cases it is useful to look at this to decide what needs to be done. | |
1745 | ||
c4cd8f6a | 1746 | Normally it is always safe for this macro to do nothing. It exists to |
1747 | recognize opportunities to optimize the output. | |
1748 | ||
1749 | But on a few ports with segmented architectures and indexed addressing | |
1750 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
3626e955 | 1751 | |
5574dbdd | 1752 | static rtx |
41e3a0c7 | 1753 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1754 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1755 | { |
3626e955 | 1756 | if (flag_pic && ! mn10300_legitimate_pic_operand_p (x)) |
1757 | x = mn10300_legitimize_pic_address (oldx, NULL_RTX); | |
b87a151a | 1758 | |
c4cd8f6a | 1759 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1760 | special handling to avoid creating an indexed memory address | |
1761 | with x-100000 as the base. */ | |
1762 | if (GET_CODE (x) == PLUS | |
3626e955 | 1763 | && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode)) |
c4cd8f6a | 1764 | { |
1765 | /* Ugly. We modify things here so that the address offset specified | |
1766 | by the index expression is computed first, then added to x to form | |
1767 | the entire address. */ | |
1768 | ||
59086782 | 1769 | rtx regx1, regy1, regy2, y; |
c4cd8f6a | 1770 | |
1771 | /* Strip off any CONST. */ | |
1772 | y = XEXP (x, 1); | |
1773 | if (GET_CODE (y) == CONST) | |
1774 | y = XEXP (y, 0); | |
1775 | ||
c927a8ab | 1776 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1777 | { | |
1778 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1779 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1780 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1781 | regx1 = force_reg (Pmode, | |
3626e955 | 1782 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, |
1783 | regy2)); | |
7014838c | 1784 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
c927a8ab | 1785 | } |
c4cd8f6a | 1786 | } |
11b4605c | 1787 | return x; |
c4cd8f6a | 1788 | } |
e2aead91 | 1789 | |
b87a151a | 1790 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
09e5ce26 | 1791 | @GOTOFF in `reg'. */ |
3626e955 | 1792 | |
b87a151a | 1793 | rtx |
3626e955 | 1794 | mn10300_legitimize_pic_address (rtx orig, rtx reg) |
b87a151a | 1795 | { |
1796 | if (GET_CODE (orig) == LABEL_REF | |
1797 | || (GET_CODE (orig) == SYMBOL_REF | |
1798 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1799 | || ! MN10300_GLOBAL_P (orig)))) | |
1800 | { | |
1801 | if (reg == 0) | |
1802 | reg = gen_reg_rtx (Pmode); | |
1803 | ||
1804 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1805 | return reg; | |
1806 | } | |
1807 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1808 | { | |
1809 | if (reg == 0) | |
1810 | reg = gen_reg_rtx (Pmode); | |
1811 | ||
1812 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1813 | return reg; | |
1814 | } | |
1815 | return orig; | |
1816 | } | |
1817 | ||
1818 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
fa483857 | 1819 | isn't protected by a PIC unspec; nonzero otherwise. */ |
3626e955 | 1820 | |
b87a151a | 1821 | int |
3626e955 | 1822 | mn10300_legitimate_pic_operand_p (rtx x) |
b87a151a | 1823 | { |
3626e955 | 1824 | const char *fmt; |
1825 | int i; | |
b87a151a | 1826 | |
1827 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1828 | return 0; | |
1829 | ||
1830 | if (GET_CODE (x) == UNSPEC | |
1831 | && (XINT (x, 1) == UNSPEC_PIC | |
1832 | || XINT (x, 1) == UNSPEC_GOT | |
1833 | || XINT (x, 1) == UNSPEC_GOTOFF | |
b6e3379c | 1834 | || XINT (x, 1) == UNSPEC_PLT |
1835 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
b87a151a | 1836 | return 1; |
1837 | ||
b87a151a | 1838 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1839 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1840 | { | |
1841 | if (fmt[i] == 'E') | |
1842 | { | |
5574dbdd | 1843 | int j; |
b87a151a | 1844 | |
1845 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3626e955 | 1846 | if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j))) |
b87a151a | 1847 | return 0; |
1848 | } | |
3626e955 | 1849 | else if (fmt[i] == 'e' |
1850 | && ! mn10300_legitimate_pic_operand_p (XEXP (x, i))) | |
b87a151a | 1851 | return 0; |
1852 | } | |
1853 | ||
1854 | return 1; | |
1855 | } | |
1856 | ||
5411aa8c | 1857 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
fd50b071 | 1858 | legitimate, and FALSE otherwise. |
1859 | ||
1860 | On the mn10300, the value in the address register must be | |
1861 | in the same memory space/segment as the effective address. | |
1862 | ||
1863 | This is problematical for reload since it does not understand | |
1864 | that base+index != index+base in a memory reference. | |
1865 | ||
1866 | Note it is still possible to use reg+reg addressing modes, | |
1867 | it's just much more difficult. For a discussion of a possible | |
1868 | workaround and solution, see the comments in pa.c before the | |
1869 | function record_unscaled_index_insn_codes. */ | |
1870 | ||
5574dbdd | 1871 | static bool |
fd50b071 | 1872 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
5411aa8c | 1873 | { |
1874 | if (CONSTANT_ADDRESS_P (x) | |
3626e955 | 1875 | && (! flag_pic || mn10300_legitimate_pic_operand_p (x))) |
5411aa8c | 1876 | return TRUE; |
1877 | ||
1878 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1879 | return TRUE; | |
1880 | ||
1881 | if (TARGET_AM33 | |
1882 | && GET_CODE (x) == POST_INC | |
1883 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1884 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1885 | return TRUE; | |
1886 | ||
1887 | if (GET_CODE (x) == PLUS) | |
1888 | { | |
1889 | rtx base = 0, index = 0; | |
1890 | ||
1891 | if (REG_P (XEXP (x, 0)) | |
1892 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1893 | { | |
1894 | base = XEXP (x, 0); | |
1895 | index = XEXP (x, 1); | |
1896 | } | |
1897 | ||
1898 | if (REG_P (XEXP (x, 1)) | |
1899 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1900 | { | |
1901 | base = XEXP (x, 1); | |
1902 | index = XEXP (x, 0); | |
1903 | } | |
1904 | ||
1905 | if (base != 0 && index != 0) | |
1906 | { | |
4879b320 | 1907 | if (CONST_INT_P (index)) |
5411aa8c | 1908 | return TRUE; |
1909 | if (GET_CODE (index) == CONST | |
9247cc1c | 1910 | && GET_CODE (XEXP (index, 0)) != PLUS |
5411aa8c | 1911 | && (! flag_pic |
3626e955 | 1912 | || (mn10300_legitimate_pic_operand_p (index) |
5574dbdd | 1913 | && GET_MODE_SIZE (mode) == 4))) |
5411aa8c | 1914 | return TRUE; |
1915 | } | |
1916 | } | |
1917 | ||
1918 | return FALSE; | |
1919 | } | |
1920 | ||
5574dbdd | 1921 | /* Used by LEGITIMATE_CONSTANT_P(). Returns TRUE if X is a valid |
1922 | constant. Note that some "constants" aren't valid, such as TLS | |
1923 | symbols and unconverted GOT-based references, so we eliminate | |
1924 | those here. */ | |
1925 | ||
1926 | bool | |
1927 | mn10300_legitimate_constant_p (rtx x) | |
1928 | { | |
1929 | switch (GET_CODE (x)) | |
1930 | { | |
1931 | case CONST: | |
1932 | x = XEXP (x, 0); | |
1933 | ||
1934 | if (GET_CODE (x) == PLUS) | |
1935 | { | |
3626e955 | 1936 | if (! CONST_INT_P (XEXP (x, 1))) |
5574dbdd | 1937 | return false; |
1938 | x = XEXP (x, 0); | |
1939 | } | |
1940 | ||
1941 | /* Only some unspecs are valid as "constants". */ | |
1942 | if (GET_CODE (x) == UNSPEC) | |
1943 | { | |
5574dbdd | 1944 | switch (XINT (x, 1)) |
1945 | { | |
1946 | case UNSPEC_INT_LABEL: | |
1947 | case UNSPEC_PIC: | |
1948 | case UNSPEC_GOT: | |
1949 | case UNSPEC_GOTOFF: | |
1950 | case UNSPEC_PLT: | |
1951 | return true; | |
1952 | default: | |
1953 | return false; | |
1954 | } | |
1955 | } | |
1956 | ||
1957 | /* We must have drilled down to a symbol. */ | |
3626e955 | 1958 | if (! mn10300_symbolic_operand (x, Pmode)) |
5574dbdd | 1959 | return false; |
1960 | break; | |
1961 | ||
1962 | default: | |
1963 | break; | |
1964 | } | |
1965 | ||
1966 | return true; | |
1967 | } | |
1968 | ||
ec0457a8 | 1969 | static int |
db65aa2c | 1970 | mn10300_address_cost_1 (rtx x, int *unsig) |
e2aead91 | 1971 | { |
e2aead91 | 1972 | switch (GET_CODE (x)) |
1973 | { | |
1974 | case REG: | |
1975 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1976 | { | |
1977 | case SP_REGS: | |
1978 | *unsig = 1; | |
1979 | return 0; | |
1980 | ||
1981 | case ADDRESS_REGS: | |
1982 | return 1; | |
1983 | ||
1984 | case DATA_REGS: | |
1985 | case EXTENDED_REGS: | |
b166356e | 1986 | case FP_REGS: |
e2aead91 | 1987 | return 3; |
1988 | ||
1989 | case NO_REGS: | |
1990 | return 5; | |
1991 | ||
1992 | default: | |
cf41bb03 | 1993 | gcc_unreachable (); |
e2aead91 | 1994 | } |
1995 | ||
1996 | case PLUS: | |
1997 | case MINUS: | |
cbe23f2f | 1998 | case ASHIFT: |
1999 | case AND: | |
e2aead91 | 2000 | case IOR: |
ec0457a8 | 2001 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
2002 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
e2aead91 | 2003 | |
2004 | case EXPR_LIST: | |
2005 | case SUBREG: | |
2006 | case MEM: | |
db65aa2c | 2007 | return mn10300_address_cost (XEXP (x, 0), !optimize_size); |
e2aead91 | 2008 | |
2009 | case ZERO_EXTEND: | |
2010 | *unsig = 1; | |
ec0457a8 | 2011 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
e2aead91 | 2012 | |
2013 | case CONST_INT: | |
2014 | if (INTVAL (x) == 0) | |
2015 | return 0; | |
2016 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
2017 | return 1; | |
2018 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
2019 | return 3; | |
2020 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
2021 | return 5; | |
2022 | return 7; | |
2023 | ||
2024 | case CONST: | |
2025 | case SYMBOL_REF: | |
cbe23f2f | 2026 | case LABEL_REF: |
e2aead91 | 2027 | return 8; |
2028 | ||
e2aead91 | 2029 | default: |
cf41bb03 | 2030 | gcc_unreachable (); |
e2aead91 | 2031 | |
2032 | } | |
2033 | } | |
fab7adbf | 2034 | |
ec0457a8 | 2035 | static int |
f529eb25 | 2036 | mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
ec0457a8 | 2037 | { |
2038 | int s = 0; | |
2039 | return mn10300_address_cost_1 (x, &s); | |
2040 | } | |
2041 | ||
fab7adbf | 2042 | static bool |
3626e955 | 2043 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, |
2044 | bool speed ATTRIBUTE_UNUSED) | |
fab7adbf | 2045 | { |
2046 | switch (code) | |
2047 | { | |
2048 | case CONST_INT: | |
2049 | /* Zeros are extremely cheap. */ | |
74f4459c | 2050 | if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE)) |
fab7adbf | 2051 | *total = 0; |
2052 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
2053 | else if (INT_8_BITS (INTVAL (x))) | |
2054 | *total = 1; | |
2055 | /* This is the "base" cost, includes constants where either the | |
2056 | upper or lower 16bits are all zeros. */ | |
2057 | else if (INT_16_BITS (INTVAL (x)) | |
2058 | || (INTVAL (x) & 0xffff) == 0 | |
2059 | || (INTVAL (x) & 0xffff0000) == 0) | |
2060 | *total = 2; | |
2061 | else | |
2062 | *total = 4; | |
2063 | return true; | |
2064 | ||
2065 | case CONST: | |
2066 | case LABEL_REF: | |
2067 | case SYMBOL_REF: | |
2068 | /* These are more costly than a CONST_INT, but we can relax them, | |
2069 | so they're less costly than a CONST_DOUBLE. */ | |
2070 | *total = 6; | |
2071 | return true; | |
2072 | ||
2073 | case CONST_DOUBLE: | |
2074 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2075 | so their cost is very high. */ | |
2076 | *total = 8; | |
2077 | return true; | |
2078 | ||
74f4459c | 2079 | case ZERO_EXTRACT: |
2080 | /* This is cheap, we can use btst. */ | |
2081 | if (outer_code == COMPARE) | |
2082 | *total = 0; | |
2083 | return false; | |
2084 | ||
fab7adbf | 2085 | /* ??? This probably needs more work. */ |
2086 | case MOD: | |
2087 | case DIV: | |
2088 | case MULT: | |
2089 | *total = 8; | |
2090 | return true; | |
2091 | ||
2092 | default: | |
2093 | return false; | |
2094 | } | |
2095 | } | |
8935d57c | 2096 | |
2097 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2098 | use a clr instruction. The code here must be kept in sync with | |
2099 | movdf and movdi. */ | |
2100 | ||
2101 | bool | |
3285410a | 2102 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
8935d57c | 2103 | { |
5f2853dd | 2104 | long val[2] = {0, 0}; |
8935d57c | 2105 | |
4879b320 | 2106 | if ((! REG_P (operands[0])) |
8935d57c | 2107 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) |
2108 | return false; | |
2109 | ||
2110 | switch (GET_CODE (operands[1])) | |
2111 | { | |
2112 | case CONST_INT: | |
2113 | { | |
2114 | rtx low, high; | |
2115 | split_double (operands[1], &low, &high); | |
2116 | val[0] = INTVAL (low); | |
2117 | val[1] = INTVAL (high); | |
2118 | } | |
2119 | break; | |
fb16c776 | 2120 | |
8935d57c | 2121 | case CONST_DOUBLE: |
2122 | if (GET_MODE (operands[1]) == DFmode) | |
2123 | { | |
2124 | REAL_VALUE_TYPE rv; | |
2125 | ||
2126 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2127 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2128 | } | |
2129 | else if (GET_MODE (operands[1]) == VOIDmode | |
2130 | || GET_MODE (operands[1]) == DImode) | |
2131 | { | |
2132 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2133 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2134 | } | |
2135 | break; | |
fb16c776 | 2136 | |
8935d57c | 2137 | default: |
2138 | return false; | |
2139 | } | |
2140 | ||
2141 | return val[0] == 0 || val[1] == 0; | |
2142 | } | |
b87a151a | 2143 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2144 | may access it using GOTOFF instead of GOT. */ | |
2145 | ||
2146 | static void | |
48ed5fc2 | 2147 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
b87a151a | 2148 | { |
2149 | rtx symbol; | |
2150 | ||
3626e955 | 2151 | if (! MEM_P (rtl)) |
b87a151a | 2152 | return; |
2153 | symbol = XEXP (rtl, 0); | |
2154 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2155 | return; | |
2156 | ||
2157 | if (flag_pic) | |
2158 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2159 | } | |
906bb5c3 | 2160 | |
2161 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2162 | and readonly data size. So we crank up the case threshold value to | |
2163 | encourage a series of if/else comparisons to implement many small switch | |
2164 | statements. In theory, this value could be increased much more if we | |
2165 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2166 | serious code efficiency lossage. */ | |
2167 | ||
5574dbdd | 2168 | static unsigned int |
2169 | mn10300_case_values_threshold (void) | |
906bb5c3 | 2170 | { |
2171 | return 6; | |
2172 | } | |
3e16f982 | 2173 | |
2174 | /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */ | |
2175 | ||
2176 | static void | |
2177 | mn10300_asm_trampoline_template (FILE *f) | |
2178 | { | |
2179 | fprintf (f, "\tadd -4,sp\n"); | |
2180 | fprintf (f, "\t.long 0x0004fffa\n"); | |
2181 | fprintf (f, "\tmov (0,sp),a0\n"); | |
2182 | fprintf (f, "\tadd 4,sp\n"); | |
2183 | fprintf (f, "\tmov (13,a0),a1\n"); | |
2184 | fprintf (f, "\tmov (17,a0),a0\n"); | |
2185 | fprintf (f, "\tjmp (a0)\n"); | |
2186 | fprintf (f, "\t.long 0\n"); | |
2187 | fprintf (f, "\t.long 0\n"); | |
2188 | } | |
2189 | ||
2190 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ | |
2191 | ||
2192 | static void | |
2193 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2194 | { | |
2195 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2196 | rtx mem; | |
2197 | ||
2198 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2199 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2200 | ||
2201 | mem = adjust_address (m_tramp, SImode, 0x14); | |
2202 | emit_move_insn (mem, chain_value); | |
2203 | mem = adjust_address (m_tramp, SImode, 0x18); | |
2204 | emit_move_insn (mem, fnaddr); | |
2205 | } | |
e92d3ba8 | 2206 | |
2207 | /* Output the assembler code for a C++ thunk function. | |
2208 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2209 | is the decl for the target function. DELTA is an immediate constant | |
2210 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2211 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2212 | additionally added to THIS. Finally jump to the entry point of | |
2213 | FUNCTION. */ | |
2214 | ||
2215 | static void | |
2216 | mn10300_asm_output_mi_thunk (FILE * file, | |
2217 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2218 | HOST_WIDE_INT delta, | |
2219 | HOST_WIDE_INT vcall_offset, | |
2220 | tree function) | |
2221 | { | |
2222 | const char * _this; | |
2223 | ||
2224 | /* Get the register holding the THIS parameter. Handle the case | |
2225 | where there is a hidden first argument for a returned structure. */ | |
2226 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2227 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2228 | else | |
2229 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2230 | ||
2231 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2232 | ||
2233 | if (delta) | |
2234 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2235 | ||
2236 | if (vcall_offset) | |
2237 | { | |
2238 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2239 | ||
2240 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2241 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2242 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2243 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2244 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2245 | } | |
2246 | ||
2247 | fputs ("\tjmp ", file); | |
2248 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2249 | putc ('\n', file); | |
2250 | } | |
2251 | ||
2252 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2253 | assembler code for the thunk function specified by the arguments | |
2254 | it is passed, and false otherwise. */ | |
2255 | ||
2256 | static bool | |
2257 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2258 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2259 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2260 | const_tree function ATTRIBUTE_UNUSED) | |
2261 | { | |
2262 | return true; | |
2263 | } | |
5574dbdd | 2264 | |
2265 | bool | |
2266 | mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) | |
2267 | { | |
2268 | if (REGNO_REG_CLASS (regno) == FP_REGS | |
2269 | || REGNO_REG_CLASS (regno) == FP_ACC_REGS) | |
2270 | /* Do not store integer values in FP registers. */ | |
2271 | return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0); | |
2272 | ||
2273 | if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4) | |
2274 | return true; | |
2275 | ||
2276 | if (REGNO_REG_CLASS (regno) == DATA_REGS | |
2277 | || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS) | |
2278 | || REGNO_REG_CLASS (regno) == EXTENDED_REGS) | |
2279 | return GET_MODE_SIZE (mode) <= 4; | |
2280 | ||
2281 | return false; | |
2282 | } | |
2283 | ||
2284 | bool | |
2285 | mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2) | |
2286 | { | |
2287 | if (GET_MODE_CLASS (mode1) == MODE_FLOAT | |
2288 | && GET_MODE_CLASS (mode2) != MODE_FLOAT) | |
2289 | return false; | |
2290 | ||
2291 | if (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
2292 | && GET_MODE_CLASS (mode1) != MODE_FLOAT) | |
2293 | return false; | |
2294 | ||
2295 | if (TARGET_AM33 | |
2296 | || mode1 == mode2 | |
2297 | || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4)) | |
2298 | return true; | |
2299 | ||
2300 | return false; | |
2301 | } | |
2302 | ||
2303 | enum machine_mode | |
2304 | mn10300_select_cc_mode (rtx x) | |
2305 | { | |
2306 | return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode; | |
2307 | } | |
4879b320 | 2308 | |
2309 | static inline bool | |
2310 | is_load_insn (rtx insn) | |
2311 | { | |
2312 | if (GET_CODE (PATTERN (insn)) != SET) | |
2313 | return false; | |
2314 | ||
2315 | return MEM_P (SET_SRC (PATTERN (insn))); | |
2316 | } | |
2317 | ||
2318 | static inline bool | |
2319 | is_store_insn (rtx insn) | |
2320 | { | |
2321 | if (GET_CODE (PATTERN (insn)) != SET) | |
2322 | return false; | |
2323 | ||
2324 | return MEM_P (SET_DEST (PATTERN (insn))); | |
2325 | } | |
2326 | ||
2327 | /* Update scheduling costs for situations that cannot be | |
2328 | described using the attributes and DFA machinery. | |
2329 | DEP is the insn being scheduled. | |
2330 | INSN is the previous insn. | |
2331 | COST is the current cycle cost for DEP. */ | |
2332 | ||
2333 | static int | |
2334 | mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost) | |
2335 | { | |
2336 | int timings = get_attr_timings (insn); | |
2337 | ||
2338 | if (!TARGET_AM33) | |
2339 | return 1; | |
2340 | ||
2341 | if (GET_CODE (insn) == PARALLEL) | |
2342 | insn = XVECEXP (insn, 0, 0); | |
2343 | ||
2344 | if (GET_CODE (dep) == PARALLEL) | |
2345 | dep = XVECEXP (dep, 0, 0); | |
2346 | ||
2347 | /* For the AM34 a load instruction that follows a | |
2348 | store instruction incurs an extra cycle of delay. */ | |
2349 | if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2350 | && is_load_insn (dep) | |
2351 | && is_store_insn (insn)) | |
2352 | cost += 1; | |
2353 | ||
2354 | /* For the AM34 a non-store, non-branch FPU insn that follows | |
2355 | another FPU insn incurs a one cycle throughput increase. */ | |
2356 | else if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2357 | && ! is_store_insn (insn) | |
2358 | && ! JUMP_P (insn) | |
2359 | && GET_CODE (PATTERN (dep)) == SET | |
2360 | && GET_CODE (PATTERN (insn)) == SET | |
2361 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT | |
2362 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | |
2363 | cost += 1; | |
2364 | ||
2365 | /* Resolve the conflict described in section 1-7-4 of | |
2366 | Chapter 3 of the MN103E Series Instruction Manual | |
2367 | where it says: | |
2368 | ||
2369 | "When the preceeding instruction is a CPU load or | |
2370 | store instruction, a following FPU instruction | |
2371 | cannot be executed until the CPU completes the | |
2372 | latency period even though there are no register | |
2373 | or flag dependencies between them." */ | |
2374 | ||
2375 | /* Only the AM33-2 (and later) CPUs have FPU instructions. */ | |
2376 | if (! TARGET_AM33_2) | |
2377 | return cost; | |
2378 | ||
2379 | /* If a data dependence already exists then the cost is correct. */ | |
2380 | if (REG_NOTE_KIND (link) == 0) | |
2381 | return cost; | |
2382 | ||
2383 | /* Check that the instruction about to scheduled is an FPU instruction. */ | |
2384 | if (GET_CODE (PATTERN (dep)) != SET) | |
2385 | return cost; | |
2386 | ||
2387 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT) | |
2388 | return cost; | |
2389 | ||
2390 | /* Now check to see if the previous instruction is a load or store. */ | |
2391 | if (! is_load_insn (insn) && ! is_store_insn (insn)) | |
2392 | return cost; | |
2393 | ||
2394 | /* XXX: Verify: The text of 1-7-4 implies that the restriction | |
2395 | only applies when an INTEGER load/store preceeds an FPU | |
2396 | instruction, but is this true ? For now we assume that it is. */ | |
2397 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT) | |
2398 | return cost; | |
2399 | ||
2400 | /* Extract the latency value from the timings attribute. */ | |
2401 | return timings < 100 ? (timings % 10) : (timings % 100); | |
2402 | } | |
5574dbdd | 2403 | \f |
3626e955 | 2404 | /* Initialize the GCC target structure. */ |
2405 | ||
2406 | #undef TARGET_EXCEPT_UNWIND_INFO | |
2407 | #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info | |
2408 | ||
2409 | #undef TARGET_ASM_ALIGNED_HI_OP | |
2410 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
2411 | ||
2412 | #undef TARGET_LEGITIMIZE_ADDRESS | |
2413 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
2414 | ||
2415 | #undef TARGET_RTX_COSTS | |
2416 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
2417 | #undef TARGET_ADDRESS_COST | |
2418 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
2419 | ||
2420 | #undef TARGET_ASM_FILE_START | |
2421 | #define TARGET_ASM_FILE_START mn10300_file_start | |
2422 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
2423 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
2424 | ||
2425 | #undef TARGET_DEFAULT_TARGET_FLAGS | |
2426 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 | |
2427 | #undef TARGET_HANDLE_OPTION | |
2428 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
2429 | #undef TARGET_OPTION_OVERRIDE | |
2430 | #define TARGET_OPTION_OVERRIDE mn10300_option_override | |
c17f64cc | 2431 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
2432 | #define TARGET_OPTION_OPTIMIZATION_TABLE mn10300_option_optimization_table | |
3626e955 | 2433 | |
2434 | #undef TARGET_ENCODE_SECTION_INFO | |
2435 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
2436 | ||
2437 | #undef TARGET_PROMOTE_PROTOTYPES | |
2438 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
2439 | #undef TARGET_RETURN_IN_MEMORY | |
2440 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
2441 | #undef TARGET_PASS_BY_REFERENCE | |
2442 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
2443 | #undef TARGET_CALLEE_COPIES | |
2444 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
2445 | #undef TARGET_ARG_PARTIAL_BYTES | |
2446 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
dc67179a | 2447 | #undef TARGET_FUNCTION_ARG |
2448 | #define TARGET_FUNCTION_ARG mn10300_function_arg | |
2449 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
2450 | #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance | |
3626e955 | 2451 | |
2452 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
2453 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
2454 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
2455 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
2456 | ||
2457 | #undef TARGET_CASE_VALUES_THRESHOLD | |
2458 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
2459 | ||
2460 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
2461 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
2462 | ||
2463 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
2464 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template | |
2465 | #undef TARGET_TRAMPOLINE_INIT | |
2466 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
2467 | ||
2468 | #undef TARGET_FUNCTION_VALUE | |
2469 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
2470 | #undef TARGET_LIBCALL_VALUE | |
2471 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
2472 | ||
2473 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
2474 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
2475 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
2476 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
2477 | ||
4879b320 | 2478 | #undef TARGET_SCHED_ADJUST_COST |
2479 | #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost | |
2480 | ||
3626e955 | 2481 | struct gcc_target targetm = TARGET_INITIALIZER; |