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29a404f9 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
59086782 | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. |
29a404f9 | 3 | Contributed by Jeff Law (law@cygnus.com). |
4 | ||
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
29a404f9 | 22 | #include "config.h" |
7014838c | 23 | #include "system.h" |
29a404f9 | 24 | #include "rtl.h" |
4faf81b8 | 25 | #include "tree.h" |
29a404f9 | 26 | #include "regs.h" |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
4faf81b8 | 37 | #include "function.h" |
29a404f9 | 38 | #include "obstack.h" |
59086782 | 39 | #include "toplev.h" |
40 | #include "tm_p.h" | |
29a404f9 | 41 | |
8ecf154e | 42 | /* The size of the callee register save area. Right now we save everything |
43 | on entry since it costs us nothing in code size. It does cost us from a | |
44 | speed standpoint, so we want to optimize this sooner or later. */ | |
3bcd7b00 | 45 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
46 | + 4 * regs_ever_live[3] \ | |
911517ac | 47 | + 4 * regs_ever_live[6] \ |
48 | + 4 * regs_ever_live[7] \ | |
49 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
50 | || regs_ever_live[16] || regs_ever_live[17])) | |
8ecf154e | 51 | |
29a404f9 | 52 | void |
53 | asm_file_start (file) | |
54 | FILE *file; | |
55 | { | |
56 | fprintf (file, "#\tGCC For the Matsushita MN10300\n"); | |
57 | if (optimize) | |
58 | fprintf (file, "# -O%d\n", optimize); | |
59 | else | |
60 | fprintf (file, "\n\n"); | |
911517ac | 61 | |
62 | if (TARGET_AM33) | |
63 | fprintf (file, "\t.am33\n"); | |
29a404f9 | 64 | output_file_directive (file, main_input_filename); |
65 | } | |
66 | \f | |
67 | ||
29a404f9 | 68 | /* Print operand X using operand code CODE to assembly language output file |
69 | FILE. */ | |
70 | ||
71 | void | |
72 | print_operand (file, x, code) | |
73 | FILE *file; | |
74 | rtx x; | |
75 | int code; | |
76 | { | |
77 | switch (code) | |
78 | { | |
79 | case 'b': | |
80 | case 'B': | |
81 | /* These are normal and reversed branches. */ | |
82 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
83 | { | |
84 | case NE: | |
85 | fprintf (file, "ne"); | |
86 | break; | |
87 | case EQ: | |
88 | fprintf (file, "eq"); | |
89 | break; | |
90 | case GE: | |
91 | fprintf (file, "ge"); | |
92 | break; | |
93 | case GT: | |
94 | fprintf (file, "gt"); | |
95 | break; | |
96 | case LE: | |
97 | fprintf (file, "le"); | |
98 | break; | |
99 | case LT: | |
100 | fprintf (file, "lt"); | |
101 | break; | |
102 | case GEU: | |
103 | fprintf (file, "cc"); | |
104 | break; | |
105 | case GTU: | |
106 | fprintf (file, "hi"); | |
107 | break; | |
108 | case LEU: | |
109 | fprintf (file, "ls"); | |
110 | break; | |
111 | case LTU: | |
112 | fprintf (file, "cs"); | |
113 | break; | |
114 | default: | |
115 | abort (); | |
116 | } | |
117 | break; | |
118 | case 'C': | |
119 | /* This is used for the operand to a call instruction; | |
120 | if it's a REG, enclose it in parens, else output | |
121 | the operand normally. */ | |
122 | if (GET_CODE (x) == REG) | |
123 | { | |
124 | fputc ('(', file); | |
125 | print_operand (file, x, 0); | |
126 | fputc (')', file); | |
127 | } | |
128 | else | |
129 | print_operand (file, x, 0); | |
130 | break; | |
131 | ||
6ce19398 | 132 | /* These are the least significant word in a 64bit value. */ |
133 | case 'L': | |
134 | switch (GET_CODE (x)) | |
135 | { | |
136 | case MEM: | |
137 | fputc ('(', file); | |
138 | output_address (XEXP (x, 0)); | |
139 | fputc (')', file); | |
140 | break; | |
141 | ||
142 | case REG: | |
143 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
144 | break; | |
145 | ||
146 | case SUBREG: | |
147 | fprintf (file, "%s", | |
148 | reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); | |
149 | break; | |
150 | ||
151 | case CONST_DOUBLE: | |
152 | { | |
153 | long val[2]; | |
154 | REAL_VALUE_TYPE rv; | |
155 | ||
156 | switch (GET_MODE (x)) | |
157 | { | |
158 | case DFmode: | |
159 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
160 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 161 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 162 | break;; |
163 | case SFmode: | |
164 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
165 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
ad3c0f03 | 166 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 167 | break;; |
168 | case VOIDmode: | |
169 | case DImode: | |
170 | print_operand_address (file, | |
171 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
172 | break; | |
59086782 | 173 | default: |
174 | break; | |
6ce19398 | 175 | } |
176 | break; | |
177 | } | |
178 | ||
179 | case CONST_INT: | |
964d057c | 180 | { |
181 | rtx low, high; | |
182 | split_double (x, &low, &high); | |
183 | fprintf (file, "%ld", (long)INTVAL (low)); | |
184 | break; | |
185 | } | |
6ce19398 | 186 | |
187 | default: | |
188 | abort (); | |
189 | } | |
190 | break; | |
191 | ||
192 | /* Similarly, but for the most significant word. */ | |
193 | case 'H': | |
194 | switch (GET_CODE (x)) | |
195 | { | |
196 | case MEM: | |
197 | fputc ('(', file); | |
198 | x = adj_offsettable_operand (x, 4); | |
199 | output_address (XEXP (x, 0)); | |
200 | fputc (')', file); | |
201 | break; | |
202 | ||
203 | case REG: | |
204 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
205 | break; | |
206 | ||
207 | case SUBREG: | |
208 | fprintf (file, "%s", | |
209 | reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1); | |
210 | break; | |
211 | ||
212 | case CONST_DOUBLE: | |
213 | { | |
214 | long val[2]; | |
215 | REAL_VALUE_TYPE rv; | |
216 | ||
217 | switch (GET_MODE (x)) | |
218 | { | |
219 | case DFmode: | |
220 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
221 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 222 | fprintf (file, "0x%lx", val[1]); |
6ce19398 | 223 | break;; |
224 | case SFmode: | |
225 | abort (); | |
226 | case VOIDmode: | |
227 | case DImode: | |
228 | print_operand_address (file, | |
229 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
230 | break; | |
59086782 | 231 | default: |
232 | break; | |
6ce19398 | 233 | } |
234 | break; | |
235 | } | |
236 | ||
237 | case CONST_INT: | |
964d057c | 238 | { |
239 | rtx low, high; | |
240 | split_double (x, &low, &high); | |
241 | fprintf (file, "%ld", (long)INTVAL (high)); | |
242 | break; | |
243 | } | |
244 | ||
6ce19398 | 245 | default: |
246 | abort (); | |
247 | } | |
248 | break; | |
249 | ||
250 | case 'A': | |
251 | fputc ('(', file); | |
252 | if (GET_CODE (XEXP (x, 0)) == REG) | |
7014838c | 253 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0))); |
6ce19398 | 254 | else |
255 | output_address (XEXP (x, 0)); | |
256 | fputc (')', file); | |
257 | break; | |
258 | ||
167fa942 | 259 | case 'N': |
260 | output_address (GEN_INT ((~INTVAL (x)) & 0xff)); | |
261 | break; | |
262 | ||
63e678f2 | 263 | /* For shift counts. The hardware ignores the upper bits of |
264 | any immediate, but the assembler will flag an out of range | |
265 | shift count as an error. So we mask off the high bits | |
266 | of the immediate here. */ | |
267 | case 'S': | |
268 | if (GET_CODE (x) == CONST_INT) | |
269 | { | |
270 | fprintf (file, "%d", INTVAL (x) & 0x1f); | |
271 | break; | |
272 | } | |
273 | /* FALL THROUGH */ | |
274 | ||
29a404f9 | 275 | default: |
276 | switch (GET_CODE (x)) | |
277 | { | |
278 | case MEM: | |
279 | fputc ('(', file); | |
280 | output_address (XEXP (x, 0)); | |
281 | fputc (')', file); | |
282 | break; | |
283 | ||
6ce19398 | 284 | case PLUS: |
285 | output_address (x); | |
286 | break; | |
287 | ||
29a404f9 | 288 | case REG: |
289 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
290 | break; | |
291 | ||
292 | case SUBREG: | |
293 | fprintf (file, "%s", | |
294 | reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); | |
295 | break; | |
296 | ||
6ce19398 | 297 | /* This will only be single precision.... */ |
298 | case CONST_DOUBLE: | |
299 | { | |
300 | unsigned long val; | |
301 | REAL_VALUE_TYPE rv; | |
302 | ||
303 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
304 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
ad3c0f03 | 305 | fprintf (file, "0x%lx", val); |
6ce19398 | 306 | break; |
307 | } | |
308 | ||
29a404f9 | 309 | case CONST_INT: |
310 | case SYMBOL_REF: | |
311 | case CONST: | |
312 | case LABEL_REF: | |
313 | case CODE_LABEL: | |
314 | print_operand_address (file, x); | |
315 | break; | |
316 | default: | |
317 | abort (); | |
318 | } | |
319 | break; | |
320 | } | |
321 | } | |
322 | ||
323 | /* Output assembly language output for the address ADDR to FILE. */ | |
324 | ||
325 | void | |
326 | print_operand_address (file, addr) | |
327 | FILE *file; | |
328 | rtx addr; | |
329 | { | |
330 | switch (GET_CODE (addr)) | |
331 | { | |
911517ac | 332 | case POST_INC: |
333 | print_operand_address (file, XEXP (addr, 0)); | |
334 | fputc ('+', file); | |
335 | break; | |
29a404f9 | 336 | case REG: |
49fd1b62 | 337 | print_operand (file, addr, 0); |
29a404f9 | 338 | break; |
339 | case PLUS: | |
340 | { | |
341 | rtx base, index; | |
342 | if (REG_P (XEXP (addr, 0)) | |
343 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
344 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
345 | else if (REG_P (XEXP (addr, 1)) | |
346 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
347 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
348 | else | |
349 | abort (); | |
350 | print_operand (file, index, 0); | |
351 | fputc (',', file); | |
352 | print_operand (file, base, 0);; | |
353 | break; | |
354 | } | |
355 | case SYMBOL_REF: | |
356 | output_addr_const (file, addr); | |
357 | break; | |
358 | default: | |
359 | output_addr_const (file, addr); | |
360 | break; | |
361 | } | |
362 | } | |
363 | ||
6ce19398 | 364 | int |
365 | can_use_return_insn () | |
366 | { | |
36ed4406 | 367 | /* size includes the fixed stack space needed for function calls. */ |
368 | int size = get_frame_size () + current_function_outgoing_args_size; | |
369 | ||
370 | /* And space for the return pointer. */ | |
371 | size += current_function_outgoing_args_size ? 4 : 0; | |
6ce19398 | 372 | |
373 | return (reload_completed | |
374 | && size == 0 | |
375 | && !regs_ever_live[2] | |
376 | && !regs_ever_live[3] | |
377 | && !regs_ever_live[6] | |
378 | && !regs_ever_live[7] | |
911517ac | 379 | && !regs_ever_live[14] |
380 | && !regs_ever_live[15] | |
381 | && !regs_ever_live[16] | |
382 | && !regs_ever_live[17] | |
6ce19398 | 383 | && !frame_pointer_needed); |
384 | } | |
385 | ||
29a404f9 | 386 | void |
387 | expand_prologue () | |
388 | { | |
e3f95b40 | 389 | HOST_WIDE_INT size; |
f1899bff | 390 | |
f1899bff | 391 | /* SIZE includes the fixed stack space needed for function calls. */ |
36ed4406 | 392 | size = get_frame_size () + current_function_outgoing_args_size; |
393 | size += (current_function_outgoing_args_size ? 4 : 0); | |
29a404f9 | 394 | |
bb4959a8 | 395 | /* If this is an old-style varargs function, then its arguments |
396 | need to be flushed back to the stack. */ | |
397 | if (current_function_varargs) | |
398 | { | |
7014838c | 399 | emit_move_insn (gen_rtx_MEM (SImode, |
400 | plus_constant (stack_pointer_rtx, 4)), | |
401 | gen_rtx_REG (SImode, 0)); | |
402 | emit_move_insn (gen_rtx_MEM (SImode, | |
403 | plus_constant (stack_pointer_rtx, 8)), | |
404 | gen_rtx_REG (SImode, 1)); | |
bb4959a8 | 405 | } |
406 | ||
48cb86e3 | 407 | /* And now store all the registers onto the stack with a |
408 | single two byte instruction. */ | |
409 | if (regs_ever_live[2] || regs_ever_live[3] | |
410 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 411 | || regs_ever_live[14] || regs_ever_live[15] |
412 | || regs_ever_live[16] || regs_ever_live[17] | |
48cb86e3 | 413 | || frame_pointer_needed) |
414 | emit_insn (gen_store_movm ()); | |
415 | ||
416 | /* Now put the frame pointer into the frame pointer register. */ | |
29a404f9 | 417 | if (frame_pointer_needed) |
014546df | 418 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
29a404f9 | 419 | |
48cb86e3 | 420 | /* Allocate stack for this frame. */ |
29a404f9 | 421 | if (size) |
422 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
423 | stack_pointer_rtx, | |
424 | GEN_INT (-size))); | |
425 | } | |
426 | ||
427 | void | |
428 | expand_epilogue () | |
429 | { | |
e3f95b40 | 430 | HOST_WIDE_INT size; |
f1899bff | 431 | |
f1899bff | 432 | /* SIZE includes the fixed stack space needed for function calls. */ |
36ed4406 | 433 | size = get_frame_size () + current_function_outgoing_args_size; |
434 | size += (current_function_outgoing_args_size ? 4 : 0); | |
29a404f9 | 435 | |
461cabcc | 436 | /* Maybe cut back the stack, except for the register save area. |
437 | ||
438 | If the frame pointer exists, then use the frame pointer to | |
439 | cut back the stack. | |
440 | ||
441 | If the stack size + register save area is more than 255 bytes, | |
442 | then the stack must be cut back here since the size + register | |
443 | save size is too big for a ret/retf instruction. | |
444 | ||
445 | Else leave it alone, it will be cut back as part of the | |
446 | ret/retf instruction, or there wasn't any stack to begin with. | |
447 | ||
448 | Under no circumstanes should the register save area be | |
449 | deallocated here, that would leave a window where an interrupt | |
450 | could occur and trash the register save area. */ | |
29a404f9 | 451 | if (frame_pointer_needed) |
452 | { | |
29a404f9 | 453 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
b21218d6 | 454 | size = 0; |
455 | } | |
55daf463 | 456 | else if (size + REG_SAVE_BYTES > 255) |
b21218d6 | 457 | { |
458 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
459 | stack_pointer_rtx, | |
460 | GEN_INT (size))); | |
461 | size = 0; | |
29a404f9 | 462 | } |
29a404f9 | 463 | |
55daf463 | 464 | /* Adjust the stack and restore callee-saved registers, if any. */ |
465 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
48cb86e3 | 466 | || regs_ever_live[6] || regs_ever_live[7] |
911517ac | 467 | || regs_ever_live[14] || regs_ever_live[15] |
468 | || regs_ever_live[16] || regs_ever_live[17] | |
48cb86e3 | 469 | || frame_pointer_needed) |
55daf463 | 470 | emit_jump_insn (gen_return_internal_regs |
471 | (GEN_INT (size + REG_SAVE_BYTES))); | |
48cb86e3 | 472 | else |
55daf463 | 473 | emit_jump_insn (gen_return_internal ()); |
29a404f9 | 474 | } |
475 | ||
476 | /* Update the condition code from the insn. */ | |
477 | ||
478 | void | |
479 | notice_update_cc (body, insn) | |
480 | rtx body; | |
481 | rtx insn; | |
482 | { | |
29a404f9 | 483 | switch (get_attr_cc (insn)) |
484 | { | |
485 | case CC_NONE: | |
486 | /* Insn does not affect CC at all. */ | |
487 | break; | |
488 | ||
489 | case CC_NONE_0HIT: | |
490 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
491 | if (cc_status.value1 != 0 | |
ed420a25 | 492 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
29a404f9 | 493 | cc_status.value1 = 0; |
494 | break; | |
495 | ||
14058057 | 496 | case CC_SET_ZN: |
ed420a25 | 497 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
14058057 | 498 | V,C are unusable. */ |
29a404f9 | 499 | CC_STATUS_INIT; |
14058057 | 500 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
ed420a25 | 501 | cc_status.value1 = recog_data.operand[0]; |
29a404f9 | 502 | break; |
503 | ||
14058057 | 504 | case CC_SET_ZNV: |
ed420a25 | 505 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
14058057 | 506 | C is unusable. */ |
45e3d109 | 507 | CC_STATUS_INIT; |
14058057 | 508 | cc_status.flags |= CC_NO_CARRY; |
ed420a25 | 509 | cc_status.value1 = recog_data.operand[0]; |
45e3d109 | 510 | break; |
511 | ||
29a404f9 | 512 | case CC_COMPARE: |
513 | /* The insn is a compare instruction. */ | |
514 | CC_STATUS_INIT; | |
515 | cc_status.value1 = SET_SRC (body); | |
516 | break; | |
517 | ||
952e42d8 | 518 | case CC_INVERT: |
519 | /* The insn is a compare instruction. */ | |
520 | CC_STATUS_INIT; | |
521 | cc_status.value1 = SET_SRC (body); | |
522 | cc_status.flags |= CC_INVERTED; | |
523 | break; | |
524 | ||
29a404f9 | 525 | case CC_CLOBBER: |
526 | /* Insn doesn't leave CC in a usable state. */ | |
527 | CC_STATUS_INIT; | |
528 | break; | |
45e3d109 | 529 | |
530 | default: | |
531 | abort (); | |
29a404f9 | 532 | } |
29a404f9 | 533 | } |
534 | ||
535 | /* Return true if OP is a valid call operand. */ | |
536 | ||
537 | int | |
538 | call_address_operand (op, mode) | |
539 | rtx op; | |
59086782 | 540 | enum machine_mode mode ATTRIBUTE_UNUSED; |
29a404f9 | 541 | { |
542 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); | |
543 | } | |
544 | ||
545 | /* What (if any) secondary registers are needed to move IN with mode | |
dc3d02df | 546 | MODE into a register in register class CLASS. |
29a404f9 | 547 | |
548 | We might be able to simplify this. */ | |
549 | enum reg_class | |
550 | secondary_reload_class (class, mode, in) | |
551 | enum reg_class class; | |
552 | enum machine_mode mode; | |
553 | rtx in; | |
554 | { | |
29a404f9 | 555 | /* Memory loads less than a full word wide can't have an |
556 | address or stack pointer destination. They must use | |
557 | a data register as an intermediate register. */ | |
79ea832f | 558 | if ((GET_CODE (in) == MEM |
559 | || (GET_CODE (in) == REG | |
560 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
561 | || (GET_CODE (in) == SUBREG | |
562 | && GET_CODE (SUBREG_REG (in)) == REG | |
563 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
29a404f9 | 564 | && (mode == QImode || mode == HImode) |
79ea832f | 565 | && (class == ADDRESS_REGS || class == SP_REGS |
b0ba03a6 | 566 | || class == SP_OR_ADDRESS_REGS)) |
8ecf154e | 567 | { |
911517ac | 568 | if (TARGET_AM33) |
569 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 570 | return DATA_REGS; |
571 | } | |
29a404f9 | 572 | |
573 | /* We can't directly load sp + const_int into a data register; | |
574 | we must use an address register as an intermediate. */ | |
48cb86e3 | 575 | if (class != SP_REGS |
576 | && class != ADDRESS_REGS | |
577 | && class != SP_OR_ADDRESS_REGS | |
911517ac | 578 | && class != SP_OR_EXTENDED_REGS |
579 | && class != ADDRESS_OR_EXTENDED_REGS | |
580 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
29a404f9 | 581 | && (in == stack_pointer_rtx |
582 | || (GET_CODE (in) == PLUS | |
48cb86e3 | 583 | && (XEXP (in, 0) == stack_pointer_rtx |
584 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
29a404f9 | 585 | return ADDRESS_REGS; |
586 | ||
19de5de1 | 587 | if (GET_CODE (in) == PLUS |
588 | && (XEXP (in, 0) == stack_pointer_rtx | |
589 | || XEXP (in, 1) == stack_pointer_rtx)) | |
8ecf154e | 590 | { |
911517ac | 591 | if (TARGET_AM33) |
592 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 593 | return DATA_REGS; |
594 | } | |
19de5de1 | 595 | |
48cb86e3 | 596 | /* Otherwise assume no secondary reloads are needed. */ |
597 | return NO_REGS; | |
598 | } | |
599 | ||
600 | int | |
601 | initial_offset (from, to) | |
602 | int from, to; | |
603 | { | |
f1899bff | 604 | /* The difference between the argument pointer and the frame pointer |
605 | is the size of the callee register save area. */ | |
48cb86e3 | 606 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
29a404f9 | 607 | { |
48cb86e3 | 608 | if (regs_ever_live[2] || regs_ever_live[3] |
609 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 610 | || regs_ever_live[14] || regs_ever_live[15] |
611 | || regs_ever_live[16] || regs_ever_live[17] | |
48cb86e3 | 612 | || frame_pointer_needed) |
8ecf154e | 613 | return REG_SAVE_BYTES; |
48cb86e3 | 614 | else |
bb4959a8 | 615 | return 0; |
29a404f9 | 616 | } |
617 | ||
f1899bff | 618 | /* The difference between the argument pointer and the stack pointer is |
619 | the sum of the size of this function's frame, the callee register save | |
620 | area, and the fixed stack space needed for function calls (if any). */ | |
48cb86e3 | 621 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
622 | { | |
623 | if (regs_ever_live[2] || regs_ever_live[3] | |
624 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 625 | || regs_ever_live[14] || regs_ever_live[15] |
626 | || regs_ever_live[16] || regs_ever_live[17] | |
48cb86e3 | 627 | || frame_pointer_needed) |
8ecf154e | 628 | return (get_frame_size () + REG_SAVE_BYTES |
36ed4406 | 629 | + (current_function_outgoing_args_size |
630 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 631 | else |
36ed4406 | 632 | return (get_frame_size () |
633 | + (current_function_outgoing_args_size | |
634 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 635 | } |
29a404f9 | 636 | |
f1899bff | 637 | /* The difference between the frame pointer and stack pointer is the sum |
638 | of the size of this function's frame and the fixed stack space needed | |
639 | for function calls (if any). */ | |
48cb86e3 | 640 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
36ed4406 | 641 | return (get_frame_size () |
642 | + (current_function_outgoing_args_size | |
643 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 644 | |
645 | abort (); | |
29a404f9 | 646 | } |
bb4959a8 | 647 | |
648 | /* Flush the argument registers to the stack for a stdarg function; | |
649 | return the new argument pointer. */ | |
650 | rtx | |
55f54832 | 651 | mn10300_builtin_saveregs () |
bb4959a8 | 652 | { |
ed554036 | 653 | rtx offset, mem; |
bb4959a8 | 654 | tree fntype = TREE_TYPE (current_function_decl); |
655 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
656 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
657 | != void_type_node))) | |
658 | ? UNITS_PER_WORD : 0); | |
ed554036 | 659 | int set = get_varargs_alias_set (); |
bb4959a8 | 660 | |
661 | if (argadj) | |
662 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
663 | else | |
664 | offset = current_function_arg_offset_rtx; | |
665 | ||
ed554036 | 666 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
667 | MEM_ALIAS_SET (mem) = set; | |
668 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); | |
669 | ||
670 | mem = gen_rtx_MEM (SImode, | |
671 | plus_constant (current_function_internal_arg_pointer, 4)); | |
672 | MEM_ALIAS_SET (mem) = set; | |
673 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); | |
674 | ||
bb4959a8 | 675 | return copy_to_reg (expand_binop (Pmode, add_optab, |
676 | current_function_internal_arg_pointer, | |
677 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
678 | } | |
679 | ||
ed554036 | 680 | void |
681 | mn10300_va_start (stdarg_p, valist, nextarg) | |
682 | int stdarg_p; | |
683 | tree valist; | |
684 | rtx nextarg; | |
685 | { | |
686 | if (stdarg_p) | |
687 | nextarg = expand_builtin_saveregs (); | |
688 | ||
689 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
690 | } | |
691 | ||
692 | rtx | |
693 | mn10300_va_arg (valist, type) | |
694 | tree valist, type; | |
695 | { | |
696 | HOST_WIDE_INT align, rsize; | |
697 | tree t, ptr, pptr; | |
698 | ||
699 | /* Compute the rounded size of the type. */ | |
700 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
701 | rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); | |
702 | ||
703 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
704 | build_int_2 ((rsize > 8 ? 4 : rsize), 0)); | |
705 | TREE_SIDE_EFFECTS (t) = 1; | |
706 | ||
707 | ptr = build_pointer_type (type); | |
708 | ||
709 | /* "Large" types are passed by reference. */ | |
710 | if (rsize > 8) | |
711 | { | |
712 | pptr = build_pointer_type (ptr); | |
713 | t = build1 (NOP_EXPR, pptr, t); | |
714 | TREE_SIDE_EFFECTS (t) = 1; | |
715 | ||
716 | t = build1 (INDIRECT_REF, ptr, t); | |
717 | TREE_SIDE_EFFECTS (t) = 1; | |
718 | } | |
719 | else | |
720 | { | |
721 | t = build1 (NOP_EXPR, ptr, t); | |
722 | TREE_SIDE_EFFECTS (t) = 1; | |
723 | } | |
724 | ||
725 | /* Calculate! */ | |
726 | return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); | |
727 | } | |
728 | ||
bb4959a8 | 729 | /* Return an RTX to represent where a value with mode MODE will be returned |
730 | from a function. If the result is 0, the argument is pushed. */ | |
731 | ||
732 | rtx | |
733 | function_arg (cum, mode, type, named) | |
734 | CUMULATIVE_ARGS *cum; | |
735 | enum machine_mode mode; | |
736 | tree type; | |
59086782 | 737 | int named ATTRIBUTE_UNUSED; |
bb4959a8 | 738 | { |
739 | rtx result = 0; | |
740 | int size, align; | |
741 | ||
742 | /* We only support using 2 data registers as argument registers. */ | |
743 | int nregs = 2; | |
744 | ||
745 | /* Figure out the size of the object to be passed. */ | |
746 | if (mode == BLKmode) | |
747 | size = int_size_in_bytes (type); | |
748 | else | |
749 | size = GET_MODE_SIZE (mode); | |
750 | ||
751 | /* Figure out the alignment of the object to be passed. */ | |
752 | align = size; | |
753 | ||
754 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
755 | ||
756 | /* Don't pass this arg via a register if all the argument registers | |
757 | are used up. */ | |
758 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
759 | return 0; | |
760 | ||
761 | /* Don't pass this arg via a register if it would be split between | |
762 | registers and memory. */ | |
763 | if (type == NULL_TREE | |
764 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
765 | return 0; | |
766 | ||
767 | switch (cum->nbytes / UNITS_PER_WORD) | |
768 | { | |
769 | case 0: | |
7014838c | 770 | result = gen_rtx_REG (mode, 0); |
bb4959a8 | 771 | break; |
772 | case 1: | |
7014838c | 773 | result = gen_rtx_REG (mode, 1); |
bb4959a8 | 774 | break; |
775 | default: | |
776 | result = 0; | |
777 | } | |
778 | ||
779 | return result; | |
780 | } | |
781 | ||
782 | /* Return the number of registers to use for an argument passed partially | |
783 | in registers and partially in memory. */ | |
784 | ||
785 | int | |
786 | function_arg_partial_nregs (cum, mode, type, named) | |
787 | CUMULATIVE_ARGS *cum; | |
788 | enum machine_mode mode; | |
789 | tree type; | |
59086782 | 790 | int named ATTRIBUTE_UNUSED; |
bb4959a8 | 791 | { |
792 | int size, align; | |
793 | ||
794 | /* We only support using 2 data registers as argument registers. */ | |
795 | int nregs = 2; | |
796 | ||
797 | /* Figure out the size of the object to be passed. */ | |
798 | if (mode == BLKmode) | |
799 | size = int_size_in_bytes (type); | |
800 | else | |
801 | size = GET_MODE_SIZE (mode); | |
802 | ||
803 | /* Figure out the alignment of the object to be passed. */ | |
804 | align = size; | |
805 | ||
806 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
807 | ||
808 | /* Don't pass this arg via a register if all the argument registers | |
809 | are used up. */ | |
810 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
811 | return 0; | |
812 | ||
813 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
814 | return 0; | |
815 | ||
816 | /* Don't pass this arg via a register if it would be split between | |
817 | registers and memory. */ | |
818 | if (type == NULL_TREE | |
819 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
820 | return 0; | |
821 | ||
822 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
823 | } | |
824 | ||
825 | /* Output a tst insn. */ | |
826 | char * | |
827 | output_tst (operand, insn) | |
828 | rtx operand, insn; | |
829 | { | |
bb4959a8 | 830 | rtx temp; |
831 | int past_call = 0; | |
832 | ||
833 | /* We can save a byte if we can find a register which has the value | |
834 | zero in it. */ | |
835 | temp = PREV_INSN (insn); | |
6e90c6cd | 836 | while (optimize && temp) |
bb4959a8 | 837 | { |
838 | rtx set; | |
839 | ||
840 | /* We allow the search to go through call insns. We record | |
841 | the fact that we've past a CALL_INSN and reject matches which | |
842 | use call clobbered registers. */ | |
843 | if (GET_CODE (temp) == CODE_LABEL | |
844 | || GET_CODE (temp) == JUMP_INSN | |
845 | || GET_CODE (temp) == BARRIER) | |
846 | break; | |
847 | ||
848 | if (GET_CODE (temp) == CALL_INSN) | |
849 | past_call = 1; | |
850 | ||
851 | if (GET_CODE (temp) == NOTE) | |
852 | { | |
853 | temp = PREV_INSN (temp); | |
854 | continue; | |
855 | } | |
856 | ||
857 | /* It must be an insn, see if it is a simple set. */ | |
858 | set = single_set (temp); | |
859 | if (!set) | |
860 | { | |
861 | temp = PREV_INSN (temp); | |
862 | continue; | |
863 | } | |
864 | ||
865 | /* Are we setting a data register to zero (this does not win for | |
866 | address registers)? | |
867 | ||
868 | If it's a call clobbered register, have we past a call? | |
869 | ||
870 | Make sure the register we find isn't the same as ourself; | |
8ecf154e | 871 | the mn10300 can't encode that. |
872 | ||
873 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
874 | so the code to detect calls here isn't doing anything useful. */ | |
bb4959a8 | 875 | if (REG_P (SET_DEST (set)) |
876 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
877 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
6e90c6cd | 878 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
879 | == REGNO_REG_CLASS (REGNO (operand))) | |
911517ac | 880 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
881 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
882 | && (!past_call | |
883 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
884 | { | |
885 | rtx xoperands[2]; | |
886 | xoperands[0] = operand; | |
887 | xoperands[1] = SET_DEST (set); | |
888 | ||
889 | output_asm_insn ("cmp %1,%0", xoperands); | |
890 | return ""; | |
891 | } | |
892 | ||
893 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
894 | && REG_P (SET_DEST (set)) | |
895 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
896 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
897 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
898 | != REGNO_REG_CLASS (REGNO (operand))) | |
899 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
bb4959a8 | 900 | && REGNO (SET_DEST (set)) != REGNO (operand) |
901 | && (!past_call | |
902 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
903 | { | |
904 | rtx xoperands[2]; | |
905 | xoperands[0] = operand; | |
906 | xoperands[1] = SET_DEST (set); | |
907 | ||
908 | output_asm_insn ("cmp %1,%0", xoperands); | |
909 | return ""; | |
910 | } | |
911 | temp = PREV_INSN (temp); | |
912 | } | |
913 | return "cmp 0,%0"; | |
914 | } | |
36ed4406 | 915 | |
916 | int | |
917 | impossible_plus_operand (op, mode) | |
918 | rtx op; | |
59086782 | 919 | enum machine_mode mode ATTRIBUTE_UNUSED; |
36ed4406 | 920 | { |
36ed4406 | 921 | if (GET_CODE (op) != PLUS) |
922 | return 0; | |
923 | ||
19de5de1 | 924 | if (XEXP (op, 0) == stack_pointer_rtx |
925 | || XEXP (op, 1) == stack_pointer_rtx) | |
36ed4406 | 926 | return 1; |
927 | ||
36ed4406 | 928 | return 0; |
929 | } | |
c4cd8f6a | 930 | |
9d3b5b5e | 931 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
932 | for the btst insn which may examine memory or a register (the memory | |
933 | variant only allows an unsigned 8 bit integer). */ | |
934 | int | |
935 | const_8bit_operand (op, mode) | |
936 | register rtx op; | |
59086782 | 937 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9d3b5b5e | 938 | { |
939 | return (GET_CODE (op) == CONST_INT | |
940 | && INTVAL (op) >= 0 | |
941 | && INTVAL (op) < 256); | |
942 | } | |
943 | ||
944 | /* Similarly, but when using a zero_extract pattern for a btst where | |
945 | the source operand might end up in memory. */ | |
946 | int | |
947 | mask_ok_for_mem_btst (len, bit) | |
948 | int len; | |
949 | int bit; | |
950 | { | |
951 | int mask = 0; | |
952 | ||
953 | while (len > 0) | |
954 | { | |
955 | mask |= (1 << bit); | |
956 | bit++; | |
957 | len--; | |
958 | } | |
959 | ||
960 | /* MASK must bit into an 8bit value. */ | |
961 | return (((mask & 0xff) == mask) | |
962 | || ((mask & 0xff00) == mask) | |
963 | || ((mask & 0xff0000) == mask) | |
964 | || ((mask & 0xff000000) == mask)); | |
965 | } | |
966 | ||
c4cd8f6a | 967 | /* Return 1 if X contains a symbolic expression. We know these |
968 | expressions will have one of a few well defined forms, so | |
969 | we need only check those forms. */ | |
970 | int | |
971 | symbolic_operand (op, mode) | |
972 | register rtx op; | |
59086782 | 973 | enum machine_mode mode ATTRIBUTE_UNUSED; |
c4cd8f6a | 974 | { |
975 | switch (GET_CODE (op)) | |
976 | { | |
977 | case SYMBOL_REF: | |
978 | case LABEL_REF: | |
979 | return 1; | |
980 | case CONST: | |
981 | op = XEXP (op, 0); | |
982 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
983 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
984 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
985 | default: | |
986 | return 0; | |
987 | } | |
988 | } | |
989 | ||
990 | /* Try machine dependent ways of modifying an illegitimate address | |
991 | to be legitimate. If we find one, return the new valid address. | |
992 | This macro is used in only one place: `memory_address' in explow.c. | |
993 | ||
994 | OLDX is the address as it was before break_out_memory_refs was called. | |
995 | In some cases it is useful to look at this to decide what needs to be done. | |
996 | ||
997 | MODE and WIN are passed so that this macro can use | |
998 | GO_IF_LEGITIMATE_ADDRESS. | |
999 | ||
1000 | Normally it is always safe for this macro to do nothing. It exists to | |
1001 | recognize opportunities to optimize the output. | |
1002 | ||
1003 | But on a few ports with segmented architectures and indexed addressing | |
1004 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1005 | rtx | |
1006 | legitimize_address (x, oldx, mode) | |
1007 | rtx x; | |
59086782 | 1008 | rtx oldx ATTRIBUTE_UNUSED; |
1009 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
c4cd8f6a | 1010 | { |
1011 | /* Uh-oh. We might have an address for x[n-100000]. This needs | |
1012 | special handling to avoid creating an indexed memory address | |
1013 | with x-100000 as the base. */ | |
1014 | if (GET_CODE (x) == PLUS | |
1015 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1016 | { | |
1017 | /* Ugly. We modify things here so that the address offset specified | |
1018 | by the index expression is computed first, then added to x to form | |
1019 | the entire address. */ | |
1020 | ||
59086782 | 1021 | rtx regx1, regy1, regy2, y; |
c4cd8f6a | 1022 | |
1023 | /* Strip off any CONST. */ | |
1024 | y = XEXP (x, 1); | |
1025 | if (GET_CODE (y) == CONST) | |
1026 | y = XEXP (y, 0); | |
1027 | ||
c927a8ab | 1028 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1029 | { | |
1030 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1031 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1032 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1033 | regx1 = force_reg (Pmode, | |
1034 | gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); | |
7014838c | 1035 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
c927a8ab | 1036 | } |
c4cd8f6a | 1037 | } |
11b4605c | 1038 | return x; |
c4cd8f6a | 1039 | } |
e2aead91 | 1040 | |
1041 | int | |
1042 | mn10300_address_cost (x, unsig) | |
1043 | rtx x; | |
1044 | int *unsig; | |
1045 | { | |
1046 | int _s = 0; | |
1047 | if (unsig == 0) | |
1048 | unsig = &_s; | |
1049 | ||
1050 | switch (GET_CODE (x)) | |
1051 | { | |
1052 | case REG: | |
1053 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1054 | { | |
1055 | case SP_REGS: | |
1056 | *unsig = 1; | |
1057 | return 0; | |
1058 | ||
1059 | case ADDRESS_REGS: | |
1060 | return 1; | |
1061 | ||
1062 | case DATA_REGS: | |
1063 | case EXTENDED_REGS: | |
1064 | return 3; | |
1065 | ||
1066 | case NO_REGS: | |
1067 | return 5; | |
1068 | ||
1069 | default: | |
1070 | abort (); | |
1071 | } | |
1072 | ||
1073 | case PLUS: | |
1074 | case MINUS: | |
cbe23f2f | 1075 | case ASHIFT: |
1076 | case AND: | |
e2aead91 | 1077 | case IOR: |
1078 | return (mn10300_address_cost (XEXP (x, 0), unsig) | |
1079 | + mn10300_address_cost (XEXP (x, 1), unsig)); | |
1080 | ||
1081 | case EXPR_LIST: | |
1082 | case SUBREG: | |
1083 | case MEM: | |
1084 | return ADDRESS_COST (XEXP (x, 0)); | |
1085 | ||
1086 | case ZERO_EXTEND: | |
1087 | *unsig = 1; | |
1088 | return mn10300_address_cost (XEXP (x, 0), unsig); | |
1089 | ||
1090 | case CONST_INT: | |
1091 | if (INTVAL (x) == 0) | |
1092 | return 0; | |
1093 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1094 | return 1; | |
1095 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1096 | return 3; | |
1097 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1098 | return 5; | |
1099 | return 7; | |
1100 | ||
1101 | case CONST: | |
1102 | case SYMBOL_REF: | |
cbe23f2f | 1103 | case LABEL_REF: |
e2aead91 | 1104 | return 8; |
1105 | ||
1106 | case ADDRESSOF: | |
1107 | switch (GET_CODE (XEXP (x, 0))) | |
1108 | { | |
1109 | case MEM: | |
1110 | return ADDRESS_COST (XEXP (x, 0)); | |
1111 | ||
1112 | case REG: | |
1113 | return 1; | |
1114 | ||
1115 | default: | |
1116 | abort (); | |
1117 | } | |
1118 | ||
1119 | default: | |
1120 | abort (); | |
1121 | ||
1122 | } | |
1123 | } |