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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
92547f12 AO |
2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
11bb1f11 | 23 | #include "config.h" |
c5c76735 | 24 | #include "system.h" |
11bb1f11 | 25 | #include "rtl.h" |
bf6bb899 | 26 | #include "tree.h" |
11bb1f11 JL |
27 | #include "regs.h" |
28 | #include "hard-reg-set.h" | |
29 | #include "real.h" | |
30 | #include "insn-config.h" | |
31 | #include "conditions.h" | |
11bb1f11 JL |
32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
e78d8e51 | 37 | #include "optabs.h" |
bf6bb899 | 38 | #include "function.h" |
11bb1f11 | 39 | #include "obstack.h" |
69bc71fa KG |
40 | #include "toplev.h" |
41 | #include "tm_p.h" | |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
11bb1f11 | 44 | |
4d1a91c2 JL |
45 | /* The size of the callee register save area. Right now we save everything |
46 | on entry since it costs us nothing in code size. It does cost us from a | |
47 | speed standpoint, so we want to optimize this sooner or later. */ | |
980d0e81 JL |
48 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
49 | + 4 * regs_ever_live[3] \ | |
705ac34f JL |
50 | + 4 * regs_ever_live[6] \ |
51 | + 4 * regs_ever_live[7] \ | |
52 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
53 | || regs_ever_live[16] || regs_ever_live[17])) | |
672a6f42 NB |
54 | \f |
55 | /* Initialize the GCC target structure. */ | |
301d03af RS |
56 | #undef TARGET_ASM_ALIGNED_HI_OP |
57 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
4d1a91c2 | 58 | |
f6897b10 | 59 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 60 | \f |
11bb1f11 JL |
61 | void |
62 | asm_file_start (file) | |
63 | FILE *file; | |
64 | { | |
65 | fprintf (file, "#\tGCC For the Matsushita MN10300\n"); | |
66 | if (optimize) | |
67 | fprintf (file, "# -O%d\n", optimize); | |
68 | else | |
69 | fprintf (file, "\n\n"); | |
705ac34f JL |
70 | |
71 | if (TARGET_AM33) | |
72 | fprintf (file, "\t.am33\n"); | |
11bb1f11 JL |
73 | output_file_directive (file, main_input_filename); |
74 | } | |
75 | \f | |
76 | ||
11bb1f11 JL |
77 | /* Print operand X using operand code CODE to assembly language output file |
78 | FILE. */ | |
79 | ||
80 | void | |
81 | print_operand (file, x, code) | |
82 | FILE *file; | |
83 | rtx x; | |
84 | int code; | |
85 | { | |
86 | switch (code) | |
87 | { | |
88 | case 'b': | |
89 | case 'B': | |
90 | /* These are normal and reversed branches. */ | |
91 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
92 | { | |
93 | case NE: | |
94 | fprintf (file, "ne"); | |
95 | break; | |
96 | case EQ: | |
97 | fprintf (file, "eq"); | |
98 | break; | |
99 | case GE: | |
100 | fprintf (file, "ge"); | |
101 | break; | |
102 | case GT: | |
103 | fprintf (file, "gt"); | |
104 | break; | |
105 | case LE: | |
106 | fprintf (file, "le"); | |
107 | break; | |
108 | case LT: | |
109 | fprintf (file, "lt"); | |
110 | break; | |
111 | case GEU: | |
112 | fprintf (file, "cc"); | |
113 | break; | |
114 | case GTU: | |
115 | fprintf (file, "hi"); | |
116 | break; | |
117 | case LEU: | |
118 | fprintf (file, "ls"); | |
119 | break; | |
120 | case LTU: | |
121 | fprintf (file, "cs"); | |
122 | break; | |
123 | default: | |
124 | abort (); | |
125 | } | |
126 | break; | |
127 | case 'C': | |
128 | /* This is used for the operand to a call instruction; | |
129 | if it's a REG, enclose it in parens, else output | |
130 | the operand normally. */ | |
131 | if (GET_CODE (x) == REG) | |
132 | { | |
133 | fputc ('(', file); | |
134 | print_operand (file, x, 0); | |
135 | fputc (')', file); | |
136 | } | |
137 | else | |
138 | print_operand (file, x, 0); | |
139 | break; | |
140 | ||
38c37a0e JL |
141 | /* These are the least significant word in a 64bit value. */ |
142 | case 'L': | |
143 | switch (GET_CODE (x)) | |
144 | { | |
145 | case MEM: | |
146 | fputc ('(', file); | |
147 | output_address (XEXP (x, 0)); | |
148 | fputc (')', file); | |
149 | break; | |
150 | ||
151 | case REG: | |
152 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
153 | break; | |
154 | ||
155 | case SUBREG: | |
ddef6bc7 | 156 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
157 | break; |
158 | ||
159 | case CONST_DOUBLE: | |
160 | { | |
161 | long val[2]; | |
162 | REAL_VALUE_TYPE rv; | |
163 | ||
164 | switch (GET_MODE (x)) | |
165 | { | |
166 | case DFmode: | |
167 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
168 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 169 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
170 | break;; |
171 | case SFmode: | |
172 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
173 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 174 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
175 | break;; |
176 | case VOIDmode: | |
177 | case DImode: | |
178 | print_operand_address (file, | |
179 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
180 | break; | |
69bc71fa KG |
181 | default: |
182 | break; | |
38c37a0e JL |
183 | } |
184 | break; | |
185 | } | |
186 | ||
187 | case CONST_INT: | |
212bc5fa AO |
188 | { |
189 | rtx low, high; | |
190 | split_double (x, &low, &high); | |
191 | fprintf (file, "%ld", (long)INTVAL (low)); | |
192 | break; | |
193 | } | |
38c37a0e JL |
194 | |
195 | default: | |
196 | abort (); | |
197 | } | |
198 | break; | |
199 | ||
200 | /* Similarly, but for the most significant word. */ | |
201 | case 'H': | |
202 | switch (GET_CODE (x)) | |
203 | { | |
204 | case MEM: | |
205 | fputc ('(', file); | |
b72f00af | 206 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
207 | output_address (XEXP (x, 0)); |
208 | fputc (')', file); | |
209 | break; | |
210 | ||
211 | case REG: | |
212 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
213 | break; | |
214 | ||
215 | case SUBREG: | |
ddef6bc7 | 216 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
217 | break; |
218 | ||
219 | case CONST_DOUBLE: | |
220 | { | |
221 | long val[2]; | |
222 | REAL_VALUE_TYPE rv; | |
223 | ||
224 | switch (GET_MODE (x)) | |
225 | { | |
226 | case DFmode: | |
227 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
228 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 229 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
230 | break;; |
231 | case SFmode: | |
232 | abort (); | |
233 | case VOIDmode: | |
234 | case DImode: | |
235 | print_operand_address (file, | |
236 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
237 | break; | |
69bc71fa KG |
238 | default: |
239 | break; | |
38c37a0e JL |
240 | } |
241 | break; | |
242 | } | |
243 | ||
244 | case CONST_INT: | |
212bc5fa AO |
245 | { |
246 | rtx low, high; | |
247 | split_double (x, &low, &high); | |
248 | fprintf (file, "%ld", (long)INTVAL (high)); | |
249 | break; | |
250 | } | |
251 | ||
38c37a0e JL |
252 | default: |
253 | abort (); | |
254 | } | |
255 | break; | |
256 | ||
257 | case 'A': | |
258 | fputc ('(', file); | |
259 | if (GET_CODE (XEXP (x, 0)) == REG) | |
c5c76735 | 260 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0))); |
38c37a0e JL |
261 | else |
262 | output_address (XEXP (x, 0)); | |
263 | fputc (')', file); | |
264 | break; | |
265 | ||
6fafc523 JL |
266 | case 'N': |
267 | output_address (GEN_INT ((~INTVAL (x)) & 0xff)); | |
268 | break; | |
269 | ||
576e5acc JL |
270 | /* For shift counts. The hardware ignores the upper bits of |
271 | any immediate, but the assembler will flag an out of range | |
272 | shift count as an error. So we mask off the high bits | |
273 | of the immediate here. */ | |
274 | case 'S': | |
275 | if (GET_CODE (x) == CONST_INT) | |
276 | { | |
277 | fprintf (file, "%d", INTVAL (x) & 0x1f); | |
278 | break; | |
279 | } | |
280 | /* FALL THROUGH */ | |
281 | ||
11bb1f11 JL |
282 | default: |
283 | switch (GET_CODE (x)) | |
284 | { | |
285 | case MEM: | |
286 | fputc ('(', file); | |
287 | output_address (XEXP (x, 0)); | |
288 | fputc (')', file); | |
289 | break; | |
290 | ||
38c37a0e JL |
291 | case PLUS: |
292 | output_address (x); | |
293 | break; | |
294 | ||
11bb1f11 JL |
295 | case REG: |
296 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
297 | break; | |
298 | ||
299 | case SUBREG: | |
ddef6bc7 | 300 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
301 | break; |
302 | ||
38c37a0e JL |
303 | /* This will only be single precision.... */ |
304 | case CONST_DOUBLE: | |
305 | { | |
306 | unsigned long val; | |
307 | REAL_VALUE_TYPE rv; | |
308 | ||
309 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
310 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 311 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
312 | break; |
313 | } | |
314 | ||
11bb1f11 JL |
315 | case CONST_INT: |
316 | case SYMBOL_REF: | |
317 | case CONST: | |
318 | case LABEL_REF: | |
319 | case CODE_LABEL: | |
320 | print_operand_address (file, x); | |
321 | break; | |
322 | default: | |
323 | abort (); | |
324 | } | |
325 | break; | |
326 | } | |
327 | } | |
328 | ||
329 | /* Output assembly language output for the address ADDR to FILE. */ | |
330 | ||
331 | void | |
332 | print_operand_address (file, addr) | |
333 | FILE *file; | |
334 | rtx addr; | |
335 | { | |
336 | switch (GET_CODE (addr)) | |
337 | { | |
705ac34f JL |
338 | case POST_INC: |
339 | print_operand_address (file, XEXP (addr, 0)); | |
340 | fputc ('+', file); | |
341 | break; | |
11bb1f11 | 342 | case REG: |
79e4122c | 343 | print_operand (file, addr, 0); |
11bb1f11 JL |
344 | break; |
345 | case PLUS: | |
346 | { | |
347 | rtx base, index; | |
348 | if (REG_P (XEXP (addr, 0)) | |
349 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
350 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
351 | else if (REG_P (XEXP (addr, 1)) | |
352 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
353 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
354 | else | |
355 | abort (); | |
356 | print_operand (file, index, 0); | |
357 | fputc (',', file); | |
358 | print_operand (file, base, 0);; | |
359 | break; | |
360 | } | |
361 | case SYMBOL_REF: | |
362 | output_addr_const (file, addr); | |
363 | break; | |
364 | default: | |
365 | output_addr_const (file, addr); | |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
f6cd7c62 RS |
370 | /* Print a set of registers in the format required by "movm" and "ret". |
371 | Register K is saved if bit K of MASK is set. The data and address | |
372 | registers can be stored individually, but the extended registers cannot. | |
373 | We assume that the mask alread takes that into account. For instance, | |
374 | bits 14 to 17 must have the same value. */ | |
375 | ||
376 | void | |
377 | mn10300_print_reg_list (file, mask) | |
378 | FILE *file; | |
379 | int mask; | |
380 | { | |
381 | int need_comma; | |
382 | int i; | |
383 | ||
384 | need_comma = 0; | |
385 | fputc ('[', file); | |
386 | ||
387 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
388 | if ((mask & (1 << i)) != 0) | |
389 | { | |
390 | if (need_comma) | |
391 | fputc (',', file); | |
392 | fputs (reg_names [i], file); | |
393 | need_comma = 1; | |
394 | } | |
395 | ||
396 | if ((mask & 0x3c000) != 0) | |
397 | { | |
398 | if ((mask & 0x3c000) != 0x3c000) | |
399 | abort(); | |
400 | if (need_comma) | |
401 | fputc (',', file); | |
402 | fputs ("exreg1", file); | |
403 | need_comma = 1; | |
404 | } | |
405 | ||
406 | fputc (']', file); | |
407 | } | |
408 | ||
38c37a0e JL |
409 | int |
410 | can_use_return_insn () | |
411 | { | |
460f4b9d JL |
412 | /* size includes the fixed stack space needed for function calls. */ |
413 | int size = get_frame_size () + current_function_outgoing_args_size; | |
414 | ||
415 | /* And space for the return pointer. */ | |
416 | size += current_function_outgoing_args_size ? 4 : 0; | |
38c37a0e JL |
417 | |
418 | return (reload_completed | |
419 | && size == 0 | |
420 | && !regs_ever_live[2] | |
421 | && !regs_ever_live[3] | |
422 | && !regs_ever_live[6] | |
423 | && !regs_ever_live[7] | |
705ac34f JL |
424 | && !regs_ever_live[14] |
425 | && !regs_ever_live[15] | |
426 | && !regs_ever_live[16] | |
427 | && !regs_ever_live[17] | |
38c37a0e JL |
428 | && !frame_pointer_needed); |
429 | } | |
430 | ||
f6cd7c62 RS |
431 | /* Returns the set of live, callee-saved registers as a bitmask. The |
432 | callee-saved extended registers cannot be stored individually, so | |
433 | all of them will be included in the mask if any one of them is used. */ | |
434 | ||
435 | int | |
436 | mn10300_get_live_callee_saved_regs () | |
437 | { | |
438 | int mask; | |
439 | int i; | |
440 | ||
441 | mask = 0; | |
442 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
443 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
444 | mask |= (1 << i); | |
445 | if ((mask & 0x3c000) != 0) | |
446 | mask |= 0x3c000; | |
447 | ||
448 | return mask; | |
449 | } | |
450 | ||
451 | /* Generate an instruction that pushes several registers onto the stack. | |
452 | Register K will be saved if bit K in MASK is set. The function does | |
453 | nothing if MASK is zero. | |
454 | ||
455 | To be compatible with the "movm" instruction, the lowest-numbered | |
456 | register must be stored in the lowest slot. If MASK is the set | |
457 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
458 | instruction will have the form: | |
459 | ||
460 | (parallel | |
461 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
462 | (set (mem:SI (plus:SI (reg:SI 9) | |
463 | (const_int -1*4))) | |
464 | (reg:SI RN)) | |
465 | ... | |
466 | (set (mem:SI (plus:SI (reg:SI 9) | |
467 | (const_int -N*4))) | |
468 | (reg:SI R1))) */ | |
469 | ||
470 | void | |
471 | mn10300_gen_multiple_store (mask) | |
472 | int mask; | |
473 | { | |
474 | if (mask != 0) | |
475 | { | |
476 | int i; | |
477 | int count; | |
478 | rtx par; | |
479 | int pari; | |
480 | ||
481 | /* Count how many registers need to be saved. */ | |
482 | count = 0; | |
483 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
484 | if ((mask & (1 << i)) != 0) | |
485 | count += 1; | |
486 | ||
487 | /* We need one PARALLEL element to update the stack pointer and | |
488 | an additional element for each register that is stored. */ | |
489 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); | |
490 | ||
491 | /* Create the instruction that updates the stack pointer. */ | |
492 | XVECEXP (par, 0, 0) | |
493 | = gen_rtx_SET (SImode, | |
494 | stack_pointer_rtx, | |
495 | gen_rtx_PLUS (SImode, | |
496 | stack_pointer_rtx, | |
497 | GEN_INT (-count * 4))); | |
498 | ||
499 | /* Create each store. */ | |
500 | pari = 1; | |
501 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
502 | if ((mask & (1 << i)) != 0) | |
503 | { | |
504 | rtx address = gen_rtx_PLUS (SImode, | |
505 | stack_pointer_rtx, | |
506 | GEN_INT (-pari * 4)); | |
507 | XVECEXP(par, 0, pari) | |
508 | = gen_rtx_SET (VOIDmode, | |
509 | gen_rtx_MEM (SImode, address), | |
510 | gen_rtx_REG (SImode, i)); | |
511 | pari += 1; | |
512 | } | |
513 | ||
514 | par = emit_insn (par); | |
515 | RTX_FRAME_RELATED_P (par) = 1; | |
516 | } | |
517 | } | |
518 | ||
11bb1f11 JL |
519 | void |
520 | expand_prologue () | |
521 | { | |
036182e7 | 522 | HOST_WIDE_INT size; |
3dbc43d1 | 523 | |
3dbc43d1 | 524 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
525 | size = get_frame_size () + current_function_outgoing_args_size; |
526 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 527 | |
22ef4e9b JL |
528 | /* If this is an old-style varargs function, then its arguments |
529 | need to be flushed back to the stack. */ | |
530 | if (current_function_varargs) | |
531 | { | |
c5c76735 JL |
532 | emit_move_insn (gen_rtx_MEM (SImode, |
533 | plus_constant (stack_pointer_rtx, 4)), | |
534 | gen_rtx_REG (SImode, 0)); | |
535 | emit_move_insn (gen_rtx_MEM (SImode, | |
536 | plus_constant (stack_pointer_rtx, 8)), | |
537 | gen_rtx_REG (SImode, 1)); | |
22ef4e9b JL |
538 | } |
539 | ||
f6cd7c62 RS |
540 | /* If we use any of the callee-saved registers, save them now. */ |
541 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); | |
777fbf09 JL |
542 | |
543 | /* Now put the frame pointer into the frame pointer register. */ | |
11bb1f11 | 544 | if (frame_pointer_needed) |
6e86170d | 545 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
11bb1f11 | 546 | |
777fbf09 | 547 | /* Allocate stack for this frame. */ |
11bb1f11 JL |
548 | if (size) |
549 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
550 | stack_pointer_rtx, | |
551 | GEN_INT (-size))); | |
552 | } | |
553 | ||
554 | void | |
555 | expand_epilogue () | |
556 | { | |
036182e7 | 557 | HOST_WIDE_INT size; |
3dbc43d1 | 558 | |
3dbc43d1 | 559 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
560 | size = get_frame_size () + current_function_outgoing_args_size; |
561 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 562 | |
5d29a95f JL |
563 | /* Maybe cut back the stack, except for the register save area. |
564 | ||
565 | If the frame pointer exists, then use the frame pointer to | |
566 | cut back the stack. | |
567 | ||
568 | If the stack size + register save area is more than 255 bytes, | |
569 | then the stack must be cut back here since the size + register | |
570 | save size is too big for a ret/retf instruction. | |
571 | ||
572 | Else leave it alone, it will be cut back as part of the | |
573 | ret/retf instruction, or there wasn't any stack to begin with. | |
574 | ||
575 | Under no circumstanes should the register save area be | |
576 | deallocated here, that would leave a window where an interrupt | |
577 | could occur and trash the register save area. */ | |
11bb1f11 JL |
578 | if (frame_pointer_needed) |
579 | { | |
11bb1f11 | 580 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
581 | size = 0; |
582 | } | |
ed6089d6 | 583 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
584 | { |
585 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
586 | stack_pointer_rtx, | |
587 | GEN_INT (size))); | |
588 | size = 0; | |
11bb1f11 | 589 | } |
11bb1f11 | 590 | |
ed6089d6 AO |
591 | /* Adjust the stack and restore callee-saved registers, if any. */ |
592 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
777fbf09 | 593 | || regs_ever_live[6] || regs_ever_live[7] |
705ac34f JL |
594 | || regs_ever_live[14] || regs_ever_live[15] |
595 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 596 | || frame_pointer_needed) |
ed6089d6 AO |
597 | emit_jump_insn (gen_return_internal_regs |
598 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 599 | else |
ed6089d6 | 600 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
601 | } |
602 | ||
603 | /* Update the condition code from the insn. */ | |
604 | ||
605 | void | |
606 | notice_update_cc (body, insn) | |
607 | rtx body; | |
608 | rtx insn; | |
609 | { | |
11bb1f11 JL |
610 | switch (get_attr_cc (insn)) |
611 | { | |
612 | case CC_NONE: | |
613 | /* Insn does not affect CC at all. */ | |
614 | break; | |
615 | ||
616 | case CC_NONE_0HIT: | |
617 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
618 | if (cc_status.value1 != 0 | |
1ccbefce | 619 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
620 | cc_status.value1 = 0; |
621 | break; | |
622 | ||
d116300b | 623 | case CC_SET_ZN: |
1ccbefce | 624 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 625 | V,C are unusable. */ |
11bb1f11 | 626 | CC_STATUS_INIT; |
d116300b | 627 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 628 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
629 | break; |
630 | ||
d116300b | 631 | case CC_SET_ZNV: |
1ccbefce | 632 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 633 | C is unusable. */ |
82c6faa8 | 634 | CC_STATUS_INIT; |
d116300b | 635 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 636 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
637 | break; |
638 | ||
11bb1f11 JL |
639 | case CC_COMPARE: |
640 | /* The insn is a compare instruction. */ | |
641 | CC_STATUS_INIT; | |
642 | cc_status.value1 = SET_SRC (body); | |
643 | break; | |
644 | ||
3b800f71 JL |
645 | case CC_INVERT: |
646 | /* The insn is a compare instruction. */ | |
647 | CC_STATUS_INIT; | |
648 | cc_status.value1 = SET_SRC (body); | |
649 | cc_status.flags |= CC_INVERTED; | |
650 | break; | |
651 | ||
11bb1f11 JL |
652 | case CC_CLOBBER: |
653 | /* Insn doesn't leave CC in a usable state. */ | |
654 | CC_STATUS_INIT; | |
655 | break; | |
82c6faa8 JL |
656 | |
657 | default: | |
658 | abort (); | |
11bb1f11 | 659 | } |
11bb1f11 JL |
660 | } |
661 | ||
f6cd7c62 RS |
662 | /* Recognise the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
663 | This function is for MATCH_PARALLEL and so assumes OP is known to be | |
664 | parallel. If OP is a multiple store, return a mask indicating which | |
665 | registers it saves. Return 0 otherwise. */ | |
666 | ||
667 | int | |
668 | store_multiple_operation (op, mode) | |
669 | rtx op; | |
670 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
671 | { | |
672 | int count; | |
673 | int mask; | |
674 | int i; | |
675 | unsigned int last; | |
676 | rtx elt; | |
677 | ||
678 | count = XVECLEN (op, 0); | |
679 | if (count < 2) | |
680 | return 0; | |
681 | ||
682 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
683 | elt = XVECEXP (op, 0, 0); | |
684 | if (GET_CODE (elt) != SET | |
685 | || GET_CODE (SET_DEST (elt)) != REG | |
686 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
687 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
688 | return 0; | |
689 | ||
690 | /* Check that A is the stack pointer and B is the expected stack size. | |
691 | For OP to match, each subsequent instruction should push a word onto | |
692 | the stack. We therefore expect the first instruction to create | |
693 | COUNT-1 stack slots. */ | |
694 | elt = SET_SRC (elt); | |
695 | if (GET_CODE (XEXP (elt, 0)) != REG | |
696 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
697 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
698 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
699 | return 0; | |
700 | ||
701 | /* Now go through the rest of the vector elements. They must be | |
702 | ordered so that the first instruction stores the highest-numbered | |
703 | register to the highest stack slot and that subsequent instructions | |
704 | store a lower-numbered register to the slot below. | |
705 | ||
706 | LAST keeps track of the smallest-numbered register stored so far. | |
707 | MASK is the set of stored registers. */ | |
708 | last = FIRST_PSEUDO_REGISTER; | |
709 | mask = 0; | |
710 | for (i = 1; i < count; i++) | |
711 | { | |
712 | /* Check that element i is a (set (mem M) R) and that R is valid. */ | |
713 | elt = XVECEXP (op, 0, i); | |
714 | if (GET_CODE (elt) != SET | |
715 | || GET_CODE (SET_DEST (elt)) != MEM | |
716 | || GET_CODE (SET_SRC (elt)) != REG | |
717 | || REGNO (SET_SRC (elt)) >= last) | |
718 | return 0; | |
719 | ||
720 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
721 | case if the rest of the instruction has a flaw. */ | |
722 | last = REGNO (SET_SRC (elt)); | |
723 | mask |= (1 << last); | |
724 | ||
725 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
726 | elt = XEXP (SET_DEST (elt), 0); | |
727 | if (GET_CODE (elt) != PLUS | |
728 | || GET_CODE (XEXP (elt, 0)) != REG | |
729 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
730 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
731 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
732 | return 0; | |
733 | } | |
734 | ||
735 | /* All or none of the callee-saved extended registers must be in the set. */ | |
736 | if ((mask & 0x3c000) != 0 | |
737 | && (mask & 0x3c000) != 0x3c000) | |
738 | return 0; | |
739 | ||
740 | return mask; | |
741 | } | |
742 | ||
11bb1f11 JL |
743 | /* Return true if OP is a valid call operand. */ |
744 | ||
745 | int | |
746 | call_address_operand (op, mode) | |
747 | rtx op; | |
69bc71fa | 748 | enum machine_mode mode ATTRIBUTE_UNUSED; |
11bb1f11 JL |
749 | { |
750 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); | |
751 | } | |
752 | ||
753 | /* What (if any) secondary registers are needed to move IN with mode | |
8493cfcb | 754 | MODE into a register in register class CLASS. |
11bb1f11 JL |
755 | |
756 | We might be able to simplify this. */ | |
757 | enum reg_class | |
758 | secondary_reload_class (class, mode, in) | |
759 | enum reg_class class; | |
760 | enum machine_mode mode; | |
761 | rtx in; | |
762 | { | |
11bb1f11 JL |
763 | /* Memory loads less than a full word wide can't have an |
764 | address or stack pointer destination. They must use | |
765 | a data register as an intermediate register. */ | |
15c09738 AH |
766 | if ((GET_CODE (in) == MEM |
767 | || (GET_CODE (in) == REG | |
768 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
769 | || (GET_CODE (in) == SUBREG | |
770 | && GET_CODE (SUBREG_REG (in)) == REG | |
771 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
11bb1f11 | 772 | && (mode == QImode || mode == HImode) |
15c09738 | 773 | && (class == ADDRESS_REGS || class == SP_REGS |
842a0788 | 774 | || class == SP_OR_ADDRESS_REGS)) |
4d1a91c2 | 775 | { |
705ac34f JL |
776 | if (TARGET_AM33) |
777 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
778 | return DATA_REGS; |
779 | } | |
11bb1f11 JL |
780 | |
781 | /* We can't directly load sp + const_int into a data register; | |
782 | we must use an address register as an intermediate. */ | |
777fbf09 JL |
783 | if (class != SP_REGS |
784 | && class != ADDRESS_REGS | |
785 | && class != SP_OR_ADDRESS_REGS | |
705ac34f JL |
786 | && class != SP_OR_EXTENDED_REGS |
787 | && class != ADDRESS_OR_EXTENDED_REGS | |
788 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
789 | && (in == stack_pointer_rtx |
790 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
791 | && (XEXP (in, 0) == stack_pointer_rtx |
792 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
793 | return ADDRESS_REGS; |
794 | ||
4c742813 JL |
795 | if (GET_CODE (in) == PLUS |
796 | && (XEXP (in, 0) == stack_pointer_rtx | |
797 | || XEXP (in, 1) == stack_pointer_rtx)) | |
4d1a91c2 | 798 | { |
705ac34f JL |
799 | if (TARGET_AM33) |
800 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
801 | return DATA_REGS; |
802 | } | |
4c742813 | 803 | |
777fbf09 JL |
804 | /* Otherwise assume no secondary reloads are needed. */ |
805 | return NO_REGS; | |
806 | } | |
807 | ||
808 | int | |
809 | initial_offset (from, to) | |
810 | int from, to; | |
811 | { | |
3dbc43d1 JL |
812 | /* The difference between the argument pointer and the frame pointer |
813 | is the size of the callee register save area. */ | |
777fbf09 | 814 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 815 | { |
777fbf09 JL |
816 | if (regs_ever_live[2] || regs_ever_live[3] |
817 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
818 | || regs_ever_live[14] || regs_ever_live[15] |
819 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 820 | || frame_pointer_needed) |
4d1a91c2 | 821 | return REG_SAVE_BYTES; |
777fbf09 | 822 | else |
22ef4e9b | 823 | return 0; |
11bb1f11 JL |
824 | } |
825 | ||
3dbc43d1 JL |
826 | /* The difference between the argument pointer and the stack pointer is |
827 | the sum of the size of this function's frame, the callee register save | |
828 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
829 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
830 | { | |
831 | if (regs_ever_live[2] || regs_ever_live[3] | |
832 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
833 | || regs_ever_live[14] || regs_ever_live[15] |
834 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 835 | || frame_pointer_needed) |
4d1a91c2 | 836 | return (get_frame_size () + REG_SAVE_BYTES |
460f4b9d JL |
837 | + (current_function_outgoing_args_size |
838 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 839 | else |
460f4b9d JL |
840 | return (get_frame_size () |
841 | + (current_function_outgoing_args_size | |
842 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 843 | } |
11bb1f11 | 844 | |
3dbc43d1 JL |
845 | /* The difference between the frame pointer and stack pointer is the sum |
846 | of the size of this function's frame and the fixed stack space needed | |
847 | for function calls (if any). */ | |
777fbf09 | 848 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d JL |
849 | return (get_frame_size () |
850 | + (current_function_outgoing_args_size | |
851 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 JL |
852 | |
853 | abort (); | |
11bb1f11 | 854 | } |
22ef4e9b JL |
855 | |
856 | /* Flush the argument registers to the stack for a stdarg function; | |
857 | return the new argument pointer. */ | |
858 | rtx | |
648d2ffc | 859 | mn10300_builtin_saveregs () |
22ef4e9b | 860 | { |
fc2acc87 | 861 | rtx offset, mem; |
22ef4e9b JL |
862 | tree fntype = TREE_TYPE (current_function_decl); |
863 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
864 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
865 | != void_type_node))) | |
866 | ? UNITS_PER_WORD : 0); | |
fc2acc87 | 867 | int set = get_varargs_alias_set (); |
22ef4e9b JL |
868 | |
869 | if (argadj) | |
870 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
871 | else | |
872 | offset = current_function_arg_offset_rtx; | |
873 | ||
fc2acc87 | 874 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ba4828e0 | 875 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
876 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
877 | ||
878 | mem = gen_rtx_MEM (SImode, | |
879 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ba4828e0 | 880 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
881 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
882 | ||
22ef4e9b JL |
883 | return copy_to_reg (expand_binop (Pmode, add_optab, |
884 | current_function_internal_arg_pointer, | |
885 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
886 | } | |
887 | ||
fc2acc87 RH |
888 | void |
889 | mn10300_va_start (stdarg_p, valist, nextarg) | |
890 | int stdarg_p; | |
891 | tree valist; | |
892 | rtx nextarg; | |
893 | { | |
894 | if (stdarg_p) | |
895 | nextarg = expand_builtin_saveregs (); | |
896 | ||
897 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
898 | } | |
899 | ||
900 | rtx | |
901 | mn10300_va_arg (valist, type) | |
902 | tree valist, type; | |
903 | { | |
904 | HOST_WIDE_INT align, rsize; | |
905 | tree t, ptr, pptr; | |
906 | ||
907 | /* Compute the rounded size of the type. */ | |
908 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
909 | rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); | |
910 | ||
911 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
912 | build_int_2 ((rsize > 8 ? 4 : rsize), 0)); | |
913 | TREE_SIDE_EFFECTS (t) = 1; | |
914 | ||
915 | ptr = build_pointer_type (type); | |
916 | ||
917 | /* "Large" types are passed by reference. */ | |
918 | if (rsize > 8) | |
919 | { | |
920 | pptr = build_pointer_type (ptr); | |
921 | t = build1 (NOP_EXPR, pptr, t); | |
922 | TREE_SIDE_EFFECTS (t) = 1; | |
923 | ||
924 | t = build1 (INDIRECT_REF, ptr, t); | |
925 | TREE_SIDE_EFFECTS (t) = 1; | |
926 | } | |
927 | else | |
928 | { | |
929 | t = build1 (NOP_EXPR, ptr, t); | |
930 | TREE_SIDE_EFFECTS (t) = 1; | |
931 | } | |
932 | ||
933 | /* Calculate! */ | |
934 | return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); | |
935 | } | |
936 | ||
22ef4e9b JL |
937 | /* Return an RTX to represent where a value with mode MODE will be returned |
938 | from a function. If the result is 0, the argument is pushed. */ | |
939 | ||
940 | rtx | |
941 | function_arg (cum, mode, type, named) | |
942 | CUMULATIVE_ARGS *cum; | |
943 | enum machine_mode mode; | |
944 | tree type; | |
69bc71fa | 945 | int named ATTRIBUTE_UNUSED; |
22ef4e9b JL |
946 | { |
947 | rtx result = 0; | |
948 | int size, align; | |
949 | ||
950 | /* We only support using 2 data registers as argument registers. */ | |
951 | int nregs = 2; | |
952 | ||
953 | /* Figure out the size of the object to be passed. */ | |
954 | if (mode == BLKmode) | |
955 | size = int_size_in_bytes (type); | |
956 | else | |
957 | size = GET_MODE_SIZE (mode); | |
958 | ||
959 | /* Figure out the alignment of the object to be passed. */ | |
960 | align = size; | |
961 | ||
962 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
963 | ||
964 | /* Don't pass this arg via a register if all the argument registers | |
965 | are used up. */ | |
966 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
967 | return 0; | |
968 | ||
969 | /* Don't pass this arg via a register if it would be split between | |
970 | registers and memory. */ | |
971 | if (type == NULL_TREE | |
972 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
973 | return 0; | |
974 | ||
975 | switch (cum->nbytes / UNITS_PER_WORD) | |
976 | { | |
977 | case 0: | |
c5c76735 | 978 | result = gen_rtx_REG (mode, 0); |
22ef4e9b JL |
979 | break; |
980 | case 1: | |
c5c76735 | 981 | result = gen_rtx_REG (mode, 1); |
22ef4e9b JL |
982 | break; |
983 | default: | |
984 | result = 0; | |
985 | } | |
986 | ||
987 | return result; | |
988 | } | |
989 | ||
990 | /* Return the number of registers to use for an argument passed partially | |
991 | in registers and partially in memory. */ | |
992 | ||
993 | int | |
994 | function_arg_partial_nregs (cum, mode, type, named) | |
995 | CUMULATIVE_ARGS *cum; | |
996 | enum machine_mode mode; | |
997 | tree type; | |
69bc71fa | 998 | int named ATTRIBUTE_UNUSED; |
22ef4e9b JL |
999 | { |
1000 | int size, align; | |
1001 | ||
1002 | /* We only support using 2 data registers as argument registers. */ | |
1003 | int nregs = 2; | |
1004 | ||
1005 | /* Figure out the size of the object to be passed. */ | |
1006 | if (mode == BLKmode) | |
1007 | size = int_size_in_bytes (type); | |
1008 | else | |
1009 | size = GET_MODE_SIZE (mode); | |
1010 | ||
1011 | /* Figure out the alignment of the object to be passed. */ | |
1012 | align = size; | |
1013 | ||
1014 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1015 | ||
1016 | /* Don't pass this arg via a register if all the argument registers | |
1017 | are used up. */ | |
1018 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1019 | return 0; | |
1020 | ||
1021 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1022 | return 0; | |
1023 | ||
1024 | /* Don't pass this arg via a register if it would be split between | |
1025 | registers and memory. */ | |
1026 | if (type == NULL_TREE | |
1027 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1028 | return 0; | |
1029 | ||
1030 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
1031 | } | |
1032 | ||
1033 | /* Output a tst insn. */ | |
1943c2c1 | 1034 | const char * |
22ef4e9b JL |
1035 | output_tst (operand, insn) |
1036 | rtx operand, insn; | |
1037 | { | |
22ef4e9b JL |
1038 | rtx temp; |
1039 | int past_call = 0; | |
1040 | ||
1041 | /* We can save a byte if we can find a register which has the value | |
1042 | zero in it. */ | |
1043 | temp = PREV_INSN (insn); | |
74452ac3 | 1044 | while (optimize && temp) |
22ef4e9b JL |
1045 | { |
1046 | rtx set; | |
1047 | ||
1048 | /* We allow the search to go through call insns. We record | |
1049 | the fact that we've past a CALL_INSN and reject matches which | |
1050 | use call clobbered registers. */ | |
1051 | if (GET_CODE (temp) == CODE_LABEL | |
1052 | || GET_CODE (temp) == JUMP_INSN | |
1053 | || GET_CODE (temp) == BARRIER) | |
1054 | break; | |
1055 | ||
1056 | if (GET_CODE (temp) == CALL_INSN) | |
1057 | past_call = 1; | |
1058 | ||
1059 | if (GET_CODE (temp) == NOTE) | |
1060 | { | |
1061 | temp = PREV_INSN (temp); | |
1062 | continue; | |
1063 | } | |
1064 | ||
1065 | /* It must be an insn, see if it is a simple set. */ | |
1066 | set = single_set (temp); | |
1067 | if (!set) | |
1068 | { | |
1069 | temp = PREV_INSN (temp); | |
1070 | continue; | |
1071 | } | |
1072 | ||
1073 | /* Are we setting a data register to zero (this does not win for | |
1074 | address registers)? | |
1075 | ||
1076 | If it's a call clobbered register, have we past a call? | |
1077 | ||
1078 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1079 | the mn10300 can't encode that. |
1080 | ||
1081 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1082 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1083 | if (REG_P (SET_DEST (set)) |
1084 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1085 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1086 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1087 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1088 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1089 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
1090 | && (!past_call | |
1091 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1092 | { | |
1093 | rtx xoperands[2]; | |
1094 | xoperands[0] = operand; | |
1095 | xoperands[1] = SET_DEST (set); | |
1096 | ||
1097 | output_asm_insn ("cmp %1,%0", xoperands); | |
1098 | return ""; | |
1099 | } | |
1100 | ||
1101 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1102 | && REG_P (SET_DEST (set)) | |
1103 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1104 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1105 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1106 | != REGNO_REG_CLASS (REGNO (operand))) | |
1107 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b JL |
1108 | && REGNO (SET_DEST (set)) != REGNO (operand) |
1109 | && (!past_call | |
1110 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1111 | { | |
1112 | rtx xoperands[2]; | |
1113 | xoperands[0] = operand; | |
1114 | xoperands[1] = SET_DEST (set); | |
1115 | ||
1116 | output_asm_insn ("cmp %1,%0", xoperands); | |
1117 | return ""; | |
1118 | } | |
1119 | temp = PREV_INSN (temp); | |
1120 | } | |
1121 | return "cmp 0,%0"; | |
1122 | } | |
460f4b9d JL |
1123 | |
1124 | int | |
1125 | impossible_plus_operand (op, mode) | |
1126 | rtx op; | |
69bc71fa | 1127 | enum machine_mode mode ATTRIBUTE_UNUSED; |
460f4b9d | 1128 | { |
460f4b9d JL |
1129 | if (GET_CODE (op) != PLUS) |
1130 | return 0; | |
1131 | ||
4c742813 JL |
1132 | if (XEXP (op, 0) == stack_pointer_rtx |
1133 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
1134 | return 1; |
1135 | ||
460f4b9d JL |
1136 | return 0; |
1137 | } | |
e9ad4573 | 1138 | |
f8912297 JL |
1139 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
1140 | for the btst insn which may examine memory or a register (the memory | |
1141 | variant only allows an unsigned 8 bit integer). */ | |
1142 | int | |
1143 | const_8bit_operand (op, mode) | |
1144 | register rtx op; | |
69bc71fa | 1145 | enum machine_mode mode ATTRIBUTE_UNUSED; |
f8912297 JL |
1146 | { |
1147 | return (GET_CODE (op) == CONST_INT | |
1148 | && INTVAL (op) >= 0 | |
1149 | && INTVAL (op) < 256); | |
1150 | } | |
1151 | ||
1152 | /* Similarly, but when using a zero_extract pattern for a btst where | |
1153 | the source operand might end up in memory. */ | |
1154 | int | |
1155 | mask_ok_for_mem_btst (len, bit) | |
1156 | int len; | |
1157 | int bit; | |
1158 | { | |
1159 | int mask = 0; | |
1160 | ||
1161 | while (len > 0) | |
1162 | { | |
1163 | mask |= (1 << bit); | |
1164 | bit++; | |
1165 | len--; | |
1166 | } | |
1167 | ||
1168 | /* MASK must bit into an 8bit value. */ | |
1169 | return (((mask & 0xff) == mask) | |
1170 | || ((mask & 0xff00) == mask) | |
1171 | || ((mask & 0xff0000) == mask) | |
1172 | || ((mask & 0xff000000) == mask)); | |
1173 | } | |
1174 | ||
e9ad4573 JL |
1175 | /* Return 1 if X contains a symbolic expression. We know these |
1176 | expressions will have one of a few well defined forms, so | |
1177 | we need only check those forms. */ | |
1178 | int | |
1179 | symbolic_operand (op, mode) | |
1180 | register rtx op; | |
69bc71fa | 1181 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e9ad4573 JL |
1182 | { |
1183 | switch (GET_CODE (op)) | |
1184 | { | |
1185 | case SYMBOL_REF: | |
1186 | case LABEL_REF: | |
1187 | return 1; | |
1188 | case CONST: | |
1189 | op = XEXP (op, 0); | |
1190 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1191 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1192 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1193 | default: | |
1194 | return 0; | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | /* Try machine dependent ways of modifying an illegitimate address | |
1199 | to be legitimate. If we find one, return the new valid address. | |
1200 | This macro is used in only one place: `memory_address' in explow.c. | |
1201 | ||
1202 | OLDX is the address as it was before break_out_memory_refs was called. | |
1203 | In some cases it is useful to look at this to decide what needs to be done. | |
1204 | ||
1205 | MODE and WIN are passed so that this macro can use | |
1206 | GO_IF_LEGITIMATE_ADDRESS. | |
1207 | ||
1208 | Normally it is always safe for this macro to do nothing. It exists to | |
1209 | recognize opportunities to optimize the output. | |
1210 | ||
1211 | But on a few ports with segmented architectures and indexed addressing | |
1212 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1213 | rtx | |
1214 | legitimize_address (x, oldx, mode) | |
1215 | rtx x; | |
69bc71fa KG |
1216 | rtx oldx ATTRIBUTE_UNUSED; |
1217 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
e9ad4573 JL |
1218 | { |
1219 | /* Uh-oh. We might have an address for x[n-100000]. This needs | |
1220 | special handling to avoid creating an indexed memory address | |
1221 | with x-100000 as the base. */ | |
1222 | if (GET_CODE (x) == PLUS | |
1223 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1224 | { | |
1225 | /* Ugly. We modify things here so that the address offset specified | |
1226 | by the index expression is computed first, then added to x to form | |
1227 | the entire address. */ | |
1228 | ||
69bc71fa | 1229 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1230 | |
1231 | /* Strip off any CONST. */ | |
1232 | y = XEXP (x, 1); | |
1233 | if (GET_CODE (y) == CONST) | |
1234 | y = XEXP (y, 0); | |
1235 | ||
bf4219f0 JL |
1236 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1237 | { | |
1238 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1239 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1240 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1241 | regx1 = force_reg (Pmode, | |
1242 | gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); | |
c5c76735 | 1243 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1244 | } |
e9ad4573 | 1245 | } |
371036e0 | 1246 | return x; |
e9ad4573 | 1247 | } |
460ad325 AO |
1248 | |
1249 | int | |
1250 | mn10300_address_cost (x, unsig) | |
1251 | rtx x; | |
1252 | int *unsig; | |
1253 | { | |
1254 | int _s = 0; | |
1255 | if (unsig == 0) | |
1256 | unsig = &_s; | |
1257 | ||
1258 | switch (GET_CODE (x)) | |
1259 | { | |
1260 | case REG: | |
1261 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1262 | { | |
1263 | case SP_REGS: | |
1264 | *unsig = 1; | |
1265 | return 0; | |
1266 | ||
1267 | case ADDRESS_REGS: | |
1268 | return 1; | |
1269 | ||
1270 | case DATA_REGS: | |
1271 | case EXTENDED_REGS: | |
1272 | return 3; | |
1273 | ||
1274 | case NO_REGS: | |
1275 | return 5; | |
1276 | ||
1277 | default: | |
1278 | abort (); | |
1279 | } | |
1280 | ||
1281 | case PLUS: | |
1282 | case MINUS: | |
d82704fb AO |
1283 | case ASHIFT: |
1284 | case AND: | |
460ad325 AO |
1285 | case IOR: |
1286 | return (mn10300_address_cost (XEXP (x, 0), unsig) | |
1287 | + mn10300_address_cost (XEXP (x, 1), unsig)); | |
1288 | ||
1289 | case EXPR_LIST: | |
1290 | case SUBREG: | |
1291 | case MEM: | |
1292 | return ADDRESS_COST (XEXP (x, 0)); | |
1293 | ||
1294 | case ZERO_EXTEND: | |
1295 | *unsig = 1; | |
1296 | return mn10300_address_cost (XEXP (x, 0), unsig); | |
1297 | ||
1298 | case CONST_INT: | |
1299 | if (INTVAL (x) == 0) | |
1300 | return 0; | |
1301 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1302 | return 1; | |
1303 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1304 | return 3; | |
1305 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1306 | return 5; | |
1307 | return 7; | |
1308 | ||
1309 | case CONST: | |
1310 | case SYMBOL_REF: | |
d82704fb | 1311 | case LABEL_REF: |
460ad325 AO |
1312 | return 8; |
1313 | ||
1314 | case ADDRESSOF: | |
1315 | switch (GET_CODE (XEXP (x, 0))) | |
1316 | { | |
1317 | case MEM: | |
1318 | return ADDRESS_COST (XEXP (x, 0)); | |
1319 | ||
1320 | case REG: | |
1321 | return 1; | |
1322 | ||
1323 | default: | |
1324 | abort (); | |
1325 | } | |
1326 | ||
1327 | default: | |
1328 | abort (); | |
1329 | ||
1330 | } | |
1331 | } |